#17 add switch to write module hierarchy before elaboration

open
nobody
3
2009-04-14
2007-08-19
thiede
No

Dealing with large quantities of files of an unknown design, it's sometimes very helpful to be able to see the module hierarchy.

Please add a switch to iverilog to write the module hierarchy with instance names as early as possible. Especially prior to any further elaboration, which might error out.

To avoid huge files in case of mixed rtl/gatelevel netlists, don't write instances of modules which are marked with `celldefine.

Other options might be to write just the instance name in the module instead of the expanded instance name.

To get nice formatting, it's beneficial to first find the max module name string length and use that as stringlength during (f)printf.

top
modulename0 fullinstancename0
modulename1 fullinstancename1
mod1 mod

Discussion

  • Cary R.

    Cary R. - 2007-12-13

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    This has been on my thought stack for a while and I'm not certain this can be done correctly before elaboration has (mostly) finished. The big gotcha is the generate statement. It must run before you know what you are going to get. I understand why we want this early, but I think to do it right it will need to be a back-end process.

    I also think as a minimum we will want the file name the module is defined in available. Here's a straw-man text based output:

    top (test.v)
    ckt_inst -> design (design.v)
    gate_inst1 -> and2 (gates/and2.v)
    gate_inst2 -> or2 (gates/or2.v)
    gate_ints3 -> dff (gates/dff.v)
    test_ckt -> test (common/test.v)

    It might also be nice to print some summary information (number of each type of primitive gate, etc.).

    In addition creating a file that something like Graphviz (http://www.graphviz.org/) could process would be huge and should not be that much more work. With this we would get a very nice graphical display of the circuit structure. To me this would be something very special that would be noticed!

     
  • Cary R.

    Cary R. - 2009-04-14

    After some more conversations this is expected to be a front-end tool that can deal with partial and possibly invalid input files. Using something like graphviz to display the output may still be desirable, but the file generation needs to happen shortly after parsing. Since this is not part of our main simulation focus I'm decreasing the priority. We will keep this in mind if we ever rework the front-end or if we find other tools that may address the issue.

     
  • Cary R.

    Cary R. - 2009-04-14
    • labels: --> Source Language Extensions
    • milestone: --> devel_(Next_Release)
    • priority: 5 --> 3
     
  • pgbackup

    pgbackup - 2009-10-24

    If interested, there is a neat script called v2html (http://www.burbleland.com/v2html/v2html.html) that converts a verilog design into html documentation and creates a window like file-explorer which can be used to see the hierarchy. It also allows for signal tracing through the hierarchy. I use this script in all my documentation. Perhaps it is something to look at.

     

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