Please browse the reported bugs/issues for Icarus Verilog at your pleasure. If you think you have found a bug of your own, first browse the existing bugs and feature requests to determine whether your bug has already been reported by someone else. It is far better to expound on an existing bug report then to create a new bug report for the same thing. If you find that your issue matches an existing report, then click on that issue page to get details. You have the option of adding comments to the bug report. Also, you will be able to monitor any existing bug report. If you have convinced yourself that your bug really is unique, then use the Submit link to start the bug submission.
The priority breakdown reflects the priority that the Icarus Verilog development team intends given the nature of the problem. This is how the Icarus Verilog team assigns priority:
3 - minor issues like invalid or missing warnings, spelling fixes, etc.
4 - functionality that is missing, but is not currently needed or can be worked around with code changes,
5 - The catch all for run-of-the-mill bugs, or unreviewed bugs,
6 - an invalid result without a warning that can be worked around; or use this priority for a program crash that is preventing one from using Icarus Verilog,
7 - An invalid result without a warning that cannot be worked around reasonably.
9 - Imminent nuclear death, meteor impact, or hysterical screaming boss.
The "Owner" field is used by the core Icarus Verilog developers to claim a bug report. Somebody may be working on unassigned reports, but when it is assigned then that individual is explicitly stating that they are (intend) to work on it. If you wish to contribute towards fixing a claimed bug report, please coordinate with the claimant.
|772||another possible sensitivity bug?||devel||open||2010-02-14||2010-03-11||5|
|740||Timing checks are not supported.||devel||open||2009-10-28||2009-10-28||5|
|733||VCD or $monitor() can contain changes from unchanged values||v0.9||open||2009-10-08||2010-01-02||4|
|698||$urandom with seed parameter treats seed as inout||devel||open||2009-06-19||2014-09-30||5|
|681||$monitor, $strobe, etc. can not use complex expressions||devel||open||2009-04-26||2013-02-08||5|
|677||C. assigns with zero delay can create zero width glitches||devel||open||2009-04-03||2009-04-07||6|
|630||Icarus Verilog accepts forward references too liberally||devel||open||2009-01-23||2012-12-10||4|
|626||VHDL Declaring logic in scope type||devel||open||2009-01-21||2009-01-21||4|
|605||Procedural continuous assign or force is only evaluated once||devel||open||2008-12-22||2014-02-21||5|
|582||VHDL functions cannot assign to non-local signals||devel||open||Nick Gasson||2008-11-30||2009-01-25||4|
|545||Inertial delays are not supported from VPI||devel||open||2008-10-27||2009-08-11||4|
|495||Unexpected race of modpath "if" expressions (pr1877743.v)||devel||open||2008-08-24||2009-10-06||6|
|493||Path delay expression without parenthesis not supported||devel||open||2008-08-15||2008-09-13||4|
|273||sorry: net delays not supported||devel||open||2007-07-21||2008-08-22||4|
|235||sorry: trireg nets not supported||devel||open||2007-04-21||2008-08-22||5|
|124||No support for configuring a design||devel||open||2006-12-14||2009-12-29||5|
|53||Synthesis fails for user defined functions||v0.8||open||2006-06-15||2009-01-27||4|