#626 VHDL Declaring logic in scope type

devel
open
nobody
4
2009-01-21
2009-01-21
thiede
No

performance bottleneck:
iverilog test.v takes 2 min total to create a.out
iverilog -pdebug=1 -tvhdl test.v spends 8 min in "Declaring logic in scope type"
No single module sticks out.

Discussion

  • thiede

    thiede - 2009-01-21

    low priority, "just" a performance issue

     
  • thiede

    thiede - 2009-01-21
    • priority: 5 --> 4
     

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