#235 sorry: trireg nets not supported

devel
open
nobody
5
2008-08-22
2007-04-21
thiede
No

verilog-20080418/bin/iverilog test.v
test.v:8: sorry: trireg nets not supported.

module test ( oen, I, C, p);

input oen;
input I;
output C;
inout p;

trireg p;
assign p = oen ? 1'bz : I;
assign C = p;

endmodule

Discussion

  • thiede

    thiede - 2007-04-21
     
  • Nobody/Anonymous

    Logged In: NO

    Trireg is a standard/basic verilog feature
    It's mandatory when using bi-directional signals.

    What it's needed to get it implemented?

     
  • Cary R.

    Cary R. - 2008-08-22
    • labels: 776822 --> Missing functionality
     
  • Cary R.

    Cary R. - 2009-05-27

    When we add this functionality do not forget to add trireg to the `default_nettype directive and to consider adding the `default_decay_time and `default_trireg_strength directives.

     

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