test.v:8: sorry: trireg nets not supported.
module test ( oen, I, C, p);
assign p = oen ? 1'bz : I;
assign C = p;
Logged In: NO
Trireg is a standard/basic verilog feature
It's mandatory when using bi-directional signals.
What it's needed to get it implemented?
When we add this functionality do not forget to add trireg to the `default_nettype directive and to consider adding the `default_decay_time and `default_trireg_strength directives.
Log in to post a comment.
Sign up for the SourceForge newsletter:
You seem to have CSS turned off.
Please don't fill out this field.