I was running a system that had two FPGAs from two different vendors. There turned out to be name conflicts, where the two vendors had the same names for different modules, and for one of the devices, the wrong modules were being picked up.
It would be of great value to be able to be able to add Verilog directives that would alter the search ordering. The directive should affect all modules (and their complete hierarchies) that follow the directive until another such directive is found. [I don't have a comment about what should happen if submodule contains another such directive. Should it be properly recursive?]
ModelSim uses the `uselib directive, although I don't think we should necessarily follow their pattern exactly. I suggest something like this:
I think what ModelSim does is first require that you have already specified the library when you compiled the code, and then the `uselib just raises the specified library to the head of the list of search paths so that it takes top priority.
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