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From: jorasse <jo...@us...> - 2014-06-10 06:59:52
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 96af776e04caa35cbd327233364a94d43c8037f5 (commit)
via df95271de11e6b5c659afdbf2b0926f671602115 (commit)
via bd63af8ec6b3de431c309f3f26e11b0079b5c1c3 (commit)
via ad80b9d880d14be4ffaf38702c0f171c2ca63c22 (commit)
via 9c8586e2486f36f714a41d2dd17febc6f33aff4a (commit)
from ac9ec6985a76c720426f6532e5f314c533b14ce1 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 96af776e04caa35cbd327233364a94d43c8037f5
Author: Philippe Reynes <tr...@ya...>
Date: Sun Jun 8 18:42:29 2014 +0200
[LINUX] 3.14: move to 3.14.6
commit df95271de11e6b5c659afdbf2b0926f671602115
Author: Philippe Reynes <tr...@ya...>
Date: Sun Jun 8 18:42:28 2014 +0200
[LINUX] 3.10: move to 3.10.42
commit bd63af8ec6b3de431c309f3f26e11b0079b5c1c3
Author: Philippe Reynes <tr...@ya...>
Date: Thu Jun 5 20:04:50 2014 +0200
[LINUX] 3.12: move to 3.12.21
commit ad80b9d880d14be4ffaf38702c0f171c2ca63c22
Author: Philippe Reynes <tr...@ya...>
Date: Mon Jun 2 22:00:22 2014 +0200
[LINUX] 3.10: move to 3.10.41
commit 9c8586e2486f36f714a41d2dd17febc6f33aff4a
Author: Philippe Reynes <tr...@ya...>
Date: Mon Jun 2 22:00:21 2014 +0200
[LINUX] 3.14: move to 3.14.5
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf27mainline_defconfig | 4 ++--
buildroot/configs/apf28mainline_defconfig | 4 ++--
buildroot/configs/apf51mainline_defconfig | 4 ++--
...x-3.10.40.config => apf27-linux-3.10.42.config} | 0
...x-3.12.20.config => apf27-linux-3.12.21.config} | 0
...nux-3.14.4.config => apf27-linux-3.14.6.config} | 0
...x-3.10.40.config => apf28-linux-3.10.42.config} | 0
...x-3.12.20.config => apf28-linux-3.12.21.config} | 0
...nux-3.14.4.config => apf28-linux-3.14.6.config} | 0
...x-3.10.40.config => apf51-linux-3.10.42.config} | 0
...x-3.12.20.config => apf51-linux-3.12.21.config} | 0
...nux-3.14.4.config => apf51-linux-3.14.6.config} | 0
patches/linux/{3.10.40 => 3.10.42} | 0
patches/linux/{3.12.20 => 3.12.21} | 0
patches/linux/{3.14.4 => 3.14.6} | 0
15 files changed, 6 insertions(+), 6 deletions(-)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.10.40.config => apf27-linux-3.10.42.config} (100%)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.12.20.config => apf27-linux-3.12.21.config} (100%)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.14.4.config => apf27-linux-3.14.6.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.10.40.config => apf28-linux-3.10.42.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.12.20.config => apf28-linux-3.12.21.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.14.4.config => apf28-linux-3.14.6.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.10.40.config => apf51-linux-3.10.42.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.12.20.config => apf51-linux-3.12.21.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.14.4.config => apf51-linux-3.14.6.config} (100%)
rename patches/linux/{3.10.40 => 3.10.42} (100%)
rename patches/linux/{3.12.20 => 3.12.21} (100%)
rename patches/linux/{3.14.4 => 3.14.6} (100%)
diff --git a/buildroot/configs/apf27mainline_defconfig b/buildroot/configs/apf27mainline_defconfig
index 10fe162..b893752 100644
--- a/buildroot/configs/apf27mainline_defconfig
+++ b/buildroot/configs/apf27mainline_defconfig
@@ -6,7 +6,7 @@ BR2_CCACHE=y
BR2_CCACHE_DIR="$(TOPDIR)/.$(BR2_BOARD_NAME)-buildroot-ccache"
BR2_STRIP_sstrip=y
BR2_KERNEL_HEADERS_VERSION=y
-BR2_DEFAULT_KERNEL_VERSION="3.14.4"
+BR2_DEFAULT_KERNEL_VERSION="3.14.6"
BR2_UCLIBC_CONFIG="target/device/armadeus/uClibc-$(BR2_UCLIBC_VERSION_STRING).config"
BR2_TOOLCHAIN_BUILDROOT_LARGEFILE=y
BR2_TOOLCHAIN_BUILDROOT_INET_IPV6=y
@@ -34,7 +34,7 @@ BR2_BOARD_NAME="apf27"
BR2_CPU_NAME="imx27"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.4"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.6"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/buildroot/configs/apf28mainline_defconfig b/buildroot/configs/apf28mainline_defconfig
index dd8c6db..da8bec8 100644
--- a/buildroot/configs/apf28mainline_defconfig
+++ b/buildroot/configs/apf28mainline_defconfig
@@ -6,7 +6,7 @@ BR2_CCACHE=y
BR2_CCACHE_DIR="$(TOPDIR)/.$(BR2_BOARD_NAME)-buildroot-ccache"
BR2_STRIP_sstrip=y
BR2_KERNEL_HEADERS_VERSION=y
-BR2_DEFAULT_KERNEL_VERSION="3.14.4"
+BR2_DEFAULT_KERNEL_VERSION="3.14.6"
BR2_UCLIBC_CONFIG="target/device/armadeus/uClibc-$(BR2_UCLIBC_VERSION_STRING).config"
BR2_TOOLCHAIN_BUILDROOT_LARGEFILE=y
BR2_TOOLCHAIN_BUILDROOT_INET_IPV6=y
@@ -35,7 +35,7 @@ BR2_CPU_NAME="imx28"
BR2_TARGET_ARMADEUS_SDRAM_SIZE="128"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.4"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.6"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/buildroot/configs/apf51mainline_defconfig b/buildroot/configs/apf51mainline_defconfig
index 977fd0e..ccf45de 100644
--- a/buildroot/configs/apf51mainline_defconfig
+++ b/buildroot/configs/apf51mainline_defconfig
@@ -7,7 +7,7 @@ BR2_CCACHE=y
BR2_CCACHE_DIR="$(TOPDIR)/.$(BR2_BOARD_NAME)-buildroot-ccache"
BR2_STRIP_sstrip=y
BR2_KERNEL_HEADERS_VERSION=y
-BR2_DEFAULT_KERNEL_VERSION="3.14.4"
+BR2_DEFAULT_KERNEL_VERSION="3.14.6"
BR2_UCLIBC_CONFIG="target/device/armadeus/uClibc-$(BR2_UCLIBC_VERSION_STRING).config"
BR2_TOOLCHAIN_BUILDROOT_LARGEFILE=y
BR2_TOOLCHAIN_BUILDROOT_INET_IPV6=y
@@ -97,7 +97,7 @@ BR2_TARGET_UBOOT_ENVIMAGE_SOURCE="$(ARMADEUS_PATH)/u-boot-env-2013.04.txt"
BR2_TARGET_UBOOT_ENVIMAGE_SIZE="0x20000"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.4"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.6"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.40.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.42.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.10.40.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.10.42.config
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.12.20.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.12.21.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.12.20.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.12.21.config
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.14.4.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.14.6.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.14.4.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.14.6.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.10.40.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.10.42.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.10.40.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.10.42.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.12.20.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.12.21.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.12.20.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.12.21.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.14.4.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.14.6.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.14.4.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.14.6.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.10.40.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.10.42.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.10.40.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.10.42.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.12.20.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.12.21.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.12.20.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.12.21.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.14.4.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.14.6.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.14.4.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.14.6.config
diff --git a/patches/linux/3.10.40 b/patches/linux/3.10.42
similarity index 100%
rename from patches/linux/3.10.40
rename to patches/linux/3.10.42
diff --git a/patches/linux/3.12.20 b/patches/linux/3.12.21
similarity index 100%
rename from patches/linux/3.12.20
rename to patches/linux/3.12.21
diff --git a/patches/linux/3.14.4 b/patches/linux/3.14.6
similarity index 100%
rename from patches/linux/3.14.4
rename to patches/linux/3.14.6
hooks/post-receive
--
armadeus
|
|
From: Sébastien S. <ss...@us...> - 2014-06-02 14:55:21
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via ac9ec6985a76c720426f6532e5f314c533b14ce1 (commit)
from 507ac454a6761f71bb4312facb1bfaae4f4098db (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit ac9ec6985a76c720426f6532e5f314c533b14ce1
Author: Sébastien Szymanski <ss...@us...>
Date: Mon Jun 2 16:55:11 2014 +0200
[LINUX] 3.15: move to 3.15-rc8.
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf6_defconfig | 2 +-
...3.15-rc7.config => apf27-linux-3.15-rc8.config} | 0
...3.15-rc7.config => apf28-linux-3.15-rc8.config} | 0
...3.15-rc7.config => apf51-linux-3.15-rc8.config} | 0
...-3.15-rc7.config => apf6-linux-3.15-rc8.config} | 0
patches/linux/{3.15-rc7 => 3.15-rc8} | 0
6 files changed, 1 insertions(+), 1 deletions(-)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.15-rc7.config => apf27-linux-3.15-rc8.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.15-rc7.config => apf28-linux-3.15-rc8.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.15-rc7.config => apf51-linux-3.15-rc8.config} (100%)
rename buildroot/target/device/armadeus/apf6/{apf6-linux-3.15-rc7.config => apf6-linux-3.15-rc8.config} (100%)
rename patches/linux/{3.15-rc7 => 3.15-rc8} (100%)
diff --git a/buildroot/configs/apf6_defconfig b/buildroot/configs/apf6_defconfig
index f8f8ac9..a1e3d67 100644
--- a/buildroot/configs/apf6_defconfig
+++ b/buildroot/configs/apf6_defconfig
@@ -22,7 +22,7 @@ BR2_TARGET_ARMADEUS_NR_SDRAM="2"
BR2_TARGET_ARMADEUS_SDRAM_SIZE="512"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.15-rc7"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.15-rc8"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc7.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc8.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc7.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc8.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc7.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc8.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc7.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc8.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc7.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc8.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc7.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc8.config
diff --git a/buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc7.config b/buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc8.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc7.config
rename to buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc8.config
diff --git a/patches/linux/3.15-rc7 b/patches/linux/3.15-rc8
similarity index 100%
rename from patches/linux/3.15-rc7
rename to patches/linux/3.15-rc8
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2014-05-29 21:58:12
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 507ac454a6761f71bb4312facb1bfaae4f4098db (commit)
from 3809a7fa8a86e698225ab0c2cd3bd065b647d233 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 507ac454a6761f71bb4312facb1bfaae4f4098db
Author: Eric Jarrige <eri...@ar...>
Date: Thu May 29 23:57:55 2014 +0200
[UBOOT] 2014.04: Fix tftp direct download to NAND flash
-----------------------------------------------------------------------
Summary of changes:
.../2014.04/350-nand_large_file_download.patch | 36 ++++++++++++++++---
1 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/patches/u-boot/2014.04/350-nand_large_file_download.patch b/patches/u-boot/2014.04/350-nand_large_file_download.patch
index c6ed8e2..25c80f1 100644
--- a/patches/u-boot/2014.04/350-nand_large_file_download.patch
+++ b/patches/u-boot/2014.04/350-nand_large_file_download.patch
@@ -100,18 +100,40 @@ index 59a8ebb..727e746 100644
/*
* TFTP operations.
*/
-@@ -156,12 +166,96 @@ mcast_cleanup(void)
+@@ -156,12 +166,120 @@ mcast_cleanup(void)
#endif /* CONFIG_MCAST_TFTP */
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_SYS_DIRECT_FLASH_TFTP)
++static size_t drop_ffs(const nand_info_t *nand, const u_char *buf,
++ const size_t *len)
++{
++ size_t l = *len;
++ ssize_t i;
++
++ for (i = l - 1; i >= 0; i--)
++ if (buf[i] != 0xFF)
++ break;
++
++ /* The resulting length must be aligned to the minimum flash I/O size */
++ l = i + 1;
++ l = (l + nand->writesize - 1) / nand->writesize;
++ l *= nand->writesize;
++
++ /*
++ * since the input length may be unaligned, prevent access past the end
++ * of the buffer
++ */
++ return min(l, *len);
++}
++
+static int tftp_nand_write(nand_info_t *meminfo, uchar *src, unsigned long *offset, size_t *length )
+{
+/* size_t written ;*/
+ int ret = 0;
+ loff_t offs;
+ int blockstart = -1;
-+
++ size_t truncated_write_size;
+ /* find first non bad block */
+ do {
+ blockstart = (*offset) & (~meminfo->erasesize+1);
@@ -132,14 +154,16 @@ index 59a8ebb..727e746 100644
+ }
+ } while ((ret!=0) && (*offset < meminfo->size) );
+
-+ if (*offset < meminfo->size)
-+ /* write out the page data */
-+ ret = nand_write(meminfo, *offset, length, src);
-+/* ret = meminfo->write(meminfo,
++ if (*offset < meminfo->size) {
++ /* write out the page data */
++ truncated_write_size = drop_ffs(meminfo, src, length);
++ ret = nand_write(meminfo, *offset, &truncated_write_size, src);
++/* ret = meminfo->write(meminfo,
+ *offset,
+ meminfo->oobblock,
+ &written,
+ src);*/
++ }
+ if (ret != 0) {
+ printf("writing NAND page at offset 0x%lx failed\n",
+ *offset);
hooks/post-receive
--
armadeus
|
|
From: Sébastien S. <ss...@us...> - 2014-05-26 08:09:35
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 3809a7fa8a86e698225ab0c2cd3bd065b647d233 (commit)
from 6b15a269fc0c2397290f28226adceb751c45e19d (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 3809a7fa8a86e698225ab0c2cd3bd065b647d233
Author: Sébastien Szymanski <ss...@us...>
Date: Mon May 26 10:11:01 2014 +0200
[LINUX] 3.15: move to 3.15-rc7
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf6_defconfig | 2 +-
...3.15-rc6.config => apf27-linux-3.15-rc7.config} | 0
.../apf28-linux-3.15-rc7.config} | 0
...3.15-rc6.config => apf51-linux-3.15-rc7.config} | 0
...-3.15-rc6.config => apf6-linux-3.15-rc7.config} | 0
patches/linux/{3.15-rc6 => 3.15-rc7} | 0
6 files changed, 1 insertions(+), 1 deletions(-)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.15-rc6.config => apf27-linux-3.15-rc7.config} (100%)
rename buildroot/target/device/armadeus/{apf27/apf28-linux-3.15-rc6.config => apf28/apf28-linux-3.15-rc7.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.15-rc6.config => apf51-linux-3.15-rc7.config} (100%)
rename buildroot/target/device/armadeus/apf6/{apf6-linux-3.15-rc6.config => apf6-linux-3.15-rc7.config} (100%)
rename patches/linux/{3.15-rc6 => 3.15-rc7} (100%)
diff --git a/buildroot/configs/apf6_defconfig b/buildroot/configs/apf6_defconfig
index abdda67..f8f8ac9 100644
--- a/buildroot/configs/apf6_defconfig
+++ b/buildroot/configs/apf6_defconfig
@@ -22,7 +22,7 @@ BR2_TARGET_ARMADEUS_NR_SDRAM="2"
BR2_TARGET_ARMADEUS_SDRAM_SIZE="512"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.15-rc6"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.15-rc7"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc6.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc7.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc6.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc7.config
diff --git a/buildroot/target/device/armadeus/apf27/apf28-linux-3.15-rc6.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc7.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf28-linux-3.15-rc6.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc7.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc6.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc7.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc6.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc7.config
diff --git a/buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc6.config b/buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc7.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc6.config
rename to buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc7.config
diff --git a/patches/linux/3.15-rc6 b/patches/linux/3.15-rc7
similarity index 100%
rename from patches/linux/3.15-rc6
rename to patches/linux/3.15-rc7
hooks/post-receive
--
armadeus
|
|
From: Sébastien S. <ss...@us...> - 2014-05-22 10:20:56
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 6b15a269fc0c2397290f28226adceb751c45e19d (commit)
from 3336bce3b64366e6477807074c0d5f162206fd46 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 6b15a269fc0c2397290f28226adceb751c45e19d
Author: Sébastien Szymanski <ss...@us...>
Date: Thu May 22 12:22:24 2014 +0200
[LINUX] 3.15: move to 3.15-rc6
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf6_defconfig | 2 +-
...3.15-rc5.config => apf27-linux-3.15-rc6.config} | 0
.../apf28-linux-3.15-rc6.config} | 0
...3.15-rc5.config => apf51-linux-3.15-rc6.config} | 0
...-3.15-rc5.config => apf6-linux-3.15-rc6.config} | 0
patches/linux/{3.15-rc5 => 3.15-rc6} | 0
6 files changed, 1 insertions(+), 1 deletions(-)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.15-rc5.config => apf27-linux-3.15-rc6.config} (100%)
rename buildroot/target/device/armadeus/{apf28/apf28-linux-3.15-rc5.config => apf27/apf28-linux-3.15-rc6.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.15-rc5.config => apf51-linux-3.15-rc6.config} (100%)
rename buildroot/target/device/armadeus/apf6/{apf6-linux-3.15-rc5.config => apf6-linux-3.15-rc6.config} (100%)
rename patches/linux/{3.15-rc5 => 3.15-rc6} (100%)
diff --git a/buildroot/configs/apf6_defconfig b/buildroot/configs/apf6_defconfig
index dce06cb..abdda67 100644
--- a/buildroot/configs/apf6_defconfig
+++ b/buildroot/configs/apf6_defconfig
@@ -22,7 +22,7 @@ BR2_TARGET_ARMADEUS_NR_SDRAM="2"
BR2_TARGET_ARMADEUS_SDRAM_SIZE="512"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.15-rc5"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.15-rc6"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc5.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc6.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc5.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc6.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc5.config b/buildroot/target/device/armadeus/apf27/apf28-linux-3.15-rc6.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc5.config
rename to buildroot/target/device/armadeus/apf27/apf28-linux-3.15-rc6.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc5.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc6.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc5.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc6.config
diff --git a/buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc5.config b/buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc6.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc5.config
rename to buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc6.config
diff --git a/patches/linux/3.15-rc5 b/patches/linux/3.15-rc6
similarity index 100%
rename from patches/linux/3.15-rc5
rename to patches/linux/3.15-rc6
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2014-05-18 22:03:15
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 3336bce3b64366e6477807074c0d5f162206fd46 (commit)
via 924c8e221f1841bcead5b827a9b9712c1379e5bf (commit)
via d27b127f970859dbe84023948b460ee00c34803c (commit)
from d3533eb7a474eb7071a1abdecda4b31b0b214082 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 3336bce3b64366e6477807074c0d5f162206fd46
Author: Philippe Reynes <tr...@ya...>
Date: Fri May 16 18:31:38 2014 +0200
[LINUX] 3.12: move to 3.12.20
commit 924c8e221f1841bcead5b827a9b9712c1379e5bf
Author: Philippe Reynes <tr...@ya...>
Date: Wed May 14 19:35:29 2014 +0200
[LINUX] 3.14: move to 3.14.4
commit d27b127f970859dbe84023948b460ee00c34803c
Author: Philippe Reynes <tr...@ya...>
Date: Wed May 14 19:35:28 2014 +0200
[LINUX] 3.10: move to 3.10.40
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf27mainline_defconfig | 4 ++--
buildroot/configs/apf28mainline_defconfig | 4 ++--
buildroot/configs/apf51mainline_defconfig | 4 ++--
...x-3.10.39.config => apf27-linux-3.10.40.config} | 0
...x-3.12.19.config => apf27-linux-3.12.20.config} | 0
...nux-3.14.3.config => apf27-linux-3.14.4.config} | 0
...x-3.10.39.config => apf28-linux-3.10.40.config} | 0
...x-3.12.19.config => apf28-linux-3.12.20.config} | 0
...nux-3.14.3.config => apf28-linux-3.14.4.config} | 0
...x-3.10.39.config => apf51-linux-3.10.40.config} | 0
...x-3.12.19.config => apf51-linux-3.12.20.config} | 0
...nux-3.14.3.config => apf51-linux-3.14.4.config} | 0
patches/linux/{3.10.39 => 3.10.40} | 0
patches/linux/{3.12.19 => 3.12.20} | 0
patches/linux/{3.14.3 => 3.14.4} | 0
15 files changed, 6 insertions(+), 6 deletions(-)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.10.39.config => apf27-linux-3.10.40.config} (100%)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.12.19.config => apf27-linux-3.12.20.config} (100%)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.14.3.config => apf27-linux-3.14.4.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.10.39.config => apf28-linux-3.10.40.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.12.19.config => apf28-linux-3.12.20.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.14.3.config => apf28-linux-3.14.4.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.10.39.config => apf51-linux-3.10.40.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.12.19.config => apf51-linux-3.12.20.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.14.3.config => apf51-linux-3.14.4.config} (100%)
rename patches/linux/{3.10.39 => 3.10.40} (100%)
rename patches/linux/{3.12.19 => 3.12.20} (100%)
rename patches/linux/{3.14.3 => 3.14.4} (100%)
diff --git a/buildroot/configs/apf27mainline_defconfig b/buildroot/configs/apf27mainline_defconfig
index 1edccfa..10fe162 100644
--- a/buildroot/configs/apf27mainline_defconfig
+++ b/buildroot/configs/apf27mainline_defconfig
@@ -6,7 +6,7 @@ BR2_CCACHE=y
BR2_CCACHE_DIR="$(TOPDIR)/.$(BR2_BOARD_NAME)-buildroot-ccache"
BR2_STRIP_sstrip=y
BR2_KERNEL_HEADERS_VERSION=y
-BR2_DEFAULT_KERNEL_VERSION="3.14.3"
+BR2_DEFAULT_KERNEL_VERSION="3.14.4"
BR2_UCLIBC_CONFIG="target/device/armadeus/uClibc-$(BR2_UCLIBC_VERSION_STRING).config"
BR2_TOOLCHAIN_BUILDROOT_LARGEFILE=y
BR2_TOOLCHAIN_BUILDROOT_INET_IPV6=y
@@ -34,7 +34,7 @@ BR2_BOARD_NAME="apf27"
BR2_CPU_NAME="imx27"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.3"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.4"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/buildroot/configs/apf28mainline_defconfig b/buildroot/configs/apf28mainline_defconfig
index 14d475b..dd8c6db 100644
--- a/buildroot/configs/apf28mainline_defconfig
+++ b/buildroot/configs/apf28mainline_defconfig
@@ -6,7 +6,7 @@ BR2_CCACHE=y
BR2_CCACHE_DIR="$(TOPDIR)/.$(BR2_BOARD_NAME)-buildroot-ccache"
BR2_STRIP_sstrip=y
BR2_KERNEL_HEADERS_VERSION=y
-BR2_DEFAULT_KERNEL_VERSION="3.14.3"
+BR2_DEFAULT_KERNEL_VERSION="3.14.4"
BR2_UCLIBC_CONFIG="target/device/armadeus/uClibc-$(BR2_UCLIBC_VERSION_STRING).config"
BR2_TOOLCHAIN_BUILDROOT_LARGEFILE=y
BR2_TOOLCHAIN_BUILDROOT_INET_IPV6=y
@@ -35,7 +35,7 @@ BR2_CPU_NAME="imx28"
BR2_TARGET_ARMADEUS_SDRAM_SIZE="128"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.3"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.4"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/buildroot/configs/apf51mainline_defconfig b/buildroot/configs/apf51mainline_defconfig
index 467de3b..977fd0e 100644
--- a/buildroot/configs/apf51mainline_defconfig
+++ b/buildroot/configs/apf51mainline_defconfig
@@ -7,7 +7,7 @@ BR2_CCACHE=y
BR2_CCACHE_DIR="$(TOPDIR)/.$(BR2_BOARD_NAME)-buildroot-ccache"
BR2_STRIP_sstrip=y
BR2_KERNEL_HEADERS_VERSION=y
-BR2_DEFAULT_KERNEL_VERSION="3.14.3"
+BR2_DEFAULT_KERNEL_VERSION="3.14.4"
BR2_UCLIBC_CONFIG="target/device/armadeus/uClibc-$(BR2_UCLIBC_VERSION_STRING).config"
BR2_TOOLCHAIN_BUILDROOT_LARGEFILE=y
BR2_TOOLCHAIN_BUILDROOT_INET_IPV6=y
@@ -97,7 +97,7 @@ BR2_TARGET_UBOOT_ENVIMAGE_SOURCE="$(ARMADEUS_PATH)/u-boot-env-2013.04.txt"
BR2_TARGET_UBOOT_ENVIMAGE_SIZE="0x20000"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.3"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.4"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.39.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.40.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.10.39.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.10.40.config
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.12.19.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.12.20.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.12.19.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.12.20.config
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.14.3.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.14.4.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.14.3.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.14.4.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.10.39.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.10.40.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.10.39.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.10.40.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.12.19.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.12.20.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.12.19.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.12.20.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.14.3.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.14.4.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.14.3.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.14.4.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.10.39.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.10.40.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.10.39.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.10.40.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.12.19.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.12.20.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.12.19.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.12.20.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.14.3.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.14.4.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.14.3.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.14.4.config
diff --git a/patches/linux/3.10.39 b/patches/linux/3.10.40
similarity index 100%
rename from patches/linux/3.10.39
rename to patches/linux/3.10.40
diff --git a/patches/linux/3.12.19 b/patches/linux/3.12.20
similarity index 100%
rename from patches/linux/3.12.19
rename to patches/linux/3.12.20
diff --git a/patches/linux/3.14.3 b/patches/linux/3.14.4
similarity index 100%
rename from patches/linux/3.14.3
rename to patches/linux/3.14.4
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2014-05-13 12:34:37
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via d3533eb7a474eb7071a1abdecda4b31b0b214082 (commit)
from 807c15de1a0519714e373a0413e18be042b8b33f (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit d3533eb7a474eb7071a1abdecda4b31b0b214082
Author: Eric Jarrige <eri...@ar...>
Date: Tue May 13 14:34:16 2014 +0200
[UBOOT] 2014.04: apf51: fix i2c bus
-----------------------------------------------------------------------
Summary of changes:
.../device/armadeus/apf51/apf51-u-boot-2014.04.h | 8 +--
.../0040-i2c-mxc-fix-mx51-i2c-declaration.patch | 41 ++++++++++++++++
patches/u-boot/2014.04/401-apf51.patch | 49 +++++--------------
3 files changed, 57 insertions(+), 41 deletions(-)
create mode 100644 patches/u-boot/2014.04/0040-i2c-mxc-fix-mx51-i2c-declaration.patch
diff --git a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2014.04.h b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2014.04.h
index b42dc59..10633c3 100644
--- a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2014.04.h
+++ b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2014.04.h
@@ -446,11 +446,9 @@
#ifdef CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0xfe
+#define CONFIG_SYS_MXC_I2C2_SPEED 400000
+#define CONFIG_SYS_MXC_I2C2_SLAVE 0xfe
+#define CONFIG_SYS_SPD_BUS_NUM 1 /* hack to force bus 1 by default */
#endif /* CONFIG_CMD_I2C */
/*
diff --git a/patches/u-boot/2014.04/0040-i2c-mxc-fix-mx51-i2c-declaration.patch b/patches/u-boot/2014.04/0040-i2c-mxc-fix-mx51-i2c-declaration.patch
new file mode 100644
index 0000000..ab992ec
--- /dev/null
+++ b/patches/u-boot/2014.04/0040-i2c-mxc-fix-mx51-i2c-declaration.patch
@@ -0,0 +1,41 @@
+From 8cc45b2a0332154b9ef2deaa3085da90f4397da7 Mon Sep 17 00:00:00 2001
+From: Eric Jarrige <eri...@ar...>
+Date: Tue, 13 May 2014 14:22:51 +0200
+Subject: [PATCH 1/1] i2c: mxc: fix mx51 i2c declaration
+
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+ drivers/i2c/mxc_i2c.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
+index 595019b..a4280b4 100644
+--- a/drivers/i2c/mxc_i2c.c
++++ b/drivers/i2c/mxc_i2c.c
+@@ -425,8 +425,11 @@ static void * const i2c_bases[] = {
+ #elif defined(CONFIG_MX27)
+ (void *)IMX_I2C1_BASE,
+ (void *)IMX_I2C2_BASE
++#elif defined(CONFIG_MX51)
++ (void *)I2C1_BASE_ADDR,
++ (void *)I2C2_BASE_ADDR,
+ #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
+- defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
++ defined(CONFIG_MX53) || \
+ defined(CONFIG_MX6)
+ (void *)I2C1_BASE_ADDR,
+ (void *)I2C2_BASE_ADDR,
+@@ -541,8 +544,7 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
+ CONFIG_SYS_MXC_I2C2_SPEED,
+ CONFIG_SYS_MXC_I2C2_SLAVE, 1)
+ #if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
+- defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
+- defined(CONFIG_MX6)
++ defined(CONFIG_MX53) || defined(CONFIG_MX6)
+ U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
+ mxc_i2c_read, mxc_i2c_write,
+ mxc_i2c_set_bus_speed,
+--
+1.7.9.5
+
diff --git a/patches/u-boot/2014.04/401-apf51.patch b/patches/u-boot/2014.04/401-apf51.patch
index 1e09789..0aaf17f 100644
--- a/patches/u-boot/2014.04/401-apf51.patch
+++ b/patches/u-boot/2014.04/401-apf51.patch
@@ -33,7 +33,7 @@ new file mode 100644
index 0000000..8ff1381
--- /dev/null
+++ b/board/armadeus/apf51/apf51.c
-@@ -0,0 +1,684 @@
+@@ -0,0 +1,677 @@
+/*
+ * Armadeus APF51 baseboard
+ *
@@ -494,36 +494,33 @@ index 0000000..8ff1381
+ imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
+}
+
-+#ifdef CONFIG_I2C_MXC
-+#define I2C_PAD_CFG (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
-+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-+
-+static void setup_i2c(unsigned int module_base)
++#ifdef CONFIG_SYS_I2C_MXC
++static void setup_i2c(unsigned int i2c_bus)
+{
+ static const iomux_v3_cfg_t i2c1_pads[] = {
-+ NEW_PAD_CTRL(MX51_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CFG),
-+ NEW_PAD_CTRL(MX51_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CFG),
++ MX51_PAD_I2C1_CLK__I2C1_CLK,
++ MX51_PAD_I2C1_DAT__I2C1_DAT,
+ };
+
+ static const iomux_v3_cfg_t i2c2_pads[] = {
-+ NEW_PAD_CTRL(MX51_PAD_EIM_D24__I2C2_SDA, I2C_PAD_CFG),
-+ NEW_PAD_CTRL(MX51_PAD_EIM_D27__I2C2_SCL, I2C_PAD_CFG),
++ MX51_PAD_EIM_D24__I2C2_SDA,
++ MX51_PAD_EIM_D27__I2C2_SCL,
+ };
+
+ /*
+ * Configure iomux for I2C interfaces
+ */
-+ switch (module_base) {
-+ case I2C1_BASE_ADDR:
++ switch (i2c_bus) {
++ case 0:
+ imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
+ break;
+
-+ case I2C2_BASE_ADDR: /* do not use without disabling UART3 first */
++ case 1:
+ imx_iomux_v3_setup_multiple_pads(i2c2_pads, ARRAY_SIZE(i2c2_pads));
+ break;
+
+ default:
-+ printf("Invalid I2C base: 0x%x\n", module_base);
++ printf("Invalid I2C bus: 0x%x\n", i2c_bus);
+ break;
+ }
+}
@@ -659,8 +656,8 @@ index 0000000..8ff1381
+ setup_spi_io();
+ setup_nfc();
+ setup_fec();
-+#ifdef CONFIG_I2C_MXC
-+ setup_i2c(I2C2_BASE_ADDR);
++#ifdef CONFIG_SYS_I2C_MXC
++ setup_i2c(1);
+#endif
+ setup_display();
+ setup_usb();
@@ -679,10 +676,6 @@ index 0000000..8ff1381
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CSD0_BASE_ADDR + 0x100;
+
-+#ifdef CONFIG_I2C_MXC
-+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-+#endif
-+
+#if defined(CONFIG_FPGA)
+ APF51_init_fpga();
+#endif
@@ -1004,21 +997,5 @@ index 9df6212..1aa7e95 100644
Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <mar...@gm...>
Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg -
Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <sb...@de...>
---- a/drivers/i2c/mxc_i2c.c
-+++ b/drivers/i2c/mxc_i2c.c
-@@ -425,8 +425,11 @@ static void * const i2c_bases[] = {
- #elif defined(CONFIG_MX27)
- (void *)IMX_I2C1_BASE,
- (void *)IMX_I2C2_BASE
-+#elif defined(CONFIG_MX51)
-+ (void *)I2C1_BASE_ADDR,
-+ (void *)I2C2_BASE_ADDR,
- #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
-- defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
-+ defined(CONFIG_MX53) || \
- defined(CONFIG_MX6)
- (void *)I2C1_BASE_ADDR,
- (void *)I2C2_BASE_ADDR,
---
1.7.2.5
hooks/post-receive
--
armadeus
|
|
From: Sébastien S. <ss...@us...> - 2014-05-12 08:29:57
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 807c15de1a0519714e373a0413e18be042b8b33f (commit)
via de15fb9f67dd604238a192bc505516b5e32d4683 (commit)
from 4f0c72f4fcce060b69c1fac5034bd7fd1f680d6c (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 807c15de1a0519714e373a0413e18be042b8b33f
Author: Sébastien Szymanski <ss...@us...>
Date: Mon May 12 10:29:33 2014 +0200
[LINUX] 3.15: dts: apf6: Few fixes in devicetrees
- add phy_type node to usbh1
- add no-1-8-v to the micro sd port
- move iomuxc nodes to the end of files.
commit de15fb9f67dd604238a192bc505516b5e32d4683
Author: Sébastien Szymanski <ss...@us...>
Date: Mon May 12 10:27:51 2014 +0200
[LINUX] 3.15: apf6: move to 3.15-rc5
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf6_defconfig | 2 +-
...-3.15-rc4.config => apf6-linux-3.15-rc5.config} | 0
...rmadeus-add-apf6q-and-apf6dl-device-trees.patch | 202 ++++++++++----------
3 files changed, 104 insertions(+), 100 deletions(-)
rename buildroot/target/device/armadeus/apf6/{apf6-linux-3.15-rc4.config => apf6-linux-3.15-rc5.config} (100%)
diff --git a/buildroot/configs/apf6_defconfig b/buildroot/configs/apf6_defconfig
index 235b120..dce06cb 100644
--- a/buildroot/configs/apf6_defconfig
+++ b/buildroot/configs/apf6_defconfig
@@ -22,7 +22,7 @@ BR2_TARGET_ARMADEUS_NR_SDRAM="2"
BR2_TARGET_ARMADEUS_SDRAM_SIZE="512"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.15-rc4"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.15-rc5"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc4.config b/buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc5.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc4.config
rename to buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc5.config
diff --git a/patches/linux/3.15/0450-armadeus-add-apf6q-and-apf6dl-device-trees.patch b/patches/linux/3.15/0450-armadeus-add-apf6q-and-apf6dl-device-trees.patch
index f9ba889..fdf1e6b 100644
--- a/patches/linux/3.15/0450-armadeus-add-apf6q-and-apf6dl-device-trees.patch
+++ b/patches/linux/3.15/0450-armadeus-add-apf6q-and-apf6dl-device-trees.patch
@@ -1,7 +1,7 @@
-Index: linux-3.15-rc2/arch/arm/boot/dts/imx6q-apf6dev.dts
+Index: linux-3.15-rc5/arch/arm/boot/dts/imx6q-apf6dev.dts
===================================================================
--- /dev/null
-+++ linux-3.15-rc2/arch/arm/boot/dts/imx6q-apf6dev.dts
++++ linux-3.15-rc5/arch/arm/boot/dts/imx6q-apf6dev.dts
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2014 Armadeus Systems
@@ -31,11 +31,11 @@ Index: linux-3.15-rc2/arch/arm/boot/dts/imx6q-apf6dev.dts
+&sata {
+ status = "okay";
+};
-Index: linux-3.15-rc2/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+Index: linux-3.15-rc5/arch/arm/boot/dts/imx6qdl-apf6.dtsi
===================================================================
--- /dev/null
-+++ linux-3.15-rc2/arch/arm/boot/dts/imx6qdl-apf6.dtsi
-@@ -0,0 +1,129 @@
++++ linux-3.15-rc5/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+@@ -0,0 +1,131 @@
+/*
+ * Copyright 2014 Armadeus Systems
+ *
@@ -80,6 +80,30 @@ Index: linux-3.15-rc2/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+ status = "okay";
+};
+
++/* Bluetooth */
++&uart2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart2>;
++ status = "okay";
++};
++
++/* Wi-Fi */
++&usdhc1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc1>;
++ status = "okay";
++};
++
++/* eMMC */
++&usdhc3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc3>;
++ bus-width = <8>;
++ no-1-8-v;
++ non-removable;
++ status = "okay";
++};
++
+&iomuxc {
+ apf6 {
+ pinctrl_enet: enetgrp {
@@ -143,33 +167,11 @@ Index: linux-3.15-rc2/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+ };
+ };
+};
-+
-+/* Bluetooth */
-+&uart2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart2>;
-+ status = "okay";
-+};
-+
-+/* Wi-Fi */
-+&usdhc1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_usdhc1>;
-+ status = "okay";
-+};
-+
-+/* eMMC */
-+&usdhc3 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_usdhc3>;
-+ //non-removable;
-+ status = "okay";
-+};
-Index: linux-3.15-rc2/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+Index: linux-3.15-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
===================================================================
--- /dev/null
-+++ linux-3.15-rc2/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
-@@ -0,0 +1,443 @@
++++ linux-3.15-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+@@ -0,0 +1,445 @@
+/*
+ * Copyright 2014 Armadeus Systems
+ *
@@ -371,6 +373,75 @@ Index: linux-3.15-rc2/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+ remote-endpoint = <&display_in>;
+};
+
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pcie>;
++ reset-gpio = <&gpio6 2 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&pwm3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm3>;
++ status = "okay";
++};
++
++/* GPS */
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart1>;
++ status = "okay";
++};
++
++/* GSM */
++&uart3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart3>;
++ status = "okay";
++};
++
++/* console */
++&uart4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart4>;
++ status = "okay";
++};
++
++&usbh1 {
++ vbus-supply = <®_usbh1_vbus>;
++ dr_mode = "host";
++ phy_type = "utmi";
++ status = "okay";
++};
++
++&usbotg {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg>;
++ vbus-supply = <®_otg_vbus>;
++ dr_mode = "otg";
++ status = "okay";
++};
++
++/* microSD */
++&usdhc2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc2>;
++ cd-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
++ no-1-8-v;
++ status = "okay";
++};
++
++&spdif {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_spdif>;
++ status = "okay";
++};
++
++&ssi1 {
++ fsl,mode = "i2s-slave";
++ status = "okay";
++};
++
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
@@ -546,77 +617,10 @@ Index: linux-3.15-rc2/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+ };
+ };
+};
-+
-+&pcie {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pcie>;
-+ reset-gpio = <&gpio6 2 GPIO_ACTIVE_HIGH>;
-+ status = "okay";
-+};
-+
-+&pwm3 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm3>;
-+ status = "okay";
-+};
-+
-+/* GPS */
-+&uart1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart1>;
-+ status = "okay";
-+};
-+
-+/* GSM */
-+&uart3 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart3>;
-+ status = "okay";
-+};
-+
-+/* console */
-+&uart4 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart4>;
-+ status = "okay";
-+};
-+
-+&usbh1 {
-+ vbus-supply = <®_usbh1_vbus>;
-+ dr_mode = "host";
-+ status = "okay";
-+};
-+
-+&usbotg {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_usbotg>;
-+ vbus-supply = <®_otg_vbus>;
-+ dr_mode = "otg";
-+ status = "okay";
-+};
-+
-+/* microSD */
-+&usdhc2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_usdhc2>;
-+ cd-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
-+ status = "okay";
-+};
-+
-+&spdif {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_spdif>;
-+ status = "okay";
-+};
-+
-+&ssi1 {
-+ fsl,mode = "i2s-slave";
-+ status = "okay";
-+};
-Index: linux-3.15-rc2/arch/arm/boot/dts/imx6dl-apf6dev.dts
+Index: linux-3.15-rc5/arch/arm/boot/dts/imx6dl-apf6dev.dts
===================================================================
--- /dev/null
-+++ linux-3.15-rc2/arch/arm/boot/dts/imx6dl-apf6dev.dts
++++ linux-3.15-rc5/arch/arm/boot/dts/imx6dl-apf6dev.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2014 Armadeus Systems
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2014-05-11 18:32:28
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 4f0c72f4fcce060b69c1fac5034bd7fd1f680d6c (commit)
via 8d0f293963229068869b33a9ac8a31f5290fbcbe (commit)
via 82c3bb44f1d576b8520a76bdf59b95c3dfc495f6 (commit)
from 709048bb3c1003066027979b593fe70b5f5bf41e (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 4f0c72f4fcce060b69c1fac5034bd7fd1f680d6c
Author: Philippe Reynes <tr...@ya...>
Date: Sun May 11 10:39:48 2014 +0200
[LINUX] 3.15: move to 3.15-rc5
commit 8d0f293963229068869b33a9ac8a31f5290fbcbe
Author: Philippe Reynes <tr...@ya...>
Date: Sun May 11 10:39:47 2014 +0200
[LINUX] 3.12: move to 3.12.19
commit 82c3bb44f1d576b8520a76bdf59b95c3dfc495f6
Author: Philippe Reynes <tr...@ya...>
Date: Sun May 11 10:39:46 2014 +0200
[LINUX] 3.10: move to 3.10.39
-----------------------------------------------------------------------
Summary of changes:
...x-3.10.38.config => apf27-linux-3.10.39.config} | 0
...x-3.12.18.config => apf27-linux-3.12.19.config} | 0
...3.15-rc4.config => apf27-linux-3.15-rc5.config} | 0
...x-3.10.38.config => apf28-linux-3.10.39.config} | 0
...x-3.12.18.config => apf28-linux-3.12.19.config} | 0
...3.15-rc4.config => apf28-linux-3.15-rc5.config} | 0
...x-3.10.38.config => apf51-linux-3.10.39.config} | 0
...x-3.12.18.config => apf51-linux-3.12.19.config} | 0
...3.15-rc4.config => apf51-linux-3.15-rc5.config} | 0
patches/linux/{3.10.38 => 3.10.39} | 0
patches/linux/{3.12.18 => 3.12.19} | 0
patches/linux/{3.15-rc4 => 3.15-rc5} | 0
12 files changed, 0 insertions(+), 0 deletions(-)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.10.38.config => apf27-linux-3.10.39.config} (100%)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.12.18.config => apf27-linux-3.12.19.config} (100%)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.15-rc4.config => apf27-linux-3.15-rc5.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.10.38.config => apf28-linux-3.10.39.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.12.18.config => apf28-linux-3.12.19.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.15-rc4.config => apf28-linux-3.15-rc5.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.10.38.config => apf51-linux-3.10.39.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.12.18.config => apf51-linux-3.12.19.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.15-rc4.config => apf51-linux-3.15-rc5.config} (100%)
rename patches/linux/{3.10.38 => 3.10.39} (100%)
rename patches/linux/{3.12.18 => 3.12.19} (100%)
rename patches/linux/{3.15-rc4 => 3.15-rc5} (100%)
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.38.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.39.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.10.38.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.10.39.config
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.12.18.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.12.19.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.12.18.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.12.19.config
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc4.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc5.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc4.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc5.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.10.38.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.10.39.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.10.38.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.10.39.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.12.18.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.12.19.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.12.18.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.12.19.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc4.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc5.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc4.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc5.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.10.38.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.10.39.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.10.38.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.10.39.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.12.18.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.12.19.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.12.18.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.12.19.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc4.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc5.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc4.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc5.config
diff --git a/patches/linux/3.10.38 b/patches/linux/3.10.39
similarity index 100%
rename from patches/linux/3.10.38
rename to patches/linux/3.10.39
diff --git a/patches/linux/3.12.18 b/patches/linux/3.12.19
similarity index 100%
rename from patches/linux/3.12.18
rename to patches/linux/3.12.19
diff --git a/patches/linux/3.15-rc4 b/patches/linux/3.15-rc5
similarity index 100%
rename from patches/linux/3.15-rc4
rename to patches/linux/3.15-rc5
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2014-05-11 10:31:27
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 709048bb3c1003066027979b593fe70b5f5bf41e (commit)
from 15e47cfd2f6345caf2d097450a25812dd7117681 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 709048bb3c1003066027979b593fe70b5f5bf41e
Author: Eric Jarrige <eri...@ar...>
Date: Sun May 11 12:31:14 2014 +0200
[UBOOT] 2014.04: apf51: cleanup
-----------------------------------------------------------------------
Summary of changes:
patches/u-boot/2014.04/401-apf51.patch | 202 +-------------------------------
1 files changed, 1 insertions(+), 201 deletions(-)
diff --git a/patches/u-boot/2014.04/401-apf51.patch b/patches/u-boot/2014.04/401-apf51.patch
index 57baa3c..1e09789 100644
--- a/patches/u-boot/2014.04/401-apf51.patch
+++ b/patches/u-boot/2014.04/401-apf51.patch
@@ -33,7 +33,7 @@ new file mode 100644
index 0000000..8ff1381
--- /dev/null
+++ b/board/armadeus/apf51/apf51.c
-@@ -0,0 +1,884 @@
+@@ -0,0 +1,684 @@
+/*
+ * Armadeus APF51 baseboard
+ *
@@ -718,206 +718,6 @@ index 0000000..8ff1381
+ asm("mcr 15, 0, r0, c1, c0, 1");
+}
+#endif
-+
-+#if defined(CONFIG_CMD_BSP)
-+/*
-+ * display dcd table. to delete
-+ */
-+int do_mx51_show_dcd_tab(cmd_tbl_t *cmdtp, int flag, int argc,
-+ char *const argv[])
-+{
-+ ulong i = 1;
-+ struct esdctl_regs *esdctl = (struct esdctl_regs *)ESDCTL_BASE_ADDR;
-+ char dcd_item[] = "MXC_DCD_ITEM(%ld, %ld, %#010lX, %#010lX)\n";
-+
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_RAS__DRAM_RAS
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_RAS);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_CAS__DRAM_CAS
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_CAS);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_SDWE__DRAM_SDWE
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_SDWE);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_SDCKE0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_SDCKE1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_SDCLK__DRAM_SDCLK
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_SDCLK);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_SDQS0__DRAM_SDQS0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_SDQS0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_SDQS1__DRAM_SDQS1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_SDQS1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_SDQS2__DRAM_SDQS2
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_SDQS2);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_SDQS3__DRAM_SDQS3
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_SDQS3);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_CS0__DRAM_CS0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_CS0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_CS1__DRAM_CS1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_CS1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_DQM0__DRAM_DQM0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_DQM0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_DQM1__DRAM_DQM1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_DQM1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_DQM2__DRAM_DQM2
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_DQM2);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_DQM3__DRAM_DQM3
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_DQM3);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_EIM_SDBA2__EIM_SDBA2
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_EIM_SDBA2);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_EIM_SDODT1__EIM_SDODT1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_EIM_SDODT1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_EIM_SDODT0__EIM_SDODT0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_EIM_SDODT0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DDRPKS
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDRPKS);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DRAM_B4
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DRAM_B4);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_INDDR
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_INDDR);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_PKEDDR
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_PKEDDR);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DDR_A0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDR_A0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DDR_A1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDR_A1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DDRAPUS
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDRAPUS);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_HYSDDR0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_HYSDDR0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_HYSDDR1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_HYSDDR1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_HYSDDR2
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_HYSDDR2);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_HVDDR
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_HVDDR);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_HYSDDR3
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_HYSDDR3);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DRAM_SR_B0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDR_SR_B0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DDRAPKS
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDRAPKS);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DRAM_SR_B1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDR_SR_B1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DDRPUS
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDRPUS);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DRAM_SR_B2
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDR_SR_B2);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_PKEADDR
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_PKEADDR);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DRAM_SR_B4
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDR_SR_B4);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_INMODE1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_INMODE1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DRAM_B0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DRAM_B0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DRAM_B1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DRAM_B1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DDR_SR_A0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDR_SR_A0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DRAM_B2
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DRAM_B2);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR +((MX51_GRP_DDR_SR_A1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDR_SR_A1);
-+
-+ printf(dcd_item, i++, 4, &esdctl->esdctl0,
-+ (ACFG_SDRAM_ESDCTL_REGISTER_VAL & 0x8FFFFFFF));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, DRR_PRECHARGE_CMD(0, 0));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, DRR_AUTOREFRESH_CMD(0));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, DRR_AUTOREFRESH_CMD(0));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr,
-+ DRR_LMR_CMD(0, 0, ACFG_DRR_MR_VAL));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr,
-+ DRR_LMR_CMD(0, 2, ACFG_DRR_EMR_VAL));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, DDR_NOP_CMD(0));
-+ printf(dcd_item, i++, 4, &esdctl->esdctl0,
-+ ACFG_SDRAM_ESDCTL_REGISTER_VAL);
-+ printf(dcd_item, i++, 4, &esdctl->esdcfg0,
-+ ACFG_SDRAM_ESDCFG_REGISTER_VAL);
-+
-+ printf(dcd_item, i++, 4, &esdctl->esdctl1,
-+ (ACFG_SDRAM_ESDCTL_REGISTER_VAL & 0x8FFFFFFF));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, DRR_PRECHARGE_CMD(1, 0));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, DRR_AUTOREFRESH_CMD(1));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, DRR_AUTOREFRESH_CMD(1));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr,
-+ DRR_LMR_CMD(1, 0, ACFG_DRR_MR_VAL));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr,
-+ DRR_LMR_CMD(1, 2, ACFG_DRR_EMR_VAL));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, DDR_NOP_CMD(1));
-+ printf(dcd_item, i++, 4, &esdctl->esdctl1,
-+ ACFG_SDRAM_ESDCTL_REGISTER_VAL);
-+ printf(dcd_item, i++, 4, &esdctl->esdcfg1,
-+ ACFG_SDRAM_ESDCFG_REGISTER_VAL);
-+
-+ printf(dcd_item, i++, 4, &esdctl->esdmisc,
-+ ACFG_SDRAM_ESDMISC_REGISTER_VAL);
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, 0x00000000);
-+
-+ printf(dcd_item, i++, 4, &esdctl->esdgpr,
-+ ACFG_SDRAM_ESDGPR_REGISTER_VAL);
-+ printf(dcd_item, i++, 4, &esdctl->esdcdly1,
-+ ACFG_SDRAM_ESDCDLY1_REGISTER_VAL);
-+ printf(dcd_item, i++, 4, &esdctl->esdcdly2,
-+ ACFG_SDRAM_ESDCDLY2_REGISTER_VAL);
-+ printf(dcd_item, i++, 4, &esdctl->esdcdly3,
-+ ACFG_SDRAM_ESDCDLY3_REGISTER_VAL);
-+ printf(dcd_item, i++, 4, &esdctl->esdcdly4,
-+ ACFG_SDRAM_ESDCDLY4_REGISTER_VAL);
-+ printf(dcd_item, i++, 4, &esdctl->esdcdly5,
-+ ACFG_SDRAM_ESDCDLY5_REGISTER_VAL);
-+
-+ return 0;
-+}
-+
-+/***************************************************/
-+
-+U_BOOT_CMD(dcdshow, 1, 1, do_mx51_show_dcd_tab,
-+ "display mx51 dcd tab\n", "");
-+#endif /* CONFIG_CMD_BSP */
diff --git a/board/armadeus/apf51/fpga.c b/board/armadeus/apf51/fpga.c
new file mode 100644
index 0000000..665928e
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2014-05-11 09:25:09
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 15e47cfd2f6345caf2d097450a25812dd7117681 (commit)
from 4cf3a49cdf7fb2f262d485d68e407bb3a08928d7 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 15e47cfd2f6345caf2d097450a25812dd7117681
Author: Eric Jarrige <eri...@ar...>
Date: Sun May 11 11:24:40 2014 +0200
[UBOOT] 2014.04: apf51: fix ethernet PHY signal integrity
-----------------------------------------------------------------------
Summary of changes:
patches/u-boot/2014.04/401-apf51.patch | 5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/patches/u-boot/2014.04/401-apf51.patch b/patches/u-boot/2014.04/401-apf51.patch
index 0e4ba2a..57baa3c 100644
--- a/patches/u-boot/2014.04/401-apf51.patch
+++ b/patches/u-boot/2014.04/401-apf51.patch
@@ -33,7 +33,7 @@ new file mode 100644
index 0000000..8ff1381
--- /dev/null
+++ b/board/armadeus/apf51/apf51.c
-@@ -0,0 +1,885 @@
+@@ -0,0 +1,884 @@
+/*
+ * Armadeus APF51 baseboard
+ *
@@ -532,8 +532,7 @@ index 0000000..8ff1381
+static void setup_fec(void)
+{
+#ifdef CONFIG_FEC_MXC
-+#define FEC_PAD_CFG (PAD_CTL_DSE_MED | PAD_CTL_PKE | \
-+ PAD_CTL_HYS )
++#define FEC_PAD_CFG (PAD_CTL_DSE_MED | PAD_CTL_HYS )
+
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_DI_GP3__FEC_TX_ER, FEC_PAD_CFG),
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2014-05-09 10:22:14
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 4cf3a49cdf7fb2f262d485d68e407bb3a08928d7 (commit)
from e2d9531d27c689bae736ea88d561d9c0fe0a3b61 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 4cf3a49cdf7fb2f262d485d68e407bb3a08928d7
Author: Eric Jarrige <eri...@ar...>
Date: Fri May 9 12:22:03 2014 +0200
[UBOOT] 2014.04: afp51: patch refactoring
-----------------------------------------------------------------------
Summary of changes:
patches/u-boot/2014.04/400-imx51.patch | 261 ++++++++++++++++++-
patches/u-boot/2014.04/401-apf51.patch | 118 +---------
patches/u-boot/2014.04/420-apf51-nand-spl-NG.patch | 39 +---
3 files changed, 254 insertions(+), 164 deletions(-)
diff --git a/patches/u-boot/2014.04/400-imx51.patch b/patches/u-boot/2014.04/400-imx51.patch
index 9066d23..66cebe9 100644
--- a/patches/u-boot/2014.04/400-imx51.patch
+++ b/patches/u-boot/2014.04/400-imx51.patch
@@ -4,14 +4,14 @@ Signed-off-by: Philippe Reynes <tr...@ya...>
arch/arm/cpu/armv7/cpu.c
arch/arm/cpu/armv7/mx5/lowlevel_init.S
arch/arm/include/asm/arch-mx5/imx-regs.h
- arch/arm/include/asm/arch-mx5/mx5x_pins.h
+ arch/arm/include/asm/arch-mx5/iomux-mx51.h
arch/arm/include/asm/arch-mx5/regs_esdctl.h
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 39a8023..c8c2293 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
-@@ -82,5 +82,9 @@ int cleanup_before_linux(void)
+@@ -66,5 +66,9 @@ int cleanup_before_linux(void)
*/
cpu_cache_initialization();
@@ -25,7 +25,7 @@ diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/low
index a40b84f..1ca9b22 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
-@@ -24,6 +24,34 @@
+@@ -11,6 +11,34 @@
#include <generated/asm-offsets.h>
#include <linux/linkage.h>
@@ -60,7 +60,7 @@ index a40b84f..1ca9b22 100644
.section ".text.init", "x"
.macro init_arm_erratum
-@@ -114,7 +142,7 @@
+@@ -107,7 +135,7 @@
#define W_DP_MFN 8
setup_pll_func:
@@ -69,7 +69,7 @@ index a40b84f..1ca9b22 100644
str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
mov r1, #0x2
str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-@@ -131,7 +159,7 @@
+@@ -124,7 +152,7 @@
str r1, [r0, #PLL_DP_MFN]
str r1, [r0, #PLL_DP_HFS_MFN]
@@ -78,7 +78,7 @@ index a40b84f..1ca9b22 100644
str r1, [r0, #PLL_DP_CTL]
1: ldr r1, [r0, #PLL_DP_CTL]
ands r1, r1, #0x1
-@@ -143,7 +171,7 @@
+@@ -136,7 +164,7 @@
.macro setup_pll_errata pll, freq
ldr r2, =\pll
str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
@@ -87,7 +87,7 @@ index a40b84f..1ca9b22 100644
str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
ands r1, r1, #0x1
-@@ -172,6 +200,16 @@
+@@ -165,6 +193,16 @@
#if defined (CONFIG_MX51)
ldr r0, =CCM_BASE_ADDR
@@ -104,7 +104,7 @@ index a40b84f..1ca9b22 100644
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
-@@ -199,7 +237,7 @@
+@@ -192,7 +230,7 @@
bne 1b
/* Switch ARM to step clock */
@@ -113,7 +113,7 @@ index a40b84f..1ca9b22 100644
str r1, [r0, #CLKCTL_CCSR]
#if defined(CONFIG_MX51_PLL_ERRATA)
-@@ -244,13 +282,14 @@
+@@ -237,13 +275,14 @@
str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1 */
@@ -132,7 +132,7 @@ index a40b84f..1ca9b22 100644
ldr r1, =CONFIG_SYS_CLKTL_CBCDR
str r1, [r0, #CLKCTL_CBCDR]
-@@ -265,9 +304,9 @@
+@@ -258,9 +297,9 @@
str r1, [r0, #CLKCTL_CCGR6]
/* Use PLL 2 for UART's, get 66.5MHz from it */
@@ -148,15 +148,15 @@ diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arc
index 46017f4..520bf98 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
-@@ -267,6 +267,7 @@
- #define M4IF_FBPM0 0x40
- #define M4IF_FIDBP 0x48
+@@ -255,6 +255,7 @@
+ #define M4IF_GENP_WEIM_MM_MASK 0x00000001
+ #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
+#ifndef DP_OP_800
/* Assuming 24MHz input clock with doubler ON */
/* MFI PDF */
#define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
-@@ -305,6 +306,7 @@
+@@ -293,6 +294,7 @@
#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
#define DP_MFD_216 (4 - 1)
#define DP_MFN_216 3
@@ -164,6 +164,239 @@ index 46017f4..520bf98 100644
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_1 0x11
+diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
+--- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h
++++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
+@@ -60,9 +60,17 @@ enum {
+ MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
++ MX51_PAD_EIM_D24__I2C2_SDA = IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL),
+ MX51_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL),
++ MX51_PAD_EIM_D25__UART2_CTS = IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_EIM_D26__UART3_TXD = IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL),
++ MX51_PAD_EIM_D26__UART2_RTS = IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL),
++ MX51_PAD_EIM_D27__I2C2_SCL = IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL),
+ MX51_PAD_EIM_D27__GPIO2_9 = IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_EIM_D28__AUD6_TXD = IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_D29__AUD6_RXD = IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_D30__AUD6_TXC = IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_D31__AUD6_TXFS = IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_A16__GPIO2_10 = IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A17__GPIO2_11 = IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A20__GPIO2_14 = IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+@@ -73,16 +81,22 @@ enum {
+ MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_EB2__FEC_MDIO = IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, PAD_CTL_PUS_22K_UP | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_HYS),
+- MX51_PAD_EIM_EB3__FEC_RDATA1 = IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_EB2__AUD5_RXFS = IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_EB3__GPIO2_23 = IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_EIM_EB3__FEC_RDATA1 = IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_EB3__AUD5_RXC = IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS0__GPIO2_25 = IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+- MX51_PAD_EIM_CS2__FEC_RDATA2 = IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS2__GPIO2_27 = IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+- MX51_PAD_EIM_CS3__FEC_RDATA3 = IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_CS2__FEC_RDATA2 = IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_CS2__AUD5_TXD = IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS3__GPIO2_28 = IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+- MX51_PAD_EIM_CS4__FEC_RX_ER = IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_EIM_CS3__FEC_RDATA3 = IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_CS3__AUD5_RXD = IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS4__GPIO2_29 = IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_EIM_CS4__FEC_RX_ER = IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_EIM_CS4__AUD5_TXC = IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS5__FEC_CRS = IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_EIM_CS5__AUD5_TXFS = IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL),
+ MX51_PAD_DRAM_RAS__DRAM_RAS = IOMUX_PAD(0x4a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_CAS__DRAM_CAS = IOMUX_PAD(0x4a8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDWE__DRAM_SDWE = IOMUX_PAD(0x4ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+@@ -99,18 +113,31 @@ enum {
+ MX51_PAD_DRAM_DQM1__DRAM_DQM1 = IOMUX_PAD(0x4d8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_DQM2__DRAM_DQM2 = IOMUX_PAD(0x4dc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_DQM3__DRAM_DQM3 = IOMUX_PAD(0x4e0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_WE_B__NANDF_WE_B = IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_WE_B__PATA_DIOW = IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_RE_B__NANDF_RE_B = IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RE_B__PATA_DIOR = IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_ALE__NANDF_ALE = IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_ALE__PATA_BUFFER_EN = IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_CLE__NANDF_CLE = IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CLE__PATA_RESET_B = IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_WP_B__NANDF_WP_B = IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_WP_B__PATA_DMACK = IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_RB0__NANDF_RB0 = IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RB0__PATA_DMARQ = IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RB1__PATA_IORDY = IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_RB1__ECSPI2_RDY = IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_NANDF_RB2__FEC_COL = IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_NANDF_RB2__ECSPI2_SCLK = IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_NANDF_RB2__GPIO3_10 = IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_RB3__FEC_RX_CLK = IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_NANDF_RB3__ECSPI2_MISO = IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_NANDF_RB3__GPIO3_11 = IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_EIM_SDBA2__EIM_SDBA2 = IOMUX_PAD(0x508, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_SDODT1__EIM_SDODT1 = IOMUX_PAD(0x50C, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_SDODT0__EIM_SDODT0 = IOMUX_PAD(0x510, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO_NAND__PATA_INTRQ = IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_CS0__NANDF_CS0 = IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS2__FEC_TX_ER = IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_NANDF_CS2__PATA_CS_0 = IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS3__FEC_MDC = IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5),
+@@ -123,13 +150,17 @@ enum {
+ MX51_PAD_NANDF_CS6__PATA_DA_2 = IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS7__FEC_TX_EN = IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK = IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4),
+- MX51_PAD_NANDF_D15__GPIO3_25 = IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_D15__PATA_DATA15 = IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+- MX51_PAD_NANDF_D14__GPIO3_26 = IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_NANDF_D15__ECSPI2_MOSI = IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
++ MX51_PAD_NANDF_D15__GPIO3_25 = IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_D14__PATA_DATA14 = IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+- MX51_PAD_NANDF_D13__GPIO3_27 = IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_NANDF_D14__ECSPI2_SS3 = IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL),
++ MX51_PAD_NANDF_D14__GPIO3_26 = IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_D13__PATA_DATA13 = IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D13__ECSPI2_SS2 = IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
++ MX51_PAD_NANDF_D13__GPIO3_27 = IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_D12__PATA_DATA12 = IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D12__ECSPI2_SS1 = IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_NANDF_D11__FEC_RX_DV = IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D11__PATA_DATA11 = IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D10__GPIO3_30 = IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+@@ -139,16 +170,47 @@ enum {
+ MX51_PAD_NANDF_D9__PATA_DATA9 = IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D8__FEC_TDATA0 = IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_NANDF_D8__PATA_DATA8 = IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D7__NANDF_D7 = IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D7__PATA_DATA7 = IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D6__NANDF_D6 = IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D6__PATA_DATA6 = IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D5__NANDF_D5 = IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D5__PATA_DATA5 = IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D4__NANDF_D4 = IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D4__PATA_DATA4 = IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D3__NANDF_D3 = IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D3__PATA_DATA3 = IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D2__NANDF_D2 = IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D2__PATA_DATA2 = IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D1__NANDF_D1 = IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D1__PATA_DATA1 = IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D0__NANDF_D0 = IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D0__PATA_DATA0 = IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D8__CSI1_D8 = IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D9__CSI1_D9 = IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D10__CSI1_D10 = IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D11__CSI1_D11 = IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D12__CSI1_D12 = IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D13__CSI1_D13 = IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D14__CSI1_D14 = IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D15__CSI1_D15 = IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D16__CSI1_D16 = IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D17__CSI1_D17 = IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D18__CSI1_D18 = IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D19__CSI1_D19 = IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_VSYNC__CSI1_VSYNC = IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_HSYNC__CSI1_HSYNC = IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK = IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_MCLK__CSI1_MCLK = IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL),
+ MX51_PAD_CSI2_D12__GPIO4_9 = IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSI2_D13__GPIO4_10 = IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_CSI2_D18__GPIO4_11 = IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL),
++ MX51_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL),
++ MX51_PAD_AUD3_BB_TXD__AUD3_TXD = IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_AUD3_BB_RXD__AUD3_RXD = IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_AUD3_BB_CK__AUD3_TXC = IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_AUD3_BB_FS__AUD3_TXFS = IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_CSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_CSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+@@ -162,6 +224,10 @@ enum {
+ MX51_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL),
++ MX51_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL),
++ MX51_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL),
++ MX51_PAD_UART3_RXD__UART3_RXD = IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL),
++ MX51_PAD_UART3_TXD__UART3_TXD = IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_USBH1_CLK__USBH1_CLK = IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DIR__USBH1_DIR = IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_STP__GPIO1_27 = IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL),
+@@ -175,6 +241,7 @@ enum {
+ MX51_PAD_USBH1_DATA5__USBH1_DATA5 = IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA6__USBH1_DATA6 = IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA7__USBH1_DATA7 = IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
++ MX51_PAD_DI1_PIN11__GPIO3_0 = IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DI1_PIN11__ECSPI1_SS2 = IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_DI1_PIN12__GPIO3_1 = IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DI1_PIN13__GPIO3_2 = IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL),
+@@ -182,10 +249,30 @@ enum {
+ MX51_PAD_DI1_D1_CS__GPIO3_4 = IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DISPB2_SER_DIN__GPIO3_5 = IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DISPB2_SER_DIO__GPIO3_6 = IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_DISPB2_SER_CLK__GPIO3_7 = IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_DISPB2_SER_RS__GPIO3_8 = IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DI1_PIN3__DI1_PIN3 = IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DI1_PIN2__DI1_PIN2 = IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_DI_GP3__FEC_TX_ER = IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5),
++ MX51_PAD_DI2_PIN4__FEC_CRS = IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL),
++ MX51_PAD_DI2_PIN2__FEC_MDC = IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5),
++ MX51_PAD_DI2_PIN3__FEC_MDIO = IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL),
+ MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK = IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 = IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL),
++ MX51_PAD_DI_GP4__FEC_RDATA2 = IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL),
+ MX51_PAD_DI_GP4__DI2_PIN15 = IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_DISP2_DAT0__FEC_RDATA3 = IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL),
++ MX51_PAD_DISP2_DAT1__FEC_RX_ER = IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL),
++ MX51_PAD_DISP2_DAT6__FEC_TDATA1 = IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5),
++ MX51_PAD_DISP2_DAT7__FEC_TDATA2 = IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5),
++ MX51_PAD_DISP2_DAT8__FEC_TDATA3 = IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5),
++ MX51_PAD_DISP2_DAT9__FEC_TX_EN = IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5),
++ MX51_PAD_DISP2_DAT10__FEC_COL = IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL),
++ MX51_PAD_DISP2_DAT11__FEC_RX_CLK = IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL),
++ MX51_PAD_DISP2_DAT12__FEC_RX_DV = IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL),
++ MX51_PAD_DISP2_DAT13__FEC_TX_CLK = IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4),
++ MX51_PAD_DISP2_DAT14__FEC_RDATA0 = IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4),
++ MX51_PAD_DISP2_DAT15__FEC_TDATA0 = IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+ MX51_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
+ MX51_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+@@ -204,13 +291,17 @@ enum {
+ MX51_PAD_GPIO1_2__GPIO1_2 = IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_GPIO1_2__PWM1_PWMO = IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO1_3__GPIO1_3 = IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_GPIO1_3__PWM2_PWMO = IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_GPIO1_4__GPIO1_4 = IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_GPIO1_5__GPIO1_5 = IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_GPIO1_5__CCM_CLKO = IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO1_6__GPIO1_6 = IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_GPIO1_7__GPIO1_7 = IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_GPIO1_7__SD2_WP = IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+ MX51_PAD_GPIO1_8__SD2_CD = IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+ MX51_GRP_DDRPKS = IOMUX_PAD(0x820, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_B4 = IOMUX_PAD(0x82c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_GRP_INDDR = IOMUX_PAD(0x830, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_PKEDDR = IOMUX_PAD(0x838, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDR_A0 = IOMUX_PAD(0x83c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDR_A1 = IOMUX_PAD(0x848, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+@@ -218,6 +309,7 @@ enum {
+ MX51_GRP_HYSDDR0 = IOMUX_PAD(0x85c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_HYSDDR1 = IOMUX_PAD(0x864, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_HYSDDR2 = IOMUX_PAD(0x86c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_GRP_HVDDR = IOMUX_PAD(0x870, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_HYSDDR3 = IOMUX_PAD(0x874, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_SR_B0 = IOMUX_PAD(0x878, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDRAPKS = IOMUX_PAD(0x87c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+@@ -229,6 +321,7 @@ enum {
+ MX51_GRP_INMODE1 = IOMUX_PAD(0x8a0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_B0 = IOMUX_PAD(0x8a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_B1 = IOMUX_PAD(0x8ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_GRP_DDR_SR_A0 = IOMUX_PAD(0x8b0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_B2 = IOMUX_PAD(0x8b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDR_SR_A1 = IOMUX_PAD(0x8bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ };
diff --git a/arch/arm/include/asm/arch-mx5/regs_esdctl.h b/arch/arm/include/asm/arch-mx5/regs_esdctl.h
new file mode 100644
index 0000000..1c0bf8e
diff --git a/patches/u-boot/2014.04/401-apf51.patch b/patches/u-boot/2014.04/401-apf51.patch
index 9ca4ad4..0e4ba2a 100644
--- a/patches/u-boot/2014.04/401-apf51.patch
+++ b/patches/u-boot/2014.04/401-apf51.patch
@@ -33,7 +33,7 @@ new file mode 100644
index 0000000..8ff1381
--- /dev/null
+++ b/board/armadeus/apf51/apf51.c
-@@ -0,0 +1,999 @@
+@@ -0,0 +1,885 @@
+/*
+ * Armadeus APF51 baseboard
+ *
@@ -177,14 +177,6 @@ index 0000000..8ff1381
+
+void setup_uart(void)
+{
-+enum {
-+ MX51_PAD_EIM_D25__UART2_CTS = IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL),
-+ MX51_PAD_EIM_D26__UART2_RTS = IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL),
-+ MX51_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL),
-+ MX51_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL),
-+ MX51_PAD_UART3_RXD__UART3_RXD = IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL),
-+ MX51_PAD_UART3_TXD__UART3_TXD = IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL),
-+};
+ /*
+ * Configure iomux for UART interfaces
+ */
@@ -225,22 +217,6 @@ index 0000000..8ff1381
+
+void setup_audio(void)
+{
-+enum {
-+ MX51_PAD_AUD3_BB_TXD__AUD3_TXD = IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_AUD3_BB_RXD__AUD3_RXD = IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_AUD3_BB_CK__AUD3_TXC = IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_AUD3_BB_FS__AUD3_TXFS = IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_EB2__AUD5_RXFS = IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_EB3__AUD5_RXC = IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_CS2__AUD5_TXD = IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL),
-+ MX51_PAD_EIM_CS3__AUD5_RXD = IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL),
-+ MX51_PAD_EIM_CS4__AUD5_TXC = IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL),
-+ MX51_PAD_EIM_CS5__AUD5_TXFS = IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL),
-+ MX51_PAD_EIM_D28__AUD6_TXD = IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_D29__AUD6_RXD = IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_D30__AUD6_TXC = IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_D31__AUD6_TXFS = IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL),
-+};
+ /*
+ * Configure iomux for audio interfaces
+ */
@@ -288,24 +264,6 @@ index 0000000..8ff1381
+
+void setup_csi(void)
+{
-+enum {
-+ MX51_PAD_CSI1_D8__CSI1_D8 = IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D9__CSI1_D9 = IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D10__CSI1_D10 = IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D11__CSI1_D11 = IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D12__CSI1_D12 = IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D13__CSI1_D13 = IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D14__CSI1_D14 = IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D15__CSI1_D15 = IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D16__CSI1_D16 = IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D17__CSI1_D17 = IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D18__CSI1_D18 = IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D19__CSI1_D19 = IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_VSYNC__CSI1_VSYNC = IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_HSYNC__CSI1_HSYNC = IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK = IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_MCLK__CSI1_MCLK = IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL),
-+};
+ /*
+ * Configure iomux for CSI interfaces
+ */
@@ -396,14 +354,6 @@ index 0000000..8ff1381
+
+void setup_misc(void)
+{
-+enum {
-+ MX51_PAD_GPIO1_3__PWM2_PWMO = IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_GPIO1_4__GPIO1_4 = IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
-+ MX51_PAD_GPIO1_5__CCM_CLKO = IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_DI1_PIN11__GPIO3_0 = IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL),
-+ MX51_PAD_DISPB2_SER_CLK__GPIO3_7 = IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL),
-+ MX51_PAD_DISPB2_SER_RS__GPIO3_8 = IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL),
-+};
+ /*
+ * Configure iomux for misc interfaces
+ */
@@ -470,7 +420,7 @@ index 0000000..8ff1381
+ FPGA_PAD_CFG));
+
+ /* FPGA INIT# */
-+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D18__GPIO4_11,
+ FPGA_PAD_CFG));
+}
+
@@ -486,25 +436,6 @@ index 0000000..8ff1381
+
+void setup_nfc(void)
+{
-+/* PAD MUX ALT INPSE PATH PADCTRL */
-+enum {
-+ MX51_PAD_NANDF_WE_B__NANDF_WE_B = IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_RE_B__NANDF_RE_B = IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_ALE__NANDF_ALE = IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_CLE__NANDF_CLE = IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_WP_B__NANDF_WP_B = IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_RB0__NANDF_RB0 = IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_CS0__NANDF_CS0 = IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D7__NANDF_D7 = IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D6__NANDF_D6 = IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D5__NANDF_D5 = IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D4__NANDF_D4 = IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D3__NANDF_D3 = IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D2__NANDF_D2 = IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D1__NANDF_D1 = IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D0__NANDF_D0 = IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL),
-+};
-+
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_NANDF_WE_B__NANDF_WE_B,
+ PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH));
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_NANDF_RE_B__NANDF_RE_B,
@@ -537,15 +468,6 @@ index 0000000..8ff1381
+
+void setup_spi_io(void)
+{
-+enum {
-+ MX51_PAD_NANDF_RB1__ECSPI2_RDY = IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
-+ MX51_PAD_NANDF_RB2__ECSPI2_SCLK = IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
-+ MX51_PAD_NANDF_RB3__ECSPI2_MISO = IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
-+ MX51_PAD_NANDF_D15__ECSPI2_MOSI = IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
-+ MX51_PAD_NANDF_D14__ECSPI2_SS3 = IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL),
-+ MX51_PAD_NANDF_D13__ECSPI2_SS2 = IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
-+ MX51_PAD_NANDF_D12__ECSPI2_SS1 = IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL),
-+};
+ /*
+ * Configure iomux for SPI interface
+ */
@@ -578,13 +500,6 @@ index 0000000..8ff1381
+
+static void setup_i2c(unsigned int module_base)
+{
-+enum {
-+ MX51_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL),
-+ MX51_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL),
-+ MX51_PAD_EIM_D24__I2C2_SDA = IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL),
-+ MX51_PAD_EIM_D27__I2C2_SCL = IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL),
-+};
-+
+ static const iomux_v3_cfg_t i2c1_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CFG),
+ NEW_PAD_CTRL(MX51_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CFG),
@@ -620,27 +535,6 @@ index 0000000..8ff1381
+#define FEC_PAD_CFG (PAD_CTL_DSE_MED | PAD_CTL_PKE | \
+ PAD_CTL_HYS )
+
-+enum {
-+ MX51_PAD_DI_GP3__FEC_TX_ER = IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5),
-+ MX51_PAD_DI2_PIN4__FEC_CRS = IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL),
-+ MX51_PAD_DI2_PIN2__FEC_MDC = IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5),
-+ MX51_PAD_DI2_PIN3__FEC_MDIO = IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL),
-+ MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 = IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL),
-+ MX51_PAD_DI_GP4__FEC_RDATA2 = IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL),
-+ MX51_PAD_DISP2_DAT0__FEC_RDATA3 = IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL),
-+ MX51_PAD_DISP2_DAT1__FEC_RX_ER = IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL),
-+ MX51_PAD_DISP2_DAT6__FEC_TDATA1 = IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5),
-+ MX51_PAD_DISP2_DAT7__FEC_TDATA2 = IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5),
-+ MX51_PAD_DISP2_DAT8__FEC_TDATA3 = IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5),
-+ MX51_PAD_DISP2_DAT9__FEC_TX_EN = IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5),
-+ MX51_PAD_DISP2_DAT10__FEC_COL = IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL),
-+ MX51_PAD_DISP2_DAT11__FEC_RX_CLK = IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL),
-+ MX51_PAD_DISP2_DAT12__FEC_RX_DV = IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL),
-+ MX51_PAD_DISP2_DAT13__FEC_TX_CLK = IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4),
-+ MX51_PAD_DISP2_DAT14__FEC_RDATA0 = IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4),
-+ MX51_PAD_DISP2_DAT15__FEC_TDATA0 = IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5),
-+};
-+
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_DI_GP3__FEC_TX_ER, FEC_PAD_CFG),
+ NEW_PAD_CTRL(MX51_PAD_DI2_PIN4__FEC_CRS, FEC_PAD_CFG),
@@ -833,14 +727,6 @@ index 0000000..8ff1381
+int do_mx51_show_dcd_tab(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
-+enum {
-+ MX51_PAD_EIM_SDBA2__EIM_SDBA2 = IOMUX_PAD(0x508, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_SDODT1__EIM_SDODT1 = IOMUX_PAD(0x50C, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_SDODT0__EIM_SDODT0 = IOMUX_PAD(0x510, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_GRP_INDDR = IOMUX_PAD(0x830, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_GRP_HVDDR = IOMUX_PAD(0x870, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_GRP_DDR_SR_A0 = IOMUX_PAD(0x8b0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+};
+ ulong i = 1;
+ struct esdctl_regs *esdctl = (struct esdctl_regs *)ESDCTL_BASE_ADDR;
+ char dcd_item[] = "MXC_DCD_ITEM(%ld, %ld, %#010lX, %#010lX)\n";
diff --git a/patches/u-boot/2014.04/420-apf51-nand-spl-NG.patch b/patches/u-boot/2014.04/420-apf51-nand-spl-NG.patch
index 61826e1..d6b45a8 100644
--- a/patches/u-boot/2014.04/420-apf51-nand-spl-NG.patch
+++ b/patches/u-boot/2014.04/420-apf51-nand-spl-NG.patch
@@ -23,7 +23,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
spl/u-boot-nand-spl.imx: SPL FORCE
--- a/board/armadeus/apf51/apf51_spl.c
+++ b/board/armadeus/apf51/apf51_spl.c
-@@ -0,0 +1,230 @@
+@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2013-2014 Eric Jarrige <eri...@ar...>
+ *
@@ -45,16 +45,6 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+static inline void init_dram(void)
+{
+ struct esdctl_regs *esdctl = (struct esdctl_regs *)ESDCTL_BASE_ADDR;
-+/* PAD MUX ALT INPSE PATH PADCTRL */
-+enum {
-+ MX51_PAD_EIM_SDBA2__EIM_SDBA2 = IOMUX_PAD(0x508, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_SDODT1__EIM_SDODT1 = IOMUX_PAD(0x50C, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_SDODT0__EIM_SDODT0 = IOMUX_PAD(0x510, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_GRP_INDDR = IOMUX_PAD(0x830, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_GRP_HVDDR = IOMUX_PAD(0x870, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_GRP_DDR_SR_A0 = IOMUX_PAD(0x8b0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+};
-+
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS,
+ ACFG_IOMUX_PAD_DRAM_RAS));
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS,
@@ -180,25 +170,6 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+
+void setup_nfc(void)
+{
-+/* PAD MUX ALT INPSE PATH PADCTRL */
-+enum {
-+ MX51_PAD_NANDF_WE_B__NANDF_WE_B = IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_RE_B__NANDF_RE_B = IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_ALE__NANDF_ALE = IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_CLE__NANDF_CLE = IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_WP_B__NANDF_WP_B = IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_RB0__NANDF_RB0 = IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_CS0__NANDF_CS0 = IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D7__NANDF_D7 = IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D6__NANDF_D6 = IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D5__NANDF_D5 = IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D4__NANDF_D4 = IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D3__NANDF_D3 = IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D2__NANDF_D2 = IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D1__NANDF_D1 = IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D0__NANDF_D0 = IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL),
-+};
-+
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_NANDF_WE_B__NANDF_WE_B,
+ PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH));
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_NANDF_RE_B__NANDF_RE_B,
@@ -298,7 +269,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
-@@ -1108,7 +1108,65 @@ void mxc_nand_command(struct mtd_info *m
+@@ -1102,7 +1102,65 @@ void mxc_nand_command(struct mtd_info *m
break;
#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
@@ -365,8 +336,8 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
/* Blocks to be unlocked */
writew(-1, &host->regs->unlockstart_blkaddr);
writew(-1, &host->regs->unlockend_blkaddr);
-@@ -1150,6 +1208,7 @@ void mxc_nand_command(struct mtd_info *m
- writew(readw(&host->regs->nf_wrprst) & ~NFC_WRPR_US, &host->regs->main_area[0][0]);
+@@ -1147,6 +1205,7 @@ void mxc_nand_command(struct mtd_info *m
+ writew(readw(&host->regs->nf_wrprst) & ~NFC_WRPR_US, main_buf);
}
return;
+#endif /* not defined(MXC_NFC_V3_2) */
@@ -375,7 +346,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
--- a/drivers/mtd/nand/mxc_nand.h
+++ b/drivers/mtd/nand/mxc_nand.h
-@@ -207,9 +207,12 @@ struct mxc_nand_ip_regs {
+@@ -191,9 +191,12 @@ struct mxc_nand_ip_regs {
#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
#define NFC_V3_WRPROT_UNLOCK (1 << 2)
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2014-05-08 20:17:21
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via e2d9531d27c689bae736ea88d561d9c0fe0a3b61 (commit)
from c6063746438e96413e1eb18a1cc05547c782228d (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit e2d9531d27c689bae736ea88d561d9c0fe0a3b61
Author: Philippe Reynes <tr...@ya...>
Date: Thu May 8 12:39:35 2014 +0200
[LINUX] 3.14: move to 3.14.3
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf27mainline_defconfig | 4 ++--
buildroot/configs/apf28mainline_defconfig | 4 ++--
buildroot/configs/apf51mainline_defconfig | 4 ++--
...nux-3.14.2.config => apf27-linux-3.14.3.config} | 0
...nux-3.14.2.config => apf28-linux-3.14.3.config} | 0
...nux-3.14.2.config => apf51-linux-3.14.3.config} | 0
patches/linux/{3.14.2 => 3.14.3} | 0
7 files changed, 6 insertions(+), 6 deletions(-)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.14.2.config => apf27-linux-3.14.3.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.14.2.config => apf28-linux-3.14.3.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.14.2.config => apf51-linux-3.14.3.config} (100%)
rename patches/linux/{3.14.2 => 3.14.3} (100%)
diff --git a/buildroot/configs/apf27mainline_defconfig b/buildroot/configs/apf27mainline_defconfig
index 9482145..1edccfa 100644
--- a/buildroot/configs/apf27mainline_defconfig
+++ b/buildroot/configs/apf27mainline_defconfig
@@ -6,7 +6,7 @@ BR2_CCACHE=y
BR2_CCACHE_DIR="$(TOPDIR)/.$(BR2_BOARD_NAME)-buildroot-ccache"
BR2_STRIP_sstrip=y
BR2_KERNEL_HEADERS_VERSION=y
-BR2_DEFAULT_KERNEL_VERSION="3.14.2"
+BR2_DEFAULT_KERNEL_VERSION="3.14.3"
BR2_UCLIBC_CONFIG="target/device/armadeus/uClibc-$(BR2_UCLIBC_VERSION_STRING).config"
BR2_TOOLCHAIN_BUILDROOT_LARGEFILE=y
BR2_TOOLCHAIN_BUILDROOT_INET_IPV6=y
@@ -34,7 +34,7 @@ BR2_BOARD_NAME="apf27"
BR2_CPU_NAME="imx27"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.2"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.3"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/buildroot/configs/apf28mainline_defconfig b/buildroot/configs/apf28mainline_defconfig
index 6b2e57f..14d475b 100644
--- a/buildroot/configs/apf28mainline_defconfig
+++ b/buildroot/configs/apf28mainline_defconfig
@@ -6,7 +6,7 @@ BR2_CCACHE=y
BR2_CCACHE_DIR="$(TOPDIR)/.$(BR2_BOARD_NAME)-buildroot-ccache"
BR2_STRIP_sstrip=y
BR2_KERNEL_HEADERS_VERSION=y
-BR2_DEFAULT_KERNEL_VERSION="3.14.2"
+BR2_DEFAULT_KERNEL_VERSION="3.14.3"
BR2_UCLIBC_CONFIG="target/device/armadeus/uClibc-$(BR2_UCLIBC_VERSION_STRING).config"
BR2_TOOLCHAIN_BUILDROOT_LARGEFILE=y
BR2_TOOLCHAIN_BUILDROOT_INET_IPV6=y
@@ -35,7 +35,7 @@ BR2_CPU_NAME="imx28"
BR2_TARGET_ARMADEUS_SDRAM_SIZE="128"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.2"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.3"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/buildroot/configs/apf51mainline_defconfig b/buildroot/configs/apf51mainline_defconfig
index 783d73e..467de3b 100644
--- a/buildroot/configs/apf51mainline_defconfig
+++ b/buildroot/configs/apf51mainline_defconfig
@@ -7,7 +7,7 @@ BR2_CCACHE=y
BR2_CCACHE_DIR="$(TOPDIR)/.$(BR2_BOARD_NAME)-buildroot-ccache"
BR2_STRIP_sstrip=y
BR2_KERNEL_HEADERS_VERSION=y
-BR2_DEFAULT_KERNEL_VERSION="3.14.2"
+BR2_DEFAULT_KERNEL_VERSION="3.14.3"
BR2_UCLIBC_CONFIG="target/device/armadeus/uClibc-$(BR2_UCLIBC_VERSION_STRING).config"
BR2_TOOLCHAIN_BUILDROOT_LARGEFILE=y
BR2_TOOLCHAIN_BUILDROOT_INET_IPV6=y
@@ -97,7 +97,7 @@ BR2_TARGET_UBOOT_ENVIMAGE_SOURCE="$(ARMADEUS_PATH)/u-boot-env-2013.04.txt"
BR2_TARGET_UBOOT_ENVIMAGE_SIZE="0x20000"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.2"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.3"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.14.2.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.14.3.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.14.2.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.14.3.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.14.2.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.14.3.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.14.2.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.14.3.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.14.2.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.14.3.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.14.2.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.14.3.config
diff --git a/patches/linux/3.14.2 b/patches/linux/3.14.3
similarity index 100%
rename from patches/linux/3.14.2
rename to patches/linux/3.14.3
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2014-05-08 11:31:11
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via c6063746438e96413e1eb18a1cc05547c782228d (commit)
from 7738c667f886fcc458b9c5c3ec40a24146bbb114 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit c6063746438e96413e1eb18a1cc05547c782228d
Author: Eric Jarrige <eri...@ar...>
Date: Thu May 8 13:30:53 2014 +0200
[UBOOT] 2014.04: apf51: cleanup
-----------------------------------------------------------------------
Summary of changes:
patches/u-boot/2014.04/400-imx51.patch | 887 --------------------------------
1 files changed, 0 insertions(+), 887 deletions(-)
diff --git a/patches/u-boot/2014.04/400-imx51.patch b/patches/u-boot/2014.04/400-imx51.patch
index acc3410..9066d23 100644
--- a/patches/u-boot/2014.04/400-imx51.patch
+++ b/patches/u-boot/2014.04/400-imx51.patch
@@ -284,893 +284,6 @@ index 0000000..1c0bf8e
+ + (cs << 2) + ba)
+
+#endif /* __REGS_ESDCTL_H__ */
---- /dev/null
-+++ b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
-@@ -0,0 +1,884 @@
-+/*
-+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__
-+#define __ASM_ARCH_MX5_MX5X_PINS_H__
-+
-+#ifndef __ASSEMBLY__
-+
-+/*
-+ * In order to identify pins more effectively, each mux-controlled pin's
-+ * enumerated value is constructed in the following way:
-+ *
-+ * -------------------------------------------------------------------
-+ * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0
-+ * -------------------------------------------------------------------
-+ * IO_P | IO_I | GPIO_I | PAD_I | MUX_I
-+ * -------------------------------------------------------------------
-+ *
-+ * Bit 0 to 9 contains MUX_I used to identify the register
-+ * offset (0-based. base is IOMUX_module_base) defined in the Section
-+ * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
-+ * similar field definitions are used for the pad control register.
-+ * The IOMUX controller can be split in two parts. At the begeinning,
-+ * there is the register definitions for the multiplexing each pin.
-+ * Then there is a set of registers (PAD_I) to configure each pin
-+ * (pullup, pulldown, etc).
-+ * PAD_I defines the offset of the pad register for each pin.
-+ * GPIO_I defines, if available, the number of gpio that can be
-+ * connected to that pad
-+ * IO_I defines the multiplexer mode required to set the pad in gpio mode
-+ * IO_P defines the gpio structure (gpio1..gpio4) the pad belongs
-+ *
-+ * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
-+ * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
-+ * It means the mux control register is at register offset 0x28. The pad control
-+ * register offset is: 0x250 and also occupy the least significant bits
-+ * within the register.
-+ */
-+
-+/*!
-+ * Starting bit position within each entry of \b iomux_pins to represent the
-+ * MUX control register offset
-+ */
-+#define MUX_I 0
-+/*!
-+ * Starting bit position within each entry of \b iomux_pins to represent the
-+ * PAD control register offset
-+ */
-+#define PAD_I 10
-+/*!
-+ * Starting bit position within each entry of \b iomux_pins to represent which
-+ * mux mode is for GPIO (0-based)
-+ */
-+#define GPIO_I 21
-+
-+#define MUX_IO_P 29
-+#define MUX_IO_I 24
-+#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
-+ GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
-+ ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
-+#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-+
-+#define NON_GPIO_PORT 0x7
-+#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
-+#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
-+#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
-+
-+#define NON_MUX_I PIN_TO_MUX_MASK
-+#define NON_PAD_I PIN_TO_PAD_MASK
-+
-+#if defined(CONFIG_MX51)
-+#define MUX_I_START 0x001C
-+#define PAD_I_START 0x3F0
-+#define INPUT_CTL_START 0x8C4
-+#define MUX_I_END (PAD_I_START - 4)
-+#elif defined(CONFIG_MX53)
-+#define MUX_I_START 0x0020
-+#define PAD_I_START 0x348
-+#define INPUT_CTL_START 0x730
-+#define MUX_I_END (PAD_I_START - 4)
-+#else
-+#error "CPU_TYPE not defined"
-+#endif
-+
-+#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
-+ (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
-+ ((mi) << MUX_I) | \
-+ ((pi - PAD_I_START) << PAD_I) | \
-+ ((ga) << GPIO_I))
-+
-+#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
-+ _MXC_BUILD_PIN(gp, gi, ga, mi, pi)
-+
-+#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
-+ _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
-+
-+#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
-+#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
-+#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
-+#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
-+
-+/*
-+ * This enumeration is constructed based on the Section
-+ * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
-+ * value is constructed based on the rules described above.
-+ */
-+enum {
-+ MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
-+ MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
-+ MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
-+ MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
-+ MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
-+ MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
-+ MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
-+ MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
-+ MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
-+ MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
-+ MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
-+ MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
-+ MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
-+ MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
-+ MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
-+ MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
-+ MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
-+ MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
-+ MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
-+ MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
-+ MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
-+ MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
-+ MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
-+ MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
-+ MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
-+ MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
-+ MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
-+ MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
-+ MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
-+ MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
-+ MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
-+ MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
-+ MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
-+ MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
-+ MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
-+ MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
-+ MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
-+ MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
-+ MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
-+ MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
-+ MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
-+ MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
-+ MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
-+ MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
-+ MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
-+ MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
-+ MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
-+ MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
-+ MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
-+ MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
-+ MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
-+ MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
-+ MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
-+ MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
-+ MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
-+ MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
-+ MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
-+ MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
-+ MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
-+ MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
-+ MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
-+ MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
-+ MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
-+ MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
-+ MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
-+ MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
-+ MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
-+ MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
-+ MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514),
-+ MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
-+ MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
-+ MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
-+ MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
-+ MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
-+ MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
-+ MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
-+ MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
-+ MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
-+ MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
-+ MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
-+ MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
-+ MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
-+ MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
-+ MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
-+ MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
-+ MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
-+ MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
-+ MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
-+ MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
-+ MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
-+ MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
-+ MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
-+ MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
-+ MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
-+ MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
-+ MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
-+ MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
-+ MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
-+ MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
-+ MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
-+ MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
-+ MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
-+ MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
-+ MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
-+ MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
-+ MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
-+ MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
-+ MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
-+ MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
-+ MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
-+ MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC),
-+ MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0),
-+ MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
-+ MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
-+ MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
-+ MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
-+ MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
-+ MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4),
-+ MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8),
-+ MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC),
-+ MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0),
-+ MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
-+ MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
-+ MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
-+ MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
-+ MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
-+ MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
-+ MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
-+ MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
-+ MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
-+ MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
-+ MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
-+ MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
-+ MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
-+ MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
-+ MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
-+ MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
-+ MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
-+ MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
-+ MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
-+ MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
-+ MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
-+ MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
-+ MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
-+ MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
-+ MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
-+ MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
-+ MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
-+ MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
-+ MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
-+ MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
-+ MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
-+ MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
-+ MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
-+ MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
-+ MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
-+ MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
-+ MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
-+ MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
-+ MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
-+ MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
-+ MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
-+ MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
-+ MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
-+ MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
-+ MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
-+ MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
-+ MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
-+ MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
-+ MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
-+ MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
-+ MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
-+ MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
-+ MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
-+ MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
-+ MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
-+ MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
-+ MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
-+ MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
-+ MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
-+ MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
-+ MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
-+ MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
-+ MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
-+ MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
-+ MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
-+ MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
-+ MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
-+ MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
-+ MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
-+ MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
-+ MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
-+ MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
-+ MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
-+ MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
-+ MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
-+ MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
-+ MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
-+ MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
-+ MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
-+ MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
-+ MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
-+ MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
-+ MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
-+ MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
-+ MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
-+ MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
-+ MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
-+ MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
-+ MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
-+ MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
-+ MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
-+ MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
-+ MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
-+ MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
-+ MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
-+ MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
-+ MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
-+ MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
-+ MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
-+ MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
-+ MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
-+ MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
-+ MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
-+ MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788),
-+ MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
-+ MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
-+ MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
-+ MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
-+ MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
-+ MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
-+ MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
-+ MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
-+ MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
-+ MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
-+ MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
-+ MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
-+ MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
-+ MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
-+ MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
-+ MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
-+ MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
-+ MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
-+ MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
-+ MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
-+ MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
-+ MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
-+ MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
-+ MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
-+ MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
-+ MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
-+ MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
-+
-+ /* The following are PADS used for drive strength */
-+
-+ MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820),
-+ MX51_PIN_CTL_GRP_INDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x830),
-+ MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838),
-+ MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890),
-+ MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C),
-+ MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C),
-+ MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884),
-+ MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C),
-+ MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864),
-+ MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C),
-+ MX51_PIN_CTL_GRP_HVDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x870),
-+ MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874),
-+ MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878),
-+ MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880),
-+ MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C),
-+ MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C),
-+ MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4),
-+ MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC),
-+ MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8),
-+ MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C),
-+ MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0),
-+ MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0),
-+ MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4),
-+ MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC),
-+ MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C),
-+ MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848),
-+ MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868),
-+ MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4),
-+ MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8),
-+ MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac),
-+ MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0),
-+ MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4),
-+ MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8),
-+ MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC),
-+ MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0),
-+ MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4),
-+ MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8),
-+ MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC),
-+ MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0),
-+ MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4),
-+ MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8),
-+ MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC),
-+ MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
-+ MX51_PIN_CTL_PAD_EIM_SDBA2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x508),
-+ MX51_PIN_CTL_PAD_EIM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x50C),
-+ MX51_PIN_CTL_PAD_EIM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x510),
-+};
-+
-+enum {
-+ MX53_PIN_GPIO_19 = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348),
-+ MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C),
-+ MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350),
-+ MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354),
-+ MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358),
-+ MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C),
-+ MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360),
-+ MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364),
-+ MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368),
-+ MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C),
-+ MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370),
-+ MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374),
-+ MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378),
-+ MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C),
-+ MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380),
-+ MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384),
-+ MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388),
-+ MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C),
-+ MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390),
-+ MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394),
-+ MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398),
-+ MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C),
-+ MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0),
-+ MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4),
-+ MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8),
-+ MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC),
-+ MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0),
-+ MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4),
-+ MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8),
-+ MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC),
-+ MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0),
-+ MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4),
-+ MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8),
-+ MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC),
-+ MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0),
-+ MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4),
-+ MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8),
-+ MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC),
-+ MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0),
-+ MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4),
-+ MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8),
-+ MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC),
-+ MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0),
-+ MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4),
-+ MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8),
-+ MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC),
-+ MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400),
-+ MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404),
-+ MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408),
-+ MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C),
-+ MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410),
-+ MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414),
-+ MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418),
-+ MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C),
-+ MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420),
-+ MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424),
-+ MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428),
-+ MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C),
-+ MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430),
-+ MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434),
-+ MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438),
-+ MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C),
-+ MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440),
-+ MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444),
-+ MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448),
-+ MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C),
-+ MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450),
-+ MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454),
-+ MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458),
-+ MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C),
-+ MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460),
-+ MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464),
-+ MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468),
-+ MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C),
-+ MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470),
-+ MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474),
-+ MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478),
-+ MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C),
-+ MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480),
-+ MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484),
-+ MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488),
-+ MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C),
-+ MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490),
-+ MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494),
-+ MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498),
-+ MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C),
-+ MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0),
-+ MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4),
-+ MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8),
-+ MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC),
-+ MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0),
-+ MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4),
-+ MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8),
-+ MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC),
-+ MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0),
-+ MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4),
-+ MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8),
-+ MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC),
-+ MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0),
-+ MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4),
-+ MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8),
-+ MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC),
-+ MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0),
-+ MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4),
-+ MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8),
-+ MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC),
-+ MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0),
-+ MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4),
-+ MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8),
-+ MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC),
-+ MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500),
-+ MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504),
-+ MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508),
-+ MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C),
-+ MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510),
-+ MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514),
-+ MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518),
-+ MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C),
-+ MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520),
-+ MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524),
-+ MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528),
-+ MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C),
-+ MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530),
-+ MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534),
-+ MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538),
-+ MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C),
-+ MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I),
-+ MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I),
-+ MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I),
-+ MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I),
-+ MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I),
-+ MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I),
-+ MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I),
-+ MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I),
-+ MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I),
-+ MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I),
-+ MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540),
-+ MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544),
-+ MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548),
-+ MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C),
-+ MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550),
-+ MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554),
-+ MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558),
-+ MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C),
-+ MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560),
-+ MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564),
-+ MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568),
-+ MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C),
-+ MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570),
-+ MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574),
-+ MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578),
-+ MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C),
-+ MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580),
-+ MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584),
-+ MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588),
-+ MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C),
-+ MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590),
-+ MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594),
-+ MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598),
-+ MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C),
-+ MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0),
-+ MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4),
-+ MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8),
-+ MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC),
-+ MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0),
-+ MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4),
-+ MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8),
-+ MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC),
-+ MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0),
-+ MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4),
-+ MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8),
-+ MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC),
-+ MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0),
-+ MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4),
-+ MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8),
-+ MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC),
-+ MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0),
-+ MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4),
-+ MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8),
-+ MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC),
-+ MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0),
-+ MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4),
-+ MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8),
-+ MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC),
-+ MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600),
-+ MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604),
-+ MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608),
-+ MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C),
-+ MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610),
-+ MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614),
-+ MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618),
-+ MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C),
-+ MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620),
-+ MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624),
-+ MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628),
-+ MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C),
-+ MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630),
-+ MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634),
-+ MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638),
-+ MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C),
-+ MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640),
-+ MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644),
-+ MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648),
-+ MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C),
-+ MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650),
-+ MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654),
-+ MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658),
-+ MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C),
-+ MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660),
-+ MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664),
-+ MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668),
-+ MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C),
-+ MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670),
-+ MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674),
-+ MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678),
-+ MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C),
-+ MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680),
-+ MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684),
-+ MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688),
-+ MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C),
-+ MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690),
-+ MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694),
-+ MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698),
-+ MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C),
-+ MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0),
-+ MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4),
-+ MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8),
-+ MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC),
-+ MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0),
-+ MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4),
-+ MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8),
-+ MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC),
-+ MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0),
-+ MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4),
-+ MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8),
-+ MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC),
-+ MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0),
-+ MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4),
-+ MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8),
-+ MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC),
-+ MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0),
-+ MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4),
-+ MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8),
-+ MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC),
-+ MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0),
-+ MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4),
-+ MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC),
-+ MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708),
-+ MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C),
-+ MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710),
-+ MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714),
-+ MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718),
-+ MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C),
-+ MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720),
-+ MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724),
-+ MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728),
-+ MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C),
-+};
-+/* various IOMUX input select register index */
-+typedef enum iomux_input_select {
-+ MX51_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
-+ MX51_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
-+ MX51_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
-+ MX51_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
-+ MX51_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
-+ MX51_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
-+ MX51_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
-+ MX51_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
-+ MX51_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
-+ MX51_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
-+ MX51_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
-+ MX51_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
-+ MX51_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
-+ MX51_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
-+ MX51_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
-+ MX51_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
-+ MX51_CCM_IPP_DI_CLK_SELECT_INPUT,
-+ /* TO2 */
-+ MX51_CCM_IPP_DI1_CLK_SELECT_INPUT,
-+ MX51_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
-+ MX51_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
-+ MX51_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
-+ MX51_CSPI_IPP_IND_MISO_SELECT_INPUT,
-+ MX51_CSPI_IPP_IND_MOSI_SELECT_INPUT,
-+ MX51_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
-+ MX51_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
-+ MX51_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
-+ MX51_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
-+ /* TO2 */
-+ MX51_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
-+ MX51_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
-+ MX51_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
-+ MX51_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
-+ MX51_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
-+ MX51_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
-+ MX51_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
-+ MX51_FEC_FEC_COL_SELECT_INPUT,
-+ MX51_FEC_FEC_CRS_SELECT_INPUT,
-+ MX51_FEC_FEC_MDI_SELECT_INPUT,
-+ MX51_FEC_FEC_RDATA_0_SELECT_INPUT,
-+ MX51_FEC_FEC_RDATA_1_SELECT_INPUT,
-+ MX51_FEC_FEC_RDATA_2_SELECT_INPUT,
-+ MX51_FEC_FEC_RDATA_3_SELECT_INPUT,
-+ MX51_FEC_FEC_RX_CLK_SELECT_INPUT,
-+ MX51_FEC_FEC_RX_DV_SELECT_INPUT,
-+ MX51_FEC_FEC_RX_ER_SELECT_INPUT,
-+ MX51_FEC_FEC_TX_CLK_SELECT_INPUT,
-+ MX51_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
-+ MX51_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
-+ MX51_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
-+ MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
-+ MX51_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
-+ MX51_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
-+ MX51_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
-+ MX51_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
-+ /* TO2 */
-+ MX51_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
-+ MX51_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
-+ MX51_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
-+ /* TO2 */
-+ MX51_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
-+ /* TO2 */
-+ MX51_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
-+ MX51_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
-+ MX51_I2C1_IPP_SCL_IN_SELECT_INPUT,
-+ MX51_I2C1_IPP_SDA_IN_SELECT_INPUT,
-+ MX51_I2C2_IPP_SCL_IN_SELECT_INPUT,
-+ MX51_I2C2_IPP_SDA_IN_SELECT_INPUT,
-+ MX51_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
-+ MX51_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
-+ MX51_KPP_IPP_IND_COL_6_SELECT_INPUT,
-+ MX51_KPP_IPP_IND_COL_7_SELECT_INPUT,
-+ MX51_KPP_IPP_IND_ROW_4_SELECT_INPUT,
-+ MX51_KPP_IPP_IND_ROW_5_SELECT_INPUT,
-+ MX51_KPP_IPP_IND_ROW_6_SELECT_INPUT,
-+ MX51_KPP_IPP_IND_ROW_7_SELECT_INPUT,
-+ MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
-+ MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
-+ MX51_UART2_IPP_UART_RTS_B_SELECT_INPUT,
-+ MX51_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
-+ MX51_UART3_IPP_UART_RTS_B_SELECT_INPUT,
-+ MX51_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
-+ MX51_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
-+ MX51_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
-+ MX51_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
-+ MX51_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
-+ MX51_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
-+ MX51_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
-+ MX51_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
-+ MX51_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
-+ MX51_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
-+ MX51_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
-+ MX51_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
-+ MX51_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
-+ MX51PUT_NUM_MUX,
-+ /* MX53 */
-+ MX53_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
-+ MX53_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
-+ MX53_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
-+ MX53_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
-+ MX53_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
-+ MX53_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
-+ MX53_AUDMUX_P5_INPUT_DA_AMX_SELECT_I,
-+ MX53_AUDMUX_P5_INPUT_DB_AMX_SELECT_I,
-+ MX53_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
-+ MX53_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT,
-+ MX53_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
-+ MX53_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
-+ MX53_CAN1_IPP_IND_CANRX_SELECT_INPUT,
-+ MX53_CAN2_IPP_IND_CANRX_SELECT_INPUT,
-+ MX53_CCM_IPP_ASRC_EXT_SELECT_INPUT,
-+ MX53_CCM_IPP_DI1_CLK_SELECT_INPUT,
-+ MX53_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
-+ MX53_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
-+ MX53_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
-+ MX53_CCM_PLL4_BYPASS_CLK_SELECT_INPUT,
-+ MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
-+ MX53_CSPI_IPP_IND_MISO_SELECT_INPUT,
-+ MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT,
-+ MX53_CSPI_IPP_IND_SS_B_0_SELECT_INPUT,
-+ MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
-+ MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
-+ MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
-+ MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
-+ MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
-+ MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
-+ MX53_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT,
-+ MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
-+ MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
-+ MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT,
-+ MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
-+ MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
-+ MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
-+ MX53_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT,
-+ MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
-+ MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT,
-+ MX53_ESAI1_IPP_IND_FST_SELECT_INPUT,
-+ MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
-+ MX53_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
-+ MX53_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
-+ MX53_ESAI1_IPP_IND_SCKT_SELECT_INPUT,
-+ MX53_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
-+ MX53_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
-+ MX53_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
-+ MX53_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
-+ MX53_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
-+ MX53_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
-+ MX53_ESDHC1_IPP_WP_ON_SELECT_INPUT,
-+ MX53_FEC_FEC_COL_SELECT_INPUT,
-+ MX53_FEC_FEC_MDI_SELECT_INPUT,
-+ MX53_FEC_FEC_RX_CLK_SELECT_INPUT,
-+ MX53_FIRI_IPP_IND_RXD_SELECT_INPUT,
-+ MX53_GPC_PMIC_RDY_SELECT_INPUT,
-+ MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
-+ MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
-+ MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
-+ MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
-+ MX53_I2C3_IPP_SCL_IN_SELECT_INPUT,
-+ MX53_I2C3_IPP_SDA_IN_SELECT_INPUT,
-+ MX53_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
-+ MX53_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
-+ MX53_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
-+ MX53_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT,
-+ MX53_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT,
-+ MX53_KPP_IPP_IND_COL_5_SELECT_INPUT,
-+ MX53_KPP_IPP_IND_COL_6_SELECT_INPUT,
-+ MX53_KPP_IPP_IND_COL_7_SELECT_INPUT,
-+ MX53_KPP_IPP_IND_ROW_5_SELECT_INPUT,
-+ MX53_KPP_IPP_IND_ROW_6_SELECT_INPUT,
-+ MX53_KPP_IPP_IND_ROW_7_SELECT_INPUT,
-+ MX53_MLB_MLBCLK_IN_SELECT_INPUT,
-+ MX53_MLB_MLBDAT_IN_SELECT_INPUT,
-+ MX53_MLB_MLBSIG_IN_SELECT_INPUT,
-+ MX53_OWIRE_BATTERY_LINE_IN_SELECT_INPUT,
-+ MX53_SDMA_EVENTS_14_SELECT_INPUT,
-+ MX53_SDMA_EVENTS_15_SELECT_INPUT,
-+ MX53_SPDIF_SPDIF_IN1_SELECT_INPUT,
-+ MX53_UART1_IPP_UART_RTS_B_SELECT_INPUT,
-+ MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
-+ MX53_UART2_IPP_UART_RTS_B_SELECT_INPUT,
-+ MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
-+ MX53_UART3_IPP_UART_RTS_B_SELECT_INPUT,
-+ MX53_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
-+ MX53_UART4_IPP_UART_RTS_B_SELECT_INPUT,
-+ MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
-+ MX53_UART5_IPP_UART_RTS_B_SELECT_INPUT,
-+ MX53_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
-+ MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT,
-+ MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT,
-+ MX53_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT,
-+} iomux_input_select_t;
-+
-+#endif /* __ASSEMBLY__ */
-+#endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */
--
1.7.2.5
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2014-05-08 11:21:31
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 7738c667f886fcc458b9c5c3ec40a24146bbb114 (commit)
from c44a8f7b92de3932cad4d1b686b92a78ebd1d0fa (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 7738c667f886fcc458b9c5c3ec40a24146bbb114
Author: Eric Jarrige <eri...@ar...>
Date: Thu May 8 13:21:11 2014 +0200
[UBOOT] 2014.04: apf51: add board configuration
-----------------------------------------------------------------------
Summary of changes:
...f51-u-boot-2013.04.h => apf51-u-boot-2014.04.h} | 150 ++++++++++----------
1 files changed, 78 insertions(+), 72 deletions(-)
copy buildroot/target/device/armadeus/apf51/{apf51-u-boot-2013.04.h => apf51-u-boot-2014.04.h} (88%)
diff --git a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2013.04.h b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2014.04.h
similarity index 88%
copy from buildroot/target/device/armadeus/apf51/apf51-u-boot-2013.04.h
copy to buildroot/target/device/armadeus/apf51/apf51-u-boot-2014.04.h
index 79440f1..b42dc59 100644
--- a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2013.04.h
+++ b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2014.04.h
@@ -35,27 +35,32 @@
* SPL
*/
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
#define CONFIG_SPL_MAX_SIZE 0x4000 /* can be extended to 128kiB */
/* CONFIG_SPL_TEXT_BASE -> IRAM start address available for SPL :
* - 0x1FFE0000 IRAM base address
* - 0x00002000 IRAM space reserved for IPL
- * - 0x00000800 size of SPL DCD header
+ * - 0x00002000 reserve space SPL DCD & header
*/
-#define CONFIG_SPL_TEXT_BASE 0x1FFE2800
+#define CONFIG_SPL_TEXT_BASE 0x1FFE4000
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_RAM_ADDR \
+ CONFIG_SYS_INIT_RAM_SIZE \
- - 0x80000 /* MMU and IPL stack */
+ - 0xC000 /* MMU and IPL stack */
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_RAM_DEVICE
+
/* NAND boot config */
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_MONITOR_OFFSET
+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_LOAD_ADDR
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
/*
@@ -120,7 +125,7 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#define CONFIG_SYS_TEXT_BASE 0x90004000
+#define CONFIG_SYS_TEXT_BASE 0x90004040
/*
* FLASH organization
@@ -391,7 +396,7 @@
*/
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_SYS_PHY_RESET_GPIO IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11)
+#define CONFIG_SYS_PHY_RESET_GPIO IMX_GPIO_NR(3, 0)
#define CONFIG_FEC_MXC_PHYADDR 0x02
#define CONFIG_MII
@@ -410,13 +415,13 @@
#define CONFIG_SYS_FPGA_CHECK_ERROR
/* FPGA program pin configuration */
-#define ACFG_FPGA_PWR MX51_PIN_DI1_D0_CS
-#define ACFG_FPGA_PRG MX51_PIN_CSI2_D12
+#define ACFG_FPGA_PWR IMX_GPIO_NR(3, 3)
+#define ACFG_FPGA_PRG IMX_GPIO_NR(4, 9)
#define ACFG_FPGA_RDATA CS1_BASE_ADDR
#define ACFG_FPGA_WDATA CS1_BASE_ADDR
-#define ACFG_FPGA_INIT MX51_PIN_CSI2_D18
-#define ACFG_FPGA_DONE MX51_PIN_CSI2_D13
-#define ACFG_FPGA_SUSPEND MX51_PIN_DISPB2_SER_DIO
+#define ACFG_FPGA_INIT IMX_GPIO_NR(4, 11)
+#define ACFG_FPGA_DONE IMX_GPIO_NR(4, 10)
+#define ACFG_FPGA_SUSPEND IMX_GPIO_NR(3, 6)
#define ACFG_FPGA_GCR1_VALUE 0x019100bf
#define ACFG_FPGA_GCR2_VALUE 0x00000000
@@ -439,6 +444,8 @@
* I2C
*/
#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
@@ -467,8 +474,8 @@
/*
* Watchdog Config
*/
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_IMX_WATCHDOG
+/*#define CONFIG_HW_WATCHDOG
+#define CONFIG_IMX_WATCHDOG*/
/*
* USB
*/
@@ -476,7 +483,6 @@
/*
* Clocks
*/
-#define CONFIG_SYS_HZ 1000 /* Ticks per second */
#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_SYS_MX5_HCLK 1024*CONFIG_SYS_MX5_CLK32
#define CONFIG_MX51_PLL_ERRATA
@@ -672,89 +678,89 @@
#define ACFG_SDRAM_ESDCDLY5_REGISTER_VAL 0x00F48000
/* SDRAM IO Muxing */
-#define ACFG_IOMUX_PAD_DRAM_RAS PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
-#define ACFG_IOMUX_PAD_DRAM_CAS PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+#define ACFG_IOMUX_PAD_DRAM_RAS PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
+#define ACFG_IOMUX_PAD_DRAM_CAS PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_SDWE \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_SDCKE0 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_SDCKE1 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_SDCLK \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_SDQS0 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PD \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_SDQS1 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PD \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_SDQS2 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PD \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_SDQS3 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PD \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_CS0 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_CS1 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_DQM0 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_DQM1 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_DQM2 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_DQM3 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_EIM_SDBA2 \
- PAD_CTL_DRV_VOT_LOW+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
- +PAD_CTL_100K_PU
+ PAD_CTL_DVS | PAD_CTL_PKE | PAD_CTL_PUE \
+ | PAD_CTL_PUS_100K_UP
#define ACFG_IOMUX_PAD_EIM_SDODT1 \
- PAD_CTL_DRV_VOT_LOW+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
- +PAD_CTL_100K_PD+PAD_CTL_DRV_LOW+PAD_CTL_SRE_FAST
+ PAD_CTL_DVS | PAD_CTL_PKE | PAD_CTL_PUE \
+ | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_LOW | PAD_CTL_SRE_FAST
#define ACFG_IOMUX_PAD_EIM_SDODT0 \
- PAD_CTL_DRV_VOT_LOW+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
- +PAD_CTL_100K_PD+PAD_CTL_DRV_LOW+PAD_CTL_SRE_FAST
-
-#define ACFG_IOMUX_GRP_DDRPKS PAD_CTL_PUE_PULL /* imx default */
-#define ACFG_IOMUX_GRP_DRAM_B4 PAD_CTL_DRV_MAX
-#define ACFG_IOMUX_GRP_INDDR PAD_CTL_DDR_INPUT_CMOS /* imx default */
-#define ACFG_IOMUX_GRP_PKEDDR PAD_CTL_PKE_ENABLE /* imx default */
-#define ACFG_IOMUX_GRP_DDR_A0 PAD_CTL_DRV_MAX
-#define ACFG_IOMUX_GRP_DDR_A1 PAD_CTL_DRV_MAX
-#define ACFG_IOMUX_GRP_DDRAPUS PAD_CTL_100K_PU /* imx default */
-#define ACFG_IOMUX_GRP_HYSDDR0 PAD_CTL_HYS_NONE /* imx default */
-#define ACFG_IOMUX_GRP_HYSDDR1 PAD_CTL_HYS_NONE /* imx default */
-#define ACFG_IOMUX_GRP_HYSDDR2 PAD_CTL_HYS_NONE /* imx default */
-#define ACFG_IOMUX_GRP_HVDDR PAD_CTL_DRV_VOT_LOW
-#define ACFG_IOMUX_GRP_HYSDDR3 PAD_CTL_HYS_NONE /* imx default */
+ PAD_CTL_DVS | PAD_CTL_PKE | PAD_CTL_PUE \
+ | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_LOW | PAD_CTL_SRE_FAST
+
+#define ACFG_IOMUX_GRP_DDRPKS PAD_CTL_PUE /* imx default */
+#define ACFG_IOMUX_GRP_DRAM_B4 PAD_CTL_DSE_MAX
+#define ACFG_IOMUX_GRP_INDDR 0 /* imx default */
+#define ACFG_IOMUX_GRP_PKEDDR PAD_CTL_PKE /* imx default */
+#define ACFG_IOMUX_GRP_DDR_A0 PAD_CTL_DSE_MAX
+#define ACFG_IOMUX_GRP_DDR_A1 PAD_CTL_DSE_MAX
+#define ACFG_IOMUX_GRP_DDRAPUS PAD_CTL_PUS_100K_UP /* imx default */
+#define ACFG_IOMUX_GRP_HYSDDR0 0 /* imx default */
+#define ACFG_IOMUX_GRP_HYSDDR1 0 /* imx default */
+#define ACFG_IOMUX_GRP_HYSDDR2 0 /* imx default */
+#define ACFG_IOMUX_GRP_HVDDR PAD_CTL_DVS
+#define ACFG_IOMUX_GRP_HYSDDR3 0 /* imx default */
#define ACFG_IOMUX_GRP_DDR_SR_B0 PAD_CTL_SRE_SLOW
-#define ACFG_IOMUX_GRP_DDRAPKS PAD_CTL_PUE_PULL /* imx default */
+#define ACFG_IOMUX_GRP_DDRAPKS PAD_CTL_PUE /* imx default */
#define ACFG_IOMUX_GRP_DDR_SR_B1 PAD_CTL_SRE_SLOW
-#define ACFG_IOMUX_GRP_DDRPUS PAD_CTL_100K_PU /* imx default */
+#define ACFG_IOMUX_GRP_DDRPUS PAD_CTL_PUS_100K_UP /* imx default */
#define ACFG_IOMUX_GRP_DDR_SR_B2 PAD_CTL_SRE_SLOW
-#define ACFG_IOMUX_GRP_PKEADDR PAD_CTL_PKE_ENABLE /* imx default */
+#define ACFG_IOMUX_GRP_PKEADDR PAD_CTL_PKE /* imx default */
#define ACFG_IOMUX_GRP_DDR_SR_B4 PAD_CTL_SRE_SLOW
-#define ACFG_IOMUX_GRP_INMODE1 PAD_CTL_DDR_INPUT_CMOS /* imx default */
-#define ACFG_IOMUX_GRP_DRAM_B0 PAD_CTL_DRV_MAX
-#define ACFG_IOMUX_GRP_DRAM_B1 PAD_CTL_DRV_MAX
+#define ACFG_IOMUX_GRP_INMODE1 0 /* imx default */
+#define ACFG_IOMUX_GRP_DRAM_B0 PAD_CTL_DSE_MAX
+#define ACFG_IOMUX_GRP_DRAM_B1 PAD_CTL_DSE_MAX
#define ACFG_IOMUX_GRP_DDR_SR_A0 PAD_CTL_SRE_SLOW
-#define ACFG_IOMUX_GRP_DRAM_B2 PAD_CTL_DRV_MAX
+#define ACFG_IOMUX_GRP_DRAM_B2 PAD_CTL_DSE_MAX
#define ACFG_IOMUX_GRP_DDR_SR_A1 PAD_CTL_SRE_SLOW
/* end of SDRAM IO Muxing */
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2014-05-08 11:19:21
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via c44a8f7b92de3932cad4d1b686b92a78ebd1d0fa (commit)
from ad1ef8252c2900310adc0d07fd43f4f69c7fb0bf (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit c44a8f7b92de3932cad4d1b686b92a78ebd1d0fa
Author: Eric Jarrige <eri...@ar...>
Date: Thu May 8 13:18:59 2014 +0200
[UBOOT] 2014.04: add apf51 patchwork
-----------------------------------------------------------------------
Summary of changes:
patches/u-boot/2014.04/400-imx51.patch | 1176 +++++++++++++++++
patches/u-boot/2014.04/401-apf51.patch | 1339 ++++++++++++++++++++
.../u-boot/{2013.04 => 2014.04}/410-imx-iim.patch | 107 +--
patches/u-boot/2014.04/420-apf51-nand-spl-NG.patch | 399 ++++++
4 files changed, 2945 insertions(+), 76 deletions(-)
create mode 100644 patches/u-boot/2014.04/400-imx51.patch
create mode 100644 patches/u-boot/2014.04/401-apf51.patch
copy patches/u-boot/{2013.04 => 2014.04}/410-imx-iim.patch (76%)
create mode 100644 patches/u-boot/2014.04/420-apf51-nand-spl-NG.patch
diff --git a/patches/u-boot/2014.04/400-imx51.patch b/patches/u-boot/2014.04/400-imx51.patch
new file mode 100644
index 0000000..acc3410
--- /dev/null
+++ b/patches/u-boot/2014.04/400-imx51.patch
@@ -0,0 +1,1176 @@
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+---
+ arch/arm/cpu/armv7/cpu.c
+ arch/arm/cpu/armv7/mx5/lowlevel_init.S
+ arch/arm/include/asm/arch-mx5/imx-regs.h
+ arch/arm/include/asm/arch-mx5/mx5x_pins.h
+ arch/arm/include/asm/arch-mx5/regs_esdctl.h
+
+diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
+index 39a8023..c8c2293 100644
+--- a/arch/arm/cpu/armv7/cpu.c
++++ b/arch/arm/cpu/armv7/cpu.c
+@@ -82,5 +82,9 @@ int cleanup_before_linux(void)
+ */
+ cpu_cache_initialization();
+
++#ifndef CONFIG_L2_OFF
++/* v7_outer_cache_enable();*/
++#endif
++
+ return 0;
+ }
+diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+index a40b84f..1ca9b22 100644
+--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
++++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+@@ -24,6 +24,34 @@
+ #include <generated/asm-offsets.h>
+ #include <linux/linkage.h>
+
++#ifndef CONFIG_SYS_PLL_DP_CTL
++/* use internal oscillator */
++#define CONFIG_SYS_PLL_DP_CTL 0x00001232
++#endif
++
++#ifndef CONFIG_SYS_CLKCTL_CCSR
++/* use internal oscillator */
++#define CONFIG_SYS_CLKCTL_CCSR 0x00000000
++#endif
++
++#ifndef CONFIG_SYS_CLKTL_CBCDR
++#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
++#endif
++
++#ifndef CONFIG_SYS_CLKTL_CBCMR
++/* Use lp_apm (24MHz) source for perclk */
++#define CONFIG_SYS_CLKTL_CBCMR 0x000020C2
++#endif
++
++#ifndef CONFIG_SYS_CLKTL_CSCDR1
++#define CONFIG_SYS_CLKTL_CSCDR1 0x00C30321
++#endif
++
++#ifndef CONFIG_SYS_CLKTL_CBCMR1
++/* Use PLL 2 for UART's, get 66.5MHz from it */
++#define CONFIG_SYS_CLKTL_CBCMR1 0xA5A2A020
++#endif
++
+ .section ".text.init", "x"
+
+ .macro init_arm_erratum
+@@ -114,7 +142,7 @@
+ #define W_DP_MFN 8
+
+ setup_pll_func:
+- ldr r1, =0x00001232
++ ldr r1, =CONFIG_SYS_PLL_DP_CTL
+ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+ mov r1, #0x2
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+@@ -131,7 +159,7 @@
+ str r1, [r0, #PLL_DP_MFN]
+ str r1, [r0, #PLL_DP_HFS_MFN]
+
+- ldr r1, =0x00001232
++ ldr r1, =CONFIG_SYS_PLL_DP_CTL
+ str r1, [r0, #PLL_DP_CTL]
+ 1: ldr r1, [r0, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+@@ -143,7 +171,7 @@
+ .macro setup_pll_errata pll, freq
+ ldr r2, =\pll
+ str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
+- ldr r1, =0x00001236
++ ldr r1, =CONFIG_SYS_PLL_DP_CTL | 0x04
+ str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
+ 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
+ ands r1, r1, #0x1
+@@ -172,6 +200,16 @@
+ #if defined (CONFIG_MX51)
+ ldr r0, =CCM_BASE_ADDR
+
++#ifdef CONFIG_SYS_CLKCTL_CCMR
++ ldr r1, =CONFIG_SYS_CLKCTL_CCMR
++ str r1, [r0, #CLKCTL_CCMR]
++
++ /* make sure clocks are ready */
++1: ldr r1, [r0, #CLKCTL_CSR]
++ cmp r1, #CONFIG_SYS_CLKCTL_CSR
++ bne 1b
++#endif
++
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+@@ -199,7 +237,7 @@
+ bne 1b
+
+ /* Switch ARM to step clock */
+- mov r1, #0x4
++ mov r1, #CONFIG_SYS_CLKCTL_CCSR | 0x04
+ str r1, [r0, #CLKCTL_CCSR]
+
+ #if defined(CONFIG_MX51_PLL_ERRATA)
+@@ -244,13 +282,14 @@
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1 */
++ mov r1, #CONFIG_SYS_CLKCTL_CCSR
+- str r4, [r0, #CLKCTL_CCSR]
++ str r1, [r0, #CLKCTL_CCSR]
+
+ /* setup the rest */
+- /* Use lp_apm (24MHz) source for perclk */
+- ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
++ /* select source for perclk */
++ ldr r1, =CONFIG_SYS_CLKTL_CBCMR | CONFIG_SYS_DDR_CLKSEL
+ str r1, [r0, #CLKCTL_CBCMR]
+- /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
++ /* ddr clock from PLL 1 */
+ ldr r1, =CONFIG_SYS_CLKTL_CBCDR
+ str r1, [r0, #CLKCTL_CBCDR]
+
+@@ -265,9 +304,9 @@
+ str r1, [r0, #CLKCTL_CCGR6]
+
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+- ldr r1, =0xA5A2A020
++ ldr r1, =CONFIG_SYS_CLKTL_CBCMR1
+ str r1, [r0, #CLKCTL_CSCMR1]
+- ldr r1, =0x00C30321
++ ldr r1, =CONFIG_SYS_CLKTL_CSCDR1
+ str r1, [r0, #CLKCTL_CSCDR1]
+ /* make sure divider effective */
+ 1: ldr r1, [r0, #CLKCTL_CDHIPR]
+diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
+index 46017f4..520bf98 100644
+--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
++++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
+@@ -267,6 +267,7 @@
+ #define M4IF_FBPM0 0x40
+ #define M4IF_FIDBP 0x48
+
++#ifndef DP_OP_800
+ /* Assuming 24MHz input clock with doubler ON */
+ /* MFI PDF */
+ #define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
+@@ -305,6 +306,7 @@
+ #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
+ #define DP_MFD_216 (4 - 1)
+ #define DP_MFN_216 3
++#endif /* DP_OP_800 */
+
+ #define CHIP_REV_1_0 0x10
+ #define CHIP_REV_1_1 0x11
+diff --git a/arch/arm/include/asm/arch-mx5/regs_esdctl.h b/arch/arm/include/asm/arch-mx5/regs_esdctl.h
+new file mode 100644
+index 0000000..1c0bf8e
+--- /dev/null
++++ b/arch/arm/include/asm/arch-mx5/regs_esdctl.h
+@@ -0,0 +1,114 @@
++/*
++ * Copyright (C) 2012 Eric Jarrige <eri...@ar...>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++
++#ifndef __REGS_ESDCTL_H__
++#define __REGS_ESDCTL_H__
++
++
++#ifndef __ASSEMBLY__
++/* ESDCTL registers */
++#if defined(CONFIG_MX51)
++struct esdctl_regs {
++ u32 esdctl0;
++ u32 esdcfg0;
++ u32 esdctl1;
++ u32 esdcfg1;
++ u32 esdmisc;
++ u32 esdscr;
++ u32 reserved[2];
++ u32 esdcdly1;
++ u32 esdcdly2;
++ u32 esdcdly3;
++ u32 esdcdly4;
++ u32 esdcdly5;
++ u32 esdgpr;
++ u32 esdprct0;
++ u32 esdprct1;
++};
++#elif defined(CONFIG_MX53)
++struct esdctl_regs {
++ u32 esdctl;
++ u32 esdpdc;
++ u32 esdotc;
++ u32 esdcfg0;
++ u32 esdcfg1;
++ u32 esdcfg2;
++ u32 esdmisc;
++ u32 esdscr;
++ u32 esdref;
++ u32 esdwcc;
++ u32 esdrcc;
++ u32 esdrwd;
++ u32 esdor;
++ u32 esdmrr;
++ u32 esdcfg3_lp;
++ u32 esdmr4;
++ u32 zqhwctrl;
++ u32 zqswctrl;
++ u32 wlgcr;
++ u32 wldectrl0;
++ u32 wldectrl1;
++ u32 wldlst;
++ u32 odtctrl;
++ u32 rddqby0dl;
++ u32 rddqby1dl;
++ u32 rddqby2dl;
++ u32 rddqby3dl;
++ u32 wrdqby0dl;
++ u32 wrdqby1dl;
++ u32 wrdqby2dl;
++ u32 wrdqby3dl;
++ u32 dgctrl0;
++ u32 dgctrl1;
++ u32 dgdlst;
++ u32 rddlctl;
++ u32 rddlst;
++ u32 wrlctl;
++ u32 wrlst;
++ u32 sdctrl;
++ u32 zqlp2ctl;
++ u32 rddlhwctl;
++ u32 wrdlhwctl;
++ u32 rddlhwst0;
++ u32 rddlhwst1;
++ u32 wrdlhwst0;
++ u32 wrdlhwst1;
++ u32 wlhwerr;
++ u32 dghwst0;
++ u32 dghwst1;
++ u32 dghwst2;
++ u32 dghwst3;
++ u32 pdcmpr1;
++ u32 pdcmpr2;
++ u32 swdar;
++ u32 swdrdr0;
++ u32 swdrdr1;
++ u32 swdrdr2;
++ u32 swdrdr3;
++ u32 swdrdr4;
++ u32 swdrdr5;
++ u32 swdrdr6;
++ u32 swdrdr7;
++ u32 mur;
++ u32 wrcadl;
++};
++#endif
++
++#endif /* __ASSEMBLY__ */
++
++/* DDR commands */
++/* cs ChipSelect in range of 0..1 */
++/* ba Bank Address in range of 0..3 */
++/* addr Pseudo Address as expected by the DDR */
++
++#define DDR_NOP_CMD(cs) (0x00008000 + (cs << 2))
++#define DRR_PRECHARGE_CMD(cs, ba) (0x04008008 + (cs << 2) + ba)
++#define DRR_AUTOREFRESH_CMD(cs) (0x00008010 + (cs << 2))
++#define DRR_LMR_CMD(cs, ba, addr) (0x00008018 + (addr << 16)\
++ + (cs << 2) + ba)
++
++#endif /* __REGS_ESDCTL_H__ */
+--- /dev/null
++++ b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
+@@ -0,0 +1,884 @@
++/*
++ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__
++#define __ASM_ARCH_MX5_MX5X_PINS_H__
++
++#ifndef __ASSEMBLY__
++
++/*
++ * In order to identify pins more effectively, each mux-controlled pin's
++ * enumerated value is constructed in the following way:
++ *
++ * -------------------------------------------------------------------
++ * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0
++ * -------------------------------------------------------------------
++ * IO_P | IO_I | GPIO_I | PAD_I | MUX_I
++ * -------------------------------------------------------------------
++ *
++ * Bit 0 to 9 contains MUX_I used to identify the register
++ * offset (0-based. base is IOMUX_module_base) defined in the Section
++ * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
++ * similar field definitions are used for the pad control register.
++ * The IOMUX controller can be split in two parts. At the begeinning,
++ * there is the register definitions for the multiplexing each pin.
++ * Then there is a set of registers (PAD_I) to configure each pin
++ * (pullup, pulldown, etc).
++ * PAD_I defines the offset of the pad register for each pin.
++ * GPIO_I defines, if available, the number of gpio that can be
++ * connected to that pad
++ * IO_I defines the multiplexer mode required to set the pad in gpio mode
++ * IO_P defines the gpio structure (gpio1..gpio4) the pad belongs
++ *
++ * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
++ * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
++ * It means the mux control register is at register offset 0x28. The pad control
++ * register offset is: 0x250 and also occupy the least significant bits
++ * within the register.
++ */
++
++/*!
++ * Starting bit position within each entry of \b iomux_pins to represent the
++ * MUX control register offset
++ */
++#define MUX_I 0
++/*!
++ * Starting bit position within each entry of \b iomux_pins to represent the
++ * PAD control register offset
++ */
++#define PAD_I 10
++/*!
++ * Starting bit position within each entry of \b iomux_pins to represent which
++ * mux mode is for GPIO (0-based)
++ */
++#define GPIO_I 21
++
++#define MUX_IO_P 29
++#define MUX_IO_I 24
++#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
++ GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
++ ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
++#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
++
++#define NON_GPIO_PORT 0x7
++#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
++#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
++#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
++
++#define NON_MUX_I PIN_TO_MUX_MASK
++#define NON_PAD_I PIN_TO_PAD_MASK
++
++#if defined(CONFIG_MX51)
++#define MUX_I_START 0x001C
++#define PAD_I_START 0x3F0
++#define INPUT_CTL_START 0x8C4
++#define MUX_I_END (PAD_I_START - 4)
++#elif defined(CONFIG_MX53)
++#define MUX_I_START 0x0020
++#define PAD_I_START 0x348
++#define INPUT_CTL_START 0x730
++#define MUX_I_END (PAD_I_START - 4)
++#else
++#error "CPU_TYPE not defined"
++#endif
++
++#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
++ (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
++ ((mi) << MUX_I) | \
++ ((pi - PAD_I_START) << PAD_I) | \
++ ((ga) << GPIO_I))
++
++#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
++ _MXC_BUILD_PIN(gp, gi, ga, mi, pi)
++
++#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
++ _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
++
++#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
++#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
++#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
++#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
++
++/*
++ * This enumeration is constructed based on the Section
++ * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
++ * value is constructed based on the rules described above.
++ */
++enum {
++ MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
++ MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
++ MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
++ MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
++ MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
++ MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
++ MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
++ MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
++ MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
++ MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
++ MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
++ MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
++ MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
++ MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
++ MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
++ MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
++ MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
++ MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
++ MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
++ MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
++ MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
++ MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
++ MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
++ MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
++ MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
++ MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
++ MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
++ MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
++ MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
++ MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
++ MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
++ MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
++ MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
++ MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
++ MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
++ MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
++ MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
++ MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
++ MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
++ MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
++ MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
++ MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
++ MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
++ MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
++ MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
++ MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
++ MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
++ MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
++ MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
++ MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
++ MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
++ MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
++ MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
++ MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
++ MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
++ MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
++ MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
++ MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
++ MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
++ MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
++ MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
++ MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
++ MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
++ MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
++ MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
++ MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
++ MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
++ MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
++ MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514),
++ MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
++ MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
++ MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
++ MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
++ MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
++ MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
++ MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
++ MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
++ MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
++ MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
++ MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
++ MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
++ MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
++ MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
++ MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
++ MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
++ MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
++ MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
++ MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
++ MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
++ MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
++ MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
++ MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
++ MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
++ MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
++ MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
++ MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
++ MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
++ MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
++ MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
++ MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
++ MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
++ MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
++ MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
++ MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
++ MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
++ MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
++ MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
++ MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
++ MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
++ MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
++ MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC),
++ MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0),
++ MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
++ MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
++ MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
++ MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
++ MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
++ MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4),
++ MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8),
++ MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC),
++ MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0),
++ MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
++ MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
++ MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
++ MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
++ MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
++ MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
++ MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
++ MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
++ MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
++ MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
++ MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
++ MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
++ MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
++ MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
++ MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
++ MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
++ MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
++ MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
++ MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
++ MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
++ MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
++ MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
++ MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
++ MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
++ MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
++ MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
++ MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
++ MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
++ MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
++ MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
++ MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
++ MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
++ MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
++ MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
++ MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
++ MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
++ MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
++ MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
++ MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
++ MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
++ MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
++ MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
++ MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
++ MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
++ MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
++ MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
++ MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
++ MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
++ MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
++ MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
++ MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
++ MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
++ MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
++ MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
++ MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
++ MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
++ MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
++ MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
++ MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
++ MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
++ MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
++ MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
++ MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
++ MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
++ MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
++ MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
++ MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
++ MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
++ MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
++ MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
++ MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
++ MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
++ MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
++ MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
++ MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
++ MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
++ MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
++ MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
++ MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
++ MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
++ MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
++ MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
++ MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
++ MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
++ MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
++ MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
++ MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
++ MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
++ MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
++ MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
++ MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
++ MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
++ MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
++ MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
++ MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
++ MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
++ MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
++ MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
++ MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
++ MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
++ MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
++ MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
++ MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
++ MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788),
++ MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
++ MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
++ MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
++ MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
++ MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
++ MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
++ MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
++ MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
++ MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
++ MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
++ MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
++ MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
++ MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
++ MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
++ MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
++ MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
++ MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
++ MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
++ MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
++ MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
++ MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
++ MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
++ MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
++ MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
++ MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
++ MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
++ MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
++
++ /* The following are PADS used for drive strength */
++
++ MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820),
++ MX51_PIN_CTL_GRP_INDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x830),
++ MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838),
++ MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890),
++ MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C),
++ MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C),
++ MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884),
++ MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C),
++ MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864),
++ MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C),
++ MX51_PIN_CTL_GRP_HVDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x870),
++ MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874),
++ MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878),
++ MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880),
++ MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C),
++ MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C),
++ MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4),
++ MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC),
++ MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8),
++ MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C),
++ MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0),
++ MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0),
++ MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4),
++ MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC),
++ MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C),
++ MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848),
++ MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868),
++ MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4),
++ MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8),
++ MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac),
++ MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0),
++ MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4),
++ MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8),
++ MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC),
++ MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0),
++ MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4),
++ MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8),
++ MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC),
++ MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0),
++ MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4),
++ MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8),
++ MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC),
++ MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
++ MX51_PIN_CTL_PAD_EIM_SDBA2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x508),
++ MX51_PIN_CTL_PAD_EIM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x50C),
++ MX51_PIN_CTL_PAD_EIM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x510),
++};
++
++enum {
++ MX53_PIN_GPIO_19 = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348),
++ MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C),
++ MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350),
++ MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354),
++ MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358),
++ MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C),
++ MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360),
++ MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364),
++ MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368),
++ MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C),
++ MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370),
++ MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374),
++ MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378),
++ MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C),
++ MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380),
++ MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384),
++ MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388),
++ MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C),
++ MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390),
++ MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394),
++ MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398),
++ MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C),
++ MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0),
++ MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4),
++ MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8),
++ MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC),
++ MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0),
++ MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4),
++ MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8),
++ MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC),
++ MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0),
++ MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4),
++ MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8),
++ MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC),
++ MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0),
++ MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4),
++ MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8),
++ MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC),
++ MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0),
++ MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4),
++ MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8),
++ MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC),
++ MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0),
++ MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4),
++ MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8),
++ MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC),
++ MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400),
++ MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404),
++ MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408),
++ MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C),
++ MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410),
++ MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414),
++ MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418),
++ MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C),
++ MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420),
++ MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424),
++ MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428),
++ MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C),
++ MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430),
++ MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434),
++ MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438),
++ MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C),
++ MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440),
++ MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444),
++ MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448),
++ MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C),
++ MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450),
++ MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454),
++ MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458),
++ MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C),
++ MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460),
++ MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464),
++ MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468),
++ MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C),
++ MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470),
++ MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474),
++ MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478),
++ MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C),
++ MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480),
++ MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484),
++ MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488),
++ MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C),
++ MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490),
++ MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494),
++ MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498),
++ MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C),
++ MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0),
++ MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4),
++ MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8),
++ MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC),
++ MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0),
++ MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4),
++ MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8),
++ MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC),
++ MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0),
++ MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4),
++ MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8),
++ MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC),
++ MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0),
++ MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4),
++ MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8),
++ MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC),
++ MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0),
++ MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4),
++ MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8),
++ MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC),
++ MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0),
++ MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4),
++ MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8),
++ MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC),
++ MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500),
++ MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504),
++ MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508),
++ MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C),
++ MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510),
++ MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514),
++ MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518),
++ MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C),
++ MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520),
++ MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524),
++ MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528),
++ MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C),
++ MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530),
++ MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534),
++ MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538),
++ MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C),
++ MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I),
++ MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I),
++ MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I),
++ MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I),
++ MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I),
++ MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I),
++ MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I),
++ MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I),
++ MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I),
++ MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I),
++ MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540),
++ MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544),
++ MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548),
++ MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C),
++ MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550),
++ MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554),
++ MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558),
++ MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C),
++ MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560),
++ MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564),
++ MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568),
++ MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C),
++ MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570),
++ MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574),
++ MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578),
++ MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C),
++ MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580),
++ MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584),
++ MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588),
++ MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C),
++ MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590),
++ MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594),
++ MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598),
++ MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C),
++ MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0),
++ MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4),
++ MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8),
++ MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC),
++ MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0),
++ MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4),
++ MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8),
++ MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC),
++ MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0),
++ MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4),
++ MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8),
++ MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC),
++ MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0),
++ MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4),
++ MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8),
++ MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC),
++ MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0),
++ MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4),
++ MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8),
++ MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC),
++ MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0),
++ MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4),
++ MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8),
++ MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC),
++ MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600),
++ MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604),
++ MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608),
++ MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C),
++ MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610),
++ MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614),
++ MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618),
++ MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C),
++ MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620),
++ MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624),
++ MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628),
++ MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C),
++ MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630),
++ MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634),
++ MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638),
++ MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C),
++ MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640),
++ MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644),
++ MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648),
++ MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C),
++ MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650),
++ MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654),
++ MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658),
++ MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C),
++ MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660),
++ MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664),
++ MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668),
++ MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C),
++ MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670),
++ MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674),
++ MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678),
++ MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C),
++ MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680),
++ MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684),
++ MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688),
++ MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C),
++ MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690),
++ MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694),
++ MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698),
++ MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C),
++ MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0),
++ MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4),
++ MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8),
++ MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC),
++ MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0),
++ MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4),
++ MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8),
++ MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC),
++ MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0),
++ MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4),
++ MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8),
++ MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC),
++ MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0),
++ MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4),
++ MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8),
++ MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC),
++ MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0),
++ MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4),
++ MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8),
++ MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC),
++ MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0),
++ MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4),
++ MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC),
++ MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708),
++ MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C),
++ MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710),
++ MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714),
++ MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718),
++ MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C),
++ MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720),
++ MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724),
++ MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728),
++ MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C),
++};
++/* various IOMUX input select register index */
++typedef enum iomux_input_select {
++ MX51_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
++ MX51_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
++ MX51_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
++ MX51_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
++ MX51_CCM_IPP_DI_CLK_SELECT_INPUT,
++ /* TO2 */
++ MX51_CCM_IPP_DI1_CLK_SELECT_INPUT,
++ MX51_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
++ MX51_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
++ MX51_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
++ MX51_CSPI_IPP_IND_MISO_SELECT_INPUT,
++ MX51_CSPI_IPP_IND_MOSI_SELECT_INPUT,
++ MX51_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
++ MX51_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
++ MX51_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
++ MX51_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
++ /* TO2 */
++ MX51_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
++ MX51_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
++ MX51_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
++ MX51_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
++ MX51_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
++ MX51_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
++ MX51_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
++ MX51_FEC_FEC_COL_SELECT_INPUT,
++ MX51_FEC_FEC_CRS_SELECT_INPUT,
++ MX51_FEC_FEC_MDI_SELECT_INPUT,
++ MX51_FEC_FEC_RDATA_0_SELECT_INPUT,
++ MX51_FEC_FEC_RDATA_1_SELECT_INPUT,
++ MX51_FEC_FEC_RDATA_2_SELECT_INPUT,
++ MX51_FEC_FEC_RDATA_3_SELECT_INPUT,
++ MX51_FEC_FEC_RX_CLK_SELECT_INPUT,
++ MX51_FEC_FEC_RX_DV_SELECT_INPUT,
++ MX51_FEC_FEC_RX_ER_SELECT_INPUT,
++ MX51_FEC_FEC_TX_CLK_SELECT_INPUT,
++ MX51_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
++ MX51_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
++ MX51_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
++ MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
++ MX51_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
++ MX51_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
++ MX51_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
++ MX51_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
++ /* TO2 */
++ MX51_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
++ MX51_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
++ MX51_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
++ /* TO2 */
++ MX51_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
++ /* TO2 */
++ MX51_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
++ MX51_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
++ MX51_I2C1_IPP_SCL_IN_SELECT_INPUT,
++ MX51_I2C1_IPP_SDA_IN_SELECT_INPUT,
++ MX51_I2C2_IPP_SCL_IN_SELECT_INPUT,
++ MX51_I2C2_IPP_SDA_IN_SELECT_INPUT,
++ MX51_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
++ MX51_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
++ MX51_KPP_IPP_IND_COL_6_SELECT_INPUT,
++ MX51_KPP_IPP_IND_COL_7_SELECT_INPUT,
++ MX51_KPP_IPP_IND_ROW_4_SELECT_INPUT,
++ MX51_KPP_IPP_IND_ROW_5_SELECT_INPUT,
++ MX51_KPP_IPP_IND_ROW_6_SELECT_INPUT,
++ MX51_KPP_IPP_IND_ROW_7_SELECT_INPUT,
++ MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
++ MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
++ MX51_UART2_IPP_UART_RTS_B_SELECT_INPUT,
++ MX51_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
++ MX51_UART3_IPP_UART_RTS_B_SELECT_INPUT,
++ MX51_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
++ MX51PUT_NUM_MUX,
++ /* MX53 */
++ MX53_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
++ MX53_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
++ MX53_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
++ MX53_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
++ MX53_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
++ MX53_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
++ MX53_AUDMUX_P5_INPUT_DA_AMX_SELECT_I,
++ MX53_AUDMUX_P5_INPUT_DB_AMX_SELECT_I,
++ MX53_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
++ MX53_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT,
++ MX53_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
++ MX53_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
++ MX53_CAN1_IPP_IND_CANRX_SELECT_INPUT,
++ MX53_CAN2_IPP_IND_CANRX_SELECT_INPUT,
++ MX53_CCM_IPP_ASRC_EXT_SELECT_INPUT,
++ MX53_CCM_IPP_DI1_CLK_SELECT_INPUT,
++ MX53_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
++ MX53_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
++ MX53_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
++ MX53_CCM_PLL4_BYPASS_CLK_SELECT_INPUT,
++ MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
++ MX53_CSPI_IPP_IND_MISO_SELECT_INPUT,
++ MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT,
++ MX53_CSPI_IPP_IND_SS_B_0_SELECT_INPUT,
++ MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
++ MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
++ MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
++ MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
++ MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
++ MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
++ MX53_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT,
++ MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
++ MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
++ MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT,
++ MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
++ MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
++ MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
++ MX53_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT,
++ MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_FST_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_SCKT_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
++ MX53_ESDHC1_IPP_WP_ON_SELECT_INPUT,
++ MX53_FEC_FEC_COL_SELECT_INPUT,
++ MX53_FEC_FEC_MDI_SELECT_INPUT,
++ MX53_FEC_FEC_RX_CLK_SELECT_INPUT,
++ MX53_FIRI_IPP_IND_RXD_SELECT_INPUT,
++ MX53_GPC_PMIC_RDY_SELECT_INPUT,
++ MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
++ MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
++ MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
++ MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
++ MX53_I2C3_IPP_SCL_IN_SELECT_INPUT,
++ MX53_I2C3_IPP_SDA_IN_SELECT_INPUT,
++ MX53_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
++ MX53_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
++ MX53_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
++ MX53_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT,
++ MX53_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT,
++ MX53_KPP_IPP_IND_COL_5_SELECT_INPUT,
++ MX53_KPP_IPP_IND_COL_6_SELECT_INPUT,
++ MX53_KPP_IPP_IND_COL_7_SELECT_INPUT,
++ MX53_KPP_IPP_IND_ROW_5_SELECT_INPUT,
++ MX53_KPP_IPP_IND_ROW_6_SELECT_INPUT,
++ MX53_KPP_IPP_IND_ROW_7_SELECT_INPUT,
++ MX53_MLB_MLBCLK_IN_SELECT_INPUT,
++ MX53_MLB_MLBDAT_IN_SELECT_INPUT,
++ MX53_MLB_MLBSIG_IN_SELECT_INPUT,
++ MX53_OWIRE_BATTERY_LINE_IN_SELECT_INPUT,
++ MX53_SDMA_EVENTS_14_SELECT_INPUT,
++ MX53_SDMA_EVENTS_15_SELECT_INPUT,
++ MX53_SPDIF_SPDIF_IN1_SELECT_INPUT,
++ MX53_UART1_IPP_UART_RTS_B_SELECT_INPUT,
++ MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
++ MX53_UART2_IPP_UART_RTS_B_SELECT_INPUT,
++ MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
++ MX53_UART3_IPP_UART_RTS_B_SELECT_INPUT,
++ MX53_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
++ MX53_UART4_IPP_UART_RTS_B_SELECT_INPUT,
++ MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
++ MX53_UART5_IPP_UART_RTS_B_SELECT_INPUT,
++ MX53_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
++ MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT,
++ MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT,
++ MX53_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT,
++} iomux_input_select_t;
++
++#endif /* __ASSEMBLY__ */
++#endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */
+--
+1.7.2.5
+
diff --git a/patches/u-boot/2014.04/401-apf51.patch b/patches/u-boot/2014.04/401-apf51.patch
new file mode 100644
index 0000000..9ca4ad4
--- /dev/null
+++ b/patches/u-boot/2014.04/401-apf51.patch
@@ -0,0 +1,1339 @@
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Nicolas Colombain <nic...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+---
+ board/armadeus/apf51/Makefile | 43 ++
+ board/armadeus/apf51/apf51.c | 1222 +++++++++++++++++++++++++++++++++++++++++
+ board/armadeus/apf51/fpga.c | 266 +++++++++
+ board/armadeus/apf51/fpga.h | 39 ++
+ boards.cfg | 1 +
+ 5 files changed, 1571 insertions(+), 0 deletions(-)
+ create mode 100644 board/armadeus/apf51/Makefile
+ create mode 100644 board/armadeus/apf51/apf51.c
+ create mode 100644 board/armadeus/apf51/fpga.c
+ create mode 100644 board/armadeus/apf51/fpga.h
+
+diff --git a/board/armadeus/apf51/Makefile b/board/armadeus/apf51/Makefile
+new file mode 100644
+index 0000000..9d94f74
+--- /dev/null
++++ b/board/armadeus/apf51/Makefile
+@@ -0,0 +1,9 @@
++#
++# (C) Copyright 2000-2006
++# Wolfgang Denk, DENX Software Engineering, wd...@de....
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y := apf51.o fpga.o
++
+diff --git a/board/armadeus/apf51/apf51.c b/board/armadeus/apf51/apf51.c
+new file mode 100644
+index 0000000..8ff1381
+--- /dev/null
++++ b/board/armadeus/apf51/apf51.c
+@@ -0,0 +1,999 @@
++/*
++ * Armadeus APF51 baseboard
++ *
++ * (C) Copyright 2010-2014 Eric Jarrige, Armadeus Project
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <command.h>
++#include <environment.h>
++#include <asm/armv7.h...
[truncated message content] |
|
From: Sébastien S. <ss...@us...> - 2014-05-05 14:31:11
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via ad1ef8252c2900310adc0d07fd43f4f69c7fb0bf (commit)
from 0fa3c1387708447d04a27eb92d767e23188fe898 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit ad1ef8252c2900310adc0d07fd43f4f69c7fb0bf
Author: Sébastien Szymanski <ss...@us...>
Date: Mon May 5 16:33:04 2014 +0200
[LINUX] 3.15: move to 3.15-rc4
-----------------------------------------------------------------------
Summary of changes:
...3.15-rc3.config => apf27-linux-3.15-rc4.config} | 0
...3.15-rc3.config => apf28-linux-3.15-rc4.config} | 0
...3.15-rc3.config => apf51-linux-3.15-rc4.config} | 0
3 files changed, 0 insertions(+), 0 deletions(-)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.15-rc3.config => apf27-linux-3.15-rc4.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.15-rc3.config => apf28-linux-3.15-rc4.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.15-rc3.config => apf51-linux-3.15-rc4.config} (100%)
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc3.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc4.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc3.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc4.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc3.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc4.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc3.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc4.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc3.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc4.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc3.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc4.config
hooks/post-receive
--
armadeus
|
|
From: Sébastien S. <ss...@us...> - 2014-05-05 14:25:41
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 0fa3c1387708447d04a27eb92d767e23188fe898 (commit)
from 121db0b2d284e5d8de7bd8cf0c16910eb4f38d97 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 0fa3c1387708447d04a27eb92d767e23188fe898
Author: Sébastien Szymanski <ss...@us...>
Date: Mon May 5 16:26:12 2014 +0200
[LINUX] apf6: move to linux 3.15-rc4
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf6_defconfig | 2 +-
...-3.15-rc3.config => apf6-linux-3.15-rc4.config} | 0
patches/linux/{3.15-rc3 => 3.15-rc4} | 0
3 files changed, 1 insertions(+), 1 deletions(-)
rename buildroot/target/device/armadeus/apf6/{apf6-linux-3.15-rc3.config => apf6-linux-3.15-rc4.config} (100%)
rename patches/linux/{3.15-rc3 => 3.15-rc4} (100%)
diff --git a/buildroot/configs/apf6_defconfig b/buildroot/configs/apf6_defconfig
index 4e30b0c..235b120 100644
--- a/buildroot/configs/apf6_defconfig
+++ b/buildroot/configs/apf6_defconfig
@@ -22,7 +22,7 @@ BR2_TARGET_ARMADEUS_NR_SDRAM="2"
BR2_TARGET_ARMADEUS_SDRAM_SIZE="512"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.15-rc3"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.15-rc4"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc3.config b/buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc4.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc3.config
rename to buildroot/target/device/armadeus/apf6/apf6-linux-3.15-rc4.config
diff --git a/patches/linux/3.15-rc3 b/patches/linux/3.15-rc4
similarity index 100%
rename from patches/linux/3.15-rc3
rename to patches/linux/3.15-rc4
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2014-05-02 10:37:38
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 121db0b2d284e5d8de7bd8cf0c16910eb4f38d97 (commit)
via 77b0b2dda5fdbdcbfee89381fdec3e4655b5cfc6 (commit)
via 894aaff73033e569e74492e0f5e0b1829edf52b3 (commit)
from 7ab179cf3a5e8d224fccfc39089cb97524c4416b (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 121db0b2d284e5d8de7bd8cf0c16910eb4f38d97
Author: Eric Jarrige <eri...@ar...>
Date: Fri May 2 12:02:21 2014 +0200
[LINUX] 3.15: afp51: fix pinctrl
commit 77b0b2dda5fdbdcbfee89381fdec3e4655b5cfc6
Author: Philippe Reynes <tr...@ya...>
Date: Thu May 1 15:53:40 2014 +0200
[LINUX] 3.10: move to 3.10.38
commit 894aaff73033e569e74492e0f5e0b1829edf52b3
Author: Philippe Reynes <tr...@ya...>
Date: Thu May 1 15:53:39 2014 +0200
[LINUX] 3.15: move to 3.15-rc3
-----------------------------------------------------------------------
Summary of changes:
...x-3.10.37.config => apf27-linux-3.10.38.config} | 0
...3.15-rc2.config => apf27-linux-3.15-rc3.config} | 0
...x-3.10.37.config => apf28-linux-3.10.38.config} | 0
...3.15-rc2.config => apf28-linux-3.15-rc3.config} | 0
...x-3.10.37.config => apf51-linux-3.10.38.config} | 0
...3.15-rc2.config => apf51-linux-3.15-rc3.config} | 0
patches/linux/{3.10.37 => 3.10.38} | 0
patches/linux/3.15/0073-armadeus-tsc2102.patch | 3 +-
.../3.15/0400-Add-apf51-basic-dt-support.patch | 48 +++++++++++++++++++-
.../0401-armadeus-add_apf51dev_baseboard.patch | 37 +++++++++++-----
10 files changed, 73 insertions(+), 15 deletions(-)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.10.37.config => apf27-linux-3.10.38.config} (100%)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.15-rc2.config => apf27-linux-3.15-rc3.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.10.37.config => apf28-linux-3.10.38.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.15-rc2.config => apf28-linux-3.15-rc3.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.10.37.config => apf51-linux-3.10.38.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.15-rc2.config => apf51-linux-3.15-rc3.config} (100%)
rename patches/linux/{3.10.37 => 3.10.38} (100%)
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.37.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.38.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.10.37.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.10.38.config
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc2.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc3.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc2.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.15-rc3.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.10.37.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.10.38.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.10.37.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.10.38.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc2.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc3.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc2.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.15-rc3.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.10.37.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.10.38.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.10.37.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.10.38.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc2.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc3.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc2.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.15-rc3.config
diff --git a/patches/linux/3.10.37 b/patches/linux/3.10.38
similarity index 100%
rename from patches/linux/3.10.37
rename to patches/linux/3.10.38
diff --git a/patches/linux/3.15/0073-armadeus-tsc2102.patch b/patches/linux/3.15/0073-armadeus-tsc2102.patch
index 90e8154..84b3e7c 100644
--- a/patches/linux/3.15/0073-armadeus-tsc2102.patch
+++ b/patches/linux/3.15/0073-armadeus-tsc2102.patch
@@ -313,7 +313,7 @@ Index: linux-3.8-rc1/drivers/spi/tsc2102.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-3.8-rc1/drivers/spi/tsc2102.c 2013-01-01 21:19:56.000000000 +0100
-@@ -0,0 +1,1311 @@
+@@ -0,0 +1,1310 @@
+/*
+ * drivers/spi/tsc2102.c
+ *
@@ -353,7 +353,6 @@ Index: linux-3.8-rc1/drivers/spi/tsc2102.c
+#include <linux/hwmon-sysfs.h>
+#include <linux/workqueue.h>
+
-+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
diff --git a/patches/linux/3.15/0400-Add-apf51-basic-dt-support.patch b/patches/linux/3.15/0400-Add-apf51-basic-dt-support.patch
index 9fb716d..9136025 100644
--- a/patches/linux/3.15/0400-Add-apf51-basic-dt-support.patch
+++ b/patches/linux/3.15/0400-Add-apf51-basic-dt-support.patch
@@ -27,8 +27,52 @@ Index: linux-3.13-rc2/arch/arm/boot/dts/imx51-apf51.dts
};
&fec {
-@@ -53,3 +66,31 @@
- pinctrl-0 = <&pinctrl_uart3_2>;
+@@ -72,6 +72,43 @@
+ MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
+ >;
+ };
++ usbh1 {
++ pinctrl_usbh1_1: usbh1grp-1 {
++ fsl,pins = <
++ MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
++ MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
++ MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
++ MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
++ MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
++ MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
++ MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
++ MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
++ MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
++ MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
++ MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
++ MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
++ >;
++ };
++ };
++
++ usbh2 {
++ pinctrl_usbh2_1: usbh2grp-1 {
++ fsl,pins = <
++ MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
++ MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
++ MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
++ MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
++ MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
++ MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
++ MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
++ MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
++ MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
++ MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
++ MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
++ MX51_PAD_EIM_A26__USBH2_STP 0x1e5
++ >;
++ };
++ };
+ };
+ };
+
+@@ -87,3 +100,31 @@
+ pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
+
diff --git a/patches/linux/3.15/0401-armadeus-add_apf51dev_baseboard.patch b/patches/linux/3.15/0401-armadeus-add_apf51dev_baseboard.patch
index 58067a6..c490052 100644
--- a/patches/linux/3.15/0401-armadeus-add_apf51dev_baseboard.patch
+++ b/patches/linux/3.15/0401-armadeus-add_apf51dev_baseboard.patch
@@ -7,8 +7,8 @@ Index: linux-3.14-rc4/arch/arm/boot/dts/imx51-apf51dev.dts
===================================================================
--- linux-3.14-rc4.orig/arch/arm/boot/dts/imx51-apf51dev.dts
+++ linux-3.14-rc4/arch/arm/boot/dts/imx51-apf51dev.dts
-@@ -61,6 +61,12 @@
- gpios = <&gpio1 2 0>;
+@@ -66,6 +66,12 @@
+ gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
+
@@ -20,9 +20,9 @@ Index: linux-3.14-rc4/arch/arm/boot/dts/imx51-apf51dev.dts
};
};
-@@ -78,6 +84,14 @@
- fsl,spi-num-chipselects = <2>;
- cs-gpios = <&gpio3 28 1>, <&gpio3 27 1>;
+@@ -85,6 +91,14 @@
+ cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>,
+ <&gpio3 27 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ spidev: spidev@1 {
@@ -35,15 +35,15 @@ Index: linux-3.14-rc4/arch/arm/boot/dts/imx51-apf51dev.dts
};
&esdhc1 {
-@@ -92,7 +106,6 @@
+@@ -99,7 +113,6 @@
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_esdhc2_1>;
+ pinctrl-0 = <&pinctrl_esdhc2>;
bus-width = <4>;
- non-removable;
status = "okay";
};
-@@ -102,6 +115,13 @@
+@@ -109,6 +122,13 @@
status = "okay";
};
@@ -57,15 +57,15 @@ Index: linux-3.14-rc4/arch/arm/boot/dts/imx51-apf51dev.dts
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
-@@ -109,6 +129,7 @@
- hog {
+@@ -116,6 +136,7 @@
+ imx51-apf51dev {
pinctrl_hog: hoggrp {
fsl,pins = <
+ MX51_PAD_GPIO1_8__GPIO1_8 0x0C5
MX51_PAD_EIM_EB2__GPIO2_22 0x0C5
MX51_PAD_EIM_EB3__GPIO2_23 0x0C5
MX51_PAD_EIM_CS4__GPIO2_29 0x100
-@@ -118,6 +139,8 @@
+@@ -125,6 +146,8 @@
MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5
MX51_PAD_GPIO1_2__GPIO1_2 0x0C5
MX51_PAD_GPIO1_3__GPIO1_3 0x0C5
@@ -73,4 +73,19 @@ Index: linux-3.14-rc4/arch/arm/boot/dts/imx51-apf51dev.dts
+ MX51_PAD_EIM_CS3__GPIO2_28 0x0C5
>;
};
+
+@@ -203,6 +203,14 @@
+ MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
+ >;
+ };
++ uart2 {
++ pinctrl_uart2_1: uart2grp-1 {
++ fsl,pins = <
++ MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
++ MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
++ >;
++ };
++ };
};
+ };
+
hooks/post-receive
--
armadeus
|
|
From: Julien B a. A. <ar...@us...> - 2014-04-30 13:51:10
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 7ab179cf3a5e8d224fccfc39089cb97524c4416b (commit)
from 53de6332e709b4224c63940549b3092f7ce4d9fe (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 7ab179cf3a5e8d224fccfc39089cb97524c4416b
Author: Philippe Reynes <tr...@ya...>
Date: Fri Apr 25 20:38:46 2014 +0200
[BUILDROOT] Add a config for mainline xenomai on APF27
-----------------------------------------------------------------------
Summary of changes:
...ne_defconfig => apf27xenomaimainline_defconfig} | 10 ++++++----
...3.10.config => apf27-linux-3.10-xenomai.config} | 15 ++++++++++-----
.../apf27/apf27-linux-3.10.32-xenomai.config | 1 +
patches/linux/{3.10.18 => 3.10.32} | 0
4 files changed, 17 insertions(+), 9 deletions(-)
copy buildroot/configs/{apf27mainline_defconfig => apf27xenomaimainline_defconfig} (92%)
copy buildroot/target/device/armadeus/apf27/{apf27-linux-3.10.config => apf27-linux-3.10-xenomai.config} (96%)
create mode 120000 buildroot/target/device/armadeus/apf27/apf27-linux-3.10.32-xenomai.config
copy patches/linux/{3.10.18 => 3.10.32} (100%)
diff --git a/buildroot/configs/apf27mainline_defconfig b/buildroot/configs/apf27xenomaimainline_defconfig
similarity index 92%
copy from buildroot/configs/apf27mainline_defconfig
copy to buildroot/configs/apf27xenomaimainline_defconfig
index 9482145..4392cfb 100644
--- a/buildroot/configs/apf27mainline_defconfig
+++ b/buildroot/configs/apf27xenomaimainline_defconfig
@@ -6,7 +6,7 @@ BR2_CCACHE=y
BR2_CCACHE_DIR="$(TOPDIR)/.$(BR2_BOARD_NAME)-buildroot-ccache"
BR2_STRIP_sstrip=y
BR2_KERNEL_HEADERS_VERSION=y
-BR2_DEFAULT_KERNEL_VERSION="3.14.2"
+BR2_DEFAULT_KERNEL_VERSION="3.10.32"
BR2_UCLIBC_CONFIG="target/device/armadeus/uClibc-$(BR2_UCLIBC_VERSION_STRING).config"
BR2_TOOLCHAIN_BUILDROOT_LARGEFILE=y
BR2_TOOLCHAIN_BUILDROOT_INET_IPV6=y
@@ -21,7 +21,6 @@ BR2_ENABLE_LOCALE_WHITELIST="C en_US"
BR2_TARGET_OPTIMIZATION="-Os -pipe"
BR2_TARGET_GENERIC_HOSTNAME="apf27"
BR2_TARGET_GENERIC_ISSUE="Welcome to Armadeus development platform !"
-BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_DEVTMPFS=y
BR2_ROOTFS_DEVICE_TABLE="$(ARMADEUS_PATH)/rootfs/device_table.txt"
BR2_ROOTFS_SKELETON_CUSTOM=y
BR2_ROOTFS_SKELETON_CUSTOM_PATH="$(ARMADEUS_PATH)/rootfs/target_skeleton"
@@ -34,13 +33,15 @@ BR2_BOARD_NAME="apf27"
BR2_CPU_NAME="imx27"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.2"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.10.32"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
BR2_LINUX_KERNEL_UIMAGE_LOADADDR="0xA0008000"
BR2_LINUX_KERNEL_DTS_SUPPORT=y
BR2_LINUX_KERNEL_INTREE_DTS_NAME="imx27-apf27dev"
+BR2_LINUX_KERNEL_EXT_XENOMAI=y
+BR2_LINUX_KERNEL_EXT_XENOMAI_ADEOS_PATCH_URL="http://download.gna.org/adeos/patches/v3.x/arm/ipipe-core-3.10.32-arm-2.patch"
BR2_PACKAGE_BUSYBOX_CONFIG="$(ARMADEUS_PATH)/busybox-$(BR2_BUSYBOX_VERSION).config"
BR2_PACKAGE_FPGAREGS=y
BR2_PACKAGE_ARMADEUS_FPGA_FIRMWARE=y
@@ -67,7 +68,6 @@ BR2_PACKAGE_IPROUTE2=y
BR2_PACKAGE_NTP=y
# BR2_PACKAGE_NTP_NTPD is not set
BR2_PACKAGE_PORTMAP=y
-BR2_PACKAGE_UUCP=y
BR2_PACKAGE_WIRELESS_TOOLS=y
BR2_PACKAGE_WPA_SUPPLICANT=y
BR2_PACKAGE_WPA_SUPPLICANT_EAP=y
@@ -75,6 +75,8 @@ BR2_PACKAGE_WPA_SUPPLICANT_CLI=y
BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y
BR2_PACKAGE_WPA_SUPPLICANT_AP_SUPPORT=y
BR2_PACKAGE_WPA_SUPPLICANT_WPS=y
+BR2_PACKAGE_XENOMAI_VERSION="2.6.3"
+BR2_PACKAGE_XENOMAI_TESTSUITE=y
BR2_PACKAGE_NANO=y
BR2_TARGET_ROOTFS_JFFS2=y
BR2_TARGET_ROOTFS_JFFS2_NANDFLASH_2K_128K=y
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.10-xenomai.config
similarity index 96%
copy from buildroot/target/device/armadeus/apf27/apf27-linux-3.10.config
copy to buildroot/target/device/armadeus/apf27/apf27-linux-3.10-xenomai.config
index d09275d..2f3f4c8 100644
--- a/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.config
+++ b/buildroot/target/device/armadeus/apf27/apf27-linux-3.10-xenomai.config
@@ -16,9 +16,14 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_XENO_HW_FPU is not set
+CONFIG_XENO_DRIVERS_TIMERBENCH=m
+CONFIG_XENO_DRIVERS_KLATENCY=m
+CONFIG_XENO_DRIVERS_IRQBENCH=m
+CONFIG_XENO_DRIVERS_SWITCHTEST=m
+CONFIG_XENO_DRIVERS_RTDMTEST=m
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_MXC=y
-CONFIG_MXC_IRQ_PRIOR=y
CONFIG_MACH_IMX27_DT=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
@@ -141,7 +146,7 @@ CONFIG_VIDEO_MX2=m
# CONFIG_DVB_TUNER_DIB0070 is not set
# CONFIG_DVB_TUNER_DIB0090 is not set
CONFIG_FB=y
-CONFIG_FB_IMX=y
+# CONFIG_FB_MX3 is not set
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_L4F00242T03=y
@@ -163,12 +168,12 @@ CONFIG_SND_IMX_SOC=m
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
-CONFIG_USB_CHIPIDEA=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_DEBUG=y
CONFIG_USB_ACM=y
CONFIG_USB_PRINTER=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_DEBUG=y
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_FTDI_SIO=y
CONFIG_USB_SERIAL_PL2303=y
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.32-xenomai.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.32-xenomai.config
new file mode 120000
index 0000000..1ee3ec7
--- /dev/null
+++ b/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.32-xenomai.config
@@ -0,0 +1 @@
+apf27-linux-3.10-xenomai.config
\ No newline at end of file
diff --git a/patches/linux/3.10.18 b/patches/linux/3.10.32
similarity index 100%
copy from patches/linux/3.10.18
copy to patches/linux/3.10.32
hooks/post-receive
--
armadeus
|
|
From: Julien B a. A. <ar...@us...> - 2014-04-30 09:47:47
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 53de6332e709b4224c63940549b3092f7ce4d9fe (commit)
from 7e5e50485e71b0cbf764a42994ad7a597db59b43 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 53de6332e709b4224c63940549b3092f7ce4d9fe
Author: Julien Boibessot <jul...@ar...>
Date: Wed Apr 30 11:42:36 2014 +0200
[BUILDROOT] Add sam7_pgm-ng package
-----------------------------------------------------------------------
Summary of changes:
.../010-armadeus-sam7-pgm-ng-new-package.patch | 50 ++++++++++++++++++++
patches/buildroot/2013.11/cleanup_buildroot.sh | 1 +
2 files changed, 51 insertions(+), 0 deletions(-)
create mode 100644 patches/buildroot/2013.11/010-armadeus-sam7-pgm-ng-new-package.patch
diff --git a/patches/buildroot/2013.11/010-armadeus-sam7-pgm-ng-new-package.patch b/patches/buildroot/2013.11/010-armadeus-sam7-pgm-ng-new-package.patch
new file mode 100644
index 0000000..a4463e1
--- /dev/null
+++ b/patches/buildroot/2013.11/010-armadeus-sam7-pgm-ng-new-package.patch
@@ -0,0 +1,50 @@
+Index: buildroot/package/Config.in
+===================================================================
+--- buildroot.orig/package/Config.in 2014-04-28 19:58:00.810406963 +0200
++++ buildroot/package/Config.in 2014-04-28 19:59:07.122735790 +0200
+@@ -347,6 +347,7 @@
+ source "package/rng-tools/Config.in"
+ source "package/rpi-userland/Config.in"
+ source "package/sane-backends/Config.in"
++source "package/sam7-pgm-ng/Config.in"
+ source "package/sdparm/Config.in"
+ source "package/setserial/Config.in"
+ source "package/sg3_utils/Config.in"
+Index: buildroot/package/sam7-pgm-ng/Config.in
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ buildroot/package/sam7-pgm-ng/Config.in 2014-04-28 21:14:16.129094736 +0200
+@@ -0,0 +1,7 @@
++config BR2_PACKAGE_SAM7_PGM_NG
++ bool "sam7_pgm-ng"
++ help
++ Armadeus fork of SAM7_PGM (with some cleanup).
++
++ https://github.com/Martoni/SAM7_PGM-NG
++ http://www.pjrc.com/arm/sam7_pgm/
+Index: buildroot/package/sam7-pgm-ng/sam7-pgm-ng.mk
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ buildroot/package/sam7-pgm-ng/sam7-pgm-ng.mk 2014-04-28 21:11:59.856418999 +0200
+@@ -0,0 +1,21 @@
++################################################################################
++#
++# sam7-pgm-ng
++#
++################################################################################
++
++SAM7_PGM_NG_VERSION = 3a837382ae2deda6796aedd594be18503ad8ad96
++SAM7_PGM_NG_SITE = https://github.com/Martoni/SAM7_PGM-NG
++SAM7_PGM_NG_SITE_METHOD = git
++SAM7_PGM_NG_LICENSE = GPLv2+
++SAM7_PGM_NG_LICENSE_FILES = COPYING
++
++define SAM7_PGM_NG_BUILD_CMDS
++ $(MAKE) $(TARGET_CONFIGURE_OPTS) -C $(@D)
++endef
++
++define SAM7_PGM_NG_INSTALL_TARGET_CMDS
++ $(INSTALL) -D -m 0755 $(@D)/sam7_pgm $(TARGET_DIR)/usr/bin/sam7_pgm
++endef
++
++$(eval $(generic-package))
diff --git a/patches/buildroot/2013.11/cleanup_buildroot.sh b/patches/buildroot/2013.11/cleanup_buildroot.sh
index 6816363..859670a 100755
--- a/patches/buildroot/2013.11/cleanup_buildroot.sh
+++ b/patches/buildroot/2013.11/cleanup_buildroot.sh
@@ -86,3 +86,4 @@ rm -rf buildroot/package/owfs/
rm -rf buildroot/package/agg/
rm -rf buildroot/package/gnash/
rm -rf buildroot/package/xc3sprog/
+rm -rf buildroot/package/sam7-pgm-ng/
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2014-04-30 08:52:52
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 7e5e50485e71b0cbf764a42994ad7a597db59b43 (commit)
from d1f6c82a4db63661dbf78a91664a4c2e98091970 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 7e5e50485e71b0cbf764a42994ad7a597db59b43
Author: Eric Jarrige <eri...@ar...>
Date: Wed Apr 30 10:51:26 2014 +0200
[UBOOT] 2014.04: apf27: support boot from RAM
-----------------------------------------------------------------------
Summary of changes:
.../2014.04/302-apf27-support-boot-from-RAM.patch | 48 ++++++++++++++++++++
1 files changed, 48 insertions(+), 0 deletions(-)
create mode 100644 patches/u-boot/2014.04/302-apf27-support-boot-from-RAM.patch
diff --git a/patches/u-boot/2014.04/302-apf27-support-boot-from-RAM.patch b/patches/u-boot/2014.04/302-apf27-support-boot-from-RAM.patch
new file mode 100644
index 0000000..7f1402e
--- /dev/null
+++ b/patches/u-boot/2014.04/302-apf27-support-boot-from-RAM.patch
@@ -0,0 +1,48 @@
+apf27: Support boot from RAM
+This patch adds capabilites to start U-Boot directly from RAM
+to test a new version of U-Boot before being programmed in FLASH.
+here is a typical use case: run download_uboot ; go a0000000
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+--- a/board/armadeus/apf27/apf27.c
++++ b/board/armadeus/apf27/apf27.c
+@@ -241,10 +241,22 @@ void board_init_f(ulong bootflag)
+ * are 4-byte-aligned.
+ */
+ ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
++ register ulong reg0;
+ asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
+ asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
+ asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
+ asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
++ asm volatile ("mov %0, pc" : "=r"(reg0));
++ if ((reg0 > (ulong)PHYS_SDRAM_1) &&
++ (reg0 < (ulong)(PHYS_SDRAM_2+PHYS_SDRAM_2_SIZE))) {
++ /*
++ * in the case we are already running from RAM we do not need
++ * to load U-Boot from flash - so let's go to U-Boot in RAM.
++ */
++ asm volatile ("ldr %0, =0xfffff800" : "=r"(reg0));
++ asm volatile ("and %0, %0, pc" : "=r"(reg0));
++ asm volatile ("add pc, %0, %1" : : "r" (reg0), "i" (CONFIG_SYS_NAND_U_BOOT_OFFS));
++ }
+ for (dst = start_ptr; dst < end_ptr; dst++)
+ *dst = *(dst+(run_ptr-link_ptr));
+
+--- a/board/armadeus/apf27/lowlevel_init.S
++++ b/board/armadeus/apf27/lowlevel_init.S
+@@ -162,6 +162,13 @@ lowlevel_init:
+ init_aipi
+ init_clock
+ #ifdef CONFIG_SPL_BUILD
++ /* skip sdram initialization if we run from RAM */
++ cmp pc, #PHYS_SDRAM_1
++ bls 1f
++ cmp pc, #(PHYS_SDRAM_2+PHYS_SDRAM_2_SIZE)
++ bhi 1f
++ mov pc, lr
++1:
+ init_ddr
+ #endif
+
hooks/post-receive
--
armadeus
|
|
From: Julien B a. A. <ar...@us...> - 2014-04-28 17:29:25
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via d1f6c82a4db63661dbf78a91664a4c2e98091970 (commit)
from 0a40a8183de15b685842f2083fdc2fd0907c2e7b (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit d1f6c82a4db63661dbf78a91664a4c2e98091970
Author: Julien Boibessot <jul...@ar...>
Date: Mon Apr 28 19:27:46 2014 +0200
[BUILDROOT] xc3sprog: add patch to support XC2C32A_QF32 CPLD
-----------------------------------------------------------------------
Summary of changes:
.../009-armadeus-xc3sprog-new-package.patch | 31 ++++++++++++++++----
1 files changed, 25 insertions(+), 6 deletions(-)
diff --git a/patches/buildroot/2013.11/009-armadeus-xc3sprog-new-package.patch b/patches/buildroot/2013.11/009-armadeus-xc3sprog-new-package.patch
index 92f8bf1..967df6b 100644
--- a/patches/buildroot/2013.11/009-armadeus-xc3sprog-new-package.patch
+++ b/patches/buildroot/2013.11/009-armadeus-xc3sprog-new-package.patch
@@ -1,8 +1,8 @@
Index: buildroot/package/Config.in
===================================================================
---- buildroot.orig/package/Config.in 2014-04-25 15:23:28.394854759 +0200
-+++ buildroot/package/Config.in 2014-04-25 15:24:07.743049855 +0200
-@@ -369,6 +369,7 @@
+--- buildroot.orig/package/Config.in 2014-04-28 17:05:25.543057967 +0200
++++ buildroot/package/Config.in 2014-04-28 17:30:01.914378896 +0200
+@@ -348,6 +348,7 @@
source "package/usbutils/Config.in"
source "package/wipe/Config.in"
source "package/w_scan/Config.in"
@@ -13,7 +13,7 @@ Index: buildroot/package/Config.in
Index: buildroot/package/xc3sprog/Config.in
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ buildroot/package/xc3sprog/Config.in 2014-04-28 11:53:32.522265102 +0200
++++ buildroot/package/xc3sprog/Config.in 2014-04-28 17:05:25.559058040 +0200
@@ -0,0 +1,13 @@
+config BR2_PACKAGE_XC3SPROG
+ bool "xc3sprog"
@@ -31,7 +31,7 @@ Index: buildroot/package/xc3sprog/Config.in
Index: buildroot/package/xc3sprog/xc3sprog.mk
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ buildroot/package/xc3sprog/xc3sprog.mk 2014-04-28 12:41:29.448531008 +0200
++++ buildroot/package/xc3sprog/xc3sprog.mk 2014-04-28 17:05:25.559058040 +0200
@@ -0,0 +1,19 @@
+################################################################################
+#
@@ -55,7 +55,7 @@ Index: buildroot/package/xc3sprog/xc3sprog.mk
Index: buildroot/package/xc3sprog/xc3sprog-fixes-version-detection.patch
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ buildroot/package/xc3sprog/xc3sprog-fixes-version-detection.patch 2014-04-28 12:37:02.587207718 +0200
++++ buildroot/package/xc3sprog/xc3sprog-fixes-version-detection.patch 2014-04-28 17:05:25.559058040 +0200
@@ -0,0 +1,30 @@
+Do not launch 'svn info' if sources directory is not a svn checkout.
+This prevents cmake to fail at configuration stage when building package in BR.
@@ -87,3 +87,22 @@ Index: buildroot/package/xc3sprog/xc3sprog-fixes-version-detection.patch
+ endif(EXISTS ${PROJECT_SOURCE_DIR}/.git)
+
+ # Create suffix to eventually install inlib64
+Index: buildroot/package/xc3sprog/xc3sprog-fixes-xc2c32a_qf32-jtag-id.patch
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ buildroot/package/xc3sprog/xc3sprog-fixes-xc2c32a_qf32-jtag-id.patch 2014-04-28 17:41:46.269871600 +0200
+@@ -0,0 +1,14 @@
++Specific for Armadeus.
++
++Signed-off-by: Fabien Marteau <fab...@ar...>
++
++--- xc3sprog-760.org/devlist.txt 2013-12-09 16:42:42.000000000 +0100
+++++ xc3sprog-760/devlist.txt 2014-04-28 17:36:03.780173296 +0200
++@@ -167,6 +167,7 @@
++ 06c1d093 8 0x1 XC2C32_PC44/64
++ 06c1b093 8 0x1 XC2C32A_QF32
++ 06d1d093 8 0x1 XC2C32A_PC44
+++06e19093 8 0x1 XC2C32A_QF32
++ 06e1b093 8 0x1 XC2C32A_CP56
++ 06e1c093 8 0x1 XC2C32A_VQ44
++ 06e1d093 8 0x1 XC2C32A_PC44/64
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2014-04-28 15:40:37
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 0a40a8183de15b685842f2083fdc2fd0907c2e7b (commit)
from 37a915c3ea610f154512436300d3620af8c04578 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 0a40a8183de15b685842f2083fdc2fd0907c2e7b
Author: Eric Jarrige <eri...@ar...>
Date: Mon Apr 28 17:40:27 2014 +0200
[UBOOT] 2014.04: update apf28 patch
-----------------------------------------------------------------------
Summary of changes:
.../u-boot/2014.04/501-imx28-update-and-fix.patch | 18 +++++++++---------
1 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/patches/u-boot/2014.04/501-imx28-update-and-fix.patch b/patches/u-boot/2014.04/501-imx28-update-and-fix.patch
index 5245f99..aaae42b 100644
--- a/patches/u-boot/2014.04/501-imx28-update-and-fix.patch
+++ b/patches/u-boot/2014.04/501-imx28-update-and-fix.patch
@@ -22,26 +22,26 @@ index c60615a..f533ad0 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
+++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
@@ -3,6 +3,6 @@ SECTION 0x0 BOOTABLE
- LOAD 0x0 spl/u-boot-spl.bin
- LOAD IVT 0x8000 0x14
+ LOAD 0x1000 spl/u-boot-spl.bin
+ LOAD IVT 0x8000 0x1000
CALL HAB 0x8000 0x0
-- LOAD 0x40000100 u-boot.bin
-- LOAD IVT 0x8000 0x40000100
+- LOAD 0x40002000 u-boot.bin
+- LOAD IVT 0x8000 0x40002000
+ LOAD 0x40000000 u-boot.bin
+ LOAD IVT 0x8000 0x40000000
CALL HAB 0x8000 0x0
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
-@@ -81,7 +81,9 @@
- * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
- * binary. In case there was more of this mess, 0x100 bytes are skipped.
+@@ -88,7 +88,9 @@
+ * As for the SPL, we must avoid the first 4 KiB as well, but we load the
+ * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB.
*/
+#ifndef CONFIG_SYS_TEXT_BASE
- #define CONFIG_SYS_TEXT_BASE 0x40000100
+ #define CONFIG_SYS_TEXT_BASE 0x40002000
+#endif
+ #define CONFIG_SPL_TEXT_BASE 0x00001000
/* U-Boot general configuration */
- #define CONFIG_SYS_LONGHELP
diff --git a/common/memsize.c b/common/memsize.c
index 963e4f3..a9f76bc 100644
--- a/common/memsize.c
hooks/post-receive
--
armadeus
|
|
From: Julien B a. A. <ar...@us...> - 2014-04-28 14:14:41
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 37a915c3ea610f154512436300d3620af8c04578 (commit)
from bfa516708940b73797c0d3a3c381b3900cc54d50 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 37a915c3ea610f154512436300d3620af8c04578
Author: Julien Boibessot <jul...@ar...>
Date: Mon Apr 28 16:07:11 2014 +0200
[BUILDROOT] Add xc3sprog package
-----------------------------------------------------------------------
Summary of changes:
.../009-armadeus-xc3sprog-new-package.patch | 89 ++++++++++++++++++++
patches/buildroot/2013.11/cleanup_buildroot.sh | 1 +
2 files changed, 90 insertions(+), 0 deletions(-)
create mode 100644 patches/buildroot/2013.11/009-armadeus-xc3sprog-new-package.patch
diff --git a/patches/buildroot/2013.11/009-armadeus-xc3sprog-new-package.patch b/patches/buildroot/2013.11/009-armadeus-xc3sprog-new-package.patch
new file mode 100644
index 0000000..92f8bf1
--- /dev/null
+++ b/patches/buildroot/2013.11/009-armadeus-xc3sprog-new-package.patch
@@ -0,0 +1,89 @@
+Index: buildroot/package/Config.in
+===================================================================
+--- buildroot.orig/package/Config.in 2014-04-25 15:23:28.394854759 +0200
++++ buildroot/package/Config.in 2014-04-25 15:24:07.743049855 +0200
+@@ -369,6 +369,7 @@
+ source "package/usbutils/Config.in"
+ source "package/wipe/Config.in"
+ source "package/w_scan/Config.in"
++source "package/xc3sprog/Config.in"
+ endmenu
+
+ menu "Interpreter languages and scripting"
+Index: buildroot/package/xc3sprog/Config.in
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ buildroot/package/xc3sprog/Config.in 2014-04-28 11:53:32.522265102 +0200
+@@ -0,0 +1,13 @@
++config BR2_PACKAGE_XC3SPROG
++ bool "xc3sprog"
++ depends on BR2_INSTALL_LIBSTDCPP
++ depends on BR2_TOOLCHAIN_HAS_THREADS # libftdi
++ select BR2_PACKAGE_LIBFTDI
++ help
++ xc3sprog is a suite of utilities for programming Xilinx FPGAs, CPLDs,
++ and EEPROMs with the Xilinx Parallel Cable and other JTAG adapters.
++
++ http://xc3sprog.sourceforge.net/
++
++comment "xc3sprog needs a toolchain w/ C++, threads"
++ depends on !(BR2_INSTALL_LIBSTDCPP && BR2_TOOLCHAIN_HAS_THREADS)
+Index: buildroot/package/xc3sprog/xc3sprog.mk
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ buildroot/package/xc3sprog/xc3sprog.mk 2014-04-28 12:41:29.448531008 +0200
+@@ -0,0 +1,19 @@
++################################################################################
++#
++# xc3sprog
++#
++################################################################################
++
++XC3SPROG_VERSION = 760
++XC3SPROG_SITE = https://svn.code.sf.net/p/xc3sprog/code/trunk
++XC3SPROG_SITE_METHOD = svn
++X3CSPROG_LICENSE = GPLv2+
++X3CSPROG_LICENSE_FILES = COPYING
++X3CSPROG_DEPENDENCIES = libftdi
++
++XC3SPROG_CONF_OPT += \
++ -DVERSION_STRING=0.0-svn$(XC3SPROG_VERSION) \
++ -DCMAKE_EXE_LINKER_FLAGS=-lpthread
++
++$(eval $(cmake-package))
++$(eval $(host-cmake-package))
+Index: buildroot/package/xc3sprog/xc3sprog-fixes-version-detection.patch
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ buildroot/package/xc3sprog/xc3sprog-fixes-version-detection.patch 2014-04-28 12:37:02.587207718 +0200
+@@ -0,0 +1,30 @@
++Do not launch 'svn info' if sources directory is not a svn checkout.
++This prevents cmake to fail at configuration stage when building package in BR.
++
++Signed-off-by: Julien Boibessot <jul...@ar...>
++
++--- xc3sprog-760.org/CMakeLists.txt 2013-12-09 16:42:37.000000000 +0100
+++++ xc3sprog-760/CMakeLists.txt 2014-04-28 11:45:20.899827274 +0200
++@@ -35,13 +35,15 @@
++ if(EXISTS ${PROJECT_SOURCE_DIR}/.git)
++ set(VERSION_STRING "${xc3sprog_VERSION_MAJOR}.${xc3sprog_VERSION_MINOR}-git")
++ else(EXISTS ${PROJECT_SOURCE_DIR}/.git)
++- FIND_PACKAGE(Subversion)
++- IF(Subversion_FOUND)
++- Subversion_WC_INFO(${PROJECT_SOURCE_DIR} Project)
++- set(VERSION_STRING "${xc3sprog_VERSION_MAJOR}.${xc3sprog_VERSION_MINOR}-svn${Project_WC_REVISION}")
++- ELSE(Subversion_FOUND)
++- set(VERSION_STRING "unknown")
++- ENDIF(Subversion_FOUND)
+++ IF(EXISTS ${PROJECT_SOURCE_DIR}/.svn)
+++ FIND_PACKAGE(Subversion)
+++ IF(Subversion_FOUND)
+++ Subversion_WC_INFO(${PROJECT_SOURCE_DIR} Project)
+++ set(VERSION_STRING "${xc3sprog_VERSION_MAJOR}.${xc3sprog_VERSION_MINOR}-svn${Project_WC_REVISION}")
+++ ELSE(Subversion_FOUND)
+++ set(VERSION_STRING "unknown")
+++ ENDIF(Subversion_FOUND)
+++ ENDIF(EXISTS ${PROJECT_SOURCE_DIR}/.svn)
++ endif(EXISTS ${PROJECT_SOURCE_DIR}/.git)
++
++ # Create suffix to eventually install inlib64
diff --git a/patches/buildroot/2013.11/cleanup_buildroot.sh b/patches/buildroot/2013.11/cleanup_buildroot.sh
index 70352f8..6816363 100755
--- a/patches/buildroot/2013.11/cleanup_buildroot.sh
+++ b/patches/buildroot/2013.11/cleanup_buildroot.sh
@@ -85,3 +85,4 @@ rm -rf buildroot/package/uclibc/0.9.33.2/uclibc-0056-assume-accept4-in-recent-ar
rm -rf buildroot/package/owfs/
rm -rf buildroot/package/agg/
rm -rf buildroot/package/gnash/
+rm -rf buildroot/package/xc3sprog/
hooks/post-receive
--
armadeus
|
