[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.3-251-g7738c66
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.3-251-g7738c66
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From: jorasse <jo...@us...> - 2014-05-08 11:21:31
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 7738c667f886fcc458b9c5c3ec40a24146bbb114 (commit)
from c44a8f7b92de3932cad4d1b686b92a78ebd1d0fa (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 7738c667f886fcc458b9c5c3ec40a24146bbb114
Author: Eric Jarrige <eri...@ar...>
Date: Thu May 8 13:21:11 2014 +0200
[UBOOT] 2014.04: apf51: add board configuration
-----------------------------------------------------------------------
Summary of changes:
...f51-u-boot-2013.04.h => apf51-u-boot-2014.04.h} | 150 ++++++++++----------
1 files changed, 78 insertions(+), 72 deletions(-)
copy buildroot/target/device/armadeus/apf51/{apf51-u-boot-2013.04.h => apf51-u-boot-2014.04.h} (88%)
diff --git a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2013.04.h b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2014.04.h
similarity index 88%
copy from buildroot/target/device/armadeus/apf51/apf51-u-boot-2013.04.h
copy to buildroot/target/device/armadeus/apf51/apf51-u-boot-2014.04.h
index 79440f1..b42dc59 100644
--- a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2013.04.h
+++ b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2014.04.h
@@ -35,27 +35,32 @@
* SPL
*/
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
#define CONFIG_SPL_MAX_SIZE 0x4000 /* can be extended to 128kiB */
/* CONFIG_SPL_TEXT_BASE -> IRAM start address available for SPL :
* - 0x1FFE0000 IRAM base address
* - 0x00002000 IRAM space reserved for IPL
- * - 0x00000800 size of SPL DCD header
+ * - 0x00002000 reserve space SPL DCD & header
*/
-#define CONFIG_SPL_TEXT_BASE 0x1FFE2800
+#define CONFIG_SPL_TEXT_BASE 0x1FFE4000
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_RAM_ADDR \
+ CONFIG_SYS_INIT_RAM_SIZE \
- - 0x80000 /* MMU and IPL stack */
+ - 0xC000 /* MMU and IPL stack */
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_RAM_DEVICE
+
/* NAND boot config */
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_MONITOR_OFFSET
+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_LOAD_ADDR
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
/*
@@ -120,7 +125,7 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#define CONFIG_SYS_TEXT_BASE 0x90004000
+#define CONFIG_SYS_TEXT_BASE 0x90004040
/*
* FLASH organization
@@ -391,7 +396,7 @@
*/
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_SYS_PHY_RESET_GPIO IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11)
+#define CONFIG_SYS_PHY_RESET_GPIO IMX_GPIO_NR(3, 0)
#define CONFIG_FEC_MXC_PHYADDR 0x02
#define CONFIG_MII
@@ -410,13 +415,13 @@
#define CONFIG_SYS_FPGA_CHECK_ERROR
/* FPGA program pin configuration */
-#define ACFG_FPGA_PWR MX51_PIN_DI1_D0_CS
-#define ACFG_FPGA_PRG MX51_PIN_CSI2_D12
+#define ACFG_FPGA_PWR IMX_GPIO_NR(3, 3)
+#define ACFG_FPGA_PRG IMX_GPIO_NR(4, 9)
#define ACFG_FPGA_RDATA CS1_BASE_ADDR
#define ACFG_FPGA_WDATA CS1_BASE_ADDR
-#define ACFG_FPGA_INIT MX51_PIN_CSI2_D18
-#define ACFG_FPGA_DONE MX51_PIN_CSI2_D13
-#define ACFG_FPGA_SUSPEND MX51_PIN_DISPB2_SER_DIO
+#define ACFG_FPGA_INIT IMX_GPIO_NR(4, 11)
+#define ACFG_FPGA_DONE IMX_GPIO_NR(4, 10)
+#define ACFG_FPGA_SUSPEND IMX_GPIO_NR(3, 6)
#define ACFG_FPGA_GCR1_VALUE 0x019100bf
#define ACFG_FPGA_GCR2_VALUE 0x00000000
@@ -439,6 +444,8 @@
* I2C
*/
#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
@@ -467,8 +474,8 @@
/*
* Watchdog Config
*/
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_IMX_WATCHDOG
+/*#define CONFIG_HW_WATCHDOG
+#define CONFIG_IMX_WATCHDOG*/
/*
* USB
*/
@@ -476,7 +483,6 @@
/*
* Clocks
*/
-#define CONFIG_SYS_HZ 1000 /* Ticks per second */
#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_SYS_MX5_HCLK 1024*CONFIG_SYS_MX5_CLK32
#define CONFIG_MX51_PLL_ERRATA
@@ -672,89 +678,89 @@
#define ACFG_SDRAM_ESDCDLY5_REGISTER_VAL 0x00F48000
/* SDRAM IO Muxing */
-#define ACFG_IOMUX_PAD_DRAM_RAS PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
-#define ACFG_IOMUX_PAD_DRAM_CAS PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+#define ACFG_IOMUX_PAD_DRAM_RAS PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
+#define ACFG_IOMUX_PAD_DRAM_CAS PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_SDWE \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_SDCKE0 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_SDCKE1 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_SDCLK \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_SDQS0 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PD \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_SDQS1 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PD \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_SDQS2 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PD \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_SDQS3 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PD \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_CS0 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_CS1 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_DQM0 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_DQM1 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_DQM2 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_DRAM_DQM3 \
- PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
- +PAD_CTL_DRV_MAX+PAD_CTL_SRE_SLOW
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP \
+ | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW
#define ACFG_IOMUX_PAD_EIM_SDBA2 \
- PAD_CTL_DRV_VOT_LOW+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
- +PAD_CTL_100K_PU
+ PAD_CTL_DVS | PAD_CTL_PKE | PAD_CTL_PUE \
+ | PAD_CTL_PUS_100K_UP
#define ACFG_IOMUX_PAD_EIM_SDODT1 \
- PAD_CTL_DRV_VOT_LOW+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
- +PAD_CTL_100K_PD+PAD_CTL_DRV_LOW+PAD_CTL_SRE_FAST
+ PAD_CTL_DVS | PAD_CTL_PKE | PAD_CTL_PUE \
+ | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_LOW | PAD_CTL_SRE_FAST
#define ACFG_IOMUX_PAD_EIM_SDODT0 \
- PAD_CTL_DRV_VOT_LOW+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
- +PAD_CTL_100K_PD+PAD_CTL_DRV_LOW+PAD_CTL_SRE_FAST
-
-#define ACFG_IOMUX_GRP_DDRPKS PAD_CTL_PUE_PULL /* imx default */
-#define ACFG_IOMUX_GRP_DRAM_B4 PAD_CTL_DRV_MAX
-#define ACFG_IOMUX_GRP_INDDR PAD_CTL_DDR_INPUT_CMOS /* imx default */
-#define ACFG_IOMUX_GRP_PKEDDR PAD_CTL_PKE_ENABLE /* imx default */
-#define ACFG_IOMUX_GRP_DDR_A0 PAD_CTL_DRV_MAX
-#define ACFG_IOMUX_GRP_DDR_A1 PAD_CTL_DRV_MAX
-#define ACFG_IOMUX_GRP_DDRAPUS PAD_CTL_100K_PU /* imx default */
-#define ACFG_IOMUX_GRP_HYSDDR0 PAD_CTL_HYS_NONE /* imx default */
-#define ACFG_IOMUX_GRP_HYSDDR1 PAD_CTL_HYS_NONE /* imx default */
-#define ACFG_IOMUX_GRP_HYSDDR2 PAD_CTL_HYS_NONE /* imx default */
-#define ACFG_IOMUX_GRP_HVDDR PAD_CTL_DRV_VOT_LOW
-#define ACFG_IOMUX_GRP_HYSDDR3 PAD_CTL_HYS_NONE /* imx default */
+ PAD_CTL_DVS | PAD_CTL_PKE | PAD_CTL_PUE \
+ | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_LOW | PAD_CTL_SRE_FAST
+
+#define ACFG_IOMUX_GRP_DDRPKS PAD_CTL_PUE /* imx default */
+#define ACFG_IOMUX_GRP_DRAM_B4 PAD_CTL_DSE_MAX
+#define ACFG_IOMUX_GRP_INDDR 0 /* imx default */
+#define ACFG_IOMUX_GRP_PKEDDR PAD_CTL_PKE /* imx default */
+#define ACFG_IOMUX_GRP_DDR_A0 PAD_CTL_DSE_MAX
+#define ACFG_IOMUX_GRP_DDR_A1 PAD_CTL_DSE_MAX
+#define ACFG_IOMUX_GRP_DDRAPUS PAD_CTL_PUS_100K_UP /* imx default */
+#define ACFG_IOMUX_GRP_HYSDDR0 0 /* imx default */
+#define ACFG_IOMUX_GRP_HYSDDR1 0 /* imx default */
+#define ACFG_IOMUX_GRP_HYSDDR2 0 /* imx default */
+#define ACFG_IOMUX_GRP_HVDDR PAD_CTL_DVS
+#define ACFG_IOMUX_GRP_HYSDDR3 0 /* imx default */
#define ACFG_IOMUX_GRP_DDR_SR_B0 PAD_CTL_SRE_SLOW
-#define ACFG_IOMUX_GRP_DDRAPKS PAD_CTL_PUE_PULL /* imx default */
+#define ACFG_IOMUX_GRP_DDRAPKS PAD_CTL_PUE /* imx default */
#define ACFG_IOMUX_GRP_DDR_SR_B1 PAD_CTL_SRE_SLOW
-#define ACFG_IOMUX_GRP_DDRPUS PAD_CTL_100K_PU /* imx default */
+#define ACFG_IOMUX_GRP_DDRPUS PAD_CTL_PUS_100K_UP /* imx default */
#define ACFG_IOMUX_GRP_DDR_SR_B2 PAD_CTL_SRE_SLOW
-#define ACFG_IOMUX_GRP_PKEADDR PAD_CTL_PKE_ENABLE /* imx default */
+#define ACFG_IOMUX_GRP_PKEADDR PAD_CTL_PKE /* imx default */
#define ACFG_IOMUX_GRP_DDR_SR_B4 PAD_CTL_SRE_SLOW
-#define ACFG_IOMUX_GRP_INMODE1 PAD_CTL_DDR_INPUT_CMOS /* imx default */
-#define ACFG_IOMUX_GRP_DRAM_B0 PAD_CTL_DRV_MAX
-#define ACFG_IOMUX_GRP_DRAM_B1 PAD_CTL_DRV_MAX
+#define ACFG_IOMUX_GRP_INMODE1 0 /* imx default */
+#define ACFG_IOMUX_GRP_DRAM_B0 PAD_CTL_DSE_MAX
+#define ACFG_IOMUX_GRP_DRAM_B1 PAD_CTL_DSE_MAX
#define ACFG_IOMUX_GRP_DDR_SR_A0 PAD_CTL_SRE_SLOW
-#define ACFG_IOMUX_GRP_DRAM_B2 PAD_CTL_DRV_MAX
+#define ACFG_IOMUX_GRP_DRAM_B2 PAD_CTL_DSE_MAX
#define ACFG_IOMUX_GRP_DDR_SR_A1 PAD_CTL_SRE_SLOW
/* end of SDRAM IO Muxing */
hooks/post-receive
--
armadeus
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