[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.3-250-gc44a8f7
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.3-250-gc44a8f7
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From: jorasse <jo...@us...> - 2014-05-08 11:19:21
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via c44a8f7b92de3932cad4d1b686b92a78ebd1d0fa (commit)
from ad1ef8252c2900310adc0d07fd43f4f69c7fb0bf (commit)
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not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit c44a8f7b92de3932cad4d1b686b92a78ebd1d0fa
Author: Eric Jarrige <eri...@ar...>
Date: Thu May 8 13:18:59 2014 +0200
[UBOOT] 2014.04: add apf51 patchwork
-----------------------------------------------------------------------
Summary of changes:
patches/u-boot/2014.04/400-imx51.patch | 1176 +++++++++++++++++
patches/u-boot/2014.04/401-apf51.patch | 1339 ++++++++++++++++++++
.../u-boot/{2013.04 => 2014.04}/410-imx-iim.patch | 107 +--
patches/u-boot/2014.04/420-apf51-nand-spl-NG.patch | 399 ++++++
4 files changed, 2945 insertions(+), 76 deletions(-)
create mode 100644 patches/u-boot/2014.04/400-imx51.patch
create mode 100644 patches/u-boot/2014.04/401-apf51.patch
copy patches/u-boot/{2013.04 => 2014.04}/410-imx-iim.patch (76%)
create mode 100644 patches/u-boot/2014.04/420-apf51-nand-spl-NG.patch
diff --git a/patches/u-boot/2014.04/400-imx51.patch b/patches/u-boot/2014.04/400-imx51.patch
new file mode 100644
index 0000000..acc3410
--- /dev/null
+++ b/patches/u-boot/2014.04/400-imx51.patch
@@ -0,0 +1,1176 @@
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+---
+ arch/arm/cpu/armv7/cpu.c
+ arch/arm/cpu/armv7/mx5/lowlevel_init.S
+ arch/arm/include/asm/arch-mx5/imx-regs.h
+ arch/arm/include/asm/arch-mx5/mx5x_pins.h
+ arch/arm/include/asm/arch-mx5/regs_esdctl.h
+
+diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
+index 39a8023..c8c2293 100644
+--- a/arch/arm/cpu/armv7/cpu.c
++++ b/arch/arm/cpu/armv7/cpu.c
+@@ -82,5 +82,9 @@ int cleanup_before_linux(void)
+ */
+ cpu_cache_initialization();
+
++#ifndef CONFIG_L2_OFF
++/* v7_outer_cache_enable();*/
++#endif
++
+ return 0;
+ }
+diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+index a40b84f..1ca9b22 100644
+--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
++++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+@@ -24,6 +24,34 @@
+ #include <generated/asm-offsets.h>
+ #include <linux/linkage.h>
+
++#ifndef CONFIG_SYS_PLL_DP_CTL
++/* use internal oscillator */
++#define CONFIG_SYS_PLL_DP_CTL 0x00001232
++#endif
++
++#ifndef CONFIG_SYS_CLKCTL_CCSR
++/* use internal oscillator */
++#define CONFIG_SYS_CLKCTL_CCSR 0x00000000
++#endif
++
++#ifndef CONFIG_SYS_CLKTL_CBCDR
++#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
++#endif
++
++#ifndef CONFIG_SYS_CLKTL_CBCMR
++/* Use lp_apm (24MHz) source for perclk */
++#define CONFIG_SYS_CLKTL_CBCMR 0x000020C2
++#endif
++
++#ifndef CONFIG_SYS_CLKTL_CSCDR1
++#define CONFIG_SYS_CLKTL_CSCDR1 0x00C30321
++#endif
++
++#ifndef CONFIG_SYS_CLKTL_CBCMR1
++/* Use PLL 2 for UART's, get 66.5MHz from it */
++#define CONFIG_SYS_CLKTL_CBCMR1 0xA5A2A020
++#endif
++
+ .section ".text.init", "x"
+
+ .macro init_arm_erratum
+@@ -114,7 +142,7 @@
+ #define W_DP_MFN 8
+
+ setup_pll_func:
+- ldr r1, =0x00001232
++ ldr r1, =CONFIG_SYS_PLL_DP_CTL
+ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+ mov r1, #0x2
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+@@ -131,7 +159,7 @@
+ str r1, [r0, #PLL_DP_MFN]
+ str r1, [r0, #PLL_DP_HFS_MFN]
+
+- ldr r1, =0x00001232
++ ldr r1, =CONFIG_SYS_PLL_DP_CTL
+ str r1, [r0, #PLL_DP_CTL]
+ 1: ldr r1, [r0, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+@@ -143,7 +171,7 @@
+ .macro setup_pll_errata pll, freq
+ ldr r2, =\pll
+ str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
+- ldr r1, =0x00001236
++ ldr r1, =CONFIG_SYS_PLL_DP_CTL | 0x04
+ str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
+ 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
+ ands r1, r1, #0x1
+@@ -172,6 +200,16 @@
+ #if defined (CONFIG_MX51)
+ ldr r0, =CCM_BASE_ADDR
+
++#ifdef CONFIG_SYS_CLKCTL_CCMR
++ ldr r1, =CONFIG_SYS_CLKCTL_CCMR
++ str r1, [r0, #CLKCTL_CCMR]
++
++ /* make sure clocks are ready */
++1: ldr r1, [r0, #CLKCTL_CSR]
++ cmp r1, #CONFIG_SYS_CLKCTL_CSR
++ bne 1b
++#endif
++
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+@@ -199,7 +237,7 @@
+ bne 1b
+
+ /* Switch ARM to step clock */
+- mov r1, #0x4
++ mov r1, #CONFIG_SYS_CLKCTL_CCSR | 0x04
+ str r1, [r0, #CLKCTL_CCSR]
+
+ #if defined(CONFIG_MX51_PLL_ERRATA)
+@@ -244,13 +282,14 @@
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1 */
++ mov r1, #CONFIG_SYS_CLKCTL_CCSR
+- str r4, [r0, #CLKCTL_CCSR]
++ str r1, [r0, #CLKCTL_CCSR]
+
+ /* setup the rest */
+- /* Use lp_apm (24MHz) source for perclk */
+- ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
++ /* select source for perclk */
++ ldr r1, =CONFIG_SYS_CLKTL_CBCMR | CONFIG_SYS_DDR_CLKSEL
+ str r1, [r0, #CLKCTL_CBCMR]
+- /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
++ /* ddr clock from PLL 1 */
+ ldr r1, =CONFIG_SYS_CLKTL_CBCDR
+ str r1, [r0, #CLKCTL_CBCDR]
+
+@@ -265,9 +304,9 @@
+ str r1, [r0, #CLKCTL_CCGR6]
+
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+- ldr r1, =0xA5A2A020
++ ldr r1, =CONFIG_SYS_CLKTL_CBCMR1
+ str r1, [r0, #CLKCTL_CSCMR1]
+- ldr r1, =0x00C30321
++ ldr r1, =CONFIG_SYS_CLKTL_CSCDR1
+ str r1, [r0, #CLKCTL_CSCDR1]
+ /* make sure divider effective */
+ 1: ldr r1, [r0, #CLKCTL_CDHIPR]
+diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
+index 46017f4..520bf98 100644
+--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
++++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
+@@ -267,6 +267,7 @@
+ #define M4IF_FBPM0 0x40
+ #define M4IF_FIDBP 0x48
+
++#ifndef DP_OP_800
+ /* Assuming 24MHz input clock with doubler ON */
+ /* MFI PDF */
+ #define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
+@@ -305,6 +306,7 @@
+ #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
+ #define DP_MFD_216 (4 - 1)
+ #define DP_MFN_216 3
++#endif /* DP_OP_800 */
+
+ #define CHIP_REV_1_0 0x10
+ #define CHIP_REV_1_1 0x11
+diff --git a/arch/arm/include/asm/arch-mx5/regs_esdctl.h b/arch/arm/include/asm/arch-mx5/regs_esdctl.h
+new file mode 100644
+index 0000000..1c0bf8e
+--- /dev/null
++++ b/arch/arm/include/asm/arch-mx5/regs_esdctl.h
+@@ -0,0 +1,114 @@
++/*
++ * Copyright (C) 2012 Eric Jarrige <eri...@ar...>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++
++#ifndef __REGS_ESDCTL_H__
++#define __REGS_ESDCTL_H__
++
++
++#ifndef __ASSEMBLY__
++/* ESDCTL registers */
++#if defined(CONFIG_MX51)
++struct esdctl_regs {
++ u32 esdctl0;
++ u32 esdcfg0;
++ u32 esdctl1;
++ u32 esdcfg1;
++ u32 esdmisc;
++ u32 esdscr;
++ u32 reserved[2];
++ u32 esdcdly1;
++ u32 esdcdly2;
++ u32 esdcdly3;
++ u32 esdcdly4;
++ u32 esdcdly5;
++ u32 esdgpr;
++ u32 esdprct0;
++ u32 esdprct1;
++};
++#elif defined(CONFIG_MX53)
++struct esdctl_regs {
++ u32 esdctl;
++ u32 esdpdc;
++ u32 esdotc;
++ u32 esdcfg0;
++ u32 esdcfg1;
++ u32 esdcfg2;
++ u32 esdmisc;
++ u32 esdscr;
++ u32 esdref;
++ u32 esdwcc;
++ u32 esdrcc;
++ u32 esdrwd;
++ u32 esdor;
++ u32 esdmrr;
++ u32 esdcfg3_lp;
++ u32 esdmr4;
++ u32 zqhwctrl;
++ u32 zqswctrl;
++ u32 wlgcr;
++ u32 wldectrl0;
++ u32 wldectrl1;
++ u32 wldlst;
++ u32 odtctrl;
++ u32 rddqby0dl;
++ u32 rddqby1dl;
++ u32 rddqby2dl;
++ u32 rddqby3dl;
++ u32 wrdqby0dl;
++ u32 wrdqby1dl;
++ u32 wrdqby2dl;
++ u32 wrdqby3dl;
++ u32 dgctrl0;
++ u32 dgctrl1;
++ u32 dgdlst;
++ u32 rddlctl;
++ u32 rddlst;
++ u32 wrlctl;
++ u32 wrlst;
++ u32 sdctrl;
++ u32 zqlp2ctl;
++ u32 rddlhwctl;
++ u32 wrdlhwctl;
++ u32 rddlhwst0;
++ u32 rddlhwst1;
++ u32 wrdlhwst0;
++ u32 wrdlhwst1;
++ u32 wlhwerr;
++ u32 dghwst0;
++ u32 dghwst1;
++ u32 dghwst2;
++ u32 dghwst3;
++ u32 pdcmpr1;
++ u32 pdcmpr2;
++ u32 swdar;
++ u32 swdrdr0;
++ u32 swdrdr1;
++ u32 swdrdr2;
++ u32 swdrdr3;
++ u32 swdrdr4;
++ u32 swdrdr5;
++ u32 swdrdr6;
++ u32 swdrdr7;
++ u32 mur;
++ u32 wrcadl;
++};
++#endif
++
++#endif /* __ASSEMBLY__ */
++
++/* DDR commands */
++/* cs ChipSelect in range of 0..1 */
++/* ba Bank Address in range of 0..3 */
++/* addr Pseudo Address as expected by the DDR */
++
++#define DDR_NOP_CMD(cs) (0x00008000 + (cs << 2))
++#define DRR_PRECHARGE_CMD(cs, ba) (0x04008008 + (cs << 2) + ba)
++#define DRR_AUTOREFRESH_CMD(cs) (0x00008010 + (cs << 2))
++#define DRR_LMR_CMD(cs, ba, addr) (0x00008018 + (addr << 16)\
++ + (cs << 2) + ba)
++
++#endif /* __REGS_ESDCTL_H__ */
+--- /dev/null
++++ b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
+@@ -0,0 +1,884 @@
++/*
++ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__
++#define __ASM_ARCH_MX5_MX5X_PINS_H__
++
++#ifndef __ASSEMBLY__
++
++/*
++ * In order to identify pins more effectively, each mux-controlled pin's
++ * enumerated value is constructed in the following way:
++ *
++ * -------------------------------------------------------------------
++ * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0
++ * -------------------------------------------------------------------
++ * IO_P | IO_I | GPIO_I | PAD_I | MUX_I
++ * -------------------------------------------------------------------
++ *
++ * Bit 0 to 9 contains MUX_I used to identify the register
++ * offset (0-based. base is IOMUX_module_base) defined in the Section
++ * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
++ * similar field definitions are used for the pad control register.
++ * The IOMUX controller can be split in two parts. At the begeinning,
++ * there is the register definitions for the multiplexing each pin.
++ * Then there is a set of registers (PAD_I) to configure each pin
++ * (pullup, pulldown, etc).
++ * PAD_I defines the offset of the pad register for each pin.
++ * GPIO_I defines, if available, the number of gpio that can be
++ * connected to that pad
++ * IO_I defines the multiplexer mode required to set the pad in gpio mode
++ * IO_P defines the gpio structure (gpio1..gpio4) the pad belongs
++ *
++ * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
++ * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
++ * It means the mux control register is at register offset 0x28. The pad control
++ * register offset is: 0x250 and also occupy the least significant bits
++ * within the register.
++ */
++
++/*!
++ * Starting bit position within each entry of \b iomux_pins to represent the
++ * MUX control register offset
++ */
++#define MUX_I 0
++/*!
++ * Starting bit position within each entry of \b iomux_pins to represent the
++ * PAD control register offset
++ */
++#define PAD_I 10
++/*!
++ * Starting bit position within each entry of \b iomux_pins to represent which
++ * mux mode is for GPIO (0-based)
++ */
++#define GPIO_I 21
++
++#define MUX_IO_P 29
++#define MUX_IO_I 24
++#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
++ GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
++ ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
++#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
++
++#define NON_GPIO_PORT 0x7
++#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
++#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
++#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
++
++#define NON_MUX_I PIN_TO_MUX_MASK
++#define NON_PAD_I PIN_TO_PAD_MASK
++
++#if defined(CONFIG_MX51)
++#define MUX_I_START 0x001C
++#define PAD_I_START 0x3F0
++#define INPUT_CTL_START 0x8C4
++#define MUX_I_END (PAD_I_START - 4)
++#elif defined(CONFIG_MX53)
++#define MUX_I_START 0x0020
++#define PAD_I_START 0x348
++#define INPUT_CTL_START 0x730
++#define MUX_I_END (PAD_I_START - 4)
++#else
++#error "CPU_TYPE not defined"
++#endif
++
++#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
++ (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
++ ((mi) << MUX_I) | \
++ ((pi - PAD_I_START) << PAD_I) | \
++ ((ga) << GPIO_I))
++
++#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
++ _MXC_BUILD_PIN(gp, gi, ga, mi, pi)
++
++#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
++ _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
++
++#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
++#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
++#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
++#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
++
++/*
++ * This enumeration is constructed based on the Section
++ * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
++ * value is constructed based on the rules described above.
++ */
++enum {
++ MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
++ MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
++ MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
++ MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
++ MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
++ MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
++ MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
++ MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
++ MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
++ MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
++ MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
++ MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
++ MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
++ MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
++ MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
++ MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
++ MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
++ MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
++ MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
++ MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
++ MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
++ MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
++ MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
++ MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
++ MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
++ MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
++ MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
++ MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
++ MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
++ MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
++ MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
++ MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
++ MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
++ MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
++ MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
++ MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
++ MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
++ MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
++ MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
++ MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
++ MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
++ MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
++ MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
++ MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
++ MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
++ MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
++ MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
++ MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
++ MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
++ MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
++ MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
++ MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
++ MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
++ MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
++ MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
++ MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
++ MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
++ MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
++ MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
++ MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
++ MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
++ MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
++ MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
++ MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
++ MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
++ MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
++ MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
++ MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
++ MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514),
++ MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
++ MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
++ MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
++ MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
++ MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
++ MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
++ MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
++ MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
++ MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
++ MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
++ MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
++ MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
++ MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
++ MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
++ MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
++ MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
++ MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
++ MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
++ MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
++ MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
++ MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
++ MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
++ MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
++ MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
++ MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
++ MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
++ MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
++ MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
++ MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
++ MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
++ MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
++ MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
++ MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
++ MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
++ MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
++ MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
++ MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
++ MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
++ MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
++ MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
++ MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
++ MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC),
++ MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0),
++ MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
++ MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
++ MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
++ MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
++ MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
++ MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4),
++ MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8),
++ MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC),
++ MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0),
++ MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
++ MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
++ MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
++ MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
++ MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
++ MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
++ MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
++ MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
++ MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
++ MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
++ MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
++ MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
++ MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
++ MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
++ MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
++ MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
++ MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
++ MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
++ MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
++ MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
++ MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
++ MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
++ MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
++ MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
++ MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
++ MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
++ MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
++ MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
++ MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
++ MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
++ MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
++ MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
++ MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
++ MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
++ MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
++ MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
++ MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
++ MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
++ MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
++ MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
++ MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
++ MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
++ MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
++ MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
++ MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
++ MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
++ MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
++ MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
++ MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
++ MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
++ MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
++ MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
++ MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
++ MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
++ MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
++ MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
++ MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
++ MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
++ MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
++ MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
++ MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
++ MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
++ MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
++ MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
++ MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
++ MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
++ MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
++ MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
++ MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
++ MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
++ MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
++ MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
++ MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
++ MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
++ MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
++ MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
++ MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
++ MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
++ MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
++ MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
++ MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
++ MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
++ MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
++ MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
++ MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
++ MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
++ MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
++ MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
++ MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
++ MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
++ MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
++ MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
++ MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
++ MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
++ MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
++ MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
++ MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
++ MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
++ MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
++ MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
++ MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
++ MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
++ MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
++ MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788),
++ MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
++ MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
++ MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
++ MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
++ MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
++ MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
++ MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
++ MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
++ MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
++ MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
++ MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
++ MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
++ MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
++ MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
++ MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
++ MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
++ MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
++ MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
++ MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
++ MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
++ MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
++ MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
++ MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
++ MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
++ MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
++ MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
++ MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
++
++ /* The following are PADS used for drive strength */
++
++ MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820),
++ MX51_PIN_CTL_GRP_INDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x830),
++ MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838),
++ MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890),
++ MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C),
++ MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C),
++ MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884),
++ MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C),
++ MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864),
++ MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C),
++ MX51_PIN_CTL_GRP_HVDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x870),
++ MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874),
++ MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878),
++ MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880),
++ MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C),
++ MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C),
++ MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4),
++ MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC),
++ MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8),
++ MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C),
++ MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0),
++ MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0),
++ MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4),
++ MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC),
++ MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C),
++ MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848),
++ MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868),
++ MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4),
++ MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8),
++ MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac),
++ MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0),
++ MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4),
++ MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8),
++ MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC),
++ MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0),
++ MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4),
++ MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8),
++ MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC),
++ MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0),
++ MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4),
++ MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8),
++ MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC),
++ MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
++ MX51_PIN_CTL_PAD_EIM_SDBA2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x508),
++ MX51_PIN_CTL_PAD_EIM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x50C),
++ MX51_PIN_CTL_PAD_EIM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x510),
++};
++
++enum {
++ MX53_PIN_GPIO_19 = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348),
++ MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C),
++ MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350),
++ MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354),
++ MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358),
++ MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C),
++ MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360),
++ MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364),
++ MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368),
++ MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C),
++ MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370),
++ MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374),
++ MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378),
++ MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C),
++ MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380),
++ MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384),
++ MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388),
++ MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C),
++ MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390),
++ MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394),
++ MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398),
++ MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C),
++ MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0),
++ MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4),
++ MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8),
++ MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC),
++ MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0),
++ MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4),
++ MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8),
++ MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC),
++ MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0),
++ MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4),
++ MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8),
++ MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC),
++ MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0),
++ MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4),
++ MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8),
++ MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC),
++ MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0),
++ MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4),
++ MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8),
++ MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC),
++ MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0),
++ MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4),
++ MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8),
++ MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC),
++ MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400),
++ MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404),
++ MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408),
++ MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C),
++ MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410),
++ MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414),
++ MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418),
++ MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C),
++ MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420),
++ MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424),
++ MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428),
++ MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C),
++ MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430),
++ MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434),
++ MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438),
++ MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C),
++ MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440),
++ MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444),
++ MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448),
++ MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C),
++ MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450),
++ MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454),
++ MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458),
++ MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C),
++ MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460),
++ MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464),
++ MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468),
++ MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C),
++ MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470),
++ MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474),
++ MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478),
++ MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C),
++ MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480),
++ MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484),
++ MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488),
++ MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C),
++ MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490),
++ MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494),
++ MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498),
++ MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C),
++ MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0),
++ MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4),
++ MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8),
++ MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC),
++ MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0),
++ MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4),
++ MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8),
++ MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC),
++ MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0),
++ MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4),
++ MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8),
++ MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC),
++ MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0),
++ MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4),
++ MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8),
++ MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC),
++ MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0),
++ MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4),
++ MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8),
++ MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC),
++ MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0),
++ MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4),
++ MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8),
++ MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC),
++ MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500),
++ MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504),
++ MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508),
++ MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C),
++ MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510),
++ MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514),
++ MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518),
++ MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C),
++ MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520),
++ MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524),
++ MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528),
++ MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C),
++ MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530),
++ MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534),
++ MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538),
++ MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C),
++ MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I),
++ MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I),
++ MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I),
++ MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I),
++ MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I),
++ MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I),
++ MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I),
++ MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I),
++ MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I),
++ MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I),
++ MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540),
++ MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544),
++ MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548),
++ MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C),
++ MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550),
++ MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554),
++ MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558),
++ MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C),
++ MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560),
++ MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564),
++ MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568),
++ MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C),
++ MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570),
++ MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574),
++ MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578),
++ MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C),
++ MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580),
++ MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584),
++ MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588),
++ MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C),
++ MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590),
++ MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594),
++ MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598),
++ MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C),
++ MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0),
++ MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4),
++ MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8),
++ MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC),
++ MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0),
++ MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4),
++ MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8),
++ MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC),
++ MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0),
++ MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4),
++ MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8),
++ MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC),
++ MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0),
++ MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4),
++ MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8),
++ MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC),
++ MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0),
++ MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4),
++ MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8),
++ MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC),
++ MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0),
++ MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4),
++ MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8),
++ MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC),
++ MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600),
++ MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604),
++ MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608),
++ MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C),
++ MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610),
++ MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614),
++ MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618),
++ MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C),
++ MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620),
++ MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624),
++ MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628),
++ MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C),
++ MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630),
++ MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634),
++ MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638),
++ MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C),
++ MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640),
++ MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644),
++ MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648),
++ MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C),
++ MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650),
++ MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654),
++ MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658),
++ MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C),
++ MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660),
++ MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664),
++ MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668),
++ MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C),
++ MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670),
++ MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674),
++ MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678),
++ MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C),
++ MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680),
++ MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684),
++ MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688),
++ MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C),
++ MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690),
++ MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694),
++ MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698),
++ MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C),
++ MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0),
++ MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4),
++ MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8),
++ MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC),
++ MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0),
++ MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4),
++ MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8),
++ MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC),
++ MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0),
++ MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4),
++ MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8),
++ MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC),
++ MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0),
++ MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4),
++ MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8),
++ MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC),
++ MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0),
++ MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4),
++ MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8),
++ MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC),
++ MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0),
++ MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4),
++ MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC),
++ MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708),
++ MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C),
++ MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710),
++ MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714),
++ MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718),
++ MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C),
++ MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720),
++ MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724),
++ MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728),
++ MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C),
++};
++/* various IOMUX input select register index */
++typedef enum iomux_input_select {
++ MX51_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
++ MX51_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
++ MX51_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
++ MX51_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
++ MX51_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
++ MX51_CCM_IPP_DI_CLK_SELECT_INPUT,
++ /* TO2 */
++ MX51_CCM_IPP_DI1_CLK_SELECT_INPUT,
++ MX51_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
++ MX51_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
++ MX51_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
++ MX51_CSPI_IPP_IND_MISO_SELECT_INPUT,
++ MX51_CSPI_IPP_IND_MOSI_SELECT_INPUT,
++ MX51_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
++ MX51_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
++ MX51_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
++ MX51_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
++ /* TO2 */
++ MX51_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
++ MX51_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
++ MX51_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
++ MX51_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
++ MX51_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
++ MX51_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
++ MX51_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
++ MX51_FEC_FEC_COL_SELECT_INPUT,
++ MX51_FEC_FEC_CRS_SELECT_INPUT,
++ MX51_FEC_FEC_MDI_SELECT_INPUT,
++ MX51_FEC_FEC_RDATA_0_SELECT_INPUT,
++ MX51_FEC_FEC_RDATA_1_SELECT_INPUT,
++ MX51_FEC_FEC_RDATA_2_SELECT_INPUT,
++ MX51_FEC_FEC_RDATA_3_SELECT_INPUT,
++ MX51_FEC_FEC_RX_CLK_SELECT_INPUT,
++ MX51_FEC_FEC_RX_DV_SELECT_INPUT,
++ MX51_FEC_FEC_RX_ER_SELECT_INPUT,
++ MX51_FEC_FEC_TX_CLK_SELECT_INPUT,
++ MX51_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
++ MX51_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
++ MX51_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
++ MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
++ MX51_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
++ MX51_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
++ MX51_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
++ MX51_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
++ /* TO2 */
++ MX51_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
++ MX51_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
++ MX51_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
++ /* TO2 */
++ MX51_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
++ /* TO2 */
++ MX51_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
++ MX51_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
++ MX51_I2C1_IPP_SCL_IN_SELECT_INPUT,
++ MX51_I2C1_IPP_SDA_IN_SELECT_INPUT,
++ MX51_I2C2_IPP_SCL_IN_SELECT_INPUT,
++ MX51_I2C2_IPP_SDA_IN_SELECT_INPUT,
++ MX51_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
++ MX51_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
++ MX51_KPP_IPP_IND_COL_6_SELECT_INPUT,
++ MX51_KPP_IPP_IND_COL_7_SELECT_INPUT,
++ MX51_KPP_IPP_IND_ROW_4_SELECT_INPUT,
++ MX51_KPP_IPP_IND_ROW_5_SELECT_INPUT,
++ MX51_KPP_IPP_IND_ROW_6_SELECT_INPUT,
++ MX51_KPP_IPP_IND_ROW_7_SELECT_INPUT,
++ MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
++ MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
++ MX51_UART2_IPP_UART_RTS_B_SELECT_INPUT,
++ MX51_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
++ MX51_UART3_IPP_UART_RTS_B_SELECT_INPUT,
++ MX51_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
++ MX51_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
++ MX51PUT_NUM_MUX,
++ /* MX53 */
++ MX53_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
++ MX53_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
++ MX53_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
++ MX53_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
++ MX53_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
++ MX53_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
++ MX53_AUDMUX_P5_INPUT_DA_AMX_SELECT_I,
++ MX53_AUDMUX_P5_INPUT_DB_AMX_SELECT_I,
++ MX53_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
++ MX53_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT,
++ MX53_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
++ MX53_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
++ MX53_CAN1_IPP_IND_CANRX_SELECT_INPUT,
++ MX53_CAN2_IPP_IND_CANRX_SELECT_INPUT,
++ MX53_CCM_IPP_ASRC_EXT_SELECT_INPUT,
++ MX53_CCM_IPP_DI1_CLK_SELECT_INPUT,
++ MX53_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
++ MX53_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
++ MX53_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
++ MX53_CCM_PLL4_BYPASS_CLK_SELECT_INPUT,
++ MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
++ MX53_CSPI_IPP_IND_MISO_SELECT_INPUT,
++ MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT,
++ MX53_CSPI_IPP_IND_SS_B_0_SELECT_INPUT,
++ MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
++ MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
++ MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
++ MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
++ MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
++ MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
++ MX53_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT,
++ MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
++ MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
++ MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT,
++ MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
++ MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
++ MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
++ MX53_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT,
++ MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_FST_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_SCKT_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
++ MX53_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
++ MX53_ESDHC1_IPP_WP_ON_SELECT_INPUT,
++ MX53_FEC_FEC_COL_SELECT_INPUT,
++ MX53_FEC_FEC_MDI_SELECT_INPUT,
++ MX53_FEC_FEC_RX_CLK_SELECT_INPUT,
++ MX53_FIRI_IPP_IND_RXD_SELECT_INPUT,
++ MX53_GPC_PMIC_RDY_SELECT_INPUT,
++ MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
++ MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
++ MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
++ MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
++ MX53_I2C3_IPP_SCL_IN_SELECT_INPUT,
++ MX53_I2C3_IPP_SDA_IN_SELECT_INPUT,
++ MX53_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
++ MX53_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
++ MX53_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
++ MX53_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT,
++ MX53_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT,
++ MX53_KPP_IPP_IND_COL_5_SELECT_INPUT,
++ MX53_KPP_IPP_IND_COL_6_SELECT_INPUT,
++ MX53_KPP_IPP_IND_COL_7_SELECT_INPUT,
++ MX53_KPP_IPP_IND_ROW_5_SELECT_INPUT,
++ MX53_KPP_IPP_IND_ROW_6_SELECT_INPUT,
++ MX53_KPP_IPP_IND_ROW_7_SELECT_INPUT,
++ MX53_MLB_MLBCLK_IN_SELECT_INPUT,
++ MX53_MLB_MLBDAT_IN_SELECT_INPUT,
++ MX53_MLB_MLBSIG_IN_SELECT_INPUT,
++ MX53_OWIRE_BATTERY_LINE_IN_SELECT_INPUT,
++ MX53_SDMA_EVENTS_14_SELECT_INPUT,
++ MX53_SDMA_EVENTS_15_SELECT_INPUT,
++ MX53_SPDIF_SPDIF_IN1_SELECT_INPUT,
++ MX53_UART1_IPP_UART_RTS_B_SELECT_INPUT,
++ MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
++ MX53_UART2_IPP_UART_RTS_B_SELECT_INPUT,
++ MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
++ MX53_UART3_IPP_UART_RTS_B_SELECT_INPUT,
++ MX53_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
++ MX53_UART4_IPP_UART_RTS_B_SELECT_INPUT,
++ MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
++ MX53_UART5_IPP_UART_RTS_B_SELECT_INPUT,
++ MX53_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
++ MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT,
++ MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT,
++ MX53_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT,
++} iomux_input_select_t;
++
++#endif /* __ASSEMBLY__ */
++#endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */
+--
+1.7.2.5
+
diff --git a/patches/u-boot/2014.04/401-apf51.patch b/patches/u-boot/2014.04/401-apf51.patch
new file mode 100644
index 0000000..9ca4ad4
--- /dev/null
+++ b/patches/u-boot/2014.04/401-apf51.patch
@@ -0,0 +1,1339 @@
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Nicolas Colombain <nic...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+---
+ board/armadeus/apf51/Makefile | 43 ++
+ board/armadeus/apf51/apf51.c | 1222 +++++++++++++++++++++++++++++++++++++++++
+ board/armadeus/apf51/fpga.c | 266 +++++++++
+ board/armadeus/apf51/fpga.h | 39 ++
+ boards.cfg | 1 +
+ 5 files changed, 1571 insertions(+), 0 deletions(-)
+ create mode 100644 board/armadeus/apf51/Makefile
+ create mode 100644 board/armadeus/apf51/apf51.c
+ create mode 100644 board/armadeus/apf51/fpga.c
+ create mode 100644 board/armadeus/apf51/fpga.h
+
+diff --git a/board/armadeus/apf51/Makefile b/board/armadeus/apf51/Makefile
+new file mode 100644
+index 0000000..9d94f74
+--- /dev/null
++++ b/board/armadeus/apf51/Makefile
+@@ -0,0 +1,9 @@
++#
++# (C) Copyright 2000-2006
++# Wolfgang Denk, DENX Software Engineering, wd...@de....
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y := apf51.o fpga.o
++
+diff --git a/board/armadeus/apf51/apf51.c b/board/armadeus/apf51/apf51.c
+new file mode 100644
+index 0000000..8ff1381
+--- /dev/null
++++ b/board/armadeus/apf51/apf51.c
+@@ -0,0 +1,999 @@
++/*
++ * Armadeus APF51 baseboard
++ *
++ * (C) Copyright 2010-2014 Eric Jarrige, Armadeus Project
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <command.h>
++#include <environment.h>
++#include <asm/armv7.h...
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