[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.3-256-g709048b
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.3-256-g709048b
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From: jorasse <jo...@us...> - 2014-05-11 10:31:27
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 709048bb3c1003066027979b593fe70b5f5bf41e (commit)
from 15e47cfd2f6345caf2d097450a25812dd7117681 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 709048bb3c1003066027979b593fe70b5f5bf41e
Author: Eric Jarrige <eri...@ar...>
Date: Sun May 11 12:31:14 2014 +0200
[UBOOT] 2014.04: apf51: cleanup
-----------------------------------------------------------------------
Summary of changes:
patches/u-boot/2014.04/401-apf51.patch | 202 +-------------------------------
1 files changed, 1 insertions(+), 201 deletions(-)
diff --git a/patches/u-boot/2014.04/401-apf51.patch b/patches/u-boot/2014.04/401-apf51.patch
index 57baa3c..1e09789 100644
--- a/patches/u-boot/2014.04/401-apf51.patch
+++ b/patches/u-boot/2014.04/401-apf51.patch
@@ -33,7 +33,7 @@ new file mode 100644
index 0000000..8ff1381
--- /dev/null
+++ b/board/armadeus/apf51/apf51.c
-@@ -0,0 +1,884 @@
+@@ -0,0 +1,684 @@
+/*
+ * Armadeus APF51 baseboard
+ *
@@ -718,206 +718,6 @@ index 0000000..8ff1381
+ asm("mcr 15, 0, r0, c1, c0, 1");
+}
+#endif
-+
-+#if defined(CONFIG_CMD_BSP)
-+/*
-+ * display dcd table. to delete
-+ */
-+int do_mx51_show_dcd_tab(cmd_tbl_t *cmdtp, int flag, int argc,
-+ char *const argv[])
-+{
-+ ulong i = 1;
-+ struct esdctl_regs *esdctl = (struct esdctl_regs *)ESDCTL_BASE_ADDR;
-+ char dcd_item[] = "MXC_DCD_ITEM(%ld, %ld, %#010lX, %#010lX)\n";
-+
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_RAS__DRAM_RAS
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_RAS);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_CAS__DRAM_CAS
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_CAS);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_SDWE__DRAM_SDWE
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_SDWE);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_SDCKE0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_SDCKE1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_SDCLK__DRAM_SDCLK
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_SDCLK);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_SDQS0__DRAM_SDQS0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_SDQS0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_SDQS1__DRAM_SDQS1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_SDQS1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_SDQS2__DRAM_SDQS2
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_SDQS2);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_SDQS3__DRAM_SDQS3
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_SDQS3);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_CS0__DRAM_CS0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_CS0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_CS1__DRAM_CS1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_CS1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_DQM0__DRAM_DQM0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_DQM0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_DQM1__DRAM_DQM1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_DQM1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_DQM2__DRAM_DQM2
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_DQM2);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_DRAM_DQM3__DRAM_DQM3
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_DRAM_DQM3);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_EIM_SDBA2__EIM_SDBA2
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_EIM_SDBA2);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_EIM_SDODT1__EIM_SDODT1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_EIM_SDODT1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_PAD_EIM_SDODT0__EIM_SDODT0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_PAD_EIM_SDODT0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DDRPKS
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDRPKS);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DRAM_B4
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DRAM_B4);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_INDDR
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_INDDR);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_PKEDDR
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_PKEDDR);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DDR_A0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDR_A0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DDR_A1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDR_A1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DDRAPUS
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDRAPUS);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_HYSDDR0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_HYSDDR0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_HYSDDR1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_HYSDDR1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_HYSDDR2
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_HYSDDR2);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_HVDDR
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_HVDDR);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_HYSDDR3
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_HYSDDR3);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DRAM_SR_B0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDR_SR_B0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DDRAPKS
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDRAPKS);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DRAM_SR_B1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDR_SR_B1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DDRPUS
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDRPUS);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DRAM_SR_B2
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDR_SR_B2);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_PKEADDR
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_PKEADDR);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DRAM_SR_B4
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDR_SR_B4);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_INMODE1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_INMODE1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DRAM_B0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DRAM_B0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DRAM_B1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DRAM_B1);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DDR_SR_A0
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDR_SR_A0);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + ((MX51_GRP_DRAM_B2
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DRAM_B2);
-+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR +((MX51_GRP_DDR_SR_A1
-+ & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT),
-+ ACFG_IOMUX_GRP_DDR_SR_A1);
-+
-+ printf(dcd_item, i++, 4, &esdctl->esdctl0,
-+ (ACFG_SDRAM_ESDCTL_REGISTER_VAL & 0x8FFFFFFF));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, DRR_PRECHARGE_CMD(0, 0));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, DRR_AUTOREFRESH_CMD(0));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, DRR_AUTOREFRESH_CMD(0));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr,
-+ DRR_LMR_CMD(0, 0, ACFG_DRR_MR_VAL));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr,
-+ DRR_LMR_CMD(0, 2, ACFG_DRR_EMR_VAL));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, DDR_NOP_CMD(0));
-+ printf(dcd_item, i++, 4, &esdctl->esdctl0,
-+ ACFG_SDRAM_ESDCTL_REGISTER_VAL);
-+ printf(dcd_item, i++, 4, &esdctl->esdcfg0,
-+ ACFG_SDRAM_ESDCFG_REGISTER_VAL);
-+
-+ printf(dcd_item, i++, 4, &esdctl->esdctl1,
-+ (ACFG_SDRAM_ESDCTL_REGISTER_VAL & 0x8FFFFFFF));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, DRR_PRECHARGE_CMD(1, 0));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, DRR_AUTOREFRESH_CMD(1));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, DRR_AUTOREFRESH_CMD(1));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr,
-+ DRR_LMR_CMD(1, 0, ACFG_DRR_MR_VAL));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr,
-+ DRR_LMR_CMD(1, 2, ACFG_DRR_EMR_VAL));
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, DDR_NOP_CMD(1));
-+ printf(dcd_item, i++, 4, &esdctl->esdctl1,
-+ ACFG_SDRAM_ESDCTL_REGISTER_VAL);
-+ printf(dcd_item, i++, 4, &esdctl->esdcfg1,
-+ ACFG_SDRAM_ESDCFG_REGISTER_VAL);
-+
-+ printf(dcd_item, i++, 4, &esdctl->esdmisc,
-+ ACFG_SDRAM_ESDMISC_REGISTER_VAL);
-+ printf(dcd_item, i++, 4, &esdctl->esdscr, 0x00000000);
-+
-+ printf(dcd_item, i++, 4, &esdctl->esdgpr,
-+ ACFG_SDRAM_ESDGPR_REGISTER_VAL);
-+ printf(dcd_item, i++, 4, &esdctl->esdcdly1,
-+ ACFG_SDRAM_ESDCDLY1_REGISTER_VAL);
-+ printf(dcd_item, i++, 4, &esdctl->esdcdly2,
-+ ACFG_SDRAM_ESDCDLY2_REGISTER_VAL);
-+ printf(dcd_item, i++, 4, &esdctl->esdcdly3,
-+ ACFG_SDRAM_ESDCDLY3_REGISTER_VAL);
-+ printf(dcd_item, i++, 4, &esdctl->esdcdly4,
-+ ACFG_SDRAM_ESDCDLY4_REGISTER_VAL);
-+ printf(dcd_item, i++, 4, &esdctl->esdcdly5,
-+ ACFG_SDRAM_ESDCDLY5_REGISTER_VAL);
-+
-+ return 0;
-+}
-+
-+/***************************************************/
-+
-+U_BOOT_CMD(dcdshow, 1, 1, do_mx51_show_dcd_tab,
-+ "display mx51 dcd tab\n", "");
-+#endif /* CONFIG_CMD_BSP */
diff --git a/board/armadeus/apf51/fpga.c b/board/armadeus/apf51/fpga.c
new file mode 100644
index 0000000..665928e
hooks/post-receive
--
armadeus
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