[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.3-254-g4cf3a49
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.3-254-g4cf3a49
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From: jorasse <jo...@us...> - 2014-05-09 10:22:14
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 4cf3a49cdf7fb2f262d485d68e407bb3a08928d7 (commit)
from e2d9531d27c689bae736ea88d561d9c0fe0a3b61 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 4cf3a49cdf7fb2f262d485d68e407bb3a08928d7
Author: Eric Jarrige <eri...@ar...>
Date: Fri May 9 12:22:03 2014 +0200
[UBOOT] 2014.04: afp51: patch refactoring
-----------------------------------------------------------------------
Summary of changes:
patches/u-boot/2014.04/400-imx51.patch | 261 ++++++++++++++++++-
patches/u-boot/2014.04/401-apf51.patch | 118 +---------
patches/u-boot/2014.04/420-apf51-nand-spl-NG.patch | 39 +---
3 files changed, 254 insertions(+), 164 deletions(-)
diff --git a/patches/u-boot/2014.04/400-imx51.patch b/patches/u-boot/2014.04/400-imx51.patch
index 9066d23..66cebe9 100644
--- a/patches/u-boot/2014.04/400-imx51.patch
+++ b/patches/u-boot/2014.04/400-imx51.patch
@@ -4,14 +4,14 @@ Signed-off-by: Philippe Reynes <tr...@ya...>
arch/arm/cpu/armv7/cpu.c
arch/arm/cpu/armv7/mx5/lowlevel_init.S
arch/arm/include/asm/arch-mx5/imx-regs.h
- arch/arm/include/asm/arch-mx5/mx5x_pins.h
+ arch/arm/include/asm/arch-mx5/iomux-mx51.h
arch/arm/include/asm/arch-mx5/regs_esdctl.h
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 39a8023..c8c2293 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
-@@ -82,5 +82,9 @@ int cleanup_before_linux(void)
+@@ -66,5 +66,9 @@ int cleanup_before_linux(void)
*/
cpu_cache_initialization();
@@ -25,7 +25,7 @@ diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/low
index a40b84f..1ca9b22 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
-@@ -24,6 +24,34 @@
+@@ -11,6 +11,34 @@
#include <generated/asm-offsets.h>
#include <linux/linkage.h>
@@ -60,7 +60,7 @@ index a40b84f..1ca9b22 100644
.section ".text.init", "x"
.macro init_arm_erratum
-@@ -114,7 +142,7 @@
+@@ -107,7 +135,7 @@
#define W_DP_MFN 8
setup_pll_func:
@@ -69,7 +69,7 @@ index a40b84f..1ca9b22 100644
str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
mov r1, #0x2
str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-@@ -131,7 +159,7 @@
+@@ -124,7 +152,7 @@
str r1, [r0, #PLL_DP_MFN]
str r1, [r0, #PLL_DP_HFS_MFN]
@@ -78,7 +78,7 @@ index a40b84f..1ca9b22 100644
str r1, [r0, #PLL_DP_CTL]
1: ldr r1, [r0, #PLL_DP_CTL]
ands r1, r1, #0x1
-@@ -143,7 +171,7 @@
+@@ -136,7 +164,7 @@
.macro setup_pll_errata pll, freq
ldr r2, =\pll
str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
@@ -87,7 +87,7 @@ index a40b84f..1ca9b22 100644
str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
ands r1, r1, #0x1
-@@ -172,6 +200,16 @@
+@@ -165,6 +193,16 @@
#if defined (CONFIG_MX51)
ldr r0, =CCM_BASE_ADDR
@@ -104,7 +104,7 @@ index a40b84f..1ca9b22 100644
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
-@@ -199,7 +237,7 @@
+@@ -192,7 +230,7 @@
bne 1b
/* Switch ARM to step clock */
@@ -113,7 +113,7 @@ index a40b84f..1ca9b22 100644
str r1, [r0, #CLKCTL_CCSR]
#if defined(CONFIG_MX51_PLL_ERRATA)
-@@ -244,13 +282,14 @@
+@@ -237,13 +275,14 @@
str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1 */
@@ -132,7 +132,7 @@ index a40b84f..1ca9b22 100644
ldr r1, =CONFIG_SYS_CLKTL_CBCDR
str r1, [r0, #CLKCTL_CBCDR]
-@@ -265,9 +304,9 @@
+@@ -258,9 +297,9 @@
str r1, [r0, #CLKCTL_CCGR6]
/* Use PLL 2 for UART's, get 66.5MHz from it */
@@ -148,15 +148,15 @@ diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arc
index 46017f4..520bf98 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
-@@ -267,6 +267,7 @@
- #define M4IF_FBPM0 0x40
- #define M4IF_FIDBP 0x48
+@@ -255,6 +255,7 @@
+ #define M4IF_GENP_WEIM_MM_MASK 0x00000001
+ #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
+#ifndef DP_OP_800
/* Assuming 24MHz input clock with doubler ON */
/* MFI PDF */
#define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
-@@ -305,6 +306,7 @@
+@@ -293,6 +294,7 @@
#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
#define DP_MFD_216 (4 - 1)
#define DP_MFN_216 3
@@ -164,6 +164,239 @@ index 46017f4..520bf98 100644
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_1 0x11
+diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
+--- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h
++++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
+@@ -60,9 +60,17 @@ enum {
+ MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
++ MX51_PAD_EIM_D24__I2C2_SDA = IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL),
+ MX51_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL),
++ MX51_PAD_EIM_D25__UART2_CTS = IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_EIM_D26__UART3_TXD = IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL),
++ MX51_PAD_EIM_D26__UART2_RTS = IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL),
++ MX51_PAD_EIM_D27__I2C2_SCL = IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL),
+ MX51_PAD_EIM_D27__GPIO2_9 = IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_EIM_D28__AUD6_TXD = IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_D29__AUD6_RXD = IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_D30__AUD6_TXC = IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_D31__AUD6_TXFS = IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_A16__GPIO2_10 = IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A17__GPIO2_11 = IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A20__GPIO2_14 = IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+@@ -73,16 +81,22 @@ enum {
+ MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_EB2__FEC_MDIO = IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, PAD_CTL_PUS_22K_UP | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_HYS),
+- MX51_PAD_EIM_EB3__FEC_RDATA1 = IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_EB2__AUD5_RXFS = IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_EB3__GPIO2_23 = IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_EIM_EB3__FEC_RDATA1 = IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_EB3__AUD5_RXC = IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS0__GPIO2_25 = IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+- MX51_PAD_EIM_CS2__FEC_RDATA2 = IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS2__GPIO2_27 = IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+- MX51_PAD_EIM_CS3__FEC_RDATA3 = IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_CS2__FEC_RDATA2 = IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_CS2__AUD5_TXD = IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS3__GPIO2_28 = IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+- MX51_PAD_EIM_CS4__FEC_RX_ER = IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_EIM_CS3__FEC_RDATA3 = IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_CS3__AUD5_RXD = IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS4__GPIO2_29 = IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_EIM_CS4__FEC_RX_ER = IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_EIM_CS4__AUD5_TXC = IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS5__FEC_CRS = IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_EIM_CS5__AUD5_TXFS = IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL),
+ MX51_PAD_DRAM_RAS__DRAM_RAS = IOMUX_PAD(0x4a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_CAS__DRAM_CAS = IOMUX_PAD(0x4a8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDWE__DRAM_SDWE = IOMUX_PAD(0x4ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+@@ -99,18 +113,31 @@ enum {
+ MX51_PAD_DRAM_DQM1__DRAM_DQM1 = IOMUX_PAD(0x4d8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_DQM2__DRAM_DQM2 = IOMUX_PAD(0x4dc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_DQM3__DRAM_DQM3 = IOMUX_PAD(0x4e0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_WE_B__NANDF_WE_B = IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_WE_B__PATA_DIOW = IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_RE_B__NANDF_RE_B = IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RE_B__PATA_DIOR = IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_ALE__NANDF_ALE = IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_ALE__PATA_BUFFER_EN = IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_CLE__NANDF_CLE = IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CLE__PATA_RESET_B = IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_WP_B__NANDF_WP_B = IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_WP_B__PATA_DMACK = IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_RB0__NANDF_RB0 = IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RB0__PATA_DMARQ = IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RB1__PATA_IORDY = IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_RB1__ECSPI2_RDY = IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_NANDF_RB2__FEC_COL = IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_NANDF_RB2__ECSPI2_SCLK = IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_NANDF_RB2__GPIO3_10 = IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_RB3__FEC_RX_CLK = IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_NANDF_RB3__ECSPI2_MISO = IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_NANDF_RB3__GPIO3_11 = IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_EIM_SDBA2__EIM_SDBA2 = IOMUX_PAD(0x508, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_SDODT1__EIM_SDODT1 = IOMUX_PAD(0x50C, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_SDODT0__EIM_SDODT0 = IOMUX_PAD(0x510, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO_NAND__PATA_INTRQ = IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_CS0__NANDF_CS0 = IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS2__FEC_TX_ER = IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_NANDF_CS2__PATA_CS_0 = IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS3__FEC_MDC = IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5),
+@@ -123,13 +150,17 @@ enum {
+ MX51_PAD_NANDF_CS6__PATA_DA_2 = IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS7__FEC_TX_EN = IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK = IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4),
+- MX51_PAD_NANDF_D15__GPIO3_25 = IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_D15__PATA_DATA15 = IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+- MX51_PAD_NANDF_D14__GPIO3_26 = IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_NANDF_D15__ECSPI2_MOSI = IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
++ MX51_PAD_NANDF_D15__GPIO3_25 = IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_D14__PATA_DATA14 = IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+- MX51_PAD_NANDF_D13__GPIO3_27 = IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_NANDF_D14__ECSPI2_SS3 = IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL),
++ MX51_PAD_NANDF_D14__GPIO3_26 = IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_D13__PATA_DATA13 = IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D13__ECSPI2_SS2 = IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
++ MX51_PAD_NANDF_D13__GPIO3_27 = IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_D12__PATA_DATA12 = IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D12__ECSPI2_SS1 = IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_NANDF_D11__FEC_RX_DV = IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D11__PATA_DATA11 = IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D10__GPIO3_30 = IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+@@ -139,16 +170,47 @@ enum {
+ MX51_PAD_NANDF_D9__PATA_DATA9 = IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D8__FEC_TDATA0 = IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_NANDF_D8__PATA_DATA8 = IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D7__NANDF_D7 = IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D7__PATA_DATA7 = IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D6__NANDF_D6 = IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D6__PATA_DATA6 = IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D5__NANDF_D5 = IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D5__PATA_DATA5 = IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D4__NANDF_D4 = IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D4__PATA_DATA4 = IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D3__NANDF_D3 = IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D3__PATA_DATA3 = IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D2__NANDF_D2 = IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D2__PATA_DATA2 = IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D1__NANDF_D1 = IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D1__PATA_DATA1 = IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D0__NANDF_D0 = IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D0__PATA_DATA0 = IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D8__CSI1_D8 = IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D9__CSI1_D9 = IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D10__CSI1_D10 = IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D11__CSI1_D11 = IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D12__CSI1_D12 = IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D13__CSI1_D13 = IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D14__CSI1_D14 = IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D15__CSI1_D15 = IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D16__CSI1_D16 = IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D17__CSI1_D17 = IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D18__CSI1_D18 = IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_D19__CSI1_D19 = IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_VSYNC__CSI1_VSYNC = IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_HSYNC__CSI1_HSYNC = IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK = IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL),
++ MX51_PAD_CSI1_MCLK__CSI1_MCLK = IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL),
+ MX51_PAD_CSI2_D12__GPIO4_9 = IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSI2_D13__GPIO4_10 = IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_CSI2_D18__GPIO4_11 = IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL),
++ MX51_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL),
++ MX51_PAD_AUD3_BB_TXD__AUD3_TXD = IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_AUD3_BB_RXD__AUD3_RXD = IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_AUD3_BB_CK__AUD3_TXC = IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_AUD3_BB_FS__AUD3_TXFS = IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_CSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_CSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+@@ -162,6 +224,10 @@ enum {
+ MX51_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL),
++ MX51_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL),
++ MX51_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL),
++ MX51_PAD_UART3_RXD__UART3_RXD = IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL),
++ MX51_PAD_UART3_TXD__UART3_TXD = IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_USBH1_CLK__USBH1_CLK = IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DIR__USBH1_DIR = IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_STP__GPIO1_27 = IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL),
+@@ -175,6 +241,7 @@ enum {
+ MX51_PAD_USBH1_DATA5__USBH1_DATA5 = IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA6__USBH1_DATA6 = IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA7__USBH1_DATA7 = IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
++ MX51_PAD_DI1_PIN11__GPIO3_0 = IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DI1_PIN11__ECSPI1_SS2 = IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_DI1_PIN12__GPIO3_1 = IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DI1_PIN13__GPIO3_2 = IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL),
+@@ -182,10 +249,30 @@ enum {
+ MX51_PAD_DI1_D1_CS__GPIO3_4 = IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DISPB2_SER_DIN__GPIO3_5 = IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DISPB2_SER_DIO__GPIO3_6 = IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_DISPB2_SER_CLK__GPIO3_7 = IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_DISPB2_SER_RS__GPIO3_8 = IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DI1_PIN3__DI1_PIN3 = IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DI1_PIN2__DI1_PIN2 = IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_DI_GP3__FEC_TX_ER = IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5),
++ MX51_PAD_DI2_PIN4__FEC_CRS = IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL),
++ MX51_PAD_DI2_PIN2__FEC_MDC = IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5),
++ MX51_PAD_DI2_PIN3__FEC_MDIO = IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL),
+ MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK = IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 = IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL),
++ MX51_PAD_DI_GP4__FEC_RDATA2 = IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL),
+ MX51_PAD_DI_GP4__DI2_PIN15 = IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_DISP2_DAT0__FEC_RDATA3 = IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL),
++ MX51_PAD_DISP2_DAT1__FEC_RX_ER = IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL),
++ MX51_PAD_DISP2_DAT6__FEC_TDATA1 = IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5),
++ MX51_PAD_DISP2_DAT7__FEC_TDATA2 = IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5),
++ MX51_PAD_DISP2_DAT8__FEC_TDATA3 = IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5),
++ MX51_PAD_DISP2_DAT9__FEC_TX_EN = IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5),
++ MX51_PAD_DISP2_DAT10__FEC_COL = IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL),
++ MX51_PAD_DISP2_DAT11__FEC_RX_CLK = IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL),
++ MX51_PAD_DISP2_DAT12__FEC_RX_DV = IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL),
++ MX51_PAD_DISP2_DAT13__FEC_TX_CLK = IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4),
++ MX51_PAD_DISP2_DAT14__FEC_RDATA0 = IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4),
++ MX51_PAD_DISP2_DAT15__FEC_TDATA0 = IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+ MX51_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
+ MX51_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+@@ -204,13 +291,17 @@ enum {
+ MX51_PAD_GPIO1_2__GPIO1_2 = IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_GPIO1_2__PWM1_PWMO = IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO1_3__GPIO1_3 = IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_GPIO1_3__PWM2_PWMO = IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_GPIO1_4__GPIO1_4 = IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_GPIO1_5__GPIO1_5 = IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_GPIO1_5__CCM_CLKO = IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO1_6__GPIO1_6 = IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_GPIO1_7__GPIO1_7 = IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_GPIO1_7__SD2_WP = IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+ MX51_PAD_GPIO1_8__SD2_CD = IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+ MX51_GRP_DDRPKS = IOMUX_PAD(0x820, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_B4 = IOMUX_PAD(0x82c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_GRP_INDDR = IOMUX_PAD(0x830, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_PKEDDR = IOMUX_PAD(0x838, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDR_A0 = IOMUX_PAD(0x83c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDR_A1 = IOMUX_PAD(0x848, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+@@ -218,6 +309,7 @@ enum {
+ MX51_GRP_HYSDDR0 = IOMUX_PAD(0x85c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_HYSDDR1 = IOMUX_PAD(0x864, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_HYSDDR2 = IOMUX_PAD(0x86c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_GRP_HVDDR = IOMUX_PAD(0x870, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_HYSDDR3 = IOMUX_PAD(0x874, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_SR_B0 = IOMUX_PAD(0x878, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDRAPKS = IOMUX_PAD(0x87c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+@@ -229,6 +321,7 @@ enum {
+ MX51_GRP_INMODE1 = IOMUX_PAD(0x8a0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_B0 = IOMUX_PAD(0x8a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_B1 = IOMUX_PAD(0x8ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_GRP_DDR_SR_A0 = IOMUX_PAD(0x8b0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_B2 = IOMUX_PAD(0x8b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDR_SR_A1 = IOMUX_PAD(0x8bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ };
diff --git a/arch/arm/include/asm/arch-mx5/regs_esdctl.h b/arch/arm/include/asm/arch-mx5/regs_esdctl.h
new file mode 100644
index 0000000..1c0bf8e
diff --git a/patches/u-boot/2014.04/401-apf51.patch b/patches/u-boot/2014.04/401-apf51.patch
index 9ca4ad4..0e4ba2a 100644
--- a/patches/u-boot/2014.04/401-apf51.patch
+++ b/patches/u-boot/2014.04/401-apf51.patch
@@ -33,7 +33,7 @@ new file mode 100644
index 0000000..8ff1381
--- /dev/null
+++ b/board/armadeus/apf51/apf51.c
-@@ -0,0 +1,999 @@
+@@ -0,0 +1,885 @@
+/*
+ * Armadeus APF51 baseboard
+ *
@@ -177,14 +177,6 @@ index 0000000..8ff1381
+
+void setup_uart(void)
+{
-+enum {
-+ MX51_PAD_EIM_D25__UART2_CTS = IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL),
-+ MX51_PAD_EIM_D26__UART2_RTS = IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL),
-+ MX51_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL),
-+ MX51_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL),
-+ MX51_PAD_UART3_RXD__UART3_RXD = IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL),
-+ MX51_PAD_UART3_TXD__UART3_TXD = IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL),
-+};
+ /*
+ * Configure iomux for UART interfaces
+ */
@@ -225,22 +217,6 @@ index 0000000..8ff1381
+
+void setup_audio(void)
+{
-+enum {
-+ MX51_PAD_AUD3_BB_TXD__AUD3_TXD = IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_AUD3_BB_RXD__AUD3_RXD = IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_AUD3_BB_CK__AUD3_TXC = IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_AUD3_BB_FS__AUD3_TXFS = IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_EB2__AUD5_RXFS = IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_EB3__AUD5_RXC = IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_CS2__AUD5_TXD = IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL),
-+ MX51_PAD_EIM_CS3__AUD5_RXD = IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL),
-+ MX51_PAD_EIM_CS4__AUD5_TXC = IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL),
-+ MX51_PAD_EIM_CS5__AUD5_TXFS = IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL),
-+ MX51_PAD_EIM_D28__AUD6_TXD = IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_D29__AUD6_RXD = IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_D30__AUD6_TXC = IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_D31__AUD6_TXFS = IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL),
-+};
+ /*
+ * Configure iomux for audio interfaces
+ */
@@ -288,24 +264,6 @@ index 0000000..8ff1381
+
+void setup_csi(void)
+{
-+enum {
-+ MX51_PAD_CSI1_D8__CSI1_D8 = IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D9__CSI1_D9 = IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D10__CSI1_D10 = IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D11__CSI1_D11 = IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D12__CSI1_D12 = IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D13__CSI1_D13 = IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D14__CSI1_D14 = IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D15__CSI1_D15 = IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D16__CSI1_D16 = IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D17__CSI1_D17 = IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D18__CSI1_D18 = IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_D19__CSI1_D19 = IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_VSYNC__CSI1_VSYNC = IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_HSYNC__CSI1_HSYNC = IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK = IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL),
-+ MX51_PAD_CSI1_MCLK__CSI1_MCLK = IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL),
-+};
+ /*
+ * Configure iomux for CSI interfaces
+ */
@@ -396,14 +354,6 @@ index 0000000..8ff1381
+
+void setup_misc(void)
+{
-+enum {
-+ MX51_PAD_GPIO1_3__PWM2_PWMO = IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_GPIO1_4__GPIO1_4 = IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
-+ MX51_PAD_GPIO1_5__CCM_CLKO = IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_DI1_PIN11__GPIO3_0 = IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL),
-+ MX51_PAD_DISPB2_SER_CLK__GPIO3_7 = IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL),
-+ MX51_PAD_DISPB2_SER_RS__GPIO3_8 = IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL),
-+};
+ /*
+ * Configure iomux for misc interfaces
+ */
@@ -470,7 +420,7 @@ index 0000000..8ff1381
+ FPGA_PAD_CFG));
+
+ /* FPGA INIT# */
-+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D18__GPIO4_11,
+ FPGA_PAD_CFG));
+}
+
@@ -486,25 +436,6 @@ index 0000000..8ff1381
+
+void setup_nfc(void)
+{
-+/* PAD MUX ALT INPSE PATH PADCTRL */
-+enum {
-+ MX51_PAD_NANDF_WE_B__NANDF_WE_B = IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_RE_B__NANDF_RE_B = IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_ALE__NANDF_ALE = IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_CLE__NANDF_CLE = IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_WP_B__NANDF_WP_B = IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_RB0__NANDF_RB0 = IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_CS0__NANDF_CS0 = IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D7__NANDF_D7 = IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D6__NANDF_D6 = IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D5__NANDF_D5 = IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D4__NANDF_D4 = IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D3__NANDF_D3 = IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D2__NANDF_D2 = IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D1__NANDF_D1 = IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D0__NANDF_D0 = IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL),
-+};
-+
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_NANDF_WE_B__NANDF_WE_B,
+ PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH));
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_NANDF_RE_B__NANDF_RE_B,
@@ -537,15 +468,6 @@ index 0000000..8ff1381
+
+void setup_spi_io(void)
+{
-+enum {
-+ MX51_PAD_NANDF_RB1__ECSPI2_RDY = IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
-+ MX51_PAD_NANDF_RB2__ECSPI2_SCLK = IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
-+ MX51_PAD_NANDF_RB3__ECSPI2_MISO = IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
-+ MX51_PAD_NANDF_D15__ECSPI2_MOSI = IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
-+ MX51_PAD_NANDF_D14__ECSPI2_SS3 = IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL),
-+ MX51_PAD_NANDF_D13__ECSPI2_SS2 = IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
-+ MX51_PAD_NANDF_D12__ECSPI2_SS1 = IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL),
-+};
+ /*
+ * Configure iomux for SPI interface
+ */
@@ -578,13 +500,6 @@ index 0000000..8ff1381
+
+static void setup_i2c(unsigned int module_base)
+{
-+enum {
-+ MX51_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL),
-+ MX51_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL),
-+ MX51_PAD_EIM_D24__I2C2_SDA = IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL),
-+ MX51_PAD_EIM_D27__I2C2_SCL = IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL),
-+};
-+
+ static const iomux_v3_cfg_t i2c1_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CFG),
+ NEW_PAD_CTRL(MX51_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CFG),
@@ -620,27 +535,6 @@ index 0000000..8ff1381
+#define FEC_PAD_CFG (PAD_CTL_DSE_MED | PAD_CTL_PKE | \
+ PAD_CTL_HYS )
+
-+enum {
-+ MX51_PAD_DI_GP3__FEC_TX_ER = IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5),
-+ MX51_PAD_DI2_PIN4__FEC_CRS = IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL),
-+ MX51_PAD_DI2_PIN2__FEC_MDC = IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5),
-+ MX51_PAD_DI2_PIN3__FEC_MDIO = IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL),
-+ MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 = IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL),
-+ MX51_PAD_DI_GP4__FEC_RDATA2 = IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL),
-+ MX51_PAD_DISP2_DAT0__FEC_RDATA3 = IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL),
-+ MX51_PAD_DISP2_DAT1__FEC_RX_ER = IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL),
-+ MX51_PAD_DISP2_DAT6__FEC_TDATA1 = IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5),
-+ MX51_PAD_DISP2_DAT7__FEC_TDATA2 = IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5),
-+ MX51_PAD_DISP2_DAT8__FEC_TDATA3 = IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5),
-+ MX51_PAD_DISP2_DAT9__FEC_TX_EN = IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5),
-+ MX51_PAD_DISP2_DAT10__FEC_COL = IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL),
-+ MX51_PAD_DISP2_DAT11__FEC_RX_CLK = IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL),
-+ MX51_PAD_DISP2_DAT12__FEC_RX_DV = IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL),
-+ MX51_PAD_DISP2_DAT13__FEC_TX_CLK = IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4),
-+ MX51_PAD_DISP2_DAT14__FEC_RDATA0 = IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4),
-+ MX51_PAD_DISP2_DAT15__FEC_TDATA0 = IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5),
-+};
-+
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_DI_GP3__FEC_TX_ER, FEC_PAD_CFG),
+ NEW_PAD_CTRL(MX51_PAD_DI2_PIN4__FEC_CRS, FEC_PAD_CFG),
@@ -833,14 +727,6 @@ index 0000000..8ff1381
+int do_mx51_show_dcd_tab(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
-+enum {
-+ MX51_PAD_EIM_SDBA2__EIM_SDBA2 = IOMUX_PAD(0x508, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_SDODT1__EIM_SDODT1 = IOMUX_PAD(0x50C, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_SDODT0__EIM_SDODT0 = IOMUX_PAD(0x510, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_GRP_INDDR = IOMUX_PAD(0x830, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_GRP_HVDDR = IOMUX_PAD(0x870, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_GRP_DDR_SR_A0 = IOMUX_PAD(0x8b0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+};
+ ulong i = 1;
+ struct esdctl_regs *esdctl = (struct esdctl_regs *)ESDCTL_BASE_ADDR;
+ char dcd_item[] = "MXC_DCD_ITEM(%ld, %ld, %#010lX, %#010lX)\n";
diff --git a/patches/u-boot/2014.04/420-apf51-nand-spl-NG.patch b/patches/u-boot/2014.04/420-apf51-nand-spl-NG.patch
index 61826e1..d6b45a8 100644
--- a/patches/u-boot/2014.04/420-apf51-nand-spl-NG.patch
+++ b/patches/u-boot/2014.04/420-apf51-nand-spl-NG.patch
@@ -23,7 +23,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
spl/u-boot-nand-spl.imx: SPL FORCE
--- a/board/armadeus/apf51/apf51_spl.c
+++ b/board/armadeus/apf51/apf51_spl.c
-@@ -0,0 +1,230 @@
+@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2013-2014 Eric Jarrige <eri...@ar...>
+ *
@@ -45,16 +45,6 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+static inline void init_dram(void)
+{
+ struct esdctl_regs *esdctl = (struct esdctl_regs *)ESDCTL_BASE_ADDR;
-+/* PAD MUX ALT INPSE PATH PADCTRL */
-+enum {
-+ MX51_PAD_EIM_SDBA2__EIM_SDBA2 = IOMUX_PAD(0x508, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_SDODT1__EIM_SDODT1 = IOMUX_PAD(0x50C, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_EIM_SDODT0__EIM_SDODT0 = IOMUX_PAD(0x510, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_GRP_INDDR = IOMUX_PAD(0x830, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_GRP_HVDDR = IOMUX_PAD(0x870, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_GRP_DDR_SR_A0 = IOMUX_PAD(0x8b0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
-+};
-+
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS,
+ ACFG_IOMUX_PAD_DRAM_RAS));
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS,
@@ -180,25 +170,6 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+
+void setup_nfc(void)
+{
-+/* PAD MUX ALT INPSE PATH PADCTRL */
-+enum {
-+ MX51_PAD_NANDF_WE_B__NANDF_WE_B = IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_RE_B__NANDF_RE_B = IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_ALE__NANDF_ALE = IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_CLE__NANDF_CLE = IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_WP_B__NANDF_WP_B = IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_RB0__NANDF_RB0 = IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_CS0__NANDF_CS0 = IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D7__NANDF_D7 = IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D6__NANDF_D6 = IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D5__NANDF_D5 = IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D4__NANDF_D4 = IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D3__NANDF_D3 = IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D2__NANDF_D2 = IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D1__NANDF_D1 = IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL),
-+ MX51_PAD_NANDF_D0__NANDF_D0 = IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL),
-+};
-+
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_NANDF_WE_B__NANDF_WE_B,
+ PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH));
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_NANDF_RE_B__NANDF_RE_B,
@@ -298,7 +269,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
-@@ -1108,7 +1108,65 @@ void mxc_nand_command(struct mtd_info *m
+@@ -1102,7 +1102,65 @@ void mxc_nand_command(struct mtd_info *m
break;
#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
@@ -365,8 +336,8 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
/* Blocks to be unlocked */
writew(-1, &host->regs->unlockstart_blkaddr);
writew(-1, &host->regs->unlockend_blkaddr);
-@@ -1150,6 +1208,7 @@ void mxc_nand_command(struct mtd_info *m
- writew(readw(&host->regs->nf_wrprst) & ~NFC_WRPR_US, &host->regs->main_area[0][0]);
+@@ -1147,6 +1205,7 @@ void mxc_nand_command(struct mtd_info *m
+ writew(readw(&host->regs->nf_wrprst) & ~NFC_WRPR_US, main_buf);
}
return;
+#endif /* not defined(MXC_NFC_V3_2) */
@@ -375,7 +346,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
--- a/drivers/mtd/nand/mxc_nand.h
+++ b/drivers/mtd/nand/mxc_nand.h
-@@ -207,9 +207,12 @@ struct mxc_nand_ip_regs {
+@@ -191,9 +191,12 @@ struct mxc_nand_ip_regs {
#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
#define NFC_V3_WRPROT_UNLOCK (1 << 2)
hooks/post-receive
--
armadeus
|
