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Showing 10 open source projects for "cpu"
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DAT Freight and Analytics - DATDAT Freight & Analytics operates DAT One, North America’s largest truckload freight marketplace; DAT iQ, the industry’s leading freight data analytics service; and Trucker Tools, the leader in load visibility. Shippers, transportation brokers, carriers, news organizations, and industry analysts rely on DAT for market trends and data insights, informed by nearly 700,000 daily load posts and a database exceeding $1 trillion in freight market transactions. Founded in 1978, DAT is a business unit of Roper Technologies (Nasdaq: ROP), a constituent of the Nasdaq 100, S&P 500, and Fortune 1000. Headquartered in Beaverton, Ore., DAT continues to set the standard for innovation in the trucking and logistics industry.
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progrep
Utility to show live progress, status & stats for running simulations
progrep is a command-line tool (Linux) to show live progress report, status & stats of a running simulation or compute job that executes a given number of iterations. It shows % completed, time remaining, time elapsed, number of threads, MPI_Rank(if any), CPU usage & speed (FPS). The FPS measures may be used in benchmarking, e.g. while optimizing HPC algorithms for performance. progrep supports both single-threaded and parallel (multicore/multinode - e.g. OpenMP/MPI) jobs. progrep can also report for jobs running on remote hosts, e.g. jobs running on Linux Clusters. progrep works in client-server model. ... -
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Emulator of Wang 700
The functional model of the old calculator series Wang 700 and 15VSM
...The main goal of the project is emulation of those models made in Soviet Union: 15ВСМ-5, 15ВМ16/32/128 - which are also known as D3-28 (Д3-28). The choice of them is due to the extremely strong and authentic CPU command set developed by Soviet engineers as a superset around the original Wang 700's command set. While Wang 700 were just programmable calculators, Soviet machines were almost complete computers taking into account their advanced CPU command set, huge RAM volume, ability to work with wide set of peripheral devices including the video terminal 15IE (15ИЭ) and existence of BASIC and other programming languages written as loadable applications. ... -
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Aquila
Software Architecture for Cognitive Robotics
Aquila 2.0, an open-source cross-platform software architecture for cognitive robotics that makes use of independent heterogeneous CPU-GPU modules with loosely coupled dynamically generated graphical user interfaces. -
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steam-sim
An accurate, scalable, and energy-aware simulator for WSNs
STEAM-Sim establishes a hardware/software/network co-simulation of wireless sensor networks. Original C code is used in simulation. The code is natively executed by the cpu where the simulation is run. The time annotation engine annotates the C source code used for simulation with the timing information as if the code is run on a microcontroller. The annotation process is fully automated. Hardware models are developed using the PAWiS framework and reflect the timing, functionality, and energy-consumption of real-world hardware such as a CC2420 radio transceiver. ... -
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neuranep
Neural Network Engineering Platform
A parallel-programming framework for concurrently running large numbers of small autonomous jobs, or microthreads, across multiple cores in a CPU or CPUs in a cluster. NeuraNEP emulates a distributed processing environment capable of handling millions of microthreads in parallel, for example running neural networks with millions of spiking cells. Microthreads are general processing elements that can also represent non-neural elements, such as cell populations, extracellular space, emulating sensory activity, etc. ... -
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...What makes Simbuca unique is that you can choose to calculate the Coulomb interaction between ions on a Graphics cards which is much faster than calculating this on the conventional CPU (reducing the simulation time from years to days). Therefore Simbuca has been applied in various projects which required to understand the behaviour of charged "trapped" particles under the influence of EM Fields and there mutual Coulomb interaction. Simbuca is easy to read and understand and can be tweaked to your personal needs. ...
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DICE is a Discrete Integrated Circuit Emulator. It emulates computer systems that lack any type of CPU, consisting only of discrete logic components.
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ppc_sim_booke
e500v2 simulator
An experimental ISS for freescale's e500v2 core. It is meant to simulate only cpu and memory subsystem and is purely intended for academic/learning purposes only. -
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A parallel-programming framework for concurrently running large numbers of small autonomous jobs, or microthreads, across multiple cores in a CPU or CPUs in a cluster. Each microthread is conceptually similar to a task in Ada and it is much lighter weight than an operating system thread. SpikeOS was designed to handle millions of microthreads, for example in a neural network hosting millions of spiking model neurons. SpikeOS handles microthread scheduling, synchronization, distribution and communication. *** This project has been forked. ...
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eProcurement SoftwareeBuyerAssist by Eyvo is a cloud-based procurement solution designed for businesses of all sizes and industries. Fully modular and scalable, it streamlines the entire procurement lifecycle—from requisition to fulfillment. The platform includes powerful tools for strategic sourcing, supplier management, warehouse operations, and contract oversight. Additional modules cover purchase orders, approval workflows, inventory and asset management, customer orders, budget control, cost accounting, invoice matching, vendor credit checks, and risk analysis. eBuyerAssist centralizes all procurement functions into a single, easy-to-use system—improving visibility, control, and efficiency across your organization. Whether you're aiming to reduce costs, enhance compliance, or align procurement with broader business goals, eBuyerAssist helps you get there faster, smarter, and with measurable results.
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Using SystemC to develop a System On Chip system. The Design includes a MIPS CPU, Arbiter, DMA controller, SRAM controller, UART controller. This design are compatible to the IBM CoreConnect™ Architecture and the On-chip Peripheral Bus (OPB) standard.
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