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zamiaCAD is a modular and extensible platform for HW design, analysis, and research. It translates a HW description (VHDL or Verilog) into a language independent IG structure. Applications like a simulator and an eclipse GUI build on top of the IG.
bel_fft is a FFT co-processor that can calculate FFTs with arbitrary radix. It is a hardware implementation of the free software Kiss FFT ("Keep it simple, Stupid!"). The target was to allow a simple replacement of the software code with the hardware implementation. Therefore bel_fft comes with a software driver that is compatible with the Kiss FFT routines. bel_fft also has a modular architecture and allows interfacing different bus architectures. So far AMBA AXI, Altera's Avalon bus and...
vHDL Obfuscator is an small GUI to obfuscate and reformat HDL files
VHDL and Verilog HDL are standards languages for hardware description. Sometimes is necessary to share the source HDL file but maintaining a little level of control and protection of the intellectual property. This tool generate obfuscated code that is almost unreadable to humans, but is still readable to compilers and simulators.
This tool use GHDL (https://sourceforge.net/projects/ghdl-updates/), HDLObf (https://sourceforge.net/projects/hdlobf/), IcarusVerilog (https://sourceforge.net...
Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
This project is ported to github and can be found at:
https://github.com/chiphackers/covered
Open source high-level synthesis system developed within the FP7 OSMOSIS project. Includes gcc-based SystemC front-end, database with browsing GUI, scheduler/allocator/binder, and Verilog back-end. (We are under migration to SVN server now)