Search Results for "vhdl compiler"
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Showing 26 open source projects for "vhdl compiler"
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GHDL
VHDL 2008/93/87 simulator
This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyze and elaborate sources for generating machine code from your design. Native program execution is the only way for high-speed simulation. Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. ... -
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Clash
Haskell to VHDL/Verilog/SystemVerilog compiler
Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. It provides a familiar structural design approach to both combinational and synchronous sequential circuits. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog. Clash is an open-source project, licensed under the permissive BSD2 license, and actively maintained by QBayLogic. The Clash project is a Haskell Foundation affiliated project. Clash is built on Haskell which provides an excellent foundation for well-typed code. ... -
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AWS EC2 FPGA
AWS EC2 FPGA hardware and software development Kit
...After creating an FPGA design (also called CL - Custom logic), developers can create an Amazon FPGA Image (AFI) and easily deploy it to an F1 instance. AFIs are reusable, shareable and can be deployed in a scalable and secure way. Development experience leverages an optimized compiler to allow easy new accelerator development or migration of existing C/C++/openCL, Verilog/VHDL to AWS FPGA instances. Fully custom hardware development experience provides hardware developers with the tools required for developing AFIs for AWS FPGA instances. -
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Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
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MPC, The Multi Purpose structural Compiler is a tool for generation of network descriptions in various formats or languages (VHDL/Verilog/..), from an efficient structural description language.
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UMHDL
Integrated Development Environment (IDE) for learning HDL
...It is an open-source application created at the Miguel Hernández University (UMH). The aim for the UMHDL development was to have a graphical application that allows learning the VHDL language without licensing restrictions (using some existing open-source tools) and requiring few resources. So, the interface developed acts as a front-end that allows writing code (with syntax highlighting), invokes an external VHDL compiler and simulator (such as GHDL), and displays the result of the simulation graphically as waveforms (invoking to GTKWave). -
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HDL Checker
Repurposing existing HDL tools to help writing better code
HDL Checker is a language server that wraps VHDL/Verilg/SystemVerilog tools that aims to reduce the boilerplate code needed to set things up. It supports Language Server Protocol or a custom HTTP interface; can infer the library VHDL files likely to belong to, besides working out mixed language dependencies, compilation order, interpreting some compiler messages and providing some (limited) static checks. -
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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PHDL
An HDL alternative to PCB graphical schematic capture tools.
...We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic circuits have been designed and captured and overcame many of the difficulties associated with the use of schematic editing tools. We believe the use of an HDL is also the way of the future when it comes to PCB design. The PHDL compiler automatically supports the output of PADS and Eagle netlists, and through extending a simple java class, users can generate a netlist in practically any format required by their choice of a layout tool. -
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JavaRock is a project to develop a compiler from java to vhdl, which enables hardware design by java. Developping JavaRock is over, and the project continues in Synthesijer http://synthesijer.sourceforge.net . Like JavaRock, Synthesijer also aims to develop a compiler from Java to VHDL, which enables hardware design by Java. In addition, Synthesijer generates Verilog HDL and aims to implement advanced features such as optimization, graphical tools, and so on.
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BlueSVEP
Bluespec SystemVerilog Eclipse Plugin
BlueSVEP is an Eclipse-based IDE for Bluespec SystemVerilog, a functional hardware description language based on a synthesizable subset of Haskell and SystemVerilog. -
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OpenShader
Open architecture GPU simulator and implementation
Documentation, simulator, compiler, and Verilog implementation of a completely open-architecture graphics processing unit. This design is intended for academic and commercial purposes. The first step is to develop a detailed GPU simulator and compiler. The second step is to implement the GPU in synthesizable Verilog. The third step is to develop a feedback loop between the simulator and implementation, allowing power, performance, and reliability aspects of the hardware to feed back into... -
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Open RVC-CAL to HDL (ORC2HDL) is an Eclipse Plugin which uses the Open RVC-CAL Compiler (ORCC) and the openForge HDL Synthesizer. This plugin gives the ability to generate HDL code from a RVC-CAL model.
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ASDM-NoC
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
This project provide a reconfigurable asynchronous SDM router which can be configured into a basic wormhole router or an SDM router with multiple virtual circuits in every direction. Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation *... -
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FpgaC compiles a subset of the C language to net lists which can be imported into an FPGA vendors tool chains. C provides an excellent alternative to VHDL/Verilog for algorithmic expression of FPGA reconfigurable computing tasks. More info in wiki.
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Endit is a text editor mean to HDL source code writing and hacking, like Verilog and VHDL. It integrated a open source verilog compiler , Icarus verilog compiler, in it which is also an excellent open source verilog compiler.
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A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.
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s2vhdl extracts structural information from SystemC HDL programs. The output is in VHDL code and graphical diagrams. GCC compiler is used as a C++ frontend.
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Compiler-like program that checks Verilog source for common design errors. This tool can help beginning Verilog programmers who aren't aware of common design pitfalls and advanced Verilog programmers who want to double check large projects.
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vcomp is a verilog compiler for x86 linux targets - it was a commercial product which is now in the process of being GPL'd
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DGC is a tool for the creation of digital netlists. DGC does an optimization and technology mapping for an abstract description of boolean functions and state machines. Output formats are EDIF, XNF and VHDL. Input formats are KISS, PLA and others. See also: http://gitorious.org/dgc-gtk/
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RSTK is a C language program that generates Reed-Solomon HDL source code modules that can be compiled and synthesized using standard VHDL or Verilog compilers and synthesis tools.
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VHDLC is a VHDL to C++ translator aiming at full VHDL '93 compliance. It provides the translator and supporting VHDL libraries for the target host C++ compiler.
