DGC is a tool for the creation of digital netlists. DGC does an optimization and technology mapping for an abstract description of boolean functions and state machines. Output formats are EDIF, XNF and VHDL. Input formats are KISS, PLA and others.
See also: http://gitorious.org/dgc-gtk/
It was very useful for me, I work with analog design for ASIC, it can generate some simple state machines. Thank you!