Search Results for "icarus verilog for linux" - Page 4
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Showing 208 open source projects for "icarus verilog for linux"
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Doxverilog is a nativ Verilog/SystemVerilog parser for the Doxygen documentation generator. This allows the production of advanced documentation from Verilog/SystemVerilog sourcecode.
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This SourceForge project hosts an open-source Verilog-A library of compact large-signal RF MEMS capacitor, resonator and switch models. The Verilog-A models can be used with SPICE solvers for large-signal simulation of analog/RF circuits based on RF
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cccutils
Clock and Control Card Utilities
cccutils provide the sources of the CCC and the CCC-Fanout. -
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openAut
Open Source Hardware For Industrial Automation
This project is aimed at producing open source hardware for real time use in industrial automation. This project will have a few sub-projects that will focus on individual hardware for various industrial purpose. Some of the sub-projects will be of type Field-IO Modules development, Analog-IO Module development etc. -
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BlueSVEP
Bluespec SystemVerilog Eclipse Plugin
BlueSVEP is an Eclipse-based IDE for Bluespec SystemVerilog, a functional hardware description language based on a synthesizable subset of Haskell and SystemVerilog. -
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Anie
PID_control, real_time, matlab_simulink, xilinx_ise, fpga_spartan3e
Embedded system design (VHDL description) based on Xilinx's Spartan3E Development Kit to perform real-time PID control and monitoring of time critical plants such as brushless DC motors, maglevs... vimeo.com/channels/anie prezi.com/gpbycavq499c/anie/ -
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Oscilloscope components, including 100MHz quad A/D, VHDL code for Xilinx FPGA, and driver for Octave or Matlab.
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VHDT
VHDL Design Tool - code generation and project management
Application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform is used as a basis for the implementation. -
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Open RVC-CAL to HDL (ORC2HDL) is an Eclipse Plugin which uses the Open RVC-CAL Compiler (ORCC) and the openForge HDL Synthesizer. This plugin gives the ability to generate HDL code from a RVC-CAL model.
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Partially Reconfigurable Hardware
Framework for Adaptive Hardware Concurrent Systems with DPR-FPGAs
This project introduces new FPGA architectural tools and Linux OS modifications that aid in supporting Dynamic Partial Reconfiguration (DPR) on FPGAs for concurrent control. It shows that control systems benefit from hardware concurrency, meaning that by moving the control intelligence into hardware, the negative effects inherent to threads and their scheduler are minimized. This leaves software with the role of a high-level administrator rather than an executor, thereby eliminating unnecessary... -
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HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL
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herramientas y widgets para escritorios que usen GTK.
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VPreproc
C++ Verilog macro preprocessor
This is a standalone preprocessor for the Verilog HDL language. It is modified from the Verilog-PreProcessor of Verilog Perl tool 3.314. Most of the code is written by the team led by Wilson Snyder. What I have done in this project: * Provide a standalone command line interface (without Perl). * Replace the parts implemented in Perl to C++. * Encapsulate the package in a separated namespace for better independence. What I may do in the future: * Replace the C language features to C... -
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ASDM-NoC
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
... testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation) -
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FAZIA DAQ
The aim of FAZIA project is to build a 4Pi array for charged particles
The FAZIA project groups together more than 10 institutions in Nuclear Physics, which are working in the domain of heavy-ion induced reactions around and below the Fermi energy (10-100AMeV). The aim of the project is to build a 4Pi array for charged particles, with high granularity and good energy resolution, with A and Z identification capability over the widest possible range. It will use the up-to-date techniques concerning detection, signal processing and data flow, with full digital... -
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This is a collection of tools and a code library to assist engineers who are developing SystemVerilog based verification environments. Components include utility libraries, scoreboard and shutdown manager implementation, register tool, etc.
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Currently in early alpha! Unfold the story of Icarus, the illegitimate son of a Duke who finds himself in a position of great responsibility and power. Whether he's ready or not, the consequences of his choices will ripple through history.
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RG7Miner
A bitcoin miner to use with the Icarus FPGA development platform.
A bitcoin miner to use with the Icarus FPGA development platform. -
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Arduloko OS
Sistema Operacional
Sistema Operacional baseado no Ubuntu 11.04 (natty) 64bits destinado à profissionais e estudantes de eletrônica. O sistema foi gerado principalmente para trabalhos elaborados com o hardware arduino, mas foi evoluindo e hoje trabalha com vários outros equipamentos. A senha para login (Arduino ou root) é arduino. Para baixar pelo DropBox, eis o link: http://dl.dropbox.com/u/65818773/arduloko.iso User: Arduino Pass: arduino User: Root Pass: arduino -
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smPla
SystemVerilog module to substitute Verilog PLA system tasks.
SystemVerilog module that models the following PLA system tasks of Verilog: $a/sync$and$array $a/sync$nand$array $a/sync$or$array $a/sync$nor$array $a/sync$and$plane $a/sync$nand$plane $a/sync$or$plane $a/sync$nor$plane. -
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Application de fines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.
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AVRILOS
Simple AVR OS
A simple Embedded System Framework that allows rapid development of applications build for AVR family. System is based on a super-loop architecture with check and skip (no-wait) flag event driver system. Supports: UART, SysTick Timer, ADC, SPI, EEPROM, PWM. Also supports: Xilinx FPGA configuration, FPGA SSI interface, smart card reader etc. Tested partially (different modules in each case) on ATMega163/16/32/323/8. Awards CodeProject 2010, Third Prize, Hardware and Device... -
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A compiled logic verilog compiler/simulator for pipelined verilog designs. The simulator can simulate n copies of the verilog where n is the width of integers on the machine that it runs on, simultaneously.