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Eclipse Verilog editor

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Programming Languages: Java

License: GNU General Public License (GPL), Eclipse Public License

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browse code, statistics, last commit on 2009-10-25 svn co https://veditor.svn.sourceforge.net/svnroot/veditor veditor

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  • Purpose

    Ohh and seems these forums are more related to development of veditor as a tool. Can someone redirect me to more about discussion -- how to use and verilog related stuff?.

    2009-11-16 04:55:30 UTC by protik

  • How to

    Hey guys hi, I'm gonna try veditor, I've been using emacs-verilog but for some reason emacs have issues, And will like to get advantage of eclipse for portability and stuff. Do we have any "how to" to get started with veditor for eclipse? Would appreciate help Thanks :)

    2009-11-16 04:52:02 UTC by protik

  • >500k VHDL file - Outline does not work

    Hi I am using veditorv 0.7.0, eclipse 3.5.1 I have a testbench with all the verif tests in. (Reason for large file) As soon as the vhdl file gets larger than +-500k, "Outline" stops working. (Hierarchy aswell) I made a very simple test vhdl file. Same thing, >500k "Outline" stop working. Is there a setting to inrease this file size limit? Thanks.

    2009-11-13 11:22:57 UTC by nemiosrein

  • Code folding for: for, if, while statements

    Is there a way to enable codefolding for VHDL if, for, while statements?.

    2009-11-13 10:51:29 UTC by nemiosrein

  • VHDL Parse: generate statement

    Following code produces a syntax error. But it should be ok. ImplOpcodeTest: if (opcode_test_mode_c>0) generate OpcodeTest: process Seen in version 0.6.3 and 0.7.

    2009-11-05 10:45:29 UTC by pammerf

  • VHDL Parse: file statement in VHDL87 syntax

    Following code produces an syntax error. But it should be ok. It's in the 87 standard OpcodeTrace: process(clk_i ) file trace_file_f : text is out "STD_OUTPUT"; -- VHDL'87 begin ... Seen in version 0.6.3 and 0.7.

    2009-11-05 10:41:24 UTC by pammerf

  • VHDL93 component binding

    Hello & thank you very much for this plugin! Would it be possible to improve the hierarchy browser to recognize VHDL93 component instantiation, e. g: ... dut: entity test_lib.test(rtl) generic map (...) port map (...); ... Thanks in advance, Alex.

    2009-10-29 12:32:18 UTC by nobody

  • Version 0.7.0 Released

    Version 0.7.0 is released. Thanks to Stijn Last and his team for submitting most of the new features. Here's a list of what's new: * Goto Definition now also searches in packages of other files, not only in current file. * Solved few bugs, added alignment on :,=> and <= (e.g. if <= is present on multiple lines under each other this operator is aligned) * Hoovering over the...

    2009-10-27 20:04:05 UTC by aghoras

  • Eclipse Verilog editor

    aghoras made 1 file-release changes.

    2009-10-27 19:55:07 UTC by aghoras

  • Eclipse Verilog editor

    aghoras made 1 file-release changes.

    2009-10-27 19:52:01 UTC by aghoras

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