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  • Committed [r708]

    Add AutoEditStrategy for Verilog multi-line com...

  • Created a blog post on Eclipse Verilog editor

    Vesion 1.2.1 Released

  • Committed [r707]

    Evaluate signal reference in Verilog condition ...

  • Committed [r706]

    Exclude Verilog signals from the full source co...

  • Committed [r705]

    Limit selection occurrence as whole word

  • Committed [r704]

    Fix unresolved variable problem start with "pr"

  • Committed [r703]

    Merge from Sjors Hettinga's repository

  • Committed [r702]

    Merge from Sjors Hettinga's repository

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tadashi-k
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