Re: [Qucs-devel] problem with node initial value setting

[Stefan J. <st...@gr...>]

Am So, 1.04.2007, 05:23, schrieb Ozgur Cobanoglu:

> Dear *,

Hi Ozgur,

> just to inform you that I wanted to set an initial value for a wire in a
> digital sim. (e.g. to form a ring oscillator) but if I set a value through
> the GUI by double clicking on the wire and give a value, it does not work
> both within Verilog or VHDL. The initial value line is put strangely (or
> am I doing something wrong ?).
>
> Here are the file beginnings :
>
> oc@olmak:~/.qucs> more digi.v
> // Qucs 0.0.12  /home/oc/.qucs/deneme_prj/ringOscillator.sch
> `timescale 1ps/100fs
> NodeSet:NS0 nettap1 U="0"
> module TestBench ();
> ...
>
> and
>
> oc@olmak:~/.qucs> more digi.vhdl
> -- Qucs 0.0.12  /home/oc/.qucs/deneme_prj/ringOscillator.sch
> entity TestBench is
> end entity;
> use work.all;
> NodeSet:NS0 nettap1 U="0"
> architecture Arch_TestBench of TestBench is
> ...

Ok, it is a bug, that these settings are put into VHDL/Verilog files.
I can fix this.

So what do you propose for VHDL/Verilog how this feature could be
implemented?  Or should they just be left out?

Thanks in advance, Stefan.