From: David B. <da...@pa...> - 2009-12-31 12:03:02
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On Thursday 31 December 2009, Antonio Borneo wrote: > On Thu, Dec 31, 2009 at 9:01 AM, David Brownell <da...@pa...> wrote: > > Do you have a strategy for finding these, or are you just > > tripping over these problems? Either way is fine, but I'm > > curious. > > At the beginning, just by chance. Well please keep it up! ;) > I'm adding support to new SOC and board based on arm926, and a new JTAG device. > In my preliminary config file I've put "arm9 vector_catch reset" to > deal with reset before fine tune SRST. > I got first segfault with board powered off. > Once found the root cause, I checked all the other points the same > variable is used. > I think that code for arm7_9 is now clean, but I'm not sure about other CPU. I figure those ARMv4 and ARMv5 class machines are probably the majority of current users, so that's good news. :) I was just noticing something via the new helptext ... there seem to be various commands which are allowed to run in the wrong stages. That suggests slightly more systematic fixes, but of course I won't be able to have the helptext announce those issues to me except for the CPUs I end up testing with. > > And do you have positive test results on the semihosting? > > Not tested. So that was one bug you found by code inspection ... ;) > It requires dedicated code on target side, while my target doesn't have. I'm not sure what you mean by "dedicated", but all you should need is something like the CodeSourcery EABI toolchain; that includes the libraries. A "hello world" should suffice. Of course that does imply you'd actually set up and test that. I've not tried, yet, but it's on my agenda. For now it's only for ARM7/ARM9, and I'm looking at other cores just now. I *really* want to see a few positive test reports for the semihosting, from folk other than Nico (who wrote thate). - Dave |