Re: [Iverilog-devel] iverilog 10.0 compile error

[Iztok J. <izt...@gm...>]

Hi,

Could you check the direction of the 'wen' port inside the
module llvm_mapl_blockram_sync_8x93bit? And perhaps if there are any
asignments to the wen signal inside the module.

Some simulators ignore signal directions, but check for multiple drivers.
So although the direction is wrong, the design might be functionally
correct.

Regards,
Iztok Jeras

On Tue, Jan 12, 2016 at 6:10 PM, Lonnie L Gliem <lg...@sr...>
wrote:

> I ran into some verilog code that iverilog is failing to compile but vcs
>
> does.
>
>
>
> It appears the problem is having the reg on the right side of an
> instantiation.
>
> If I comment out the line .wen  (rmw_busy_fifo_wen) it compiles.
>
>
>
> Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the wire it
> compiles.
>
>
>
> I have several of these in one module and they all fail the same.
>
>
>
> Here are the iverilog errors:
>
>
> /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066:
>
> error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
>
>
> /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068:
>
> error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
>
>
>
> Thanks
>
> Lonnie
>
>
>
> reg rmw_busy_fifo_wen;
>
>
>
> always @ (posedge sysclk or posedge user_reset)
>
>    if (user_reset)
>
>       rmw_busy_fifo_wen <= 1'b0;   <----- this is line 2066
>
>    else
>
>       rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy | obm_busy))
> | <--- this is 2067
>
>
> (set_normal_wr_patha & (obm_read | obm_read_d1)));
>
>
>
> llvm_mapl_blockram_sync_8x93bit                 rmw_busy_fifo (
>
>                 .out    (rmw_busy_fifo_rd[92:00]),
>
>                         .almost_empty  (rmw_busy_fifo_almost_empty),
>
>                                 .empty (rmw_busy_fifo_empty),
>
>                                 .data_valid (rmw_busy_fifo_valid),
>
>                                 .almost_full (rmw_busy_fifo_full),
>
>                                 .inbit      (rmw_busy_fifo_wrdata[92:0]),
>
>                                 .ren  (rmw_busy_fifo_ren),
>
>                                 .wen  (rmw_busy_fifo_wen),
>
>                                 .ce   (1'b1),
>
>                                 .clk  (sysclk),
>
>                                 .rst  (user_reset)
>
>                                 );
>
>
>
>
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