Bugs Maximize Restore

Please browse the reported bugs/issues for Icarus Verilog at your pleasure. If you think you have found a bug of your own, first browse the existing bugs and feature requests to determine whether your bug has already been reported by someone else. It is far better to expound on an existing bug report then to create a new bug report for the same thing. If you find that your issue matches an existing report, then click on that issue page to get details. You have the option of adding comments to the bug report. Also, you will be able to monitor any existing bug report. If you have convinced yourself that your bug really is unique, then use the Submit link to start the bug submission.

The priority breakdown reflects the priority that the Icarus Verilog development team intends given the nature of the problem. This is how the Icarus Verilog team assigns priority:

3 - minor issues like invalid or missing warnings, spelling fixes, etc.

4 - functionality that is missing, but is not currently needed or can be worked around with code changes,

5 - The catch all for run-of-the-mill bugs, or unreviewed bugs,

6 - an invalid result without a warning that can be worked around; or use this priority for a program crash that is preventing one from using Icarus Verilog,

7 - An invalid result without a warning that cannot be worked around reasonably.

9 - Imminent nuclear death, meteor impact, or hysterical screaming boss.

The "Owner" field is used by the core Icarus Verilog developers to claim a bug report. Somebody may be working on unassigned reports, but when it is assigned then that individual is explicitly stating that they are (intend) to work on it. If you wish to contribute towards fixing a claimed bug report, please coordinate with the claimant.

Showing results of 34

# Summary Milestone Status Owner Created Updated Priority
958 Unable to successfully import a class from a package. devel open 2014-09-11 2014-09-11 5  
957 No support for SV compilation unit classes, tasks or functions devel open Stephen Williams 2014-09-11 6 days ago 5  
956 sv package enumerated type and function devel open Cary R. 2014-08-21 2014-09-17 5  
954 specify block delays break when multiple inputs have the same driver devel open 2014-04-27 2014-04-27 7  
953 Variable out of bound multi-dim array accesses are broken devel open 2014-03-19 2014-03-20 7  
948 user-func call may return incorrect value in a CA context v0.9 open 2014-03-01 2014-03-02 6  
944 VHDL enum type declaration generates syntax errors devel open 2013-12-09 2014-08-25 5  
943 VHDL enum values not available outside of switch statements devel open 2013-12-09 2014-01-01 5  
941 VHDL attributes not supported devel open 2013-12-09 2014-08-25 5  
928 No support for passing arrays (SystemVerilog) devel open 2013-04-18 2013-04-18 5  
908 Can't set arrays of reals using VPI devel open 2012-10-05 2012-12-10 5  
889 No support for annotating specparams from SDF file devel open 2012-05-07 2012-12-10 4  
888 Module path delays do not properly filter pulses devel open Martin Whitaker 2012-05-07 2012-08-09 6  
872 Issues cross-compiling 32-bit on a 64-bit (Linux) system v0.9 open Cary R. 2011-12-19 2011-12-19 5  
858 VHDL signal initialization doesn't detect errors devel open 2011-11-10 2012-12-10 4  
836 various attributes not parsed devel open 2011-02-24 2011-03-21 4  
829 VVP error when trying to $dumpvars real array devel open 2010-11-18 2012-12-10 5  
772 another possible sensitivity bug? devel open 2010-02-14 2010-03-11 5  
740 Timing checks are not supported. devel open 2009-10-28 2009-10-28 5  
733 VCD or $monitor() can contain changes from unchanged values v0.9 open 2009-10-08 2010-01-02 4  
698 $urandom with seed parameter treats seed as inout devel open 2009-06-19 11 hours ago 5  
681 $monitor, $strobe, etc. can not use complex expressions devel open 2009-04-26 2013-02-08 5  
677 C. assigns with zero delay can create zero width glitches devel open 2009-04-03 2009-04-07 6  
630 Icarus Verilog accepts forward references too liberally devel open 2009-01-23 2012-12-10 4  
626 VHDL Declaring logic in scope type devel open 2009-01-21 2009-01-21 4  
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