Re: [Iverilog-devel] Icarus Verilog snapshot 20130827

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Hmm... I didn't see a syntax for allowing this, but it appears
that package_items can be in the root context, so that will make
it possible. So I guess this is a bug.

You will be able to put your classes in packages, though, and
that is what most people do.

On 08/28/2013 04:14 PM, Victor Lyuboslavsky wrote:
> Yes, compile works when the class is inside a program, but not when
> it is outside (like in another file). I'm using -g2012
> 
> Do you guys have a goal for when iverilog will support the UVM
> library?
> 
> 
> On Wed, Aug 28, 2013 at 4:03 PM, Cary R. <cy...@ya... 
> <mailto:cy...@ya...>> wrote:
> 
> Depending on the keywords/functionality you want to activate 
> -g2005-sv, -g2009 or -g2012 should all enable some level of 
> SystemVerilog.
> 
> And they do compile the following:
> 
> program main; class a; endclass endprogram
> 
> Cary
> 
> ------------------------------------------------------------------------
>
> 
*From:* Stephen Williams <st...@ic... <mailto:st...@ic...>>
> *To:* ive...@li... 
> <mailto:ive...@li...> *Sent:* Wednesday,
> August 28, 2013 1:49 PM *Subject:* Re: [Iverilog-devel] Icarus
> Verilog snapshot 20130827
> 
> 
> You have to enable SystemVerilog support with the "-g2009" or 
> similar flag. The default "generation" is to stick with 1364-2005, 
> which is baseline Verilog. The -g2009 flag enables 1364-2009 
> features, which includes SystemVerilog.
> 
> On 08/28/2013 01:40 PM, Victor Lyuboslavsky wrote:
>> Steve,
> 
>> You mentioned the snapshot has class support. I'm not seeing it. 
>> The following simple example doesn't compile with iverilog:
> 
>> class a; endclass
> 
>> Thanks, Victor
> 
> 
>> On Tue, Aug 27, 2013 at 10:22 PM, Stephen Williams 
>> <st...@ic... <mailto:st...@ic...>
> <mailto:st...@ic... <mailto:st...@ic...>>> wrote:
> 
> 
>> Yep, I made a snapshot. The last time I made a snapshot is, 
>> according to my git logs, December of 2012. That's been a while. 
>> And since this is a snapshot of the master development branch, 
>> there is no way I can come up with a usefully descriptive list
>> of bug fixes. But here is a list of grander points:
> 
>> *) Big chunks of SystemVerilog support, including various
>> complex types, classes, packages, etc. Still a work in progress,
>> but it should be a quite useable subset by now.
> 
>> *) Non-trivial chunks of VHDL (yes, VHDL) support. This is still 
>> very much a work in progress, more a harbinger of things to come 
>> then a useful tool at this point, but feedback is welcome.
> 
>> *) Added a new BLIF code generator. (ASIC guys may know what
>> this means.) In the process, I've resuscitated some of the
>> synthesis support in the core compiler. This turned out to be
>> easier then I thought, so, to some degree, synthesis is back on
>> the table.
> 
>> *) Cary has put a lot of work into his vlog95 code generator,
>> he's been posting progress reports along the way.
> 
>> *) Tons, and tons, and more tons of bug fixes, especially from
>> Cary and Martin, and others.
> 
>> Of course, I suspect a lot of people who are interested in 
>> snapshots are actually getting all of this by going directly to 
>> git, but it seems to me enough has piled on to go to another 
>> snapshot. So have at it!
> 
> 
> 
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- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
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