Re: [Iverilog-devel] System Verilog test

[Jared C. <jar...@gm...>]

Just ran it on what I have available...

ModelSim 10.0a and NCVerilog 06.20-s011 both passed

VCS Version C-2009.06 gave your expected compilation error.

In a quick scan of both 1800-2005 and 1800-2009 I didn't see any
language the explicitly disallows this.  Section 6.7 doesn't even
mention packed structures.  To me it seems to be pretty ambiguous
whether the members of a packed structure are considered different
nets/variables that can be referenced together as a whole with a
defined ordering, or the whole packed structure is a single
net/variable with named slices.  It seems the big-3 are interpreting
the former while you interpret the later?

Note that if you put "wire" in front of the "struct packed", then of
course they complain about the procedural assignment.

Jared

On Sun, Jan 29, 2012 at 3:43 PM, Stephen Williams <st...@ic...> wrote:
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> I am truly astonished. This is not at all what I expected based on
> my reading of IEEE1800-2005. Also, I'm getting contradictory results
> from a colleague using Modelsim. I'll try to find out the exact version
> that he is using, but I'm going to need to get this resolved.
>
> (It is as if in your runs the "packed" keyword is being ignored.)
>
> On 01/28/2012 08:59 PM, Michael Strelnikov wrote:
>> Modelsim 10.c passed as well:
>>
>>> vlog -sv test.v
>> Model Technology ModelSim SE-64 vlog 10.0c Compiler 2011.07 Jul 21
>> 2011 -- Compiling module test
>>
>> Top level modules: test
>>> vsim -c -do 'run -all; quit' test
>> Reading /CAD/modelsim/10c/modeltech/tcl/vsim/pref.tcl
>>
>> # 10.0c
>>
>> # vsim -do {run -all; quit} -c test # //  ModelSim SE-64 10.0c Jul
>> 21 2011 Linux 2.6.18-194.el5 # // # //  Copyright 1991-2011 Mentor
>> Graphics Corporation # //  All Rights Reserved. # // # //  THIS
>> WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION # //  WHICH
>> IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS # //
>> LICENSORS AND IS SUBJECT TO LICENSE TERMS. # // # Loading
>> sv_std.std # Loading work.test(fast) # run -all # PASSED #  quit
>>
>>
>> Best regards, Michael Strelnikov
>>
>>
>> On Sun, Jan 29, 2012 at 3:47 PM, Stephen Williams
>> <st...@ic...> wrote:
>>
>>
>> Huh, that's surprising. I have from another source results that
>> Modelsim is reporting an error for this example:
>>
>> ** Error: foo.sv(14): 'foo' is driven procedurally and
>> continuously.
>>
>> This is what I expect. I'm really surprised if neither NC or VCS
>> report an error there.
>>
>> On 01/28/2012 07:21 PM, Michael Strelnikov wrote:
>>>>> Both NC and VCS passed.
>>>>>
>>>>> Best regards, Michael Strelnikov
>>>>>
>>>>>
>>>>> 2012/1/29 Stephen Williams <st...@ic...>
>>>>>
>>>>>
>>>>> I've attached a SystemVerilog program that tests an
>>>>> interesting feature of SystemVerilog. I *think* this program
>>>>> should generate an error, but I'm only about 75% certain, so
>>>>> it would be helpful if someone could try this with some Big-3
>>>>> compilers.
>>>>>
>>>>> It issue in particular is that this packed struct has one
>>>>> member continuously assigned and another member behaviorally
>>>>> assigned. I think this is illegal for *packed* structures
>>>>> like this, and "Section 6.7 Nets, regs and logic" in the LRM
>>>>> seems to be explicit about this case. I just want to make
>>>>> extra sure.
>
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
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