Re: [Iverilog-devel] Default port values in Verilog?

[Larry D. <ldo...@re...>]

Steve -

On Thu, Apr 29, 2010 at 01:45:32PM -0700, Stephen Williams wrote:
> I'd be OK with supporting default ports a la SystemVerilog and
> enabling then with the -g2009 flag. Strikes me as a fun little
> project for someone.

OK.  In order for me to acually use a construct, I need synthesis
tools (mostly Xilinx XST) _and_ iverilog to support it.  I'll keep
it in mind for the future, and check out each new release of XST
to see if they add it.

   - Larry