Re: [Iverilog-devel] Problems with wires' names in module instantiation

[Wojciech A. K. <wkoszek@FreeBSD.org>]

On Wed, Sep 17, 2008 at 06:07:58PM -0700, Cary R. wrote:
> --- On Wed, 9/17/08, Wojciech A. Koszek <wkoszek@FreeBSD.org> wrote:
> 
> > Please note that I even don't get a warning about buggy
> > ``r_i'' reference
> > in module ``ivt''. This looks like a regression
> > from the previous version.
> 
> Try using -Wall. It will report all four problem nets as
> implicitly defined. It even gives the file name, line number
> and full scope name!

Any reason why such warnings doesn't show up without passing additional
switches?

-- 
Wojciech A. Koszek
wkoszek@FreeBSD.org
http://people.freebsd.org/~wkoszek/