Re: [Iverilog-devel] GSoC Proposal Verilog Unit Test

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Hi,
I'll try to explain in a good way.
I'm using a 16 bits fulladder as example. It's simple, however can helps
us to understanding the tool. The rule file can be much more complex.
I try to eliminate the reference model putting high level language to
do its function.

Ok let's go.

#############################################
#The 16 bits fulladder rule file should be: #
##############################################################
 1     <vut module_name="fulladder_16bits">
 2      <time_scale t_div="10" unit="ns"/>
 3      <waveform>
 4            =================================================
 5            a[7:0]     i@|0000|0000|ffff|ffff|R1|R3|R4|R3|R2|
 6            -------------------------------------------------
 7            b[7:0]     i@|0000|ffff|0000|ffff|R2|R3|R1|R1|R4|
 8            =================================================
 9            result[7:0]o@|0000|ffff|ffff|0000|...res
10            -------------------------------------------------
11            overflow   o@|0   |0   |0   |1   |...tmp
12            =================================================
13        </waveform>
14        <gen_with>
15            R1 = (0,ff)
16            R2 = (ff,fff)
17            R3 = (fff,1fff)
18            R4 = (1fff,ffff)
19            <python_code var="res">lambda a,b: a+b</python_code>
20            <python_code var="tmp">lambda a,b: (a+b) > 0xffff and 1 or
0</python_code>
21        </gen_with>
22    </vut>
###############################################################
Line 1: Module name

Line 2: Define Timescale

Line 3: Begin waveform behavior definition. The test will be guided
by the defined waveform.
Lines 5,7: Input definition with random values
Lines 9,11: Output definition with random values
Lines 4,6,8,10,12: Ignored

Line 14: Begin the random generation directives
Line 15,16,17,18: Intervals to the random range generation
Line 19,20: Describes the actions that must be executed using
the a:Rx and b:Ry values to fill the result and overflow values.

For example:
    at the 5th time division let's assumes R1=0x13 and R2=0xf4a , so the
    result output will receive R1+R2 (0x13 + 0xf4a) that will be 0xf5d
    and the overflow output will receive 0 (0xf5d < 0xffff).

According the waveform tag it will be create memory files which it will be
used
in the simulations (i_a.mem, i_b.mem, o_result.mem and o_overflow.mem)

########################
#File example i_a.mem: #
############################################
//@This file was generated by VUTGenerator@
//@Do not edit! VUTWarning@

0000
0000
ffff
ffff
0013
100f
acff
b0a0
0800

############################################

Alternatively we can use the follow tag to avoid memory generation:
<waveform>
    =================================================
    a[7:0]     i@|use_mem_file("my_a_memory.mem")
    -------------------------------------------------
    b[7:0]     i@|use_mem_file("my_b_memory.mem")
    =================================================
    result[7:0]o@|0000|ffff|ffff|0000|...res
    -------------------------------------------------
    overflow   o@|0   |0   |0   |1   |...tmp
    =================================================
</waveform>

#############################
#The skeleton Generated is: #
################################################
/*
@The skeleton was generated by VUTGenerator@
=======================================
module_name: fulladder_16bits
---------------------------------------
Author: <author>
Data: <date>
---------------------------------------
Description: <description>
=======================================
*/

module fulladder_16bits(a,b,result,overflow);
//Inputs
    input [15:0] a;
    input [15:0] b;

//Outputs
    output [15:0] result;
    output overflow;

//Wires
    wire [15:0] a;
    wire [15:0] b;

//Regs
    reg [15:0] result;
    reg overflow;

//Behavior

endmodule
################################################
It is generated based in the input and output information passed in the
waveform tag.

##############################
#The TestBench generated is: #
###############################################################

/*
@This UnitTest was generated by VUTGenerator@
@Do not edit! VUTWarning@
=======================================
module_name: vut_fulladder_16bits
---------------------------------------
Author: <author>
Data: <date>
---------------------------------------
Description: <description>
=======================================
*/

module vut_fulladder_16bits();

//Wires
    wire [15:0] result;
    wire overflow;

//Regs
    reg [15:0] a;
    reg [15:0] b;

//Behavior

    reg [15:0] mem_a [0:9];
    reg [15:0] mem_b [0:9];
    reg [15:0] mem_result [0:9];
    reg mem_overflow [0:9];
    reg [15:0] tmp_result;
    reg tmp_overflow;
    integer k;
    event send, ready;

    fulladder_16bits test(
        .a(a),
        .b(b),
        .result(result),
        .overflow(overflow));

    initial $readmemh("i_a.mem",mem_a);
    initial $readmemh("i_b.mem",mem_b);
    initial $readmemh("o_result.mem",mem_result);
    initial $readmemh("o_overflow.mem",mem_overflow);

    initial begin
        $dumpfile ("waveform.vcd");
        $dumpvars;
        #1;
        a = 0;
        b = 0;
        k = 0;
        #4 -> ready;
    end

    always @ ready begin
        a = mem_a[k];
        b = mem_b[k];
        tmp_result = mem_result[k];
        tmp_overflow = mem_overflow[k];
        k = k + 1;
        if (k > 10) begin
            $display("|VUT_OK| > All the signals are right-right!\n");
            #5 $finish;
        end //if
        else #2 -> send;
    end

    always @ send begin
        if (result !== tmp_result) begin
            $display("|VUT_FAIL|> Error in result value at time
%0dns!!!",$time);
            $finish;
        end //if
        if (overflow !== tmp_overflow) begin
            $display("|VUT_FAIL|> Error in overflow value at time
%0dns!!!",$time);
            $finish;
        end //if
        #3 -> ready;
    end

endmodule
###################################################################################

During the simulation, if occur any error, the simulation will stop
and will show the exact error's time.

Example:
    At the 22ns of the simulation the result should be 0x1111 and it is
    0x1110 the simulation will stop and the message "|VUT_FAIL|> Error in
result value at time 22ns!!!"
    will appear.
    In case of the simulation finishes without errors the message
    "|VUT_OK| > All the signals are right-right!" will appear.

Ok, just it..

Is it clear? If not, I can write more, no problem! :)

Thank you all.

If there are any suggestions, doubts or critics go ahead! I'm waiting
feedback! :D

Ps.: Sorry my English..

Best Regards,
===================================================
Rodrigo José Sarmento Peixoto
-----------------------------------------------------------------------------------------------------
UFPE - CIn ( Engenharia da Computacao )
Skype: rodrigopex
msn: rod...@ho...
-----------------------------------------------------------------------------------------------------
Participante dos projetos:
- HPCIn (Petrobras)
- EriMont (Amadeus)
Projeto de extensão: Inclusão digital escola Padre Machado
Membro do CInLUG: www.cinlug-br.org
===================================================