This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.

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Categories

Hardware, Scientific/Engineering

License

Mozilla Public License 1.1 (MPL 1.1)

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Additional Project Details

Languages

English

Intended Audience

Science/Research, Education, Developers

Programming Language

Assembly

Related Categories

Assembly Hardware Platform, Assembly Scientific Engineering

Registered

2003-06-03
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