===============================================================================
RELEASE NOTES : Kactus2
Copyright (c) 2012-2025 Tampere University
https://research.tuni.fi/system-on-chip/tools
===============================================================================
+ Improvement or feature added
- Bug fix or something removed
* Changed or Information
===============================================================================
08/05/2025 3.13.5
----------------------------------------------------
- Fixed bug introduced in 3.13.4 where rows couldn't be removed in some table editors
- Fixed VLNV editor crash and improved tab and shift+tab behaviour
- Fixed a crash when creating a register inside a register file inside another register file
* Changed default AUB for CPUs and address spaces to 8 bits
24/04/2025 3.13.4
----------------------------------------------------
* Reworked memory designer to correctly show memory connections
* Designer now shows each address space as separate connection sets
* Items can be displayed in multiple connections
* Target-initiator path search now finds multiple paths instead of just the shortest
* Simple view of the designer excludes connections that are out of bounds (of connected address space)
* Simplified file dependency scanning. File dependencies are no longer stored in IP-XACT files, except if manually created.
+ Added option to toggle memory overlap on and off in memory designer
+ Added ability to create IP-XACT 2022 components and designs through the Python API
- Fixed Verilog and VHDL dependency scanning. Only file set files are scanned for dependencies, other dependencies are marked as external.
- Fixed removal of multiple non-contiguous rows in tables
- Fixed writing tied value of ad-hoc port with direction out (Verilog generator)
14/10/2024 3.13.3
----------------------------------------------------
* Document lock made optional. Can be changed in settings, locking is disabled by default.
+ Added parameter editors to abstraction definition editor and bus definition editor, added expression support to port abstractions
+ Added HW Designer tool shortcuts
+ Added ability to open referenced bus and abstraction definitions in bus interfaces by right-clicking in the component editor tree
+ Improved validation in the component editor
+ Improved windows installer
- Fixed launching Kactus2 in CLI mode on Windows
- Fixed design parameter dock window disappearing when switching tabs
- Fixed changes made in component editor not reflecting in edited design (bus interfaces, ports)
- Fixed issue with expression editors scrambling expression when overwriting current expression or a section of it
- Fixed parsing unary minuses in systemverilog expressions
- Fixed component mode condition validation
- Fixed various bugs leading to crashes
23/04/2024 3.13.2
----------------------------------------------------
+ HW Design improvements
* Added interconnection highlighting when hovered over
* Widened interconnection hitboxes to make them easier to select
* Added checks for double connections between component instances
* Reworked component instance auto connector tool to enable editing existing connections between component instances
* Reworked memory designer
- Fixed source importers not detecting filetype of files with absolute paths
- Fixed creating new design configurations in the HW design configuration editor
- Fixed AUB editors in memory map to accept expressions, AUB defaults to 8 bits when empty
- Fixed crash in bus interface wizard caused by non-existent abstraction definition
- Fixed the created bus interface from bus interface wizard not appearing in the editor
- Fixed validation in abstraction definition ports editor
- Fixed coloring of mirrored initiator interfaces
- Fixed logical port creation for abstraction definitions in bus interface wizard
13/02/2024 3.13.1
----------------------------------------------------
+ Prevent drag & drop between cross-standard revision components, designs etc.
- Fixed missing fields in memory map visualizer on linux
- Fixed crash when adding generated files to fileset when using specific generators
- Fixed modelsim generator crashing in rare cases when changing generation output directory
- Fixed portmap editor for 2022 standard
- Fixed connectivity graph for 2022 standard
08/12/2023 3.13.0
----------------------------------------------------
+ Added IP-XACT 2022 standard support for existing Kactus2 workflows
* Now possible to create and edit IP-XACT components compliant with the new 2022 IP-XACT standard
* Old 2014 standard is still supported
* IPs can be filtered by standard revision in the library
* Power domains added as a new feature of the IP-XACT 2022 standard
- Fixed memory map visualization not showing overlap in some cases
- Other fixes and tweaks in memory map visualization
- Fixed Linux build issues (community contribution)
- Fixed crashing when starting PythonAPI from Python
07/06/2023 3.12.0
----------------------------------------------------
+ Updated user interface visuals
* Changed only one side editor to be visible on left and right
* Added sidebars for controlling side editor visibilities
* Updated side editor colors
* Updated library layout and filters
* Updated lots of icons
* Updated Component editor navigation tree to show modified elements
* Updated Design editor column and grid color
* Relocated script editor from side editor to the right side of main window
* Relocated Component preview to LibraryWidget
* Relocated all generator plugins under one button in toolbar
+ Improved documentation generation
* Added markdown format
* Added register files
* Added table of registers for each address block
* Added field enumerations
* Updated formatting for both HTML and markdown
+ Added validity check results in Component editor general page
+ Added new editor for selecting channels, abstraction types and file sets
+ Added Renode platform description generator as a plugin
* Added generation of platform description files (.repl) for CPUs, peripherals and memories
* Added configuration file for generation
- Fixed port ad-hoc status after importing from CSV file
- Fixed updating address space visualization when local memory map changes
- Fixed Design editor crashing with ad-hoc connection referencing non-existent port as endpoint
- Fixed library filters not being saved in settings
- Fixed crashing on Verilog generation (community contribution)
- Fixed generated indexing in Verilog when many interfaces map to the same physical port
- Fixed VHDL importing failing with last port on specific conditions
- Fixed reset mask default value in SVD generation
* Separated Abstraction Definition editor from Bus Definition editor
* Combined ad-hoc visibility and ad-hoc tieoff editor into one
* Changed build target directory to executable in Visual Studio
* Removed x86 build configurations in Visual Studio
17/01/2023 3.11.1
----------------------------------------------------
* Added missing Windows vista style library
12/01/2023 3.11.0
----------------------------------------------------
* Migrated to Qt 6.2.4, Qt5 build is no longer supported
+ Updated choice editor
+ Added line editor for expressions
+ Added doxygen flag to swig for better documentation of functions
+ Added undo/redo in Python script editor
+ Added support for ternary opertor (?:) in SystemVerilog expressions (community contribution)
+ Added width for port default values in generated Verilog (community contribution)
+ Added register dimensions in SVD generation
- Changed configurable element values of a component instance to use table instead of a tree view
- Improved port editor performance
- Improved configuration and help generation in Linux (community contribution)
- Fixed disappearing component remap states
- Fixed application settings losing code editor settings on startup
- Fixed Python script editor visibility to persist between documents
- Fixed Python interpreter thread not quiting at application shutdown
- Fixed component editor crashing after removing last memory map
- Fixed component editor crashing after removing memory remaps
- Fixed SVD generator crashing on sticky note with assosiaction
- Removed win32 build configurations for VS
* Migrated to VS2022
* Windows installer now embeds Python version 3.10.6
21/06/2022 3.10.0
----------------------------------------------------
+ Added bus interfaces in Python API
+ Added subspace maps to memory maps visualization
+ Replaced Python console in GUI with a text editor
+ Increased editor title sizes and marked Kactus2 extensions with an icon
+ Added automatic expansion of hierarchy for lone items in library views and
component editor tree.
+ Added register dimension indexing in SVD generator
+ Added checks and formatting for address-cells and size-cells in Linux Device
Tree Generator
- Removed file modification watches for XML files so changes on the disk are no
shown to user. The implementation was incompatible with standalone Python
script runs
- Removed exit screen
- Fixed crashing when creating connection in design with draft bus interface
- Fixed crashing for incorrect indexing with memory remaps
- Fixed crashing when reading invalid XML file
- Fixed design editor reordering component bus interfaces in XML
- Fixed Verilog generator parameter order
- Fixed Verilog generator module parameter values
- Fixed VHDL generics import stopping on semicolon in a comment
* Relocated common functions and library handling to new KactusAPI shared
library
* Changed port map editor tree format to a table format
* Migrated to Qt 5.15.2
* Kactus2 will migrate to Qt6 in version 3.11.
06/04/2022 3.9.333
----------------------------------------------------
+ Added subspace maps to memory maps
- Fixed configurable element value usage in design instantiations
19/01/2022 3.9.171
----------------------------------------------------
- Fixed inclusion of plugins to installer
- Fixed rare crashing in adding memory remaps
07/12/2021 3.9.168
----------------------------------------------------
+ Embedded Python 3.8 to Kactus2
+ Added SVD generation to Python interpreter
+ Updated Verilog generator path selection and file renaming
+ Ports can be created from bus interface abstraction definition
+ Added basic design handling to Python interpreter
* Component instances can be added and removed
* Interconnections can be created between bus interfaces
* Ad hoc connections can be created between ports
+ Updated Linux Device Tree Generator
* Added channels
* Added address blocks
* Added calculation for address and size cells
* Generates files for each found CPU
+ Added warning symbols for bus interfaces without connected port maps in HW design
24/06/2021 3.9.0
----------------------------------------------------
+ Added PythonAPI to provide access to Kactus2 through python code
* PythonAPI is separated from Qt
* PythonAPI folder contains example scripts
* PythonAPI can also use some generators (VHDL, Verilog, Linux device tree and Makefile)
+ Added KactusAPI class to provide library and utilities to PythonAPI
+ Added a console in GUI for interpreting python scripts
* Allows multiline code to be executed in Python on Windows console mode
* Added script history, run file and save function
+ Separated Kactus2 editor models into interfaces
* Ports
* Parameters
* Fields
* Field resets
* Registers
* Address block
* Memory maps
* Files
* File sets
* Component instantiations
* Port maps
* Port abstractions
* Bus interfaces
+ Added CMSIS System View Description (SVD) generator plugin
* SVD files can be created from a HW design
+ Added extend port abstractions to abstraction definition editor
+ Added depenency analysis for (system) Verilog module instantiations
- Fixed parameter string value parsing in Verilog import
- Fixed right port boundary in ConnectionEditor
- Fixed port map tables with non-existing ports
- Fixed document writing pointer sharing
- Fixed memory visualization
* Changed fields and field gaps for faster updates
* Fixed label resizing, positioning and clipping
* Fixed visualization on expanding items
* Fixed updating register files
* Updated visualization to correctly display over 32-bit long address ranges
- Fixed crashing when re-importing a file to a Component
13/11/2019 3.8.0
----------------------------------------------------
+ Improved support for Transactional ports
* Added editor in Component Editor
* Added transactional connections and interfaces in Design schematic
* Removed transactional ports from generated Verilog files
+ Added tags for component categorization and searchs in library
+ Improved RTL import
* Added option to browse for files outside file sets
* Added option to select one module/entity from a file containing multiple definitions
+ Added support for file set references in slave bus interfaces
+ Improved editing options for Other Clock Driver timing values
- Fixed an issue where "Save as..." on locked bus definition caused the application to crash
- Fixed Linux Device Tree Generator Plugin to correctly format one device tree instead of multiple
29/03/2019 3.7.0
----------------------------------------------------
+ Added auto connector tool for component instances in a design
+ Added editor for Vendor Extensions in Component and Design
+ Added support for register files
+ Added support for multiple reset values for register fields
+ Added scrolling to design view when items are dragged
+ Improved memory map visualization and library loading performance
+ Improved expression parsing
* Added support for bitwise operations
* Improved expression solving performance
+ Improved VHDL and Verilog support
* Fixed array and vector boundary handling
* Include Verilog file parameters are imported
* Imported parameter type is set based on the data type in VHDL
+ Improved HW design editor to accept connections between extended bus definitions
- Fixed an issue where removing an item in library did not remove the file on disk
- Fixed an issue where removing items in memory maps would cause the application to crash
- Fixed an issue where setting an empty bus interface mode would cause the application to crash
- Fixed an issue where design active views were cleared on save
- Fixed an issue where plugin details were incorrectly displayed in the settings
- Fixed an issue where component instance parameter override was incorrectly displayed when
using parameter choices
- Fixed an issue where multiline description was not correctly CSV imported/exported
29/06/2018 3.6.50
----------------------------------------------------
+ Added editor for AbstractionDefinition transactional ports
+ Added option to extend BusDefinitions
+ Added editor for field reserved-value
+ Added SystemVerilog files to be included in generated Quartus projects
- Fixed an issue where modifying/removing files outside Kactus2 caused the application to crash
- Fixed an issue where editing AbstractionDefinition port properties affected all modes
12/06/2018 3.6.0
----------------------------------------------------
+ Added support to run Kactus2 from command-line without GUI
+ Added editor for port type definitions
+ Added support for multiple abstraction definitions in a bus interface
+ Improvements to Memory Designer
* Improved item scaling in non-compressed mode
* Improved search through hierarchies
* Improved visulization for multiple address spaces connected to one memory map
+ Added feature to save HW, System and Memory Designer view as a PNG, JPG or SVG image
+ Improved expression parsing
* Support for exp, pow and sqrt functions
* Better suppport for string expressions and their comparison
* Faster parsing algorithm
+ Added Linux Device Tree Generator plugin
+ IP-XACT library handling improved for better performance and readability
+ HW and System design area size now adjusts to contents
- Restored automatic item selection in library view when component instance is selected
- Fixed addressSpaceRef-attribute parsing and writing
- Fixed export dialog from hierarchy view
- Fixed missing type information in VHDL generation
- Fixed error in entity parsing in VHDL import
- Fixed a crash when creating a new HW Design
- Fixed a crash in saving user settings for code editor
- Fixed an issue where Component file set directories were lost on refresh
* Changed binary name to kactus2 (previously Kactus2) in Linux
* Enabled C++11 by default in Linux compilation
* Improved Linux installation in user-specified directory
* Migrated to Qt 5.10.1
* Migrated to VS2017
23/11/2017 3.5.0
----------------------------------------------------
+ Graphical user interface visual update:
* All icons updated
* Instruction labels added in dialogs
* Colors centralized in KactusColors.h
+ Added feature to show the directory icons provided by OS for library paths
which shows version controlled items in Windows
+ Added feature to automatically update library view when file changes on disk
+ Added feature to select the which HW design to open for an IP-XACT component
with multiple designs
+ Added editor for indirect interfaces in component
+ Added editor for component instantiation parameters
+ Added editor for design configuration instantiation parameters
+ Added editor for design configuration instantiation configurable elements
+ Added editor for design instantiation configurable elements
+ Added feature to define prefix in port map auto-connect for better matching
+ Added editor for design parameters
+ Improved performance on drawing connections in design
+ Added delete in context menu in design view
+ Improvements in Memory Designer:
* Added support for multiple items accessing the same memory map
* Improved layout for items
+ Improvements in HTML generation:
* Added writing register and field reset values in HTML
* Added writing instantiations within a component in HTML
- Fixed error in XML schema location writing
- Fixed C source editor refresh
- Fixed port size parsign in PADS part generator which previously caused the
plugin to crash
- TLMW generator plugin removed from build
* Software component instance merged to component instance
* Changed VHDL import to create component parameters and retains references in
port boundaries
* Moved VHDL generator from core to a separate plugin
* ModelSim generator plugin moved to same framework as Verilog generator
22/03/2017 3.4.0
----------------------------------------------------
+ Enhanced features for Memory Designer:
* Added feature to visualize overlapping memory items
* Added feature to open the containing component and the editor for the selected item
* Added feature to visualize local memory maps
* Changed the visual look of a connection through a bridge
* Changed display name to be shown instead of element name, if defined
+ Improvements to Verilog generation:
* Added preview for generated files
* Added message console for reporting generation status
* Improved port assignment and vector boundary generation logic
+ Fixed error in importing Verilog ports
+ Added editor for Catalogs
+ Component editor layout updated for most editors
+ Enabled expressions in parameter value when using a choice
+ Added isPresent-property to memory maps, address blocks, address spaces and segments
+ Improved completion help for fileset filetypes and groups
+ Enabled CSV import/export of files in a fileset
+ Added feature to hide immediate values from configurable element values
+ Enabled keyboard navigation in VLNV tree view
+ Added expand/collapse options in VLNV tree view context menu
+ Help and tooltips updated
+ Custom XML namespaces are retained in XML files
- Removed address space reference and base address from mirrored-master bus interface
- Fixed crashing when adding port maps in component
- Fixed a referencing issue with configurable element values when changing active view
- Fixed crashing when a design did not have a configuration
- Fixed crashing when closing a design in specific cases
- Fixed modifications to design connections while the document was unlocked
- Fixed CSV import/export of signal definitions in abstraction definition
- Fixed missing component editor visibility options
* System mode bus interface coloring changed from red to purple to avoid confusion with invalid interfaces
* Changed "frozen column" in editors to use vertical headers instead of a separate table
* Toolbar "Check intergrity" changed to show listing of all errors within the library
in separate window.
* Exit screen is displayed longer
09/12/2016 3.3.0
----------------------------------------------------
+ Enhanced features for Memory Designer:
* Register fields added
* Compression of items to minimize the required space
* Multiple address spaces can now be shown as part of the same connection
* Filtering options added
+ Memory connectivity analysis now manages also instances with identical names
+ File paths within filesets now accept URI expressions
+ Files can be drag-dropped to filesets from the file system
+ Memory map visualization items have now bigger area for expand/collapse
+ Port direction is now checked when a default value is set
+ Port map invert and tieoff are now also shown on the top level of tree hierarchy
+ Zooming now follows mouse location in design
+ Enhanced usage of drafts in design:
* Bus interface definitions copying when connecting hierarchical draft interface fixed
* Bus interface definitions copying when connecting non-hierarchical draft interface removed
* Bus interface definitions and port copying to draft instances changed to take place on
packaging of the containing draft component instance
* Copy-paste of bus interface to a draft component instance changed to copy only the name and
the mode of the interface
+ Notification on trying to read XML files of previous standard versions added
+ Improvements to Verilog generation:
* Generation setup dialog simplified
* Register definition creation set as optional
* Module name is correctly used for component instances
* Environmental identifier created by the generator changed
+ Improvements to Verilog import:
* Port type parsing improved for Verilog-2001 style ports
* Parameter parsing improved for lists of parameters
* Environmental identifier created by the import changed
+ Improved features for MakefileGenerator:
* Conflicting file selection added
* Launcher script creation set to optional
- Bus interface creation wizard fixed from preventing user to proceed from the general
settings page due to missing port maps
- Component instance replace in design changed to better preserve existing connections
- Port bounds for ad-hoc connections in design fixed
- Author information read from XML fixed
- Symbolic file link usage for XML files fixed
- Toolbar placement at the bottom of main window fixed
- Software views are replaced by views and component instantiations
* Community guidelines included in manual
* Settings file path is now shown on the General page of Settings
* Automatic port mapping changed to less aggressively connect ports
* Component instance architecture changed to be correctly set by VHDL generator
KNOWN UNRESOLVED ISSUES:
* UI issue: paste command does not update usage count of referenced parameters
05/10/2016 3.2.35
----------------------------------------------------
+ Enabled URIs to be used in filepaths for files within filesets
+ Improved memory design layout of items
- Fixed bug preventing signal renaming in Abstraction Defintions
KNOWN UNRESOLVED ISSUES:
* UI issue: paste command does not update usage count of referenced parameters.
23/09/2016 3.2.0
----------------------------------------------------
+ Added preliminary version of memory designer:
* Address spaces and Memory maps within design hierarchy are visualized with their
addressing information
* Connectivity between spaces and maps are visualized
+ Added preliminary version of memory connectivity analysis within designs
* Added plugin for generating memory listing in CSV format
+ Improvements to Verilog generation
+ Added "Getting started" section to help
+ Fixed performance issues
- Fixed crashing when opening a bus interface without abstraction definition
* ModelSim Generator moved from core to a separate plugin
KNOWN UNRESOLVED ISSUES:
* UI issue: paste command does not update usage count of referenced parameters.
17/06/2016 3.1.0
----------------------------------------------------
+ New design for port map editor:
* Added feature to auto-connect logical and physical ports
* Logical and physical bounds are now easily editable
+ Added support for tieoff values in design and port maps
+ Added feature to copy memory-elements along with their sub-elements
+ Improved expression support:
* Basic comparison operators are now accepted
* Values true/false are now accepted
+ System group names are now visible and editable in Bus editor
+ Generated Verilog parameters are now correctly ordered for references
+ Performance improvements
* ModelSim Generator moved from core to a separate plugin
* XML processing instructions are now retained in IP-XACT files
* Added option for Linux installation without admin privilidges
KNOWN UNRESOLVED ISSUES:
* UI issue: paste command does not update usage count of referenced parameters.
22/04/2016 3.0.0
----------------------------------------------------
+ Updated all IP-XACT elements to 2014 standard
+ Improved validation for many IP-XACT elements
+ Updated Verilog generation for one-to-many ad-hoc connections.
+ Added new view related editors for component editor:
* Component instantiations
* Design instantiations
* Design configuration instantiations.
+ Updated port editor to accept ports without defined left and right bounds as ports with a width of 1.
+ Updated parameter referencing.
+ Updated expression parser.
+ Updated component editor memory map visualization.
+ In component editor, changed cut command to copy and remove selected cells of a table.
+ Updated HW design editor:
* Updated component instance creation.
* Updated component instance removing.
* Updated component instance replacing.
* Updated connection removing.
* Invalid ad-hoc interfaces and ports are displayed with a red colour.
* Enabled deleting of invalid ad-hoc interfaces and ports.
+ Usability fixing.
KNOWN UNRESOLVED ISSUES:
* UI issue: paste command does not update usage count of referenced parameters.
18/03/2016 3.0.0 RC2
----------------------------------------------------
+ Fixed Linux compilation
+ Added support for expressions in file build command flag replace
+ Improved element validation with large numbers
+ Improved expression evaluation performance
+ Other minor improvements to usability
- Corrected loading sticky notes in design editor
KNOWN UNRESOLVED ISSUES:
* Memory map header generation from a system design does not work properly.
* SystemVerilog expressions are not supported by some features including generators.
If expressions or references have been used, it may cause at least the following issues:
* VHDL generator will generate wrong values.
* Port maps will not automatically adjust to changes in port size.
* VHDL import does not preserve references to model parameters.
* In ports editor, creating a bus interface through ports is not possible for name column.
* VHDL generator crashes unexpectedly during run
29/02/2016 3.0.0 RC1
----------------------------------------------------
+ Updated all IP-XACT elements to 2014 standard
+ Improved validation for many IP-XACT elements
KNOWN UNRESOLVED ISSUES:
* Memory map header generation from a system design does not work properly.
* Parameters created with version 2.7.0 may not work with the latest release due to
change in id formatting. The fastest way to fix this is to re-create the parameters.
* SystemVerilog expressions are not supported by some features including generators.
If expressions or references have been used, it may cause at least the following issues:
* VHDL generator will generate wrong values.
* Port maps will not automatically adjust to changes in port size.
* VHDL import does not preserve references to model parameters.
* In ports editor, creating a bus interface through ports is not possible for name column.
* VHDL generator crashes unexpectedly during run
15/06/2015 2.8.0
----------------------------------------------------
+ Added feature to import parameters from include files.
+ Improved configurable element variables editor
* Synchronizes with the enhanced model parameter definition.
* The parameters of the top component can be used in the configurable element variables.
* Variables are now grouped according to their location in the component.
+ Added editors for IP-XACT elements remapState and memoryRemap.
+ Added support for expressions in memory map elements.
+ Added support for parameter references in generated header files.
+ Added feature to save new versions of design configurations and designs.
+ Added support for module parameters to hierarchical views.
KNOWN UNRESOLVED ISSUES:
* Memory map header generation from a system design does not work properly.
* Parameters created with version 2.7.0 may not work with the latest release due to
change in id formatting. The fastest way to fix this is to re-create the parameters.
* SystemVerilog expressions are not supported by some features including generators.
If expressions or references have been used, it may cause at least the following issues:
* VHDL generator will generate wrong values.
* Port maps will not automatically adjust to changes in port size.
* VHDL import does not preserve references to model parameters.
* In ports editor, creating a bus interface through ports is not possible for name column.
13/05/2015 2.7.970
----------------------------------------------------
+ Added support for SystemVerilog expressions in memory map and address space visualization
+ Added register dimensions in memory map visualization
+ Added remaps for memory maps
+ Added support for SystemVerilog expressions in generated memory map header files
excluding generation from a system design
+ Improvements in memory map editor user interface
KNOWN UNRESOLVED ISSUES:
* Memory map header generation from a system design does not work properly.
* Parameters created with version 2.7.0 may not work with the latest release due to
change in id formatting. The fastest way to fix this is to re-create the parameters.
* SystemVerilog expressions are not supported by some features including generators.
If expressions or references have been used, it may cause at least the following issues:
* VHDL generator will generate wrong values.
* Port maps will not automatically adjust to changes in port size.
* VHDL import does not preserve references to model parameters.
09/04/2015 2.7.572
----------------------------------------------------
+ Added import for Verilog defines as component parameters
+ Added dependency analysis for Verilog include directives
+ Added grouping of configurable element values according to location in component
+ Added placeholder for remap states in component editor
* Changed types in Plugin and Source analyzer plugin interfaces
KNOWN UNRESOLVED ISSUES:
* Parameters created with version 2.7.0 may not work with the latest release due to
change in id formatting. The fastest way to fix this is to re-create the parameters.
* SystemVerilog expressions are not supported by some features including generators.
If expressions or references have been used, it may cause at least the following issues:
* Memory map header generator will generate wrong offsets for registers.
* Memory maps visualization shows wrong offset for register and aligns them wrong.
* VHDL generator will generate wrong values.
* Port maps will not automatically adjust to changes in port size.
* VHDL import does not preserve references to model parameters.
27/03/2015 2.7.463
----------------------------------------------------
+ Added support for referencing parameters in top component of a design.
+ Added new editor for parameter values in an array.
+ Improved validation of configurable element values:
* Minimum, maximum and type restrictions are enforced.
* Choices can be selected from drop-down list.
* Arrays can be edited in similar fashion to component editor.
+ Added support for enabling/disabling register fields.
+ Added support for expressions in AddressBlock base addrss, range and width.
+ Added validity checks and separate display for referenced designs in hierarchical views.
* Configurable element values are now stored by default in Design Configuration instead of Design.
* Renamed hierarchy level "Global" to "Flat".
* Changed Quartus Pin Import plugin to conform with Import plugin interface.
KNOWN UNRESOLVED ISSUES:
* Parameters created with version 2.7.0 may not work with the latest release due to
change in id formatting. The fastest way to fix this is to re-create the parameters.
* SystemVerilog expressions are not supported by some features including generators.
If expressions or references have been used, it may cause at least the following issues:
* Memory map header generator will generate wrong offsets for registers.
* Memory maps visualization shows wrong offset for register and aligns them wrong.
* VHDL generator will generate wrong values.
* Port maps will not automatically adjust to changes in port size.
* VHDL import does not preserve references to model parameters.
06/03/2015 2.7.192
----------------------------------------------------
+ Added support for references in Verilog generator.
+ Verilog importer accepts semicolons in comments.
+ Added memory maps and registers to html documentation.
+ Added support for references in import wizard.
* Replaced evaluated value with IDs in Verilog import.
+ Improved usability of expression editor.
+ Added support for references in document generator.
+ Implemented module parameters in views.
+ Added name as a frozen column to parameters, model parameters and module parameters.
* Name and port number columns were frozen in port table.
+ Where expressions are used, changed the table to show the expression by default.
* The tooltip now shows the evaluated value.
+ Register reset value and reset mask can now be inserted as a bit type value.
+ Arrays can be insterted as a value for parameters.
KNOWN UNRESOLVED ISSUES:
* Parameters created with version 2.7.0 may not work with the latest release due to
change in id formatting. The fastest way to fix this is to re-create the parameters.
* SystemVerilog expressions are not supported by some features including generators.
If expressions or references have been used, it may cause at least the following issues:
* Memory map header generator will generate wrong offsets for registers.
* Memory maps visualization shows wrong offset for register and aligns them wrong.
* VHDL generator will generate wrong values.
* Port maps will not automatically adjust to changes in port size.
* VHDL import does not preserve references to model parameters.
06/02/2015 2.7.0
----------------------------------------------------
+ Added support for SystemVerilog expressions in
* component parameter and model parameter value,
* component port bounds and default value,
* component register offset, size and dimension and
* design configurable element values.
+ Added support for referencing parameter and model parameter values in expressions.
+ Added autocomplete feature for available parameter names in expressions.
+ Added feature to view all elements referencing a parameter or model parameter.
+ Configurable element values editor now automatically shows the configurable
elements in component instance, their current and default value.
+ Added feature to show/hide elements of a component in component editor.
+ Added support for component choices.
+ Enabled different signal widths for master and slave modes in abstraction definition.
+ Improved ribbon toolbar.
KNOWN UNRESOLVED ISSUES:
* SystemVerilog expressions are not supported by some features including generators.
If expressions or references have been used, it may cause at least the following issues:
* Memory map header generator will generate wrong offsets for registers.
* Memory maps visualization shows wrong offset for register and aligns them wrong.
* VHDL and Verilog generator will generate wrong values.
* Port maps will not automatically adjust to changes in port size.
* VHDL import does not preserve references to model parameters.
31/10/2014 2.6.0
----------------------------------------------------
+ New plugin interface for file import.
+ New plugins:
* Verilog import.
* Verilog generator for components and designs.
* Makefile generator.
+ Added feature to run import from component editor.
+ Added editing of views to component wizard.
+ Added feature to sort port list by port number.
* Moved VHDL import tool to import plugin.
* Updated MCAPI to version 2.015.
* Updated MCAPI generator.
08/07/2014 2.5.0
----------------------------------------------------
+ All vendor extensions are conserved in IP-XACT documents.
+ Added feature to insert notes in designs.
+ Added feature to run files e.g. script files from Filesets.
+ Added feature to define default run executable for file types.
+ Improved lock operation: Enables browsing of tabs while the document is locked.
+ Added design column for memories.
+ Improved opening of hierarchical components in design.
+ Added feature to reorder bus interfaces in component editor.
- Fixed library crashing with Abstractor objects.
- Fixed other minor bugs and usability issues.
07/02/2014 2.4.17
----------------------------------------------------
+ Added PadsPartGenerator and QuartusPinImport plugins.
30/1/2014 2.4.0
----------------------------------------------------
+ Improved Editor for port maps.
- Improved visualization of port maps.
- Added bit-by-bit port map creation.
+ Added Bus interface generation wizard.
- New Bus and Abstraction definition generation based on ports in a
component.
- Bus interface and port map generation to component using the
generatarted or existing Bus and Abstraction definitions.
+ Added help page for keyboard and mouse shortcuts.
- Fixed numerous non-critical bugs and usability issues.
* Migrated to Qt 5.2.0.
* Separated plugin system from Kactus2 core.
20/09/2013 2.3.0
----------------------------------------------------
+ Added copy-paste to all designs allowing copying of component instances,
interfaces and whole columns excluding connections.
+ Added multi-selection capability for copy-paste and deletion to all designs.
+ Added VLNV drag & drop support to summary tables in the component editor.
+ Added the possibility to rearrange the default positions of component's
interfaces in the general page of the component editor.
+ Added a tooltip to show memory map size in AUB for each address block and
segment in the memory map and address space editors.
+ Added a check box to enable/disable local memory map.
+ Added Browse button to New dialog pages in order to have more convenient
directory selection if the automatically suggested location does not
suffice.
+ Added 'Select All' to the right-click context menu in design editors.
+ Added library filter selections to be saved as a part of the workspace.
- Fixed numerous bugs, both critical and non-critical ones.
- Fixed a bug causing the port maps dialog to open when using the off-page
connection tool.
- Fixed API/COM interface deletion to also delete the underlying interface
metadata from the SW component.
- Fixed an issue of ad-hoc ports not disappearing when a bus interface
containing the corresponding ports is deleted.
- Removed the 'Parameterizable' firmness attribute option.
* Migrated to Qt 5.1.1.
* Improved routing of connections in all designs with automatic overlap
avoidance.
* Improved memory map visualization with the following changes:
- Memory block widths are now scaled acccording to the window size.
- Changes to colors, fonts and alignment to improve readability.
- Visualization of overlapping addresses and violations.
* Improved address spaces visualization.
* SW designs are now shown in the library and they can be mapped to
the CPU's SW view by dragging from the library.
* Bus interface port maps editor now shows also the port directions.
* Component editor now highlights the used sections in the tree view.
* Name conflicts are now checked in all tables in the component editor.
This concerns also copy-paste to the tables.
* Changed the sorting in port and generic editors to case-insensitive.
* Renamed 'Add Signals to Bus' to 'New Abstraction Definition' to prevent
confusion with the Add signals option in the bus editor.
* Changed the order of HW views in the component editor to list hierarchical
views before non-hierarchical ones. Hierarchical views now also show an
icon.
05/07/2013 2.2.0
----------------------------------------------------
+ NEW: Component creation wizard, including a VHDL import tool.
+ NEW: Dependency analysis tool with enhanced file set editing features.
+ NEW: Generator plugins.
* Memory map header generator.
* Altera BSP generator.
+ NEW: Source analyzer plugins for dependency analysis.
* VHDL source analyzer.
* C/C++ source analyzer.
+ Added printing of library summary report to the output window after the
library scan.
+ Added COM interface implementation reference to be able to specify an
implementing driver for each COM interface in the components.
+ Added editing features for HW view reference and file set references
to the system view editor in the component editor.
+ Added file set references, build commands, BSP build tools and environment
variables to software views in the component editor.
+ Added half-automatic port creation for draft interfaces.
+ Added copy-paste for bus interfaces in the HW design editor.
+ Added UUIDs to be used to identify component instances in the designs
(especially in system designs).
+ Added the ability to launch shell scripts for components.
- Fixed performance issues with large libraries causing unnecessary slowdowns
in the library window and the component editor.
- Removed the possibility to create new components/objects from scratch in the
library window.
- Bus editor now shows width field as empty instead of an invalid -1 when the
optional width value is not specified in the abstraction definition.
- Unnecessary errors about URL file paths are no longer shown.
- Fixed the missing yellow color in the mandatory file type field in the file
set editor.
- Fixed the bus interface editor showing master interface settings by default
even though the interface mode is undefined.
- Fixed the issue of an ad-hoc port not being hidden in a design after the
ad-hoc visibility has been unchecked in the component editor and saved.
- Fixed a crash when trying to auto-assign addresses in the address editor
when the selected component instance has no bus interfaces that would
be shown in the editor.
* Migrated to Qt 5.1.0.
* Changed the naming of library context menu New items.
* Replaced the old list editor with a better collection editor.
* Disabled the instantiation of template components to designs.
* Updated context-sensitive help content.
* Fixed the issue of the component editor tree view not being updated
when making changes through the actual editor pages.
* Added more detailed information to be generated at the beginning of the
generated files.
* Generated VHDL is now formatted to max 80 character lines.
* Enhanced editing of ports in the component editor.
12/02/2013 2.1 (Build 194)
----------------------------------------------------
+ Menu ribbon remade completely with better scaling behaviour. This also
fixes the blackout bug present in the previous version.
+ Added the possibility to select which library locations are currently active.
- Fixed missing prints from the library integrity check.
- Fixed the problem of context help not working due to a missing Qt DLL.
- Removed any dependencies to GCF framework.
* Migrated to Qt 5.0.1.
06/02/2013 2.1
----------------------------------------------------
+ Designs can be opened through component editor by double clicking a
hierarchical view.
+ Linux desktop integration added.
+ Added info column to memory maps editor displaying which bus interfaces the
memory map in binded to.
+ Support for local memory map within address spaces added.
+ Added visualization of memory maps to component editor.
+ Added visualization of adress space to component editor.
+ Added XML header editor to component editor for user to create custom headers
to XML IP-XACT files.
- Fixed compilation flags on Kactus2.pro project file to support 64-bit Linux.
- Fixed bug when drag & dropping abstraction definition to bus interface within
component editor.
- Fixed bug when exporting SW in system design.
- Fixed bugs in CSV import and export.
- Fixed VLNV editor content assist bugs.
* Migrated to Qt 5.0.
* Changed colors of API and COM connections within system designs.
10/09/2012 2.0
----------------------------------------------------
+ Added address editor for setting memory addresses in HW designs.
+ Added context-sensitive help system (help pages are still work-in-progress).
+ Added support for memory maps and registers to the component editor.
+ Added Show Errors feature to the library in order to enumerate errors of a
specific library item in a dialog.
+ Added naming policies to the settings dialog.
- Fixed the crash after library refresh.
* The hierarchical library view now shows also the designs.
* Changed icons in the library view.
* Kactus2 settings are now saved to an INI file in the user's AppData folder.
* VLNV tree does not sort library items according to the item type anymore.
13/07/2012 2.0 RC
----------------------------------------------------
+ NEW: Fully revised system design architecture.
+ NEW: Experimental C++ plugin API for creating component generators.
+ Added design editing feature that allows component replacement using
drag'n'drop both from the library and within a design.
+ Added rubberband connections to new system designs.
+ Added auto-suggestion of possible generic names.
+ Added refresh button to the ribbon.
+ Added two new document types (extensions): COM definition and API definition.
+ Added CSV import for generics.
+ Added contact information to Kactus2-generated XML files.
- Removed internal IP-XACT objects that are no longer needed with the new
system designs.
* Connection bullets now indicate also the direction of the connection.
* Broken/invalid connections and missing interfaces are now visualized in
red in designs.
* Component instances referencing IP-XACT components that are not found in the
library are now kept in the design and visualized in red.
* Drafted designs can now be saved without packetizing the draft components.
* Added more information to tool tip texts shown in the library and design
editors.
KNOWN UNRESOLVED ISSUES:
* Kactus2 may crash when the library is refreshed after Plain IP-XACT library
view has been used.
28/03/2012 1.3 (Build 27)
----------------------------------------------------
+ Added shortcuts: Ctrl+Tab for switching tabs, Ctrl+W for closing tabs,
F5 for refreshing the documents and Ctrl+Space for switching protection mode.
- Fixed a critical crash in system designs and components having CPU elements.
22/03/2012 1.3 (Build 1)
----------------------------------------------------
+ NEW CORE FEATURE: Added support for ad-hoc connections and setting ad-hoc
visibility for each port separately.
+ Added better validity checking for IP-Xact objects.
+ Added usage instructions to lists that are editable by double clicking.
+ Added address space editor and CPU editing features to the component editor.
- Fixed an incorrect connection of Qt signals in HW designs.
- Fixed a scroll bar issue in New dialog when using larger fonts in Windows.
- Fixed the scaling issue of the component editor's left pane.
- Fixed a crash when saving a design with a packetized draft component.
- Fixed a regression bug of workspaces working incorrectly with Qt 4.8.0.
- Removed the unnecessary dependencies to Qt ActiveX modules.
* Migrated to Qt 4.8.0.
* The library locations are now scanned automatically on program start or
when the library locations are changed.
* Enhanced the error messages coming from the Quartus generator.
* Enhanced the error messages when saving an incomplete component.
* Error messages from the library check are now indented.
* Library check now prints more detailed error summary.
* Also the MCAPI channel connection function calls are now automatically
generated to sender side application code.
* A flat view is now automatically added to drafted components when they
are packetized.
* Changed the component instance numbering to start from zero instead of one.
* Abstraction definition is not compulsory anymore in the component editor,
but is auto-filled when using bus and abstraction definitions created with
Kactus2.
03/02/2012 1.2 (Build 396)
----------------------------------------------------
+ Added more detailed error reporting to the library's check integrity tool.
+ Added workspaces for managing different window layouts easily.
+ Added bus width display for connections (can be shown/hidden using
visibility control).
+ Added automatic association of bus definitions and abstraction definitions
when drag'n'dropping bus definitions from the library to a HW design.
+ Added dot graphics for visualizing connected bus intersections.
+ Added undercrossing graphics for visualizing bus intersections which are
separate (i.e., not connected with each other).
- Fixed a crash when trying to remove files that were already moved on the
disk.
* Kactus2 now saves the paths to library locations, not the direct paths
to the XML files.
* Changed the plain IP-XACT view so that it is not reset when items
are added or removed. Also the VLNV dialer now keeps it's contents
regardless of the tree updates.
* New component properties are automatically named to 'unnamed' instead of
having no name set.
19/01/2012 1.2 (Build 1)
----------------------------------------------------
+ Added possibility to select the name of the generated ModelSim file with
an extension.
+ Added more thorough error printing for invalid/incomplete IP-XACT documents.
+ Added off-page connectors with rubber-band routing mode for often used
interfaces/ports to achieve more readable designs by auto-hiding the rubber-
band connections when they are not edited.
+ Added the ability to execute ModelSim generator through the component editor.
+ Added the possibility to select which C source file to open through the
system design editor when right-clicking an application component.
+ Added the SW component type visualization in the component editor.
+ Kactus2 now remembers the filter settings that were set on a previous run
of the program.
- Fixed the modelsim generator to use the correct syntax for vmake call.
- Fixed the inability to scroll the port map list when a bus interface is
selected.
- Fixed the problem of opening the component editor by a double-click when a
view is not selected.
- Fixed the out-of-sync problem of editing the same component simultaneously
in the component editor and design editor.
- Fixed the crash when editing endpoints in the SW design editor.
- Fixed the regular expression problem in the MCAPI code assist.
- Fixed various small bugs in the system design editor.
* Made the protection feature more user-friendly by not always asking
the confirmation whether the user wants to unlock the document.
* Simplified some list input boxes by removing explicit add/remove buttons.
* Reorganized the file information view in the component editor.
* Decreased the VLNV fields area on the docking windows.
* Moved the XML file writing order so that the general description is written
at the beginning part of the file.
* Double-clicking an SW platform component in the platform stack editor now
opens up the hierarchy if it exists and the component editor only if it
does not exists (meaning a flat component).
* Removed the always repeating question of whether the user wants to add
the generated VHDL-file to IP-XACT meta-data if it already exists there.
* Docking windows are now kept visible based on the user's selection of
what windows to show/hide.
25/11/2011 1.1 (Build 1)
----------------------------------------------------
+ Added undo/redo support for system designs.
+ Added SW design editor for editing SW that will be mapped directly to HW
components.
+ Added a connection editor for HW designs.
+ Added VHDL template generation for drafted HW components.
+ Added comment generation to the vHDL generator.
+ Added user modifiable code areas to generated VHDL.
+ Added an option to create a new HW design based on an old one.
+ Added component port default value support to the vHDL generator.
+ Added component port type column to the component editor.
+ Default programs set in the operating system are now used to open
the files in the component editor.
+ Added entity name setting support for the VHDL generator.
+ Added automatic creation of views for HW components (RTL view for IP and SoC
level components, "hierarchical" view for Chip, Board and Product level
designs and a fla t view for same lvel components).
+ Added IP-XACT object path to be visible in the component editor's general
view.
+ Added more information about ports and model parameters to the generated
documentation.
+ Added the possibility to select which windows are shown and which are hidden.
+ Added a component interface editor for HW designs.
- Added missing internal bus definitions for MCAPI and SW to the program's
own internal library.
- Fixed the VLNV editor crash after a library refresh.
- IP-XACT namespace fields are now correctly writted to the generated XML files.
- All created VLNVs are now checked for existence when creating a new object
through the New dialog to prevent overwrite errors.
- Fixed content assist visibility problem on Linux.
- Fixed the filtering of API/bus definitions according to SW/HW.
- Fixed the crash when scrolling a locked empty design.
- Fixed the error of changes being applied without saving when editing
hierarchical interfaces of a design.
- Inout ports are now directly mapped to component instance ports as opposed
to using signals which did not work as expected.
* General page is now shown by default in the component editor.
* Designs can now be browsed and component details previewed even if
the document is locked.
* Appropriate editor windows on the right side are now automatically
shown/hidden when an element is selected or deselected on a design.
* Configuration editor is now hidden for other editors than the HW design
editor.
* Unnecessary ribbon groups are now hidden automatically based on the open
editor.
* Changed the report generator to categorize ports under bus interfaces
instead of one long list.
04/10/2011 1.0 (Build 1)
----------------------------------------------------
* Public release
* System designs and MCAPI editing are not fully featured in this release.
Upcoming system design features include undo/redo support, enhanced code
generation & validation and Makefile generation.
Download Latest Version
kactus2-3.13.5.tar.gz (18.2 MB)
