This is a formal equivalence checking tool developed @ IIT Guwahati which can be used to verify functional equivalence between circuits (combinational and sequential) of the formats BLIF, verilog and EDIF.

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Categories

Build Tools, Electronic Design Automation (EDA), Exam

License

GNU General Public License version 2.0 (GPLv2)

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Additional Project Details

Programming Language

C

Related Categories

C Build Tools, C Electronic Design Automation (EDA) Software, C Exam Software

Registered

2008-11-18
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