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From: <joe...@us...> - 2002-11-28 00:40:53
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_le
In directory sc8-pr-cvs1:/tmp/cvs-serv11618/include/asm-xtensa/xtensa/config-linux_le
Modified Files:
core.h
Log Message:
Add unaligned exception handling. None of this code is on by default, and we'll leave it off until we sync up with hardware that supports this exception. See the XTFIXME comment in the core.h files to enable this code.
Index: core.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_le/core.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** core.h 23 Oct 2002 20:53:21 -0000 1.1
--- core.h 28 Nov 2002 00:40:50 -0000 1.2
***************
*** 64,67 ****
--- 64,81 ----
/*----------------------------------------------------------------------
+ ADDRESS ALIGNMENT
+ ----------------------------------------------------------------------*/
+
+ /* XTFIXME: I disabled XCHAL_UNALIGNED_LOAD_EXCEPTION by adding an
+ _XTFIXME suffix until I update all linux_be/linux_le configs to have
+ unaligned exceptions. Do enable in software, simply remove the
+ suffix. */
+
+ /* These apply to a selected set of core load and store instructions only (see ISA): */
+ #define XCHAL_UNALIGNED_LOAD_EXCEPTION_XTFIXME 1 /* 1 if unaligned loads cause an exception, 0 otherwise */
+ #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* 1 if unaligned stores cause an exception, 0 otherwise */
+
+
+ /*----------------------------------------------------------------------
INTERRUPTS
----------------------------------------------------------------------*/
***************
*** 413,416 ****
--- 427,431 ----
#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation (Speculation) */
#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction (Privileged) */
+ #define XCHAL_EXCCAUSE_LOAD_STORE_ALIGNMENT 9 /* Load or Store to Unaligned Address (LoadStoreAlignment) */
#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception (ITlbMiss) */
#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception (ITlbMultihit) */
***************
*** 797,800 ****
--- 812,818 ----
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* number of write buffer entries */
+
+ #define XCHAL_CORE_ID "linux_le" /* configuration's alphanumeric core identifier
+ (CoreID) set in the Xtensa Processor Generator */
#define XCHAL_BUILD_UNIQUE_ID 0x00002AD6 /* software build-unique ID (22-bit) */
|
|
From: <joe...@us...> - 2002-11-28 00:40:53
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_be
In directory sc8-pr-cvs1:/tmp/cvs-serv11618/include/asm-xtensa/xtensa/config-linux_be
Modified Files:
core.h
Log Message:
Add unaligned exception handling. None of this code is on by default, and we'll leave it off until we sync up with hardware that supports this exception. See the XTFIXME comment in the core.h files to enable this code.
Index: core.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_be/core.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** core.h 23 Oct 2002 20:53:21 -0000 1.1
--- core.h 28 Nov 2002 00:40:49 -0000 1.2
***************
*** 66,69 ****
--- 66,83 ----
/*----------------------------------------------------------------------
+ ADDRESS ALIGNMENT
+ ----------------------------------------------------------------------*/
+
+ /* XTFIXME: I disabled XCHAL_UNALIGNED_LOAD_EXCEPTION by adding an
+ _XTFIXME suffix until I update all linux_be/linux_le configs to have
+ unaligned exceptions. Do enable in software, simply remove the
+ suffix. */
+
+ /* These apply to a selected set of core load and store instructions only (see ISA): */
+ #define XCHAL_UNALIGNED_LOAD_EXCEPTION_XTFIXME 1 /* 1 if unaligned loads cause an exception, 0 otherwise */
+ #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* 1 if unaligned stores cause an exception, 0 otherwise */
+
+
+ /*----------------------------------------------------------------------
INTERRUPTS
----------------------------------------------------------------------*/
***************
*** 415,418 ****
--- 429,433 ----
#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation (Speculation) */
#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction (Privileged) */
+ #define XCHAL_EXCCAUSE_LOAD_STORE_ALIGNMENT 9 /* Load or Store to Unaligned Address (LoadStoreAlignment) */
#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception (ITlbMiss) */
#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception (ITlbMultihit) */
***************
*** 799,802 ****
--- 814,820 ----
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* number of write buffer entries */
+
+ #define XCHAL_CORE_ID "linux_be" /* configuration's alphanumeric core identifier
+ (CoreID) set in the Xtensa Processor Generator */
#define XCHAL_BUILD_UNIQUE_ID 0x00002AD3 /* software build-unique ID (22-bit) */
|
|
From: <joe...@us...> - 2002-11-27 21:42:14
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory sc8-pr-cvs1:/tmp/cvs-serv4000/arch/xtensa/kernel Modified Files: vectors.S Log Message: Documentation clarifications only. Index: vectors.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/vectors.S,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** vectors.S 11 Nov 2002 22:25:25 -0000 1.2 --- vectors.S 27 Nov 2002 21:42:11 -0000 1.3 *************** *** 139,142 **** --- 139,145 ---- * suitable for immediate transfer of control to * handle_double, where "normal" exception processing occurs. + * Also in kernel mode, TLB misses can occur if accessing + * vmalloc memory, possibly requiring repair in a double + * exception handler. * * The variable at TABLE_FIXUP offset from the pointer in *************** *** 167,176 **** /* The double exception did occur within a window exception ! * handler. The registered handler expects the following: * * a0 is undefined * DEPC contains original a0 * DEPC saved in [ EXCSAVE_1 + TABLE_SAVEA0 ] ! * All other register contain their original values. */ --- 170,197 ---- /* The double exception did occur within a window exception ! * handler. All entry conditions below say "All other ! * registers contain their original values." These values ! * usually are not user values, but kernel values, since ! * the double exception will return to the kernel handler, ! * not the user code. ! * ! * find_handler has some entry conditions, but these are met ! * by the Double Exception Vector code, not the routines that ! * register find_handler with TABLE_FIXUP. They are: ! * ! * a0 is undefined ! * a1 = &exception_handlers[0] ! * EXCSAVE_1 contains original a1 ! * a2 is undefined ! * [ EXCSAVE_1 + TABLE_SAVEA2 ] contains original a2 ! * All other registers contain their original values. ! * ! * We setup the following conditions for the registered ! * handler: * * a0 is undefined * DEPC contains original a0 * DEPC saved in [ EXCSAVE_1 + TABLE_SAVEA0 ] ! * All other registers contain their original values. */ |
|
From: <jgr...@us...> - 2002-11-21 20:57:57
|
Update of /cvsroot/xtensa/linux/arch/xtensa In directory sc8-pr-cvs1:/tmp/cvs-serv27008/arch/xtensa Modified Files: Makefile Log Message: Correct path for defconfig file. Index: Makefile =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/Makefile,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** Makefile 1 Nov 2002 21:47:17 -0000 1.5 --- Makefile 21 Nov 2002 20:57:54 -0000 1.6 *************** *** 128,132 **** CLEAN_FILES += arch/xtensa/vmlinux.lds ! MRPROPER_FILES += defconfig \ include/asm-xtensa/platform \ include/asm-xtensa/xtensa/config --- 128,133 ---- CLEAN_FILES += arch/xtensa/vmlinux.lds ! MRPROPER_FILES += \ ! arch/xtensa/defconfig \ include/asm-xtensa/platform \ include/asm-xtensa/xtensa/config |
|
From: <joe...@us...> - 2002-11-21 17:18:55
|
Update of /cvsroot/xtensa/linux/arch/xtensa/lib/hal In directory sc8-pr-cvs1:/tmp/cvs-serv26438/arch/xtensa/lib/hal Modified Files: memcopy.S Log Message: Thanks to Marc Gauthier for these changes: 1. Bug fix to non-LOOP version of memcpy(). 2. Removes all unaligned accesses (needed for upcoming unaligned exceptions). 3. Optimized for common case (dst and src are aligned). Index: memcopy.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/hal/memcopy.S,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** memcopy.S 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- memcopy.S 21 Nov 2002 17:18:52 -0000 1.2 *************** *** 12,15 **** --- 12,32 ---- */ + #include <xtensa/coreasm.h> + + .macro src_b r, w0, w1 + #ifdef __XTENSA_EB__ + src \r, \w0, \w1 + #else + src \r, \w1, \w0 + #endif + .endm + + .macro ssa8 r + #ifdef __XTENSA_EB__ + ssa8b \r + #else + ssa8l \r + #endif + .endm /* *************** *** 25,46 **** * types of devices). * ! * !!!!!!! FIXME: ! * !!!!!!! Handling of IRAM/IROM/DRAM/DROM has not yet ! * !!!!!!! been implemented, and should be added here. * * The bcopy version is provided here to avoid the overhead * of an extra call, for callers that require this convention. * ! * The general case algorithm is as follows: ! * If the destination and source are both aligned, ! * do 16B chunks with a loop, and then finish up with ! * 8B, 4B, 2B, and 1B copies conditional on the length. ! * If destination is aligned and source unaligned, ! * do the same, but use SRC to align the source data. * If destination is unaligned, align it by conditionally ! * copying 1B and 2B and then retest. ! * This code tries to use fall-through braches for the common ! * case of aligned destinations (except for the branches to ! * the alignment label). * * Register use: --- 42,63 ---- * types of devices). * ! * !!!!!!! XTFIXME: ! * !!!!!!! Handling of IRAM/IROM has not yet ! * !!!!!!! been implemented. * * The bcopy version is provided here to avoid the overhead * of an extra call, for callers that require this convention. * ! * The (general case) algorithm is as follows: * If destination is unaligned, align it by conditionally ! * copying 1 and 2 bytes. ! * If source is aligned, ! * do 16 bytes with a loop, and then finish up with ! * 8, 4, 2, and 1 byte copies conditional on the length; ! * else (if source is unaligned), ! * do the same, but use SRC to align the source data. ! * This code tries to use fall-through branches for the common ! * case of aligned source and destination and multiple ! * of 4 (or 8) length. * * Register use: *************** *** 55,70 **** * a8/ tmp * a9/ tmp */ - #include <xtensa/coreasm.h> - - #ifdef __XTENSA_EB__ - #define ALIGN(R, W0, W1) src R, W0, W1 - #define SSA8(R) ssa8b R - #else - #define ALIGN(R, W0, W1) src R, W1, W0 - #define SSA8(R) ssa8l R - #endif - .text .align 4 --- 72,79 ---- * a8/ tmp * a9/ tmp + * a10/ tmp + * a11/ tmp */ .text .align 4 *************** *** 80,129 **** - .align 4 - .global xthal_memcpy - .type xthal_memcpy,@function - xthal_memcpy: - entry sp, 16 # minimal stack frame - # a2/ dst, a3/ src, a4/ len - mov a5, a2 # copy dst so that a2 is return value - .Lcommon: - bbsi.l a2, 0, .Ldst1mod2 # if dst is 1 mod 2 - bbsi.l a2, 1, .Ldst2mod4 # if dst is 2 mod 4 - .Ldstaligned: # return here from .Ldstunaligned when dst is aligned - srli a7, a4, 4 # number of loop iterations with 16B - # per iteration - movi a8, 3 # if source is also aligned, - bnone a3, a8, .Laligned # then use word copy - SSA8( a3) # set shift amount from byte offset - bnez a4, .Lsrcunaligned - retw - - /* - * Destination is unaligned - */ - - .Ldst1mod2: # dst is only byte aligned - bltui a4, 7, .Lbytecopy # do short copies byte by byte - - # copy 1 byte - l8ui a6, a3, 0 - addi a3, a3, 1 - s8i a6, a5, 0 - addi a5, a5, 1 - addi a4, a4, -1 - bbci.l a5, 1, .Ldstaligned # if dst is now aligned, then - # return to main algorithm - .Ldst2mod4: # dst 16-bit aligned - # copy 2 bytes - bltui a4, 6, .Lbytecopy # do short copies byte by byte - l8ui a6, a3, 0 - l8ui a7, a3, 1 - addi a3, a3, 2 - s8i a6, a5, 0 - s8i a7, a5, 1 - addi a5, a5, 2 - addi a4, a4, -2 - j .Ldstaligned # dst is now aligned, return to main algorithm - /* * Byte by byte copy --- 89,92 ---- *************** *** 151,160 **** /* ! * Destination and source are word-aligned. */ # copy 16 bytes per iteration for word-aligned dst and word-aligned src - .align 4 # 1 mod 4 alignment for LOOPNEZ - .byte 0 # (0 mod 4 alignment for LBEG) - .Laligned: #if XCHAL_HAVE_LOOPS loopnez a7, .Loop1done --- 114,164 ---- /* ! * Destination is unaligned */ + + .align 4 + .Ldst1mod2: # dst is only byte aligned + _bltui a4, 7, .Lbytecopy # do short copies byte by byte + + # copy 1 byte + l8ui a6, a3, 0 + addi a3, a3, 1 + addi a4, a4, -1 + s8i a6, a5, 0 + addi a5, a5, 1 + _bbci.l a5, 1, .Ldstaligned # if dst is now aligned, then + # return to main algorithm + .Ldst2mod4: # dst 16-bit aligned + # copy 2 bytes + _bltui a4, 6, .Lbytecopy # do short copies byte by byte + l8ui a6, a3, 0 + l8ui a7, a3, 1 + addi a3, a3, 2 + addi a4, a4, -2 + s8i a6, a5, 0 + s8i a7, a5, 1 + addi a5, a5, 2 + j .Ldstaligned # dst is now aligned, return to main algorithm + + + .align 4 + .global xthal_memcpy + .type xthal_memcpy,@function + xthal_memcpy: + entry sp, 16 # minimal stack frame + # a2/ dst, a3/ src, a4/ len + mov a5, a2 # copy dst so that a2 is return value + .Lcommon: + _bbsi.l a2, 0, .Ldst1mod2 # if dst is 1 mod 2 + _bbsi.l a2, 1, .Ldst2mod4 # if dst is 2 mod 4 + .Ldstaligned: # return here from .Ldst?mod? once dst is aligned + srli a7, a4, 4 # number of loop iterations with 16B + # per iteration + movi a8, 3 # if source is not aligned, + _bany a3, a8, .Lsrcunaligned # then use shifting copy + /* + * Destination and source are word-aligned, use word copy. + */ # copy 16 bytes per iteration for word-aligned dst and word-aligned src #if XCHAL_HAVE_LOOPS loopnez a7, .Loop1done *************** *** 188,192 **** addi a5, a5, 8 .L2: ! bbci.l a4, 2, .L3 # copy 4 bytes l32i a6, a3, 0 --- 192,200 ---- addi a5, a5, 8 .L2: ! bbsi.l a4, 2, .L3 ! bbsi.l a4, 1, .L4 ! bbsi.l a4, 0, .L5 ! retw ! .L3: # copy 4 bytes l32i a6, a3, 0 *************** *** 194,199 **** s32i a6, a5, 0 addi a5, a5, 4 ! .L3: ! bbci.l a4, 1, .L4 # copy 2 bytes l16ui a6, a3, 0 --- 202,209 ---- s32i a6, a5, 0 addi a5, a5, 4 ! bbsi.l a4, 1, .L4 ! bbsi.l a4, 0, .L5 ! retw ! .L4: # copy 2 bytes l16ui a6, a3, 0 *************** *** 201,211 **** s16i a6, a5, 0 addi a5, a5, 2 ! .L4: ! bbci.l a4, 0, .L5 # copy 1 byte l8ui a6, a3, 0 s8i a6, a5, 0 - .L5: - .Lret1: retw --- 211,220 ---- s16i a6, a5, 0 addi a5, a5, 2 ! bbsi.l a4, 0, .L5 ! retw ! .L5: # copy 1 byte l8ui a6, a3, 0 s8i a6, a5, 0 retw *************** *** 215,224 **** .align 4 - .byte 0 # 1 mod 4 alignement for LOOPNEZ - # (0 mod 4 alignment for LBEG) .Lsrcunaligned: # copy 16 bytes per iteration for word-aligned dst and unaligned src ! and a10, a3, a8 # save unalignment offset for below ! sub a3, a3, a10 # align a3 (to avoid sim warnings only; not needed for hardware) l32i a6, a3, 0 # load first word #if XCHAL_HAVE_LOOPS --- 224,237 ---- .align 4 .Lsrcunaligned: + _beqz a4, .Ldone # avoid loading anything for zero-length copies # copy 16 bytes per iteration for word-aligned dst and unaligned src ! ssa8 a3 # set shift amount from byte offset ! #define SIM_CHECKS_ALIGNMENT 1 /* set to 1 when running on ISS (simulator) with the ! lint or ferret client, or 0 to save a few cycles */ ! #if XCHAL_UNALIGNED_LOAD_EXCEPTION || SIM_CHECKS_ALIGNMENT ! and a11, a3, a8 # save unalignment offset for below ! sub a3, a3, a11 # align a3 ! #endif l32i a6, a3, 0 # load first word #if XCHAL_HAVE_LOOPS *************** *** 232,245 **** l32i a7, a3, 4 l32i a8, a3, 8 ! ALIGN( a6, a6, a7) s32i a6, a5, 0 l32i a9, a3, 12 ! ALIGN( a7, a7, a8) s32i a7, a5, 4 l32i a6, a3, 16 ! ALIGN( a8, a8, a9) s32i a8, a5, 8 addi a3, a3, 16 ! ALIGN( a9, a9, a6) s32i a9, a5, 12 addi a5, a5, 16 --- 245,258 ---- l32i a7, a3, 4 l32i a8, a3, 8 ! src_b a6, a6, a7 s32i a6, a5, 0 l32i a9, a3, 12 ! src_b a7, a7, a8 s32i a7, a5, 4 l32i a6, a3, 16 ! src_b a8, a8, a9 s32i a8, a5, 8 addi a3, a3, 16 ! src_b a9, a9, a6 s32i a9, a5, 12 addi a5, a5, 16 *************** *** 252,259 **** l32i a7, a3, 4 l32i a8, a3, 8 ! ALIGN( a6, a6, a7) s32i a6, a5, 0 addi a3, a3, 8 ! ALIGN( a7, a7, a8) s32i a7, a5, 4 addi a5, a5, 8 --- 265,272 ---- l32i a7, a3, 4 l32i a8, a3, 8 ! src_b a6, a6, a7 s32i a6, a5, 0 addi a3, a3, 8 ! src_b a7, a7, a8 s32i a7, a5, 4 addi a5, a5, 8 *************** *** 264,274 **** l32i a7, a3, 4 addi a3, a3, 4 ! ALIGN( a6, a6, a7) s32i a6, a5, 0 addi a5, a5, 4 mov a6, a7 .L13: ! add a3, a3, a10 # readjust a3 with correct misalignment ! bbci.l a4, 1, .L14 # copy 2 bytes l8ui a6, a3, 0 --- 277,292 ---- l32i a7, a3, 4 addi a3, a3, 4 ! src_b a6, a6, a7 s32i a6, a5, 0 addi a5, a5, 4 mov a6, a7 .L13: ! #if XCHAL_UNALIGNED_LOAD_EXCEPTION || SIM_CHECKS_ALIGNMENT ! add a3, a3, a11 # readjust a3 with correct misalignment ! #endif ! bbsi.l a4, 1, .L14 ! bbsi.l a4, 0, .L15 ! .Ldone: retw ! .L14: # copy 2 bytes l8ui a6, a3, 0 *************** *** 278,287 **** s8i a7, a5, 1 addi a5, a5, 2 ! .L14: ! bbci.l a4, 0, .L15 # copy 1 byte l8ui a6, a3, 0 s8i a6, a5, 0 - .L15: retw --- 296,305 ---- s8i a7, a5, 1 addi a5, a5, 2 ! bbsi.l a4, 0, .L15 ! retw ! .L15: # copy 1 byte l8ui a6, a3, 0 s8i a6, a5, 0 retw |
|
From: <joe...@us...> - 2002-11-11 22:25:29
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory usw-pr-cvs1:/tmp/cvs-serv18841/kernel Modified Files: handlers.S traps.c vectors.S Log Message: We need to backout some exception-handling cleverness that packs state information into unused least-significant bits of a table pointer. We still use EXCSAVE_1 as the table pointer, but when we introduce unaligned exceptions (soon), that table pointer must always be on a 32-bit boundary. Index: handlers.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/handlers.S,v retrieving revision 1.6 retrieving revision 1.7 diff -C2 -d -r1.6 -r1.7 *** handlers.S 8 Nov 2002 21:39:28 -0000 1.6 --- handlers.S 11 Nov 2002 22:25:25 -0000 1.7 *************** *** 87,144 **** - /* - EXCSAVE_1 Usage Conventions - - The new XSR instruction, introduced at the same time as the PS.EXCM - bit and other MMU related additions and changes, adds more flexibility - to how EXCSAVE_1 can be used. - - This section describes the conventions adopted for using EXCSAVE_1 in - this kernel implementation. - - EXCSAVE_1 is divided into 2 fields: - - bits 31-2 a 4-byte aligned pointer - bits 1-0 recovery/handling mode - - The contents of the pointer depends on the mode bits as follows: - - bit 1 bit 0 pointer - ----- ----- ------- - 0 0 invalid EXCSAVE_1 value, jump to local critical handling - 0 1 pointer to L32E/S32E recovery routine - 1 0 pointer to RAM vector table - 1 1 pointer to ROM vector table - - Normally, EXCSAVE_1 is set to point to a vector table (e.g., the - first-level dispatch table). The handling code for RAM vector tables - is more efficient (the vector table includes a temporary save area - that can be accessed immediately, rather than having to resolve the - type of exception first) and allows saving the full EPC_1 to provide - more detail on where a window handler got an exception (useful for - debugging), and thus is preferred. However, ROM startup or memory - diagnostic functions may need or want the vector to be placed in ROM, - and have fewer requirements for efficiency etc, so the ROM vector - table option is provided. - - When exception handling code (other than window handlers) executes - L32E and/or S32E instructions, it must be ready to handle exceptions - occurring during these instructions. What must be done when such a - (double) exception occurs is specific to the code executing L32E/S32E. - The recovery code to execute is specified via EXCSAVE_1, by setting a1 - as follows then exchanging it (via xsr) with EXCSAVE_1 just prior to - executing L32E/S32E, then exchanging it again immediately after. a1 - should thus contain the usual EXCSAVE_1 value during execution of - L32E/S32E. The recovery value of EXCSAVE_1 (set first in a1) is: bit - 1 set, bit 0 clear, and pointer set to the recovery routine. When the - double exception vector sees this EXCSAVE_1 mode setting, it simply - jumps to the recovery routine. See the double exception vector - implementation for more details on register conventions. Note that a1 - was chosen because its 2 lsbits are usually 0, so if an exception - occurs when a1 was temporarily saved in EXCSAVE_1, chances are that - will be detected as a critical condition and be handled as such. - */ - - /******************************************************************* * EXCEPTION STACK FRAME FORMAT --- 87,90 ---- Index: traps.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/traps.c,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** traps.c 10 Oct 2002 17:01:17 -0000 1.3 --- traps.c 11 Nov 2002 22:25:25 -0000 1.4 *************** *** 425,429 **** * Initialize EXCSAVE_1: */ ! i = (unsigned long)exception_handlers + 2; __asm__ __volatile__( "wsr %0, "XTSTR(EXCSAVE_1)"\n" : --- 425,429 ---- * Initialize EXCSAVE_1: */ ! i = (unsigned long)exception_handlers; __asm__ __volatile__( "wsr %0, "XTSTR(EXCSAVE_1)"\n" : Index: vectors.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/vectors.S,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** vectors.S 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- vectors.S 11 Nov 2002 22:25:25 -0000 1.2 *************** *** 75,131 **** /* - EXCSAVE_1 Usage Conventions - - The new XSR instruction, introduced at the same time as the PS.EXCM - bit and other MMU related additions and changes, adds more flexibility - to how EXCSAVE_1 can be used. - - This section describes the conventions adopted for using EXCSAVE_1 in - this kernel implementation. - - EXCSAVE_1 is divided into 2 fields: - - bits 31-2 a 4-byte aligned pointer - bits 1-0 recovery/handling mode - - The contents of the pointer depends on the mode bits as follows: - - bit 1 bit 0 pointer - ----- ----- ------- - 0 0 invalid EXCSAVE_1 value, jump to local critical handling - 0 1 pointer to L32E/S32E recovery routine - 1 0 pointer to RAM vector table - 1 1 pointer to ROM vector table - - Normally, EXCSAVE_1 is set to point to a vector table (e.g., the - first-level dispatch table). The handling code for RAM vector tables - is more efficient (the vector table includes a temporary save area - that can be accessed immediately, rather than having to resolve the - type of exception first) and allows saving the full EPC_1 to provide - more detail on where a window handler got an exception (useful for - debugging), and thus is preferred. However, ROM startup or memory - diagnostic functions may need or want the vector to be placed in ROM, - and have fewer requirements for efficiency etc, so the ROM vector - table option is provided. - - When exception handling code (other than window handlers) executes - L32E and/or S32E instructions, it must be ready to handle exceptions - occurring during these instructions. What must be done when such a - (double) exception occurs is specific to the code executing L32E/S32E. - The recovery code to execute is specified via EXCSAVE_1, by setting a1 - as follows then exchanging it (via xsr) with EXCSAVE_1 just prior to - executing L32E/S32E, then exchanging it again immediately after. a1 - should thus contain the usual EXCSAVE_1 value during execution of - L32E/S32E. The recovery value of EXCSAVE_1 (set first in a1) is: bit - 1 set, bit 0 clear, and pointer set to the recovery routine. When the - double exception vector sees this EXCSAVE_1 mode setting, it simply - jumps to the recovery routine. See the double exception vector - implementation for more details on register conventions. Note that a1 - was chosen because its 2 lsbits are usually 0, so if an exception - occurs when a1 was temporarily saved in EXCSAVE_1, chances are that - will be detected as a critical condition and be handled as such. - */ - - /* _DoubleExceptionVector --- 75,78 ---- *************** *** 157,162 **** _DoubleExceptionVector: - /* See comments above for conventions on the use of EXCSAVE_1. */ - /* Various TABLE_FIXUP functions depend on specific actions in * the DoubleExceptionVector. If you change this code, you also --- 104,107 ---- *************** *** 164,225 **** */ ! /* XTFIXME: Support for unaligned exceptions is coming. We ! need to remove the functionality of using the lower two bits ! of the EXCSAVE_1 pointer as bit flags. */ ! ! xsr a1, EXCSAVE_1 // get EXCSAVE_1, save a1 ! xsr a0, DEPC // get return PC, save a0 ! _bbci.l a1, 1, recover_or_crit // jump to L32E/S32E recovery code or critical handling ! _bbsi.l a1, 0, slowdeh // EXCSAVE_1 points to ROM, not RAM, use slower handler ! // that doesn't requires as many temp registers ! ! /* ! * Okay, now the slightly tricky part. ! * We want to resolve whether the double exception occurred ! * within a window exception handler. But *without* corrupting ! * any registers, or having to store registers to memory (which ! * would require the vector table to be in RAM so we could have ! * a save area next to it; and which isn't very safe in a double ! * exception handler in any case). ! * ! * Offset Size Vector Addr bits 8:6 ! * 0x000 64 Overflow4 000 ! * 0x040 64 Underflow4 001 ! * 0x080 64 Overflow8 010 ! * 0x0C0 64 Underflow8 011 ! * 0x100 64 Overflow12 100 ! * 0x140 64 Underflow12 101 ! * ! * So we use the following techniques: ! * - we assume the double exception occurred during ! * processing of a window exception if EPC_1 points ! * within one of the window vectors (see offsets above; ! * base of window vectors is configuration specific) ! * - double exceptions NOT occurring as part of ! * processing a window exception are not a normal ! * or expected occurrence, and are generally an ! * indication of faulty OS code, or of an unrecoverable ! * situation; EPC_1 and EXCCAUSE of the context in ! * which the double exception occurred are likely ! * irrecoverably lost (and it isn't easy to find ! * out whether they were saved, etc); ! * SO, such double exceptions are considered ! * critical exceptions, where some state has ! * already been corrupted, so corrupting a bit ! * more state is probably okay (ie. the handling ! * of a critical exception will typically do something ! * drastic like reset the system after perhaps ! * recording the event, in minimal steps, because ! * the system is considered unstable at that point) ! * - we resolve the type of window exception from ! * EPC_1 lower bits (which we can do without needing ! * temporary registers, thanks to XSR), assuming ! * the previous context was a window exception, ! * and process it enough to get a temporary ! * register, which we then use to verify whether ! * it really was a window exception; if not, and ! * we clobbered a register, that's pretty much ! * okay since what we have is a critical exception. ! */ /* The vector table must be preceded by a save area (which --- 109,114 ---- */ ! xsr a1, EXCSAVE_1 // save a1, get dispatch table ! xsr a0, DEPC // save a0, get return PC /* The vector table must be preceded by a save area (which *************** *** 229,249 **** s32i a2, a1, TABLE_SAVEA2 // save a2 ! movi a2, XCHAL_WINDOW_VECTORS_VADDR // start of window exception vectors s32i a0, a1, TABLE_SAVEA0 // save DEPC ! /* Determine whether the double exception occurred within a ! * window exception handler. */ ! _bltu a0, a2, 1f // if PC precedes window vectors, jump to next test ! addi a2, a2, XSHAL_WINDOW_VECTORS_SIZE // end of window exception vectors area ! _bltu a0, a2, find_handler // if PC follows window vectors, fall thru to next test ! /* Occasionally, the kernel expects double exception to occur. ! * This usually happens when accessing user-space memory with ! * the user's permissions (l32e/s32e instructions). The ! * kernel state, though, is not always suitable for immediate ! * transfer of control to handle_double, where "normal" ! * exception processing occurs. * * The variable at TABLE_FIXUP offset from the pointer in --- 118,142 ---- s32i a2, a1, TABLE_SAVEA2 // save a2 ! movi a2, XCHAL_WINDOW_VECTORS_VADDR // start of window exc vectors s32i a0, a1, TABLE_SAVEA0 // save DEPC ! /* If the PC falls within the window-exception vectors area, ! * the exception occured within a window exception handler. ! * In this case, we jump to find_handler to handle the ! * exception. Otherwise, the PC falls outside this area ! * (before or after), and we fall through to test for the ! * TABLE_FIXUP case. */ ! _bltu a0, a2, 1f ! addi a2, a2, XSHAL_WINDOW_VECTORS_SIZE ! _bltu a0, a2, find_handler ! /* Occasionally, the kernel expects a double exception to ! * occur. This usually happens when accessing user-space ! * memory with the user's permissions (l32e/s32e ! * instructions). The kernel state, though, is not always ! * suitable for immediate transfer of control to ! * handle_double, where "normal" exception processing occurs. * * The variable at TABLE_FIXUP offset from the pointer in *************** *** 266,270 **** * * See the handle_alloca_user and spill_registers routines ! * for examples. */ --- 159,163 ---- * * See the handle_alloca_user and spill_registers routines ! * for example clients of TABLE_FIXUP. */ *************** *** 274,279 **** /* The double exception did occur within a window exception ! * handler or the alloca handler. The registered handler expects ! * the following: * * a0 is undefined --- 167,171 ---- /* The double exception did occur within a window exception ! * handler. The registered handler expects the following: * * a0 is undefined *************** *** 294,298 **** ! /* XTFIXME, Temp logic until we complete the double exception vector code. */ recover_or_crit: j 2f --- 186,193 ---- ! /* XTFIXME: recover_or_crit and slowdeg are dead code now, but useful ! * as an alternate LED msg example. We still use CriticalExc as a ! * sort of panic indicator. */ ! recover_or_crit: j 2f *************** *** 373,377 **** --- 268,327 ---- /* XTFIXME: The following code is incomplete, but has many * ideas for optimizing this handler. + + XTFIXME: To-do List for double exception vector: + + 1. Provide the ability to place the vector table in ROM. Currently, + it must be located in RAM because we assume some temporary save area + immediately preceding the table itself. Here are some old comments + with some ideas: + + * Okay, now the slightly tricky part. + * We want to resolve whether the double exception occurred + * within a window exception handler. But *without* corrupting + * any registers, or having to store registers to memory (which + * would require the vector table to be in RAM so we could have + * a save area next to it; and which isn't very safe in a double + * exception handler in any case). + * + * Offset Size Vector Addr bits 8:6 + * 0x000 64 Overflow4 000 + * 0x040 64 Underflow4 001 + * 0x080 64 Overflow8 010 + * 0x0C0 64 Underflow8 011 + * 0x100 64 Overflow12 100 + * 0x140 64 Underflow12 101 + * + * So we use the following techniques: + * - we assume the double exception occurred during + * processing of a window exception if EPC_1 points + * within one of the window vectors (see offsets above; + * base of window vectors is configuration specific) + * - double exceptions NOT occurring as part of + * processing a window exception are not a normal + * or expected occurrence, and are generally an + * indication of faulty OS code, or of an unrecoverable + * situation; EPC_1 and EXCCAUSE of the context in + * which the double exception occurred are likely + * irrecoverably lost (and it isn't easy to find + * out whether they were saved, etc); + * SO, such double exceptions are considered + * critical exceptions, where some state has + * already been corrupted, so corrupting a bit + * more state is probably okay (ie. the handling + * of a critical exception will typically do something + * drastic like reset the system after perhaps + * recording the event, in minimal steps, because + * the system is considered unstable at that point) + * - we resolve the type of window exception from + * EPC_1 lower bits (which we can do without needing + * temporary registers, thanks to XSR), assuming + * the previous context was a window exception, + * and process it enough to get a temporary + * register, which we then use to verify whether + * it really was a window exception; if not, and + * we clobbered a register, that's pretty much + * okay since what we have is a critical exception. */ + /* Underflows can always be restarted; test this case: */ |
|
From: <joe...@us...> - 2002-11-09 02:23:16
|
Update of /cvsroot/xtensa/linux/arch/xtensa/configs In directory usw-pr-cvs1:/tmp/cvs-serv16918/configs Modified Files: xt2000_defconfig Log Message: This set of kernel-config defaults is more complete. Index: xt2000_defconfig =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/configs/xt2000_defconfig,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** xt2000_defconfig 23 Oct 2002 20:53:19 -0000 1.2 --- xt2000_defconfig 9 Nov 2002 02:23:11 -0000 1.3 *************** *** 15,23 **** # Loadable module support # ! # CONFIG_MODULES is not set # # Platform dependent support # # CONFIG_XTENSA_PLATFORM_ISS is not set CONFIG_XTENSA_PLATFORM_XT2000=y --- 15,28 ---- # Loadable module support # ! CONFIG_MODULES=y ! # CONFIG_MODVERSIONS is not set ! CONFIG_KMOD=y # # Platform dependent support # + CONFIG_XTENSA_CONFIG_LINUX_BE=y + # CONFIG_XTENSA_CONFIG_LINUX_LE is not set + # CONFIG_XTENSA_CONFIG_LINUX_TEST is not set # CONFIG_XTENSA_PLATFORM_ISS is not set CONFIG_XTENSA_PLATFORM_XT2000=y *************** *** 25,29 **** # CONFIG_SMP is not set # CONFIG_IEEEFPU_EMULATION is not set - CONFIG_SERIAL_CONSOLE=y # --- 30,33 ---- *************** *** 36,48 **** CONFIG_PCI=y CONFIG_NET=y ! # CONFIG_SYSCTL is not set ! # CONFIG_SYSVIPC is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set # CONFIG_HOTPLUG is not set # CONFIG_PCMCIA is not set - CONFIG_CMDLINE_BOOL=y # --- 40,55 ---- CONFIG_PCI=y CONFIG_NET=y ! CONFIG_SYSCTL=y ! CONFIG_SYSVIPC=y # CONFIG_BSD_PROCESS_ACCT is not set + CONFIG_KCORE_ELF=y # CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set + CONFIG_CMDLINE_BOOL=y + CONFIG_CMDLINE="console=ttyS0,38400 root=/dev/nfs ip=bootp" + # CONFIG_PCI_NAMES is not set # CONFIG_HOTPLUG is not set # CONFIG_PCMCIA is not set # *************** *** 61,65 **** # CONFIG_PNP is not set # CONFIG_ISAPNP is not set - # CONFIG_PNPBIOS is not set # --- 68,71 ---- *************** *** 72,76 **** # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set ! # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y --- 78,82 ---- # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set ! CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y *************** *** 93,116 **** # Networking options # ! # CONFIG_PACKET is not set ! # CONFIG_NETLINK is not set ! # CONFIG_NETFILTER is not set # CONFIG_FILTER is not set ! # CONFIG_UNIX is not set CONFIG_INET=y ! # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_PNP=y # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set # CONFIG_INET_ECN is not set # CONFIG_SYN_COOKIES is not set - # CONFIG_IPV6 is not set - # CONFIG_KHTTPD is not set - # CONFIG_ATM is not set # # ! # # CONFIG_IPX is not set # CONFIG_ATALK is not set --- 99,135 ---- # Networking options # ! CONFIG_PACKET=y ! # CONFIG_PACKET_MMAP is not set ! # CONFIG_NETLINK_DEV is not set ! CONFIG_NETFILTER=y ! # CONFIG_NETFILTER_DEBUG is not set # CONFIG_FILTER is not set ! CONFIG_UNIX=y CONFIG_INET=y ! CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_PNP=y + # CONFIG_IP_PNP_DHCP is not set + CONFIG_IP_PNP_BOOTP=y + # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set + # CONFIG_IP_MROUTE is not set + # CONFIG_ARPD is not set # CONFIG_INET_ECN is not set # CONFIG_SYN_COOKIES is not set # + # IP: Netfilter Configuration # ! # CONFIG_IP_NF_CONNTRACK is not set ! # CONFIG_IP_NF_QUEUE is not set ! # CONFIG_IP_NF_IPTABLES is not set ! # CONFIG_IP_NF_COMPAT_IPCHAINS is not set ! # CONFIG_IP_NF_COMPAT_IPFWADM is not set ! # CONFIG_IPV6 is not set ! # CONFIG_KHTTPD is not set ! # CONFIG_ATM is not set ! # CONFIG_VLAN_8021Q is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set *************** *** 121,126 **** # CONFIG_LLC is not set # CONFIG_NET_DIVERT is not set ! # CONFIG_ECONET_AUNUDP is not set ! # CONFIG_ECONET_NATIVE is not set # CONFIG_WAN_ROUTER is not set # CONFIG_NET_FASTROUTE is not set --- 140,144 ---- # CONFIG_LLC is not set # CONFIG_NET_DIVERT is not set ! # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_NET_FASTROUTE is not set *************** *** 132,136 **** # CONFIG_NET_SCHED is not set - # # ATA/IDE/MFM/RLL support --- 150,153 ---- *************** *** 156,159 **** --- 173,177 ---- # CONFIG_I2O_PCI is not set # CONFIG_I2O_BLOCK is not set + # CONFIG_I2O_LAN is not set # CONFIG_I2O_SCSI is not set # CONFIG_I2O_PROC is not set *************** *** 172,175 **** --- 190,194 ---- # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set + # CONFIG_ETHERTAP is not set # *************** *** 179,182 **** --- 198,202 ---- CONFIG_XTENSA_PLATFORM_XT2000_SONIC=y # CONFIG_SUNLANCE is not set + # CONFIG_HAPPYMEAL is not set # CONFIG_SUNBMAC is not set # CONFIG_SUNQE is not set *************** *** 187,190 **** --- 207,211 ---- # CONFIG_NET_VENDOR_SMC is not set # CONFIG_NET_VENDOR_RACAL is not set + # CONFIG_HP100 is not set # CONFIG_NET_ISA is not set # CONFIG_NET_PCI is not set *************** *** 204,208 **** # CONFIG_HIPPI is not set # CONFIG_PLIP is not set ! # CONFIG_PPP is not set # CONFIG_SLIP is not set --- 225,236 ---- # CONFIG_HIPPI is not set # CONFIG_PLIP is not set ! CONFIG_PPP=m ! CONFIG_PPP_MULTILINK=y ! # CONFIG_PPP_FILTER is not set ! CONFIG_PPP_ASYNC=m ! # CONFIG_PPP_SYNC_TTY is not set ! CONFIG_PPP_DEFLATE=m ! # CONFIG_PPP_BSDCOMP is not set ! CONFIG_PPPOE=m # CONFIG_SLIP is not set *************** *** 231,236 **** --- 259,270 ---- # + # IrDA (infrared) support + # + # CONFIG_IRDA is not set + + # # ISDN subsystem # + # CONFIG_ISDN is not set # *************** *** 255,264 **** # Character devices # ! # CONFIG_VT is not set CONFIG_SERIAL=y CONFIG_SERIAL_CONSOLE=y # CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set ! # CONFIG_UNIX98_PTYS is not set # --- 289,300 ---- # Character devices # ! CONFIG_VT=y ! # CONFIG_VT_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_CONSOLE=y # CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set ! CONFIG_UNIX98_PTYS=y ! CONFIG_UNIX98_PTY_COUNT=256 # *************** *** 289,293 **** # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set - # CONFIG_SONYPI is not set # --- 325,328 ---- *************** *** 308,314 **** # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set ! # CONFIG_AUTOFS4_FS is not set ! # CONFIG_REISERFS_FS is not set # CONFIG_REISERFS_CHECK is not set # CONFIG_ADFS_FS is not set # CONFIG_ADFS_FS_RW is not set --- 343,350 ---- # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set ! CONFIG_AUTOFS4_FS=m ! CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set + # CONFIG_REISERFS_PROC_INFO is not set # CONFIG_ADFS_FS is not set # CONFIG_ADFS_FS_RW is not set *************** *** 316,319 **** --- 352,358 ---- # CONFIG_HFS_FS is not set # CONFIG_BFS_FS is not set + CONFIG_EXT3_FS=m + CONFIG_JBD=m + # CONFIG_JBD_DEBUG is not set # CONFIG_FAT_FS is not set # CONFIG_MSDOS_FS is not set *************** *** 322,330 **** # CONFIG_EFS_FS is not set # CONFIG_JFFS_FS is not set ! # CONFIG_CRAMFS is not set ! # CONFIG_TMPFS is not set ! CONFIG_RAMFS=y # CONFIG_ISO9660_FS is not set # CONFIG_JOLIET is not set # CONFIG_MINIX_FS is not set # CONFIG_VXFS_FS is not set --- 361,371 ---- # CONFIG_EFS_FS is not set # CONFIG_JFFS_FS is not set ! # CONFIG_JFFS2_FS is not set ! CONFIG_CRAMFS=m ! CONFIG_TMPFS=y ! CONFIG_RAMFS=m # CONFIG_ISO9660_FS is not set # CONFIG_JOLIET is not set + # CONFIG_ZISOFS is not set # CONFIG_MINIX_FS is not set # CONFIG_VXFS_FS is not set *************** *** 332,344 **** # CONFIG_NTFS_RW is not set # CONFIG_HPFS_FS is not set ! # CONFIG_PROC_FS is not set # CONFIG_DEVFS_FS is not set # CONFIG_DEVFS_MOUNT is not set # CONFIG_DEVFS_DEBUG is not set ! # CONFIG_DEVPTS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_QNX4FS_RW is not set # CONFIG_ROMFS_FS is not set ! CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set # CONFIG_UDF_FS is not set --- 373,385 ---- # CONFIG_NTFS_RW is not set # CONFIG_HPFS_FS is not set ! CONFIG_PROC_FS=y # CONFIG_DEVFS_FS is not set # CONFIG_DEVFS_MOUNT is not set # CONFIG_DEVFS_DEBUG is not set ! CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set # CONFIG_QNX4FS_RW is not set # CONFIG_ROMFS_FS is not set ! CONFIG_EXT2_FS=m # CONFIG_SYSV_FS is not set # CONFIG_UDF_FS is not set *************** *** 346,351 **** # CONFIG_UFS_FS is not set # CONFIG_UFS_FS_WRITE is not set - # CONFIG_NCPFS_NLS is not set - # CONFIG_SMB_FS is not set # --- 387,390 ---- *************** *** 353,365 **** # # CONFIG_CODA_FS is not set CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set CONFIG_ROOT_NFS=y ! # CONFIG_NFSD is not set # CONFIG_NFSD_V3 is not set ! # CONFIG_SUNRPC is not set ! # CONFIG_LOCKD is not set ! # CONFIG_SMB_FS is not set # CONFIG_NCPFS_NLS is not set # --- 392,416 ---- # # CONFIG_CODA_FS is not set + # CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set CONFIG_ROOT_NFS=y ! CONFIG_NFSD=m # CONFIG_NFSD_V3 is not set ! CONFIG_SUNRPC=y ! CONFIG_LOCKD=y ! CONFIG_SMB_FS=m ! # CONFIG_SMB_NLS_DEFAULT is not set ! # CONFIG_NCP_FS is not set ! # CONFIG_NCPFS_PACKET_SIGNING is not set ! # CONFIG_NCPFS_IOCTL_LOCKING is not set ! # CONFIG_NCPFS_STRONG is not set ! # CONFIG_NCPFS_NFS_NS is not set ! # CONFIG_NCPFS_OS2_NS is not set ! # CONFIG_NCPFS_SMALLDOS is not set # CONFIG_NCPFS_NLS is not set + # CONFIG_NCPFS_EXTRAS is not set + # CONFIG_ZISOFS_FS is not set + CONFIG_ZLIB_FS_INFLATE=m # *************** *** 368,373 **** # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y ! # CONFIG_SMB_NLS is not set ! # CONFIG_NLS is not set # --- 419,465 ---- # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y ! CONFIG_SMB_NLS=y ! CONFIG_NLS=y ! ! # ! # Native Language Support ! # ! CONFIG_NLS_DEFAULT="iso8859-1" ! # CONFIG_NLS_CODEPAGE_437 is not set ! # CONFIG_NLS_CODEPAGE_737 is not set ! # CONFIG_NLS_CODEPAGE_775 is not set ! # CONFIG_NLS_CODEPAGE_850 is not set ! # CONFIG_NLS_CODEPAGE_852 is not set ! # CONFIG_NLS_CODEPAGE_855 is not set ! # CONFIG_NLS_CODEPAGE_857 is not set ! # CONFIG_NLS_CODEPAGE_860 is not set ! # CONFIG_NLS_CODEPAGE_861 is not set ! # CONFIG_NLS_CODEPAGE_862 is not set ! # CONFIG_NLS_CODEPAGE_863 is not set ! # CONFIG_NLS_CODEPAGE_864 is not set ! # CONFIG_NLS_CODEPAGE_865 is not set ! # CONFIG_NLS_CODEPAGE_866 is not set ! # CONFIG_NLS_CODEPAGE_869 is not set ! # CONFIG_NLS_CODEPAGE_936 is not set ! # CONFIG_NLS_CODEPAGE_950 is not set ! # CONFIG_NLS_CODEPAGE_932 is not set ! # CONFIG_NLS_CODEPAGE_949 is not set ! # CONFIG_NLS_CODEPAGE_874 is not set ! # CONFIG_NLS_ISO8859_8 is not set ! # CONFIG_NLS_CODEPAGE_1251 is not set ! # CONFIG_NLS_ISO8859_1 is not set ! # CONFIG_NLS_ISO8859_2 is not set ! # CONFIG_NLS_ISO8859_3 is not set ! # CONFIG_NLS_ISO8859_4 is not set ! # CONFIG_NLS_ISO8859_5 is not set ! # CONFIG_NLS_ISO8859_6 is not set ! # CONFIG_NLS_ISO8859_7 is not set ! # CONFIG_NLS_ISO8859_9 is not set ! # CONFIG_NLS_ISO8859_13 is not set ! # CONFIG_NLS_ISO8859_14 is not set ! # CONFIG_NLS_ISO8859_15 is not set ! # CONFIG_NLS_KOI8_R is not set ! # CONFIG_NLS_KOI8_U is not set ! # CONFIG_NLS_UTF8 is not set # *************** *** 375,378 **** --- 467,537 ---- # # CONFIG_SOUND is not set + + # + # USB support + # + # CONFIG_USB is not set + # CONFIG_USB_UHCI is not set + # CONFIG_USB_UHCI_ALT is not set + # CONFIG_USB_OHCI is not set + # CONFIG_USB_AUDIO is not set + # CONFIG_USB_BLUETOOTH is not set + # CONFIG_USB_STORAGE is not set + # CONFIG_USB_STORAGE_DEBUG is not set + # CONFIG_USB_STORAGE_DATAFAB is not set + # CONFIG_USB_STORAGE_FREECOM is not set + # CONFIG_USB_STORAGE_ISD200 is not set + # CONFIG_USB_STORAGE_DPCM is not set + # CONFIG_USB_STORAGE_HP8200e is not set + # CONFIG_USB_STORAGE_SDDR09 is not set + # CONFIG_USB_STORAGE_JUMPSHOT is not set + # CONFIG_USB_ACM is not set + # CONFIG_USB_PRINTER is not set + # CONFIG_USB_DC2XX is not set + # CONFIG_USB_MDC800 is not set + # CONFIG_USB_SCANNER is not set + # CONFIG_USB_MICROTEK is not set + # CONFIG_USB_HPUSBSCSI is not set + # CONFIG_USB_PEGASUS is not set + # CONFIG_USB_KAWETH is not set + # CONFIG_USB_CATC is not set + # CONFIG_USB_CDCETHER is not set + # CONFIG_USB_USBNET is not set + # CONFIG_USB_USS720 is not set + + # + # USB Serial Converter support + # + # CONFIG_USB_SERIAL is not set + # CONFIG_USB_SERIAL_GENERIC is not set + # CONFIG_USB_SERIAL_BELKIN is not set + # CONFIG_USB_SERIAL_WHITEHEAT is not set + # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set + # CONFIG_USB_SERIAL_EMPEG is not set + # CONFIG_USB_SERIAL_FTDI_SIO is not set + # CONFIG_USB_SERIAL_VISOR is not set + # CONFIG_USB_SERIAL_IR is not set + # CONFIG_USB_SERIAL_EDGEPORT is not set + # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set + # CONFIG_USB_SERIAL_KEYSPAN is not set + # CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set + # CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set + # CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set + # CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set + # CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set + # CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set + # CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set + # CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set + # CONFIG_USB_SERIAL_MCT_U232 is not set + # CONFIG_USB_SERIAL_PL2303 is not set + # CONFIG_USB_SERIAL_CYBERJACK is not set + # CONFIG_USB_SERIAL_XIRCOM is not set + # CONFIG_USB_SERIAL_OMNINET is not set + # CONFIG_USB_RIO500 is not set + + # + # Bluetooth support + # + # CONFIG_BLUEZ is not set # |
|
From: <joe...@us...> - 2002-11-08 23:17:46
|
Update of /cvsroot/xtensa/linux/arch/xtensa/lib In directory usw-pr-cvs1:/tmp/cvs-serv31798/arch/xtensa/lib Modified Files: checksum.S Log Message: csum_partial() now handles odd addresses properly, just to be safe. Index: checksum.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/checksum.S,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** checksum.S 8 Nov 2002 01:44:00 -0000 1.3 --- checksum.S 8 Nov 2002 23:17:41 -0000 1.4 *************** *** 117,125 **** beqz a3, 7b /* branch if len == 0 */ beqi a3, 1, 6b /* branch if len == 1 */ ! l16ui a6, a2, 0 /* common case, len == 2 */ ONES_ADD(a4, a6) addi a2, a2, 2 /* adjust buf */ addi a3, a3, -2 /* adjust len */ j 1b /* now buf is 4-byte aligned */ --- 117,174 ---- beqz a3, 7b /* branch if len == 0 */ beqi a3, 1, 6b /* branch if len == 1 */ ! ! extui a5, a2, 0, 1 ! bnez a5, 8f /* branch if 1-byte aligned */ ! ! l16ui a6, a2, 0 /* common case, len >= 2 */ ONES_ADD(a4, a6) addi a2, a2, 2 /* adjust buf */ addi a3, a3, -2 /* adjust len */ j 1b /* now buf is 4-byte aligned */ + + /* case: odd-byte aligned, len > 1 + * This case is dog slow, so don't give us an odd address. + * (I don't think this ever happens, but just in case.) + */ + 8: + srli a5, a3, 2 /* 4-byte chunks */ + #if XCHAL_HAVE_LOOPS + loopgtz a5, 2f + #else + beqz a5, 2f + slli a5, a5, 2 + add a5, a5, a2 /* a5 = end of last 4-byte chunk */ + .Loop3: + #endif + l8ui a6, a2, 0 /* bits 24..31 */ + l16ui a7, a2, 1 /* bits 8..23 */ + l8ui a8, a2, 3 /* bits 0.. 8 */ + #ifdef __XTENSA_EB__ + slli a6, a6, 24 + #else + slli a8, a8, 24 + #endif + slli a7, a7, 8 + or a7, a7, a6 + or a7, a7, a8 + ONES_ADD(a4, a7) + addi a2, a2, 4 + #if !XCHAL_HAVE_LOOPS + blt a2, a5, .Loop3 + #endif + 2: + _bbci.l a3, 1, 3f /* remaining 2-byte chunk, still odd addr */ + l8ui a6, a2, 0 + l8ui a7, a2, 1 + #ifdef __XTENSA_EB__ + slli a6, a6, 8 + #else + slli a7, a7, 8 + #endif + or a7, a7, a6 + ONES_ADD(a4, a7) + addi a2, a2, 2 + 3: + j 5b /* branch to handle the remaining byte */ |
|
From: <joe...@us...> - 2002-11-08 21:39:34
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory usw-pr-cvs1:/tmp/cvs-serv28520/arch/xtensa/kernel Modified Files: handlers.S Log Message: Two things: (1) bug fix: this handler now correctly registers a TABLE_FIXUP handler *before* accessing any memory in the regmove_table case, and (2) improved layout and use of the offset constants. Index: handlers.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/handlers.S,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** handlers.S 22 Oct 2002 17:59:43 -0000 1.5 --- handlers.S 8 Nov 2002 21:39:28 -0000 1.6 *************** *** 1,3 **** ! /* * arch/xtensa/kernel/handlers.S * --- 1,3 ---- ! /* * arch/xtensa/kernel/handlers.S * *************** *** 1661,1676 **** .data .align 4 - reg_space: - .space 20, 0 - .text ! /* Define some constants to make the assembly code more robust and ! * improve readability. */ ! #define RSAVE_A0 0 ! #define RSAVE_A2 4 ! #define RSAVE_A3 8 ! #define RSAVE_A4 12 ! #define RSAVE_A5 16 --- 1661,1677 ---- .data .align 4 ! /* Define some offsets for robustness and readability. */ ! #define RSAVE_A0 0 ! #define RSAVE_A2 4 ! #define RSAVE_A3 8 ! #define RSAVE_A4 12 ! #define RSAVE_A5 16 ! #define RSAVE_TOTAL 20 ! ! reg_space: ! .space RSAVE_TOTAL, 0 ! .text *************** *** 1850,1855 **** movi a5, find_handler - l32e a3, a1, -16 s32i a5, a4, TABLE_FIXUP // register a fixup routine l32e a5, a1, -12 s32e a3, a2, -16 --- 1851,1857 ---- movi a5, find_handler s32i a5, a4, TABLE_FIXUP // register a fixup routine + // before accessing memory + l32e a3, a1, -16 l32e a5, a1, -12 s32e a3, a2, -16 *************** *** 1961,1976 **** .data .align 16 - miss_reg_space: - .space 4*5, 0 - .text ! /* Define some offsets into miss_reg_space. They improve assembler ! * readability and reduce potential for coding blunders. */ ! #define MISS_SAVE_A2 0 ! #define MISS_SAVE_A3 4 ! #define MISS_SAVE_A4 8 ! #define MISS_SAVE_A5 12 ! #define MISS_SAVE_A6 16 .align 4 --- 1963,1979 ---- .data .align 16 ! /* Define some offsets for robustness and readability. */ ! #define MISS_SAVE_A2 0 ! #define MISS_SAVE_A3 4 ! #define MISS_SAVE_A4 8 ! #define MISS_SAVE_A5 12 ! #define MISS_SAVE_A6 16 ! #define MISS_SAVE_TOTAL 20 ! ! miss_reg_space: ! .space MISS_SAVE_TOTAL, 0 ! .text .align 4 *************** *** 2207,2217 **** /* Allocate some scratch area in which to save original values of ! * registers. Also define some constants to make the code more ! * readable and less prone to coding blunders. */ ! ! cp_save_area: ! .space 4*14, 0 ! ! .text #define CP_SAVE_A2 0 --- 2210,2215 ---- /* Allocate some scratch area in which to save original values of ! * registers. Also define some offsets for robustness and ! * readability. */ #define CP_SAVE_A2 0 *************** *** 2230,2233 **** --- 2228,2237 ---- #define CP_SAVE_A15 52 #define CP_SAVE_A0 56 + #define CP_SAVE_TOTAL (15*4) + + cp_save_area: + .space CP_SAVE_TOTAL, 0 + + .text |
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From: <jgr...@us...> - 2002-11-08 01:44:03
|
Update of /cvsroot/xtensa/linux/arch/xtensa/lib In directory usw-pr-cvs1:/tmp/cvs-serv25639 Modified Files: checksum.S Log Message: Fix checksum calculations for little-endian configurations. Index: checksum.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/checksum.S,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** checksum.S 14 Oct 2002 19:14:33 -0000 1.2 --- checksum.S 8 Nov 2002 01:44:00 -0000 1.3 *************** *** 105,109 **** --- 105,111 ---- _bbci.l a3, 0, 7f /* remaining 1-byte chunk */ 6: l8ui a6, a2, 0 + #ifdef __XTENSA_EB__ slli a6, a6, 8 /* load byte into bits 8..15 */ + #endif ONES_ADD(a4, a6) 7: *************** *** 277,281 **** --- 279,285 ---- SRC( l8ui a9, a2, 0 ) DST( s8i a9, a3, 0 ) + #ifdef __XTENSA_EB__ slli a9, a9, 8 /* shift byte to bits 8..15 */ + #endif ONES_ADD(a5, a9) 8: |
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From: <jgr...@us...> - 2002-11-08 01:10:21
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory usw-pr-cvs1:/tmp/cvs-serv15594 Modified Files: signal.c Log Message: Fix signal return code generation for little endian configurations. Index: signal.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/signal.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** signal.c 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- signal.c 8 Nov 2002 01:10:18 -0000 1.2 *************** *** 450,456 **** #elif defined __XTENSA_EL__ /* Little Endian version */ /* Generate instruction: MOVI a2, retcall */ ! err |= __put_user(retcall, &codemem[0]); err |= __put_user(0xa0, &codemem[1]); ! err |= __put_user(0x22, &codemem[2]); /* Generate instruction: SYSCALL */ err |= __put_user(0x00, &codemem[3]); --- 450,456 ---- #elif defined __XTENSA_EL__ /* Little Endian version */ /* Generate instruction: MOVI a2, retcall */ ! err |= __put_user(0x22, &codemem[0]); err |= __put_user(0xa0, &codemem[1]); ! err |= __put_user(retcall, &codemem[2]); /* Generate instruction: SYSCALL */ err |= __put_user(0x00, &codemem[3]); |
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From: <joe...@us...> - 2002-11-05 19:39:02
|
Update of /cvsroot/xtensa/linux/drivers/net In directory usw-pr-cvs1:/tmp/cvs-serv21381/drivers/net Modified Files: sonic.h Log Message: Little-endian Xtensa processors were reading from the wrong side of the bus. This change fixes the ethernet problems of LE Xtensas (i.e., bootp now works in the kernel). Index: sonic.h =================================================================== RCS file: /cvsroot/xtensa/linux/drivers/net/sonic.h,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** sonic.h 23 Oct 2002 20:53:20 -0000 1.2 --- sonic.h 5 Nov 2002 19:38:58 -0000 1.3 *************** *** 218,222 **** ! #if defined(CONFIG_MACSONIC) || defined(CONFIG_XTENSA_PLATFORM_XT2000) /* * Big endian like structures on 680x0 Macs --- 218,222 ---- ! #if defined(CONFIG_MACSONIC) || defined(__XTENSA_EB__) /* * Big endian like structures on 680x0 Macs |
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From: <jgr...@us...> - 2002-11-01 21:47:20
|
Update of /cvsroot/xtensa/linux/arch/xtensa In directory usw-pr-cvs1:/tmp/cvs-serv18805/arch/xtensa Modified Files: Makefile Log Message: Make header symlinks during config phase--"symlinks" target--rather than dep phase. Helps when building header files package for glibc. Add config symlink to MRPROPER_FILES. Don't need "configsymlinks" anymore, and prefer to stick to "arch" targets in this file. Index: Makefile =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/Makefile,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** Makefile 25 Oct 2002 23:37:26 -0000 1.4 --- Makefile 1 Nov 2002 21:47:17 -0000 1.5 *************** *** 129,133 **** CLEAN_FILES += arch/xtensa/vmlinux.lds MRPROPER_FILES += defconfig \ ! include/asm-xtensa/platform # XTFIXME: Xtensa frame pointers can theoretically be in any register, --- 129,134 ---- CLEAN_FILES += arch/xtensa/vmlinux.lds MRPROPER_FILES += defconfig \ ! include/asm-xtensa/platform \ ! include/asm-xtensa/xtensa/config # XTFIXME: Xtensa frame pointers can theoretically be in any register, *************** *** 152,160 **** $(MAKETOOLS) archsymlinks: $(RM) include/asm-xtensa/platform (cd include/asm-xtensa; ln -sf platform-$(PLATFORM) platform) - - configsymlinks: $(RM) include/asm-xtensa/xtensa/config (cd include/asm-xtensa/xtensa; ln -sf config-$(XTENSA_CONFIG) config) --- 153,161 ---- $(MAKETOOLS) + symlinks: archsymlinks + archsymlinks: $(RM) include/asm-xtensa/platform (cd include/asm-xtensa; ln -sf platform-$(PLATFORM) platform) $(RM) include/asm-xtensa/xtensa/config (cd include/asm-xtensa/xtensa; ln -sf config-$(XTENSA_CONFIG) config) *************** *** 167,171 **** @$(MAKETOOLS) mrproper ! archdep:archsymlinks configsymlinks # @$(MAKEBOOT) fastdep @$(MAKETOOLS) fastdep --- 168,172 ---- @$(MAKETOOLS) mrproper ! archdep:archsymlinks # @$(MAKEBOOT) fastdep @$(MAKETOOLS) fastdep |
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From: <joe...@us...> - 2002-11-01 20:08:58
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa In directory usw-pr-cvs1:/tmp/cvs-serv19135/include/asm-xtensa Modified Files: processor.h Log Message: Direct the kernel to mmap dynamic objects at a sane address (that is, 0x20000000 instead of 0x15555555). An overdue boon for debugging. Index: processor.h =================================================================== RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/processor.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** processor.h 28 Aug 2002 16:11:31 -0000 1.1.1.1 --- processor.h 1 Nov 2002 20:08:53 -0000 1.2 *************** *** 146,150 **** * space during mmap's. */ ! #define TASK_UNMAPPED_BASE (TASK_SIZE / 3) #define INIT_THREAD \ --- 146,150 ---- * space during mmap's. */ ! #define TASK_UNMAPPED_BASE (TASK_SIZE / 2) #define INIT_THREAD \ |
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From: <jgr...@us...> - 2002-10-29 01:20:36
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory usw-pr-cvs1:/tmp/cvs-serv12829/include/asm-xtensa
Modified Files:
page.h pgtable.h siginfo.h
Log Message:
Add changes for Linux 2.4.19 compatibility.
Index: page.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/page.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** page.h 28 Aug 2002 16:11:31 -0000 1.1.1.1
--- page.h 29 Oct 2002 01:20:33 -0000 1.2
***************
*** 97,100 ****
--- 97,102 ----
#define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
+ #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
+ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
#endif /* defined (__KERNEL__) */
Index: pgtable.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/pgtable.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** pgtable.h 12 Sep 2002 18:14:11 -0000 1.2
--- pgtable.h 29 Oct 2002 01:20:33 -0000 1.3
***************
*** 48,51 ****
--- 48,52 ----
#define flush_icache_range(start, end) flush_cache_all()
#define flush_icache_page(vma, page) do { } while (0)
+ #define flush_icache_user_range(vma, page, addr, len) do { } while (0)
#define invalidate_dcache_range(start, end) \
Index: siginfo.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/siginfo.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** siginfo.h 28 Aug 2002 16:11:31 -0000 1.1.1.1
--- siginfo.h 29 Oct 2002 01:20:33 -0000 1.2
***************
*** 118,121 ****
--- 118,122 ----
#define SI_ASYNCIO -4 /* sent by AIO completion */
#define SI_SIGIO -5 /* sent by queued SIGIO */
+ #define SI_TKILL -6 /* sent by tkill system call */
#define SI_FROMUSER(siptr) ((siptr)->si_code <= 0)
|
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From: <jgr...@us...> - 2002-10-29 01:20:36
|
Update of /cvsroot/xtensa/linux/drivers/net In directory usw-pr-cvs1:/tmp/cvs-serv12829/drivers/net Modified Files: xtsonic.c Log Message: Add changes for Linux 2.4.19 compatibility. Index: xtsonic.c =================================================================== RCS file: /cvsroot/xtensa/linux/drivers/net/xtsonic.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** xtsonic.c 28 Aug 2002 16:10:46 -0000 1.1.1.1 --- xtsonic.c 29 Oct 2002 01:20:32 -0000 1.2 *************** *** 22,25 **** --- 22,26 ---- #include <linux/ioport.h> #include <linux/in.h> + #include <linux/module.h> #include <linux/slab.h> #include <linux/string.h> |
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From: <jgr...@us...> - 2002-10-25 23:37:29
|
Update of /cvsroot/xtensa/linux/arch/xtensa In directory usw-pr-cvs1:/tmp/cvs-serv27535/arch/xtensa Modified Files: Makefile Log Message: Pass on "make mrproper" to tools directory. Index: Makefile =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/Makefile,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** Makefile 23 Oct 2002 20:53:18 -0000 1.3 --- Makefile 25 Oct 2002 23:37:26 -0000 1.4 *************** *** 165,169 **** archmrproper: ! @/bin/true archdep:archsymlinks configsymlinks --- 165,169 ---- archmrproper: ! @$(MAKETOOLS) mrproper archdep:archsymlinks configsymlinks |
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From: <joe...@us...> - 2002-10-25 20:52:20
|
Update of /cvsroot/xtensa/linux/Documentation
In directory usw-pr-cvs1:/tmp/cvs-serv31294/Documentation
Modified Files:
Configure.help
Log Message:
Add some 'help' text for Xtensa-specific kernel configuration options.
Index: Configure.help
===================================================================
RCS file: /cvsroot/xtensa/linux/Documentation/Configure.help,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** Configure.help 28 Aug 2002 16:09:52 -0000 1.1.1.1
--- Configure.help 25 Oct 2002 20:52:16 -0000 1.2
***************
*** 234,237 ****
--- 234,298 ----
Axis Communication site, <http://developer.axis.com/>.
+ Tensilica Xtensa processors
+ CONFIG_XTENSA
+ Xtensa processors are 32-bit RISC machines designed by Tensilica
+ primarily for embedded systems. These processors are both
+ configurable and extensible. The Linux port supports all processor
+ configurations and extensions, with reasonable minimum requirements.
+ The Xtensa Linux project has a home page at
+ <http://xtensa.sourceforge.net/>.
+
+ Xtensa processor configuration
+ CONFIG_XTENSA_CONFIG_LINUX_BE
+ The linux_be processor configuration is a base Xtensa config
+ supported in MontaVista Linux distributions. It contains no TIE,
+ no coprocessors, and the following configuration options:
+
+ Code Density Option 2 Misc Special Registers
+ NSA/NSAU Instructions 128-bit Data Bus Width
+ Processor ID 8K, 2-way I and D Caches
+ Zero-Overhead Loops 2 Inst Address Break Registers
+ Big Endian 2 Data Address Break Registers
+ 64 General-Purpose Registers JTAG Interface and Trace Port
+ 17 Interrupts MMU w/ TLBs and Autorefill
+ 3 Interrupt Levels 8 Autorefill Ways (I/D TLBs)
+ 3 Timers
+
+ The linux_le processor configuration is the same as linux_be,
+ except that it is little endian.
+
+ The linux_test processor configuration is designed for internal
+ testing only. It is probably not suitable for production systems.
+
+ Your processor configuration must match exactly to what you select
+ here. You can manually add your configuration (search the source
+ tree for "CONFIG_XTENSA_CONFIG_LINUX_BE") or use Tensilica's
+ script to install an overlay automatically for your processor
+ configuration.
+
+ Xtensa system type
+ CONFIG_XTENSA_PLATFORM_ISS
+ ISS is an acronym for Tensilica's Instruction Set Simulator. As of
+ this writing, ISS can be used to boot Linux and even run simple
+ user tasks in a ramdisk. While extremely useful for debugging
+ kernel startup, limitations exist (e.g., no stdin, no networking).
+
+ XT2000 is the name of Tensilica's feature-rich emulation platform.
+ This hardware is capable of running a full Linux distribution.
+
+ Xtensa clock calibration
+ CONFIG_XTENSA_CALIBRATE
+ On the XT2000 platform, the CPU clock rate can vary. The frequency
+ can be determined, however, by measuring against the known, fixed
+ frequency of the UART oscillator. The kernel on an XT2000 will
+ always auto-calibrate.
+
+ On the ISS platform, the CPU clock rate is fixed. There is no
+ notion of auto-calibration.
+
+ The ISS and XT2000 platforms are unaffected by this option setting.
+ This option is provided for the benefit of other platforms yet to
+ be defined.
+
Multiquad support for NUMA systems
CONFIG_MULTIQUAD
|
|
From: <joe...@us...> - 2002-10-25 20:52:20
|
Update of /cvsroot/xtensa/linux/arch/xtensa In directory usw-pr-cvs1:/tmp/cvs-serv31294/arch/xtensa Modified Files: config.in Log Message: Add some 'help' text for Xtensa-specific kernel configuration options. Index: config.in =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/config.in,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** config.in 23 Oct 2002 20:53:18 -0000 1.3 --- config.in 25 Oct 2002 20:52:17 -0000 1.4 *************** *** 9,13 **** define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n ! mainmenu_name "Linux/Xtensa Kernel Configuration" mainmenu_option next_comment --- 9,13 ---- define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n ! mainmenu_name "Xtensa Linux Kernel Configuration" mainmenu_option next_comment *************** *** 35,39 **** "ISS CONFIG_XTENSA_PLATFORM_ISS \ XT2000 CONFIG_XTENSA_PLATFORM_XT2000" ISS - bool 'Auto calibration of the CPU clock rate' CONFIG_XTENSA_CALIBRATE --- 35,38 ---- |
|
From: <jgr...@us...> - 2002-10-25 19:33:17
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory usw-pr-cvs1:/tmp/cvs-serv32454/include/asm-xtensa
Modified Files:
atomic.h
Log Message:
Clean up includes that cause problems with user applications.
Index: atomic.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/atomic.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** atomic.h 28 Aug 2002 16:11:31 -0000 1.1.1.1
--- atomic.h 25 Oct 2002 19:33:13 -0000 1.2
***************
*** 34,42 ****
#include <linux/config.h>
- #include <asm/xtutil.h>
typedef struct { volatile int counter; } atomic_t;
#ifdef __KERNEL__
#define ATOMIC_INIT(i) ( (atomic_t) { (i) } )
--- 34,43 ----
#include <linux/config.h>
typedef struct { volatile int counter; } atomic_t;
#ifdef __KERNEL__
+ #include <asm/xtutil.h>
+ #include <asm/system.h>
#define ATOMIC_INIT(i) ( (atomic_t) { (i) } )
***************
*** 45,50 ****
#define atomic_set(v,i) ((v)->counter = (i))
- #include <asm/system.h>
- #include <xtensa/config/specreg.h>
/*
--- 46,49 ----
***************
*** 53,59 ****
* branch back to restart the operation.
*/
-
- #define _XTSTR(x) # x
- #define XTSTR(x) _XTSTR(x)
extern __inline__ void atomic_add(int i, atomic_t * v)
--- 52,55 ----
|
|
From: <joe...@us...> - 2002-10-23 20:55:15
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config In directory usw-pr-cvs1:/tmp/cvs-serv32053/config Removed Files: core.h defs.h specreg.h system.h Log Message: Removing unneeded config files (really, they are moved to the config-linux_be directory). --- core.h DELETED --- --- defs.h DELETED --- --- specreg.h DELETED --- --- system.h DELETED --- |
|
From: <joe...@us...> - 2002-10-23 20:53:52
|
Update of /cvsroot/xtensa/linux/arch/xtensa/configs In directory usw-pr-cvs1:/tmp/cvs-serv28395/arch/xtensa/configs Modified Files: iss_defconfig xt2000_defconfig Log Message: Add processor config information for two additional configs: linux_le and linux_test. Also make the selection of processor configuration selectable at kernel-configuration time. linux_be is the default. Index: iss_defconfig =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/configs/iss_defconfig,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** iss_defconfig 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- iss_defconfig 23 Oct 2002 20:53:18 -0000 1.2 *************** *** 20,25 **** # Platform dependent support # ! CONFIG_XTENSA_ISS=y ! # CONFIG_XTENSA_XT2000 is not set # CONFIG_SMP is not set # CONFIG_IEEEFPU_EMULATION is not set --- 20,25 ---- # Platform dependent support # ! CONFIG_XTENSA_PLATFORM_ISS=y ! # CONFIG_XTENSA_PLATFORM_XT2000 is not set # CONFIG_SMP is not set # CONFIG_IEEEFPU_EMULATION is not set Index: xt2000_defconfig =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/configs/xt2000_defconfig,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** xt2000_defconfig 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- xt2000_defconfig 23 Oct 2002 20:53:19 -0000 1.2 *************** *** 20,25 **** # Platform dependent support # ! # CONFIG_XTENSA_ISS is not set ! CONFIG_XTENSA_XT2000=y CONFIG_XTENSA_CALIBRATE=y # CONFIG_SMP is not set --- 20,25 ---- # Platform dependent support # ! # CONFIG_XTENSA_PLATFORM_ISS is not set ! CONFIG_XTENSA_PLATFORM_XT2000=y CONFIG_XTENSA_CALIBRATE=y # CONFIG_SMP is not set *************** *** 177,181 **** # CONFIG_NET_ETHERNET=y ! CONFIG_XTENSA_XT2000_SONIC=y # CONFIG_SUNLANCE is not set # CONFIG_SUNBMAC is not set --- 177,181 ---- # CONFIG_NET_ETHERNET=y ! CONFIG_XTENSA_PLATFORM_XT2000_SONIC=y # CONFIG_SUNLANCE is not set # CONFIG_SUNBMAC is not set |
|
From: <joe...@us...> - 2002-10-23 20:53:51
|
Update of /cvsroot/xtensa/linux/arch/xtensa/boot In directory usw-pr-cvs1:/tmp/cvs-serv28395/arch/xtensa/boot Modified Files: Makefile Log Message: Add processor config information for two additional configs: linux_le and linux_test. Also make the selection of processor configuration selectable at kernel-configuration time. linux_be is the default. Index: Makefile =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/boot/Makefile,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** Makefile 28 Aug 2002 16:10:13 -0000 1.1.1.1 --- Makefile 23 Oct 2002 20:53:18 -0000 1.2 *************** *** 25,30 **** # Subdirs for the boot loader(s) ! subdir-$(CONFIG_XTENSA_ISS) += boot-elf ! subdir-$(CONFIG_XTENSA_XT2000) += boot-redboot boot-elf lib/zlib.a: --- 25,30 ---- # Subdirs for the boot loader(s) ! subdir-$(CONFIG_XTENSA_PLATFORM_ISS) += boot-elf ! subdir-$(CONFIG_XTENSA_PLATFORM_XT2000) += boot-redboot boot-elf lib/zlib.a: |
|
From: <joe...@us...> - 2002-10-23 20:53:51
|
Update of /cvsroot/xtensa/linux/arch/xtensa
In directory usw-pr-cvs1:/tmp/cvs-serv28395/arch/xtensa
Modified Files:
Makefile config.in
Log Message:
Add processor config information for two additional configs: linux_le and linux_test. Also make the selection of processor configuration selectable at kernel-configuration time. linux_be is the default.
Index: Makefile
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/Makefile,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** Makefile 6 Sep 2002 20:30:40 -0000 1.2
--- Makefile 23 Oct 2002 20:53:18 -0000 1.3
***************
*** 40,44 ****
LIBS += $(LIBGCC)
! ifeq ($(CONFIG_XTENSA_ISS),y)
PLATFORM = iss
#xcc libs
--- 40,44 ----
LIBS += $(LIBGCC)
! ifeq ($(CONFIG_XTENSA_PLATFORM_ISS),y)
PLATFORM = iss
#xcc libs
***************
*** 50,54 ****
endif
! ifeq ($(CONFIG_XTENSA_XT2000),y)
PLATFORM = xt2000
#xcc libs
--- 50,54 ----
endif
! ifeq ($(CONFIG_XTENSA_PLATFORM_XT2000),y)
PLATFORM = xt2000
#xcc libs
***************
*** 56,59 ****
--- 56,73 ----
endif
+ ifeq ($(CONFIG_XTENSA_CONFIG_LINUX_BE),y)
+ XTENSA_CONFIG = linux_be
+ endif
+ ifeq ($(CONFIG_XTENSA_CONFIG_LINUX_LE),y)
+ XTENSA_CONFIG = linux_le
+ endif
+ ifeq ($(CONFIG_XTENSA_CONFIG_LINUX_TEST),y)
+ XTENSA_CONFIG = linux_test
+ endif
+ ifeq "$(XTENSA_CONFIG)" ""
+ XTENSA_CONFIG = linux_be
+ endif
+
+
export CFLAGS
export AFLAGS
***************
*** 68,72 ****
# Use the compile-time HAL to identify endianess.
! CORE_H := include/asm-$(ARCH)/xtensa/config/core.h
ENDIAN_STRING := $(shell grep XCHAL_HAVE_BE $(CORE_H) | grep 1 )
ifeq "$(ENDIAN_STRING)" ""
--- 82,87 ----
# Use the compile-time HAL to identify endianess.
! PCONF := include/asm-$(ARCH)/xtensa/config-$(XTENSA_CONFIG)
! CORE_H := $(PCONF)/core.h
ENDIAN_STRING := $(shell grep XCHAL_HAVE_BE $(CORE_H) | grep 1 )
ifeq "$(ENDIAN_STRING)" ""
***************
*** 82,92 ****
# Use the compiler to identify endianess and verify XTENSA_{BIG,LITTLE}_ENDIAN
CC_ENDIAN_STRING := $(shell echo 'main(){}' | $(CC) -E -dM -xc - | grep __XTENSA_EB__)
ifeq "$(CC_ENDIAN_STRING)" ""
ifeq "$(XTENSA_LITTLE_ENDIAN)" "n"
! $(error Your $(CC) and file $(CORE_H) mismatch on endianess)
endif
endif
-
# The "tools" subdirectory needs to be built before all others.
--- 97,113 ----
# Use the compiler to identify endianess and verify XTENSA_{BIG,LITTLE}_ENDIAN
+ ifndef IGNORE_ENDIANESS
CC_ENDIAN_STRING := $(shell echo 'main(){}' | $(CC) -E -dM -xc - | grep __XTENSA_EB__)
ifeq "$(CC_ENDIAN_STRING)" ""
ifeq "$(XTENSA_LITTLE_ENDIAN)" "n"
! $(error Your compiler <$(CC)> and processor configuration <$(PCONF)> mismatch on endianess, use "make IGNORE_ENDIANESS=1" to ignore)
! endif
! endif
! ifneq "$(CC_ENDIAN_STRING)" ""
! ifeq "$(XTENSA_LITTLE_ENDIAN)" "y"
! $(error Your compiler <$(CC)> and processor configuration <$(PCONF)> mismatch on endianess, use "make IGNORE_ENDIANESS=1" to ignore)
! endif
endif
endif
# The "tools" subdirectory needs to be built before all others.
***************
*** 135,138 ****
--- 156,163 ----
(cd include/asm-xtensa; ln -sf platform-$(PLATFORM) platform)
+ configsymlinks:
+ $(RM) include/asm-xtensa/xtensa/config
+ (cd include/asm-xtensa/xtensa; ln -sf config-$(XTENSA_CONFIG) config)
+
archclean:
@$(MAKEBOOT) clean
***************
*** 142,146 ****
@/bin/true
! archdep:archsymlinks
# @$(MAKEBOOT) fastdep
@$(MAKETOOLS) fastdep
--- 167,171 ----
@/bin/true
! archdep:archsymlinks configsymlinks
# @$(MAKEBOOT) fastdep
@$(MAKETOOLS) fastdep
Index: config.in
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/config.in,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** config.in 19 Sep 2002 07:06:10 -0000 1.2
--- config.in 23 Oct 2002 20:53:18 -0000 1.3
***************
*** 27,33 ****
comment 'Platform dependent support'
! choice 'Xtensa system type' \
! "ISS CONFIG_XTENSA_ISS \
! XT2000 CONFIG_XTENSA_XT2000" ISS
bool 'Auto calibration of the CPU clock rate' CONFIG_XTENSA_CALIBRATE
--- 27,39 ----
comment 'Platform dependent support'
! choice 'Xtensa Processor Configuration' \
! "linux_be CONFIG_XTENSA_CONFIG_LINUX_BE \
! linux_le CONFIG_XTENSA_CONFIG_LINUX_LE \
! linux_test CONFIG_XTENSA_CONFIG_LINUX_TEST" linux_be
!
! choice 'Xtensa System Type' \
! "ISS CONFIG_XTENSA_PLATFORM_ISS \
! XT2000 CONFIG_XTENSA_PLATFORM_XT2000" ISS
!
bool 'Auto calibration of the CPU clock rate' CONFIG_XTENSA_CALIBRATE
***************
*** 38,42 ****
bool 'IEEE FPU emulation' CONFIG_IEEEFPU_EMULATION
! if [ "$CONFIG_XTENSA_ISS" = "y" ]; then
define_bool CONFIG_SERIAL_CONSOLE y
fi
--- 44,48 ----
bool 'IEEE FPU emulation' CONFIG_IEEEFPU_EMULATION
! if [ "$CONFIG_XTENSA_PLATFORM_ISS" = "y" ]; then
define_bool CONFIG_SERIAL_CONSOLE y
fi
***************
*** 52,56 ****
define_bool CONFIG_MCA n
! if [ "$CONFIG_XTENSA_ISS" != "y" ]; then
define_bool CONFIG_PCI y
fi
--- 58,62 ----
define_bool CONFIG_MCA n
! if [ "$CONFIG_XTENSA_PLATFORM_ISS" != "y" ]; then
define_bool CONFIG_PCI y
fi
|
|
From: <joe...@us...> - 2002-10-23 20:53:25
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test
In directory usw-pr-cvs1:/tmp/cvs-serv28395/include/asm-xtensa/xtensa/config-linux_test
Added Files:
core.h defs.h specreg.h system.h
Log Message:
Add processor config information for two additional configs: linux_le and linux_test. Also make the selection of processor configuration selectable at kernel-configuration time. linux_be is the default.
--- NEW FILE: core.h ---
/*
* xtensa/config/core.h -- HAL definitions that are dependent on CORE configuration
*
* This header file is sometimes referred to as the "compile-time HAL" or CHAL.
* It was generated for a specific Xtensa processor configuration.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* It is perfectly normal, however, for the HAL source itself to include this file.
*/
/*
* Customer ID=40; Build=11206; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
[...1320 lines suppressed...]
/*----------------------------------------------------------------------
DERIVED
----------------------------------------------------------------------*/
#if XCHAL_HAVE_BE
#define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */
#define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */
#define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */
#else
#define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */
#define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */
#define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */
#endif
/* Belongs in xtensa/hal.h: */
#define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */
#endif /*XTENSA_CONFIG_CORE_H*/
--- NEW FILE: defs.h ---
/* Definitions for Xtensa instructions, types, and protos. */
/*
* Customer ID=40; Build=11206; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_BASE_HEADER
#define _XTENSA_BASE_HEADER
#ifdef __XTENSA__
#if defined(__GNUC__) && !defined(__XCC__)
#define L8UI_ASM(arr, ars, imm) { \
__asm__ volatile("l8ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L8UI(ars, imm) \
({ \
unsigned char _arr; \
const unsigned char *_ars = ars; \
L8UI_ASM(_arr, _ars, imm); \
_arr; \
})
#define L16UI_ASM(arr, ars, imm) { \
__asm__ volatile("l16ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L16UI(ars, imm) \
({ \
unsigned short _arr; \
const unsigned short *_ars = ars; \
L16UI_ASM(_arr, _ars, imm); \
_arr; \
})
#define L16SI_ASM(arr, ars, imm) {\
__asm__ volatile("l16si %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L16SI(ars, imm) \
({ \
signed short _arr; \
const signed short *_ars = ars; \
L16SI_ASM(_arr, _ars, imm); \
_arr; \
})
#define L32I_ASM(arr, ars, imm) { \
__asm__ volatile("l32i %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L32I(ars, imm) \
({ \
unsigned _arr; \
const unsigned *_ars = ars; \
L32I_ASM(_arr, _ars, imm); \
_arr; \
})
#define S8I_ASM(arr, ars, imm) {\
__asm__ volatile("s8i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
}
#define XT_S8I(arr, ars, imm) \
({ \
signed char _arr = arr; \
const signed char *_ars = ars; \
S8I_ASM(_arr, _ars, imm); \
})
#define S16I_ASM(arr, ars, imm) {\
__asm__ volatile("s16i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
}
#define XT_S16I(arr, ars, imm) \
({ \
signed short _arr = arr; \
const signed short *_ars = ars; \
S16I_ASM(_arr, _ars, imm); \
})
#define S32I_ASM(arr, ars, imm) { \
__asm__ volatile("s32i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
}
#define XT_S32I(arr, ars, imm) \
({ \
signed int _arr = arr; \
const signed int *_ars = ars; \
S32I_ASM(_arr, _ars, imm); \
})
#define ADDI_ASM(art, ars, imm) {\
__asm__ ("addi %0, %1, %2" : "=a" (art) : "a" (ars), "i" (imm)); \
}
#define XT_ADDI(ars, imm) \
({ \
unsigned _art; \
unsigned _ars = ars; \
ADDI_ASM(_art, _ars, imm); \
_art; \
})
#define ABS_ASM(arr, art) {\
__asm__ ("abs %0, %1" : "=a" (arr) : "a" (art)); \
}
#define XT_ABS(art) \
({ \
unsigned _arr; \
signed _art = art; \
ABS_ASM(_arr, _art); \
_arr; \
})
/* Note: In the following macros that reference SAR, the magic "state"
register is used to capture the dependency on SAR. This is because
SAR is a 5-bit register and thus there are no C types that can be
used to represent it. It doesn't appear that the SAR register is
even relevant to GCC, but it is marked as "clobbered" just in
case. */
#define SRC_ASM(arr, ars, art) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("src %0, %1, %2" \
: "=a" (arr) : "a" (ars), "a" (art), "t" (_xt_sar)); \
}
#define XT_SRC(ars, art) \
({ \
unsigned _arr; \
unsigned _ars = ars; \
unsigned _art = art; \
SRC_ASM(_arr, _ars, _art); \
_arr; \
})
#define SSR_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssr %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSR(ars) \
({ \
unsigned _ars = ars; \
SSR_ASM(_ars); \
})
#define SSL_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssl %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSL(ars) \
({ \
unsigned _ars = ars; \
SSL_ASM(_ars); \
})
#define SSA8B_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssa8b %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSA8B(ars) \
({ \
unsigned _ars = ars; \
SSA8B_ASM(_ars); \
})
#define SSA8L_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssa8l %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSA8L(ars) \
({ \
unsigned _ars = ars; \
SSA8L_ASM(_ars); \
})
#define SSAI_ASM(imm) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssai %1" : "=t" (_xt_sar) : "i" (imm) : "sar"); \
}
#define XT_SSAI(imm) \
({ \
SSAI_ASM(imm); \
})
#define SEXT_ASM(arr, ars, tp7) {\
__asm__ ("sext %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (tp7)); \
}
#define XT_SEXT(ars, tp7) \
({ \
int _arr; \
SEXT_ASM(_arr, ars, tp7); \
_arr; \
})
#define CLAMPS_ASM(arr, ars, tp7) {\
__asm__ ("clamps %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (tp7)); \
}
#define XT_CLAMPS(ars, tp7) \
({ \
int _arr; \
CLAMPS_ASM(_arr, ars, tp7); \
_arr; \
})
#define MIN_ASM(arr, ars, art) {\
__asm__ ("min %0, %1, %2" : "=a" (arr) : "a" (ars) , "a" (art)); \
}
#define XT_MIN(ars, art) \
({ \
int _arr; \
int _ars = ars; \
int _art = art; \
MIN_ASM(_arr, _ars, _art); \
_arr; \
})
#define MAX_ASM(arr, ars, art) {\
__asm__ ("max %0, %1, %2" : "=a" (arr) : "a" (ars) , "a" (art)); \
}
#define XT_MAX(ars, art) \
({ \
int _arr; \
int _ars = ars; \
int _art = art; \
MAX_ASM(_arr, _ars, _art); \
_arr; \
})
#define MINU_ASM(arr, ars, art) {\
__asm__ ("minu %0, %1, %2" : "=a" (arr) : "a" (ars) , "a" (art)); \
}
#define XT_MINU(ars, art) \
({ \
unsigned _arr; \
unsigned _ars = ars; \
unsigned _art = art; \
MINU_ASM(_arr, _ars, _art); \
_arr; \
})
#define MAXU_ASM(arr, ars, art) {\
__asm__ ("maxu %0, %1, %2" : "=a" (arr) : "a" (ars) , "a" (art)); \
}
#define XT_MAXU(ars, art) \
({ \
unsigned _arr; \
unsigned _ars = ars; \
unsigned _art = art; \
MAXU_ASM(_arr, _ars, _art); \
_arr; \
})
#define NSA_ASM(arr, ars) {\
__asm__ ("nsa %0, %1" : "=a" (arr) : "a" (ars)); \
}
#define XT_NSA(ars) \
({ \
unsigned _arr; \
int _ars = ars; \
NSA_ASM(_arr, _ars); \
_arr; \
})
#define NSAU_ASM(arr, ars) {\
__asm__ ("nsau %0, %1" : "=a" (arr) : "a" (ars)); \
}
#define XT_NSAU(ars) \
({ \
unsigned _arr; \
unsigned _ars = ars; \
NSAU_ASM(_arr, _ars); \
_arr; \
})
typedef int xtbool __attribute__ ((coprocessor (0)));
typedef int xtbool2 __attribute__ ((coprocessor (1)));
typedef int xtbool4 __attribute__ ((coprocessor (2)));
typedef int xtbool8 __attribute__ ((coprocessor (3)));
typedef int xtbool16 __attribute__ ((coprocessor (4)));
#define ANDB_ASM(br, bs, bt) { \
__asm__ ("andb %0,%1,%2" : "=b" (br) : "b" (bs), "b" (bt)); \
}
#define XT_ANDB(bs, bt) ({ \
xtbool _br; \
xtbool _bs = bs; \
xtbool _bt = bt; \
ANDB_ASM(_br, _bs, _bt); \
_br; \
})
#define ANDBC_ASM(br, bs, bt) { \
__asm__ ("andbc %0,%1,%2" : "=b" (br) : "b" (bs), "b" (bt)); \
}
#define XT_ANDBC(bs, bt) ({ \
xtbool _br; \
xtbool _bs = bs; \
xtbool _bt = bt; \
ANDBC_ASM(_br, _bs, _bt); \
_br; \
})
#define ORB_ASM(br, bs, bt) { \
__asm__ ("orb %0,%1,%2" : "=b" (br) : "b" (bs), "b" (bt)); \
}
#define XT_ORB(bs, bt) ({ \
xtbool _br; \
xtbool _bs = bs; \
xtbool _bt = bt; \
ORB_ASM(_br, _bs, _bt); \
_br; \
})
#define ORBC_ASM(br, bs, bt) { \
__asm__ ("orbc %0,%1,%2" : "=b" (br) : "b" (bs), "b" (bt)); \
}
#define XT_ORBC(bs, bt) ({ \
xtbool _br; \
xtbool _bs = bs; \
xtbool _bt = bt; \
ORBC_ASM(_br, _bs, _bt); \
_br; \
})
#define XORB_ASM(br, bs, bt) { \
__asm__ ("xorb %0,%1,%2" : "=b" (br) : "b" (bs), "b" (bt)); \
}
#define XT_XORB(bs, bt) ({ \
xtbool _br; \
xtbool _bs = bs; \
xtbool _bt = bt; \
XORB_ASM(_br, _bs, _bt); \
_br; \
})
#define ANY4_ASM(bt, bs4) { \
__asm__ ("any4 %0,%1" : "=b" (bt) : "b" (bs4)); \
}
#define XT_ANY4(bs4) ({ \
xtbool _bt; \
xtbool4 _bs4 = bs4; \
ANY4_ASM(_bt, _bs4); \
_bt; \
})
#define ALL4_ASM(bt, bs4) { \
__asm__ ("all4 %0,%1" : "=b" (bt) : "b" (bs4)); \
}
#define XT_ALL4(bs4) ({ \
xtbool _bt; \
xtbool4 _bs4 = bs4; \
ALL4_ASM(_bt, _bs4); \
_bt; \
})
#define ANY8_ASM(bt, bs8) { \
__asm__ ("any8 %0,%1" : "=b" (bt) : "b" (bs8)); \
}
#define XT_ANY8(bs8) ({ \
xtbool _bt; \
xtbool8 _bs8 = bs8; \
ANY8_ASM(_bt, _bs8); \
_bt; \
})
#define ALL8_ASM(bt, bs8) { \
__asm__ ("all8 %0,%1" : "=b" (bt) : "b" (bs8)); \
}
#define XT_ALL8(bs8) ({ \
xtbool _bt; \
xtbool8 _bs8 = bs8; \
ALL8_ASM(_bt, _bs8); \
_bt; \
})
#endif /* __GNUC__ && !__XCC__ */
#ifdef __XCC__
/* Core load/store instructions */
extern unsigned char _TIE_L8UI(const unsigned char * ars, immediate imm);
extern unsigned short _TIE_L16UI(const unsigned short * ars, immediate imm);
extern signed short _TIE_L16SI(const signed short * ars, immediate imm);
extern unsigned _TIE_L32I(const unsigned * ars, immediate imm);
extern void _TIE_S8I(unsigned char arr, unsigned char * ars, immediate imm);
extern void _TIE_S16I(unsigned short arr, unsigned short * ars, immediate imm);
extern void _TIE_S32I(unsigned arr, unsigned * ars, immediate imm);
#define XT_L8UI _TIE_L8UI
#define XT_L16UI _TIE_L16UI
#define XT_L16SI _TIE_L16SI
#define XT_L32I _TIE_L32I
#define XT_S8I _TIE_S8I
#define XT_S16I _TIE_S16I
#define XT_S32I _TIE_S32I
/* Add-immediate instruction */
extern unsigned _TIE_ADDI(unsigned ars, immediate imm);
#define XT_ADDI _TIE_ADDI
/* Absolute value instruction */
extern unsigned _TIE_ABS(int art);
#define XT_ABS _TIE_ABS
/* funnel shift instructions */
extern unsigned _TIE_SRC(unsigned ars, unsigned art);
#define XT_SRC _TIE_SRC
extern void _TIE_SSR(unsigned ars);
#define XT_SSR _TIE_SSR
extern void _TIE_SSL(unsigned ars);
#define XT_SSL _TIE_SSL
extern void _TIE_SSA8B(unsigned ars);
#define XT_SSA8B _TIE_SSA8B
extern void _TIE_SSA8L(unsigned ars);
#define XT_SSA8L _TIE_SSA8L
extern void _TIE_SSAI(immediate imm);
#define XT_SSAI _TIE_SSAI
/* Miscellaneous instructions */
extern int _TIE_SEXT(unsigned ars, immediate tp7);
#define XT_SEXT _TIE_SEXT
extern int _TIE_CLAMPS(int ars, immediate tp7);
#define XT_CLAMPS _TIE_CLAMPS
extern int _TIE_MIN(int ars, int art);
extern int _TIE_MAX(int ars, int art);
extern unsigned _TIE_MINU(unsigned ars, unsigned art);
extern unsigned _TIE_MAXU(unsigned ars, unsigned art);
#define XT_MIN _TIE_MIN
#define XT_MAX _TIE_MAX
#define XT_MINU _TIE_MINU
#define XT_MAXU _TIE_MAXU
extern unsigned _TIE_NSA(int ars);
extern unsigned _TIE_NSAU(unsigned ars);
#define XT_NSA _TIE_NSA
#define XT_NSAU _TIE_NSAU
/* Boolean registers and related instructions */
typedef _TIE_xtbool xtbool;
typedef _TIE_xtbool2 xtbool2;
typedef _TIE_xtbool4 xtbool4;
typedef _TIE_xtbool8 xtbool8;
typedef _TIE_xtbool16 xtbool16;
extern xtbool _TIE_ANDB(xtbool bs, xtbool bt);
extern xtbool _TIE_ANDBC(xtbool bs, xtbool bt);
extern xtbool _TIE_ORB(xtbool bs, xtbool bt);
extern xtbool _TIE_ORBC(xtbool bs, xtbool bt);
extern xtbool _TIE_XORB(xtbool bs, xtbool bt);
extern xtbool _TIE_ANY4(xtbool4 bs4);
extern xtbool _TIE_ALL4(xtbool4 bs4);
extern xtbool _TIE_ANY8(xtbool8 bs8);
extern xtbool _TIE_ALL8(xtbool8 bs8);
#define XT_ANDB _TIE_ANDB
#define XT_ANDBC _TIE_ANDBC
#define XT_ORB _TIE_ORB
#define XT_ORBC _TIE_ORBC
#define XT_XORB _TIE_XORB
#define XT_ANY4 _TIE_ANY4
#define XT_ALL4 _TIE_ALL4
#define XT_ANY8 _TIE_ANY8
#define XT_ALL8 _TIE_ALL8
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_BASE_HEADER */
--- NEW FILE: specreg.h ---
/*
* Xtensa Special Register symbolic names
*/
/* $Id: specreg.h,v 1.1 2002/10/23 20:53:21 joetaylor Exp $ */
/*
* Customer ID=40; Build=11206; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef XTENSA_SPECREG_H
#define XTENSA_SPECREG_H
/* Include these special register bitfield definitions, for historical reasons: */
#include <xtensa/corebits.h>
/* Special registers: */
#define LBEG 0
#define LEND 1
#define LCOUNT 2
#define SAR 3
#define BR 4
#define ACCLO 16
#define ACCHI 17
#define MR_0 32
#define MR_1 33
#define MR_2 34
#define MR_3 35
#define WINDOWBASE 72
#define WINDOWSTART 73
#define PTEVADDR 83
#define RASID 90
#define ITLBCFG 91
#define DTLBCFG 92
#define IBREAKENABLE 96
#define DDR 104
#define IBREAKA_0 128
#define IBREAKA_1 129
#define DBREAKA_0 144
#define DBREAKA_1 145
#define DBREAKC_0 160
#define DBREAKC_1 161
#define EPC_1 177
#define EPC_2 178
#define EPC_3 179
#define EPC_4 180
#define EPC_5 181
#define EPC_6 182
#define EPC_7 183
#define DEPC 192
#define EPS_2 194
#define EPS_3 195
#define EPS_4 196
#define EPS_5 197
#define EPS_6 198
#define EPS_7 199
#define EXCSAVE_1 209
#define EXCSAVE_2 210
#define EXCSAVE_3 211
#define EXCSAVE_4 212
#define EXCSAVE_5 213
#define EXCSAVE_6 214
#define EXCSAVE_7 215
#define CPENABLE 224
#define INTERRUPT 226
#define INTENABLE 228
#define PS 230
#define EXCCAUSE 232
#define DEBUGCAUSE 233
#define CCOUNT 234
#define PRID 235
#define ICOUNT 236
#define ICOUNTLEVEL 237
#define EXCVADDR 238
#define CCOMPARE_0 240
#define CCOMPARE_1 241
#define CCOMPARE_2 242
#define MISC_REG_0 244
#define MISC_REG_1 245
#define MISC_REG_2 246
#define MISC_REG_3 247
/* Special cases (bases of special register series): */
#define MR 32
#define IBREAKA 128
#define DBREAKA 144
#define DBREAKC 160
#define EPC 176
#define EPS 192
#define EXCSAVE 208
#define CCOMPARE 240
/* Special names for read-only and write-only interrupt registers: */
#define INTREAD 226
#define INTSET 226
#define INTCLEAR 227
#endif /* XTENSA_SPECREG_H */
--- NEW FILE: system.h ---
/*
* xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
*
* NOTE: The location and contents of this file are highly subject to change.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* The HAL itself has historically included this file in some instances,
* but this is not appropriate either, because the HAL is meant to be
* core-specific but system independent.
*/
/*
* Customer ID=40; Build=11206; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef XTENSA_CONFIG_SYSTEM_H
#define XTENSA_CONFIG_SYSTEM_H
/*#include <xtensa/hal.h>*/
/*----------------------------------------------------------------------
DEVICE ADDRESSES
----------------------------------------------------------------------*/
/*
* Strange place to find these, but the configuration GUI
* allows moving these around to account for various core
* configurations. Specific boards (and their BSP software)
* will have specific meanings for these components.
*/
/* I/O Block areas: */
#define XSHAL_IOBLOCK_CACHED_VADDR 0xE0000000
#define XSHAL_IOBLOCK_CACHED_PADDR 0xF0000000
#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
#define XSHAL_IOBLOCK_BYPASS_VADDR 0xF0000000
#define XSHAL_IOBLOCK_BYPASS_PADDR 0xF0000000
#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
#if 0
#define XSHAL_ETHER_VADDR 0xFD030000
#define XSHAL_ETHER_PADDR 0xFD030000
#define XSHAL_UART_VADDR 0xFD050000
#define XSHAL_UART_PADDR 0xFD050000
#define XSHAL_LED_VADDR 0xFD040000
#define XSHAL_LED_PADDR 0xFD040000
#define XSHAL_FLASH_VADDR 0xF8000000
#define XSHAL_FLASH_PADDR 0xF8000000
#define XSHAL_FLASH_SIZE 0x04000000
#endif /*0*/
/* System ROM: */
#define XSHAL_ROM_VADDR 0xEE000000
#define XSHAL_ROM_PADDR 0xFE000000
#define XSHAL_ROM_SIZE 0x00400000
/* Largest available area (free of vectors): */
#define XSHAL_ROM_AVAIL_VADDR 0xEE00052C
#define XSHAL_ROM_AVAIL_VSIZE 0x003FFAD4
/* System RAM: */
#define XSHAL_RAM_VADDR 0xD0000000
#define XSHAL_RAM_PADDR 0x00000000
#define XSHAL_RAM_VSIZE 0x08000000
#define XSHAL_RAM_PSIZE 0x10000000
#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
/* Largest available area (free of vectors): */
#define XSHAL_RAM_AVAIL_VADDR 0xD0000390
#define XSHAL_RAM_AVAIL_VSIZE 0x07FFFC70
/*
* Shadow system RAM (same device as system RAM, at different address).
* (Emulation boards need this for the SONIC Ethernet driver
* when data caches are configured for writeback mode.)
* NOTE: on full MMU configs, this points to the BYPASS virtual address
* of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
* addresses are viewed through the BYPASS static map rather than
* the CACHED static map.
*/
#define XSHAL_RAM_BYPASS_VADDR 0xD8000000
#define XSHAL_RAM_BYPASS_PADDR 0x00000000
#define XSHAL_RAM_BYPASS_PSIZE 0x08000000
/* Alternate system RAM (different device than system RAM): */
#define XSHAL_ALTRAM_VADDR 0xCFA00000
#define XSHAL_ALTRAM_PADDR 0xC0000000
#define XSHAL_ALTRAM_SIZE 0x00200000
/*----------------------------------------------------------------------
* DEVICE-ADDRESS DEPENDENT...
*
* Values written to CACHEATTR special register (or its equivalent)
* to enable and disable caches in various modes.
*----------------------------------------------------------------------*/
/*----------------------------------------------------------------------
BACKWARD COMPATIBILITY ...
----------------------------------------------------------------------*/
/*
* NOTE: the following two macros are DEPRECATED. Use the latter
* board-specific macros instead, which are specially tuned for the
* particular target environments' memory maps.
*/
#define XSHAL_CACHEATTR_BYPASS 0x22FFFFF2 /* disable caches in bypass mode */
#define XSHAL_CACHEATTR_DEFAULT 0x22FFFFF1 /* default setting to enable caches (no writeback!) */
/*----------------------------------------------------------------------
ISS (Instruction Set Simulator) SPECIFIC ...
----------------------------------------------------------------------*/
#define XSHAL_ISS_CACHEATTR_WRITEBACK 0x4422222F /* enable caches in write-back mode */
#define XSHAL_ISS_CACHEATTR_WRITEALLOC 0x1122222F /* enable caches in write-allocate mode */
#define XSHAL_ISS_CACHEATTR_WRITETHRU 0x1122222F /* enable caches in write-through mode */
#define XSHAL_ISS_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_WRITEBACK /* default setting to enable caches */
#define XSHAL_ISS_PIPE_REGIONS 0
#define XSHAL_ISS_SDRAM_REGIONS 0
/*----------------------------------------------------------------------
XT2000 BOARD SPECIFIC ...
----------------------------------------------------------------------*/
#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0x22FFFFFF /* enable caches in write-back mode */
#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0x22FFFFFF /* enable caches in write-allocate mode */
#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0x22FFFFFF /* enable caches in write-through mode */
#define XSHAL_XT2000_CACHEATTR_BYPASS 0x22FFFFFF /* disable caches in bypass mode */
#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
#define XSHAL_XT2000_PIPE_REGIONS 0x00001000 /* BusInt pipeline regions */
#define XSHAL_XT2000_SDRAM_REGIONS 0x00000005 /* BusInt SDRAM regions */
/*----------------------------------------------------------------------
VECTOR SIZES
----------------------------------------------------------------------*/
/*
* Sizes allocated to vectors by the system (memory map) configuration.
* These sizes are constrained by core configuration (eg. one vector's
* code cannot overflow into another vector) but are dependent on the
* system or board (or LSP) memory map configuration.
*
* Whether or not each vector happens to be in a system ROM is also
* a system configuration matter, sometimes useful, included here also:
*/
#define XSHAL_RESET_VECTOR_SIZE 0x000004E0
#define XSHAL_RESET_VECTOR_ISROM 1
#define XSHAL_USER_VECTOR_SIZE 0x0000001C
#define XSHAL_USER_VECTOR_ISROM 0
#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNEL_VECTOR_SIZE 0x0000001C
#define XSHAL_KERNEL_VECTOR_ISROM 0
#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x000000E0
#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
#define XSHAL_WINDOW_VECTORS_SIZE 0x00000180
#define XSHAL_WINDOW_VECTORS_ISROM 0
#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL4_VECTOR_ISROM 0
#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL5_VECTOR_ISROM 0
#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL6_VECTOR_ISROM 1
#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE
#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM
#define XSHAL_NMI_VECTOR_SIZE 0x0000000C
#define XSHAL_NMI_VECTOR_ISROM 1
#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE
#endif /*XTENSA_CONFIG_SYSTEM_H*/
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