[xtensa-cvscommit] linux/include/asm-xtensa/xtensa/config-linux_test core.h,NONE,1.1 defs.h,NONE,1.1
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[xtensa-cvscommit] linux/include/asm-xtensa/xtensa/config-linux_test core.h,NONE,1.1 defs.h,NONE,1.1 specreg.h,NONE,1.1 system.h,NONE,1.1
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From: <joe...@us...> - 2002-10-23 20:53:25
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Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test
In directory usw-pr-cvs1:/tmp/cvs-serv28395/include/asm-xtensa/xtensa/config-linux_test
Added Files:
core.h defs.h specreg.h system.h
Log Message:
Add processor config information for two additional configs: linux_le and linux_test. Also make the selection of processor configuration selectable at kernel-configuration time. linux_be is the default.
--- NEW FILE: core.h ---
/*
* xtensa/config/core.h -- HAL definitions that are dependent on CORE configuration
*
* This header file is sometimes referred to as the "compile-time HAL" or CHAL.
* It was generated for a specific Xtensa processor configuration.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* It is perfectly normal, however, for the HAL source itself to include this file.
*/
/*
* Customer ID=40; Build=11206; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
[...1320 lines suppressed...]
/*----------------------------------------------------------------------
DERIVED
----------------------------------------------------------------------*/
#if XCHAL_HAVE_BE
#define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */
#define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */
#define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */
#else
#define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */
#define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */
#define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */
#endif
/* Belongs in xtensa/hal.h: */
#define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */
#endif /*XTENSA_CONFIG_CORE_H*/
--- NEW FILE: defs.h ---
/* Definitions for Xtensa instructions, types, and protos. */
/*
* Customer ID=40; Build=11206; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_BASE_HEADER
#define _XTENSA_BASE_HEADER
#ifdef __XTENSA__
#if defined(__GNUC__) && !defined(__XCC__)
#define L8UI_ASM(arr, ars, imm) { \
__asm__ volatile("l8ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L8UI(ars, imm) \
({ \
unsigned char _arr; \
const unsigned char *_ars = ars; \
L8UI_ASM(_arr, _ars, imm); \
_arr; \
})
#define L16UI_ASM(arr, ars, imm) { \
__asm__ volatile("l16ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L16UI(ars, imm) \
({ \
unsigned short _arr; \
const unsigned short *_ars = ars; \
L16UI_ASM(_arr, _ars, imm); \
_arr; \
})
#define L16SI_ASM(arr, ars, imm) {\
__asm__ volatile("l16si %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L16SI(ars, imm) \
({ \
signed short _arr; \
const signed short *_ars = ars; \
L16SI_ASM(_arr, _ars, imm); \
_arr; \
})
#define L32I_ASM(arr, ars, imm) { \
__asm__ volatile("l32i %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L32I(ars, imm) \
({ \
unsigned _arr; \
const unsigned *_ars = ars; \
L32I_ASM(_arr, _ars, imm); \
_arr; \
})
#define S8I_ASM(arr, ars, imm) {\
__asm__ volatile("s8i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
}
#define XT_S8I(arr, ars, imm) \
({ \
signed char _arr = arr; \
const signed char *_ars = ars; \
S8I_ASM(_arr, _ars, imm); \
})
#define S16I_ASM(arr, ars, imm) {\
__asm__ volatile("s16i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
}
#define XT_S16I(arr, ars, imm) \
({ \
signed short _arr = arr; \
const signed short *_ars = ars; \
S16I_ASM(_arr, _ars, imm); \
})
#define S32I_ASM(arr, ars, imm) { \
__asm__ volatile("s32i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
}
#define XT_S32I(arr, ars, imm) \
({ \
signed int _arr = arr; \
const signed int *_ars = ars; \
S32I_ASM(_arr, _ars, imm); \
})
#define ADDI_ASM(art, ars, imm) {\
__asm__ ("addi %0, %1, %2" : "=a" (art) : "a" (ars), "i" (imm)); \
}
#define XT_ADDI(ars, imm) \
({ \
unsigned _art; \
unsigned _ars = ars; \
ADDI_ASM(_art, _ars, imm); \
_art; \
})
#define ABS_ASM(arr, art) {\
__asm__ ("abs %0, %1" : "=a" (arr) : "a" (art)); \
}
#define XT_ABS(art) \
({ \
unsigned _arr; \
signed _art = art; \
ABS_ASM(_arr, _art); \
_arr; \
})
/* Note: In the following macros that reference SAR, the magic "state"
register is used to capture the dependency on SAR. This is because
SAR is a 5-bit register and thus there are no C types that can be
used to represent it. It doesn't appear that the SAR register is
even relevant to GCC, but it is marked as "clobbered" just in
case. */
#define SRC_ASM(arr, ars, art) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("src %0, %1, %2" \
: "=a" (arr) : "a" (ars), "a" (art), "t" (_xt_sar)); \
}
#define XT_SRC(ars, art) \
({ \
unsigned _arr; \
unsigned _ars = ars; \
unsigned _art = art; \
SRC_ASM(_arr, _ars, _art); \
_arr; \
})
#define SSR_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssr %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSR(ars) \
({ \
unsigned _ars = ars; \
SSR_ASM(_ars); \
})
#define SSL_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssl %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSL(ars) \
({ \
unsigned _ars = ars; \
SSL_ASM(_ars); \
})
#define SSA8B_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssa8b %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSA8B(ars) \
({ \
unsigned _ars = ars; \
SSA8B_ASM(_ars); \
})
#define SSA8L_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssa8l %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSA8L(ars) \
({ \
unsigned _ars = ars; \
SSA8L_ASM(_ars); \
})
#define SSAI_ASM(imm) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssai %1" : "=t" (_xt_sar) : "i" (imm) : "sar"); \
}
#define XT_SSAI(imm) \
({ \
SSAI_ASM(imm); \
})
#define SEXT_ASM(arr, ars, tp7) {\
__asm__ ("sext %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (tp7)); \
}
#define XT_SEXT(ars, tp7) \
({ \
int _arr; \
SEXT_ASM(_arr, ars, tp7); \
_arr; \
})
#define CLAMPS_ASM(arr, ars, tp7) {\
__asm__ ("clamps %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (tp7)); \
}
#define XT_CLAMPS(ars, tp7) \
({ \
int _arr; \
CLAMPS_ASM(_arr, ars, tp7); \
_arr; \
})
#define MIN_ASM(arr, ars, art) {\
__asm__ ("min %0, %1, %2" : "=a" (arr) : "a" (ars) , "a" (art)); \
}
#define XT_MIN(ars, art) \
({ \
int _arr; \
int _ars = ars; \
int _art = art; \
MIN_ASM(_arr, _ars, _art); \
_arr; \
})
#define MAX_ASM(arr, ars, art) {\
__asm__ ("max %0, %1, %2" : "=a" (arr) : "a" (ars) , "a" (art)); \
}
#define XT_MAX(ars, art) \
({ \
int _arr; \
int _ars = ars; \
int _art = art; \
MAX_ASM(_arr, _ars, _art); \
_arr; \
})
#define MINU_ASM(arr, ars, art) {\
__asm__ ("minu %0, %1, %2" : "=a" (arr) : "a" (ars) , "a" (art)); \
}
#define XT_MINU(ars, art) \
({ \
unsigned _arr; \
unsigned _ars = ars; \
unsigned _art = art; \
MINU_ASM(_arr, _ars, _art); \
_arr; \
})
#define MAXU_ASM(arr, ars, art) {\
__asm__ ("maxu %0, %1, %2" : "=a" (arr) : "a" (ars) , "a" (art)); \
}
#define XT_MAXU(ars, art) \
({ \
unsigned _arr; \
unsigned _ars = ars; \
unsigned _art = art; \
MAXU_ASM(_arr, _ars, _art); \
_arr; \
})
#define NSA_ASM(arr, ars) {\
__asm__ ("nsa %0, %1" : "=a" (arr) : "a" (ars)); \
}
#define XT_NSA(ars) \
({ \
unsigned _arr; \
int _ars = ars; \
NSA_ASM(_arr, _ars); \
_arr; \
})
#define NSAU_ASM(arr, ars) {\
__asm__ ("nsau %0, %1" : "=a" (arr) : "a" (ars)); \
}
#define XT_NSAU(ars) \
({ \
unsigned _arr; \
unsigned _ars = ars; \
NSAU_ASM(_arr, _ars); \
_arr; \
})
typedef int xtbool __attribute__ ((coprocessor (0)));
typedef int xtbool2 __attribute__ ((coprocessor (1)));
typedef int xtbool4 __attribute__ ((coprocessor (2)));
typedef int xtbool8 __attribute__ ((coprocessor (3)));
typedef int xtbool16 __attribute__ ((coprocessor (4)));
#define ANDB_ASM(br, bs, bt) { \
__asm__ ("andb %0,%1,%2" : "=b" (br) : "b" (bs), "b" (bt)); \
}
#define XT_ANDB(bs, bt) ({ \
xtbool _br; \
xtbool _bs = bs; \
xtbool _bt = bt; \
ANDB_ASM(_br, _bs, _bt); \
_br; \
})
#define ANDBC_ASM(br, bs, bt) { \
__asm__ ("andbc %0,%1,%2" : "=b" (br) : "b" (bs), "b" (bt)); \
}
#define XT_ANDBC(bs, bt) ({ \
xtbool _br; \
xtbool _bs = bs; \
xtbool _bt = bt; \
ANDBC_ASM(_br, _bs, _bt); \
_br; \
})
#define ORB_ASM(br, bs, bt) { \
__asm__ ("orb %0,%1,%2" : "=b" (br) : "b" (bs), "b" (bt)); \
}
#define XT_ORB(bs, bt) ({ \
xtbool _br; \
xtbool _bs = bs; \
xtbool _bt = bt; \
ORB_ASM(_br, _bs, _bt); \
_br; \
})
#define ORBC_ASM(br, bs, bt) { \
__asm__ ("orbc %0,%1,%2" : "=b" (br) : "b" (bs), "b" (bt)); \
}
#define XT_ORBC(bs, bt) ({ \
xtbool _br; \
xtbool _bs = bs; \
xtbool _bt = bt; \
ORBC_ASM(_br, _bs, _bt); \
_br; \
})
#define XORB_ASM(br, bs, bt) { \
__asm__ ("xorb %0,%1,%2" : "=b" (br) : "b" (bs), "b" (bt)); \
}
#define XT_XORB(bs, bt) ({ \
xtbool _br; \
xtbool _bs = bs; \
xtbool _bt = bt; \
XORB_ASM(_br, _bs, _bt); \
_br; \
})
#define ANY4_ASM(bt, bs4) { \
__asm__ ("any4 %0,%1" : "=b" (bt) : "b" (bs4)); \
}
#define XT_ANY4(bs4) ({ \
xtbool _bt; \
xtbool4 _bs4 = bs4; \
ANY4_ASM(_bt, _bs4); \
_bt; \
})
#define ALL4_ASM(bt, bs4) { \
__asm__ ("all4 %0,%1" : "=b" (bt) : "b" (bs4)); \
}
#define XT_ALL4(bs4) ({ \
xtbool _bt; \
xtbool4 _bs4 = bs4; \
ALL4_ASM(_bt, _bs4); \
_bt; \
})
#define ANY8_ASM(bt, bs8) { \
__asm__ ("any8 %0,%1" : "=b" (bt) : "b" (bs8)); \
}
#define XT_ANY8(bs8) ({ \
xtbool _bt; \
xtbool8 _bs8 = bs8; \
ANY8_ASM(_bt, _bs8); \
_bt; \
})
#define ALL8_ASM(bt, bs8) { \
__asm__ ("all8 %0,%1" : "=b" (bt) : "b" (bs8)); \
}
#define XT_ALL8(bs8) ({ \
xtbool _bt; \
xtbool8 _bs8 = bs8; \
ALL8_ASM(_bt, _bs8); \
_bt; \
})
#endif /* __GNUC__ && !__XCC__ */
#ifdef __XCC__
/* Core load/store instructions */
extern unsigned char _TIE_L8UI(const unsigned char * ars, immediate imm);
extern unsigned short _TIE_L16UI(const unsigned short * ars, immediate imm);
extern signed short _TIE_L16SI(const signed short * ars, immediate imm);
extern unsigned _TIE_L32I(const unsigned * ars, immediate imm);
extern void _TIE_S8I(unsigned char arr, unsigned char * ars, immediate imm);
extern void _TIE_S16I(unsigned short arr, unsigned short * ars, immediate imm);
extern void _TIE_S32I(unsigned arr, unsigned * ars, immediate imm);
#define XT_L8UI _TIE_L8UI
#define XT_L16UI _TIE_L16UI
#define XT_L16SI _TIE_L16SI
#define XT_L32I _TIE_L32I
#define XT_S8I _TIE_S8I
#define XT_S16I _TIE_S16I
#define XT_S32I _TIE_S32I
/* Add-immediate instruction */
extern unsigned _TIE_ADDI(unsigned ars, immediate imm);
#define XT_ADDI _TIE_ADDI
/* Absolute value instruction */
extern unsigned _TIE_ABS(int art);
#define XT_ABS _TIE_ABS
/* funnel shift instructions */
extern unsigned _TIE_SRC(unsigned ars, unsigned art);
#define XT_SRC _TIE_SRC
extern void _TIE_SSR(unsigned ars);
#define XT_SSR _TIE_SSR
extern void _TIE_SSL(unsigned ars);
#define XT_SSL _TIE_SSL
extern void _TIE_SSA8B(unsigned ars);
#define XT_SSA8B _TIE_SSA8B
extern void _TIE_SSA8L(unsigned ars);
#define XT_SSA8L _TIE_SSA8L
extern void _TIE_SSAI(immediate imm);
#define XT_SSAI _TIE_SSAI
/* Miscellaneous instructions */
extern int _TIE_SEXT(unsigned ars, immediate tp7);
#define XT_SEXT _TIE_SEXT
extern int _TIE_CLAMPS(int ars, immediate tp7);
#define XT_CLAMPS _TIE_CLAMPS
extern int _TIE_MIN(int ars, int art);
extern int _TIE_MAX(int ars, int art);
extern unsigned _TIE_MINU(unsigned ars, unsigned art);
extern unsigned _TIE_MAXU(unsigned ars, unsigned art);
#define XT_MIN _TIE_MIN
#define XT_MAX _TIE_MAX
#define XT_MINU _TIE_MINU
#define XT_MAXU _TIE_MAXU
extern unsigned _TIE_NSA(int ars);
extern unsigned _TIE_NSAU(unsigned ars);
#define XT_NSA _TIE_NSA
#define XT_NSAU _TIE_NSAU
/* Boolean registers and related instructions */
typedef _TIE_xtbool xtbool;
typedef _TIE_xtbool2 xtbool2;
typedef _TIE_xtbool4 xtbool4;
typedef _TIE_xtbool8 xtbool8;
typedef _TIE_xtbool16 xtbool16;
extern xtbool _TIE_ANDB(xtbool bs, xtbool bt);
extern xtbool _TIE_ANDBC(xtbool bs, xtbool bt);
extern xtbool _TIE_ORB(xtbool bs, xtbool bt);
extern xtbool _TIE_ORBC(xtbool bs, xtbool bt);
extern xtbool _TIE_XORB(xtbool bs, xtbool bt);
extern xtbool _TIE_ANY4(xtbool4 bs4);
extern xtbool _TIE_ALL4(xtbool4 bs4);
extern xtbool _TIE_ANY8(xtbool8 bs8);
extern xtbool _TIE_ALL8(xtbool8 bs8);
#define XT_ANDB _TIE_ANDB
#define XT_ANDBC _TIE_ANDBC
#define XT_ORB _TIE_ORB
#define XT_ORBC _TIE_ORBC
#define XT_XORB _TIE_XORB
#define XT_ANY4 _TIE_ANY4
#define XT_ALL4 _TIE_ALL4
#define XT_ANY8 _TIE_ANY8
#define XT_ALL8 _TIE_ALL8
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_BASE_HEADER */
--- NEW FILE: specreg.h ---
/*
* Xtensa Special Register symbolic names
*/
/* $Id: specreg.h,v 1.1 2002/10/23 20:53:21 joetaylor Exp $ */
/*
* Customer ID=40; Build=11206; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef XTENSA_SPECREG_H
#define XTENSA_SPECREG_H
/* Include these special register bitfield definitions, for historical reasons: */
#include <xtensa/corebits.h>
/* Special registers: */
#define LBEG 0
#define LEND 1
#define LCOUNT 2
#define SAR 3
#define BR 4
#define ACCLO 16
#define ACCHI 17
#define MR_0 32
#define MR_1 33
#define MR_2 34
#define MR_3 35
#define WINDOWBASE 72
#define WINDOWSTART 73
#define PTEVADDR 83
#define RASID 90
#define ITLBCFG 91
#define DTLBCFG 92
#define IBREAKENABLE 96
#define DDR 104
#define IBREAKA_0 128
#define IBREAKA_1 129
#define DBREAKA_0 144
#define DBREAKA_1 145
#define DBREAKC_0 160
#define DBREAKC_1 161
#define EPC_1 177
#define EPC_2 178
#define EPC_3 179
#define EPC_4 180
#define EPC_5 181
#define EPC_6 182
#define EPC_7 183
#define DEPC 192
#define EPS_2 194
#define EPS_3 195
#define EPS_4 196
#define EPS_5 197
#define EPS_6 198
#define EPS_7 199
#define EXCSAVE_1 209
#define EXCSAVE_2 210
#define EXCSAVE_3 211
#define EXCSAVE_4 212
#define EXCSAVE_5 213
#define EXCSAVE_6 214
#define EXCSAVE_7 215
#define CPENABLE 224
#define INTERRUPT 226
#define INTENABLE 228
#define PS 230
#define EXCCAUSE 232
#define DEBUGCAUSE 233
#define CCOUNT 234
#define PRID 235
#define ICOUNT 236
#define ICOUNTLEVEL 237
#define EXCVADDR 238
#define CCOMPARE_0 240
#define CCOMPARE_1 241
#define CCOMPARE_2 242
#define MISC_REG_0 244
#define MISC_REG_1 245
#define MISC_REG_2 246
#define MISC_REG_3 247
/* Special cases (bases of special register series): */
#define MR 32
#define IBREAKA 128
#define DBREAKA 144
#define DBREAKC 160
#define EPC 176
#define EPS 192
#define EXCSAVE 208
#define CCOMPARE 240
/* Special names for read-only and write-only interrupt registers: */
#define INTREAD 226
#define INTSET 226
#define INTCLEAR 227
#endif /* XTENSA_SPECREG_H */
--- NEW FILE: system.h ---
/*
* xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
*
* NOTE: The location and contents of this file are highly subject to change.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* The HAL itself has historically included this file in some instances,
* but this is not appropriate either, because the HAL is meant to be
* core-specific but system independent.
*/
/*
* Customer ID=40; Build=11206; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef XTENSA_CONFIG_SYSTEM_H
#define XTENSA_CONFIG_SYSTEM_H
/*#include <xtensa/hal.h>*/
/*----------------------------------------------------------------------
DEVICE ADDRESSES
----------------------------------------------------------------------*/
/*
* Strange place to find these, but the configuration GUI
* allows moving these around to account for various core
* configurations. Specific boards (and their BSP software)
* will have specific meanings for these components.
*/
/* I/O Block areas: */
#define XSHAL_IOBLOCK_CACHED_VADDR 0xE0000000
#define XSHAL_IOBLOCK_CACHED_PADDR 0xF0000000
#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
#define XSHAL_IOBLOCK_BYPASS_VADDR 0xF0000000
#define XSHAL_IOBLOCK_BYPASS_PADDR 0xF0000000
#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
#if 0
#define XSHAL_ETHER_VADDR 0xFD030000
#define XSHAL_ETHER_PADDR 0xFD030000
#define XSHAL_UART_VADDR 0xFD050000
#define XSHAL_UART_PADDR 0xFD050000
#define XSHAL_LED_VADDR 0xFD040000
#define XSHAL_LED_PADDR 0xFD040000
#define XSHAL_FLASH_VADDR 0xF8000000
#define XSHAL_FLASH_PADDR 0xF8000000
#define XSHAL_FLASH_SIZE 0x04000000
#endif /*0*/
/* System ROM: */
#define XSHAL_ROM_VADDR 0xEE000000
#define XSHAL_ROM_PADDR 0xFE000000
#define XSHAL_ROM_SIZE 0x00400000
/* Largest available area (free of vectors): */
#define XSHAL_ROM_AVAIL_VADDR 0xEE00052C
#define XSHAL_ROM_AVAIL_VSIZE 0x003FFAD4
/* System RAM: */
#define XSHAL_RAM_VADDR 0xD0000000
#define XSHAL_RAM_PADDR 0x00000000
#define XSHAL_RAM_VSIZE 0x08000000
#define XSHAL_RAM_PSIZE 0x10000000
#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
/* Largest available area (free of vectors): */
#define XSHAL_RAM_AVAIL_VADDR 0xD0000390
#define XSHAL_RAM_AVAIL_VSIZE 0x07FFFC70
/*
* Shadow system RAM (same device as system RAM, at different address).
* (Emulation boards need this for the SONIC Ethernet driver
* when data caches are configured for writeback mode.)
* NOTE: on full MMU configs, this points to the BYPASS virtual address
* of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
* addresses are viewed through the BYPASS static map rather than
* the CACHED static map.
*/
#define XSHAL_RAM_BYPASS_VADDR 0xD8000000
#define XSHAL_RAM_BYPASS_PADDR 0x00000000
#define XSHAL_RAM_BYPASS_PSIZE 0x08000000
/* Alternate system RAM (different device than system RAM): */
#define XSHAL_ALTRAM_VADDR 0xCFA00000
#define XSHAL_ALTRAM_PADDR 0xC0000000
#define XSHAL_ALTRAM_SIZE 0x00200000
/*----------------------------------------------------------------------
* DEVICE-ADDRESS DEPENDENT...
*
* Values written to CACHEATTR special register (or its equivalent)
* to enable and disable caches in various modes.
*----------------------------------------------------------------------*/
/*----------------------------------------------------------------------
BACKWARD COMPATIBILITY ...
----------------------------------------------------------------------*/
/*
* NOTE: the following two macros are DEPRECATED. Use the latter
* board-specific macros instead, which are specially tuned for the
* particular target environments' memory maps.
*/
#define XSHAL_CACHEATTR_BYPASS 0x22FFFFF2 /* disable caches in bypass mode */
#define XSHAL_CACHEATTR_DEFAULT 0x22FFFFF1 /* default setting to enable caches (no writeback!) */
/*----------------------------------------------------------------------
ISS (Instruction Set Simulator) SPECIFIC ...
----------------------------------------------------------------------*/
#define XSHAL_ISS_CACHEATTR_WRITEBACK 0x4422222F /* enable caches in write-back mode */
#define XSHAL_ISS_CACHEATTR_WRITEALLOC 0x1122222F /* enable caches in write-allocate mode */
#define XSHAL_ISS_CACHEATTR_WRITETHRU 0x1122222F /* enable caches in write-through mode */
#define XSHAL_ISS_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_WRITEBACK /* default setting to enable caches */
#define XSHAL_ISS_PIPE_REGIONS 0
#define XSHAL_ISS_SDRAM_REGIONS 0
/*----------------------------------------------------------------------
XT2000 BOARD SPECIFIC ...
----------------------------------------------------------------------*/
#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0x22FFFFFF /* enable caches in write-back mode */
#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0x22FFFFFF /* enable caches in write-allocate mode */
#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0x22FFFFFF /* enable caches in write-through mode */
#define XSHAL_XT2000_CACHEATTR_BYPASS 0x22FFFFFF /* disable caches in bypass mode */
#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
#define XSHAL_XT2000_PIPE_REGIONS 0x00001000 /* BusInt pipeline regions */
#define XSHAL_XT2000_SDRAM_REGIONS 0x00000005 /* BusInt SDRAM regions */
/*----------------------------------------------------------------------
VECTOR SIZES
----------------------------------------------------------------------*/
/*
* Sizes allocated to vectors by the system (memory map) configuration.
* These sizes are constrained by core configuration (eg. one vector's
* code cannot overflow into another vector) but are dependent on the
* system or board (or LSP) memory map configuration.
*
* Whether or not each vector happens to be in a system ROM is also
* a system configuration matter, sometimes useful, included here also:
*/
#define XSHAL_RESET_VECTOR_SIZE 0x000004E0
#define XSHAL_RESET_VECTOR_ISROM 1
#define XSHAL_USER_VECTOR_SIZE 0x0000001C
#define XSHAL_USER_VECTOR_ISROM 0
#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNEL_VECTOR_SIZE 0x0000001C
#define XSHAL_KERNEL_VECTOR_ISROM 0
#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x000000E0
#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
#define XSHAL_WINDOW_VECTORS_SIZE 0x00000180
#define XSHAL_WINDOW_VECTORS_ISROM 0
#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL4_VECTOR_ISROM 0
#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL5_VECTOR_ISROM 0
#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL6_VECTOR_ISROM 1
#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE
#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM
#define XSHAL_NMI_VECTOR_SIZE 0x0000000C
#define XSHAL_NMI_VECTOR_ISROM 1
#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE
#endif /*XTENSA_CONFIG_SYSTEM_H*/
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