xtensa-cvscommit Mailing List for xtensa (Page 7)
Brought to you by:
zankel
Menu
▾
▴
xtensa-cvscommit — email list for cvs commit
You can subscribe to this list here.
| 2002 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
(18) |
Oct
(30) |
Nov
(18) |
Dec
(12) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2003 |
Jan
(24) |
Feb
(38) |
Mar
(28) |
Apr
(27) |
May
(17) |
Jun
(6) |
Jul
(12) |
Aug
(2) |
Sep
|
Oct
|
Nov
|
Dec
|
| 2004 |
Jan
(1) |
Feb
|
Mar
|
Apr
|
May
(2) |
Jun
(1) |
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
|
| 2006 |
Jan
|
Feb
|
Mar
|
Apr
|
May
(1) |
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
|
|
From: <joe...@us...> - 2003-01-20 22:44:20
|
Update of /cvsroot/xtensa/linux/arch/xtensa/mm
In directory sc8-pr-cvs1:/tmp/cvs-serv15600/arch/xtensa/mm
Modified Files:
cache.c mmu.c
Log Message:
Mnemonic constants are better than hard-coded values. Change 0 to NO_CONTEXT in several places.
Index: cache.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/cache.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** cache.c 17 Jan 2003 00:31:30 -0000 1.1
--- cache.c 20 Jan 2003 22:44:16 -0000 1.2
***************
*** 50,54 ****
void flush_cache_mm(struct mm_struct *mm)
{
! if (mm && mm->context != 0) {
#ifdef DEBUG_CACHE
--- 50,54 ----
void flush_cache_mm(struct mm_struct *mm)
{
! if (mm && mm->context != NO_CONTEXT) {
#ifdef DEBUG_CACHE
***************
*** 68,72 ****
struct vm_area_struct *vma;
! if (!mm || mm->context == 0)
return;
--- 68,72 ----
struct vm_area_struct *vma;
! if (!mm || mm->context == NO_CONTEXT)
return;
***************
*** 97,101 ****
unsigned long flags;
! if (!mm || mm->context == 0)
return;
--- 97,101 ----
unsigned long flags;
! if (!mm || mm->context == NO_CONTEXT)
return;
***************
*** 125,129 ****
unsigned long start;
! if (!mm || mm->context == 0)
return;
--- 125,129 ----
unsigned long start;
! if (!mm || mm->context == NO_CONTEXT)
return;
Index: mmu.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/mmu.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** mmu.c 22 Oct 2002 17:59:46 -0000 1.3
--- mmu.c 20 Jan 2003 22:44:16 -0000 1.4
***************
*** 36,40 ****
void flush_tlb_mm (struct mm_struct *mm)
{
! if (mm->context != 0) {
unsigned long flags;
--- 36,40 ----
void flush_tlb_mm (struct mm_struct *mm)
{
! if (mm->context != NO_CONTEXT) {
unsigned long flags;
***************
*** 53,57 ****
void flush_tlb_range (struct mm_struct *mm, unsigned long start, unsigned long end)
{
! if (mm->context != 0) {
unsigned long flags;
int size;
--- 53,57 ----
void flush_tlb_range (struct mm_struct *mm, unsigned long start, unsigned long end)
{
! if (mm->context != NO_CONTEXT) {
unsigned long flags;
int size;
***************
*** 87,91 ****
void flush_tlb_page (struct vm_area_struct *vma, unsigned long page)
{
! if(vma->vm_mm->context != 0) {
unsigned long flags;
int oldpid;
--- 87,91 ----
void flush_tlb_page (struct vm_area_struct *vma, unsigned long page)
{
! if(vma->vm_mm->context != NO_CONTEXT) {
unsigned long flags;
int oldpid;
|
|
From: <joe...@us...> - 2003-01-20 22:44:19
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv15600/include/asm-xtensa
Modified Files:
mmu_context.h
Log Message:
Mnemonic constants are better than hard-coded values. Change 0 to NO_CONTEXT in several places.
Index: mmu_context.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/mmu_context.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** mmu_context.h 28 Aug 2002 16:11:31 -0000 1.1.1.1
--- mmu_context.h 20 Jan 2003 22:44:15 -0000 1.2
***************
*** 121,124 ****
--- 121,131 ----
+ /* NO_CONTEXT is the invalid ASID value that we don't ever assign to
+ any user or kernel context. NO_CONTEXT is a better mnemonic than
+ XCHAL_MMU_ASID_INVALID, so we use it in code instead. */
+
+ #define NO_CONTEXT XCHAL_MMU_ASID_INVALID
+
+
#if (KERNEL_RING != 0)
#error The KERNEL_RING really should be zero.
***************
*** 226,230 ****
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
! mm->context = 0;
return 0;
}
--- 233,237 ----
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
! mm->context = NO_CONTEXT;
return 0;
}
|
|
From: <joe...@us...> - 2003-01-17 18:17:57
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test
In directory sc8-pr-cvs1:/tmp/cvs-serv30478
Modified Files:
core.h defs.h specreg.h system.h
Log Message:
Update config-specific files to reflect new linux_test config.
Index: core.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test/core.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** core.h 28 Nov 2002 01:21:16 -0000 1.2
--- core.h 17 Jan 2003 18:17:48 -0000 1.3
***************
*** 11,15 ****
/*
! * Customer ID=40; Build=11206; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
--- 11,15 ----
/*
! * Customer ID=40; Build=25579; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
***************
*** 64,82 ****
/*----------------------------------------------------------------------
INTERRUPTS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_INTERRUPTS 1 /* 1 if interrupt option configured, 0 otherwise */
! #define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS 1 /* 1 if high-level interrupt option configured, 0 otherwise */
#define XCHAL_HAVE_NMI 1 /* 1 if NMI option configured, 0 otherwise */
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
#define XCHAL_NUM_EXTINTERRUPTS 10 /* number of external interrupts */
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels (not including level zero!) */
/* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL0_MASK 0x00000000
! #define XCHAL_INTLEVEL1_MASK 0x0C44F022
! #define XCHAL_INTLEVEL2_MASK 0x120A0050
! #define XCHAL_INTLEVEL3_MASK 0x00000204
#define XCHAL_INTLEVEL4_MASK 0x81B00408
#define XCHAL_INTLEVEL5_MASK 0x60010901
--- 64,100 ----
/*----------------------------------------------------------------------
+ ADDRESS ALIGNMENT
+ ----------------------------------------------------------------------*/
+
+ /* These apply to a selected set of core load and store instructions only (see ISA): */
+ #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* 1 if unaligned loads cause an exception, 0 otherwise */
+ #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* 1 if unaligned stores cause an exception, 0 otherwise */
+
+
+ /*----------------------------------------------------------------------
INTERRUPTS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_INTERRUPTS 1 /* 1 if interrupt option configured, 0 otherwise */
! #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* 1 if high-priority interrupt option configured, 0 otherwise */
! #define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS
#define XCHAL_HAVE_NMI 1 /* 1 if NMI option configured, 0 otherwise */
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
+ #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* number of bits to hold an interrupt number: roundup(log2(number of interrupts)) */
#define XCHAL_NUM_EXTINTERRUPTS 10 /* number of external interrupts */
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels (not including level zero!) */
+ #define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */
+ #define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */
+ #define XCHAL_EXCM_LEVEL 1 /* level of interrupts masked by PS.EXCM (XEA2 only; always 1 in T10xx);
+ for XEA1, where there is no PS.EXCM, this is always 1;
+ interrupts at levels FIRST_HIGHPRI <= n <= EXCM_LEVEL, if any,
+ are termed "medium priority" interrupts (post T10xx only) */
+ /* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */
/* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL0_MASK 0x00000000
! #define XCHAL_INTLEVEL1_MASK 0x0C04F222
! #define XCHAL_INTLEVEL2_MASK 0x124A0050
! #define XCHAL_INTLEVEL3_MASK 0x00000004
#define XCHAL_INTLEVEL4_MASK 0x81B00408
#define XCHAL_INTLEVEL5_MASK 0x60010901
***************
*** 93,99 ****
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INTLEVEL_MASKS 0x00000000 XCHAL_SEP \
! 0x0C44F022 XCHAL_SEP \
! 0x120A0050 XCHAL_SEP \
! 0x00000204 XCHAL_SEP \
0x81B00408 XCHAL_SEP \
0x60010901 XCHAL_SEP \
--- 111,117 ----
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INTLEVEL_MASKS 0x00000000 XCHAL_SEP \
! 0x0C04F222 XCHAL_SEP \
! 0x124A0050 XCHAL_SEP \
! 0x00000004 XCHAL_SEP \
0x81B00408 XCHAL_SEP \
0x60010901 XCHAL_SEP \
***************
*** 111,116 ****
/* Masks of interrupts at each range 1..n of interrupt levels: */
#define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000
! #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0C44F022
! #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x1E4EF072
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x1E4EF276
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x9FFEF67E
--- 129,134 ----
/* Masks of interrupts at each range 1..n of interrupt levels: */
#define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000
! #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0C04F222
! #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x1E4EF272
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x1E4EF276
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x9FFEF67E
***************
*** 126,133 ****
#define XCHAL_INTLEVEL14_ANDBELOW_MASK 0xFFFFFFFF
#define XCHAL_INTLEVEL15_ANDBELOW_MASK 0xFFFFFFFF
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INTLEVEL_ANDBELOW_MASKS 0x00000000 XCHAL_SEP \
! 0x0C44F022 XCHAL_SEP \
! 0x1E4EF072 XCHAL_SEP \
0x1E4EF276 XCHAL_SEP \
0x9FFEF67E XCHAL_SEP \
--- 144,153 ----
#define XCHAL_INTLEVEL14_ANDBELOW_MASK 0xFFFFFFFF
#define XCHAL_INTLEVEL15_ANDBELOW_MASK 0xFFFFFFFF
+ #define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK /* mask of all low-priority interrupts */
+ #define XCHAL_EXCM_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK /* mask of all interrupts masked by PS.EXCM (or CEXCM) */
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INTLEVEL_ANDBELOW_MASKS 0x00000000 XCHAL_SEP \
! 0x0C04F222 XCHAL_SEP \
! 0x1E4EF272 XCHAL_SEP \
0x1E4EF276 XCHAL_SEP \
0x9FFEF67E XCHAL_SEP \
***************
*** 144,147 ****
--- 164,175 ----
0xFFFFFFFF
+ /* Interrupt numbers for each interrupt level at which only one interrupt was configured: */
+ /*#define XCHAL_INTLEVEL1_NUM ...more than one interrupt at this level...*/
+ /*#define XCHAL_INTLEVEL2_NUM ...more than one interrupt at this level...*/
+ #define XCHAL_INTLEVEL3_NUM 2
+ /*#define XCHAL_INTLEVEL4_NUM ...more than one interrupt at this level...*/
+ /*#define XCHAL_INTLEVEL5_NUM ...more than one interrupt at this level...*/
+ #define XCHAL_INTLEVEL7_NUM 7
+
/* Level of each interrupt: */
#define XCHAL_INT0_LEVEL 5
***************
*** 154,158 ****
#define XCHAL_INT7_LEVEL 7
#define XCHAL_INT8_LEVEL 5
! #define XCHAL_INT9_LEVEL 3
#define XCHAL_INT10_LEVEL 4
#define XCHAL_INT11_LEVEL 5
--- 182,186 ----
#define XCHAL_INT7_LEVEL 7
#define XCHAL_INT8_LEVEL 5
! #define XCHAL_INT9_LEVEL 1
#define XCHAL_INT10_LEVEL 4
#define XCHAL_INT11_LEVEL 5
***************
*** 167,171 ****
#define XCHAL_INT20_LEVEL 4
#define XCHAL_INT21_LEVEL 4
! #define XCHAL_INT22_LEVEL 1
#define XCHAL_INT23_LEVEL 4
#define XCHAL_INT24_LEVEL 4
--- 195,199 ----
#define XCHAL_INT20_LEVEL 4
#define XCHAL_INT21_LEVEL 4
! #define XCHAL_INT22_LEVEL 2
#define XCHAL_INT23_LEVEL 4
#define XCHAL_INT24_LEVEL 4
***************
*** 188,192 ****
7 XCHAL_SEP \
5 XCHAL_SEP \
! 3 XCHAL_SEP \
4 XCHAL_SEP \
5 XCHAL_SEP \
--- 216,220 ----
7 XCHAL_SEP \
5 XCHAL_SEP \
! 1 XCHAL_SEP \
4 XCHAL_SEP \
5 XCHAL_SEP \
***************
*** 201,205 ****
4 XCHAL_SEP \
4 XCHAL_SEP \
! 1 XCHAL_SEP \
4 XCHAL_SEP \
4 XCHAL_SEP \
--- 229,233 ----
4 XCHAL_SEP \
4 XCHAL_SEP \
! 2 XCHAL_SEP \
4 XCHAL_SEP \
4 XCHAL_SEP \
***************
*** 322,326 ****
! /* External interrupt vectors/levels: */
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
--- 350,361 ----
! /*
! * External interrupt vectors/levels.
! * These macros describe how Xtensa processor interrupt numbers
! * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
! * map to external BInterrupt<n> pins, for those interrupts
! * configured as external (level-triggered, edge-triggered, or NMI).
! * See the Xtensa processor databook for more details.
! */
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
***************
*** 328,336 ****
#define XCHAL_EXTINT1_NUM 4 /* (intlevel 2) */
#define XCHAL_EXTINT2_NUM 7 /* (intlevel 7) */
! #define XCHAL_EXTINT3_NUM 9 /* (intlevel 3) */
#define XCHAL_EXTINT4_NUM 13 /* (intlevel 1) */
#define XCHAL_EXTINT5_NUM 15 /* (intlevel 1) */
#define XCHAL_EXTINT6_NUM 18 /* (intlevel 1) */
! #define XCHAL_EXTINT7_NUM 22 /* (intlevel 1) */
#define XCHAL_EXTINT8_NUM 23 /* (intlevel 4) */
#define XCHAL_EXTINT9_NUM 30 /* (intlevel 5) */
--- 363,371 ----
#define XCHAL_EXTINT1_NUM 4 /* (intlevel 2) */
#define XCHAL_EXTINT2_NUM 7 /* (intlevel 7) */
! #define XCHAL_EXTINT3_NUM 9 /* (intlevel 1) */
#define XCHAL_EXTINT4_NUM 13 /* (intlevel 1) */
#define XCHAL_EXTINT5_NUM 15 /* (intlevel 1) */
#define XCHAL_EXTINT6_NUM 18 /* (intlevel 1) */
! #define XCHAL_EXTINT7_NUM 22 /* (intlevel 2) */
#define XCHAL_EXTINT8_NUM 23 /* (intlevel 4) */
#define XCHAL_EXTINT9_NUM 30 /* (intlevel 5) */
***************
*** 352,360 ****
#define XCHAL_EXTINT1_LEVEL 2 /* (int number 4) */
#define XCHAL_EXTINT2_LEVEL 7 /* (int number 7) */
! #define XCHAL_EXTINT3_LEVEL 3 /* (int number 9) */
#define XCHAL_EXTINT4_LEVEL 1 /* (int number 13) */
#define XCHAL_EXTINT5_LEVEL 1 /* (int number 15) */
#define XCHAL_EXTINT6_LEVEL 1 /* (int number 18) */
! #define XCHAL_EXTINT7_LEVEL 1 /* (int number 22) */
#define XCHAL_EXTINT8_LEVEL 4 /* (int number 23) */
#define XCHAL_EXTINT9_LEVEL 5 /* (int number 30) */
--- 387,395 ----
#define XCHAL_EXTINT1_LEVEL 2 /* (int number 4) */
#define XCHAL_EXTINT2_LEVEL 7 /* (int number 7) */
! #define XCHAL_EXTINT3_LEVEL 1 /* (int number 9) */
#define XCHAL_EXTINT4_LEVEL 1 /* (int number 13) */
#define XCHAL_EXTINT5_LEVEL 1 /* (int number 15) */
#define XCHAL_EXTINT6_LEVEL 1 /* (int number 18) */
! #define XCHAL_EXTINT7_LEVEL 2 /* (int number 22) */
#define XCHAL_EXTINT8_LEVEL 4 /* (int number 23) */
#define XCHAL_EXTINT9_LEVEL 5 /* (int number 30) */
***************
*** 425,428 ****
--- 460,464 ----
#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation (Speculation) */
#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction (Privileged) */
+ #define XCHAL_EXCCAUSE_LOAD_STORE_ALIGNMENT 9 /* Load or Store to Unaligned Address (LoadStoreAlignment) */
#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception (ITlbMiss) */
#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception (ITlbMultihit) */
***************
*** 1196,1211 ****
(CoreID) set in the Xtensa Processor Generator */
! #define XCHAL_BUILD_UNIQUE_ID 0x00002BC6 /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
#define XCHAL_HW_CONFIGID0 0xC1FFDFFE /* config ID reg 0 value (upper 32 of 64 bits) */
! #define XCHAL_HW_CONFIGID1 0x00402BC6 /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
! #define XCHAL_HW_RELEASE_MINOR 0 /* minor release of targeted hardware */
! #define XCHAL_HW_RELEASE_NAME "T1050.0" /* full release name of targeted hardware */
#define XTHAL_HW_REL_T1050 1
! #define XTHAL_HW_REL_T1050_0 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
--- 1232,1247 ----
(CoreID) set in the Xtensa Processor Generator */
! #define XCHAL_BUILD_UNIQUE_ID 0x000063EB /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
#define XCHAL_HW_CONFIGID0 0xC1FFDFFE /* config ID reg 0 value (upper 32 of 64 bits) */
! #define XCHAL_HW_CONFIGID1 0x008063EB /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
! #define XCHAL_HW_RELEASE_MINOR 1 /* minor release of targeted hardware */
! #define XCHAL_HW_RELEASE_NAME "T1050.1" /* full release name of targeted hardware */
#define XTHAL_HW_REL_T1050 1
! #define XTHAL_HW_REL_T1050_1 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
Index: defs.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test/defs.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** defs.h 23 Oct 2002 20:53:21 -0000 1.1
--- defs.h 17 Jan 2003 18:17:49 -0000 1.2
***************
*** 2,6 ****
/*
! * Customer ID=40; Build=11206; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
--- 2,6 ----
/*
! * Customer ID=40; Build=25579; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
Index: specreg.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test/specreg.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** specreg.h 23 Oct 2002 20:53:21 -0000 1.1
--- specreg.h 17 Jan 2003 18:17:50 -0000 1.2
***************
*** 6,10 ****
/*
! * Customer ID=40; Build=11206; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
--- 6,10 ----
/*
! * Customer ID=40; Build=25579; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
Index: system.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test/system.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** system.h 23 Oct 2002 20:53:21 -0000 1.1
--- system.h 17 Jan 2003 18:17:50 -0000 1.2
***************
*** 12,16 ****
/*
! * Customer ID=40; Build=11206; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
--- 12,16 ----
/*
! * Customer ID=40; Build=25579; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
|
From: <joe...@us...> - 2003-01-17 18:10:22
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa In directory sc8-pr-cvs1:/tmp/cvs-serv27518 Modified Files: pgtable.h Log Message: Fix check for cache aliasing (currently disallowed). Index: pgtable.h =================================================================== RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/pgtable.h,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** pgtable.h 17 Jan 2003 00:31:30 -0000 1.4 --- pgtable.h 17 Jan 2003 18:10:15 -0000 1.5 *************** *** 63,70 **** /* Check for cache aliasing, and kill the build if found. */ ! #if (XCHAL_ICACHE_WAYS * PAGE_SIZE) > XCHAL_ICACHE_SIZE #error Cache aliasing not supported. #endif ! #if (XCHAL_DCACHE_WAYS * PAGE_SIZE) > XCHAL_DCACHE_SIZE #error Cache aliasing not supported. #endif --- 63,70 ---- /* Check for cache aliasing, and kill the build if found. */ ! #if XCHAL_ICACHE_SIZE > (XCHAL_ICACHE_WAYS * PAGE_SIZE) #error Cache aliasing not supported. #endif ! #if XCHAL_DCACHE_SIZE > (XCHAL_DCACHE_WAYS * PAGE_SIZE) #error Cache aliasing not supported. #endif |
|
From: <joe...@us...> - 2003-01-17 00:31:33
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv4681/include/asm-xtensa
Modified Files:
pgtable.h
Log Message:
Add support for writeback caches. Affects only linux_test config.
Index: pgtable.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/pgtable.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** pgtable.h 29 Oct 2002 01:20:33 -0000 1.3
--- pgtable.h 17 Jan 2003 00:31:30 -0000 1.4
***************
*** 27,68 ****
! /* With physically tagged caches and appropriately sized caches (to
! * avoid aliasing problems), caches do not need flushing at all. This
! * limitation is imposed on Xtensa Processors intending to run Linux.
! * Those using Xtensa Processors with potential aliasing problems must
! * rethink these macros.
*/
! /* XTFIXME: Perhaps a #error statement would be useful here. The
! * condition would be based on constants from the CHAL, and would
! * detect potential aliasing problems.
! */
! #define flush_dcache_page(page) do { } while (0)
! #define flush_cache_all() do { } while (0)
! #define flush_cache_mm(mm) do { } while (0)
! #define flush_cache_range(mm,start,end) do { } while (0)
! #define flush_cache_page(vma,page) do { } while (0)
! #define flush_cache_sigtramp(addr) do { } while (0)
! #define flush_page_to_ram(page) do { } while (0)
! #define flush_icache_range(start, end) flush_cache_all()
! #define flush_icache_page(vma, page) do { } while (0)
#define flush_icache_user_range(vma, page, addr, len) do { } while (0)
! #define invalidate_dcache_range(start, end) \
! do { \
! unsigned long v = (unsigned long)start & ~(XCHAL_DCACHE_LINESIZE - 1); \
! asm ("99: dhi %0, 0\n\r" \
! " addi %0, %0, " XTSTR(XCHAL_DCACHE_LINESIZE) "\n\r" \
! " blt %0, %1, 99b\n\r" : "+r" (v) : "r" (end)); \
! } while (0)
/* Basically we have the same two-level (which is the logical three level
* Linux page table layout folded) page tables as the i386.
*/
- #endif /* !defined (_LANGUAGE_ASSEMBLY) */
-
/* XTFIXME: Need to pull the following constant from the CHAL, if possible. */
#define WIRED_WAY_FOR_PAGE_TABLE 7
--- 27,79 ----
! /* Only if the dcache is writeback do we still need to flush at
! * times. Cache aliasing is not allowed (yet) and not supported (yet).
*/
! #if XCHAL_DCACHE_IS_WRITEBACK
! extern void flush_cache_all(void);
! extern void flush_cache_mm(struct mm_struct *mm);
! extern void flush_cache_range(struct mm_struct *mm, unsigned long start,
! unsigned long end);
! extern void flush_cache_page(struct vm_area_struct *vma, unsigned long page);
! extern void flush_icache_range(unsigned long start, unsigned long end);
! extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
! extern void flush_page_to_ram(struct page *page);
!
! /* dcache aliasing isn't a problem, so this can be null. */
! #define flush_dcache_page(page) do { } while (0)
!
! #else
!
! #define flush_dcache_page(page) do { } while (0)
! #define flush_cache_all() do { } while (0)
! #define flush_cache_mm(mm) do { } while (0)
! #define flush_cache_range(mm,start,end) do { } while (0)
! #define flush_cache_page(vma,page) do { } while (0)
! #define flush_cache_sigtramp(addr) do { } while (0)
! #define flush_page_to_ram(page) do { } while (0)
! #define flush_icache_range(start, end) do { } while (0)
! #define flush_icache_page(vma, page) do { } while (0)
#define flush_icache_user_range(vma, page, addr, len) do { } while (0)
! #endif
+ /* Check for cache aliasing, and kill the build if found. */
+
+ #if (XCHAL_ICACHE_WAYS * PAGE_SIZE) > XCHAL_ICACHE_SIZE
+ #error Cache aliasing not supported.
+ #endif
+ #if (XCHAL_DCACHE_WAYS * PAGE_SIZE) > XCHAL_DCACHE_SIZE
+ #error Cache aliasing not supported.
+ #endif
+
+ #endif /* !defined (_LANGUAGE_ASSEMBLY) */
+
/* Basically we have the same two-level (which is the logical three level
* Linux page table layout folded) page tables as the i386.
*/
/* XTFIXME: Need to pull the following constant from the CHAL, if possible. */
#define WIRED_WAY_FOR_PAGE_TABLE 7
***************
*** 743,750 ****
}
-
- /* The document "Linux Cache Flush Architecture" offers hints on
- * function update_mmu_cache, but it's misleading for Xtensa
- * processors. */
/* The kernel (in mm/memory.c) often invokes this macro when a page
--- 754,757 ----
|
|
From: <joe...@us...> - 2003-01-17 00:31:33
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory sc8-pr-cvs1:/tmp/cvs-serv4681/arch/xtensa/kernel Modified Files: pci-dma.c Log Message: Add support for writeback caches. Affects only linux_test config. Index: pci-dma.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/pci-dma.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** pci-dma.c 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- pci-dma.c 17 Jan 2003 00:31:30 -0000 1.2 *************** *** 33,36 **** --- 33,40 ---- } + #if XCHAL_DCACHE_IS_WRITEBACK + xthal_dcache_region_writeback_inv((void *)ret, size); + #endif + return (void*) BYPASS_ADDR((unsigned long)ret); } *************** *** 48,57 **** BUG(); case PCI_DMA_FROMDEVICE: /* invalidate only */ ! invalidate_dcache_range(vaddr, vaddr + size); break; case PCI_DMA_TODEVICE: /* writeback only */ break; case PCI_DMA_BIDIRECTIONAL: /* writeback and invalidate */ ! invalidate_dcache_range(vaddr, vaddr + size); break; } --- 52,73 ---- BUG(); case PCI_DMA_FROMDEVICE: /* invalidate only */ ! xthal_dcache_region_invalidate(vaddr, size); break; case PCI_DMA_TODEVICE: /* writeback only */ + + #if XCHAL_DCACHE_IS_WRITEBACK + /* Invoke only if wb-caches exist. Invoking nothing + * is better if no wb-caches exist. */ + xthal_dcache_region_writeback(vaddr, size); + #endif break; case PCI_DMA_BIDIRECTIONAL: /* writeback and invalidate */ ! ! /* On Xtensa processors without writeback caches, the ! * writeback functionality does nothing, leaving only ! * the invalidate functionality. Thus, it's safe to ! * call the writeback function. */ ! ! xthal_dcache_region_writeback_inv(vaddr, size); break; } |
|
From: <joe...@us...> - 2003-01-17 00:31:33
|
Update of /cvsroot/xtensa/linux/arch/xtensa/mm
In directory sc8-pr-cvs1:/tmp/cvs-serv4681/arch/xtensa/mm
Modified Files:
Makefile
Added Files:
cache.c
Log Message:
Add support for writeback caches. Affects only linux_test config.
--- NEW FILE: cache.c ---
/*
* arch/xtensa/mm/cache.c
*
* Documentation/cachetlb.txt implementation. Derived from many archs.
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file "COPYING" in the main directory of
* this archive for more details.
*
* Copyright (C) 2003 Tensilica Inc. (by Joe Taylor, jo...@te...)
*/
/* Some points to remember:
- Instruction and data caches are separate and independent.
- Icaches are never writeback.
- If dcaches are not writeback, dhwbi equals dhi, etc.
- When flushing a range in the icache, we have to first writeback
the dcache for the same range, so new ifetches will see any
data that was dirty in the dcache.
*/
/* XTFIXME: Compare against arch/mips/mm/r4xx0.c, which has extensive
tests before deciding to flush anything. Possible optimization
opportunities. */
/* XTFIXME: I don't know why the *cache_region_* functions don't do
the job in flush_cache_range, but the system hangs. Wiping it all
out works, though probably less efficiently than desired. */
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <xtensa/hal.h>
#if XCHAL_DCACHE_IS_WRITEBACK
void flush_cache_all(void)
{
unsigned long flags;
save_and_cli(flags);
xthal_dcache_all_writeback_inv();
xthal_icache_all_invalidate();
restore_flags(flags);
}
void flush_cache_mm(struct mm_struct *mm)
{
if (mm && mm->context != 0) {
#ifdef DEBUG_CACHE
printk("cmm[%d]", (int)mm->context);
#endif
/* Too compute intensive, so just wipe it all out. */
flush_cache_all();
}
}
void flush_cache_range(struct mm_struct *mm, unsigned long start,
unsigned long end)
{
flush_cache_all();
#if 0 /* this is broken for some reason.. */
struct vm_area_struct *vma;
if (!mm || mm->context == 0)
return;
start &= PAGE_MASK;
#ifdef DEBUG_CACHE
printk("crange[%d,%08lx,%08lx]", (long)mm->context, start, end);
#endif
vma = find_vma(mm, start);
if (!vma)
return;
if (mm->context != current->active_mm->context) {
flush_cache_all();
} else {
unsigned long flags;
save_and_cli(flags);
xthal_dcache_region_writeback_inv((void *)start, end - start);
xthal_icache_region_invalidate((void *)start, end - start);
restore_flags(flags);
}
#endif
}
void flush_cache_page(struct vm_area_struct *vma, unsigned long addr)
{
struct mm_struct *mm = vma->vm_mm;
unsigned long flags;
if (!mm || mm->context == 0)
return;
addr &= PAGE_MASK;
#ifdef DEBUG_CACHE
printk("cpage[%d,%08lx]", (long)mm->context, addr);
#endif
save_and_cli(flags);
xthal_dcache_region_writeback_inv((void *)addr, PAGE_SIZE);
xthal_icache_region_invalidate((void *)addr, PAGE_SIZE);
restore_flags(flags);
}
void flush_icache_range(unsigned long start, unsigned long end)
{
unsigned long flags;
save_and_cli(flags);
xthal_dcache_region_writeback_inv((void *)start, end - start);
xthal_icache_region_invalidate((void *)start, end - start);
restore_flags(flags);
}
void flush_icache_page(struct vm_area_struct *vma, struct page *page)
{
struct mm_struct *mm = vma->vm_mm;
unsigned long start;
if (!mm || mm->context == 0)
return;
if ( ! (vma->vm_flags & VM_EXEC) )
return;
start = (unsigned long) page_address(page);
#ifdef DEBUG_CACHE
printk("icpage[%d,%08lx]", (long)mm->context, start);
#endif
flush_icache_range(start, start + PAGE_SIZE);
}
void flush_page_to_ram (struct page *page)
{
unsigned long addr = (unsigned long) page_address(page);
unsigned long flags;
save_and_cli(flags);
xthal_dcache_region_writeback_inv((void *)addr, PAGE_SIZE);
restore_flags(flags);
}
/* Define only if dcache aliasing is a problem. It currently is not. */
#if 0
void flush_dcache_page (struct page *page)
{
unsigned long addr = (unsigned long) page_address(page);
unsigned long flags;
save_and_cli(flags);
xthal_dcache_region_writeback_inv((void *)addr, PAGE_SIZE);
restore_flags(flags);
}
#endif
#endif /* #if XCHAL_DCACHE_IS_WRITEBACK */
Index: Makefile
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/Makefile,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** Makefile 28 Aug 2002 16:10:14 -0000 1.1.1.1
--- Makefile 17 Jan 2003 00:31:30 -0000 1.2
***************
*** 9,13 ****
O_TARGET := mm.o
! obj-y := extable.o init.o fault.o loadmmu.o mmu.o
include $(TOPDIR)/Rules.make
--- 9,13 ----
O_TARGET := mm.o
! obj-y := extable.o init.o fault.o loadmmu.o mmu.o cache.o
include $(TOPDIR)/Rules.make
|
|
From: <ahe...@us...> - 2003-01-08 23:32:31
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv1563/include/asm-xtensa
Modified Files:
io.h
Log Message:
Added define for page_to_phys so compiles with 2.4.20 kernel.
Changed defines for memset_io,
memcpy_fromio and memcpy_toio to remove pci reference.
Index: io.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/io.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** io.h 28 Aug 2002 16:11:31 -0000 1.1.1.1
--- io.h 8 Jan 2003 23:32:28 -0000 1.2
***************
*** 48,51 ****
--- 48,56 ----
}
+ /*
+ * Change "struct page" to physical address.
+ */
+ #define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
+
extern inline void *ioremap(unsigned long offset, unsigned long size)
{
***************
*** 117,123 ****
#define IO_SPACE_LIMIT ~0
! #define memset_io(a,b,c) _memset_io(__mem_pci(a),(b),(c))
! #define memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_pci(b),(c))
! #define memcpy_toio(a,b,c) _memcpy_toio(__mem_pci(a),(b),(c))
/* At this point the Xtensa doesn't provide byte swap instructions */
--- 122,128 ----
#define IO_SPACE_LIMIT ~0
! #define memset_io(a,b,c) memset((void *)(a),(b),(c))
! #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
! #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
/* At this point the Xtensa doesn't provide byte swap instructions */
|
|
From: <ahe...@us...> - 2003-01-08 23:30:35
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv1197/include/asm-xtensa
Modified Files:
timex.h
Log Message:
Added defines for vxtime_lock and vmtime_unlock so compiles with 2.4.20
kernel.
Index: timex.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/timex.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** timex.h 28 Aug 2002 16:11:31 -0000 1.1.1.1
--- timex.h 8 Jan 2003 23:30:31 -0000 1.2
***************
*** 48,51 ****
--- 48,53 ----
}
+ #define vxtime_lock() do {} while (0)
+ #define vxtime_unlock() do {} while (0)
#endif /* __ASM_XTENSA_TIMEX_H */
|
|
From: <joe...@us...> - 2002-12-31 23:35:28
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory sc8-pr-cvs1:/tmp/cvs-serv13296/arch/xtensa/kernel Modified Files: head.S Log Message: Forgot to include <xtensa/cacheasm.h> for the dcache_writeback_all macro. cacheasm.h also include core.h. Index: head.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/head.S,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** head.S 16 Dec 2002 21:17:49 -0000 1.2 --- head.S 31 Dec 2002 23:35:24 -0000 1.3 *************** *** 27,31 **** #define _LANGUAGE_ASSEMBLY 1 #include <xtensa/config/specreg.h> ! #include <xtensa/config/core.h> #include <linux/config.h> #include <asm/page.h> --- 27,31 ---- #define _LANGUAGE_ASSEMBLY 1 #include <xtensa/config/specreg.h> ! #include <xtensa/cacheasm.h> #include <linux/config.h> #include <asm/page.h> |
|
From: <jgr...@us...> - 2002-12-16 22:38:48
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa In directory sc8-pr-cvs1:/tmp/cvs-serv17995/include/asm-xtensa Modified Files: checksum.h Log Message: Remove ifdefs surrounding csum_ipv6_magic; code for static inline will not be generated unless needed. Index: checksum.h =================================================================== RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/checksum.h,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** checksum.h 12 Dec 2002 22:54:43 -0000 1.2 --- checksum.h 16 Dec 2002 22:38:44 -0000 1.3 *************** *** 183,187 **** } - #if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) #define _HAVE_ARCH_IPV6_CSUM static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr, --- 183,186 ---- *************** *** 246,250 **** return csum_fold(sum); } - #endif /* --- 245,248 ---- |
|
From: <joe...@us...> - 2002-12-16 21:17:55
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory sc8-pr-cvs1:/tmp/cvs-serv19414 Modified Files: head.S Log Message: If caches are writeback, flush them after unpacking the text/data sections to ensure the data is available from memory thereafter. Index: head.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/head.S,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** head.S 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- head.S 16 Dec 2002 21:17:49 -0000 1.2 *************** *** 393,396 **** --- 393,404 ---- 1: + #if XCHAL_DCACHE_IS_WRITEBACK + + /* After unpacking, flush the writeback cache to memory so the + * instructions/data are available. */ + + dcache_writeback_all a3, a4 + #endif + #ifdef CONFIG_BLK_DEV_INITRD *************** *** 411,415 **** wsr a0, MISC_REG_1 #endif - _setup_stack: --- 419,422 ---- |
|
From: <jgr...@us...> - 2002-12-12 22:54:46
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa In directory sc8-pr-cvs1:/tmp/cvs-serv16705/include/asm-xtensa Modified Files: checksum.h Log Message: Fix undefined symbols for IPV6 module. Index: checksum.h =================================================================== RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/checksum.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** checksum.h 28 Aug 2002 16:11:31 -0000 1.1.1.1 --- checksum.h 12 Dec 2002 22:54:43 -0000 1.2 *************** *** 183,188 **** } #define _HAVE_ARCH_IPV6_CSUM - #ifdef CONFIG_IPV6 static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr, struct in6_addr *daddr, --- 183,188 ---- } + #if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) #define _HAVE_ARCH_IPV6_CSUM static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr, struct in6_addr *daddr, |
|
From: <jgr...@us...> - 2002-12-12 22:54:46
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory sc8-pr-cvs1:/tmp/cvs-serv16705/arch/xtensa/kernel Modified Files: xtensa_ksyms.c Log Message: Fix undefined symbols for IPV6 module. Index: xtensa_ksyms.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/xtensa_ksyms.c,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** xtensa_ksyms.c 19 Oct 2002 04:39:53 -0000 1.2 --- xtensa_ksyms.c 12 Dec 2002 22:54:43 -0000 1.3 *************** *** 32,35 **** --- 32,38 ---- #include <asm/floppy.h> #endif + #ifdef CONFIG_NET + #include <net/checksum.h> + #endif /* CONFIG_NET */ *************** *** 86,89 **** --- 89,99 ---- EXPORT_SYMBOL(__down_trylock); EXPORT_SYMBOL(__up); + + #ifdef CONFIG_NET + /* + * Networking support + */ + EXPORT_SYMBOL(csum_partial_copy_generic); + #endif /* CONFIG_NET */ /* |
|
From: <joe...@us...> - 2002-12-02 22:15:08
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa In directory sc8-pr-cvs1:/tmp/cvs-serv12851/include/asm-xtensa Modified Files: processor.h Log Message: Fix a structure that assumed config sizes were defined in words instead of bytes. The CHAL always defines sizes in bytes. Index: processor.h =================================================================== RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/processor.h,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** processor.h 1 Nov 2002 20:08:53 -0000 1.2 --- processor.h 2 Dec 2002 22:15:03 -0000 1.3 *************** *** 111,136 **** #if (XCHAL_CP_MASK & 1) ! unsigned cp0_regs[XCHAL_CP0_SA_SIZE] __attribute__ ((aligned(16))); #endif #if (XCHAL_CP_MASK & 2) ! unsigned cp1_regs[XCHAL_CP1_SA_SIZE] __attribute__ ((aligned(16))); #endif #if (XCHAL_CP_MASK & 4) ! unsigned cp2_regs[XCHAL_CP2_SA_SIZE] __attribute__ ((aligned(16))); #endif #if (XCHAL_CP_MASK & 8) ! unsigned cp3_regs[XCHAL_CP3_SA_SIZE] __attribute__ ((aligned(16))); #endif #if (XCHAL_CP_MASK & 16) ! unsigned cp4_regs[XCHAL_CP4_SA_SIZE] __attribute__ ((aligned(16))); #endif #if (XCHAL_CP_MASK & 32) ! unsigned cp5_regs[XCHAL_CP5_SA_SIZE] __attribute__ ((aligned(16))); #endif #if (XCHAL_CP_MASK & 64) ! unsigned cp6_regs[XCHAL_CP6_SA_SIZE] __attribute__ ((aligned(16))); #endif #if (XCHAL_CP_MASK & 128) ! unsigned cp7_regs[XCHAL_CP7_SA_SIZE] __attribute__ ((aligned(16))); #endif --- 111,144 ---- #if (XCHAL_CP_MASK & 1) ! #define __CP0SZ ((XCHAL_CP0_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned)) ! unsigned cp0_regs[__CP0SZ] __attribute__ ((aligned(16))); #endif #if (XCHAL_CP_MASK & 2) ! #define __CP1SZ ((XCHAL_CP1_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned)) ! unsigned cp1_regs[__CP1SZ] __attribute__ ((aligned(16))); #endif #if (XCHAL_CP_MASK & 4) ! #define __CP2SZ ((XCHAL_CP2_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned)) ! unsigned cp2_regs[__CP2SZ] __attribute__ ((aligned(16))); #endif #if (XCHAL_CP_MASK & 8) ! #define __CP3SZ ((XCHAL_CP3_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned)) ! unsigned cp3_regs[__CP3SZ] __attribute__ ((aligned(16))); #endif #if (XCHAL_CP_MASK & 16) ! #define __CP4SZ ((XCHAL_CP4_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned)) ! unsigned cp4_regs[__CP4SZ] __attribute__ ((aligned(16))); #endif #if (XCHAL_CP_MASK & 32) ! #define __CP5SZ ((XCHAL_CP5_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned)) ! unsigned cp5_regs[__CP5SZ] __attribute__ ((aligned(16))); #endif #if (XCHAL_CP_MASK & 64) ! #define __CP6SZ ((XCHAL_CP6_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned)) ! unsigned cp6_regs[__CP6SZ] __attribute__ ((aligned(16))); #endif #if (XCHAL_CP_MASK & 128) ! #define __CP7SZ ((XCHAL_CP7_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned)) ! unsigned cp7_regs[__CP7SZ] __attribute__ ((aligned(16))); #endif |
|
From: <joe...@us...> - 2002-12-02 21:05:18
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory sc8-pr-cvs1:/tmp/cvs-serv18536/arch/xtensa/kernel Modified Files: setup.c Log Message: Add the processor's unique build ID to /proc/cpuinfo Index: setup.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/setup.c,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** setup.c 2 Dec 2002 20:34:17 -0000 1.2 --- setup.c 2 Dec 2002 21:05:09 -0000 1.3 *************** *** 317,320 **** --- 317,321 ---- "release : " XCHAL_HW_RELEASE_NAME "\n" "core ID : " XCHAL_CORE_ID "\n" + "build ID : 0x%x\n" #if XCHAL_HAVE_BE "endianness : big\n" *************** *** 324,327 **** --- 325,329 ---- "cpu MHz : %u.%02u\n" "bogomips : %lu.%02lu\n", + XCHAL_BUILD_UNIQUE_ID, clock_tick_rate/1000000, (clock_tick_rate/10000) % 100, |
|
From: <joe...@us...> - 2002-12-02 20:34:33
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory sc8-pr-cvs1:/tmp/cvs-serv7467/arch/xtensa/kernel Modified Files: setup.c Log Message: Replace the hard-coded config name with the core ID properly derived from the CHAL. Index: setup.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/setup.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** setup.c 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- setup.c 2 Dec 2002 20:34:17 -0000 1.2 *************** *** 316,321 **** "arch : Xtensa\n" "release : " XCHAL_HW_RELEASE_NAME "\n" ! /* XTFIXME: Need to pull config name from CHAL. */ ! "config : linux_be\n" #if XCHAL_HAVE_BE "endianness : big\n" --- 316,320 ---- "arch : Xtensa\n" "release : " XCHAL_HW_RELEASE_NAME "\n" ! "core ID : " XCHAL_CORE_ID "\n" #if XCHAL_HAVE_BE "endianness : big\n" |
|
From: <joe...@us...> - 2002-12-02 20:33:01
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv6920/arch/xtensa/kernel
Modified Files:
proc.c
Log Message:
Remove dead code, cruft leftover from previous cpuinfo implementation.
Index: proc.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/proc.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** proc.c 28 Aug 2002 16:10:14 -0000 1.1.1.1
--- proc.c 2 Dec 2002 20:32:22 -0000 1.2
***************
*** 9,12 ****
--- 9,16 ----
*/
+ #if 0
+
+ /* Should we just move this function to irq.c and remove this file? */
+
#include <linux/delay.h>
#include <linux/kernel.h>
***************
*** 14,25 ****
#include <asm/processor.h>
! int get_cpuinfo(char *buffer)
! {
! /* XTFIXME: Need an implementation for Xtensa Processors. See
! * other architectures for examples.
! */
! buffer = "Nothing to report in LINUX/arch/xtensa/kernel/proc.c::get_cpuinfo()\n";
! return strlen(buffer);
! }
void init_irq_proc(void)
--- 18,22 ----
#include <asm/processor.h>
! #endif
void init_irq_proc(void)
***************
*** 27,28 ****
--- 24,26 ----
/* Nothing, for now. */
}
+
|
|
From: <joe...@us...> - 2002-12-02 20:32:35
|
Update of /cvsroot/xtensa/linux/arch/xtensa/platform-xt2000
In directory sc8-pr-cvs1:/tmp/cvs-serv6920/arch/xtensa/platform-xt2000
Modified Files:
setup.c
Log Message:
Remove dead code, cruft leftover from previous cpuinfo implementation.
Index: setup.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/platform-xt2000/setup.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** setup.c 18 Oct 2002 21:57:28 -0000 1.2
--- setup.c 2 Dec 2002 20:32:29 -0000 1.3
***************
*** 48,62 ****
- int xt2000_get_cpuinfo(char *buffer)
- {
- int len;
-
- len = sprintf(buffer, "vendor\t\t: Tensilica\n");
- len += sprintf(buffer+len, "platform\t\t: XT2000\n");
- len += sprintf(buffer+len, "memory type\t: SDRAM\n");
-
- return len;
- }
-
void __init xt2000_init_IRQ(void)
{
--- 48,51 ----
|
|
From: <joe...@us...> - 2002-12-02 20:32:33
|
Update of /cvsroot/xtensa/linux/arch/xtensa/platform-iss
In directory sc8-pr-cvs1:/tmp/cvs-serv6920/arch/xtensa/platform-iss
Modified Files:
setup.c
Log Message:
Remove dead code, cruft leftover from previous cpuinfo implementation.
Index: setup.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/platform-iss/setup.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** setup.c 18 Oct 2002 21:57:27 -0000 1.2
--- setup.c 2 Dec 2002 20:32:25 -0000 1.3
***************
*** 51,66 ****
}
- int iss_get_cpuinfo(char *buffer)
- {
- int len;
-
- len = sprintf(buffer, "vendor\t\t: Tensilica\n");
- len += sprintf(buffer+len, "platform\t\t: ISS\n");
- len += sprintf(buffer+len, "memory type\t: SDRAM\n");
-
- return len;
- }
-
-
static void iss_halt(void)
{
--- 51,54 ----
|
|
From: <joe...@us...> - 2002-12-02 19:35:09
|
Update of /cvsroot/xtensa/linux/arch/xtensa/lib/hal In directory sc8-pr-cvs1:/tmp/cvs-serv29384/arch/xtensa/lib/hal Modified Files: clock.S debug.c debug_hndlr.S disass.c int_asm.S interrupts.c memcopy.S misc.c mp_asm.S state_asm.S state.c windowspill_asm.S cache.c cache_asm.S Log Message: Documentation updates only. I'm removing warnings about auto-generated files. They are no longer auto-generated. Index: clock.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/hal/clock.S,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** clock.S 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- clock.S 2 Dec 2002 19:34:55 -0000 1.2 *************** *** 1,5 **** /* - * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND - * * arch/xtensa/lib/hal/clock.S -- assembly language clock routines * --- 1,3 ---- Index: debug.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/hal/debug.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** debug.c 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- debug.c 2 Dec 2002 19:34:55 -0000 1.2 *************** *** 1,5 **** /* - * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND - * * arch/xtensa/lib/hal/debug.c -- debug related constants and functions * --- 1,3 ---- Index: debug_hndlr.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/hal/debug_hndlr.S,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** debug_hndlr.S 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- debug_hndlr.S 2 Dec 2002 19:34:56 -0000 1.2 *************** *** 1,5 **** /* - * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND - * * arch/xtensa/lib/hal/debug_hndlr.S -- default Xtensa debug exception handler * --- 1,3 ---- Index: disass.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/hal/disass.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** disass.c 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- disass.c 2 Dec 2002 19:34:56 -0000 1.2 *************** *** 1,5 **** /* - * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND - * * arch/xtensa/lib/hal/disass.c -- disassembly routines for Xtensa * --- 1,3 ---- Index: int_asm.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/hal/int_asm.S,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** int_asm.S 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- int_asm.S 2 Dec 2002 19:34:56 -0000 1.2 *************** *** 1,5 **** /* - * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND - * * arch/xtensa/lib/hal/int_asm.S -- assembly language interrupt * utility routines --- 1,3 ---- Index: interrupts.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/hal/interrupts.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** interrupts.c 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- interrupts.c 2 Dec 2002 19:34:56 -0000 1.2 *************** *** 1,5 **** /* - * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND - * * arch/xtensa/lib/hal/interrupts.c -- interrupts related constants * and functions --- 1,3 ---- Index: memcopy.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/hal/memcopy.S,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** memcopy.S 21 Nov 2002 17:18:52 -0000 1.2 --- memcopy.S 2 Dec 2002 19:34:57 -0000 1.3 *************** *** 1,5 **** /* - * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND - * * arch/xtensa/lib/hal/memcopy.S -- Core HAL library functions * xthal_memcpy and xthal_bcopy --- 1,3 ---- Index: misc.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/hal/misc.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** misc.c 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- misc.c 2 Dec 2002 19:34:57 -0000 1.2 *************** *** 1,5 **** /* - * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND - * * arch/xtensa/lib/hal/misc.c -- miscellaneous constants * --- 1,3 ---- Index: mp_asm.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/hal/mp_asm.S,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** mp_asm.S 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- mp_asm.S 2 Dec 2002 19:34:57 -0000 1.2 *************** *** 1,15 **** ! // ! // mp_asm.S - multi-processor synchronization routines ! // ! // $Id$ ! ! // ! // Customer ID=40; Build=10963; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED. ! // These coded instructions, statements, and computer programs are the ! // copyrighted works and confidential proprietary information of Tensilica Inc. ! // They may not be modified, copied, reproduced, distributed, or disclosed to ! // third parties in any manner, medium, or form, in whole or in part, without ! // the prior written consent of Tensilica Inc. ! // #include <xtensa/coreasm.h> --- 1,11 ---- ! /* ! * arch/xtensa/lib/hal/mp_asm.S -- multiprocessor sync routines ! * ! * This file is subject to the terms and conditions of the GNU General Public ! * License. See the file "COPYING" in the main directory of this archive ! * for more details. ! * ! * Copyright (C) 2002 Tensilica Inc. ! */ #include <xtensa/coreasm.h> Index: state_asm.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/hal/state_asm.S,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** state_asm.S 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- state_asm.S 2 Dec 2002 19:34:57 -0000 1.2 *************** *** 1,5 **** /* - * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND - * * arch/xtensa/lib/hal/state_asm.S - assembly language processor * management routines --- 1,3 ---- Index: state.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/hal/state.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** state.c 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- state.c 2 Dec 2002 19:34:57 -0000 1.2 *************** *** 1,5 **** /* - * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND - * * arch/xtensa/lib/hal/state.c - processor state management routines * --- 1,3 ---- Index: windowspill_asm.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/hal/windowspill_asm.S,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** windowspill_asm.S 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- windowspill_asm.S 2 Dec 2002 19:34:57 -0000 1.2 *************** *** 1,5 **** /* - * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND - * * arch/xtensa/lib/hal/windowspill.S -- register window spill routine * --- 1,3 ---- Index: cache.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/hal/cache.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** cache.c 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- cache.c 2 Dec 2002 19:34:57 -0000 1.2 *************** *** 1,6 **** /* ! * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND ! * ! * arch/xtensa/lib/hal/cache.c -- cache management routines * * This file is subject to the terms and conditions of the GNU General Public --- 1,4 ---- /* ! * arch/xtensa/lib/hal/cache.c -- cache management information * * This file is subject to the terms and conditions of the GNU General Public Index: cache_asm.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/hal/cache_asm.S,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** cache_asm.S 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- cache_asm.S 2 Dec 2002 19:34:57 -0000 1.2 *************** *** 1,5 **** /* - * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND - * * arch/xtensa/lib/hal/cache_asm.S - assembly language cache * management routines --- 1,3 ---- |
|
From: <joe...@us...> - 2002-11-28 01:21:22
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test In directory sc8-pr-cvs1:/tmp/cvs-serv25260/include/asm-xtensa/xtensa/config-linux_test Modified Files: core.h Log Message: Add the core ID identifier for linux_test. Index: core.h =================================================================== RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test/core.h,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** core.h 23 Oct 2002 20:53:21 -0000 1.1 --- core.h 28 Nov 2002 01:21:16 -0000 1.2 *************** *** 1193,1196 **** --- 1193,1199 ---- #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* number of write buffer entries */ + #define XCHAL_CORE_ID "linux_test" /* configuration's alphanumeric core identifier + (CoreID) set in the Xtensa Processor Generator */ + #define XCHAL_BUILD_UNIQUE_ID 0x00002BC6 /* software build-unique ID (22-bit) */ |
|
From: <joe...@us...> - 2002-11-28 00:42:57
|
Update of /cvsroot/xtensa/linux/arch/xtensa/lib In directory sc8-pr-cvs1:/tmp/cvs-serv13939/arch/xtensa/lib Modified Files: strnlen_user.S Log Message: Remove potential unaligned access. Index: strnlen_user.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/strnlen_user.S,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** strnlen_user.S 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- strnlen_user.S 28 Nov 2002 00:42:54 -0000 1.2 *************** *** 131,136 **** .L2mod4: # address is 2 mod 4 ! EX(l32i, a9, a4, 4, lenfixup) # get word with first two bytes of string ! addi a4, a4, 2 # advance string pointer bnone a9, a7, .Lz2 # if byte 2 (of word, not string) is zero bany a9, a8, .Laligned # if byte 3 (of word, not string) is nonzero --- 131,136 ---- .L2mod4: # address is 2 mod 4 ! addi a4, a4, 2 # advance ptr for aligned access ! EX(l32i, a9, a4, 0, lenfixup) # get word with first two bytes of string bnone a9, a7, .Lz2 # if byte 2 (of word, not string) is zero bany a9, a8, .Laligned # if byte 3 (of word, not string) is nonzero |
|
From: <joe...@us...> - 2002-11-28 00:40:53
|
Update of /cvsroot/xtensa/linux/arch/xtensa/mm
In directory sc8-pr-cvs1:/tmp/cvs-serv11618/arch/xtensa/mm
Modified Files:
init.c
Log Message:
Add unaligned exception handling. None of this code is on by default, and we'll leave it off until we sync up with hardware that supports this exception. See the XTFIXME comment in the core.h files to enable this code.
Index: init.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/init.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** init.c 22 Sep 2002 21:46:48 -0000 1.3
--- init.c 28 Nov 2002 00:40:49 -0000 1.4
***************
*** 492,495 ****
--- 492,528 ----
}
+
+ static void unaligned_test (void);
+
+ void debug_hooks (void)
+ {
+
+ #ifdef CONFIG_KGDB
+
+ /* We put the kgdb hook here, since we want it in
+ * arch-specific code, and after the console has been
+ * initialized. Doing this right after the IRQs are
+ * initialized would be ideal, but then the user wouldn't see
+ * the "Waiting for..." message on the console. */
+
+ extern int gdb_enter;
+ extern void breakpoint(void);
+ extern void set_debug_traps(void);
+ extern void rs_kgdb_hook(void);
+ if (gdb_enter) {
+ rs_kgdb_hook();
+ set_debug_traps();
+ printk("Waiting for connection from remote gdb... \n");
+ breakpoint();
+ }
+ #endif
+
+ #ifdef DEBUG_UNALIGNMENT_TEST
+ unaligned_test();
+ #endif
+
+ }
+
+
/* mem_init()
*
***************
*** 528,549 ****
initsize >> 10);
! /* We put the kgdb hook here, since we want it in arch-specific code, and after
! * the console has been initialized. Doing this right after the IRQs are
! * initialized would be ideal, but then the user wouldn't see the
! * "Waiting for..." message on the console. */
! #ifdef CONFIG_KGDB
! extern int gdb_enter;
! extern void breakpoint(void);
! extern void set_debug_traps(void);
! extern void rs_kgdb_hook(void);
! if (gdb_enter) {
! rs_kgdb_hook();
! set_debug_traps();
! printk("Waiting for connection from remote gdb... \n");
! breakpoint();
! }
! #endif
!
}
--- 561,569 ----
initsize >> 10);
! /* We put the debug hooks here, since we want it in
! * arch-specific code, and after the console has been
! * initialized. */
+ debug_hooks();
}
***************
*** 594,595 ****
--- 614,949 ----
return;
}
+
+
+
+ /***************************************************************************
+ * Debug code for unaligned-access exceptions
+ * ... from here on down
+ */
+
+ #ifdef DEBUG_UNALIGNMENT_TEST
+
+ static inline int get_byte (char *p)
+ {
+ int i;
+ asm volatile (" l8ui %0, %1, 0\n" : "=a" (i) : "a" (p));
+ return i;
+ }
+
+ static inline int get_hword (char *p)
+ {
+ int i;
+ asm volatile (" l16ui %0, %1, 0\n" : "=a" (i) : "a" (p));
+ return i;
+ }
+
+ static inline int get_shword (char *p)
+ {
+ int i;
+ asm volatile (" l16si %0, %1, 0\n" : "=a" (i) : "a" (p));
+ return i;
+ }
+
+ static inline int get_word (char *p)
+ {
+ int i;
+ asm volatile (" l32i %0, %1, 0\n" : "=a" (i) : "a" (p));
+ return i;
+ }
+
+ static inline int get_wordn (char *p)
+ {
+ int i;
+ asm volatile (" l32i.n %0, %1, 0\n" : "=a" (i) : "a" (p));
+ return i;
+ }
+
+ static inline int store_word (char *p, int val)
+ {
+ int i;
+ asm volatile (" s32i %0, %1, 0\n" : : "a" (val), "a" (p));
+ return i;
+ }
+
+ static inline int store_wordn (char *p, int val)
+ {
+ int i;
+ asm volatile (" s32i.n %0, %1, 0\n" : : "a" (val), "a" (p));
+ return i;
+ }
+
+ static inline int store_hword (char *p, int val)
+ {
+ int i;
+ asm volatile (" s16i %0, %1, 0\n" : : "a" (val), "a" (p));
+ return i;
+ }
+
+ static void test_l32i (char *p, int val)
+ {
+ int i = get_word(p);
+ printk ("loaded 0x%.8x, test %s\n", i, ((i == val) ? "passed" : "failed"));
+ }
+
+ static void test_l32in (char *p, int val)
+ {
+ int i = get_wordn(p);
+ printk ("loaded 0x%.8x, test %s\n", i, ((i == val) ? "passed" : "failed"));
+ }
+
+ static void test_l16ui (char *p, int val)
+ {
+ int i = get_hword(p);
+ printk ("loaded 0x%.8x, test %s\n", i, ((i == val) ? "passed" : "failed"));
+ }
+
+ static void test_l16si (char *p, int val)
+ {
+ int i = get_shword(p);
+ printk ("loaded 0x%.8x, test %s\n", i, ((i == val) ? "passed" : "failed"));
+ }
+
+ #define BYTE0(x) ((x)&0xff)
+ #define BYTE1(x) (((x)>>8)&0xff)
+ #define BYTE2(x) (((x)>>16)&0xff)
+ #define BYTE3(x) (((x)>>24)&0xff)
+
+ #define REVERSE(x) ( (BYTE0(x)<<24) | (BYTE1(x)<<16) | (BYTE2(x)<<8) | BYTE3(x) )
+ #define REVERSE16(x) ( ((BYTE0(x)<<8) | BYTE1(x)) & 0x0000ffff )
+
+ #ifdef __XTENSA_EB__
+ #define RESULT(x) (x)
+ #else
+ #define RESULT(x) REVERSE(x)
+ #endif
+
+ static void test_s16i (char *space, int offset, int val)
+ {
+ /* Byte ops are OK here. Calling this function on an IRAM is an error. */
+
+ int i;
+ char *s = "failed";
+ unsigned short *p = (unsigned short *)space;
+ for (i=0; i<8; i++)
+ space[i] = 0xcc;
+
+ store_hword(&space[offset], val);
+
+ switch (offset) {
+ case 0:
+ if ((p[0] == val) && (p[1] == 0xcccc))
+ s = "passed";
+ break;
+ case 1:
+ if ((space[0] == 0xcc) &&
+ #ifdef __XTENSA_EB__
+ (space[1] == (val>>8)) &&
+ (space[2] == (val & 0xff)) &&
+ #else
+ (space[1] == (val & 0xff)) &&
+ (space[2] == (val >> 8)) &&
+ #endif
+ (space[3] == 0xcc) )
+ s = "passed";
+ break;
+ default:
+ break;
+ }
+
+ printk ("stored val=0x%.4x to 0x%.8x, test %s\n", val, (int)(&space[offset]), s);
+ }
+
+ #ifdef __XTENSA_EB__
+ #define GET_WORD(x,arr,off) \
+ x = ((arr)[(off)] << 24) | ((arr)[(off)+1] << 16) | ((arr)[(off)+2] << 8) | (arr)[(off)+3]
+ #else
+ #define GET_WORD(x,arr,off) \
+ x = ((arr)[(off)+3] << 24) | ((arr)[(off)+2] << 16) | ((arr)[(off)+1] << 8) | (arr)[(off)]
+ #endif
+
+ static int extract_word (char *p, int off)
+ {
+ int *ip = (int *)p;
+ char temp[8];
+ int i;
+
+ /* p may address IRAM. Copy it to the stack, where we know we
+ * can do byte operations. */
+
+ int *it = (int *)temp;
+ it[0] = ip[0];
+ it[1] = ip[1];
+
+ GET_WORD(i,temp,off);
+ return i;
+ }
+
+ static void test_s32i (char *space, int offset, int val, int narrow)
+ {
+ int i, first, second;
+ char *s = "failed";
+ int *p = (int *)space;
+ p[0] = 0xcccccccc;
+ p[1] = 0xcccccccc;
+
+ if (narrow)
+ store_word(&space[offset], val);
+ else
+ store_wordn(&space[offset], val);
+
+ i = extract_word (space, offset);
+ first = p[0];
+ second = p[1];
+
+ switch (offset) {
+ case 0:
+ if ((first == val) && (second == 0xcccccccc))
+ s = "passed";
+ break;
+ case 1:
+ if ( (i == val) &&
+ ((first & RESULT(0xff000000)) == RESULT(0xcc000000)) &&
+ ((second & RESULT(0x00ffffff)) == RESULT(0x00cccccc)) )
+ s = "passed";
+ break;
+ case 2:
+ if ( (i == val) &&
+ ((first & RESULT(0xffff0000)) == RESULT(0xcccc0000)) &&
+ ((second & RESULT(0x0000ffff)) == RESULT(0x0000cccc)) )
+ s = "passed";
+ break;
+ case 3:
+ if ( (i == val) &&
+ ((first & RESULT(0xffffff00)) == RESULT(0xcccccc00)) &&
+ ((second & RESULT(0x000000ff)) == RESULT(0x000000cc)) )
+ s = "passed";
+ break;
+ default:
+ break;
+ }
+
+ printk ("stored val=0x%.8x to 0x%.8x, test %s\n", val, (int)(&space[offset]), s);
+ }
+
+ static char load_space[16];
+ static char store_space[16];
+
+ int unaexc_count;
+ static int iram_base;
+
+ static inline int result16s(int x)
+ {
+ #ifdef __XTENSA_EL__
+ x = REVERSE16(x);
+ #endif
+ if (x & 0x00008000)
+ x |= 0xffff0000;
+ return x;
+ }
+
+ static inline int result16u(int x)
+ {
+ #ifdef __XTENSA_EL__
+ x = REVERSE16(x);
+ #endif
+ return x & 0x0000ffff;
+ }
+
+ static void test_all_loads (char *p)
+ {
+ /* Init buffer, then test unaligned loads. We must use 32-bit
+ * stores because the pointer may address IRAM. We setup
+ * memory to look the same, byte by byte, independent of
+ * endianness. This approach simplifies prediction of the
+ * loaded value, at least for me. :) */
+
+ int *ip = (int *)p;
+ #ifdef __XTENSA_EB__
+ ip[0] = 0x01234567;
+ ip[1] = 0x4080aa22;
+ ip[2] = 0x897b3dbf;
+ ip[3] = 0x89abcdef;
+ #else
+ ip[0] = 0x67452301;
+ ip[1] = 0x22aa8040;
+ ip[2] = 0xbf3d7b89;
+ ip[3] = 0xefcdab89;
+ #endif
+
+ test_l32i (p, RESULT(0x01234567));
+ test_l32i (p+1, RESULT(0x23456740));
+ test_l32i (p+2, RESULT(0x45674080));
+ test_l32i (p+3, RESULT(0x674080aa));
+
+ test_l32in (p, RESULT(0x01234567));
+ test_l32in (p+1, RESULT(0x23456740));
+ test_l32in (p+2, RESULT(0x45674080));
+ test_l32in (p+3, RESULT(0x674080aa));
+
+ /* Insn that work on 16-bits are not allowed in IRAMs. */
+
+ if ( ! iram_base ) {
+ test_l16ui (p, result16u(0x0123));
+ test_l16ui (p+1, result16u(0x2345));
+ test_l16ui (p+4, result16u(0x4080));
+ test_l16ui (p+5, result16u(0x80aa));
+
+ test_l16si (p, result16s(0x0123));
+ test_l16si (p+1, result16s(0x2345));
+ test_l16si (p+4, result16s(0x4080));
+ test_l16si (p+5, result16s(0x80aa));
+ }
+ }
+
+ static void test_all_stores (char *p)
+ {
+ test_s32i (p, 0, 0x33557799, /* narrow = */ 0);
+ test_s32i (p, 1, 0x33557799, /* narrow = */ 0);
+ test_s32i (p, 2, 0x33557799, /* narrow = */ 0);
+ test_s32i (p, 3, 0x33557799, /* narrow = */ 0);
+
+ test_s32i (p, 0, 0x22446688, /* narrow = */ 1);
+ test_s32i (p, 1, 0x22446688, /* narrow = */ 1);
+ test_s32i (p, 2, 0x22446688, /* narrow = */ 1);
+ test_s32i (p, 3, 0x22446688, /* narrow = */ 1);
+
+ /* Insn that work on 16-bits are not allowed in IRAMs. */
+
+ if ( ! iram_base ) {
+ test_s16i (p, 0, 0xaadd);
+ test_s16i (p, 1, 0xaadd);
+ }
+ }
+
+ static void unaligned_test(void)
+ {
+ printk ("\nSTARTING UNALIGNMENT TEST, KERNEL ACCESSES\n\n");
+
+ printk ("** Testing load instructions with buffer 0x%.8x\n", (int)load_space);
+ if (((int)(load_space)) & 3)
+ printk ("WARNING: load_space array is not on a word boundary.\n");
+ test_all_loads (load_space);
+
+ printk ("** Testing store instructions with buffer 0x%.8x\n", (int)store_space);
+ if (((int)(store_space)) & 3)
+ printk ("WARNING: store_space array is not on a word boundary.\n");
+ test_all_stores (store_space);
+
+ #if XCHAL_NUM_INSTRAM
+ iram_base = (int) XCHAL_INSTRAM0_VADDR;
+ printk ("** Testing load instructions with IRAM buffer 0x%.8x\n", iram_base);
+ test_all_loads ((char *)iram_base);
+
+ printk ("** Testing store instructions with IRAM buffer 0x%.8x\n",
+ (int)XCHAL_INSTRAM0_VADDR);
+ test_all_stores ((char *)XCHAL_INSTRAM0_VADDR);
+ iram_base = 0; /* done testing IRAMs */
+ #endif
+
+ printk ("\n%d unaligned exceptions occured\n", unaexc_count);
+ printk ("\nEND UNALIGNMENT TEST\n\n");
+
+ panic ("Debugging halt request after unalignment test");
+ }
+
+ #endif /* DEBUG_UNALIGNMENT_TEST */
|
|
From: <joe...@us...> - 2002-11-28 00:40:53
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv11618/arch/xtensa/kernel
Modified Files:
handlers.S traps.c
Log Message:
Add unaligned exception handling. None of this code is on by default, and we'll leave it off until we sync up with hardware that supports this exception. See the XTFIXME comment in the core.h files to enable this code.
Index: handlers.S
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/handlers.S,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** handlers.S 11 Nov 2002 22:25:25 -0000 1.7
--- handlers.S 28 Nov 2002 00:40:49 -0000 1.8
***************
*** 1193,1197 ****
.type _excStub,@function
_excStub:
! l32i a7, a1, PT_EXCCAUSE // vector number (also infrequently-used 2nd parm passed to handler, below)
// Determine which C handler to call, and place in a4.
--- 1193,1197 ----
.type _excStub,@function
_excStub:
! l32i a7, a1, PT_EXCCAUSE // vector number (also infrequently-used 2ndparm passed to handler, below)
// Determine which C handler to call, and place in a4.
***************
*** 1886,1889 ****
--- 1886,2589 ----
l32i a0, a0, RSAVE_A0 // restore a0 from memory
rfe
+
+
+ #if XCHAL_UNALIGNED_LOAD_EXCEPTION
+
+ /* First-level exit handler for unaligned exceptions.
+ *
+ * This handler works only for kernel exceptions. Unaligned user
+ * access should get a seg fault.
+ *
+ * Entry conditions: a0 is undefined
+ * depc contains original a0 value
+ */
+
+
+ .macro src_b r, w0, w1
+ #ifdef __XTENSA_EB__
+ src \r, \w0, \w1
+ #else
+ src \r, \w1, \w0
+ #endif
+ .endm
+
+ .macro ssa8 r
+ #ifdef __XTENSA_EB__
+ ssa8b \r
+ #else
+ ssa8l \r
+ #endif
+ .endm
+
+
+ .data
+ .align 4
+
+ /* Define some offsets for robustness and readability.
+ *
+ * WARNING: If you add or subtract to this list, you'll likely impact
+ * code at labels unaligned_copyreg and unaligned_movereg below. */
+
+ #define UNALIGNED_A0 0
+ #define UNALIGNED_A2 4
+ #define UNALIGNED_A3 8
+ #define UNALIGNED_A4 12
+ #define UNALIGNED_A5 16
+ #define UNALIGNED_A6 20
+ #define UNALIGNED_A7 24
+ #define UNALIGNED_SAR 28
+ #define UNALIGNED_TOTAL 32
+
+ unaligned_space:
+ .space UNALIGNED_TOTAL, 0
+ unaligned_scratch:
+ .space 2*4, 0
+
+ .text
+
+ .align 4
+ .global handle_unaligned_kernel
+ handle_unaligned_kernel:
+
+ /* Save some working registers. We also save the original a0
+ * to memory so we don't lose it when a double exception
+ * happens (and overwrites DEPC). A double exception can
+ * reasonably happen in kernel mode with vmalloc memory. */
+
+ movi a0, unaligned_space
+ s32i a2, a0, UNALIGNED_A2 // save a2
+ rsr a2, EPC_1 // load PC of load/store
+ s32i a3, a0, UNALIGNED_A3 // save a3
+ rsr a3, DEPC // load original a0
+ s32i a4, a0, UNALIGNED_A4 // save a4
+ rsr a4, SAR // load original SAR
+ s32i a5, a0, UNALIGNED_A5 // save a5
+ s32i a6, a0, UNALIGNED_A6 // save a6
+ s32i a7, a0, UNALIGNED_A7 // save a7
+ s32i a3, a0, UNALIGNED_A0 // save a0
+ s32i a4, a0, UNALIGNED_SAR // save SAR
+
+ #ifdef DEBUG_UNALIGNMENT_TEST
+ movi a3, unaexc_count
+ l32i a4, a3, 0
+ addi a4, a4, 1
+ s32i a4, a3, 0
+ #endif
+
+ /* Now, identify one of the following load/store instructions.
+
+ xxxx xxxx = imm8 field
+ yyyy = imm4 field
+ ssss = s field
+ tttt = t field
+
+ 23 0
+ -----------------------------
+ L32I xxxx xxxx 0010 ssss tttt 0010
+ L32I.N yyyy ssss tttt 1000
+ L32SI xxxx xxxx 0011 ssss tttt 0010
+ L16UI xxxx xxxx 0001 ssss tttt 0010
+ L16SI xxxx xxxx 1001 ssss tttt 0010
+
+ S32I xxxx xxxx 0110 ssss tttt 0010
+ S32I.N yyyy ssss tttt 1001
+ S16I xxxx xxxx 0101 ssss tttt 0010
+ S32RI xxxx xxxx 1111 ssss tttt 0010
+ -----------------------------
+ ^ ^ ^
+ sub-opcode (NIBBLE_R) -+ | |
+ t field (NIBBLE_T) -----------+ |
+ major opcode (NIBBLE_OP0) --------------+
+
+ * The maximum instruction size is 24 bits. Our strategy
+ * below is to load the complete instruction into a register
+ * so we can interrogate various fields. However, formats and
+ * orientation within the register will differ based on
+ * endianess. For big endian processors, we pack the
+ * instruction words in the most-significant end of the
+ * register. For little endian, we pack the instruction at
+ * the least-significant end. We preserve the original
+ * instruction format per endian ordering (see the ISA chapter
+ * entitled "Instruction Formats and Opcodes").
+
+ * Because endian-different Xtensa processors have different
+ * instruction formats, we define the following constants into
+ * the register to access certain fields of the instruction.
+
+ */
+
+ #if XCHAL_HAVE_BE
+ #define NIBBLE_OP0 28
+ #else
+ #define NIBBLE_OP0 0
+ #endif
+
+ #if XCHAL_HAVE_BE
+ #define NIBBLE_T 24
+ #else
+ #define NIBBLE_T 4
+ #endif
+
+ #if XCHAL_HAVE_BE
+ #define NIBBLE_R 16
+ #else
+ #define NIBBLE_R 12
+ #endif
+
+ /* Big and little endian 16-bit values are located in
+ * different halves of a register. HWORD_START helps to
+ * abstract the notion of extracting a 16-bit value from a
+ * register. */
+
+ #if XCHAL_HAVE_BE
+ #define HWORD_START 16
+ #else
+ #define HWORD_START 0
+ #endif
+
+ /* If the exception address is already aligned on a word
+ * boundary, the exception is spurious, and we just return.
+ * Note that we want to test and return before advancing over
+ * the load or store instruction so the processor can
+ * re-execute the instruction at EPC_1 when the spurious
+ * exception occured. Also, this handler does not consider
+ * the case of a load/store of a 16-bit value on a halfword
+ * boundary, which would also be spurious. For this 16-bit
+ * value case, this handler ends up loading/storing the value,
+ * and returns. */
+
+ rsr a3, EXCVADDR // read unaligned memory address
+ extui a3, a3, 0, 2 // branch to return if exc is spurious
+ beqz a3, unaligned_return // (if addr is already aligned)
+
+ /* We align the instruction address (EPC_1, not EXCVADDR),
+ * load two words, and shift the bytes such that the next
+ * three instruction bytes are in the most/least-significant
+ * end of a4 for big/little endianess, respectively. Also,
+ * remember narrow instructions are only two bytes.
+ *
+ * The only possible danger of a double exception on the
+ * following l32i instructions is kernel code in vmalloc
+ * memory. The processor was just executing at the EPC_1
+ * address, and indeed, already fetched the instruction. That
+ * guarantees a TLB mapping, which hasn't been replaced by
+ * this unaligned exception handler that uses only static TLB
+ * mappings. However, high-level interrupt handlers might
+ * modify TLB entries, so for the generic case, we register a
+ * TABLE_FIXUP handler here, too. */
+
+ movi a6, find_handler
+ rsr a7, EXCSAVE_1
+ s32i a6, a7, TABLE_FIXUP
+
+ movi a3, ~3
+ and a3, a3, a2 // mask lower bits
+ l32i a4, a3, 0 // load 2 words
+ l32i a5, a3, 4
+ ssa8 a2
+ src_b a4, a4, a5 // a4 has insn bytes
+ movi a6, 0
+ s32i a6, a7, TABLE_FIXUP
+
+ /* We first check for load instructions and branch to handle
+ * them when found. */
+
+ extui a5, a4, NIBBLE_OP0, 4 // load insn.op0 nibble
+
+ #if XCHAL_HAVE_DENSITY
+ _beqi a5, 8, unaligned_loadn // L32I.N
+ #endif
+ _bnei a5, 2, 1f // branch if no more loads
+ extui a6, a4, NIBBLE_R, 4 // load insn.r nibble
+ _beqi a6, 2, unaligned_load // L32I
+ #if XCHAL_HAVE_SPECULATION
+ _beqi a6, 3, unaligned_load // L32SI
+ #endif
+ _beqi a6, 1, unaligned_load // L16UI
+ movi a7, 9
+ _beq a6, a7, unaligned_load // L16SI
+ 1:
+ j check_for_stores
+
+ /* Control comes here when we have a load instruction
+ * accessing an unaligned address. At this point,
+
+ a2 = EPC_1
+ a3 = EPC_1 & ~3
+ a4 = packed instruction nibbles
+ a5, a6, and a7 are temp registers
+
+ * We carefully use only 32-bit load instructions so that this
+ * handler will also work with IRAM (which requires 32-bit
+ * accesses). */
+
+ unaligned_loadn:
+
+ addi a7, a2, 2 // advance over 16-bit l32i.n insn
+ wsr a7, EPC_1 // ...
+ j 3f
+
+ unaligned_load:
+
+ addi a7, a2, 3 // advance over 24-bit load insn
+ wsr a7, EPC_1 // ...
+ 3:
+
+ /* Before accessing memory, we must first register a
+ * TABLE_FIXUP handler. Should this data reside in vmalloc
+ * memory without an existing TLB mapping, a double exception
+ * could occur. */
+
+ movi a5, find_handler
+ rsr a6, EXCSAVE_1
+ rsr a2, EXCVADDR // load unaligned memory address
+ movi a3, ~3 // align memory address
+ and a3, a3, a2 // ...
+ s32i a5, a6, TABLE_FIXUP
+
+ l32i a5, a3, 0 // load 2 words
+ l32i a6, a3, 4
+ ssa8 a2
+ src_b a5, a5, a6 // a5 has word to return
+
+ /* We're done accessing memory, so clear the TABLE_FIXUP
+ * handler. */
+
+ rsr a6, EXCSAVE_1
+ movi a7, 0
+ s32i a7, a6, TABLE_FIXUP
+
+ /* a5 now has 32 bits from the unaligned memory address.
+ * Probe the instruction once again to see if it should be
+ * signed/unsigned 16-bit value instead, and make it so. The
+ * algorithm here is as follows:
+ *
+ * 1. If it's the narrow load, branch ahead.
+ * 2. Otherwise, check the R nibble for L16UI or L16SI.
+ *
+ * Omitting step one is wrong, since we may just be checking
+ * the yyyy field of an L32I.N instruction.
+ */
+
+ extui a6, a4, NIBBLE_OP0, 4 // get insn.op0 nibble
+ _beqi a6, 8, 5f // branch if L32I.N
+ extui a6, a4, NIBBLE_R, 4 // get insn.r nibble
+ _beqi a6, 1, 4f // branch if L16UI
+ movi a7, 9
+ _bne a6, a7, 5f // branch if not L16SI
+
+ extui a5, a5, HWORD_START, 16 // 16-bit, still unsigned
+ movi a6, 16
+ ssr a6 // ssr and ssl are equal when a6=16
+ sll a5, a5 // put the sign bit in the ms-bit
+ sra a5, a5 // copy the sign bit in 31..16
+ j 5f // a5 is now 16-bit, signed
+ 4:
+ extui a5, a5, HWORD_START, 16 // 16-bit, unsigned
+
+ /* a5 now contains the word of interest. Figure out the
+ * destination register and put the value there before
+ * returning. */
+
+ 5: extui a6, a4, NIBBLE_T, 4 // get dst register number
+ movi a7, unaligned_copyreg
+ addx8 a7, a6, a7 // index into jump table
+ jx a7 // jump according to dst reg
+
+ /* The following code is dependent on the working registers we
+ * save at the start of this exception handler. Should
+ * someone add or subtract to that list, the following code
+ * will likely break. */
+
+ #if (UNALIGNED_TOTAL != 32)
+ #error Changes to saved-register list impact the following code
+ #endif
+
+ .align 8
+ unaligned_copyreg:
+ s32i a5, a0, UNALIGNED_A0 // dst=a0
+ _j 1f
+ .align 8
+ mov a1, a5 // dst=a1, fishy??
+ _j 1f
+ .align 8
+ s32i a5, a0, UNALIGNED_A2 // dst=a2
+ _j 1f
+ .align 8
+ s32i a5, a0, UNALIGNED_A3 // dst=a3
+ _j 1f
+ .align 8
+ s32i a5, a0, UNALIGNED_A4 // dst=a4
+ _j 1f
+ .align 8
+ s32i a5, a0, UNALIGNED_A5 // dst=a5
+ _j 1f
+ .align 8
+ s32i a5, a0, UNALIGNED_A6 // dst=a6
+ _j 1f
+ .align 8
+ s32i a5, a0, UNALIGNED_A7 // dst=a7
+ _j 1f
+ .align 8
+ mov a8, a5 // dst=a8
+ _j 1f
+ .align 8
+ mov a9, a5 // dst=a9
+ _j 1f
+ .align 8
+ mov a10,a5 // dst=a10
+ _j 1f
+ .align 8
+ mov a11,a5 // dst=a11
+ _j 1f
+ .align 8
+ mov a12,a5 // dst=a12
+ _j 1f
+ .align 8
+ mov a13,a5 // dst=a13
+ _j 1f
+ .align 8
+ mov a14,a5 // dst=a14
+ _j 1f
+ .align 8
+ mov a15,a5 // dst=a15
+ _j 1f
+
+ /* The dst register (or corresponding memory location)
+ * contains the desired word from the unaligned memory
+ * address, so we can now restore the working registers, and
+ * return. */
+
+ .align 4
+ 1:
+ unaligned_return:
+ l32i a6, a0, UNALIGNED_SAR
+ l32i a2, a0, UNALIGNED_A2
+ l32i a3, a0, UNALIGNED_A3
+ wsr a6, SAR
+ l32i a4, a0, UNALIGNED_A4
+ l32i a5, a0, UNALIGNED_A5
+ l32i a6, a0, UNALIGNED_A6
+ l32i a7, a0, UNALIGNED_A7
+ l32i a0, a0, UNALIGNED_A0
+ rfe
+
+
+ /* After not finding any load instructions, control branches
+ * to here to check for stores. At this point
+
+ a2 = EPC_1
+ a3 = EPC_1 & ~3
+ a4 = packed instruction bytes
+ a5 = insn.op0 nibble
+ a6, a7 = scratch registers
+ */
+
+ check_for_stores:
+ #if XCHAL_HAVE_DENSITY
+ movi a7, 9
+ _beq a5, a7, unaligned_storen // S32I.N
+ #endif
+ _bnei a5, 2, 3f // branch if no more stores
+ extui a6, a4, NIBBLE_R, 4 // load insn.r nibble
+ _beqi a6, 6, unaligned_store // S32I
+ _beqi a6, 5, unaligned_store // S16I
+ #if 0 /* not implemented in hardware yet */
+ movi a7, 15
+ _beq a6, a7, unaligned_store // S32RI
+ #endif
+
+ /* We didn't find a valid load or store instruction. The
+ * exception is spurious, so just return. Note that we
+ * haven't yet advance EPC_1 to skip the current instruction,
+ * so the processor will re-execute it. */
+
+ j unaligned_return
+
+ /* Control comes here when we have a store instruction
+ * accessing an unaligned address. Advance EPC over the store
+ * instruction. */
+
+ unaligned_storen:
+ addi a7, a2, 2 // advance over 16-bit s32i.n insn
+ wsr a7, EPC_1 // ...
+ j 3f
+
+ unaligned_store:
+ addi a7, a2, 3 // advance over 24-bit store insn
+ wsr a7, EPC_1 // ...
+ 3:
+
+ /* First, we must identify the register in which the data
+ * resides, and copy it to a5. */
+
+ extui a5, a4, NIBBLE_T, 4 // src reg number
+ movi a7, unaligned_movereg
+ addx8 a7, a5, a7 // index into jump table
+ jx a7 // jump according to src reg
+
+ /* The following code is dependent on the working registers we
+ * save at the start of this exception handler. Should
+ * someone add or subtract to that list, the following code
+ * will likely break. */
+
+ #if (UNALIGNED_TOTAL != 32)
+ #error Changes to saved-register list impact the following code
+ #endif
+
+ .align 8
+ unaligned_movereg:
+ l32i a5, a0, UNALIGNED_A0 // src=a0
+ _j 1f
+ .align 8
+ mov a1, a5 // src=a1, fishy??
+ _j 1f
+ .align 8
+ l32i a5, a0, UNALIGNED_A2 // src=a2
+ _j 1f
+ .align 8
+ l32i a5, a0, UNALIGNED_A3 // src=a3
+ _j 1f
+ .align 8
+ l32i a5, a0, UNALIGNED_A4 // src=a4
+ _j 1f
+ .align 8
+ l32i a5, a0, UNALIGNED_A5 // src=a5
+ _j 1f
+ .align 8
+ l32i a5, a0, UNALIGNED_A6 // src=a6
+ _j 1f
+ .align 8
+ l32i a5, a0, UNALIGNED_A7 // src=a7
+ _j 1f
+ .align 8
+ mov a5, a8 // src=a8
+ _j 1f
+ .align 8
+ mov a5, a9 // src=a9
+ _j 1f
+ .align 8
+ mov a5, a10 // src=a10
+ _j 1f
+ .align 8
+ mov a5, a11 // src=a11
+ _j 1f
+ .align 8
+ mov a5, a12 // src=a12
+ _j 1f
+ .align 8
+ mov a5, a13 // src=a13
+ _j 1f
+ .align 8
+ mov a5, a14 // src=a14
+ _j 1f
+ .align 8
+ mov a5, a15 // src=a15
+ _j 1f
+
+ /* a5 now contains the data to save. Now, store 32-bits or
+ * 16-bits? To local IRAM or not? Several cases to check...
+ *
+ * If the store address is not in local IRAM, we simply store
+ * 8 bits at a time, until the data is written. Local IRAM
+ * requires 32-bit stores, so that case is more complex.
+ * Furthermore, Xtensa processors may have multiple IRAMs at
+ * noncontiguous addresses (in theory, at least), so we use
+ * the compile-time HAL to determine (1) how many exist, (2)
+ * where each is located, and (3) the size of each. Note,
+ * however, that the T1050 release was limited to a single
+ * IRAM, and the following release might support two IRAMs.
+ *
+ * The purpose of the following iramchk macro is to provide
+ * the infrastructure to support an arbitrary number of IRAMs
+ * of various sizes at noncontiguous addresses. As of this
+ * writing, the code supports only two local IRAMs (this
+ * should last a long while). Adding support for additional
+ * IRAMs is trivial with the iramchk macro. Just add new
+ * conditional blocks similar to the (XCHAL_NUM_INSTRAM >= 2)
+ * block below.
+ *
+ * The iramchk macro has 4 arguments (all are registers):
+ *
+ * iram_base = base virtual address of the IRAM
+ * iram_size = size (in bytes) of the IRAM
+ * first_byte = first memory address of the store
+ * last_byte = last memory address of the store
+ *
+ * The iram_{base,size} arguments should come straight from
+ * the compile-time HAL. The first and last byte addresses of
+ * the store help determine exactly whether the store resides
+ * within, even partially, the IRAM. A store may be 2 or 4
+ * bytes, so the last_byte parameter is not fixed relative to
+ * the first_byte.
+ *
+ * Macro iramchk modifies only the iram_size register.
+ *
+ * If iramchk finds a store residing at all in IRAM, it will
+ * branch to label iram_store. Otherwise, it falls through.
+ */
+
+ .macro iramchk iram_base, iram_size, first_byte, last_byte
+ bltu \last_byte, \iram_base, 0f // check next
+ add \iram_size, \iram_size, \iram_base
+ bltu \first_byte, \iram_size, iram_store
+ 0:
+ .endm
+
+ .align 4
+ 1:
+ rsr a2, EXCVADDR // load unaligned memory address
+ movi a3, ~3 // align memory address
+ and a3, a3, a2 // ...
+
+ #if XCHAL_NUM_INSTRAM
+
+ /* For our IRAM comparisions, we can assume the store is 4
+ * bytes. 16-bit stores to IRAM result in a Load Store Error
+ * exception. */
+
+ movi a3, 3 // stores to IRAM are 4 bytes
+ add a3, a2, a3 // a3 <-- addr of last byte of store
+ movi a6, XCHAL_INSTRAM0_VADDR
+ movi a7, XCHAL_INSTRAM0_SIZE
+ iramchk a6, a7, a2, a3
+
+ #if (XCHAL_NUM_INSTRAM >= 2)
+ movi a6, XCHAL_INSTRAM1_VADDR
+ movi a7, XCHAL_INSTRAM1_SIZE
+ iramchk a6, a7, a2, a3
+ #endif
+
+ #if (XCHAL_NUM_INSTRAM >= 3)
+ #error More than two local IRAMs not handled!
+ /* To handle more IRAMs, you really just need to add more conditionals
+ * like the one above. */
+ #endif
+
+ /* Control falls through to here when we're done checking
+ * whether the store falls within an IRAM. In this case, we
+ * have a non-IRAM store, so just jump to that code. */
+
+ j noniram_store
+
+ /* The iramchk macro jumps to here when we have a store to a
+ * local IRAM. Worst case is that two IRAM words need
+ * modification. The strategy here is to copy the two words
+ * from IRAM to some temp space where we know we can use 8-bit
+ * stores, then use common code below to insert the store data
+ * appropriately, then copy the data back into IRAM. Recall
+ * that
+ *
+ * a2 = store address
+ * a4 = packed instruction bytes
+ * a5 = data to store
+ * a3, a6, a7 = working registers
+ */
+
+ iram_store:
+
+ /* Register a fixup handler since the IRAM may not be mapped.
+ * However, it usually is mapped through a wired way. */
+
+ movi a3, find_handler
+ rsr a6, EXCSAVE_1
+ s32i a3, a6, TABLE_FIXUP
+
+ movi a3, ~3
+ and a3, a3, a2
+ movi a2, unaligned_scratch
+ l32i a6, a3, 0 // load first word
+ l32i a7, a3, 4 // load second word
+ s32i a6, a2, 0 // save first word
+ s32i a7, a2, 4 // save second word
+
+ /* Mimic the odd IRAM address in the unaligned_scratch space
+ * for the common code below. Also, set a7 as a flag to the
+ * common code so it knows it must recopy the data back to
+ * IRAM. */
+
+ rsr a3, EXCVADDR
+ extui a3, a3, 0, 2 // get 2 lsbits
+ or a2, a2, a3 // copy over 2 lsbits to scratch addr
+ movi a7, 1 // set IRAM flag
+ j 1f
+
+ #endif /* XCHAL_NUM_INSTRAM */
+
+ noniram_store:
+ movi a7, 0 // clear IRAM flag
+
+ /* These stores might not be mapped in the tlb, so register a
+ * TABLE_FIXUP handler. */
+
+ movi a3, find_handler
+ rsr a6, EXCSAVE_1
+ s32i a3, a6, TABLE_FIXUP
+
+ /* Test the instruction again to see whether we should store 2
+ * or 4 bytes. We use this algorithm to compute whether we
+ * have a 16-bit store:
+ *
+ * 1. If it's the narrow store, branch ahead.
+ * 2. Otherwise, check the R nibble for S16I.
+ *
+ * Omitting step one is wrong, since we may just be checking
+ * the yyyy field of an S32I.N instruction.
+ */
+
+ 1: extui a6, a4, NIBBLE_OP0, 4 // get insn.op0 nibble
+ addi a6, a6, -1 // no spare regs, check for 9
+ _beqi a6, 9-1, 3f // branch if S32I.N
+ extui a6, a4, NIBBLE_R, 4
+ _beqi a6, 5, 2f // branch if S16I
+ 3:
+
+ #if XCHAL_HAVE_BE
+ s8i a5, a2, 3 // Store each byte in big-endian order.
+ srli a5, a5, 8 // Note the entry point at 2: for S16I.
+ s8i a5, a2, 2
+ srli a5, a5, 8
+ 2: s8i a5, a2, 1
+ srli a5, a5, 8
+ s8i a5, a2, 0
+ #else
+ s8i a5, a2, 0 // Store each byte in little-endian
+ addi a2, a2, 1 // order. Note the entry point at 2:
+ srli a5, a5, 8 // for S16I. The store32 case is
+ // slightly more complex than needed
+ s8i a5, a2, 0 // to accomodate and simplify the S16I
+ addi a2, a2, 1 // case in a general way.
+ srli a5, a5, 8
+
+ 2: s8i a5, a2, 0
+ addi a2, a2, 1
+ srli a5, a5, 8
+
+ s8i a5, a2, 0
+ #endif
+
+ /* Now check the IRAM flag. If set, we came from the
+ * iram_store code, and we must copy the data back to IRAM.
+ * Otherwise, the data is already stored, and we just branch
+ * to clear TABLE_FIXUP, and return. */
+
+ beqz a7, 3f
+
+ rsr a2, EXCVADDR
+ movi a3, unaligned_scratch
+ movi a6, ~3
+ and a2, a2, a6
+ l32i a6, a3, 0
+ l32i a7, a3, 4
+ s32i a6, a2, 0
+ s32i a7, a2, 4
+ 3:
+ rsr a7, EXCSAVE_1
+ movi a6, 0
+ s32i a6, a7, TABLE_FIXUP
+
+ j unaligned_return
+
+ #endif /* XCHAL_UNALIGNED_LOAD_EXCEPTION */
Index: traps.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/traps.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** traps.c 11 Nov 2002 22:25:25 -0000 1.4
--- traps.c 28 Nov 2002 00:40:49 -0000 1.5
***************
*** 51,54 ****
--- 51,55 ----
extern asmlinkage void handle_double_2nd_level_miss (void);
extern asmlinkage void handle_2nd_level_miss (void);
+ extern asmlinkage void handle_unaligned_kernel (void);
extern asmlinkage void do_page_fault (void);
#if (XCHAL_CP_MASK & 1)
***************
*** 83,87 ****
} _exceptions_t;
! _exceptions_t exc_translations [] = {
{ XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION, "Illegal Instruction" },
--- 84,88 ----
} _exceptions_t;
! static _exceptions_t exc_translations [] = {
{ XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION, "Illegal Instruction" },
***************
*** 256,263 ****
--- 257,312 ----
+ #if XCHAL_UNALIGNED_LOAD_EXCEPTION
+ static void
+ handle_unaligned_user (struct pt_regs *regs)
+ {
+ struct task_struct *tsk = current;
+ siginfo_t info;
+
+ if (user_mode(regs)) { /* Sanity check */
+
+ tsk->thread.bad_vaddr = regs->excvaddr;
+ tsk->thread.error_code = -3; /* unaligned access, load or store */
+ #if 1
+ printk("handle_unaligned_user(): sending SIGSEGV to %s (pid=%d)"
+ " for illegal access\n"
+ "(load or store) to %08x (pc == %08x, ra == %08x)\n",
+ tsk->comm,
+ tsk->pid,
+ regs->excvaddr,
+ regs->pc,
+ /* XTFIXME: Shouldn't the 0xC0000000 value come from the CHAL? */
+ (regs->aregs[0] & 0x3FFFFFFF) | (regs->pc & 0xC0000000) );
+ #endif
+ info.si_signo = SIGSEGV;
+ info.si_errno = 0;
+ info.si_code = SEGV_ACCERR;
+ info.si_addr = (void *) regs->excvaddr;
+ force_sig_info(SIGSEGV, &info, tsk);
+ }
+ else {
+
+ /* Control should not get here, because we register a
+ * first-level handler in traps.c to catch all
+ * unaligned kernel accesses. This code is here,
+ * however, to assist in debugging. Just "unregister"
+ * the kernel handler, and you'll get this debugging
+ * information. */
+
+ printk ("handle_unaligned_user(): tsk happened to be %s\n"
+ " access addr=0x%.8x, pc=%08x, ra=%08x\n",
+ tsk->comm, regs->excvaddr, regs->pc,
+ (regs->aregs[0] & 0x3FFFFFFF) | (regs->pc & 0xC0000000) );
+ panic ("Giving up on unaligned kernel access\n");
+ }
+ }
+ #endif
+
static void
do_debug(struct pt_regs *regs)
{
+ #if 0
int i;
+ #endif
#if 0
***************
*** 365,368 ****
--- 414,422 ----
set_c_except_handler(i, do_unhandled);
}
+
+ #if XCHAL_UNALIGNED_LOAD_EXCEPTION
+ set_except_vector(EXC_CODE_KERNEL + XCHAL_EXCCAUSE_LOAD_STORE_ALIGNMENT, handle_unaligned_kernel);
+ set_c_except_handler (XCHAL_EXCCAUSE_LOAD_STORE_ALIGNMENT, handle_unaligned_user);
+ #endif
/* Now change the one for system calls. */
|
