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From: <joe...@us...> - 2002-10-23 20:53:25
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_le
In directory usw-pr-cvs1:/tmp/cvs-serv28395/include/asm-xtensa/xtensa/config-linux_le
Added Files:
core.h defs.h specreg.h system.h
Log Message:
Add processor config information for two additional configs: linux_le and linux_test. Also make the selection of processor configuration selectable at kernel-configuration time. linux_be is the default.
--- NEW FILE: core.h ---
/*
* xtensa/config/core.h -- HAL definitions that are dependent on CORE configuration
*
* This header file is sometimes referred to as the "compile-time HAL" or CHAL.
* It was generated for a specific Xtensa processor configuration.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* It is perfectly normal, however, for the HAL source itself to include this file.
*/
/*
* Customer ID=40; Build=10966; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef XTENSA_CONFIG_CORE_H
#define XTENSA_CONFIG_CORE_H
#include <xtensa/hal.h>
/*----------------------------------------------------------------------
GENERAL
----------------------------------------------------------------------*/
/*
* Separators for macros that expand into arrays.
* These can be predefined by files that #include this one,
* when different separators are required.
*/
/* Element separator for macros that expand into 1-dimensional arrays: */
#ifndef XCHAL_SEP
#define XCHAL_SEP ,
#endif
/* Array separator for macros that expand into 2-dimensional arrays: */
#ifndef XCHAL_SEP2
#define XCHAL_SEP2 },{
#endif
/*----------------------------------------------------------------------
ENDIANNESS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_BE 0
#define XCHAL_HAVE_LE 1
#define XCHAL_MEMORY_ORDER XTHAL_LITTLEENDIAN
/*----------------------------------------------------------------------
REGISTER WINDOWS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_WINDOWED 1 /* 1 if windowed registers option configured, 0 otherwise */
#define XCHAL_NUM_AREGS 64 /* number of physical address regs */
#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
/*----------------------------------------------------------------------
INTERRUPTS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_INTERRUPTS 1 /* 1 if interrupt option configured, 0 otherwise */
#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS 1 /* 1 if high-level interrupt option configured, 0 otherwise */
#define XCHAL_HAVE_NMI 0 /* 1 if NMI option configured, 0 otherwise */
#define XCHAL_NUM_INTERRUPTS 17 /* number of interrupts */
#define XCHAL_NUM_EXTINTERRUPTS 10 /* number of external interrupts */
#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels (not including level zero!) */
/* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL0_MASK 0x00000000
#define XCHAL_INTLEVEL1_MASK 0x000064F9
#define XCHAL_INTLEVEL2_MASK 0x00008902
#define XCHAL_INTLEVEL3_MASK 0x00011204
#define XCHAL_INTLEVEL4_MASK 0x00000000
#define XCHAL_INTLEVEL5_MASK 0x00000000
#define XCHAL_INTLEVEL6_MASK 0x00000000
#define XCHAL_INTLEVEL7_MASK 0x00000000
#define XCHAL_INTLEVEL8_MASK 0x00000000
#define XCHAL_INTLEVEL9_MASK 0x00000000
#define XCHAL_INTLEVEL10_MASK 0x00000000
#define XCHAL_INTLEVEL11_MASK 0x00000000
#define XCHAL_INTLEVEL12_MASK 0x00000000
#define XCHAL_INTLEVEL13_MASK 0x00000000
#define XCHAL_INTLEVEL14_MASK 0x00000000
#define XCHAL_INTLEVEL15_MASK 0x00000000
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INTLEVEL_MASKS 0x00000000 XCHAL_SEP \
0x000064F9 XCHAL_SEP \
0x00008902 XCHAL_SEP \
0x00011204 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000
/* Masks of interrupts at each range 1..n of interrupt levels: */
#define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000064F9
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x0000EDFB
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL8_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL9_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL10_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL11_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL12_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL13_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL14_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL15_ANDBELOW_MASK 0x0001FFFF
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INTLEVEL_ANDBELOW_MASKS 0x00000000 XCHAL_SEP \
0x000064F9 XCHAL_SEP \
0x0000EDFB XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF
/* Level of each interrupt: */
#define XCHAL_INT0_LEVEL 1
#define XCHAL_INT1_LEVEL 2
#define XCHAL_INT2_LEVEL 3
#define XCHAL_INT3_LEVEL 1
#define XCHAL_INT4_LEVEL 1
#define XCHAL_INT5_LEVEL 1
#define XCHAL_INT6_LEVEL 1
#define XCHAL_INT7_LEVEL 1
#define XCHAL_INT8_LEVEL 2
#define XCHAL_INT9_LEVEL 3
#define XCHAL_INT10_LEVEL 1
#define XCHAL_INT11_LEVEL 2
#define XCHAL_INT12_LEVEL 3
#define XCHAL_INT13_LEVEL 1
#define XCHAL_INT14_LEVEL 1
#define XCHAL_INT15_LEVEL 2
#define XCHAL_INT16_LEVEL 3
#define XCHAL_INT17_LEVEL 0
#define XCHAL_INT18_LEVEL 0
#define XCHAL_INT19_LEVEL 0
#define XCHAL_INT20_LEVEL 0
#define XCHAL_INT21_LEVEL 0
#define XCHAL_INT22_LEVEL 0
#define XCHAL_INT23_LEVEL 0
#define XCHAL_INT24_LEVEL 0
#define XCHAL_INT25_LEVEL 0
#define XCHAL_INT26_LEVEL 0
#define XCHAL_INT27_LEVEL 0
#define XCHAL_INT28_LEVEL 0
#define XCHAL_INT29_LEVEL 0
#define XCHAL_INT30_LEVEL 0
#define XCHAL_INT31_LEVEL 0
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INT_LEVELS 1 XCHAL_SEP \
2 XCHAL_SEP \
3 XCHAL_SEP \
1 XCHAL_SEP \
1 XCHAL_SEP \
1 XCHAL_SEP \
1 XCHAL_SEP \
1 XCHAL_SEP \
2 XCHAL_SEP \
3 XCHAL_SEP \
1 XCHAL_SEP \
2 XCHAL_SEP \
3 XCHAL_SEP \
1 XCHAL_SEP \
1 XCHAL_SEP \
2 XCHAL_SEP \
3 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0
/* Type of each interrupt: */
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INT_TYPES XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_EDGE XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_EDGE XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_EDGE XCHAL_SEP \
XTHAL_INTTYPE_TIMER XCHAL_SEP \
XTHAL_INTTYPE_TIMER XCHAL_SEP \
XTHAL_INTTYPE_TIMER XCHAL_SEP \
XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED
/* Masks of interrupts for each type of interrupt: */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFE0000
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0001E000
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000380
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000007F
#define XCHAL_INTTYPE_MASK_TIMER 0x00001C00
#define XCHAL_INTTYPE_MASK_NMI 0x00000000
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INTTYPE_MASKS 0xFFFE0000 XCHAL_SEP \
0x0001E000 XCHAL_SEP \
0x00000380 XCHAL_SEP \
0x0000007F XCHAL_SEP \
0x00001C00 XCHAL_SEP \
0x00000000
/* Interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3), -1 if unassigned */
#define XCHAL_TIMER0_INTERRUPT 10
#define XCHAL_TIMER1_INTERRUPT 11
#define XCHAL_TIMER2_INTERRUPT 12
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_TIMER_INTERRUPTS 10 XCHAL_SEP \
11 XCHAL_SEP \
12 XCHAL_SEP \
XTHAL_TIMER_UNCONFIGURED
/* Indexing macros: */
#define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK
#define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */
#define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
#define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */
#define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL
#define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */
#define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE
#define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */
#define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT
#define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */
/* External interrupt vectors/levels: */
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 2) */
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 3) */
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */
#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */
#define XCHAL_EXTINT8_NUM 8 /* (intlevel 2) */
#define XCHAL_EXTINT9_NUM 9 /* (intlevel 3) */
/* Corresponding interrupt masks: */
#define XCHAL_EXTINT0_MASK 0x00000001
#define XCHAL_EXTINT1_MASK 0x00000002
#define XCHAL_EXTINT2_MASK 0x00000004
#define XCHAL_EXTINT3_MASK 0x00000008
#define XCHAL_EXTINT4_MASK 0x00000010
#define XCHAL_EXTINT5_MASK 0x00000020
#define XCHAL_EXTINT6_MASK 0x00000040
#define XCHAL_EXTINT7_MASK 0x00000080
#define XCHAL_EXTINT8_MASK 0x00000100
#define XCHAL_EXTINT9_MASK 0x00000200
/* Core config interrupt levels mapped to each external interrupt: */
#define XCHAL_EXTINT0_LEVEL 1 /* (int number 0) */
#define XCHAL_EXTINT1_LEVEL 2 /* (int number 1) */
#define XCHAL_EXTINT2_LEVEL 3 /* (int number 2) */
#define XCHAL_EXTINT3_LEVEL 1 /* (int number 3) */
#define XCHAL_EXTINT4_LEVEL 1 /* (int number 4) */
#define XCHAL_EXTINT5_LEVEL 1 /* (int number 5) */
#define XCHAL_EXTINT6_LEVEL 1 /* (int number 6) */
#define XCHAL_EXTINT7_LEVEL 1 /* (int number 7) */
#define XCHAL_EXTINT8_LEVEL 2 /* (int number 8) */
#define XCHAL_EXTINT9_LEVEL 3 /* (int number 9) */
/*----------------------------------------------------------------------
EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_EXCEPTIONS 1 /* 1 if exception option configured, 0 otherwise */
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture number: 1 for XEA1 (old), 2 for XEA2 (new) */
#define XCHAL_HAVE_XEA1 0 /* 1 if XEA1, 0 otherwise */
#define XCHAL_HAVE_XEA2 1 /* 1 if XEA2, 0 otherwise */
/* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */
#define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */
#define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */
#define XCHAL_RESET_VECTOR_VADDR 0xFE000020
#define XCHAL_RESET_VECTOR_PADDR 0xFE000020
#define XCHAL_USER_VECTOR_VADDR 0xD0000220
#define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR /* for backward compatibility */
#define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR /* for backward compatibility */
#define XCHAL_USER_VECTOR_PADDR 0x00000220
#define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR /* for backward compatibility */
#define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR /* for backward compatibility */
#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000200
#define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
#define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
#define XCHAL_KERNERL_VECTOR_PADDR 0x00000200
#define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
#define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD0000290
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x00000290
#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000
#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000240
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000240
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xD0000250
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x00000250
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xFE000520
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xFE000520
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
/* Indexing macros: */
#define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR
#define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */
/*
* Level-1 Exception Causes:
*/
#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction (IllegalInstruction) */
#define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call (SystemCall) */
#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error (InstructionFetchError) */
#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error (LoadStoreError) */
#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt (Level1Interrupt) */
#define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (Alloca) */
#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero (IntegerDivideByZero) */
#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation (Speculation) */
#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction (Privileged) */
#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception (ITlbMiss) */
#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception (ITlbMultihit) */
#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception (ITlbPrivilege) */
#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception (ITlbSizeRestriction) */
#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception (FetchCacheAttribute) */
#define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception (DTlbMiss) */
#define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception (DTlbMultihit) */
#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception (DTlbPrivilege) */
#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception (DTlbSizeRestriction) */
#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception (LoadCacheAttribute) */
#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception (StoreCacheAttribute) */
#define XCHAL_EXCCAUSE_FLOATING_POINT 40 /* Floating Point Exception (FloatingPoint) */
/*----------------------------------------------------------------------
TIMERS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_CCOUNT 1 /* 1 if have CCOUNT, 0 otherwise */
/*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
/*----------------------------------------------------------------------
DEBUG
----------------------------------------------------------------------*/
#define XCHAL_HAVE_DEBUG 1 /* 1 if debug option configured, 0 otherwise */
#define XCHAL_HAVE_OCD 1 /* 1 if OnChipDebug option configured, 0 otherwise */
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */
/*DebugExternalInterrupt 0 0|1*/
/*DebugUseDIRArray 0 0|1*/
/*----------------------------------------------------------------------
COPROCESSORS and EXTRA STATE
----------------------------------------------------------------------*/
#define XCHAL_HAVE_CP 0 /* 1 if coprocessor option configured (CPENABLE present) */
#define XCHAL_CP_NUM 0 /* number of coprocessors */
#define XCHAL_CP_MAX 0 /* max coprocessor id plus one (0 if none) */
#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one (per cfg) */
#define XCHAL_CP_MASK 0x00 /* bitmask of coprocessors by id */
/* Space for coprocessors' state save areas: */
#define XCHAL_CP0_SA_SIZE 0
#define XCHAL_CP1_SA_SIZE 0
#define XCHAL_CP2_SA_SIZE 0
#define XCHAL_CP3_SA_SIZE 0
#define XCHAL_CP4_SA_SIZE 0
#define XCHAL_CP5_SA_SIZE 0
#define XCHAL_CP6_SA_SIZE 0
#define XCHAL_CP7_SA_SIZE 0
/* Minimum required alignments of CP state save areas: */
#define XCHAL_CP0_SA_ALIGN 1
#define XCHAL_CP1_SA_ALIGN 1
#define XCHAL_CP2_SA_ALIGN 1
#define XCHAL_CP3_SA_ALIGN 1
#define XCHAL_CP4_SA_ALIGN 1
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP6_SA_ALIGN 1
#define XCHAL_CP7_SA_ALIGN 1
/* Indexing macros: */
#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
/* Space for "extra" state (user special registers and non-cp TIE) save area: */
#define XCHAL_EXTRA_SA_SIZE 0
#define XCHAL_EXTRA_SA_ALIGN 1
/* Total save area size (extra + all coprocessors) */
/* (not useful until xthal_{save,restore}_all_extra() is implemented, */
/* but included for Tor2 beta; doesn't account for alignment!): */
#define XCHAL_CPEXTRA_SA_SIZE_TOR2 0 /* Tor2Beta temporary definition -- do not use */
/* Combined required alignment for all CP and EXTRA state save areas */
/* (does not include required alignment for any base config registers): */
#define XCHAL_CPEXTRA_SA_ALIGN 1
/* ... */
#ifdef _ASMLANGUAGE
/*
* Assembly-language specific definitions (assembly macros, etc.).
*/
#include <xtensa/config/specreg.h>
/********************
* Macros to save and restore the non-coprocessor TIE portion of EXTRA state.
*/
/* (none) */
/********************
* Macros to create functions that save and restore all EXTRA (non-coprocessor) state
* (does not include zero-overhead loop registers and non-optional registers).
*/
/*
* Macro that expands to the body of a function that
* stores the extra (non-coprocessor) optional/custom state.
* Entry: a2 = ptr to save area in which to save extra state
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_extra_store_funcbody
.endm
/*
* Macro that expands to the body of a function that
* loads the extra (non-coprocessor) optional/custom state.
* Entry: a2 = ptr to save area from which to restore extra state
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_extra_load_funcbody
.endm
/********************
* Macros to save and restore the state of each TIE coprocessor.
*/
/********************
* Macros to create functions that save and restore the state of *any* TIE coprocessor.
*/
/*
* Macro that expands to the body of a function
* that stores the selected coprocessor's state (registers etc).
* Entry: a2 = ptr to save area in which to save cp state
* a3 = coprocessor number
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_cpi_store_funcbody
.endm
/*
* Macro that expands to the body of a function
* that loads the selected coprocessor's state (registers etc).
* Entry: a2 = ptr to save area from which to restore cp state
* a3 = coprocessor number
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_cpi_load_funcbody
.endm
#endif /*_ASMLANGUAGE*/
/*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/
#define XCHAL_NUM_INSTROM 0 /* number of core instruction ROMs configured */
#define XCHAL_NUM_INSTRAM 1 /* number of core instruction RAMs configured */
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs configured */
#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs configured */
#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports configured */
#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */
#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */
#define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */
#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */
/* Instruction RAM 0: */
#define XCHAL_INSTRAM0_VADDR 0xCFFFF000
#define XCHAL_INSTRAM0_PADDR 0xCFFFF000
#define XCHAL_INSTRAM0_SIZE 4096
#define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */
#define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */
#define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */
/* Data RAM 0: */
#define XCHAL_DATARAM0_VADDR 0xCFFFE000
#define XCHAL_DATARAM0_PADDR 0xCFFFE000
#define XCHAL_DATARAM0_SIZE 2048
#define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */
#define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */
#define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */
/* XLMI Port 0: */
#define XCHAL_XLMI0_VADDR 0xCFF80000
#define XCHAL_XLMI0_PADDR 0xCFF80000
#define XCHAL_XLMI0_SIZE 262144
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
/* Size of the cache lines in log2(bytes): */
#define XCHAL_ICACHE_LINEWIDTH 4
#define XCHAL_DCACHE_LINEWIDTH 4
/* Size of the cache lines in bytes: */
#define XCHAL_ICACHE_LINESIZE 16
#define XCHAL_DCACHE_LINESIZE 16
/* Max for both I-cache and D-cache (used for general alignment): */
#define XCHAL_CACHE_LINEWIDTH_MAX 4
#define XCHAL_CACHE_LINESIZE_MAX 16
/* Number of cache sets in log2(lines per way): */
#define XCHAL_ICACHE_SETWIDTH 8
#define XCHAL_DCACHE_SETWIDTH 8
/* Max for both I-cache and D-cache (used for general cache-coherency page alignment): */
#define XCHAL_CACHE_SETWIDTH_MAX 8
#define XCHAL_CACHE_SETSIZE_MAX 256
/* Cache set associativity (number of ways): */
#define XCHAL_ICACHE_WAYS 2
#define XCHAL_DCACHE_WAYS 2
/* Size of the caches in bytes (ways * 2^(linewidth + setwidth)): */
#define XCHAL_ICACHE_SIZE 8192
#define XCHAL_DCACHE_SIZE 8192
/* Cache features: */
#define XCHAL_DCACHE_IS_WRITEBACK 0
/* Whether cache locking feature is available: */
#define XCHAL_ICACHE_LINE_LOCKABLE 0
#define XCHAL_DCACHE_LINE_LOCKABLE 0
/* Number of (encoded) cache attribute bits: */
#define XCHAL_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
/* (The number of access mode bits (decoded cache attribute bits) is defined by the architecture; see xtensa/hal.h?) */
/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_CACHED XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_CACHED XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_CACHED XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_CACHED XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION
#define XCHAL_LCA_LIST XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_CACHED XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_CACHED XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_NACACHED XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_NACACHED XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_ISOLATE XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_CACHED
#define XCHAL_SCA_LIST XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_WRITETHRU XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_WRITETHRU XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_ISOLATE XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_WRITETHRU
/* Test:
read/only: 0 + 1 + 2 + 4 + 5 + 6 + 8 + 9 + 10 + 12 + 14
read/only: 0 + 1 + 2 + 4 + 5 + 6 + 8 + 9 + 10 + 12 + 14
all: 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15
fault: 0 + 2 + 4 + 6 + 8 + 10 + 12 + 14
r/w/x cached:
r/w/x dcached:
I-bypass: 1 + 3
load guard bit set: 1 + 3
load guard bit clr: 0 + 2 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15
hit-cache r/w/x: 7 + 11
fams: 5
fams: 0 / 6 / 18 / 1 / 2
fams: Bypass / Isolate / Cached / Exception / NACached
*/
/* MMU okay: yes */
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
#define XCHAL_HAVE_CACHEATTR 0 /* 1 if CACHEATTR register present, 0 if TLBs present instead */
#define XCHAL_HAVE_TLBS 1 /* 1 if TLBs present, 0 if CACHEATTR present instead */
#define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS /* (DEPRECATED; use XCHAL_HAVE_TLBS instead; will be removed in future release) */
#define XCHAL_HAVE_SPANNING_WAY 0 /* 1 if single way maps entire virtual address space in I+D */
#define XCHAL_HAVE_IDENTITY_MAP 0 /* 1 if virtual addr == physical addr always, 0 otherwise */
#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* 1 if have MMU that mimics a CACHEATTR config (CaMMU) */
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* 1 if have MMU that mimics a CACHEATTR config, but with translation (CaXltMMU) */
#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs (address space IDs) */
#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
#define XCHAL_MMU_ASID_KERNEL 1 /* ASID value indicating kernel (ring 0) address space */
#define XCHAL_MMU_RINGS 4 /* number of rings supported (1..4) */
#define XCHAL_MMU_RING_BITS 2 /* number of bits needed to hold ring number */
#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 12 /* max page size in a PTE structure */
#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 /* min page size in a PTE structure */
/* Instruction TLB: */
#define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */
#define XCHAL_ITLB_WAYS 7 /* number of ways */
#define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */
/* Data TLB: */
#define XCHAL_DTLB_WAY_BITS 4 /* number of bits holding the ways */
#define XCHAL_DTLB_WAYS 10 /* number of ways */
#define XCHAL_DTLB_ARF_WAYS 4 /* number of auto-refill ways */
/* ... */
/*
* Determine whether we have a full MMU (with Page Table and Protection)
* usable for an MMU-based OS:
*/
#if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2
# define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */
#else
# define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */
#endif
/*
* For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings:
*/
#if XCHAL_HAVE_PTP_MMU
#define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */
#define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */
#define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */
#define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */
#define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */
#define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */
#define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */
#define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */
#define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */
#define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */
#define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */
#define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */
#define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */
#define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */
/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */
#endif
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* number of write buffer entries */
#define XCHAL_BUILD_UNIQUE_ID 0x00002AD6 /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
#define XCHAL_HW_CONFIGID0 0xC10FD3FE /* config ID reg 0 value (upper 32 of 64 bits) */
#define XCHAL_HW_CONFIGID1 0x00402AD6 /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
#define XCHAL_HW_RELEASE_MINOR 0 /* minor release of targeted hardware */
#define XCHAL_HW_RELEASE_NAME "T1050.0" /* full release name of targeted hardware */
#define XTHAL_HW_REL_T1050 1
#define XTHAL_HW_REL_T1050_0 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
/*
* Miscellaneous special register fields:
*/
/* DBREAKC (special register number 160): */
#define XCHAL_DBREAKC_VALIDMASK 0xC000003F /* bits of DBREAKC that are defined */
/* MASK field: */
#define XCHAL_DBREAKC_MASK_BITS 6 /* number of bits in MASK field */
#define XCHAL_DBREAKC_MASK_NUM 64 /* max number of possible causes (2^bits) */
#define XCHAL_DBREAKC_MASK_SHIFT 0 /* position of MASK bits in DBREAKC, starting from lsbit */
#define XCHAL_DBREAKC_MASK_MASK 0x0000003F /* mask of bits in MASK field of DBREAKC */
/* LOADBREAK field: */
#define XCHAL_DBREAKC_LOADBREAK_BITS 1 /* number of bits in LOADBREAK field */
#define XCHAL_DBREAKC_LOADBREAK_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_DBREAKC_LOADBREAK_SHIFT 30 /* position of LOADBREAK bits in DBREAKC, starting from lsbit */
#define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000 /* mask of bits in LOADBREAK field of DBREAKC */
/* STOREBREAK field: */
#define XCHAL_DBREAKC_STOREBREAK_BITS 1 /* number of bits in STOREBREAK field */
#define XCHAL_DBREAKC_STOREBREAK_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_DBREAKC_STOREBREAK_SHIFT 31 /* position of STOREBREAK bits in DBREAKC, starting from lsbit */
#define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000 /* mask of bits in STOREBREAK field of DBREAKC */
/* PS (special register number 230): */
#define XCHAL_PS_VALIDMASK 0x00070FFF /* bits of PS that are defined */
/* INTLEVEL field: */
#define XCHAL_PS_INTLEVEL_BITS 4 /* number of bits in INTLEVEL field */
#define XCHAL_PS_INTLEVEL_NUM 16 /* max number of possible causes (2^bits) */
#define XCHAL_PS_INTLEVEL_SHIFT 0 /* position of INTLEVEL bits in PS, starting from lsbit */
#define XCHAL_PS_INTLEVEL_MASK 0x0000000F /* mask of bits in INTLEVEL field of PS */
/* EXCM field: */
#define XCHAL_PS_EXCM_BITS 1 /* number of bits in EXCM field */
#define XCHAL_PS_EXCM_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_PS_EXCM_SHIFT 4 /* position of EXCM bits in PS, starting from lsbit */
#define XCHAL_PS_EXCM_MASK 0x00000010 /* mask of bits in EXCM field of PS */
/* PROGSTACK field: */
#define XCHAL_PS_PROGSTACK_BITS 1 /* number of bits in PROGSTACK field */
#define XCHAL_PS_PROGSTACK_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_PS_PROGSTACK_SHIFT 5 /* position of PROGSTACK bits in PS, starting from lsbit */
#define XCHAL_PS_PROGSTACK_MASK 0x00000020 /* mask of bits in PROGSTACK field of PS */
/* RING field: */
#define XCHAL_PS_RING_BITS 2 /* number of bits in RING field */
#define XCHAL_PS_RING_NUM 4 /* max number of possible causes (2^bits) */
#define XCHAL_PS_RING_SHIFT 6 /* position of RING bits in PS, starting from lsbit */
#define XCHAL_PS_RING_MASK 0x000000C0 /* mask of bits in RING field of PS */
/* OWB field: */
#define XCHAL_PS_OWB_BITS 4 /* number of bits in OWB field */
#define XCHAL_PS_OWB_NUM 16 /* max number of possible causes (2^bits) */
#define XCHAL_PS_OWB_SHIFT 8 /* position of OWB bits in PS, starting from lsbit */
#define XCHAL_PS_OWB_MASK 0x00000F00 /* mask of bits in OWB field of PS */
/* CALLINC field: */
#define XCHAL_PS_CALLINC_BITS 2 /* number of bits in CALLINC field */
#define XCHAL_PS_CALLINC_NUM 4 /* max number of possible causes (2^bits) */
#define XCHAL_PS_CALLINC_SHIFT 16 /* position of CALLINC bits in PS, starting from lsbit */
#define XCHAL_PS_CALLINC_MASK 0x00030000 /* mask of bits in CALLINC field of PS */
/* WOE field: */
#define XCHAL_PS_WOE_BITS 1 /* number of bits in WOE field */
#define XCHAL_PS_WOE_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_PS_WOE_SHIFT 18 /* position of WOE bits in PS, starting from lsbit */
#define XCHAL_PS_WOE_MASK 0x00040000 /* mask of bits in WOE field of PS */
/* EXCCAUSE (special register number 232): */
#define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F /* bits of EXCCAUSE that are defined */
/* EXCCAUSE field: */
#define XCHAL_EXCCAUSE_BITS 6 /* number of bits in EXCCAUSE register */
#define XCHAL_EXCCAUSE_NUM 64 /* max number of possible causes (2^bits) */
#define XCHAL_EXCCAUSE_SHIFT 0 /* position of EXCCAUSE bits in register, starting from lsbit */
#define XCHAL_EXCCAUSE_MASK 0x0000003F /* mask of bits in EXCCAUSE register */
/* DEBUGCAUSE (special register number 233): */
#define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F /* bits of DEBUGCAUSE that are defined */
/* ICOUNT field: */
#define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1 /* number of bits in ICOUNT field */
#define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0 /* position of ICOUNT bits in DEBUGCAUSE, starting from lsbit */
#define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001 /* mask of bits in ICOUNT field of DEBUGCAUSE */
/* IBREAK field: */
#define XCHAL_DEBUGCAUSE_IBREAK_BITS 1 /* number of bits in IBREAK field */
#define XCHAL_DEBUGCAUSE_IBREAK_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1 /* position of IBREAK bits in DEBUGCAUSE, starting from lsbit */
#define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002 /* mask of bits in IBREAK field of DEBUGCAUSE */
/* DBREAK field: */
#define XCHAL_DEBUGCAUSE_DBREAK_BITS 1 /* number of bits in DBREAK field */
#define XCHAL_DEBUGCAUSE_DBREAK_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2 /* position of DBREAK bits in DEBUGCAUSE, starting from lsbit */
#define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004 /* mask of bits in DBREAK field of DEBUGCAUSE */
/* BREAK field: */
#define XCHAL_DEBUGCAUSE_BREAK_BITS 1 /* number of bits in BREAK field */
#define XCHAL_DEBUGCAUSE_BREAK_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3 /* position of BREAK bits in DEBUGCAUSE, starting from lsbit */
#define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008 /* mask of bits in BREAK field of DEBUGCAUSE */
/* BREAKN field: */
#define XCHAL_DEBUGCAUSE_BREAKN_BITS 1 /* number of bits in BREAKN field */
#define XCHAL_DEBUGCAUSE_BREAKN_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4 /* position of BREAKN bits in DEBUGCAUSE, starting from lsbit */
#define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010 /* mask of bits in BREAKN field of DEBUGCAUSE */
/* DEBUGINT field: */
#define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1 /* number of bits in DEBUGINT field */
#define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5 /* position of DEBUGINT bits in DEBUGCAUSE, starting from lsbit */
#define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020 /* mask of bits in DEBUGINT field of DEBUGCAUSE */
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#define XCHAL_HAVE_DENSITY 1 /* 1 if density option configured, 0 otherwise */
#define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
#define XCHAL_HAVE_LOOPS 1 /* 1 if zero-overhead loops option configured, 0 otherwise */
/* Misc instructions: */
#define XCHAL_HAVE_NSA 1 /* 1 if NSA/NSAU instructions option configured, 0 otherwise */
#define XCHAL_HAVE_MINMAX 0 /* 1 if MIN/MAX instructions option configured, 0 otherwise */
#define XCHAL_HAVE_SEXT 0 /* 1 if sign-extend instruction option configured, 0 otherwise */
#define XCHAL_HAVE_CLAMPS 0 /* 1 if CLAMPS instruction option configured, 0 otherwise */
#define XCHAL_HAVE_MAC16 0 /* 1 if MAC16 option configured, 0 otherwise */
#define XCHAL_HAVE_MUL16 0 /* 1 if 16-bit integer multiply option configured, 0 otherwise */
#define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
#define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
/*#define XCHAL_HAVE_POPC 0*/ /* 1 if CRC instruction option configured, 0 otherwise */
/*#define XCHAL_HAVE_CRC 0*/ /* 1 if POPC instruction option configured, 0 otherwise */
#define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
#define XCHAL_HAVE_SPECULATION 0 /* 1 if speculation option configured, 0 otherwise */
/*#define XCHAL_HAVE_MP_SYNC 0*/ /* 1 if multiprocessor sync. option configured, 0 otherwise */
#define XCHAL_HAVE_PRID 1 /* 1 if processor ID register configured, 0 otherwise */
#define XCHAL_NUM_MISC_REGS 2 /* number of miscellaneous registers (0..4) */
/*----------------------------------------------------------------------
DERIVED
----------------------------------------------------------------------*/
#if XCHAL_HAVE_BE
#define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */
#define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */
#define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */
#else
#define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */
#define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */
#define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */
#endif
/* Belongs in xtensa/hal.h: */
#define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */
#endif /*XTENSA_CONFIG_CORE_H*/
--- NEW FILE: defs.h ---
/* Definitions for Xtensa instructions, types, and protos. */
/*
* Customer ID=40; Build=10966; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_BASE_HEADER
#define _XTENSA_BASE_HEADER
#ifdef __XTENSA__
#if defined(__GNUC__) && !defined(__XCC__)
#define L8UI_ASM(arr, ars, imm) { \
__asm__ volatile("l8ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L8UI(ars, imm) \
({ \
unsigned char _arr; \
const unsigned char *_ars = ars; \
L8UI_ASM(_arr, _ars, imm); \
_arr; \
})
#define L16UI_ASM(arr, ars, imm) { \
__asm__ volatile("l16ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L16UI(ars, imm) \
({ \
unsigned short _arr; \
const unsigned short *_ars = ars; \
L16UI_ASM(_arr, _ars, imm); \
_arr; \
})
#define L16SI_ASM(arr, ars, imm) {\
__asm__ volatile("l16si %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L16SI(ars, imm) \
({ \
signed short _arr; \
const signed short *_ars = ars; \
L16SI_ASM(_arr, _ars, imm); \
_arr; \
})
#define L32I_ASM(arr, ars, imm) { \
__asm__ volatile("l32i %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L32I(ars, imm) \
({ \
unsigned _arr; \
const unsigned *_ars = ars; \
L32I_ASM(_arr, _ars, imm); \
_arr; \
})
#define S8I_ASM(arr, ars, imm) {\
__asm__ volatile("s8i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
}
#define XT_S8I(arr, ars, imm) \
({ \
signed char _arr = arr; \
const signed char *_ars = ars; \
S8I_ASM(_arr, _ars, imm); \
})
#define S16I_ASM(arr, ars, imm) {\
__asm__ volatile("s16i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
}
#define XT_S16I(arr, ars, imm) \
({ \
signed short _arr = arr; \
const signed short *_ars = ars; \
S16I_ASM(_arr, _ars, imm); \
})
#define S32I_ASM(arr, ars, imm) { \
__asm__ volatile("s32i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
}
#define XT_S32I(arr, ars, imm) \
({ \
signed int _arr = arr; \
const signed int *_ars = ars; \
S32I_ASM(_arr, _ars, imm); \
})
#define ADDI_ASM(art, ars, imm) {\
__asm__ ("addi %0, %1, %2" : "=a" (art) : "a" (ars), "i" (imm)); \
}
#define XT_ADDI(ars, imm) \
({ \
unsigned _art; \
unsigned _ars = ars; \
ADDI_ASM(_art, _ars, imm); \
_art; \
})
#define ABS_ASM(arr, art) {\
__asm__ ("abs %0, %1" : "=a" (arr) : "a" (art)); \
}
#define XT_ABS(art) \
({ \
unsigned _arr; \
signed _art = art; \
ABS_ASM(_arr, _art); \
_arr; \
})
/* Note: In the following macros that reference SAR, the magic "state"
register is used to capture the dependency on SAR. This is because
SAR is a 5-bit register and thus there are no C types that can be
used to represent it. It doesn't appear that the SAR register is
even relevant to GCC, but it is marked as "clobbered" just in
case. */
#define SRC_ASM(arr, ars, art) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("src %0, %1, %2" \
: "=a" (arr) : "a" (ars), "a" (art), "t" (_xt_sar)); \
}
#define XT_SRC(ars, art) \
({ \
unsigned _arr; \
unsigned _ars = ars; \
unsigned _art = art; \
SRC_ASM(_arr, _ars, _art); \
_arr; \
})
#define SSR_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssr %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSR(ars) \
({ \
unsigned _ars = ars; \
SSR_ASM(_ars); \
})
#define SSL_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssl %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSL(ars) \
({ \
unsigned _ars = ars; \
SSL_ASM(_ars); \
})
#define SSA8B_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssa8b %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSA8B(ars) \
({ \
unsigned _ars = ars; \
SSA8B_ASM(_ars); \
})
#define SSA8L_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssa8l %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSA8L(ars) \
({ \
unsigned _ars = ars; \
SSA8L_ASM(_ars); \
})
#define SSAI_ASM(imm) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssai %1" : "=t" (_xt_sar) : "i" (imm) : "sar"); \
}
#define XT_SSAI(imm) \
({ \
SSAI_ASM(imm); \
})
#define NSA_ASM(arr, ars) {\
__asm__ ("nsa %0, %1" : "=a" (arr) : "a" (ars)); \
}
#define XT_NSA(ars) \
({ \
unsigned _arr; \
int _ars = ars; \
NSA_ASM(_arr, _ars); \
_arr; \
})
#define NSAU_ASM(arr, ars) {\
__asm__ ("nsau %0, %1" : "=a" (arr) : "a" (ars)); \
}
#define XT_NSAU(ars) \
({ \
unsigned _arr; \
unsigned _ars = ars; \
NSAU_ASM(_arr, _ars); \
_arr; \
})
#endif /* __GNUC__ && !__XCC__ */
#ifdef __XCC__
/* Core load/store instructions */
extern unsigned char _TIE_L8UI(const unsigned char * ars, immediate imm);
extern unsigned short _TIE_L16UI(const unsigned short * ars, immediate imm);
extern signed short _TIE_L16SI(const signed short * ars, immediate imm);
extern unsigned _TIE_L32I(const unsigned * ars, immediate imm);
extern void _TIE_S8I(unsigned char arr, unsigned char * ars, immediate imm);
extern void _TIE_S16I(unsigned short arr, unsigned short * ars, immediate imm);
extern void _TIE_S32I(unsigned arr, unsigned * ars, immediate imm);
#define XT_L8UI _TIE_L8UI
#define XT_L16UI _TIE_L16UI
#define XT_L16SI _TIE_L16SI
#define XT_L32I _TIE_L32I
#define XT_S8I _TIE_S8I
#define XT_S16I _TIE_S16I
#define XT_S32I _TIE_S32I
/* Add-immediate instruction */
extern unsigned _TIE_ADDI(unsigned ars, immediate imm);
#define XT_ADDI _TIE_ADDI
/* Absolute value instruction */
extern unsigned _TIE_ABS(int art);
#define XT_ABS _TIE_ABS
/* funnel shift instructions */
extern unsigned _TIE_SRC(unsigned ars, unsigned art);
#define XT_SRC _TIE_SRC
extern void _TIE_SSR(unsigned ars);
#define XT_SSR _TIE_SSR
extern void _TIE_SSL(unsigned ars);
#define XT_SSL _TIE_SSL
extern void _TIE_SSA8B(unsigned ars);
#define XT_SSA8B _TIE_SSA8B
extern void _TIE_SSA8L(unsigned ars);
#define XT_SSA8L _TIE_SSA8L
extern void _TIE_SSAI(immediate imm);
#define XT_SSAI _TIE_SSAI
/* Miscellaneous instructions */
extern unsigned _TIE_NSA(int ars);
extern unsigned _TIE_NSAU(unsigned ars);
#define XT_NSA _TIE_NSA
#define XT_NSAU _TIE_NSAU
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_BASE_HEADER */
--- NEW FILE: specreg.h ---
/*
* Xtensa Special Register symbolic names
*/
/* $Id: specreg.h,v 1.1 2002/10/23 20:53:21 joetaylor Exp $ */
/*
* Customer ID=40; Build=10966; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef XTENSA_SPECREG_H
#define XTENSA_SPECREG_H
/* Include these special register bitfield definitions, for historical reasons: */
#include <xtensa/corebits.h>
/* Special registers: */
#define LBEG 0
#define LEND 1
#define LCOUNT 2
#define SAR 3
#define WINDOWBASE 72
#define WINDOWSTART 73
#define PTEVADDR 83
#define RASID 90
#define ITLBCFG 91
#define DTLBCFG 92
#define IBREAKENABLE 96
#define DDR 104
#define IBREAKA_0 128
#define IBREAKA_1 129
#define DBREAKA_0 144
#define DBREAKA_1 145
#define DBREAKC_0 160
#define DBREAKC_1 161
#define EPC_1 177
#define EPC_2 178
#define EPC_3 179
#define EPC_4 180
#define DEPC 192
#define EPS_2 194
#define EPS_3 195
#define EPS_4 196
#define EXCSAVE_1 209
#define EXCSAVE_2 210
#define EXCSAVE_3 211
#define EXCSAVE_4 212
#define INTERRUPT 226
#define INTENABLE 228
#define PS 230
#define EXCCAUSE 232
#define DEBUGCAUSE 233
#define CCOUNT 234
#define PRID 235
#define ICOUNT 236
#define ICOUNTLEVEL 237
#define EXCVADDR 238
#define CCOMPARE_0 240
#define CCOMPARE_1 241
#define CCOMPARE_2 242
#define MISC_REG_0 244
#define MISC_REG_1 245
/* Special cases (bases of special register series): */
#define IBREAKA 128
#define DBREAKA 144
#define DBREAKC 160
#define EPC 176
#define EPS 192
#define EXCSAVE 208
#define CCOMPARE 240
/* Special names for read-only and write-only interrupt registers: */
#define INTREAD 226
#define INTSET 226
#define INTCLEAR 227
#endif /* XTENSA_SPECREG_H */
--- NEW FILE: system.h ---
/*
* xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
*
* NOTE: The location and contents of this file are highly subject to change.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* The HAL itself has historically included this file in some instances,
* but this is not appropriate either, because the HAL is meant to be
* core-specific but system independent.
*/
/*
* Customer ID=40; Build=10966; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef XTENSA_CONFIG_SYSTEM_H
#define XTENSA_CONFIG_SYSTEM_H
/*#include <xtensa/hal.h>*/
/*----------------------------------------------------------------------
DEVICE ADDRESSES
----------------------------------------------------------------------*/
/*
* Strange place to find these, but the configuration GUI
* allows moving these around to account for various core
* configurations. Specific boards (and their BSP software)
* will have specific meanings for these components.
*/
/* I/O Block areas: */
#define XSHAL_IOBLOCK_CACHED_VADDR 0xE0000000
#define XSHAL_IOBLOCK_CACHED_PADDR 0xF0000000
#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
#define XSHAL_IOBLOCK_BYPASS_VADDR 0xF0000000
#define XSHAL_IOBLOCK_BYPASS_PADDR 0xF0000000
#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
#if 0
#define XSHAL_ETHER_VADDR 0xFD030000
#define XSHAL_ETHER_PADDR 0xFD030000
#define XSHAL_UART_VADDR 0xFD050000
#define XSHAL_UART_PADDR 0xFD050000
#define XSHAL_LED_VADDR 0xFD040000
#define XSHAL_LED_PADDR 0xFD040000
#define XSHAL_FLASH_VADDR 0xF8000000
#define XSHAL_FLASH_PADDR 0xF8000000
#define XSHAL_FLASH_SIZE 0x04000000
#endif /*0*/
/* System ROM: */
#define XSHAL_ROM_VADDR 0xEE000000
#define XSHAL_ROM_PADDR 0xFE000000
#define XSHAL_ROM_SIZE 0x00400000
/* Largest available area (free of vectors): */
#define XSHAL_ROM_AVAIL_VADDR 0xEE00052C
#define XSHAL_ROM_AVAIL_VSIZE 0x003FFAD4
/* System RAM: */
#define XSHAL_RAM_VADDR 0xD0000000
#define XSHAL_RAM_PADDR 0x00000000
#define XSHAL_RAM_VSIZE 0x08000000
#define XSHAL_RAM_PSIZE 0x10000000
#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
/* Largest available area (free of vectors): */
#define XSHAL_RAM_AVAIL_VADDR 0xD0000370
#define XSHAL_RAM_AVAIL_VSIZE 0x07FFFC90
/*
* Shadow system RAM (same device as system RAM, at different address).
* (Emulation boards need this for the SONIC Ethernet driver
* when data caches are configured for writeback mode.)
* NOTE: on full MMU configs, this points to the BYPASS virtual address
* of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
* addresses are viewed through the BYPASS static map rather than
* the CACHED static map.
*/
#define XSHAL_RAM_BYPASS_VADDR 0xD8000000
#define XSHAL_RAM_BYPASS_PADDR 0x00000000
#define XSHAL_RAM_BYPASS_PSIZE 0x08000000
/* Alternate system RAM (different device than system RAM): */
#define XSHAL_ALTRAM_VADDR 0xCFA00000
#define XSHAL_ALTRAM_PADDR 0xC0000000
#define XSHAL_ALTRAM_SIZE 0x00200000
/*----------------------------------------------------------------------
DEVICE-ADDRESS DEPENDENT...
----------------------------------------------------------------------*/
/*
* Values written to CACHEATTR special register (or its equivalent)
* to enable and disable caches in various modes:
*/
#define XSHAL_CACHEATTR_WRITEBACK 0x22FFFFF1 /* enable caches in write-back mode */
#define XSHAL_CACHEATTR_WRITEALLOC 0x22FFFFF1 /* enable caches in write-allocate mode */
#define XSHAL_CACHEATTR_WRITETHRU 0x22FFFFF1 /* enable caches in write-through mode */
#define XSHAL_CACHEATTR_BYPASS 0x22FFFFF2 /* disable caches in bypass mode */
#define XSHAL_CACHEATTR_DEFAULT XSHAL_CACHEATTR_WRITETHRU /* default setting to enable caches */
/*----------------------------------------------------------------------
ISS (Instruction Set Simulator) SPECIFIC ...
----------------------------------------------------------------------*/
#define XSHAL_ISS_CACHEATTR_WRITEBACK 0x1122222F /* enable caches in write-back mode */
#define XSHAL_ISS_CACHEATTR_WRITEALLOC 0x1122222F /* enable caches in write-allocate mode */
#define XSHAL_ISS_CACHEATTR_WRITETHRU 0x1122222F /* enable caches in write-through mode */
#define XSHAL_ISS_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_WRITEBACK /* default setting to enable caches */
#define XSHAL_ISS_PIPE_REGIONS 0
#define XSHAL_ISS_SDRAM_REGIONS 0
/*----------------------------------------------------------------------
XT2000 BOARD SPECIFIC ...
----------------------------------------------------------------------*/
#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0x21FFFFFF /* enable caches in write-back mode */
#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0x21FFFFFF /* enable caches in write-allocate mode */
#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0x21FFFFFF /* enable caches in write-through mode */
#define XSHAL_XT2000_CACHEATTR_BYPASS 0x22FFFFFF /* disable caches in bypass mode */
#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
#define XSHAL_XT2000_PIPE_REGIONS 0x00001000 /* BusInt pipeline regions */
#define XSHAL_XT2000_SDRAM_REGIONS 0x00000005 /* BusInt SDRAM regions */
/*----------------------------------------------------------------------
VECTOR SIZES
----------------------------------------------------------------------*/
/*
* Sizes allocated to vectors by the system (memory map) configuration.
* These sizes are constrained by core configuration (eg. one vector's
* code cannot overflow into another vector) but are dependent on the
* system or board (or LSP) memory map configuration.
*
* Whether or not each vector happens to be in a system ROM is also
* a system configuration matter, sometimes useful, included here also:
*/
#define XSHAL_RESET_VECTOR_SIZE 0x000004E0
#define XSHAL_RESET_VECTOR_ISROM 1
#define XSHAL_USER_VECTOR_SIZE 0x0000001C
#define XSHAL_USER_VECTOR_ISROM 0
#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNEL_VECTOR_SIZE 0x0000001C
#define XSHAL_KERNEL_VECTOR_ISROM 0
#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x000000E0
#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
#define XSHAL_WINDOW_VECTORS_SIZE 0x00000180
#define XSHAL_WINDOW_VECTORS_ISROM 0
#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL4_VECTOR_ISROM 1
#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL4_VECTOR_SIZE
#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL4_VECTOR_ISROM
#endif /*XTENSA_CONFIG_SYSTEM_H*/
|
|
From: <joe...@us...> - 2002-10-23 20:53:25
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_be
In directory usw-pr-cvs1:/tmp/cvs-serv28395/include/asm-xtensa/xtensa/config-linux_be
Added Files:
core.h defs.h specreg.h system.h
Log Message:
Add processor config information for two additional configs: linux_le and linux_test. Also make the selection of processor configuration selectable at kernel-configuration time. linux_be is the default.
--- NEW FILE: core.h ---
#ifndef XTENSA_CONFIG_CORE_H
#define XTENSA_CONFIG_CORE_H
/*
* THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
*
* include/asm-xtensa/xtensa/config/core.h -- HAL definitions that are
* dependent on CORE configuration.
*
* This header file is sometimes referred to as the "compile-time HAL"
* or CHAL. It was generated for a specific Xtensa processor
* configuration.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* It is perfectly normal, however, for the HAL source itself to
* include this file.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002 Tensilica Inc.
*/
#include <xtensa/hal.h>
/*----------------------------------------------------------------------
GENERAL
----------------------------------------------------------------------*/
/*
* Separators for macros that expand into arrays.
* These can be predefined by files that #include this one,
* when different separators are required.
*/
/* Element separator for macros that expand into 1-dimensional arrays: */
#ifndef XCHAL_SEP
#define XCHAL_SEP ,
#endif
/* Array separator for macros that expand into 2-dimensional arrays: */
#ifndef XCHAL_SEP2
#define XCHAL_SEP2 },{
#endif
/*----------------------------------------------------------------------
ENDIANNESS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_BE 1
#define XCHAL_HAVE_LE 0
#define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN
/*----------------------------------------------------------------------
REGISTER WINDOWS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_WINDOWED 1 /* 1 if windowed registers option configured, 0 otherwise */
#define XCHAL_NUM_AREGS 64 /* number of physical address regs */
#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
/*----------------------------------------------------------------------
INTERRUPTS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_INTERRUPTS 1 /* 1 if interrupt option configured, 0 otherwise */
#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS 1 /* 1 if high-level interrupt option configured, 0 otherwise */
#define XCHAL_HAVE_NMI 0 /* 1 if NMI option configured, 0 otherwise */
#define XCHAL_NUM_INTERRUPTS 17 /* number of interrupts */
#define XCHAL_NUM_EXTINTERRUPTS 10 /* number of external interrupts */
#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels (not including level zero!) */
/* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL0_MASK 0x00000000
#define XCHAL_INTLEVEL1_MASK 0x000064F9
#define XCHAL_INTLEVEL2_MASK 0x00008902
#define XCHAL_INTLEVEL3_MASK 0x00011204
#define XCHAL_INTLEVEL4_MASK 0x00000000
#define XCHAL_INTLEVEL5_MASK 0x00000000
#define XCHAL_INTLEVEL6_MASK 0x00000000
#define XCHAL_INTLEVEL7_MASK 0x00000000
#define XCHAL_INTLEVEL8_MASK 0x00000000
#define XCHAL_INTLEVEL9_MASK 0x00000000
#define XCHAL_INTLEVEL10_MASK 0x00000000
#define XCHAL_INTLEVEL11_MASK 0x00000000
#define XCHAL_INTLEVEL12_MASK 0x00000000
#define XCHAL_INTLEVEL13_MASK 0x00000000
#define XCHAL_INTLEVEL14_MASK 0x00000000
#define XCHAL_INTLEVEL15_MASK 0x00000000
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INTLEVEL_MASKS 0x00000000 XCHAL_SEP \
0x000064F9 XCHAL_SEP \
0x00008902 XCHAL_SEP \
0x00011204 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000 XCHAL_SEP \
0x00000000
/* Masks of interrupts at each range 1..n of interrupt levels: */
#define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000064F9
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x0000EDFB
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL8_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL9_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL10_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL11_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL12_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL13_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL14_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL15_ANDBELOW_MASK 0x0001FFFF
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INTLEVEL_ANDBELOW_MASKS 0x00000000 XCHAL_SEP \
0x000064F9 XCHAL_SEP \
0x0000EDFB XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF XCHAL_SEP \
0x0001FFFF
/* Level of each interrupt: */
#define XCHAL_INT0_LEVEL 1
#define XCHAL_INT1_LEVEL 2
#define XCHAL_INT2_LEVEL 3
#define XCHAL_INT3_LEVEL 1
#define XCHAL_INT4_LEVEL 1
#define XCHAL_INT5_LEVEL 1
#define XCHAL_INT6_LEVEL 1
#define XCHAL_INT7_LEVEL 1
#define XCHAL_INT8_LEVEL 2
#define XCHAL_INT9_LEVEL 3
#define XCHAL_INT10_LEVEL 1
#define XCHAL_INT11_LEVEL 2
#define XCHAL_INT12_LEVEL 3
#define XCHAL_INT13_LEVEL 1
#define XCHAL_INT14_LEVEL 1
#define XCHAL_INT15_LEVEL 2
#define XCHAL_INT16_LEVEL 3
#define XCHAL_INT17_LEVEL 0
#define XCHAL_INT18_LEVEL 0
#define XCHAL_INT19_LEVEL 0
#define XCHAL_INT20_LEVEL 0
#define XCHAL_INT21_LEVEL 0
#define XCHAL_INT22_LEVEL 0
#define XCHAL_INT23_LEVEL 0
#define XCHAL_INT24_LEVEL 0
#define XCHAL_INT25_LEVEL 0
#define XCHAL_INT26_LEVEL 0
#define XCHAL_INT27_LEVEL 0
#define XCHAL_INT28_LEVEL 0
#define XCHAL_INT29_LEVEL 0
#define XCHAL_INT30_LEVEL 0
#define XCHAL_INT31_LEVEL 0
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INT_LEVELS 1 XCHAL_SEP \
2 XCHAL_SEP \
3 XCHAL_SEP \
1 XCHAL_SEP \
1 XCHAL_SEP \
1 XCHAL_SEP \
1 XCHAL_SEP \
1 XCHAL_SEP \
2 XCHAL_SEP \
3 XCHAL_SEP \
1 XCHAL_SEP \
2 XCHAL_SEP \
3 XCHAL_SEP \
1 XCHAL_SEP \
1 XCHAL_SEP \
2 XCHAL_SEP \
3 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0 XCHAL_SEP \
0
/* Type of each interrupt: */
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED
#define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INT_TYPES XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_EDGE XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_EDGE XCHAL_SEP \
XTHAL_INTTYPE_EXTERN_EDGE XCHAL_SEP \
XTHAL_INTTYPE_TIMER XCHAL_SEP \
XTHAL_INTTYPE_TIMER XCHAL_SEP \
XTHAL_INTTYPE_TIMER XCHAL_SEP \
XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
XTHAL_INTTYPE_UNCONFIGURED
/* Masks of interrupts for each type of interrupt: */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFE0000
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0001E000
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000380
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000007F
#define XCHAL_INTTYPE_MASK_TIMER 0x00001C00
#define XCHAL_INTTYPE_MASK_NMI 0x00000000
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INTTYPE_MASKS 0xFFFE0000 XCHAL_SEP \
0x0001E000 XCHAL_SEP \
0x00000380 XCHAL_SEP \
0x0000007F XCHAL_SEP \
0x00001C00 XCHAL_SEP \
0x00000000
/* Interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3), -1 if unassigned */
#define XCHAL_TIMER0_INTERRUPT 10
#define XCHAL_TIMER1_INTERRUPT 11
#define XCHAL_TIMER2_INTERRUPT 12
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_TIMER_INTERRUPTS 10 XCHAL_SEP \
11 XCHAL_SEP \
12 XCHAL_SEP \
XTHAL_TIMER_UNCONFIGURED
/* Indexing macros: */
#define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK
#define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */
#define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
#define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */
#define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL
#define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */
#define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE
#define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */
#define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT
#define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */
/* External interrupt vectors/levels: */
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 2) */
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 3) */
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */
#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */
#define XCHAL_EXTINT8_NUM 8 /* (intlevel 2) */
#define XCHAL_EXTINT9_NUM 9 /* (intlevel 3) */
/* Corresponding interrupt masks: */
#define XCHAL_EXTINT0_MASK 0x00000001
#define XCHAL_EXTINT1_MASK 0x00000002
#define XCHAL_EXTINT2_MASK 0x00000004
#define XCHAL_EXTINT3_MASK 0x00000008
#define XCHAL_EXTINT4_MASK 0x00000010
#define XCHAL_EXTINT5_MASK 0x00000020
#define XCHAL_EXTINT6_MASK 0x00000040
#define XCHAL_EXTINT7_MASK 0x00000080
#define XCHAL_EXTINT8_MASK 0x00000100
#define XCHAL_EXTINT9_MASK 0x00000200
/* Core config interrupt levels mapped to each external interrupt: */
#define XCHAL_EXTINT0_LEVEL 1 /* (int number 0) */
#define XCHAL_EXTINT1_LEVEL 2 /* (int number 1) */
#define XCHAL_EXTINT2_LEVEL 3 /* (int number 2) */
#define XCHAL_EXTINT3_LEVEL 1 /* (int number 3) */
#define XCHAL_EXTINT4_LEVEL 1 /* (int number 4) */
#define XCHAL_EXTINT5_LEVEL 1 /* (int number 5) */
#define XCHAL_EXTINT6_LEVEL 1 /* (int number 6) */
#define XCHAL_EXTINT7_LEVEL 1 /* (int number 7) */
#define XCHAL_EXTINT8_LEVEL 2 /* (int number 8) */
#define XCHAL_EXTINT9_LEVEL 3 /* (int number 9) */
/*----------------------------------------------------------------------
EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_EXCEPTIONS 1 /* 1 if exception option configured, 0 otherwise */
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture number: 1 for XEA1 (old), 2 for XEA2 (new) */
#define XCHAL_HAVE_XEA1 0 /* 1 if XEA1, 0 otherwise */
#define XCHAL_HAVE_XEA2 1 /* 1 if XEA2, 0 otherwise */
/* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */
#define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */
#define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */
#define XCHAL_RESET_VECTOR_VADDR 0xFE000020
#define XCHAL_RESET_VECTOR_PADDR 0xFE000020
#define XCHAL_USER_VECTOR_VADDR 0xD0000220
#define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR /* for backward compatibility */
#define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR /* for backward compatibility */
#define XCHAL_USER_VECTOR_PADDR 0x00000220
#define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR /* for backward compatibility */
#define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR /* for backward compatibility */
#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000200
#define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
#define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
#define XCHAL_KERNERL_VECTOR_PADDR 0x00000200
#define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
#define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD0000290
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x00000290
#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000
#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000240
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000240
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xD0000250
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x00000250
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xFE000520
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xFE000520
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
/* Indexing macros: */
#define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR
#define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */
/*
* Level-1 Exception Causes:
*/
#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction (IllegalInstruction) */
#define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call (SystemCall) */
#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error (InstructionFetchError) */
#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error (LoadStoreError) */
#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt (Level1Interrupt) */
#define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (Alloca) */
#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero (IntegerDivideByZero) */
#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation (Speculation) */
#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction (Privileged) */
#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception (ITlbMiss) */
#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception (ITlbMultihit) */
#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception (ITlbPrivilege) */
#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception (ITlbSizeRestriction) */
#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception (FetchCacheAttribute) */
#define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception (DTlbMiss) */
#define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception (DTlbMultihit) */
#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception (DTlbPrivilege) */
#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception (DTlbSizeRestriction) */
#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception (LoadCacheAttribute) */
#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception (StoreCacheAttribute) */
#define XCHAL_EXCCAUSE_FLOATING_POINT 40 /* Floating Point Exception (FloatingPoint) */
/*----------------------------------------------------------------------
TIMERS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_CCOUNT 1 /* 1 if have CCOUNT, 0 otherwise */
/*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
/*----------------------------------------------------------------------
DEBUG
----------------------------------------------------------------------*/
#define XCHAL_HAVE_DEBUG 1 /* 1 if debug option configured, 0 otherwise */
#define XCHAL_HAVE_OCD 1 /* 1 if OnChipDebug option configured, 0 otherwise */
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */
/*DebugExternalInterrupt 0 0|1*/
/*DebugUseDIRArray 0 0|1*/
/*----------------------------------------------------------------------
COPROCESSORS and EXTRA STATE
----------------------------------------------------------------------*/
#define XCHAL_HAVE_CP 0 /* 1 if coprocessor option configured (CPENABLE present) */
#define XCHAL_CP_NUM 0 /* number of coprocessors */
#define XCHAL_CP_MAX 0 /* max coprocessor id plus one (0 if none) */
#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one (per cfg) */
#define XCHAL_CP_MASK 0x00 /* bitmask of coprocessors by id */
/* Space for coprocessors' state save areas: */
#define XCHAL_CP0_SA_SIZE 0
#define XCHAL_CP1_SA_SIZE 0
#define XCHAL_CP2_SA_SIZE 0
#define XCHAL_CP3_SA_SIZE 0
#define XCHAL_CP4_SA_SIZE 0
#define XCHAL_CP5_SA_SIZE 0
#define XCHAL_CP6_SA_SIZE 0
#define XCHAL_CP7_SA_SIZE 0
/* Minimum required alignments of CP state save areas: */
#define XCHAL_CP0_SA_ALIGN 1
#define XCHAL_CP1_SA_ALIGN 1
#define XCHAL_CP2_SA_ALIGN 1
#define XCHAL_CP3_SA_ALIGN 1
#define XCHAL_CP4_SA_ALIGN 1
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP6_SA_ALIGN 1
#define XCHAL_CP7_SA_ALIGN 1
/* Indexing macros: */
#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
/* Space for "extra" state (user special registers and non-cp TIE) save area: */
#define XCHAL_EXTRA_SA_SIZE 0
#define XCHAL_EXTRA_SA_ALIGN 1
/* Total save area size (extra + all coprocessors) */
/* (not useful until xthal_{save,restore}_all_extra() is implemented, */
/* but included for Tor2 beta; doesn't account for alignment!): */
#define XCHAL_CPEXTRA_SA_SIZE_TOR2 0 /* Tor2Beta temporary definition -- do not use */
/* Combined required alignment for all CP and EXTRA state save areas */
/* (does not include required alignment for any base config registers): */
#define XCHAL_CPEXTRA_SA_ALIGN 1
/* ... */
#ifdef _ASMLANGUAGE
/*
* Assembly-language specific definitions (assembly macros, etc.).
*/
#include <xtensa/config/specreg.h>
/********************
* Macros to save and restore the non-coprocessor TIE portion of EXTRA state.
*/
/* (none) */
/********************
* Macros to create functions that save and restore all EXTRA (non-coprocessor) state
* (does not include zero-overhead loop registers and non-optional registers).
*/
/*
* Macro that expands to the body of a function that
* stores the extra (non-coprocessor) optional/custom state.
* Entry: a2 = ptr to save area in which to save extra state
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_extra_store_funcbody
.endm
/*
* Macro that expands to the body of a function that
* loads the extra (non-coprocessor) optional/custom state.
* Entry: a2 = ptr to save area from which to restore extra state
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_extra_load_funcbody
.endm
/********************
* Macros to save and restore the state of each TIE coprocessor.
*/
/********************
* Macros to create functions that save and restore the state of *any* TIE coprocessor.
*/
/*
* Macro that expands to the body of a function
* that stores the selected coprocessor's state (registers etc).
* Entry: a2 = ptr to save area in which to save cp state
* a3 = coprocessor number
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_cpi_store_funcbody
.endm
/*
* Macro that expands to the body of a function
* that loads the selected coprocessor's state (registers etc).
* Entry: a2 = ptr to save area from which to restore cp state
* a3 = coprocessor number
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_cpi_load_funcbody
.endm
#endif /*_ASMLANGUAGE*/
/*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/
#define XCHAL_NUM_INSTROM 0 /* number of core instruction ROMs configured */
#define XCHAL_NUM_INSTRAM 1 /* number of core instruction RAMs configured */
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs configured */
#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs configured */
#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports configured */
#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */
#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */
#define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */
#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */
/* Instruction RAM 0: */
#define XCHAL_INSTRAM0_VADDR 0xCFFFF000
#define XCHAL_INSTRAM0_PADDR 0xCFFFF000
#define XCHAL_INSTRAM0_SIZE 4096
#define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */
#define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */
#define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */
/* Data RAM 0: */
#define XCHAL_DATARAM0_VADDR 0xCFFFE000
#define XCHAL_DATARAM0_PADDR 0xCFFFE000
#define XCHAL_DATARAM0_SIZE 2048
#define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */
#define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */
#define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */
/* XLMI Port 0: */
#define XCHAL_XLMI0_VADDR 0xCFF80000
#define XCHAL_XLMI0_PADDR 0xCFF80000
#define XCHAL_XLMI0_SIZE 262144
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
/* Size of the cache lines in log2(bytes): */
#define XCHAL_ICACHE_LINEWIDTH 4
#define XCHAL_DCACHE_LINEWIDTH 4
/* Size of the cache lines in bytes: */
#define XCHAL_ICACHE_LINESIZE 16
#define XCHAL_DCACHE_LINESIZE 16
/* Max for both I-cache and D-cache (used for general alignment): */
#define XCHAL_CACHE_LINEWIDTH_MAX 4
#define XCHAL_CACHE_LINESIZE_MAX 16
/* Number of cache sets in log2(lines per way): */
#define XCHAL_ICACHE_SETWIDTH 8
#define XCHAL_DCACHE_SETWIDTH 8
/* Max for both I-cache and D-cache (used for general cache-coherency page alignment): */
#define XCHAL_CACHE_SETWIDTH_MAX 8
#define XCHAL_CACHE_SETSIZE_MAX 256
/* Cache set associativity (number of ways): */
#define XCHAL_ICACHE_WAYS 2
#define XCHAL_DCACHE_WAYS 2
/* Size of the caches in bytes (ways * 2^(linewidth + setwidth)): */
#define XCHAL_ICACHE_SIZE 8192
#define XCHAL_DCACHE_SIZE 8192
/* Cache features: */
#define XCHAL_DCACHE_IS_WRITEBACK 0
/* Whether cache locking feature is available: */
#define XCHAL_ICACHE_LINE_LOCKABLE 0
#define XCHAL_DCACHE_LINE_LOCKABLE 0
/* Number of (encoded) cache attribute bits: */
#define XCHAL_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
/* (The number of access mode bits (decoded cache attribute bits) is defined by the architecture; see xtensa/hal.h?) */
/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_CACHED XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_CACHED XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_CACHED XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_CACHED XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION
#define XCHAL_LCA_LIST XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_CACHED XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_CACHED XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_NACACHED XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_NACACHED XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_ISOLATE XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_CACHED
#define XCHAL_SCA_LIST XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_WRITETHRU XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_WRITETHRU XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_ISOLATE XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_WRITETHRU
/* Test:
read/only: 0 + 1 + 2 + 4 + 5 + 6 + 8 + 9 + 10 + 12 + 14
read/only: 0 + 1 + 2 + 4 + 5 + 6 + 8 + 9 + 10 + 12 + 14
all: 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15
fault: 0 + 2 + 4 + 6 + 8 + 10 + 12 + 14
r/w/x cached:
r/w/x dcached:
I-bypass: 1 + 3
load guard bit set: 1 + 3
load guard bit clr: 0 + 2 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15
hit-cache r/w/x: 7 + 11
fams: 5
fams: 0 / 6 / 18 / 1 / 2
fams: Bypass / Isolate / Cached / Exception / NACached
*/
/* MMU okay: yes */
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
#define XCHAL_HAVE_CACHEATTR 0 /* 1 if CACHEATTR register present, 0 if TLBs present instead */
#define XCHAL_HAVE_TLBS 1 /* 1 if TLBs present, 0 if CACHEATTR present instead */
#define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS /* (DEPRECATED; use XCHAL_HAVE_TLBS instead; will be removed in future release) */
#define XCHAL_HAVE_SPANNING_WAY 0 /* 1 if single way maps entire virtual address space in I+D */
#define XCHAL_HAVE_IDENTITY_MAP 0 /* 1 if virtual addr == physical addr always, 0 otherwise */
#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* 1 if have MMU that mimics a CACHEATTR config (CaMMU) */
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* 1 if have MMU that mimics a CACHEATTR config, but with translation (CaXltMMU) */
#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs (address space IDs) */
#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
#define XCHAL_MMU_ASID_KERNEL 1 /* ASID value indicating kernel (ring 0) address space */
#define XCHAL_MMU_RINGS 4 /* number of rings supported (1..4) */
#define XCHAL_MMU_RING_BITS 2 /* number of bits needed to hold ring number */
#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 12 /* max page size in a PTE structure */
#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 /* min page size in a PTE structure */
/* Instruction TLB: */
#define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */
#define XCHAL_ITLB_WAYS 7 /* number of ways */
#define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */
/* Data TLB: */
#define XCHAL_DTLB_WAY_BITS 4 /* number of bits holding the ways */
#define XCHAL_DTLB_WAYS 10 /* number of ways */
#define XCHAL_DTLB_ARF_WAYS 4 /* number of auto-refill ways */
/* ... */
/*
* Determine whether we have a full MMU (with Page Table and Protection)
* usable for an MMU-based OS:
*/
#if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2
# define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */
#else
# define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */
#endif
/*
* For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings:
*/
#if XCHAL_HAVE_PTP_MMU
#define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */
#define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */
#define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */
#define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */
#define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */
#define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */
#define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */
#define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */
#define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */
#define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */
#define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */
#define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */
#define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */
#define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */
/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */
#endif
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* number of write buffer entries */
#define XCHAL_BUILD_UNIQUE_ID 0x00002AD3 /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
#define XCHAL_HW_CONFIGID0 0xC10FD3FF /* config ID reg 0 value (upper 32 of 64 bits) */
#define XCHAL_HW_CONFIGID1 0x00402AD3 /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
#define XCHAL_HW_RELEASE_MINOR 0 /* minor release of targeted hardware */
#define XCHAL_HW_RELEASE_NAME "T1050.0" /* full release name of targeted hardware */
#define XTHAL_HW_REL_T1050 1
#define XTHAL_HW_REL_T1050_0 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
/*
* Miscellaneous special register fields:
*/
/* DBREAKC (special register number 160): */
#define XCHAL_DBREAKC_VALIDMASK 0xC000003F /* bits of DBREAKC that are defined */
/* MASK field: */
#define XCHAL_DBREAKC_MASK_BITS 6 /* number of bits in MASK field */
#define XCHAL_DBREAKC_MASK_NUM 64 /* max number of possible causes (2^bits) */
#define XCHAL_DBREAKC_MASK_SHIFT 0 /* position of MASK bits in DBREAKC, starting from lsbit */
#define XCHAL_DBREAKC_MASK_MASK 0x0000003F /* mask of bits in MASK field of DBREAKC */
/* LOADBREAK field: */
#define XCHAL_DBREAKC_LOADBREAK_BITS 1 /* number of bits in LOADBREAK field */
#define XCHAL_DBREAKC_LOADBREAK_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_DBREAKC_LOADBREAK_SHIFT 30 /* position of LOADBREAK bits in DBREAKC, starting from lsbit */
#define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000 /* mask of bits in LOADBREAK field of DBREAKC */
/* STOREBREAK field: */
#define XCHAL_DBREAKC_STOREBREAK_BITS 1 /* number of bits in STOREBREAK field */
#define XCHAL_DBREAKC_STOREBREAK_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_DBREAKC_STOREBREAK_SHIFT 31 /* position of STOREBREAK bits in DBREAKC, starting from lsbit */
#define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000 /* mask of bits in STOREBREAK field of DBREAKC */
/* PS (special register number 230): */
#define XCHAL_PS_VALIDMASK 0x00070FFF /* bits of PS that are defined */
/* INTLEVEL field: */
#define XCHAL_PS_INTLEVEL_BITS 4 /* number of bits in INTLEVEL field */
#define XCHAL_PS_INTLEVEL_NUM 16 /* max number of possible causes (2^bits) */
#define XCHAL_PS_INTLEVEL_SHIFT 0 /* position of INTLEVEL bits in PS, starting from lsbit */
#define XCHAL_PS_INTLEVEL_MASK 0x0000000F /* mask of bits in INTLEVEL field of PS */
/* EXCM field: */
#define XCHAL_PS_EXCM_BITS 1 /* number of bits in EXCM field */
#define XCHAL_PS_EXCM_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_PS_EXCM_SHIFT 4 /* position of EXCM bits in PS, starting from lsbit */
#define XCHAL_PS_EXCM_MASK 0x00000010 /* mask of bits in EXCM field of PS */
/* PROGSTACK field: */
#define XCHAL_PS_PROGSTACK_BITS 1 /* number of bits in PROGSTACK field */
#define XCHAL_PS_PROGSTACK_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_PS_PROGSTACK_SHIFT 5 /* position of PROGSTACK bits in PS, starting from lsbit */
#define XCHAL_PS_PROGSTACK_MASK 0x00000020 /* mask of bits in PROGSTACK field of PS */
/* RING field: */
#define XCHAL_PS_RING_BITS 2 /* number of bits in RING field */
#define XCHAL_PS_RING_NUM 4 /* max number of possible causes (2^bits) */
#define XCHAL_PS_RING_SHIFT 6 /* position of RING bits in PS, starting from lsbit */
#define XCHAL_PS_RING_MASK 0x000000C0 /* mask of bits in RING field of PS */
/* OWB field: */
#define XCHAL_PS_OWB_BITS 4 /* number of bits in OWB field */
#define XCHAL_PS_OWB_NUM 16 /* max number of possible causes (2^bits) */
#define XCHAL_PS_OWB_SHIFT 8 /* position of OWB bits in PS, starting from lsbit */
#define XCHAL_PS_OWB_MASK 0x00000F00 /* mask of bits in OWB field of PS */
/* CALLINC field: */
#define XCHAL_PS_CALLINC_BITS 2 /* number of bits in CALLINC field */
#define XCHAL_PS_CALLINC_NUM 4 /* max number of possible causes (2^bits) */
#define XCHAL_PS_CALLINC_SHIFT 16 /* position of CALLINC bits in PS, starting from lsbit */
#define XCHAL_PS_CALLINC_MASK 0x00030000 /* mask of bits in CALLINC field of PS */
/* WOE field: */
#define XCHAL_PS_WOE_BITS 1 /* number of bits in WOE field */
#define XCHAL_PS_WOE_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_PS_WOE_SHIFT 18 /* position of WOE bits in PS, starting from lsbit */
#define XCHAL_PS_WOE_MASK 0x00040000 /* mask of bits in WOE field of PS */
/* EXCCAUSE (special register number 232): */
#define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F /* bits of EXCCAUSE that are defined */
/* EXCCAUSE field: */
#define XCHAL_EXCCAUSE_BITS 6 /* number of bits in EXCCAUSE register */
#define XCHAL_EXCCAUSE_NUM 64 /* max number of possible causes (2^bits) */
#define XCHAL_EXCCAUSE_SHIFT 0 /* position of EXCCAUSE bits in register, starting from lsbit */
#define XCHAL_EXCCAUSE_MASK 0x0000003F /* mask of bits in EXCCAUSE register */
/* DEBUGCAUSE (special register number 233): */
#define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F /* bits of DEBUGCAUSE that are defined */
/* ICOUNT field: */
#define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1 /* number of bits in ICOUNT field */
#define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0 /* position of ICOUNT bits in DEBUGCAUSE, starting from lsbit */
#define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001 /* mask of bits in ICOUNT field of DEBUGCAUSE */
/* IBREAK field: */
#define XCHAL_DEBUGCAUSE_IBREAK_BITS 1 /* number of bits in IBREAK field */
#define XCHAL_DEBUGCAUSE_IBREAK_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1 /* position of IBREAK bits in DEBUGCAUSE, starting from lsbit */
#define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002 /* mask of bits in IBREAK field of DEBUGCAUSE */
/* DBREAK field: */
#define XCHAL_DEBUGCAUSE_DBREAK_BITS 1 /* number of bits in DBREAK field */
#define XCHAL_DEBUGCAUSE_DBREAK_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2 /* position of DBREAK bits in DEBUGCAUSE, starting from lsbit */
#define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004 /* mask of bits in DBREAK field of DEBUGCAUSE */
/* BREAK field: */
#define XCHAL_DEBUGCAUSE_BREAK_BITS 1 /* number of bits in BREAK field */
#define XCHAL_DEBUGCAUSE_BREAK_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3 /* position of BREAK bits in DEBUGCAUSE, starting from lsbit */
#define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008 /* mask of bits in BREAK field of DEBUGCAUSE */
/* BREAKN field: */
#define XCHAL_DEBUGCAUSE_BREAKN_BITS 1 /* number of bits in BREAKN field */
#define XCHAL_DEBUGCAUSE_BREAKN_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4 /* position of BREAKN bits in DEBUGCAUSE, starting from lsbit */
#define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010 /* mask of bits in BREAKN field of DEBUGCAUSE */
/* DEBUGINT field: */
#define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1 /* number of bits in DEBUGINT field */
#define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2 /* max number of possible causes (2^bits) */
#define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5 /* position of DEBUGINT bits in DEBUGCAUSE, starting from lsbit */
#define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020 /* mask of bits in DEBUGINT field of DEBUGCAUSE */
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#define XCHAL_HAVE_DENSITY 1 /* 1 if density option configured, 0 otherwise */
#define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
#define XCHAL_HAVE_LOOPS 1 /* 1 if zero-overhead loops option configured, 0 otherwise */
/* Misc instructions: */
#define XCHAL_HAVE_NSA 1 /* 1 if NSA/NSAU instructions option configured, 0 otherwise */
#define XCHAL_HAVE_MINMAX 0 /* 1 if MIN/MAX instructions option configured, 0 otherwise */
#define XCHAL_HAVE_SEXT 0 /* 1 if sign-extend instruction option configured, 0 otherwise */
#define XCHAL_HAVE_CLAMPS 0 /* 1 if CLAMPS instruction option configured, 0 otherwise */
#define XCHAL_HAVE_MAC16 0 /* 1 if MAC16 option configured, 0 otherwise */
#define XCHAL_HAVE_MUL16 0 /* 1 if 16-bit integer multiply option configured, 0 otherwise */
#define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
#define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
/*#define XCHAL_HAVE_POPC 0*/ /* 1 if CRC instruction option configured, 0 otherwise */
/*#define XCHAL_HAVE_CRC 0*/ /* 1 if POPC instruction option configured, 0 otherwise */
#define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
#define XCHAL_HAVE_SPECULATION 0 /* 1 if speculation option configured, 0 otherwise */
/*#define XCHAL_HAVE_MP_SYNC 0*/ /* 1 if multiprocessor sync. option configured, 0 otherwise */
#define XCHAL_HAVE_PRID 1 /* 1 if processor ID register configured, 0 otherwise */
#define XCHAL_NUM_MISC_REGS 2 /* number of miscellaneous registers (0..4) */
/*----------------------------------------------------------------------
DERIVED
----------------------------------------------------------------------*/
#if XCHAL_HAVE_BE
#define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */
#define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */
#define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */
#else
#define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */
#define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */
#define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */
#endif
/* Belongs in xtensa/hal.h: */
#define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */
#endif /*XTENSA_CONFIG_CORE_H*/
--- NEW FILE: defs.h ---
#ifndef _XTENSA_BASE_HEADER
#define _XTENSA_BASE_HEADER
/*
* THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
*
* include/asm-xtensa/xtensa/config/defs.h -- Definitions for Xtensa
* instructions, types, and protos.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002 Tensilica Inc.
*/
#ifdef __XTENSA__
#if defined(__GNUC__) && !defined(__XCC__)
#define L8UI_ASM(arr, ars, imm) { \
__asm__ volatile("l8ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L8UI(ars, imm) \
({ \
unsigned char _arr; \
const unsigned char *_ars = ars; \
L8UI_ASM(_arr, _ars, imm); \
_arr; \
})
#define L16UI_ASM(arr, ars, imm) { \
__asm__ volatile("l16ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L16UI(ars, imm) \
({ \
unsigned short _arr; \
const unsigned short *_ars = ars; \
L16UI_ASM(_arr, _ars, imm); \
_arr; \
})
#define L16SI_ASM(arr, ars, imm) {\
__asm__ volatile("l16si %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L16SI(ars, imm) \
({ \
signed short _arr; \
const signed short *_ars = ars; \
L16SI_ASM(_arr, _ars, imm); \
_arr; \
})
#define L32I_ASM(arr, ars, imm) { \
__asm__ volatile("l32i %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L32I(ars, imm) \
({ \
unsigned _arr; \
const unsigned *_ars = ars; \
L32I_ASM(_arr, _ars, imm); \
_arr; \
})
#define S8I_ASM(arr, ars, imm) {\
__asm__ volatile("s8i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
}
#define XT_S8I(arr, ars, imm) \
({ \
signed char _arr = arr; \
const signed char *_ars = ars; \
S8I_ASM(_arr, _ars, imm); \
})
#define S16I_ASM(arr, ars, imm) {\
__asm__ volatile("s16i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
}
#define XT_S16I(arr, ars, imm) \
({ \
signed short _arr = arr; \
const signed short *_ars = ars; \
S16I_ASM(_arr, _ars, imm); \
})
#define S32I_ASM(arr, ars, imm) { \
__asm__ volatile("s32i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
}
#define XT_S32I(arr, ars, imm) \
({ \
signed int _arr = arr; \
const signed int *_ars = ars; \
S32I_ASM(_arr, _ars, imm); \
})
#define ADDI_ASM(art, ars, imm) {\
__asm__ ("addi %0, %1, %2" : "=a" (art) : "a" (ars), "i" (imm)); \
}
#define XT_ADDI(ars, imm) \
({ \
unsigned _art; \
unsigned _ars = ars; \
ADDI_ASM(_art, _ars, imm); \
_art; \
})
#define ABS_ASM(arr, art) {\
__asm__ ("abs %0, %1" : "=a" (arr) : "a" (art)); \
}
#define XT_ABS(art) \
({ \
unsigned _arr; \
signed _art = art; \
ABS_ASM(_arr, _art); \
_arr; \
})
/* Note: In the following macros that reference SAR, the magic "state"
register is used to capture the dependency on SAR. This is because
SAR is a 5-bit register and thus there are no C types that can be
used to represent it. It doesn't appear that the SAR register is
even relevant to GCC, but it is marked as "clobbered" just in
case. */
#define SRC_ASM(arr, ars, art) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("src %0, %1, %2" \
: "=a" (arr) : "a" (ars), "a" (art), "t" (_xt_sar)); \
}
#define XT_SRC(ars, art) \
({ \
unsigned _arr; \
unsigned _ars = ars; \
unsigned _art = art; \
SRC_ASM(_arr, _ars, _art); \
_arr; \
})
#define SSR_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssr %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSR(ars) \
({ \
unsigned _ars = ars; \
SSR_ASM(_ars); \
})
#define SSL_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssl %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSL(ars) \
({ \
unsigned _ars = ars; \
SSL_ASM(_ars); \
})
#define SSA8B_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssa8b %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSA8B(ars) \
({ \
unsigned _ars = ars; \
SSA8B_ASM(_ars); \
})
#define SSA8L_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssa8l %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSA8L(ars) \
({ \
unsigned _ars = ars; \
SSA8L_ASM(_ars); \
})
#define SSAI_ASM(imm) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssai %1" : "=t" (_xt_sar) : "i" (imm) : "sar"); \
}
#define XT_SSAI(imm) \
({ \
SSAI_ASM(imm); \
})
#define NSA_ASM(arr, ars) {\
__asm__ ("nsa %0, %1" : "=a" (arr) : "a" (ars)); \
}
#define XT_NSA(ars) \
({ \
unsigned _arr; \
int _ars = ars; \
NSA_ASM(_arr, _ars); \
_arr; \
})
#define NSAU_ASM(arr, ars) {\
__asm__ ("nsau %0, %1" : "=a" (arr) : "a" (ars)); \
}
#define XT_NSAU(ars) \
({ \
unsigned _arr; \
unsigned _ars = ars; \
NSAU_ASM(_arr, _ars); \
_arr; \
})
#endif /* __GNUC__ && !__XCC__ */
#ifdef __XCC__
/* Core load/store instructions */
extern unsigned char _TIE_L8UI(const unsigned char * ars, immediate imm);
extern unsigned short _TIE_L16UI(const unsigned short * ars, immediate imm);
extern signed short _TIE_L16SI(const signed short * ars, immediate imm);
extern unsigned _TIE_L32I(const unsigned * ars, immediate imm);
extern void _TIE_S8I(unsigned char arr, unsigned char * ars, immediate imm);
extern void _TIE_S16I(unsigned short arr, unsigned short * ars, immediate imm);
extern void _TIE_S32I(unsigned arr, unsigned * ars, immediate imm);
#define XT_L8UI _TIE_L8UI
#define XT_L16UI _TIE_L16UI
#define XT_L16SI _TIE_L16SI
#define XT_L32I _TIE_L32I
#define XT_S8I _TIE_S8I
#define XT_S16I _TIE_S16I
#define XT_S32I _TIE_S32I
/* Add-immediate instruction */
extern unsigned _TIE_ADDI(unsigned ars, immediate imm);
#define XT_ADDI _TIE_ADDI
/* Absolute value instruction */
extern unsigned _TIE_ABS(int art);
#define XT_ABS _TIE_ABS
/* funnel shift instructions */
extern unsigned _TIE_SRC(unsigned ars, unsigned art);
#define XT_SRC _TIE_SRC
extern void _TIE_SSR(unsigned ars);
#define XT_SSR _TIE_SSR
extern void _TIE_SSL(unsigned ars);
#define XT_SSL _TIE_SSL
extern void _TIE_SSA8B(unsigned ars);
#define XT_SSA8B _TIE_SSA8B
extern void _TIE_SSA8L(unsigned ars);
#define XT_SSA8L _TIE_SSA8L
extern void _TIE_SSAI(immediate imm);
#define XT_SSAI _TIE_SSAI
/* Miscellaneous instructions */
extern unsigned _TIE_NSA(int ars);
extern unsigned _TIE_NSAU(unsigned ars);
#define XT_NSA _TIE_NSA
#define XT_NSAU _TIE_NSAU
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_BASE_HEADER */
--- NEW FILE: specreg.h ---
#ifndef XTENSA_SPECREG_H
#define XTENSA_SPECREG_H
/*
* THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
*
* include/asm-xtensa/xtensa/config/specreg.h
* Xtensa Special Register symbolic names.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002 Tensilica Inc.
*/
/* Include these special register bitfield definitions, for historical reasons: */
#include <xtensa/corebits.h>
/* Special registers: */
#define LBEG 0
#define LEND 1
#define LCOUNT 2
#define SAR 3
#define WINDOWBASE 72
#define WINDOWSTART 73
#define PTEVADDR 83
#define RASID 90
#define ITLBCFG 91
#define DTLBCFG 92
#define IBREAKENABLE 96
#define DDR 104
#define IBREAKA_0 128
#define IBREAKA_1 129
#define DBREAKA_0 144
#define DBREAKA_1 145
#define DBREAKC_0 160
#define DBREAKC_1 161
#define EPC_1 177
#define EPC_2 178
#define EPC_3 179
#define EPC_4 180
#define DEPC 192
#define EPS_2 194
#define EPS_3 195
#define EPS_4 196
#define EXCSAVE_1 209
#define EXCSAVE_2 210
#define EXCSAVE_3 211
#define EXCSAVE_4 212
#define INTERRUPT 226
#define INTENABLE 228
#define PS 230
#define EXCCAUSE 232
#define DEBUGCAUSE 233
#define CCOUNT 234
#define PRID 235
#define ICOUNT 236
#define ICOUNTLEVEL 237
#define EXCVADDR 238
#define CCOMPARE_0 240
#define CCOMPARE_1 241
#define CCOMPARE_2 242
#define MISC_REG_0 244
#define MISC_REG_1 245
/* Special cases (bases of special register series): */
#define IBREAKA 128
#define DBREAKA 144
#define DBREAKC 160
#define EPC 176
#define EPS 192
#define EXCSAVE 208
#define CCOMPARE 240
/* Special names for read-only and write-only interrupt registers: */
#define INTREAD 226
#define INTSET 226
#define INTCLEAR 227
#endif /* XTENSA_SPECREG_H */
--- NEW FILE: system.h ---
#ifndef XTENSA_CONFIG_SYSTEM_H
#define XTENSA_CONFIG_SYSTEM_H
/*
* THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
*
* include/asm-xtensa/xtensa/config/system.h -- HAL definitions that
* are dependent on SYSTEM configuration.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* The HAL itself has historically included this file in some
* instances, but this is not appropriate either because the HAL is
* meant to be core-specific but system independent.
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file "COPYING" in the main directory of
* this archive for more details.
*
* Copyright (C) 2002 Tensilica Inc.
*/
/*#include <xtensa/hal.h>*/
/*----------------------------------------------------------------------
DEVICE ADDRESSES
----------------------------------------------------------------------*/
/*
* Strange place to find these, but the configuration GUI
* allows moving these around to account for various core
* configurations. Specific boards (and their BSP software)
* will have specific meanings for these components.
*/
/* I/O Block areas: */
#define XSHAL_IOBLOCK_CACHED_VADDR 0xE0000000
#define XSHAL_IOBLOCK_CACHED_PADDR 0xF0000000
#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
#define XSHAL_IOBLOCK_BYPASS_VADDR 0xF0000000
#define XSHAL_IOBLOCK_BYPASS_PADDR 0xF0000000
#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
#if 0
#define XSHAL_ETHER_VADDR 0xFD030000
#define XSHAL_ETHER_PADDR 0xFD030000
#define XSHAL_UART_VADDR 0xFD050000
#define XSHAL_UART_PADDR 0xFD050000
#define XSHAL_LED_VADDR 0xFD040000
#define XSHAL_LED_PADDR 0xFD040000
#define XSHAL_FLASH_VADDR 0xF8000000
#define XSHAL_FLASH_PADDR 0xF8000000
#define XSHAL_FLASH_SIZE 0x04000000
#endif /*0*/
/* System ROM: */
#define XSHAL_ROM_VADDR 0xEE000000
#define XSHAL_ROM_PADDR 0xFE000000
#define XSHAL_ROM_SIZE 0x00400000
/* Largest available area (free of vectors): */
#define XSHAL_ROM_AVAIL_VADDR 0xEE00052C
#define XSHAL_ROM_AVAIL_VSIZE 0x003FFAD4
/* System RAM: */
#define XSHAL_RAM_VADDR 0xD0000000
#define XSHAL_RAM_PADDR 0x00000000
#define XSHAL_RAM_VSIZE 0x08000000
#define XSHAL_RAM_PSIZE 0x10000000
#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
/* Largest available area (free of vectors): */
#define XSHAL_RAM_AVAIL_VADDR 0xD0000370
#define XSHAL_RAM_AVAIL_VSIZE 0x07FFFC90
/*
* Shadow system RAM (same device as system RAM, at different address).
* (Emulation boards need this for the SONIC Ethernet driver
* when data caches are configured for writeback mode.)
* NOTE: on full MMU configs, this points to the BYPASS virtual address
* of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
* addresses are viewed through the BYPASS static map rather than
* the CACHED static map.
*/
#define XSHAL_RAM_BYPASS_VADDR 0xD8000000
#define XSHAL_RAM_BYPASS_PADDR 0x00000000
#define XSHAL_RAM_BYPASS_PSIZE 0x08000000
/* Alternate system RAM (different device than system RAM): */
#define XSHAL_ALTRAM_VADDR 0xCFA00000
#define XSHAL_ALTRAM_PADDR 0xC0000000
#define XSHAL_ALTRAM_SIZE 0x00200000
/*----------------------------------------------------------------------
DEVICE-ADDRESS DEPENDENT...
----------------------------------------------------------------------*/
/*
* Values written to CACHEATTR special register (or its equivalent)
* to enable and disable caches in various modes:
*/
#define XSHAL_CACHEATTR_WRITEBACK 0x22FFFFF1 /* enable caches in write-back mode */
#define XSHAL_CACHEATTR_WRITEALLOC 0x22FFFFF1 /* enable caches in write-allocate mode */
#define XSHAL_CACHEATTR_WRITETHRU 0x22FFFFF1 /* enable caches in write-through mode */
#define XSHAL_CACHEATTR_BYPASS 0x22FFFFF2 /* disable caches in bypass mode */
#define XSHAL_CACHEATTR_DEFAULT XSHAL_CACHEATTR_WRITETHRU /* default setting to enable caches */
/*----------------------------------------------------------------------
ISS (Instruction Set Simulator) SPECIFIC ...
----------------------------------------------------------------------*/
#define XSHAL_ISS_CACHEATTR_WRITEBACK 0x1122222F /* enable caches in write-back mode */
#define XSHAL_ISS_CACHEATTR_WRITEALLOC 0x1122222F /* enable caches in write-allocate mode */
#define XSHAL_ISS_CACHEATTR_WRITETHRU 0x1122222F /* enable caches in write-through mode */
#define XSHAL_ISS_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_WRITEBACK /* default setting to enable caches */
#define XSHAL_ISS_PIPE_REGIONS 0
#define XSHAL_ISS_SDRAM_REGIONS 0
/*----------------------------------------------------------------------
XT2000 BOARD SPECIFIC ...
----------------------------------------------------------------------*/
#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0x21FFFFFF /* enable caches in write-back mode */
#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0x21FFFFFF /* enable caches in write-allocate mode */
#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0x21FFFFFF /* enable caches in write-through mode */
#define XSHAL_XT2000_CACHEATTR_BYPASS 0x22FFFFFF /* disable caches in bypass mode */
#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
#define XSHAL_XT2000_PIPE_REGIONS 0x00001000 /* BusInt pipeline regions */
#define XSHAL_XT2000_SDRAM_REGIONS 0x00000005 /* BusInt SDRAM regions */
/*----------------------------------------------------------------------
VECTOR SIZES
----------------------------------------------------------------------*/
/*
* Sizes allocated to vectors by the system (memory map) configuration.
* These sizes are constrained by core configuration (eg. one vector's
* code cannot overflow into another vector) but are dependent on the
* system or board (or LSP) memory map configuration.
*
* Whether or not each vector happens to be in a system ROM is also
* a system configuration matter, sometimes useful, included here also:
*/
#define XSHAL_RESET_VECTOR_SIZE 0x000004E0
#define XSHAL_RESET_VECTOR_ISROM 1
#define XSHAL_USER_VECTOR_SIZE 0x0000001C
#define XSHAL_USER_VECTOR_ISROM 0
#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNEL_VECTOR_SIZE 0x0000001C
#define XSHAL_KERNEL_VECTOR_ISROM 0
#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x000000E0
#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
#define XSHAL_WINDOW_VECTORS_SIZE 0x00000180
#define XSHAL_WINDOW_VECTORS_ISROM 0
#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL4_VECTOR_ISROM 1
#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL4_VECTOR_SIZE
#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL4_VECTOR_ISROM
#endif /*XTENSA_CONFIG_SYSTEM_H*/
|
|
From: <joe...@us...> - 2002-10-23 20:53:24
|
Update of /cvsroot/xtensa/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv28395/drivers/net
Modified Files:
Config.in Makefile sonic.h
Log Message:
Add processor config information for two additional configs: linux_le and linux_test. Also make the selection of processor configuration selectable at kernel-configuration time. linux_be is the default.
Index: Config.in
===================================================================
RCS file: /cvsroot/xtensa/linux/drivers/net/Config.in,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** Config.in 28 Aug 2002 16:10:41 -0000 1.1.1.1
--- Config.in 23 Oct 2002 20:53:20 -0000 1.2
***************
*** 53,58 ****
tristate ' MIPS JAZZ onboard SONIC Ethernet support' CONFIG_MIPS_JAZZ_SONIC
fi
! if [ "$CONFIG_XTENSA_XT2000" = "y" ]; then
! tristate ' Xtensa XT2000 onboard SONIC Ethernet support' CONFIG_XTENSA_XT2000_SONIC
fi
if [ "$CONFIG_MIPS_GT96100" = "y" ]; then
--- 53,58 ----
tristate ' MIPS JAZZ onboard SONIC Ethernet support' CONFIG_MIPS_JAZZ_SONIC
fi
! if [ "$CONFIG_XTENSA_PLATFORM_XT2000" = "y" ]; then
! tristate ' Xtensa XT2000 onboard SONIC Ethernet support' CONFIG_XTENSA_PLATFORM_XT2000_SONIC
fi
if [ "$CONFIG_MIPS_GT96100" = "y" ]; then
Index: Makefile
===================================================================
RCS file: /cvsroot/xtensa/linux/drivers/net/Makefile,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** Makefile 28 Aug 2002 16:10:41 -0000 1.1.1.1
--- Makefile 23 Oct 2002 20:53:20 -0000 1.2
***************
*** 211,215 ****
obj-$(CONFIG_TUN) += tun.o
obj-$(CONFIG_DL2K) += dl2k.o
! obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o
ifeq ($(CONFIG_ARCH_ACORN),y)
--- 211,215 ----
obj-$(CONFIG_TUN) += tun.o
obj-$(CONFIG_DL2K) += dl2k.o
! obj-$(CONFIG_XTENSA_PLATFORM_XT2000_SONIC) += xtsonic.o
ifeq ($(CONFIG_ARCH_ACORN),y)
Index: sonic.h
===================================================================
RCS file: /cvsroot/xtensa/linux/drivers/net/sonic.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** sonic.h 28 Aug 2002 16:10:45 -0000 1.1.1.1
--- sonic.h 23 Oct 2002 20:53:20 -0000 1.2
***************
*** 218,222 ****
! #if defined(CONFIG_MACSONIC) || defined(CONFIG_XTENSA_XT2000)
/*
* Big endian like structures on 680x0 Macs
--- 218,222 ----
! #if defined(CONFIG_MACSONIC) || defined(CONFIG_XTENSA_PLATFORM_XT2000)
/*
* Big endian like structures on 680x0 Macs
|
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From: <joe...@us...> - 2002-10-23 20:47:36
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/platform-iss In directory usw-pr-cvs1:/tmp/cvs-serv22572/include/asm-xtensa/platform-iss Modified Files: hardware.h Log Message: Documentation update only. Index: hardware.h =================================================================== RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/platform-iss/hardware.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** hardware.h 28 Aug 2002 16:11:31 -0000 1.1.1.1 --- hardware.h 23 Oct 2002 20:47:31 -0000 1.2 *************** *** 10,14 **** /* ! * This file contains the hardware configuration of the XT2000 board. */ --- 10,14 ---- /* ! * This file contains the default configuration of ISS. */ |
|
From: <joe...@us...> - 2002-10-23 18:34:02
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_be In directory usw-pr-cvs1:/tmp/cvs-serv6463/config-linux_be Log Message: Directory /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_be added to the repository |
|
From: <joe...@us...> - 2002-10-23 18:33:52
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test In directory usw-pr-cvs1:/tmp/cvs-serv8562/config-linux_test Log Message: Directory /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test added to the repository |
|
From: <joe...@us...> - 2002-10-23 18:33:52
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_le In directory usw-pr-cvs1:/tmp/cvs-serv8562/config-linux_le Log Message: Directory /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_le added to the repository |
|
From: <joe...@us...> - 2002-10-22 17:59:50
|
Update of /cvsroot/xtensa/linux/arch/xtensa/tools
In directory usw-pr-cvs1:/tmp/cvs-serv11036/arch/xtensa/tools
Modified Files:
offset.c
Log Message:
The 2nd-level miss handlers overlooked a rare case where current->mm might be NULL and they should use current->active_mm instead. See the inline comments for details.
This fixes the board crash manifested by 'apachectl stop'.
Index: offset.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/tools/offset.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** offset.c 28 Aug 2002 16:10:14 -0000 1.1.1.1
--- offset.c 22 Oct 2002 17:59:47 -0000 1.2
***************
*** 83,86 ****
--- 83,87 ----
offset("#define TASK_NICE ", struct task_struct, nice);
offset("#define TASK_MM ", struct task_struct, mm);
+ offset("#define TASK_ACTIVE_MM ", struct task_struct, active_mm);
offset("#define TASK_PID ", struct task_struct, pid);
offset("#define TASK_THREAD ", struct task_struct, thread);
|
|
From: <joe...@us...> - 2002-10-22 17:59:49
|
Update of /cvsroot/xtensa/linux/arch/xtensa/mm
In directory usw-pr-cvs1:/tmp/cvs-serv11036/arch/xtensa/mm
Modified Files:
mmu.c
Log Message:
The 2nd-level miss handlers overlooked a rare case where current->mm might be NULL and they should use current->active_mm instead. See the inline comments for details.
This fixes the board crash manifested by 'apachectl stop'.
Index: mmu.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/mmu.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** mmu.c 18 Oct 2002 21:57:27 -0000 1.2
--- mmu.c 22 Oct 2002 17:59:46 -0000 1.3
***************
*** 160,163 ****
--- 160,164 ----
{
struct task_struct *tsk = current;
+ struct mm_struct *mm = tsk->mm;
unsigned long vpnval;
pgd_t *pgd;
***************
*** 166,173 ****
pte_t pteval;
! /* We need to map the page of PTEs for the user task. Find
! * the pointer to that page. */
! pgd = pgd_offset (tsk->mm, regs->excvaddr);
pmd = pmd_offset (pgd, regs->excvaddr);
--- 167,183 ----
pte_t pteval;
! /* We need to map the page of PTEs for the user task. Find *
! * the pointer to that page. Also, it's possible for tsk->mm
! * to be NULL while tsk->active_mm is nonzero if we faulted on
! * a vmalloc address. In that rare case, we must use
! * active_mm instead to avoid a fault in this handler. See
! *
! * http://mail.nl.linux.org/linux-mm/2002-08/msg00258.html
! * (or search Internet on "mm vs. active_mm")
! */
! if (!mm)
! mm = tsk->active_mm;
! pgd = pgd_offset (mm, regs->excvaddr);
pmd = pmd_offset (pgd, regs->excvaddr);
***************
*** 185,197 ****
pmdval = __pmd((unsigned long)exception_pte_table);
- #if 0 /* XTFIXME: Remove this old code after a while.. [JET, 25 Mar 2002] */
- /* convert regs->excvaddr to relative offset into page-table pages */
- vpnval = (regs->excvaddr / PAGE_SIZE) * sizeof(pte_t);
- vpnval += PGTABLE_START; /* convert to absolute, virtual address */
- vpnval &= PAGE_MASK; /* convert to top of page-table page */
- #else
/* read ptevaddr and convert to top of page-table page */
vpnval = read_ptevaddr_register() & PAGE_MASK;
- #endif
vpnval += WIRED_WAY_FOR_PAGE_TABLE; /* add way number for 'wdtlb' insn */
pteval = mk_pte (virt_to_page(pmd_val(pmdval)), PAGE_KERNEL);
--- 195,200 ----
|
|
From: <joe...@us...> - 2002-10-22 17:59:49
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv11036/arch/xtensa/kernel
Modified Files:
handlers.S
Log Message:
The 2nd-level miss handlers overlooked a rare case where current->mm might be NULL and they should use current->active_mm instead. See the inline comments for details.
This fixes the board crash manifested by 'apachectl stop'.
Index: handlers.S
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/handlers.S,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** handlers.S 22 Sep 2002 21:18:02 -0000 1.4
--- handlers.S 22 Oct 2002 17:59:43 -0000 1.5
***************
*** 1996,1999 ****
--- 1996,2000 ----
{
struct task_struct *tsk = current;
+ struct mm_struct *mm = tsk->mm;
unsigned long vpnval;
pgd_t *pgd;
***************
*** 2012,2033 ****
movi a2, kernelsp
s32i a3, a0, MISS_SAVE_A3
- l32i a2, a2, 0 // a2 <-- kernel sp
s32i a4, a0, MISS_SAVE_A4
s32i a5, a0, MISS_SAVE_A5
! /* We need to map the page of PTEs for the user task. Find
! * the pointer to that page.
! pgd = pgd_offset (tsk->mm, regs->excvaddr);
pmd = pmd_offset (pgd, regs->excvaddr);
- */
! srli a2, a2, _CURRENT_SHIFT
! slli a2, a2, _CURRENT_SHIFT // a2 <-- 'current' or 'tsk'
! rsr a3, EXCVADDR
! l32i a2, a2, TASK_MM
_PGD_OFFSET a2, a3
_PMD_OFFSET a2, addr // empty macro, 2nd parm is optimized away
!
/* We want to map the page of PTEs into the Page Table, but if
* the task doesn't yet have a mapping for the region, just
--- 2013,2045 ----
movi a2, kernelsp
s32i a3, a0, MISS_SAVE_A3
s32i a4, a0, MISS_SAVE_A4
+ l32i a4, a2, 0 // a4 <-- kernel sp
s32i a5, a0, MISS_SAVE_A5
! /* We need to map the page of PTEs for the user task. Find *
! * the pointer to that page. Also, it's possible for tsk->mm
! * to be NULL while tsk->active_mm is nonzero if we faulted on
! * a vmalloc address. In that rare case, we must use
! * active_mm instead to avoid a fault in this handler. See
! *
! * http://mail.nl.linux.org/linux-mm/2002-08/msg00258.html
! * (or search Internet on "mm vs. active_mm")
! if (!mm)
! mm = tsk->active_mm;
! pgd = pgd_offset (mm, regs->excvaddr);
pmd = pmd_offset (pgd, regs->excvaddr);
! */
!
! srli a4, a4, _CURRENT_SHIFT
! slli a4, a4, _CURRENT_SHIFT // a4 <-- 'current' or 'tsk'
! rsr a3, EXCVADDR // a3 <-- fault address
! l32i a2, a4, TASK_MM // a2 <-- tsk->mm
! beqz a2, vmalloc_case // branch on rare vmalloc case
! 4:
_PGD_OFFSET a2, a3
_PMD_OFFSET a2, addr // empty macro, 2nd parm is optimized away
!
/* We want to map the page of PTEs into the Page Table, but if
* the task doesn't yet have a mapping for the region, just
***************
*** 2106,2109 ****
--- 2118,2125 ----
xsr a1, EXCSAVE_1
rfde
+
+ vmalloc_case:
+ l32i a2, a4, TASK_ACTIVE_MM // a2 <-- tsk->active_mm
+ j 4b
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From: <jgr...@us...> - 2002-10-19 04:39:57
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory usw-pr-cvs1:/tmp/cvs-serv29583/arch/xtensa/kernel Modified Files: Makefile xtensa_ksyms.c Log Message: Add xtensa kernel symbol exports. FIXES BUG: 619989 (depmod resulted in unresolved symbols) Index: Makefile =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/Makefile,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** Makefile 19 Sep 2002 07:06:11 -0000 1.2 --- Makefile 19 Oct 2002 04:39:53 -0000 1.3 *************** *** 22,25 **** --- 22,26 ---- obj-$(CONFIG_PCI) += pci-dma.o pcibios.o obj-$(CONFIG_PROC_FS) += proc.o + obj-$(CONFIG_MODULES) += xtensa_ksyms.o # obj-$(CONFIG_REMOTE_DEBUG) += gdb-low.o gdb-stub.o [KCC] Take this out for now Index: xtensa_ksyms.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/xtensa_ksyms.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** xtensa_ksyms.c 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- xtensa_ksyms.c 19 Oct 2002 04:39:53 -0000 1.2 *************** *** 33,47 **** #endif - extern void *__bzero(void *__s, size_t __count); - extern long __strncpy_from_user_nocheck_asm(char *__to, - const char *__from, long __len); - extern long __strncpy_from_user_asm(char *__to, const char *__from, - long __len); - extern long __strlen_user_nocheck_asm(const char *s); - extern long __strlen_user_asm(const char *s); - extern long __strnlen_user_nocheck_asm(const char *s); - extern long __strnlen_user_asm(const char *s); - - EXPORT_SYMBOL(EISA_bus); /* --- 33,36 ---- *************** *** 52,56 **** EXPORT_SYMBOL_NOVERS(memcpy); EXPORT_SYMBOL_NOVERS(memmove); ! EXPORT_SYMBOL(simple_strtol); EXPORT_SYMBOL_NOVERS(strcat); EXPORT_SYMBOL_NOVERS(strchr); --- 41,45 ---- EXPORT_SYMBOL_NOVERS(memcpy); EXPORT_SYMBOL_NOVERS(memmove); ! EXPORT_SYMBOL_NOVERS(memchr); EXPORT_SYMBOL_NOVERS(strcat); EXPORT_SYMBOL_NOVERS(strchr); *************** *** 63,96 **** EXPORT_SYMBOL_NOVERS(strtok); - EXPORT_SYMBOL(_clear_page); EXPORT_SYMBOL(enable_irq); EXPORT_SYMBOL(disable_irq); EXPORT_SYMBOL(kernel_thread); /* ! * Userspace access stuff. */ ! EXPORT_SYMBOL_NOVERS(__copy_user); ! EXPORT_SYMBOL_NOVERS(__bzero); ! EXPORT_SYMBOL_NOVERS(__strncpy_from_user_nocheck_asm); ! EXPORT_SYMBOL_NOVERS(__strncpy_from_user_asm); ! EXPORT_SYMBOL_NOVERS(__strlen_user_nocheck_asm); ! EXPORT_SYMBOL_NOVERS(__strlen_user_asm); ! EXPORT_SYMBOL_NOVERS(__strnlen_user_nocheck_asm); ! EXPORT_SYMBOL_NOVERS(__strnlen_user_asm); ! ! /* Networking helper routines. */ ! EXPORT_SYMBOL(csum_partial_copy); /* ! * Functions to control caches. */ ! EXPORT_SYMBOL(_flush_page_to_ram); ! EXPORT_SYMBOL(_flush_cache_all); ! EXPORT_SYMBOL(_dma_cache_wback_inv); ! EXPORT_SYMBOL(_dma_cache_inv); ! EXPORT_SYMBOL(invalid_pte_table); /* --- 52,95 ---- EXPORT_SYMBOL_NOVERS(strtok); EXPORT_SYMBOL(enable_irq); EXPORT_SYMBOL(disable_irq); EXPORT_SYMBOL(kernel_thread); + EXPORT_SYMBOL(invalid_pte_table); /* ! * gcc internal math functions */ ! extern long long __ashrdi3(long long, int); ! extern long long __ashldi3(long long, int); ! extern long long __lshrdi3(long long, int); ! extern int __divsi3(int, int); ! extern int __modsi3(int, int); ! extern long long __muldi3(long long, long long); ! extern int __mulsi3(int, int); ! extern unsigned int __udivsi3(unsigned int, unsigned int); ! extern unsigned int __umodsi3(unsigned int, unsigned int); ! EXPORT_SYMBOL_NOVERS(__ashldi3); ! EXPORT_SYMBOL_NOVERS(__ashrdi3); ! EXPORT_SYMBOL_NOVERS(__lshrdi3); ! EXPORT_SYMBOL_NOVERS(__divsi3); ! EXPORT_SYMBOL_NOVERS(__modsi3); ! EXPORT_SYMBOL_NOVERS(__muldi3); ! EXPORT_SYMBOL_NOVERS(__mulsi3); ! EXPORT_SYMBOL_NOVERS(__udivsi3); ! EXPORT_SYMBOL_NOVERS(__umodsi3); /* ! * Semaphore operations */ ! EXPORT_SYMBOL(__down); ! EXPORT_SYMBOL(__down_trylock); ! EXPORT_SYMBOL(__up); ! /* ! * Architecture-specific symbols ! */ ! EXPORT_SYMBOL(__xtensa_copy_user); ! EXPORT_SYMBOL(xt_panic); /* *************** *** 98,102 **** */ ! #ifdef CONFIG_VT EXPORT_SYMBOL(screen_info); #endif --- 97,101 ---- */ ! #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) EXPORT_SYMBOL(screen_info); #endif |
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From: <joe...@us...> - 2002-10-18 21:57:32
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv1903/arch/xtensa/kernel
Modified Files:
process.c reset.c
Log Message:
Fix three reset functions: machine_restart(), machine_halt(), and machine_power_off(). They no longer call xt_panic() to hang the system, but try to do something meaningful in the context of Xtensa and the XT2000 or ISS platforms, as appropriate.
Index: process.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/process.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** process.c 6 Sep 2002 20:02:20 -0000 1.2
--- process.c 18 Oct 2002 21:57:26 -0000 1.3
***************
*** 38,43 ****
#include <xtensa/hal.h>
- extern void xt_panic (void);
-
void cpu_idle(void)
{
--- 38,41 ----
Index: reset.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/reset.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** reset.c 28 Aug 2002 16:10:14 -0000 1.1.1.1
--- reset.c 18 Oct 2002 21:57:27 -0000 1.2
***************
*** 9,39 ****
! void xt_panic(void);
! void machine_restart(char *command)
{
! xt_panic(); /* XTFIXME: machine_restart called in $LINUX/kernel/sys.c */
!
! /*
! XTFIXME [kcc]
! platform_restart(command);
! */
}
void machine_halt(void)
{
! xt_panic(); /* XTFIXME: machine_halt called in $LINUX/kernel/sys.c */
!
! /*
! platform_halt();
! */
}
void machine_power_off(void)
{
! xt_panic(); /* XTFIXME: machine_power_off called in $LINUX/kernel/sys.c */
!
! /*
! platform_power_off();
! */
}
--- 9,37 ----
! void (*mach_restart)(char *);
! void (*mach_halt)(void);
! void (*mach_power_off)(void);
! void machine_restart(char * cmd)
{
! if (mach_restart)
! mach_restart(cmd);
! printk (" ** No mach restart, looping forever! **\n");
! while (1);
}
void machine_halt(void)
{
! if (mach_halt)
! mach_halt();
! printk (" ** No mach halt, looping forever! **\n");
! while (1);
}
void machine_power_off(void)
{
! if (mach_power_off)
! mach_power_off();
! printk (" ** No mach power off, looping forever! **\n");
! while (1);
}
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From: <joe...@us...> - 2002-10-18 21:57:31
|
Update of /cvsroot/xtensa/linux/arch/xtensa/platform-xt2000
In directory usw-pr-cvs1:/tmp/cvs-serv1903/arch/xtensa/platform-xt2000
Modified Files:
setup.c
Log Message:
Fix three reset functions: machine_restart(), machine_halt(), and machine_power_off(). They no longer call xt_panic() to hang the system, but try to do something meaningful in the context of Xtensa and the XT2000 or ISS platforms, as appropriate.
Index: setup.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/platform-xt2000/setup.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** setup.c 28 Aug 2002 16:10:14 -0000 1.1.1.1
--- setup.c 18 Oct 2002 21:57:28 -0000 1.2
***************
*** 5,9 ****
* ...
*
! * Author: Chris Zankel <za...@te...>
*
* Copyright 2001 Tensilica Inc.
--- 5,10 ----
* ...
*
! * Authors: Chris Zankel <za...@te...>
! * Joe Taylor <jo...@te...>
*
* Copyright 2001 Tensilica Inc.
***************
*** 31,34 ****
--- 32,39 ----
#include <asm/machvec.h>
#include <asm/bootparam.h>
+ #include <asm/xtutil.h>
+
+ #include <xtensa/xt2000.h>
+
/* Initialize vector table if configured */
***************
*** 37,40 ****
--- 42,50 ----
extern void xt2000_setup_pci(void);
+ extern void reset_mmu(void);
+ extern void (*mach_restart)(char *);
+ extern void (*mach_halt)(void);
+ extern void (*mach_power_off)(void);
+
int xt2000_get_cpuinfo(char *buffer)
***************
*** 49,70 ****
}
! void __init xt2000_setup(char** cmdline)
{
- /* Setup PCI bus */
- xt2000_setup_pci();
}
! void __init xt2000_init_IRQ(void)
{
}
! void xt2000_restart(char *cmd)
{
! while(1);
}
! void xt2000_power_off(void)
{
! while(1);
}
--- 59,121 ----
}
! void __init xt2000_init_IRQ(void)
{
}
! /* Assumes s points to an 8-chr string. No checking for NULL. */
! static void led_print (char *s)
{
+ volatile unsigned long * led_addr = (unsigned long *) (XTBOARD_LED_VADDR+0xE0);
+ int i;
+ for (i = 0; i < 8; i++)
+ *led_addr++ = *s++;
}
! static void xt2000_halt(void)
{
! led_print (" HALT ");
! cli();
! while (1);
}
! static void xt2000_power_off(void)
{
! led_print ("POWEROFF");
! cli();
! while (1);
! }
!
! static void xt2000_restart(char *cmd)
! {
! /* Flush and reset the mmu, simulate a processor reset, and
! * jump to the reset vector. */
!
! reset_mmu();
! __asm__ __volatile__ ("movi a2, 15\n\t"
! "wsr a2, " XTSTR(ICOUNTLEVEL) "\n\t"
! "movi a2, 0\n\t"
! "wsr a2, " XTSTR(ICOUNT) "\n\t"
! "wsr a2, " XTSTR(IBREAKENABLE) "\n\t"
! "wsr a2, " XTSTR(LCOUNT) "\n\t"
! "movi a2, 0x1f\n\t"
! "wsr a2, " XTSTR(PS) "\n\t"
! "isync\n\t"
! "jx %0\n\t"
! :
! : "a" (XCHAL_RESET_VECTOR_VADDR)
! : "a2"
! );
!
! /* control never gets here */
! }
!
! void __init xt2000_setup(char** cmdline)
! {
! /* Setup PCI bus */
! xt2000_setup_pci();
!
! mach_restart = xt2000_restart;
! mach_halt = xt2000_halt;
! mach_power_off = xt2000_power_off;
}
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From: <joe...@us...> - 2002-10-18 21:57:31
|
Update of /cvsroot/xtensa/linux/arch/xtensa/platform-iss
In directory usw-pr-cvs1:/tmp/cvs-serv1903/arch/xtensa/platform-iss
Modified Files:
setup.c
Log Message:
Fix three reset functions: machine_restart(), machine_halt(), and machine_power_off(). They no longer call xt_panic() to hang the system, but try to do something meaningful in the context of Xtensa and the XT2000 or ISS platforms, as appropriate.
Index: setup.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/platform-iss/setup.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** setup.c 28 Aug 2002 16:10:14 -0000 1.1.1.1
--- setup.c 18 Oct 2002 21:57:27 -0000 1.2
***************
*** 5,9 ****
* Platform specific initialization.
*
! * Author: Chris Zankel <za...@te...>
*
* Copyright 2001 Tensilica Inc.
--- 5,10 ----
* Platform specific initialization.
*
! * Authors: Chris Zankel <za...@te...>
! * Joe Taylor <jo...@te...>
*
* Copyright 2001 Tensilica Inc.
***************
*** 38,41 ****
--- 39,47 ----
extern void rs_init(void);
extern void xtensa_console_init(void);
+ extern void reset_mmu(void);
+ extern void (*mach_restart)(char *);
+ extern void (*mach_halt)(void);
+ extern void (*mach_power_off)(void);
+
void __init platform_init(bp_tag_t* bootparam)
***************
*** 45,53 ****
}
- void __init iss_setup(char **p_cmdline)
- {
- rs_init();
- }
-
int iss_get_cpuinfo(char *buffer)
{
--- 51,54 ----
***************
*** 55,59 ****
len = sprintf(buffer, "vendor\t\t: Tensilica\n");
! len += sprintf(buffer+len, "platform\t\t: XT2000\n");
len += sprintf(buffer+len, "memory type\t: SDRAM\n");
--- 56,60 ----
len = sprintf(buffer, "vendor\t\t: Tensilica\n");
! len += sprintf(buffer+len, "platform\t\t: ISS\n");
len += sprintf(buffer+len, "memory type\t: SDRAM\n");
***************
*** 62,73 ****
! void iss_restart(char *cmd)
{
! while(1);
}
! void iss_power_off(void)
{
! while(1);
}
--- 63,109 ----
! static void iss_halt(void)
{
! printk (" ** Called iss_halt(), looping forever! **\n");
! cli();
! while (1);
}
! static void iss_power_off(void)
{
! printk (" ** Called iss_power_off(), looping forever! **\n");
! cli();
! while (1);
! }
! static void iss_restart(char *cmd)
! {
! /* Flush and reset the mmu, simulate a processor reset, and
! * jump to the reset vector. */
!
! reset_mmu();
! __asm__ __volatile__ ("movi a2, 15\n\t"
! "wsr a2, " XTSTR(ICOUNTLEVEL) "\n\t"
! "movi a2, 0\n\t"
! "wsr a2, " XTSTR(ICOUNT) "\n\t"
! "wsr a2, " XTSTR(IBREAKENABLE) "\n\t"
! "wsr a2, " XTSTR(LCOUNT) "\n\t"
! "movi a2, 0x1f\n\t"
! "wsr a2, " XTSTR(PS) "\n\t"
! "isync\n\t"
! "jx %0\n\t"
! :
! : "a" (XCHAL_RESET_VECTOR_VADDR)
! : "a2"
! );
!
! /* control never gets here */
}
+ void __init iss_setup(char **p_cmdline)
+ {
+ rs_init();
+
+ mach_restart = iss_restart;
+ mach_halt = iss_halt;
+ mach_power_off = iss_power_off;
+ }
|
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From: <joe...@us...> - 2002-10-18 21:57:30
|
Update of /cvsroot/xtensa/linux/arch/xtensa/mm
In directory usw-pr-cvs1:/tmp/cvs-serv1903/arch/xtensa/mm
Modified Files:
mmu.c
Log Message:
Fix three reset functions: machine_restart(), machine_halt(), and machine_power_off(). They no longer call xt_panic() to hang the system, but try to do something meaningful in the context of Xtensa and the XT2000 or ISS platforms, as appropriate.
Index: mmu.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/mmu.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** mmu.c 28 Aug 2002 16:10:14 -0000 1.1.1.1
--- mmu.c 18 Oct 2002 21:57:27 -0000 1.2
***************
*** 21,26 ****
#include <asm/pgalloc.h>
- extern void xt_panic (void);
-
/* Called from arch-indep. files: */
--- 21,24 ----
***************
*** 107,114 ****
}
!
! void init_mmu (void)
{
-
/* Writing zeros to the <t>TLBCFG special registers ensure
* that valid values exist in the register. For existing
--- 105,110 ----
}
! void reset_mmu (void)
{
/* Writing zeros to the <t>TLBCFG special registers ensure
* that valid values exist in the register. For existing
***************
*** 125,137 ****
set_rasid_register (ASID_ALL_RESERVED);
! /*
! * Set PTEVADDR special register to the start of the page table,
! * which is in kernel mappable space (ie. not statically mapped).
! * This register's value is undefined on reset.
! */
! set_ptevaddr_register (PGTABLE_START);
}
--- 121,139 ----
set_rasid_register (ASID_ALL_RESERVED);
+ }
! void init_mmu (void)
! {
! /* Flush the mmu and reset associated register to default
! * values. */
! reset_mmu();
+ /* Set PTEVADDR special register to the start of the page
+ * table, which is in kernel mappable space (ie. not
+ * statically mapped). This register's value is undefined on
+ * reset. */
+
+ set_ptevaddr_register (PGTABLE_START);
}
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From: <joe...@us...> - 2002-10-14 19:14:37
|
Update of /cvsroot/xtensa/linux/arch/xtensa/lib In directory usw-pr-cvs1:/tmp/cvs-serv18811/arch/xtensa/lib Modified Files: checksum.S Log Message: Handle trailing odd bytes correctly. That is, include an 8-bit pad of zero before adding it to the checksum. Index: checksum.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/lib/checksum.S,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** checksum.S 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- checksum.S 14 Oct 2002 19:14:33 -0000 1.2 *************** *** 105,108 **** --- 105,109 ---- _bbci.l a3, 0, 7f /* remaining 1-byte chunk */ 6: l8ui a6, a2, 0 + slli a6, a6, 8 /* load byte into bits 8..15 */ ONES_ADD(a4, a6) 7: *************** *** 276,279 **** --- 277,281 ---- SRC( l8ui a9, a2, 0 ) DST( s8i a9, a3, 0 ) + slli a9, a9, 8 /* shift byte to bits 8..15 */ ONES_ADD(a5, a9) 8: |
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From: <joe...@us...> - 2002-10-10 17:01:25
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory usw-pr-cvs1:/tmp/cvs-serv3183a/arch/xtensa/kernel Modified Files: traps.c Log Message: Remove cut-and-paste error. This error affects only linux_test config, not linux_be or linux_le. Index: traps.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/traps.c,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** traps.c 19 Sep 2002 07:06:12 -0000 1.2 --- traps.c 10 Oct 2002 17:01:17 -0000 1.3 *************** *** 54,58 **** #if (XCHAL_CP_MASK & 1) extern asmlinkage void handle_cp0(void); - REGISTER_CP(0); #endif #if (XCHAL_CP_MASK & 2) --- 54,57 ---- |
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From: <sfo...@us...> - 2002-10-04 06:30:58
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv19701
Modified Files:
ptrace.c
Log Message:
Update algorithm to write AR registers via ptrace.
Do not return an error when reading/writing an AR register via ptrace that was not saved because it was not part of an active pane. Return a value of 0 when reading.
Allow PC to be written via ptrace.
Index: ptrace.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/ptrace.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** ptrace.c 23 Sep 2002 19:20:20 -0000 1.3
--- ptrace.c 4 Oct 2002 06:30:55 -0000 1.4
***************
*** 162,167 ****
}
else {
! tmp = -1;
! res = -EIO;
}
break;
--- 162,171 ----
}
else {
! /* If we are here, we are writing to an AR register
! * that was not saved, because it was not part of
! * an active window. gdb sometimes save/restores
! * all registers, so we behave as if it worked --
! * return a value of 0 with no error. */
! tmp = 0;
}
break;
***************
*** 220,223 ****
--- 224,228 ----
case PTRACE_POKEUSR: {
struct pt_regs *regs;
+ unsigned long tmp;
res = 0;
regs = (struct pt_regs *)
***************
*** 239,250 ****
}
else if(a_reg >= first_pane*4) {
! if(first_pane < 0)
! res = -EIO;
! else
! child->thread.regfile[a_reg - first_pane*4] = data;
}
else {
! res = -EIO;
}
break;
case SYSCALL_NR:
--- 244,265 ----
}
else if(a_reg >= first_pane*4) {
! if(first_pane < 0)
! res = -EIO;
! else {
! tmp = XCHAL_NUM_AREGS / 4 - first_pane -
! (a_reg / 4 - first_pane) - 1;
! child->thread.regfile[tmp*4 + a_reg % 4] = data;
! }
}
else {
! /* If we are here, we are writing to an AR register
! * that was not saved, because it was not part of
! * an active window. gdb sometimes save/restores
! * all registers, so we behave as if it worked --
! * return 0, but don't set any values. */
}
+ break;
+ case REG_PC:
+ regs->pc = data;
break;
case SYSCALL_NR:
|
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From: <joe...@us...> - 2002-10-01 22:35:45
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory usw-pr-cvs1:/tmp/cvs-serv13766/arch/xtensa/kernel Modified Files: syscalls.h Log Message: Change the parameter count for sys_ipc() to match glibc. Man pages show six parameters for ipc, yet glibc uses only 5. The goofy syscall parameter layout requires that they match exactly. Index: syscalls.h =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/syscalls.h,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** syscalls.h 11 Sep 2002 16:29:49 -0000 1.2 --- syscalls.h 1 Oct 2002 22:35:41 -0000 1.3 *************** *** 141,145 **** SYS(sys_swapoff, 1) /* 115 */ SYS(sys_sysinfo, 1) ! SYS(sys_ipc, 6) SYS(sys_fsync, 1) SYS(sys_sigreturn, 0) --- 141,145 ---- SYS(sys_swapoff, 1) /* 115 */ SYS(sys_sysinfo, 1) ! SYS(sys_ipc, 5) /* 6 really, but glibc uses only 5) */ SYS(sys_fsync, 1) SYS(sys_sigreturn, 0) |
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From: <joe...@us...> - 2002-09-26 20:45:21
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Update of /cvsroot/xtensa/linux/include/asm-xtensa In directory usw-pr-cvs1:/tmp/cvs-serv12341/include/asm-xtensa Modified Files: socket.h Log Message: Fix TCP problems. The kernel and glibc now agree on the enumeration values for SOCK_DGRAM and SOCK_STREAM. Further, I replaced all the bit-field definitions for the other values in socket.h with consecutive values starting from 1. On Xtensa, this change improves efficiency in related code by eliminating the loading of literals. However, it also requires rebuilding of any user apps that say "#include <sys/socket.h>". Index: socket.h =================================================================== RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/socket.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** socket.h 28 Aug 2002 16:11:31 -0000 1.1.1.1 --- socket.h 26 Sep 2002 20:45:16 -0000 1.2 *************** *** 5,57 **** * include/asm-xtensa/socket.h * ! * Derived from MIPS. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. - * - * Copyright (C) 2001 Tensilica Inc. */ #include <asm/sockios.h> ! /* ! * For setsockoptions(2) ! * ! * This defines are ABI conformant as far as Linux supports these ... ! */ ! #define SOL_SOCKET 0xffff ! ! #define SO_DEBUG 0x0001 /* Record debugging information. */ ! #define SO_REUSEADDR 0x0004 /* Allow reuse of local addresses. */ ! #define SO_KEEPALIVE 0x0008 /* Keep connections alive and send ! SIGPIPE when they die. */ ! #define SO_DONTROUTE 0x0010 /* Don't do local routing. */ ! #define SO_BROADCAST 0x0020 /* Allow transmission of ! broadcast messages. */ ! #define SO_LINGER 0x0080 /* Block on close of a reliable ! socket to transmit pending data. */ ! #define SO_OOBINLINE 0x0100 /* Receive out-of-band data in-band. */ ! #if 0 ! To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */ ! #endif ! ! #define SO_TYPE 0x1008 /* Compatible name for SO_STYLE. */ ! #define SO_STYLE SO_TYPE /* Synonym */ ! #define SO_ERROR 0x1007 /* get error status and clear */ ! #define SO_SNDBUF 0x1001 /* Send buffer size. */ ! #define SO_RCVBUF 0x1002 /* Receive buffer. */ ! #define SO_SNDLOWAT 0x1003 /* send low-water mark */ ! #define SO_RCVLOWAT 0x1004 /* receive low-water mark */ ! #define SO_SNDTIMEO 0x1005 /* send timeout */ ! #define SO_RCVTIMEO 0x1006 /* receive timeout */ ! /* linux-specific, might as well be the same as on i386 */ #define SO_NO_CHECK 11 #define SO_PRIORITY 12 #define SO_BSDCOMPAT 14 ! ! #define SO_PASSCRED 17 ! #define SO_PEERCRED 18 /* Security levels - as per NRL IPv6 - don't actually do anything */ --- 5,41 ---- * include/asm-xtensa/socket.h * ! * Copied from i386. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ #include <asm/sockios.h> ! /* For setsockoptions(2) */ ! #define SOL_SOCKET 1 ! #define SO_DEBUG 1 ! #define SO_REUSEADDR 2 ! #define SO_TYPE 3 ! #define SO_ERROR 4 ! #define SO_DONTROUTE 5 ! #define SO_BROADCAST 6 ! #define SO_SNDBUF 7 ! #define SO_RCVBUF 8 ! #define SO_KEEPALIVE 9 ! #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 #define SO_PRIORITY 12 + #define SO_LINGER 13 #define SO_BSDCOMPAT 14 ! /* To add :#define SO_REUSEPORT 15 */ ! #define SO_PASSCRED 16 ! #define SO_PEERCRED 17 ! #define SO_RCVLOWAT 18 ! #define SO_SNDLOWAT 19 ! #define SO_RCVTIMEO 20 ! #define SO_SNDTIMEO 21 /* Security levels - as per NRL IPv6 - don't actually do anything */ *************** *** 60,64 **** #define SO_SECURITY_ENCRYPTION_NETWORK 24 ! #define SO_BINDTODEVICE 25 /* Socket filtering */ --- 44,48 ---- #define SO_SECURITY_ENCRYPTION_NETWORK 24 ! #define SO_BINDTODEVICE 25 /* Socket filtering */ *************** *** 66,70 **** #define SO_DETACH_FILTER 27 ! #define SO_PEERNAME 28 #define SO_TIMESTAMP 29 #define SCM_TIMESTAMP SO_TIMESTAMP --- 50,54 ---- #define SO_DETACH_FILTER 27 ! #define SO_PEERNAME 28 #define SO_TIMESTAMP 29 #define SCM_TIMESTAMP SO_TIMESTAMP *************** *** 72,80 **** #define SO_ACCEPTCONN 30 ! /* Nast libc5 fixup - bletch */ ! #if defined(__KERNEL__) /* Socket types. */ ! #define SOCK_DGRAM 1 /* datagram (conn.less) socket */ ! #define SOCK_STREAM 2 /* stream (connection) socket */ #define SOCK_RAW 3 /* raw socket */ #define SOCK_RDM 4 /* reliably-delivered message */ --- 56,64 ---- #define SO_ACCEPTCONN 30 ! /* Nasty libc5 fixup - bletch */ ! #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) /* Socket types. */ ! #define SOCK_STREAM 1 /* stream (connection) socket */ ! #define SOCK_DGRAM 2 /* datagram (conn.less) socket */ #define SOCK_RAW 3 /* raw socket */ #define SOCK_RDM 4 /* reliably-delivered message */ |
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From: <sfo...@us...> - 2002-09-23 19:20:23
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Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv28814
Modified Files:
ptrace.c gdb-stub.c
Log Message:
The panes of AR registers are stored in the reverse order of which I thought in the save area on user exceptions. Fix the algorithm to find saved AR registers accordingly. This improves backtracing with gdb markedly.
Index: ptrace.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/ptrace.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** ptrace.c 19 Sep 2002 07:06:12 -0000 1.2
--- ptrace.c 23 Sep 2002 19:20:20 -0000 1.3
***************
*** 147,154 ****
}
else if(a_reg >= first_pane*4) {
! if(first_pane < 0)
! res = -EIO;
! else
! tmp = child->thread.regfile[a_reg - first_pane*4];
}
else {
--- 147,163 ----
}
else if(a_reg >= first_pane*4) {
! if(first_pane < 0)
! res = -EIO;
! else {
! /* Calculate pane of saved registers.
! * first_pane also corresponds to the number of
! * INactive panes, so num_aregs/4 - first_pane
! * is the number of active panes. The highest
! * active pane is is stored in the lowest part
! * of the regfile array. */
! tmp = XCHAL_NUM_AREGS / 4 - first_pane -
! (a_reg / 4 - first_pane) - 1;
! tmp = child->thread.regfile[tmp*4 + a_reg % 4];
! }
}
else {
Index: gdb-stub.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/gdb-stub.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** gdb-stub.c 22 Sep 2002 21:46:48 -0000 1.4
--- gdb-stub.c 23 Sep 2002 19:20:20 -0000 1.5
***************
*** 386,389 ****
--- 386,390 ----
int ar_reg, a_reg, first_pane;
extern int find_first_pane(int, int);
+ int temp;
kernel_single_step = 0;
***************
*** 575,580 ****
if (first_pane < 0)
strcpy(output_buffer, "E01");
! else
! mem2hex((char *)&(current->thread.regfile[a_reg - first_pane*4]), output_buffer, 4, 0);
}
else {
--- 576,590 ----
if (first_pane < 0)
strcpy(output_buffer, "E01");
! else {
! /* Calculate pane of saved registers.
! * first_pane also corresponds to the number of
! * INactive panes, so num_aregs/4 - first_pane
! * is the number of active panes. The highest
! * active pane is is stored in the lowest part
! * of the regfile array. */
! temp = XCHAL_NUM_AREGS / 4 - first_pane
! - (a_reg / 4 - first_pane) - 1;
! mem2hex((char *)&(current->thread.regfile[temp * 4 + a_reg % 4]), output_buffer, 4, 0);
! }
}
else {
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From: <sfo...@us...> - 2002-09-23 19:17:55
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Update of /cvsroot/xtensa/linux/include/asm-xtensa In directory usw-pr-cvs1:/tmp/cvs-serv28104 Modified Files: ptrace.h Log Message: Cast to int, or the >= 0 test never fails. Index: ptrace.h =================================================================== RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/ptrace.h,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** ptrace.h 19 Sep 2002 07:06:08 -0000 1.3 --- ptrace.h 23 Sep 2002 19:17:50 -0000 1.4 *************** *** 35,39 **** /* Note: can return illegal A reg numbers, i.e. > 15 */ #define AR_REGNO_TO_A_REGNO(ar_regno, wb) \ ! ((ar_regno - wb*4) >= 0 ? \ ar_regno - wb*4 : \ XCHAL_NUM_AREGS + ar_regno - wb*4) --- 35,39 ---- /* Note: can return illegal A reg numbers, i.e. > 15 */ #define AR_REGNO_TO_A_REGNO(ar_regno, wb) \ ! ((int)(ar_regno - wb*4) >= 0 ? \ ar_regno - wb*4 : \ XCHAL_NUM_AREGS + ar_regno - wb*4) |
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From: <sfo...@us...> - 2002-09-22 21:46:52
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Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv1995/kernel
Modified Files:
gdb-stub.c
Log Message:
Parameterize serial port and baud rate for kgdb connection.
There are 2 new command line parameters recognized by kgdb:
"gdbbaud=<baud rate>", and "gdbttyS=<serial port>".
The defaults are gdbbaud=9600 and gdbttyS=1 if these parameters are not specified.
Index: gdb-stub.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/gdb-stub.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** gdb-stub.c 22 Sep 2002 21:18:02 -0000 1.3
--- gdb-stub.c 22 Sep 2002 21:46:48 -0000 1.4
***************
*** 116,119 ****
--- 116,121 ----
int gdb_enter = 0; /* when set, kernel waits for connection from gdb on boot */
+ int gdb_ttyS = 1; /* which serail port to use, default ttyS1 */
+ int gdb_baud = 9600; /* baud rate to use */
int kernel_single_step = 0; /* when set, kernel should single step */
***************
*** 790,794 ****
return 1;
}
__setup("gdb", kgdb_opt_gdb);
-
--- 792,807 ----
return 1;
}
+ static int __init kgdb_opt_gdbttyS(char *str)
+ {
+ gdb_ttyS = simple_strtoul(str,NULL,10);
+ return 1;
+ }
+ static int __init kgdb_opt_gdbbaud(char *str)
+ {
+ gdb_baud = simple_strtoul(str,NULL,10);
+ return 1;
+ }
+ __setup("gdbttyS=", kgdb_opt_gdbttyS);
+ __setup("gdbbaud=", kgdb_opt_gdbbaud);
__setup("gdb", kgdb_opt_gdb);
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From: <sfo...@us...> - 2002-09-22 21:46:51
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Update of /cvsroot/xtensa/linux/arch/xtensa/mm
In directory usw-pr-cvs1:/tmp/cvs-serv1995/mm
Modified Files:
init.c
Log Message:
Parameterize serial port and baud rate for kgdb connection.
There are 2 new command line parameters recognized by kgdb:
"gdbbaud=<baud rate>", and "gdbttyS=<serial port>".
The defaults are gdbbaud=9600 and gdbttyS=1 if these parameters are not specified.
Index: init.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/init.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** init.c 19 Sep 2002 07:06:12 -0000 1.2
--- init.c 22 Sep 2002 21:46:48 -0000 1.3
***************
*** 536,542 ****
extern void breakpoint(void);
extern void set_debug_traps(void);
! extern void rs_kgdb_hook(int);
if (gdb_enter) {
! rs_kgdb_hook(1);
set_debug_traps();
printk("Waiting for connection from remote gdb... \n");
--- 536,542 ----
extern void breakpoint(void);
extern void set_debug_traps(void);
! extern void rs_kgdb_hook(void);
if (gdb_enter) {
! rs_kgdb_hook();
set_debug_traps();
printk("Waiting for connection from remote gdb... \n");
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From: <sfo...@us...> - 2002-09-22 21:46:51
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Update of /cvsroot/xtensa/linux/arch/xtensa/platform-xt2000
In directory usw-pr-cvs1:/tmp/cvs-serv1995/platform-xt2000
Modified Files:
gdb_hook.c
Log Message:
Parameterize serial port and baud rate for kgdb connection.
There are 2 new command line parameters recognized by kgdb:
"gdbbaud=<baud rate>", and "gdbttyS=<serial port>".
The defaults are gdbbaud=9600 and gdbttyS=1 if these parameters are not specified.
Index: gdb_hook.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/platform-xt2000/gdb_hook.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** gdb_hook.c 19 Sep 2002 07:06:12 -0000 1.1
--- gdb_hook.c 22 Sep 2002 21:46:48 -0000 1.2
***************
*** 18,21 ****
--- 18,23 ----
#include <asm/io.h>
+ extern int gdb_baud;
+
static struct serial_state rs_table[RS_TABLE_SIZE] = {
SERIAL_PORT_DFNS /* Defined in serial.h */
***************
*** 47,53 ****
}
! void rs_kgdb_hook(int tty_no) {
int t;
! struct serial_state *ser = &rs_table[tty_no];
kdb_port_info.state = ser;
--- 49,56 ----
}
! void rs_kgdb_hook(void) {
int t;
! extern int gdb_ttyS;
! struct serial_state *ser = &rs_table[gdb_ttyS];
kdb_port_info.state = ser;
***************
*** 84,93 ****
/*
! * and set the speed of the serial port
! * (currently hardwired to 9600 8N1
*/
! /* baud rate is fixed to 9600 (is this sufficient?)*/
! t = kdb_port_info.state->baud_base / 9600;
#if 0
--- 87,94 ----
/*
! * and set the speed of the serial port (hardwired to 8N1)
*/
! t = kdb_port_info.state->baud_base / gdb_baud;
#if 0
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