It is not possible to use "New SystemVerilog Module" to create a new Verilog module. Changing the extension to .v does not work.
Either a checkbox "Verilog instead of SystemVerilog" or a "New Verilog Module" menu option would be nice.
This has been corrected for the 1.7.3 release
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This has been corrected for the 1.7.3 release