#355 (* attribute *) in port list is marked as error

[thomas0774]

The "( mark_debug = "true" )" is reported as error (while it compiles correctly with Vivado, so I guess it is OK):

module out_esi_read_buffer_simple #(
parameter a_w = 32, // address width (e.g. 32)
parameter d_w = 512, // data width input-side
parameter burst_len = 16 // length of one burst
) (
input wire clk,
input wire reset,
// Pixel interface
input wire [a_w-1:0] start_addr, // start-address of frame
input wire restart, // single cycle restart pulse
output reg line_complete, // indicates that a complete line is in the buffer
input wire [10:0] width, // width of a line in words
( mark_debug = "true" ) input wire next_line, // single cycle pulse
input wire [10:0] p1_x, // x-coordinate of word
...

BTW: I am filling quite a bunch of tickets in the moment. If you think it is getting too much, please let me know. My intend is to help improve SVEditor.

P.S.: Sorry, the format of the code appears to get lost... and also the * before and after the ) and (

[Matthew Ballance]

Thanks for the bug report, and no worries about filing too many. SystemVerilog is a large language, so bug reports and testcases from users are critical to ensuring SVEditor has solid support for the language.

[Matthew Ballance]

This will be corrected in the 1.6.7 release.

One note here: SystemVerilog allows attributes to show up in many, many places. SVEditor only checks for attributes in a few locations, so you may well run into more cases where the presence of attributes results in a parse error. Please file bug reports for any additional cases you run into.