openocd-devel — Discuss development of OpenOCD

[PATCH]: 22bb335b17 target/armv7a: Hide multiprocessing support message

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8965

-- gerrit

commit 22bb335b17502e60b619d6568b428371025cbbb6
Author: Marc Schink <de...@za...>
Date:   Fri Jun 20 10:53:09 2025 +0200

    target/armv7a: Hide multiprocessing support message
    
    Print a debug message about missing multiprocessing support rather than
    an error message.
    
    Change-Id: Ia1581f7284747d8a92096d6f5515f891c8069f71
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 4d353dec65..651241b772 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -263,7 +263,7 @@ static int armv7a_read_mpidr(struct target *target)
 			armv7a->multi_threading_processor == 1 ? "SMT" : "no SMT");
 
 	} else
-		LOG_ERROR("MPIDR not in multiprocessor format");
+		LOG_DEBUG("MPIDR not in multiprocessor format");
 
 done:
 	dpm->finish(dpm);

-- 

[PATCH]: a5c20cce01 target/armv4: Use LOG_TARGET_xxx()

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8967

-- gerrit

commit a5c20cce0194996ac848d6df32259d2472fb2b85
Author: Marc Schink <de...@za...>
Date:   Fri Jun 20 10:44:21 2025 +0200

    target/armv4: Use LOG_TARGET_xxx()
    
    Use LOG_TARGET_xxx() for log messages as it is used for other targets.
    
    While at it, rework the log messages. For example by removing spaces or
    punctuation marks at the end of the message.
    
    Change-Id: I295001876d40527ec8f35c2aec8d562a29e57b26
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 597dc8990c..22cdba8ced 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -437,7 +437,7 @@ const int armv4_5_core_reg_map[9][17] = {
 static const char *arm_core_state_string(struct arm *arm)
 {
 	if (arm->core_state > ARRAY_SIZE(arm_state_strings)) {
-		LOG_ERROR("core_state exceeds table size");
+		LOG_TARGET_ERROR(arm->target, "core_state exceeds table size");
 		return "Unknown";
 	}
 
@@ -483,20 +483,20 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
 
 	if (cpsr & (1 << 5)) {	/* T */
 		if (cpsr & (1 << 24)) {	/* J */
-			LOG_WARNING("ThumbEE -- incomplete support");
+			LOG_TARGET_WARNING(arm->target, "ThumbEE -- incomplete support");
 			state = ARM_STATE_THUMB_EE;
 		} else
 			state = ARM_STATE_THUMB;
 	} else {
 		if (cpsr & (1 << 24)) {	/* J */
-			LOG_ERROR("Jazelle state handling is BROKEN!");
+			LOG_TARGET_ERROR(arm->target, "Jazelle state handling is broken");
 			state = ARM_STATE_JAZELLE;
 		} else
 			state = ARM_STATE_ARM;
 	}
 	arm->core_state = state;
 
-	LOG_DEBUG("set CPSR %#8.8" PRIx32 ": %s mode, %s state", cpsr,
+	LOG_TARGET_DEBUG(arm->target, "set CPSR %#8.8" PRIx32 ": %s mode, %s state", cpsr,
 		arm_mode_name(mode),
 		arm_core_state_string(arm));
 }
@@ -521,7 +521,7 @@ struct reg *arm_reg_current(struct arm *arm, unsigned int regnum)
 		return NULL;
 
 	if (!arm->map) {
-		LOG_ERROR("Register map is not available yet, the target is not fully initialised");
+		LOG_TARGET_ERROR(arm->target, "Register map is not available yet, the target is not fully initialised");
 		r = arm->core_cache->reg_list + regnum;
 	} else
 		r = arm->core_cache->reg_list + arm->map[regnum];
@@ -530,7 +530,7 @@ struct reg *arm_reg_current(struct arm *arm, unsigned int regnum)
 	 * that doesn't support it...
 	 */
 	if (!r) {
-		LOG_ERROR("Invalid CPSR mode");
+		LOG_TARGET_ERROR(arm->target, "Invalid CPSR mode");
 		r = arm->core_cache->reg_list + regnum;
 	}
 
@@ -631,7 +631,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
 		 */
 		if (armv4_5_target->core_mode !=
 			(enum arm_mode)(value & 0x1f)) {
-			LOG_DEBUG("changing ARM core mode to '%s'",
+			LOG_TARGET_DEBUG(target, "changing ARM core mode to '%s'",
 				arm_mode_name(value & 0x1f));
 			value &= ~((1 << 24) | (1 << 5));
 			uint8_t t[4];
@@ -798,7 +798,7 @@ int arm_arch_state(struct target *target)
 	struct arm *arm = target_to_arm(target);
 
 	if (arm->common_magic != ARM_COMMON_MAGIC) {
-		LOG_ERROR("BUG: called for a non-ARM target");
+		LOG_TARGET_ERROR(target, "BUG: called for a non-ARM target");
 		return ERROR_FAIL;
 	}
 
@@ -806,7 +806,7 @@ int arm_arch_state(struct target *target)
 	if (target->semihosting && target->semihosting->hit_fileio)
 		return ERROR_OK;
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
+	LOG_TARGET_USER(target, "target halted in %s state due to %s, current mode: %s\n"
 		"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s%s",
 		arm_core_state_string(arm),
 		debug_reason_name(target),
@@ -1291,7 +1291,7 @@ int arm_get_gdb_reg_list(struct target *target,
 	unsigned int i;
 
 	if (!is_arm_mode(arm->core_mode)) {
-		LOG_ERROR("not a valid arm core mode - communication failure?");
+		LOG_TARGET_ERROR(target, "not a valid arm core mode - communication failure?");
 		return ERROR_FAIL;
 	}
 
@@ -1362,7 +1362,7 @@ int arm_get_gdb_reg_list(struct target *target,
 		return ERROR_OK;
 
 	default:
-		LOG_ERROR("not a valid register class type in query.");
+		LOG_TARGET_ERROR(target, "not a valid register class type in query");
 		return ERROR_FAIL;
 	}
 }
@@ -1391,8 +1391,7 @@ static int armv4_5_run_algorithm_completion(struct target *target,
 
 	/* fast exit: ARMv5+ code can use BKPT */
 	if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
-		LOG_WARNING(
-			"target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
+		LOG_TARGET_ERROR(target, "reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32,
 			buf_get_u32(arm->pc->value, 0, 32));
 		return ERROR_TARGET_TIMEOUT;
 	}
@@ -1417,10 +1416,10 @@ int armv4_5_run_algorithm_inner(struct target *target,
 	int i;
 	int retval = ERROR_OK;
 
-	LOG_DEBUG("Running algorithm");
+	LOG_TARGET_DEBUG(target, "Running algorithm");
 
 	if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) {
-		LOG_ERROR("current target isn't an ARMV4/5 target");
+		LOG_TARGET_ERROR(target, "current target isn't an ARMV4/5 target");
 		return ERROR_TARGET_INVALID;
 	}
 
@@ -1430,13 +1429,13 @@ int armv4_5_run_algorithm_inner(struct target *target,
 	}
 
 	if (!is_arm_mode(arm->core_mode)) {
-		LOG_ERROR("not a valid arm core mode - communication failure?");
+		LOG_TARGET_ERROR(target, "not a valid arm core mode - communication failure?");
 		return ERROR_FAIL;
 	}
 
 	/* armv5 and later can terminate with BKPT instruction; less overhead */
 	if (!exit_point && arm->arch == ARM_ARCH_V4) {
-		LOG_ERROR("ARMv4 target needs HW breakpoint location");
+		LOG_TARGET_ERROR(target, "ARMv4 target needs HW breakpoint location");
 		return ERROR_FAIL;
 	}
 
@@ -1470,12 +1469,12 @@ int armv4_5_run_algorithm_inner(struct target *target,
 
 		struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, false);
 		if (!reg) {
-			LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+			LOG_TARGET_ERROR(target, "BUG: register '%s' not found", reg_params[i].reg_name);
 			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 
 		if (reg->size != reg_params[i].size) {
-			LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
+			LOG_TARGET_ERROR(target, "BUG: register '%s' size doesn't match reg_params[i].size",
 				reg_params[i].reg_name);
 			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
@@ -1491,12 +1490,12 @@ int armv4_5_run_algorithm_inner(struct target *target,
 	else if (arm->core_state == ARM_STATE_THUMB)
 		exit_breakpoint_size = 2;
 	else {
-		LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
+		LOG_TARGET_ERROR(target, "BUG: can't execute algorithms when not in ARM or Thumb state");
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
 	if (arm_algorithm_info->core_mode != ARM_MODE_ANY) {
-		LOG_DEBUG("setting core_mode: 0x%2.2x",
+		LOG_TARGET_DEBUG(target, "setting core_mode: 0x%2.2x",
 			arm_algorithm_info->core_mode);
 		buf_set_u32(arm->cpsr->value, 0, 5,
 			arm_algorithm_info->core_mode);
@@ -1509,7 +1508,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
 		retval = breakpoint_add(target, exit_point,
 				exit_breakpoint_size, BKPT_HARD);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("can't add HW breakpoint to terminate algorithm");
+			LOG_TARGET_ERROR(target, "can't add HW breakpoint to terminate algorithm");
 			return ERROR_TARGET_FAILURE;
 		}
 	}
@@ -1542,13 +1541,13 @@ int armv4_5_run_algorithm_inner(struct target *target,
 					reg_params[i].reg_name,
 					false);
 			if (!reg) {
-				LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+				LOG_TARGET_ERROR(target, "BUG: register '%s' not found", reg_params[i].reg_name);
 				retval = ERROR_COMMAND_SYNTAX_ERROR;
 				continue;
 			}
 
 			if (reg->size != reg_params[i].size) {
-				LOG_ERROR(
+				LOG_TARGET_ERROR(target,
 					"BUG: register '%s' size doesn't match reg_params[i].size",
 					reg_params[i].reg_name);
 				retval = ERROR_COMMAND_SYNTAX_ERROR;
@@ -1667,7 +1666,7 @@ int arm_checksum_memory(struct target *target,
 	if (retval == ERROR_OK)
 		*checksum = buf_get_u32(reg_params[0].value, 0, 32);
 	else
-		LOG_ERROR("error executing ARM crc algorithm");
+		LOG_TARGET_ERROR(target, "error executing ARM CRC algorithm");
 
 	destroy_reg_param(&reg_params[0]);
 	destroy_reg_param(&reg_params[1]);
@@ -1702,7 +1701,7 @@ int arm_blank_check_memory(struct target *target,
 	assert(sizeof(check_code_le) % 4 == 0);
 
 	if (erased_value != 0xff) {
-		LOG_ERROR("Erase value 0x%02" PRIx8 " not yet supported for ARMv4/v5 targets",
+		LOG_TARGET_ERROR(target, "Erase value 0x%02" PRIx8 " not yet supported for ARMv4/v5 targets",
 			erased_value);
 		return ERROR_FAIL;
 	}
@@ -1781,7 +1780,7 @@ static int arm_default_mrc(struct target *target, int cpnum,
 	uint32_t crn, uint32_t crm,
 	uint32_t *value)
 {
-	LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
+	LOG_TARGET_ERROR(target, "%s doesn't implement MRC", target_type_name(target));
 	return ERROR_FAIL;
 }
 
@@ -1789,7 +1788,7 @@ static int arm_default_mrrc(struct target *target, int cpnum,
 	uint32_t op, uint32_t crm,
 	uint64_t *value)
 {
-	LOG_ERROR("%s doesn't implement MRRC", target_type_name(target));
+	LOG_TARGET_ERROR(target, "%s doesn't implement MRRC", target_type_name(target));
 	return ERROR_FAIL;
 }
 
@@ -1798,7 +1797,7 @@ static int arm_default_mcr(struct target *target, int cpnum,
 	uint32_t crn, uint32_t crm,
 	uint32_t value)
 {
-	LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
+	LOG_TARGET_ERROR(target, "%s doesn't implement MCR", target_type_name(target));
 	return ERROR_FAIL;
 }
 
@@ -1806,7 +1805,7 @@ static int arm_default_mcrr(struct target *target, int cpnum,
 	uint32_t op, uint32_t crm,
 	uint64_t value)
 {
-	LOG_ERROR("%s doesn't implement MCRR", target_type_name(target));
+	LOG_TARGET_ERROR(target, "%s doesn't implement MCRR", target_type_name(target));
 	return ERROR_FAIL;
 }
 

-- 

[PATCH]: 17d8529441 target/armv7a: Use LOG_TARGET_xxx()

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8966

-- gerrit

commit 17d8529441e7a8fd6465a74f5136bc7f2c65a653
Author: Marc Schink <de...@za...>
Date:   Fri Jun 20 10:30:03 2025 +0200

    target/armv7a: Use LOG_TARGET_xxx()
    
    Use LOG_TARGET_xxx() to indicate which target the message belongs to.
    
    Change-Id: Ic40c61a779c1a1ebdc96ebc56b27541fff5e6205
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 651241b772..2bbafd420f 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -68,9 +68,9 @@ static void armv7a_show_fault_registers(struct target *target)
 	if (retval != ERROR_OK)
 		goto done;
 
-	LOG_USER("Data fault registers        DFSR: %8.8" PRIx32
+	LOG_TARGET_USER(target, "Data fault registers        DFSR: %8.8" PRIx32
 		", DFAR: %8.8" PRIx32, dfsr, dfar);
-	LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
+	LOG_TARGET_USER(target, "Instruction fault registers IFSR: %8.8" PRIx32
 		", IFAR: %8.8" PRIx32, ifsr, ifar);
 
 done:
@@ -134,7 +134,7 @@ int armv7a_read_ttbcr(struct target *target)
 	if (retval != ERROR_OK)
 		goto done;
 
-	LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
+	LOG_TARGET_DEBUG(target, "ttbcr %" PRIx32, ttbcr);
 
 	ttbcr_n = ttbcr & 0x7;
 	armv7a->armv7a_mmu.ttbcr = ttbcr;
@@ -169,7 +169,7 @@ int armv7a_read_ttbcr(struct target *target)
 		armv7a->armv7a_mmu.ttbr_mask[0]  = 7 << (32 - ttbcr_n);
 	}
 
-	LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
+	LOG_TARGET_DEBUG(target, "ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
 		  (ttbcr_n != 0) ? "used" : "not used",
 		  armv7a->armv7a_mmu.ttbr_mask[0],
 		  armv7a->armv7a_mmu.ttbr_mask[1]);
@@ -248,14 +248,13 @@ static int armv7a_read_mpidr(struct target *target)
 
 	/* Is register in Multiprocessing Extensions register format? */
 	if (mpidr & MPIDR_MP_EXT) {
-		LOG_DEBUG("%s: MPIDR 0x%" PRIx32, target_name(target), mpidr);
+		LOG_TARGET_DEBUG(target, "%s: MPIDR 0x%" PRIx32, target_name(target), mpidr);
 		armv7a->multi_processor_system = (mpidr >> 30) & 1;
 		armv7a->multi_threading_processor = (mpidr >> 24) & 1;
 		armv7a->level2_id = (mpidr >> 16) & 0xf;
 		armv7a->cluster_id = (mpidr >> 8) & 0xf;
 		armv7a->cpu_id = mpidr & 0xf;
-		LOG_INFO("%s: MPIDR level2 %x, cluster %x, core %x, %s, %s",
-			target_name(target),
+		LOG_TARGET_INFO(target, "MPIDR level2 %x, cluster %x, core %x, %s, %s",
 			armv7a->level2_id,
 			armv7a->cluster_id,
 			armv7a->cpu_id,
@@ -263,7 +262,7 @@ static int armv7a_read_mpidr(struct target *target)
 			armv7a->multi_threading_processor == 1 ? "SMT" : "no SMT");
 
 	} else
-		LOG_DEBUG("MPIDR not in multiprocessor format");
+		LOG_TARGET_DEBUG(target, "MPIDR not in multiprocessor format");
 
 done:
 	dpm->finish(dpm);
@@ -338,7 +337,7 @@ int armv7a_identify_cache(struct target *target)
 
 	cache->iminline = 4UL << (ctr & 0xf);
 	cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
-	LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
+	LOG_TARGET_DEBUG(target, "ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
 		 ctr, cache->iminline, cache->dminline);
 
 	/*  retrieve CLIDR
@@ -350,7 +349,7 @@ int armv7a_identify_cache(struct target *target)
 		goto done;
 
 	cache->loc = (clidr & 0x7000000) >> 24;
-	LOG_DEBUG("Number of cache levels to PoC %" PRId32, cache->loc);
+	LOG_TARGET_DEBUG(target, "Number of cache levels to PoC %" PRId32, cache->loc);
 
 	/*  retrieve selected cache for later restore
 	 *  MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
@@ -378,13 +377,13 @@ int armv7a_identify_cache(struct target *target)
 				goto done;
 			cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
 
-			LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
+			LOG_TARGET_DEBUG(target, "data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
 					cache->arch[cl].d_u_size.index,
 					cache->arch[cl].d_u_size.index_shift,
 					cache->arch[cl].d_u_size.way,
 					cache->arch[cl].d_u_size.way_shift);
 
-			LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
+			LOG_TARGET_DEBUG(target, "cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
 					cache->arch[cl].d_u_size.linelen,
 					cache->arch[cl].d_u_size.cachesize,
 					cache->arch[cl].d_u_size.associativity);
@@ -398,13 +397,13 @@ int armv7a_identify_cache(struct target *target)
 				goto done;
 			cache->arch[cl].i_size = decode_cache_reg(cache_reg);
 
-			LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
+			LOG_TARGET_DEBUG(target, "instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
 					cache->arch[cl].i_size.index,
 					cache->arch[cl].i_size.index_shift,
 					cache->arch[cl].i_size.way,
 					cache->arch[cl].i_size.way_shift);
 
-			LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
+			LOG_TARGET_DEBUG(target, "cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
 					cache->arch[cl].i_size.linelen,
 					cache->arch[cl].i_size.cachesize,
 					cache->arch[cl].i_size.associativity);
@@ -445,7 +444,7 @@ static int armv7a_setup_semihosting(struct target *target, int enable)
 					 armv7a->debug_base + CPUDBG_VCR,
 					 &vcr);
 	if (ret < 0) {
-		LOG_ERROR("Failed to read VCR register\n");
+		LOG_TARGET_ERROR(target, "Failed to read VCR register");
 		return ret;
 	}
 
@@ -458,7 +457,7 @@ static int armv7a_setup_semihosting(struct target *target, int enable)
 					  armv7a->debug_base + CPUDBG_VCR,
 					  vcr);
 	if (ret < 0)
-		LOG_ERROR("Failed to write VCR register\n");
+		LOG_TARGET_ERROR(target, "Failed to write VCR register");
 
 	return ret;
 }
@@ -489,18 +488,18 @@ int armv7a_arch_state(struct target *target)
 	struct arm *arm = &armv7a->arm;
 
 	if (armv7a->common_magic != ARMV7_COMMON_MAGIC) {
-		LOG_ERROR("BUG: called for a non-ARMv7A target");
+		LOG_TARGET_ERROR(target, "BUG: called for a non-ARMv7A target");
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
 	arm_arch_state(target);
 
 	if (armv7a->is_armv7r) {
-		LOG_USER("D-Cache: %s, I-Cache: %s",
+		LOG_TARGET_USER(target, "D-Cache: %s, I-Cache: %s",
 			state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
 			state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);
 	} else {
-		LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
+		LOG_TARGET_USER(target, "MMU: %s, D-Cache: %s, I-Cache: %s",
 			state[armv7a->armv7a_mmu.mmu_enabled],
 			state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
 			state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);

-- 

[PATCH]: fcf0cf3a05 target/arm_dpm: Use LOG_TARGET_xxx()

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8964

-- gerrit

commit fcf0cf3a05c4d96039cf954ca0a2657e0a2e3d85
Author: Marc Schink <de...@za...>
Date:   Fri Jun 20 10:17:12 2025 +0200

    target/arm_dpm: Use LOG_TARGET_xxx()
    
    Use LOG_TARGET_xxx() to indicate which target the message belongs to.
    
    While at it, rework the log messages. For example, using correct format
    specifiers.
    
    Change-Id: I05031e0ae25fe9e7bc38dfb781b6623a967fd533
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 0b2db77c5c..8ab464d0ab 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -50,9 +50,8 @@ static int dpm_mrc(struct target *target, int cpnum,
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
-		(int) op1, (int) crn,
-		(int) crm, (int) op2);
+	LOG_TARGET_DEBUG(target, "MRC p%d, %" PRId32 ", r0, c%" PRId32 ", c%" PRId32 ", %" PRId32,
+		cpnum, op1, crn, crm, op2);
 
 	/* read coprocessor register into R0; return via DCC */
 	retval = dpm->instr_read_data_r0(dpm,
@@ -74,8 +73,8 @@ static int dpm_mrrc(struct target *target, int cpnum,
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_DEBUG("MRRC p%d, %d, r0, r1, c%d", cpnum,
-		 (int)op, (int)crm);
+	LOG_TARGET_DEBUG(target, "MRRC p%d, %" PRId32 ", r0, r1, c%" PRId32,
+		cpnum, op, crm);
 
 	/* read coprocessor register into R0, R1; return via DCC */
 	retval = dpm->instr_read_data_r0_r1(dpm,
@@ -98,9 +97,8 @@ static int dpm_mcr(struct target *target, int cpnum,
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
-		(int) op1, (int) crn,
-		(int) crm, (int) op2);
+	LOG_TARGET_DEBUG(target, "MCR p%d, %" PRId32 ", r0, c%" PRId32 ", c%" PRId32 ", %" PRId32,
+		cpnum, op1, crn, crm, op2);
 
 	/* read DCC into r0; then write coprocessor register from R0 */
 	retval = dpm->instr_write_data_r0(dpm,
@@ -122,8 +120,8 @@ static int dpm_mcrr(struct target *target, int cpnum,
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_DEBUG("MCRR p%d, %d, r0, r1, c%d", cpnum,
-		(int)op, (int)crm);
+	LOG_TARGET_DEBUG(target, "MCRR p%d, %" PRId32 ", r0, r1, c%" PRId32,
+		cpnum, op, crm);
 
 	/* read DCC into r0, r1; then write coprocessor register from R0, R1 */
 	retval = dpm->instr_write_data_r0_r1(dpm,
@@ -198,7 +196,8 @@ static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned int reg
 		buf_set_u32(r->value + 4, 0, 32, value_r1);
 		r->valid = true;
 		r->dirty = false;
-		LOG_DEBUG("READ: %s, %8.8" PRIx32 ", %8.8" PRIx32, r->name, value_r0, value_r1);
+		LOG_TARGET_DEBUG(dpm->arm->target, "READ: %s, %8.8" PRIx32 ", %8.8" PRIx32,
+			r->name, value_r0, value_r1);
 	}
 
 	return retval;
@@ -237,10 +236,10 @@ int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
 					break;
 				case ARM_STATE_JAZELLE:
 					/* core-specific ... ? */
-					LOG_WARNING("Jazelle PC adjustment unknown");
+					LOG_TARGET_WARNING(dpm->arm->target, "Jazelle PC adjustment unknown");
 					break;
 				default:
-					LOG_WARNING("unknown core state");
+					LOG_TARGET_WARNING(dpm->arm->target, "unknown core state");
 					break;
 			}
 			break;
@@ -265,7 +264,8 @@ int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
 		buf_set_u32(r->value, 0, 32, value);
 		r->valid = true;
 		r->dirty = false;
-		LOG_DEBUG("READ: %s, %8.8" PRIx32, r->name, value);
+		LOG_TARGET_DEBUG(dpm->arm->target, "READ: %s, %8.8" PRIx32, r->name,
+			value);
 	}
 
 	return retval;
@@ -301,7 +301,8 @@ static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned int re
 
 	if (retval == ERROR_OK) {
 		r->dirty = false;
-		LOG_DEBUG("WRITE: %s, %8.8" PRIx32 ", %8.8" PRIx32, r->name, value_r0, value_r1);
+		LOG_TARGET_DEBUG(dpm->arm->target, "WRITE: %s, %8.8" PRIx32 ", %8.8" PRIx32,
+			r->name, value_r0, value_r1);
 	}
 
 	return retval;
@@ -349,7 +350,8 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum
 
 	if (retval == ERROR_OK) {
 		r->dirty = false;
-		LOG_DEBUG("WRITE: %s, %8.8" PRIx32, r->name, value);
+		LOG_TARGET_DEBUG(dpm->arm->target, "WRITE: %s, %8.8" PRIx32, r->name,
+			value);
 	}
 
 	return retval;
@@ -463,9 +465,8 @@ static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp,
 				xp->address, xp->control);
 
 	if (retval != ERROR_OK)
-		LOG_ERROR("%s: can't %s HW %spoint %d",
+		LOG_TARGET_ERROR(dpm->arm->target, "can't %s HW %spoint %d",
 			disable ? "disable" : "enable",
-			target_name(dpm->arm->target),
 			(xp->number < 16) ? "break" : "watch",
 			xp->number & 0xf);
 done:
@@ -670,7 +671,7 @@ static enum arm_mode dpm_mapmode(struct arm *arm,
 		case ARM_VFP_V3_D0 ... ARM_VFP_V3_FPSCR:
 			return mode;
 		default:
-			LOG_WARNING("invalid register #%u", num);
+			LOG_TARGET_WARNING(arm->target, "invalid register #%u", num);
 			break;
 	}
 	return ARM_MODE_ANY;
@@ -885,7 +886,7 @@ static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp,
 			}
 		/* FALL THROUGH */
 		default:
-			LOG_ERROR("unsupported {break,watch}point length/alignment");
+			LOG_TARGET_ERROR(dpm->arm->target, "unsupported {break,watch}point length/alignment");
 			return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
@@ -899,7 +900,7 @@ static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp,
 	xp->control = control;
 	xp->dirty = true;
 
-	LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
+	LOG_TARGET_DEBUG(dpm->arm->target, "BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
 		xp->address, control, xp->number);
 
 	/* hardware is updated in write_dirty_registers() */
@@ -919,7 +920,7 @@ static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp)
 
 	/* FIXME we need a generic solution for software breakpoints. */
 	if (bp->type == BKPT_SOFT)
-		LOG_DEBUG("using HW bkpt, not SW...");
+		LOG_TARGET_DEBUG(dpm->arm->target, "using HW breakpoint instead of SW");
 
 	for (unsigned int i = 0; i < dpm->nbp; i++) {
 		if (!dpm->dbp[i].bp) {
@@ -963,7 +964,7 @@ static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned int index_t,
 
 	/* this hardware doesn't support data value matching or masking */
 	if (wp->mask != WATCHPOINT_IGNORE_DATA_VALUE_MASK) {
-		LOG_DEBUG("watchpoint values and masking not supported");
+		LOG_TARGET_ERROR(dpm->arm->target, "watchpoint values and masking not supported");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
@@ -1143,8 +1144,8 @@ int arm_dpm_setup(struct arm_dpm *dpm)
 		return ERROR_FAIL;
 	}
 
-	LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
-		target_name(target), dpm->nbp, dpm->nwp);
+	LOG_TARGET_INFO(target, "hardware has %d breakpoints, %d watchpoints",
+		dpm->nbp, dpm->nwp);
 
 	/* REVISIT ... and some of those breakpoints could match
 	 * execution context IDs...
@@ -1172,8 +1173,7 @@ int arm_dpm_initialize(struct arm_dpm *dpm)
 			(void) dpm->bpwp_disable(dpm, 16 + i);
 		}
 	} else
-		LOG_WARNING("%s: can't disable breakpoints and watchpoints",
-			target_name(dpm->arm->target));
+		LOG_TARGET_WARNING(dpm->arm->target, "can't disable breakpoints and watchpoints");
 
 	return ERROR_OK;
 }

-- 

[PATCH]: 0668f8077b target/armv4: Use command_print() instead of LOG_ERROR()

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8968

-- gerrit

commit 0668f8077bea61c1fb9544c3392c100b14acd79d
Author: Marc Schink <de...@za...>
Date:   Fri Jun 20 10:47:23 2025 +0200

    target/armv4: Use command_print() instead of LOG_ERROR()
    
    Use command_print() in order to provide an error message to the caller.
    
    Change-Id: I9f1a2ef07a102e1d6e755f3680bed0f7183b5c9c
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 22cdba8ced..d907615691 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -842,7 +842,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 	}
 
 	if (!is_arm_mode(arm->core_mode)) {
-		LOG_ERROR("not a valid arm core mode - communication failure?");
+		command_print(CMD, "not a valid arm core mode - communication failure?");
 		return ERROR_FAIL;
 	}
 
@@ -954,7 +954,7 @@ COMMAND_HANDLER(handle_arm_disassemble_command)
 	struct target *target = get_current_target(CMD_CTX);
 
 	if (!target) {
-		LOG_ERROR("No target selected");
+		command_print(CMD, "No target selected");
 		return ERROR_FAIL;
 	}
 

-- 

[PATCH]: 0bd7fc9155 doc: Fix 'add_help_text' and 'add_usage_text' usage

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8963

-- gerrit

commit 0bd7fc9155f84c79978dbb29cd7a4affd2d83516
Author: Marc Schink <de...@za...>
Date:   Thu Jun 19 23:44:23 2025 +0200

    doc: Fix 'add_help_text' and 'add_usage_text' usage
    
    Remove the quotation marks as they are used for strings and not
    parameter names.
    
    Change-Id: I7bb25eb251427e89256b73cf697d8ec5c1b401dc
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index db63fe06db..3ce57897b7 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -9870,11 +9870,11 @@ Requests the current target to map the specified @var{virtual_address}
 to its corresponding physical address, and displays the result.
 @end deffn
 
-@deffn {Command} {add_help_text} 'command_name' 'help-string'
+@deffn {Command} {add_help_text} command_name help_string
 Add or replace help text on the given @var{command_name}.
 @end deffn
 
-@deffn {Command} {add_usage_text} 'command_name' 'help-string'
+@deffn {Command} {add_usage_text} command_name help_string
 Add or replace usage text on the given @var{command_name}.
 @end deffn
 

-- 

[PATCH]: 4c5db683f6 tcl/target/lsch3_common: Remove 'mem2array'

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8962

-- gerrit

commit 4c5db683f6087ab6c4f4ada0d79410f76826b498
Author: Marc Schink <de...@za...>
Date:   Thu Jun 19 10:28:36 2025 +0200

    tcl/target/lsch3_common: Remove 'mem2array'
    
    The 'mem2array' function is deprecated and replaced by 'read_memory'.
    
    Change-Id: Iea54a390d67978d20dbb99ab6f7f4178dda481c2
    Reported-by: Paul Fertser <fer...@gm...>
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/tcl/target/lsch3_common.cfg b/tcl/target/lsch3_common.cfg
index f48d59b9d8..ad88b2e1b3 100644
--- a/tcl/target/lsch3_common.cfg
+++ b/tcl/target/lsch3_common.cfg
@@ -51,8 +51,8 @@ proc release_cpu {cpu} {
 	}
 
 	# Release the cpu; it will start executing something bogus
-	mem2array regs 32 $RST_BRRL 1
-	mww $RST_BRRL [expr {$regs(0) | 1 << $cpu}]
+	set reg [read_memory $RST_BRRL 32 1]
+	mww $RST_BRRL [expr {$reg | 1 << $cpu}]
 
 	if {$not_halted} {
 		resume

-- 

[PATCH]: 6136cd82f0 target/cortex_m: introduce security manipulation routines

[<ge...@op...>]

This is an automated email from Gerrit.

"Tomas Vanek <va...@fb...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8959

-- gerrit

commit 6136cd82f0c4b7a220097674be4e4a24e6b7b780
Author: Tomas Vanek <va...@fb...>
Date:   Tue Jun 17 16:23:12 2025 +0200

    target/cortex_m: introduce security manipulation routines
    
    Running target algorithms on ARMv8M may require core in secure
    mode with SAU and MPU off (as set after reset).
    
    cortex_m_set_secure() forces this mode with optional save of
    the previous state.
    
    cortex_m_security_restore() restores previously saved state.
    
    Change-Id: Ia71826db47ee7b0557eaffd55244ce13eacbcb4b
    Signed-off-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index ba9d83d79f..5fddfb91c8 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2562,6 +2562,112 @@ static bool cortex_m_has_tz(struct target *target)
 	return (dauthstatus & DAUTHSTATUS_SID_MASK) != 0;
 }
 
+int cortex_m_set_secure(struct target *target, struct cortex_m_saved_security *ssec)
+{
+	if (ssec) {
+		ssec->dscsr_dirty = false;
+		ssec->sau_ctrl_dirty = false;
+		ssec->mpu_ctrl_dirty = false;
+	}
+
+	if (!cortex_m_has_tz(target))
+		return ERROR_OK;
+
+	uint32_t dscsr;
+	int retval = target_read_u32(target, DCB_DSCSR, &dscsr);
+	if (retval != ERROR_OK) {
+		LOG_ERROR("ARMv8M set secure: DSCSR read failed");
+		return retval;
+	}
+	if (!(dscsr & DSCSR_CDS)) {
+		if (ssec) {
+			ssec->dscsr_dirty = true;
+			ssec->dscsr = dscsr;
+		}
+		LOG_DEBUG("Setting Current Domain Secure in DSCSR");
+		retval = target_write_u32(target, DCB_DSCSR, DSCSR_CDS);
+		if (retval != ERROR_OK) {
+			LOG_ERROR("ARMv8M set secure: DSCSR write failed");
+			return retval;
+		}
+	}
+
+	uint32_t sau_ctrl;
+	retval = target_read_u32(target, SAU_CTRL, &sau_ctrl);
+	if (retval != ERROR_OK) {
+		LOG_ERROR("ARMv8M set secure: SAU_CTRL read failed");
+		return retval;
+	}
+	if (sau_ctrl & SAU_CTRL_ENABLE) {
+		if (ssec) {
+			ssec->sau_ctrl_dirty = true;
+			ssec->sau_ctrl = sau_ctrl;
+		}
+		retval = target_write_u32(target, SAU_CTRL, sau_ctrl & ~SAU_CTRL_ENABLE);
+		if (retval != ERROR_OK) {
+			LOG_ERROR("ARMv8M set secure: SAU_CTRL write failed");
+			return retval;
+		}
+	}
+
+	uint32_t mpu_ctrl;
+	retval = target_read_u32(target, MPU_CTRL, &mpu_ctrl);
+	if (retval != ERROR_OK) {
+		LOG_ERROR("ARMv8M set secure: MPU_CTRL read failed");
+		return retval;
+	}
+	if (mpu_ctrl & MPU_CTRL_ENABLE) {
+		if (ssec) {
+			ssec->mpu_ctrl_dirty = true;
+			ssec->mpu_ctrl = mpu_ctrl;
+		}
+		retval = target_write_u32(target, MPU_CTRL, mpu_ctrl & ~MPU_CTRL_ENABLE);
+		if (retval != ERROR_OK) {
+			LOG_ERROR("ARMv8M set secure: MPU_CTRL write failed");
+			return retval;
+		}
+	}
+	return ERROR_OK;
+}
+
+int cortex_m_security_restore(struct target *target, struct cortex_m_saved_security *ssec)
+{
+	int retval;
+	if (!cortex_m_has_tz(target))
+		return ERROR_OK;
+
+	if (!ssec)
+		return ERROR_OK;
+
+	if (ssec->mpu_ctrl_dirty) {
+		retval = target_write_u32(target, MPU_CTRL, ssec->mpu_ctrl);
+		if (retval != ERROR_OK) {
+			LOG_ERROR("ARMv8M security restore: MPU_CTRL write failed");
+			return retval;
+		}
+		ssec->mpu_ctrl_dirty = false;
+	}
+
+	if (ssec->sau_ctrl_dirty) {
+		retval = target_write_u32(target, SAU_CTRL, ssec->sau_ctrl);
+		if (retval != ERROR_OK) {
+			LOG_ERROR("ARMv8M security restore: SAU_CTRL write failed");
+			return retval;
+		}
+		ssec->sau_ctrl_dirty = false;
+	}
+
+	if (ssec->dscsr_dirty) {
+		LOG_DEBUG("Restoring Current Domain Security in DSCSR");
+		retval = target_write_u32(target, DCB_DSCSR, ssec->dscsr & ~DSCSR_CDSKEY);
+		if (retval != ERROR_OK) {
+			LOG_ERROR("ARMv8M set secure: DSCSR write failed");
+			return retval;
+		}
+		ssec->dscsr_dirty = false;
+	}
+	return ERROR_OK;
+}
 
 #define MVFR0          0xE000EF40
 #define MVFR0_SP_MASK  0x000000F0
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 144f24560c..82b2c1ecde 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -167,6 +167,8 @@ struct cortex_m_part_info {
 #define NVIC_DFSR		0xE000ED30
 #define NVIC_MMFAR		0xE000ED34
 #define NVIC_BFAR		0xE000ED38
+#define MPU_CTRL		0xE000ED94
+#define SAU_CTRL		0xE000EDD0
 #define NVIC_SFSR		0xE000EDE4
 #define NVIC_SFAR		0xE000EDE8
 
@@ -184,6 +186,9 @@ struct cortex_m_part_info {
 #define DFSR_VCATCH			8
 #define DFSR_EXTERNAL		16
 
+#define MPU_CTRL_ENABLE		BIT(0)
+#define SAU_CTRL_ENABLE		BIT(0)
+
 #define FPCR_CODE 0
 #define FPCR_LITERAL 1
 #define FPCR_REPLACE_REMAP  (0ul << 30)
@@ -264,6 +269,15 @@ struct cortex_m_common {
 	bool incorrect_halt_erratum;
 };
 
+struct cortex_m_saved_security {
+	bool dscsr_dirty;
+	uint32_t dscsr;
+	bool sau_ctrl_dirty;
+	uint32_t sau_ctrl;
+	bool mpu_ctrl_dirty;
+	uint32_t mpu_ctrl;
+};
+
 static inline bool is_cortex_m_or_hla(const struct cortex_m_common *cortex_m)
 {
 	return cortex_m->common_magic == CORTEX_M_COMMON_MAGIC;
@@ -341,4 +355,17 @@ void cortex_m_deinit_target(struct target *target);
 int cortex_m_profiling(struct target *target, uint32_t *samples,
 	uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
 
+/**
+ * Forces Cortex-M core to the basic secure context with SAU and MPU off
+ * @param ssec pointer to save previous security state or NULL
+ * @returns error code or ERROR_OK if secure mode was set or is not applicable
+ * (not ARMv8M with security extension)
+ */
+int cortex_m_set_secure(struct target *target, struct cortex_m_saved_security *ssec);
+
+/**
+ * Restores saved security context to MPU_CTRL, SAU_CTRL and DSCSR
+ */
+int cortex_m_security_restore(struct target *target, struct cortex_m_saved_security *ssec);
+
 #endif /* OPENOCD_TARGET_CORTEX_M_H */

-- 

[PATCH]: 770a065343 flash/nor/rp2xxx: save ACCESSCTRL over ROM API calls

[<ge...@op...>]

This is an automated email from Gerrit.

"Tomas Vanek <va...@fb...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8961

-- gerrit

commit 770a06534392ac66134581eff0fe6f683fdcf306
Author: Tomas Vanek <va...@fb...>
Date:   Wed Jun 18 12:01:08 2025 +0200

    flash/nor/rp2xxx: save ACCESSCTRL over ROM API calls
    
    Especially after the flash probe (used in gdb-attach event)
    we need to completely restore the original security state to allow
    'resume' or gdb 'continue' without injecting strange errors
    to application code.
    
    Save all ACCESSCTRL registers potentially changed by triggering CFGRESET.
    Restore them at cleanup.
    
    Fixes: commit ea775d49fc71 ("flash/nor/rp2040: add RP2350 support")
    Change-Id: I964886d5b1d0269497c343811ee4dcd5c31953db
    Signed-off-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/rp2xxx.c b/src/flash/nor/rp2xxx.c
index fa13ec527f..7011904873 100644
--- a/src/flash/nor/rp2xxx.c
+++ b/src/flash/nor/rp2xxx.c
@@ -41,10 +41,18 @@
 #define BOOTROM_STATE_RESET_OTHER_CORE   0x02
 #define BOOTROM_STATE_RESET_GLOBAL_STATE 0x04
 
-#define ACCESSCTRL_LOCK_OFFSET     0x40060000u
-#define ACCESSCTRL_LOCK_DEBUG_BITS 0x00000008u
-#define ACCESSCTRL_CFGRESET_OFFSET 0x40060008u
-#define ACCESSCTRL_WRITE_PASSWORD  0xacce0000u
+#define ACCESSCTRL_LOCK_OFFSET			0x40060000u
+#define ACCESSCTRL_CFGRESET_OFFSET		0x40060008u
+#define ACCESSCTRL_GPIO_NSMASK0_OFFSET	0x4006000cu
+#define ACCESSCTRL_GPIO_ROM_OFFSET		0x40060014u
+#define ACCESSCTRL_GPIO_XIP_AUX_OFFSET	0x400600e8u
+
+#define ACCESSCTRL_SAVE_BASE			ACCESSCTRL_GPIO_NSMASK0_OFFSET
+#define ACCESSCTRL_SAVE_SIZE \
+			(ACCESSCTRL_GPIO_XIP_AUX_OFFSET + 4 - ACCESSCTRL_SAVE_BASE)
+
+#define ACCESSCTRL_LOCK_DEBUG_BITS		0x00000008u
+#define ACCESSCTRL_WRITE_PASSWORD		0xacce0000u
 
 #define RP2040_SSI_DR0			0x18000060
 #define RP2040_QSPI_CTRL		0x4001800c
@@ -211,6 +219,8 @@ struct rp2xxx_flash_bank {
 	unsigned int sfdp_dummy, sfdp_dummy_detect;
 
 	struct cortex_m_saved_security saved_security;
+	bool accessctrl_dirty;
+	uint8_t saved_accessctrl[ACCESSCTRL_SAVE_SIZE]; /* in target byte order */
 };
 
 #ifndef LOG_ROM_SYMBOL_DEBUG
@@ -601,8 +611,28 @@ static int rp2xxx_call_rom_func(struct target *target, struct rp2xxx_flash_bank
 	return rp2xxx_call_rom_func_batch(target, priv, &call, 1);
 }
 
-static int rp2350_init_accessctrl(struct target *target)
+static int rp2350_save_accessctrl(struct target *target, struct rp2xxx_flash_bank *priv)
 {
+	return target_read_memory(target, ACCESSCTRL_SAVE_BASE, 4, ACCESSCTRL_SAVE_SIZE / 4,
+							  priv->saved_accessctrl);
+}
+
+static int rp2350_restore_accessctrl(struct target *target, struct rp2xxx_flash_bank *priv)
+{
+	// Add write passwords to all ACCESSCTRL regs from ACCESSCTRL_GPIO_ROM to the end
+	// (exclude not keyed ACCESSCTRL_GPIO_NSMASK0 and ACCESSCTRL_GPIO_NSMASK1
+	for (unsigned int i = ACCESSCTRL_GPIO_ROM_OFFSET - ACCESSCTRL_SAVE_BASE;
+			 i < ACCESSCTRL_SAVE_SIZE; i += 4)
+		target_buffer_set_u32(target, priv->saved_accessctrl + i,
+			target_buffer_get_u32(target, priv->saved_accessctrl + i) | ACCESSCTRL_WRITE_PASSWORD);
+
+	return target_write_memory(target, ACCESSCTRL_SAVE_BASE, 4, ACCESSCTRL_SAVE_SIZE / 4,
+							   priv->saved_accessctrl);
+}
+
+static int rp2350_init_accessctrl(struct target *target, struct rp2xxx_flash_bank *priv)
+{
+	priv->accessctrl_dirty = false;
 	// Attempt to reset ACCESSCTRL, in case Secure access to SRAM has been
 	// blocked, which will stop us from loading/running algorithms such as RCP
 	// init. (Also ROM, QMI regs are needed later)
@@ -620,6 +650,11 @@ static int rp2350_init_accessctrl(struct target *target)
 	if (accessctrl_lock_reg & ACCESSCTRL_LOCK_DEBUG_BITS) {
 		LOG_ERROR("ACCESSCTRL is locked, so can't reset permissions. Following steps might fail");
 	} else {
+		int retval = rp2350_save_accessctrl(target, priv);
+		if (retval == ERROR_OK)
+			priv->accessctrl_dirty = true;
+		// Don't fail on save ACCESSCTRL error, not vital for ROM API call
+
 		LOG_DEBUG("Reset ACCESSCTRL permissions via CFGRESET");
 		return target_write_u32(target, ACCESSCTRL_CFGRESET_OFFSET, ACCESSCTRL_WRITE_PASSWORD | 1u);
 	}
@@ -704,7 +739,7 @@ static int setup_for_raw_flash_cmd(struct target *target, struct rp2xxx_flash_ba
 	}
 
 	if (IS_RP2350(priv->id)) {
-		err = rp2350_init_accessctrl(target);
+		err = rp2350_init_accessctrl(target, priv);
 		if (err != ERROR_OK) {
 			LOG_ERROR("Failed to init ACCESSCTRL before ROM call");
 			return err;
@@ -833,12 +868,19 @@ static void cleanup_after_raw_flash_cmd(struct target *target, struct rp2xxx_fla
 	LOG_DEBUG("Cleaning up after flash operations");
 
 	if (IS_RP2350(priv->id)) {
-		/* TODO: restore ACCESSCTRL */
-		if (is_arm(target_to_arm(target))) {
-			int retval = cortex_m_security_restore(target, &priv->saved_security);
-			if (retval != ERROR_OK)
-				LOG_WARNING("RP2xxx: security state was not restored properly. Debug 'resume' will probably fail, use 'reset' instead");
+		int retval1 = ERROR_OK;
+		if (priv->accessctrl_dirty) {
+			retval1 = rp2350_restore_accessctrl(target, priv);
+			priv->accessctrl_dirty = false;
 		}
+
+		int retval2 = ERROR_OK;
+		if (is_arm(target_to_arm(target)))
+			retval2 = cortex_m_security_restore(target, &priv->saved_security);
+
+		if (retval1 != ERROR_OK || retval2 != ERROR_OK)
+			LOG_WARNING("RP2xxx: security state was not restored properly. Debug 'resume' will probably fail, use 'reset' instead");
+		/* Don't fail on security restore error, not vital for flash operation */
 	}
 	if (priv->stack) {
 		target_free_working_area(target, priv->stack);

-- 

[PATCH]: baae57625a flash/nor/rp2xxx: save security state over target algo

[<ge...@op...>]

This is an automated email from Gerrit.

"Tomas Vanek <va...@fb...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8960

-- gerrit

commit baae57625afd9410204ab2ab338849230e650106
Author: Tomas Vanek <va...@fb...>
Date:   Wed Jun 18 09:44:03 2025 +0200

    flash/nor/rp2xxx: save security state over target algo
    
    RP2040 and RP2350 flash driver runs a ROM API target algorithm
    in probe to setup QSPI command interface. The Cortex-M33 core
    of RP2350 has to be in secure mode with SAU and MPU switched off
    to ensure ROM API call working properly.
    
    Especially after the flash probe (used in gdb-attach event)
    we need to completely restore the original security state to allow
    'resume' or gdb 'continue' without injecting strange errors
    to application code.
    
    Use cortex_m support to set secure mode and to restore it back.
    
    Fixes: commit ea775d49fc71 ("flash/nor/rp2040: add RP2350 support")
    Change-Id: I72096bfecbb45a8aa4d3a7a37ad140532b3b00b2
    Signed-off-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/rp2xxx.c b/src/flash/nor/rp2xxx.c
index 85c5911041..fa13ec527f 100644
--- a/src/flash/nor/rp2xxx.c
+++ b/src/flash/nor/rp2xxx.c
@@ -209,6 +209,8 @@ struct rp2xxx_flash_bank {
 	bool size_override;
 	struct flash_device spi_dev;		/* detected model of SPI flash */
 	unsigned int sfdp_dummy, sfdp_dummy_detect;
+
+	struct cortex_m_saved_security saved_security;
 };
 
 #ifndef LOG_ROM_SYMBOL_DEBUG
@@ -630,23 +632,12 @@ static int rp2350_init_arm_core0(struct target *target, struct rp2xxx_flash_bank
 	// run in the Secure state, so flip the state now before attempting to
 	// execute any code on the core.
 	int retval;
-	uint32_t dscsr;
-	retval = target_read_u32(target, DCB_DSCSR, &dscsr);
+	retval = cortex_m_set_secure(target, &priv->saved_security);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("RP2350 init ARM core: DSCSR read failed");
+		LOG_ERROR("RP2350 init ARM core: set secure mode failed");
 		return retval;
 	}
 
-	LOG_DEBUG("DSCSR: 0x%08" PRIx32, dscsr);
-	if (!(dscsr & DSCSR_CDS)) {
-		LOG_DEBUG("Setting Current Domain Secure in DSCSR");
-		retval = target_write_u32(target, DCB_DSCSR, (dscsr & ~DSCSR_CDSKEY) | DSCSR_CDS);
-		if (retval != ERROR_OK) {
-			LOG_ERROR("RP2350 init ARM core: DSCSR read failed");
-			return retval;
-		}
-	}
-
 	if (!priv->stack) {
 		LOG_ERROR("No stack for flash programming code");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
@@ -840,6 +831,15 @@ static void cleanup_after_raw_flash_cmd(struct target *target, struct rp2xxx_fla
 	   driver state. Best to clean up our allocations manually after
 	   completing each flash call, so we know to make fresh ones next time. */
 	LOG_DEBUG("Cleaning up after flash operations");
+
+	if (IS_RP2350(priv->id)) {
+		/* TODO: restore ACCESSCTRL */
+		if (is_arm(target_to_arm(target))) {
+			int retval = cortex_m_security_restore(target, &priv->saved_security);
+			if (retval != ERROR_OK)
+				LOG_WARNING("RP2xxx: security state was not restored properly. Debug 'resume' will probably fail, use 'reset' instead");
+		}
+	}
 	if (priv->stack) {
 		target_free_working_area(target, priv->stack);
 		priv->stack = 0;

-- 

[PATCH]: fa7f15dc82 breakpoint: SMP updates wrt arp_examine support

[<ge...@op...>]

This is an automated email from Gerrit.

"Daniel Goehring <dgo...@os...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8958

-- gerrit

commit fa7f15dc829077f2541c9017055cec2044657abd
Author: Daniel Goehring <dgo...@os...>
Date:   Thu Jun 12 18:32:30 2025 -0400

    breakpoint: SMP updates wrt arp_examine support
    
    Modify SMP breakpoint logic to support a per-core granularity.
    
    Before setting and removing breakpoints/watchpoints for a
    processor core contained in a SMP group, verify the core
    is halted and examined.
    
    For software breakpoints, assign the breakpoint to the current
    selected processor target, not the first target in the SMP group.
    
    Also verify at least one target in a SMP group is examined
    before setting the breakpoint/watchpoint.
    
    Change-Id: I9923ed20ea02ad92cce5ea12558f95e0ae1b161a
    Signed-off-by: Daniel Goehring <dgo...@os...>

diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c
index a080416291..7f79daf538 100644
--- a/src/target/breakpoints.c
+++ b/src/target/breakpoints.c
@@ -211,18 +211,25 @@ int breakpoint_add(struct target *target,
 	enum breakpoint_type type)
 {
 	if (target->smp) {
+		bool breakpoint_set = false;
 		struct target_list *head;
 
-		if (type == BKPT_SOFT) {
-			head = list_first_entry(target->smp_targets, struct target_list, lh);
-			return breakpoint_add_internal(head->target, address, length, type);
-		}
+		if (type == BKPT_SOFT)
+			return breakpoint_add_internal(target, address, length, type);
 
 		foreach_smp_target(head, target->smp_targets) {
 			struct target *curr = head->target;
-			int retval = breakpoint_add_internal(curr, address, length, type);
-			if (retval != ERROR_OK)
-				return retval;
+			if (target_was_examined(curr) && curr->state == TARGET_HALTED) {
+				int retval = breakpoint_add_internal(curr, address, length, type);
+				if (retval != ERROR_OK)
+					return retval;
+				breakpoint_set = true;
+			}
+		}
+
+		if (!breakpoint_set) {
+			LOG_ERROR("Unable to set breakpoint. All SMP targets are in the examine deferred state.");
+			return ERROR_FAIL;
 		}
 
 		return ERROR_OK;
@@ -237,13 +244,22 @@ int context_breakpoint_add(struct target *target,
 	enum breakpoint_type type)
 {
 	if (target->smp) {
+		bool breakpoint_set = false;
 		struct target_list *head;
 
 		foreach_smp_target(head, target->smp_targets) {
 			struct target *curr = head->target;
-			int retval = context_breakpoint_add_internal(curr, asid, length, type);
-			if (retval != ERROR_OK)
-				return retval;
+			if (target_was_examined(curr) && curr->state == TARGET_HALTED) {
+				int retval = context_breakpoint_add_internal(curr, asid, length, type);
+				if (retval != ERROR_OK)
+					return retval;
+				breakpoint_set = true;
+			}
+		}
+
+		if (!breakpoint_set) {
+			LOG_ERROR("Unable to set context breakpoint. All SMP targets are in the examine deferred state.");
+			return ERROR_FAIL;
 		}
 
 		return ERROR_OK;
@@ -259,13 +275,22 @@ int hybrid_breakpoint_add(struct target *target,
 	enum breakpoint_type type)
 {
 	if (target->smp) {
+		bool breakpoint_set = false;
 		struct target_list *head;
 
 		foreach_smp_target(head, target->smp_targets) {
 			struct target *curr = head->target;
-			int retval = hybrid_breakpoint_add_internal(curr, address, asid, length, type);
-			if (retval != ERROR_OK)
-				return retval;
+			if (target_was_examined(curr) && curr->state == TARGET_HALTED) {
+				int retval = hybrid_breakpoint_add_internal(curr, address, asid, length, type);
+				if (retval != ERROR_OK)
+					return retval;
+				breakpoint_set = true;
+			}
+		}
+
+		if (!breakpoint_set) {
+			LOG_ERROR("Unable to set hybrid breakpoint. All SMP targets are in the examine deferred state.");
+			return ERROR_FAIL;
 		}
 
 		return ERROR_OK;
@@ -350,18 +375,19 @@ int breakpoint_remove(struct target *target, target_addr_t address)
 
 		foreach_smp_target(head, target->smp_targets) {
 			struct target *curr = head->target;
-			int status = breakpoint_remove_internal(curr, address);
+			if (target_was_examined(curr) && curr->state == TARGET_HALTED) {
+				int status = breakpoint_remove_internal(curr, address);
 
-			if (status != ERROR_BREAKPOINT_NOT_FOUND) {
-				num_found_breakpoints++;
+				if (status != ERROR_BREAKPOINT_NOT_FOUND) {
+					num_found_breakpoints++;
 
-				if (status != ERROR_OK) {
-					LOG_TARGET_ERROR(curr, "failed to remove breakpoint at address " TARGET_ADDR_FMT, address);
-					retval = status;
+					if (status != ERROR_OK) {
+						LOG_TARGET_ERROR(curr, "failed to remove breakpoint at address " TARGET_ADDR_FMT, address);
+						retval = status;
+					}
 				}
 			}
 		}
-
 	} else {
 		retval = breakpoint_remove_internal(target, address);
 
@@ -396,6 +422,7 @@ static int watchpoint_free(struct target *target, struct watchpoint *watchpoint_
 
 	if (!watchpoint)
 		return ERROR_OK;
+
 	retval = target_remove_watchpoint(target, watchpoint);
 	if (retval != ERROR_OK) {
 		LOG_TARGET_ERROR(target, "could not remove watchpoint #%d on this target",
@@ -436,14 +463,16 @@ static int breakpoint_watchpoint_remove_all(struct target *target, enum breakpoi
 		foreach_smp_target(head, target->smp_targets) {
 			struct target *curr = head->target;
 
-			int status = ERROR_OK;
-			if (bp_wp == BREAKPOINT)
-				status = breakpoint_remove_all_internal(curr);
-			else
-				status = watchpoint_remove_all_internal(curr);
+			if (target_was_examined(curr) && curr->state == TARGET_HALTED) {
+				int status = ERROR_OK;
+				if (bp_wp == BREAKPOINT)
+					status = breakpoint_remove_all_internal(curr);
+				else
+					status = watchpoint_remove_all_internal(curr);
 
-			if (status != ERROR_OK)
-				retval = status;
+				if (status != ERROR_OK)
+					retval = status;
+			}
 		}
 	} else {
 		if (bp_wp == BREAKPOINT)
@@ -468,16 +497,18 @@ int watchpoint_remove_all(struct target *target)
 int breakpoint_clear_target(struct target *target)
 {
 	int retval = ERROR_OK;
-
 	if (target->smp) {
 		struct target_list *head;
 
 		foreach_smp_target(head, target->smp_targets) {
 			struct target *curr = head->target;
-			int status = breakpoint_remove_all_internal(curr);
 
-			if (status != ERROR_OK)
-				retval = status;
+			if (target_was_examined(curr) && curr->state == TARGET_HALTED) {
+				int status = breakpoint_remove_all_internal(curr);
+
+				if (status != ERROR_OK)
+					retval = status;
+			}
 		}
 	} else {
 		retval = breakpoint_remove_all_internal(target);
@@ -569,13 +600,22 @@ int watchpoint_add(struct target *target, target_addr_t address,
 		unsigned int length, enum watchpoint_rw rw, uint64_t value, uint64_t mask)
 {
 	if (target->smp) {
+		bool watchpoint_set = false;
 		struct target_list *head;
 
 		foreach_smp_target(head, target->smp_targets) {
 			struct target *curr = head->target;
-			int retval = watchpoint_add_internal(curr, address, length, rw, value, mask);
-			if (retval != ERROR_OK)
-				return retval;
+			if (target_was_examined(curr) && curr->state == TARGET_HALTED) {
+				int retval = watchpoint_add_internal(curr, address, length, rw, value, mask);
+				if (retval != ERROR_OK)
+					return retval;
+				watchpoint_set = true;
+			}
+		}
+
+		if (!watchpoint_set) {
+			LOG_ERROR("Unable to set watchpoint. All SMP targets are in the examine deferred state.");
+			return ERROR_FAIL;
 		}
 
 		return ERROR_OK;
@@ -611,14 +651,16 @@ int watchpoint_remove(struct target *target, target_addr_t address)
 
 		foreach_smp_target(head, target->smp_targets) {
 			struct target *curr = head->target;
-			int status = watchpoint_remove_internal(curr, address);
+			if (target_was_examined(curr) && curr->state == TARGET_HALTED) {
+				int status = watchpoint_remove_internal(curr, address);
 
-			if (status != ERROR_WATCHPOINT_NOT_FOUND) {
-				num_found_watchpoints++;
+				if (status != ERROR_WATCHPOINT_NOT_FOUND) {
+					num_found_watchpoints++;
 
-				if (status != ERROR_OK) {
-					LOG_TARGET_ERROR(curr, "failed to remove watchpoint at address " TARGET_ADDR_FMT, address);
-					retval = status;
+					if (status != ERROR_OK) {
+						LOG_TARGET_ERROR(curr, "failed to remove watchpoint at address " TARGET_ADDR_FMT, address);
+						retval = status;
+					}
 				}
 			}
 		}

-- 

[PATCH]: 0afaa0b7b5 openocd.c: 'init' should fail if GDB service cannot be created

[<ge...@op...>]

This is an automated email from Gerrit.

"Jan Matyas <jan...@co...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8957

-- gerrit

commit 0afaa0b7b5b63ee3b51ee73d0a72a16e5f1927e5
Author: Jan Matyas <jan...@co...>
Date:   Tue Jun 17 13:17:23 2025 +0200

    openocd.c: 'init' should fail if GDB service cannot be created
    
    If it is not possible to create a GDB service for a certain target
    (for example the given TCP port is already occupied), the "init"
    command should fail, but it currently does not.
    
    Fix this by checking the return code of gdb_target_add_all().
    
    Steps to reproduce:
    
    1) Make the port 3333/tcp occupied. For example by:
    
       nc -l 3333
    
    2) In another terminal, launch OpenOCD. Use the gdb_port
       3333 (which is the default). For example:
    
       path/to/your/openocd \
          -c "adapter driver ..." \
          -c "jtag newtap ..."
          -c "target create ..."
    
    3) Observe the outcome:
    
       Before this patch:
    
       Error "couldn't bind gdb to socket on port 3333: Address already in use"
       is displayed but OpenOCD keeps running.
    
       After this patch:
    
       The error message is displayed and OpenOCD exits - as expected.
    
    Change-Id: I63c283a9a1095167b78e69e9ee879c378a6b9f2a
    Signed-off-by: Jan Matyas <jan...@co...>

diff --git a/src/openocd.c b/src/openocd.c
index 3fbece3955..e63a9661a3 100644
--- a/src/openocd.c
+++ b/src/openocd.c
@@ -170,7 +170,8 @@ COMMAND_HANDLER(handle_init_command)
 	jtag_poll_unmask(save_poll_mask);
 
 	/* initialize telnet subsystem */
-	gdb_target_add_all(all_targets);
+	if (gdb_target_add_all(all_targets) != ERROR_OK)
+		return ERROR_FAIL;
 
 	target_register_event_callback(log_target_callback_event_handler, CMD_CTX);
 

-- 

[PATCH]: c98954f893 jimtcl: anticipate possible change in jimtcl

[<ge...@op...>]

This is an automated email from Gerrit.

"Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8956

-- gerrit

commit c98954f893d2d608f0b3dd041862c1717d116b9c
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Sep 28 17:58:51 2024 +0200

    jimtcl: anticipate possible change in jimtcl
    
    Current jimtcl release 0.83 has been tagged on 2024-08-28 and the
    new 0.84 is on the way.
    
    A new change [1] in jimtcl branch 'master-next', potentially to be
    merged in 0.85, breaks the build of OpenOCD.
    OpenOCD releases are not frequent and jimtcl is now by default an
    external build dependency. The change [1], once gets merged, would
    force OpenOCD to deliver a fix release to support it.
    
    Anticipate the change [1] by detecting it at compile time, without
    relying on jimtcl version, and providing an alternative code.
    
    Link: https://github.com/msteveb/jimtcl/commit/b09e50834824 [1]
    Change-Id: I61bf100d447083258aea222aaf15608b7cbe2e57
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/src/helper/command.c b/src/helper/command.c
index b70081a4dd..04f4f9a54c 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -45,17 +45,22 @@ static enum command_mode get_command_mode(Jim_Interp *interp, const char *cmd_na
 /* set of functions to wrap jimtcl internal data */
 static inline bool jimcmd_is_proc(Jim_Cmd *cmd)
 {
+#if defined(JIM_CMD_ISPROC)
+	// JIM_VERSION >= 84
+	return cmd->flags & JIM_CMD_ISPROC;
+#else
 	return cmd->isproc;
+#endif
 }
 
 bool jimcmd_is_oocd_command(Jim_Cmd *cmd)
 {
-	return !cmd->isproc && cmd->u.native.cmdProc == jim_command_dispatch;
+	return !jimcmd_is_proc(cmd) && cmd->u.native.cmdProc == jim_command_dispatch;
 }
 
 void *jimcmd_privdata(Jim_Cmd *cmd)
 {
-	return cmd->isproc ? NULL : cmd->u.native.privData;
+	return jimcmd_is_proc(cmd) ? NULL : cmd->u.native.privData;
 }
 
 static int command_retval_set(Jim_Interp *interp, int retval)

-- 

[PATCH]: 136ab3e972 Fix 'find' and 'ocd_find' usage

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8955

-- gerrit

commit 136ab3e97265b9e37d49b9e0bd88ae031c08960d
Author: Marc Schink <de...@za...>
Date:   Mon Jun 16 10:04:44 2025 +0200

    Fix 'find' and 'ocd_find' usage
    
    Remove the quotation marks as they are used for strings and not
    parameter names.
    
    Change-Id: Ib0629e1465f821f91cd1e837f4ef8c752013b6b7
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 4ad66ee5f4..db63fe06db 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1382,11 +1382,11 @@ Read the OpenOCD source code (and Developer's Guide)
 if you have a new kind of hardware interface
 and need to provide a driver for it.
 
-@deffn {Command} {find} 'filename'
+@deffn {Command} {find} filename
 Prints full path to @var{filename} according to OpenOCD search rules.
 @end deffn
 
-@deffn {Command} {ocd_find} 'filename'
+@deffn {Command} {ocd_find} filename
 Prints full path to @var{filename} according to OpenOCD search rules. This
 is a low level function used by the @command{find}. Usually you want
 to use @command{find}, instead.

-- 

[PATCH]: c56306f4ff doc: Fix 'add_script_search_dir' usage

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8954

-- gerrit

commit c56306f4ff3c68ddb74d836eb0c7140dc2d7a120
Author: Marc Schink <de...@za...>
Date:   Sun Jun 15 22:44:53 2025 +0200

    doc: Fix 'add_script_search_dir' usage
    
    The 'directory' parameter is not optional.
    
    Change-Id: Ifbc7b311692157dae0621dfa6d35a24b8fe8cbb2
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 4ad66ee5f4..ec856757d4 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -9335,7 +9335,7 @@ Redirect logging to @var{filename}. If used without an argument or
 stderr.
 @end deffn
 
-@deffn {Command} {add_script_search_dir} [directory]
+@deffn {Command} {add_script_search_dir} directory
 Add @var{directory} to the file/script search path.
 @end deffn
 

-- 

[PATCH]: b2e2bc8bcb target: sort the targets by alphabetic order

[<ge...@op...>]

This is an automated email from Gerrit.

"Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8951

-- gerrit

commit b2e2bc8bcbb04e008b4827fd16f80c17319c1d28
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 14:51:43 2025 +0200

    target: sort the targets by alphabetic order
    
    Add comments to require the list of targets to be kept sorted.
    
    Change-Id: Ie3d7e3f5d55a9f9214dc179c5c986b6682f59412
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/target.c b/src/target/target.c
index fd0e0116b5..8bf654a272 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -71,44 +71,45 @@ static int target_gdb_fileio_end_default(struct target *target, int retcode,
 		int fileio_errno, bool ctrl_c);
 
 static struct target_type *target_types[] = {
+	// Keep in alphabetic order this list of targets
+	&aarch64_target,
+	&arcv2_target,
+	&arm11_target,
+	&arm720t_target,
 	&arm7tdmi_target,
-	&arm9tdmi_target,
 	&arm920t_target,
-	&arm720t_target,
-	&arm966e_target,
-	&arm946e_target,
 	&arm926ejs_target,
-	&fa526_target,
-	&feroceon_target,
-	&dragonite_target,
-	&xscale_target,
-	&xtensa_chip_target,
-	&cortexm_target,
+	&arm946e_target,
+	&arm966e_target,
+	&arm9tdmi_target,
+	&armv8r_target,
+	&avr32_ap7k_target,
+	&avr_target,
 	&cortexa_target,
+	&cortexm_target,
 	&cortexr4_target,
-	&arm11_target,
-	&ls1_sap_target,
-	&mips_m4k_target,
-	&avr_target,
+	&dragonite_target,
 	&dsp563xx_target,
 	&dsp5680xx_target,
-	&testee_target,
-	&avr32_ap7k_target,
-	&hla_target,
-	&esp32_target,
+	&esirisc_target,
 	&esp32s2_target,
 	&esp32s3_target,
+	&esp32_target,
+	&fa526_target,
+	&feroceon_target,
+	&hla_target,
+	&ls1_sap_target,
+	&mem_ap_target,
+	&mips_m4k_target,
+	&mips_mips64_target,
 	&or1k_target,
-	&quark_x10xx_target,
 	&quark_d20xx_target,
-	&stm8_target,
+	&quark_x10xx_target,
 	&riscv_target,
-	&mem_ap_target,
-	&esirisc_target,
-	&arcv2_target,
-	&aarch64_target,
-	&armv8r_target,
-	&mips_mips64_target,
+	&stm8_target,
+	&testee_target,
+	&xscale_target,
+	&xtensa_chip_target,
 	NULL,
 };
 
diff --git a/src/target/target_type.h b/src/target/target_type.h
index 5b0dc5a6c0..a146fab763 100644
--- a/src/target/target_type.h
+++ b/src/target/target_type.h
@@ -307,6 +307,7 @@ struct target_type {
 	unsigned int (*data_bits)(struct target *target);
 };
 
+// Keep in alphabetic order this list of targets
 extern struct target_type aarch64_target;
 extern struct target_type arcv2_target;
 extern struct target_type arm11_target;

-- 

[PATCH]: dddc8c0b71 flash: nand: sort the drivers by alphabetic order

[<ge...@op...>]

This is an automated email from Gerrit.

"Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8948

-- gerrit

commit dddc8c0b7125ddcf448611e247ceec7b9058de51
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 13:53:50 2025 +0200

    flash: nand: sort the drivers by alphabetic order
    
    Add comments to require the list of drivers to be kept sorted.
    
    Change-Id: I21b52cc1f5e679b0ebf7797e204248507f53557b
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/src/flash/nand/driver.c b/src/flash/nand/driver.c
index 5d99102c85..69b3ba9618 100644
--- a/src/flash/nand/driver.c
+++ b/src/flash/nand/driver.c
@@ -14,20 +14,21 @@
 #include "driver.h"
 
 static struct nand_flash_controller *nand_flash_controllers[] = {
-	&nonce_nand_controller,
+	// Keep in alphabetic order the list of drivers
+	&at91sam9_nand_controller,
 	&davinci_nand_controller,
+	&imx31_nand_flash_controller,
 	&lpc3180_nand_controller,
 	&lpc32xx_nand_controller,
+	&mxc_nand_flash_controller,
+	&nonce_nand_controller,
+	&nuc910_nand_controller,
 	&orion_nand_controller,
 	&s3c2410_nand_controller,
 	&s3c2412_nand_controller,
 	&s3c2440_nand_controller,
 	&s3c2443_nand_controller,
 	&s3c6400_nand_controller,
-	&mxc_nand_flash_controller,
-	&imx31_nand_flash_controller,
-	&at91sam9_nand_controller,
-	&nuc910_nand_controller,
 	NULL
 };
 
diff --git a/src/flash/nand/driver.h b/src/flash/nand/driver.h
index 4e84f10fbd..d26e77c75b 100644
--- a/src/flash/nand/driver.h
+++ b/src/flash/nand/driver.h
@@ -89,6 +89,7 @@ typedef int (*nand_driver_walker_t)(struct nand_flash_controller *c, void *);
  */
 int nand_driver_walk(nand_driver_walker_t f, void *x);
 
+// Keep in alphabetic order the list of drivers
 extern struct nand_flash_controller at91sam9_nand_controller;
 extern struct nand_flash_controller davinci_nand_controller;
 extern struct nand_flash_controller imx31_nand_flash_controller;

-- 

[PATCH]: fcff4d61e2 flash: nand: use array size to constraint the loop

[<ge...@op...>]

This is an automated email from Gerrit.

"Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8949

-- gerrit

commit fcff4d61e2aa5e95b5a617ba48a6430f08c5c445
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 13:58:38 2025 +0200

    flash: nand: use array size to constraint the loop
    
    Instead of using NULL terminated arrays to determine the last
    element of the array, use the size of the array.
    
    Change-Id: I532a51a223061348e57bae3bd66ee6b346c1b070
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/src/flash/nand/driver.c b/src/flash/nand/driver.c
index 69b3ba9618..eda033b5b7 100644
--- a/src/flash/nand/driver.c
+++ b/src/flash/nand/driver.c
@@ -10,6 +10,8 @@
 #ifdef HAVE_CONFIG_H
 #include <config.h>
 #endif
+
+#include <helper/types.h>
 #include "core.h"
 #include "driver.h"
 
@@ -29,12 +31,11 @@ static struct nand_flash_controller *nand_flash_controllers[] = {
 	&s3c2440_nand_controller,
 	&s3c2443_nand_controller,
 	&s3c6400_nand_controller,
-	NULL
 };
 
 struct nand_flash_controller *nand_driver_find_by_name(const char *name)
 {
-	for (unsigned int i = 0; nand_flash_controllers[i]; i++) {
+	for (size_t i = 0; i < ARRAY_SIZE(nand_flash_controllers); i++) {
 		struct nand_flash_controller *controller = nand_flash_controllers[i];
 		if (strcmp(name, controller->name) == 0)
 			return controller;
@@ -43,7 +44,7 @@ struct nand_flash_controller *nand_driver_find_by_name(const char *name)
 }
 int nand_driver_walk(nand_driver_walker_t f, void *x)
 {
-	for (unsigned int i = 0; nand_flash_controllers[i]; i++) {
+	for (size_t i = 0; i < ARRAY_SIZE(nand_flash_controllers); i++) {
 		int retval = (*f)(nand_flash_controllers[i], x);
 		if (retval != ERROR_OK)
 			return retval;

-- 

[PATCH]: ba9eb609c7 flash: nor: use array size to constraint the loop

[<ge...@op...>]

This is an automated email from Gerrit.

"Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8947

-- gerrit

commit ba9eb609c7001a6891284c2d1eb2a6c3029fffd7
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 14:02:25 2025 +0200

    flash: nor: use array size to constraint the loop
    
    Instead of using NULL terminated arrays to determine the last
    element of the array, use the size of the array.
    
    Change-Id: Ia3d739b0a9f201ba2e7b1d1244d60c8e5546c9c1
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/src/flash/nor/drivers.c b/src/flash/nor/drivers.c
index 4f468848bc..c67c386af5 100644
--- a/src/flash/nor/drivers.c
+++ b/src/flash/nor/drivers.c
@@ -7,6 +7,8 @@
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
+
+#include <helper/types.h>
 #include "imp.h"
 
 /**
@@ -89,12 +91,11 @@ static const struct flash_driver * const flash_drivers[] = {
 	&xcf_flash,
 	&xmc1xxx_flash,
 	&xmc4xxx_flash,
-	NULL,
 };
 
 const struct flash_driver *flash_driver_find_by_name(const char *name)
 {
-	for (unsigned int i = 0; flash_drivers[i]; i++) {
+	for (size_t i = 0; ARRAY_SIZE(flash_drivers); i++) {
 		if (strcmp(name, flash_drivers[i]->name) == 0)
 			return flash_drivers[i];
 	}

-- 

[PATCH]: eb0aebb3dc target: use array size to constraint the loop

[<ge...@op...>]

This is an automated email from Gerrit.

"Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8952

-- gerrit

commit eb0aebb3dca272ca189215b1ea2050141df70b89
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 15:02:04 2025 +0200

    target: use array size to constraint the loop
    
    Instead of using NULL terminated arrays to determine the last
    element of the array, use the size of the array.
    
    Change-Id: I3cdc0f6aef8a5110073aeef333c439e61fc54032
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/target.c b/src/target/target.c
index 8bf654a272..995adbc9d3 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -110,7 +110,6 @@ static struct target_type *target_types[] = {
 	&testee_target,
 	&xscale_target,
 	&xtensa_chip_target,
-	NULL,
 };
 
 struct target *all_targets;
@@ -5708,7 +5707,6 @@ static const struct command_registration target_instance_command_handlers[] = {
 COMMAND_HANDLER(handle_target_create)
 {
 	int retval = ERROR_OK;
-	int x;
 
 	if (CMD_ARGC < 2)
 		return ERROR_COMMAND_SYNTAX_ERROR;
@@ -5732,15 +5730,16 @@ COMMAND_HANDLER(handle_target_create)
 		LOG_INFO("The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD");
 	}
 	/* now does target type exist */
-	for (x = 0 ; target_types[x] ; x++) {
+	size_t x;
+	for (x = 0 ; x < ARRAY_SIZE(target_types) ; x++) {
 		if (strcmp(cp, target_types[x]->name) == 0) {
 			/* found */
 			break;
 		}
 	}
-	if (!target_types[x]) {
+	if (x == ARRAY_SIZE(target_types)) {
 		char *all = NULL;
-		for (x = 0 ; target_types[x] ; x++) {
+		for (x = 0 ; x < ARRAY_SIZE(target_types) ; x++) {
 			char *prev = all;
 			if (all)
 				all = alloc_printf("%s, %s", all, target_types[x]->name);
@@ -5942,7 +5941,7 @@ COMMAND_HANDLER(handle_target_types)
 	if (CMD_ARGC != 0)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	for (unsigned int x = 0; target_types[x]; x++)
+	for (size_t x = 0; x < ARRAY_SIZE(target_types); x++)
 		command_print(CMD, "%s", target_types[x]->name);
 
 	return ERROR_OK;

-- 

[PATCH]: efae8e54ce rtos: sort the rtos by alphabetic order

[<ge...@op...>]

This is an automated email from Gerrit.

"Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8953

-- gerrit

commit efae8e54cef176f2ebe74e2cc524ff4187848283
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 15:07:50 2025 +0200

    rtos: sort the rtos by alphabetic order
    
    Add comments to require the list of rtos to be kept sorted.
    
    Change-Id: Iecf9250a14f6593d0a24a9f9b8930c0ec8d74bd2
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
index 216129b971..2ccccf1b0d 100644
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@@ -17,20 +17,22 @@
 #include "server/gdb_server.h"
 
 static const struct rtos_type *rtos_types[] = {
-	&threadx_rtos,
-	&freertos_rtos,
-	&ecos_rtos,
-	&linux_rtos,
+	// Keep in alphabetic order this list of rtos, except hwthread
 	&chibios_rtos,
 	&chromium_ec_rtos,
+	&ecos_rtos,
 	&embkernel_rtos,
+	&freertos_rtos,
+	&linux_rtos,
 	&mqx_rtos,
-	&ucos_iii_rtos,
 	&nuttx_rtos,
 	&riot_rtos,
-	&zephyr_rtos,
 	&rtkernel_rtos,
-	/* keep this as last, as it always matches with rtos auto */
+	&threadx_rtos,
+	&ucos_iii_rtos,
+	&zephyr_rtos,
+
+	// keep this as last, as it always matches with rtos auto
 	&hwthread_rtos,
 };
 
diff --git a/src/rtos/rtos.h b/src/rtos/rtos.h
index 05beab1459..dbaa7e8ce8 100644
--- a/src/rtos/rtos.h
+++ b/src/rtos/rtos.h
@@ -136,6 +136,7 @@ int rtos_read_buffer(struct target *target, target_addr_t address,
 int rtos_write_buffer(struct target *target, target_addr_t address,
 		uint32_t size, const uint8_t *buffer);
 
+// Keep in alphabetic order this list of rtos
 extern const struct rtos_type chibios_rtos;
 extern const struct rtos_type chromium_ec_rtos;
 extern const struct rtos_type ecos_rtos;

-- 

[PATCH]: 8ec60b93e5 jtag: interfaces: sort the drivers by alphabetic order

[<ge...@op...>]

This is an automated email from Gerrit.

"Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8950

-- gerrit

commit 8ec60b93e5d0e449de1e3adfb8ef06a62ca8edfc
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 14:39:37 2025 +0200

    jtag: interfaces: sort the drivers by alphabetic order
    
    Add comments to require the list of drivers to be kept sorted.
    While there:
    - align the check on BUILD_PRESTO and BUILD_USB_BLASTER;
    - fix indentation of the closing parenthesis.
    
    Change-Id: Ic78281b1cdfb5bf72ea41427233e76516001b429
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/src/jtag/interface.h b/src/jtag/interface.h
index 475dbed36e..8349973613 100644
--- a/src/jtag/interface.h
+++ b/src/jtag/interface.h
@@ -371,6 +371,7 @@ int adapter_config_trace(bool enabled, enum tpiu_pin_protocol pin_protocol,
 		unsigned int traceclkin_freq, uint16_t *prescaler);
 int adapter_poll_trace(uint8_t *buf, size_t *size);
 
+// Keep in alphabetic order this list of drivers
 extern struct adapter_driver am335xgpio_adapter_driver;
 extern struct adapter_driver amt_jtagaccel_adapter_driver;
 extern struct adapter_driver angie_adapter_driver;
diff --git a/src/jtag/interfaces.c b/src/jtag/interfaces.c
index e49bd9e0f3..834247245b 100644
--- a/src/jtag/interfaces.c
+++ b/src/jtag/interfaces.c
@@ -36,125 +36,128 @@
  * drivers that were enabled by the @c configure script.
  */
 struct adapter_driver *adapter_drivers[] = {
-#if BUILD_PARPORT == 1
-		&parport_adapter_driver,
+		// Keep in alphabetic order this list of drivers
+
+#if BUILD_AM335XGPIO == 1
+		&am335xgpio_adapter_driver,
 #endif
-#if BUILD_DUMMY == 1
-		&dummy_adapter_driver,
+#if BUILD_AMTJTAGACCEL == 1
+		&amt_jtagaccel_adapter_driver,
 #endif
-#if BUILD_FTDI == 1
-		&ftdi_adapter_driver,
+#if BUILD_ANGIE == 1
+		&angie_adapter_driver,
 #endif
-#if BUILD_USB_BLASTER || BUILD_USB_BLASTER_2 == 1
-		&usb_blaster_adapter_driver,
+#if BUILD_ARMJTAGEW == 1
+		&armjtagew_adapter_driver,
 #endif
-#if BUILD_ESP_USB_JTAG == 1
-		&esp_usb_adapter_driver,
+#if BUILD_AT91RM9200 == 1
+		&at91rm9200_adapter_driver,
 #endif
-#if BUILD_JTAG_VPI == 1
-		&jtag_vpi_adapter_driver,
+#if BUILD_BCM2835GPIO == 1
+		&bcm2835gpio_adapter_driver,
 #endif
-#if BUILD_VDEBUG == 1
-		&vdebug_adapter_driver,
+#if BUILD_BUS_PIRATE == 1
+		&buspirate_adapter_driver,
 #endif
-#if BUILD_JTAG_DPI == 1
-		&jtag_dpi_adapter_driver,
+#if BUILD_CMSIS_DAP_USB == 1 || BUILD_CMSIS_DAP_HID == 1
+		&cmsis_dap_adapter_driver,
 #endif
-#if BUILD_FT232R == 1
-		&ft232r_adapter_driver,
+#if BUILD_DMEM == 1
+		&dmem_dap_adapter_driver,
 #endif
-#if BUILD_AMTJTAGACCEL == 1
-		&amt_jtagaccel_adapter_driver,
+#if BUILD_DUMMY == 1
+		&dummy_adapter_driver,
 #endif
 #if BUILD_EP93XX == 1
 		&ep93xx_adapter_driver,
 #endif
-#if BUILD_AT91RM9200 == 1
-		&at91rm9200_adapter_driver,
+#if BUILD_ESP_USB_JTAG == 1
+		&esp_usb_adapter_driver,
+#endif
+#if BUILD_FT232R == 1
+		&ft232r_adapter_driver,
+#endif
+#if BUILD_FTDI == 1
+		&ftdi_adapter_driver,
 #endif
 #if BUILD_GW16012 == 1
 		&gw16012_adapter_driver,
 #endif
-#if BUILD_PRESTO
-		&presto_adapter_driver,
-#endif
-#if BUILD_USBPROG == 1
-		&usbprog_adapter_driver,
+#if BUILD_HLADAPTER == 1
+		&hl_adapter_driver,
 #endif
-#if BUILD_OPENJTAG == 1
-		&openjtag_adapter_driver,
+#if BUILD_IMX_GPIO == 1
+		&imx_gpio_adapter_driver,
 #endif
 #if BUILD_JLINK == 1
 		&jlink_adapter_driver,
 #endif
-#if BUILD_VSLLINK == 1
-		&vsllink_adapter_driver,
-#endif
-#if BUILD_RLINK == 1
-		&rlink_adapter_driver,
+#if BUILD_JTAG_DPI == 1
+		&jtag_dpi_adapter_driver,
 #endif
-#if BUILD_ULINK == 1
-		&ulink_adapter_driver,
+#if BUILD_JTAG_VPI == 1
+		&jtag_vpi_adapter_driver,
 #endif
-#if BUILD_ANGIE == 1
-		&angie_adapter_driver,
+#if BUILD_KITPROG == 1
+		&kitprog_adapter_driver,
 #endif
-#if BUILD_ARMJTAGEW == 1
-		&armjtagew_adapter_driver,
+#if BUILD_LINUXGPIOD == 1
+		&linuxgpiod_adapter_driver,
 #endif
-#if BUILD_BUS_PIRATE == 1
-		&buspirate_adapter_driver,
+#if BUILD_LINUXSPIDEV == 1
+		&linuxspidev_adapter_driver,
 #endif
-#if BUILD_REMOTE_BITBANG == 1
-		&remote_bitbang_adapter_driver,
+#if BUILD_OPENDOUS == 1
+		&opendous_adapter_driver,
 #endif
-#if BUILD_HLADAPTER == 1
-		&hl_adapter_driver,
+#if BUILD_OPENJTAG == 1
+		&openjtag_adapter_driver,
 #endif
 #if BUILD_OSBDM == 1
 		&osbdm_adapter_driver,
 #endif
-#if BUILD_OPENDOUS == 1
-		&opendous_adapter_driver,
+#if BUILD_PARPORT == 1
+		&parport_adapter_driver,
 #endif
-#if BUILD_SYSFSGPIO == 1
-		&sysfsgpio_adapter_driver,
+#if BUILD_PRESTO == 1
+		&presto_adapter_driver,
 #endif
-#if BUILD_LINUXGPIOD == 1
-		&linuxgpiod_adapter_driver,
+#if BUILD_REMOTE_BITBANG == 1
+		&remote_bitbang_adapter_driver,
 #endif
-#if BUILD_LINUXSPIDEV == 1
-		&linuxspidev_adapter_driver,
+#if BUILD_RLINK == 1
+		&rlink_adapter_driver,
 #endif
-#if BUILD_XLNX_PCIE_XVC == 1
-		&xlnx_pcie_xvc_adapter_driver,
+#if BUILD_RSHIM == 1
+		&rshim_dap_adapter_driver,
 #endif
-#if BUILD_BCM2835GPIO == 1
-		&bcm2835gpio_adapter_driver,
+#if BUILD_HLADAPTER_STLINK == 1
+		&stlink_dap_adapter_driver,
 #endif
-#if BUILD_CMSIS_DAP_USB == 1 || BUILD_CMSIS_DAP_HID == 1
-		&cmsis_dap_adapter_driver,
+#if BUILD_SYSFSGPIO == 1
+		&sysfsgpio_adapter_driver,
 #endif
-#if BUILD_KITPROG == 1
-		&kitprog_adapter_driver,
+#if BUILD_ULINK == 1
+		&ulink_adapter_driver,
 #endif
-#if BUILD_IMX_GPIO == 1
-		&imx_gpio_adapter_driver,
+#if BUILD_USB_BLASTER == 1 || BUILD_USB_BLASTER_2 == 1
+		&usb_blaster_adapter_driver,
 #endif
-#if BUILD_XDS110 == 1
-		&xds110_adapter_driver,
+#if BUILD_USBPROG == 1
+		&usbprog_adapter_driver,
 #endif
-#if BUILD_HLADAPTER_STLINK == 1
-		&stlink_dap_adapter_driver,
+#if BUILD_VDEBUG == 1
+		&vdebug_adapter_driver,
 #endif
-#if BUILD_RSHIM == 1
-		&rshim_dap_adapter_driver,
+#if BUILD_VSLLINK == 1
+		&vsllink_adapter_driver,
 #endif
-#if BUILD_DMEM == 1
-		&dmem_dap_adapter_driver,
+#if BUILD_XDS110 == 1
+		&xds110_adapter_driver,
 #endif
-#if BUILD_AM335XGPIO == 1
-		&am335xgpio_adapter_driver,
+#if BUILD_XLNX_PCIE_XVC == 1
+		&xlnx_pcie_xvc_adapter_driver,
 #endif
+
 		NULL,
-	};
+};

-- 

[PATCH]: e1aab59bce flash: nor: sort the drivers by alphabetic order

[<ge...@op...>]

This is an automated email from Gerrit.

"Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8946

-- gerrit

commit e1aab59bcef03e47762e7bf9ddec36cf2dadb93a
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 12:36:07 2025 +0200

    flash: nor: sort the drivers by alphabetic order
    
    Add comments to require the list of drivers to be kept sorted.
    
    Change-Id: I57382605edc6a38d6c1ac18393421b18ae72215b
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/src/flash/nor/driver.h b/src/flash/nor/driver.h
index 3b57ef9ff0..da649e7831 100644
--- a/src/flash/nor/driver.h
+++ b/src/flash/nor/driver.h
@@ -237,6 +237,7 @@ struct flash_driver {
  */
 const struct flash_driver *flash_driver_find_by_name(const char *name);
 
+// Keep in alphabetic order this list of drivers
 extern const struct flash_driver aduc702x_flash;
 extern const struct flash_driver aducm360_flash;
 extern const struct flash_driver ambiqmicro_flash;
diff --git a/src/flash/nor/drivers.c b/src/flash/nor/drivers.c
index 3770bfbd3c..4f468848bc 100644
--- a/src/flash/nor/drivers.c
+++ b/src/flash/nor/drivers.c
@@ -14,6 +14,7 @@
  * @todo Make this dynamically extendable with loadable modules.
  */
 static const struct flash_driver * const flash_drivers[] = {
+	// Keep in alphabetic order the list of drivers
 	&aduc702x_flash,
 	&aducm360_flash,
 	&ambiqmicro_flash,
@@ -27,8 +28,8 @@ static const struct flash_driver * const flash_drivers[] = {
 	&atsamv_flash,
 	&avr_flash,
 	&bluenrgx_flash,
-	&cc3220sf_flash,
 	&cc26xx_flash,
+	&cc3220sf_flash,
 	&cfi_flash,
 	&dsp5680xx_flash,
 	&dw_spi_flash,
@@ -37,9 +38,9 @@ static const struct flash_driver * const flash_drivers[] = {
 	&eneispif_flash,
 	&esirisc_flash,
 	&faux_flash,
+	&fespi_flash,
 	&fm3_flash,
 	&fm4_flash,
-	&fespi_flash,
 	&jtagspi_flash,
 	&kinetis_flash,
 	&kinetis_ke_flash,
@@ -54,40 +55,40 @@ static const struct flash_driver * const flash_drivers[] = {
 	&mspm0_flash,
 	&niietcm4_flash,
 	&npcx_flash,
-	&nrf5_flash,
 	&nrf51_flash,
+	&nrf5_flash,
 	&numicro_flash,
 	&ocl_flash,
 	&pic32mx_flash,
 	&psoc4_flash,
-	&psoc5lp_flash,
 	&psoc5lp_eeprom_flash,
+	&psoc5lp_flash,
 	&psoc5lp_nvl_flash,
 	&psoc6_flash,
 	&qn908x_flash,
 	&renesas_rpchf_flash,
 	&rp2xxx_flash,
+	&rsl10_flash,
 	&sh_qspi_flash,
 	&sim3x_flash,
 	&stellaris_flash,
 	&stm32f1x_flash,
 	&stm32f2x_flash,
-	&stm32lx_flash,
-	&stm32l4x_flash,
 	&stm32h7x_flash,
-	&stmsmi_flash,
+	&stm32l4x_flash,
+	&stm32lx_flash,
 	&stmqspi_flash,
+	&stmsmi_flash,
 	&str7x_flash,
 	&str9x_flash,
 	&str9xpec_flash,
 	&swm050_flash,
 	&tms470_flash,
 	&virtual_flash,
+	&w600_flash,
 	&xcf_flash,
 	&xmc1xxx_flash,
 	&xmc4xxx_flash,
-	&w600_flash,
-	&rsl10_flash,
 	NULL,
 };
 

-- 

[PATCH]: dfe9edbb5c target/cortex_m: fix debug reason after reset halt

[<ge...@op...>]

This is an automated email from Gerrit.

"Tomas Vanek <va...@fb...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8945

-- gerrit

commit dfe9edbb5cdf2503ba80b0c8f2001fdd8f0f6bda
Author: Tomas Vanek <va...@fb...>
Date:   Sat Jun 14 12:18:53 2025 +0200

    target/cortex_m: fix debug reason after reset halt
    
    [1] removed target_halt() from cortex_m_assert_reset()
    It broke debug_reason tracking and the previous reason
    was shown after reset halt.
    
    Set debug_reason to DBG_REASON_DBGRQ during reset halt
    preparation.
    
    Fixes: [1] commit 226085065bdf ("target/cortex_m: drop useless target_halt() call")
    Reported-by: Marc Schink <de...@za...>
    Change-Id: I685618ed158abde11f6e00eeeee1dfa8ed90952d
    Signed-off-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index ba9d83d79f..8eaf70f60a 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -1779,6 +1779,7 @@ static int cortex_m_assert_reset(struct target *target)
 		int retval2;
 		retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
 				TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
+		target->debug_reason = DBG_REASON_DBGRQ;
 		if (retval != ERROR_OK || retval2 != ERROR_OK)
 			LOG_TARGET_INFO(target, "AP write error, reset will not halt");
 	}

-- 

[PATCH]: 1127de9033 jep106: update to revision JEP106BM Jun 2025

[<ge...@op...>]

This is an automated email from Gerrit.

"Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8944

-- gerrit

commit 1127de903369d1d5c0ede5591a56b60ae5a7c662
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 09:52:57 2025 +0200

    jep106: update to revision JEP106BM Jun 2025
    
    Update to latest available document.
    
    Change-Id: Ic1c892b42d3efbb35ad4a6c85deb17ab31ad9997
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/src/helper/jep106.inc b/src/helper/jep106.inc
index 8bbaf4ca5c..5e50e19550 100644
--- a/src/helper/jep106.inc
+++ b/src/helper/jep106.inc
@@ -8,7 +8,7 @@
  * identification code list, please visit the JEDEC website at www.jedec.org .
  */
 
-/* This file is aligned to revision JEP106BL February 2025. */
+/* This file is aligned to revision JEP106BM June 2025. */
 
 [0][0x01 - 1] = "AMD",
 [0][0x02 - 1] = "AMI",
@@ -78,7 +78,7 @@
 [0][0x42 - 1] = "Macronix",
 [0][0x43 - 1] = "Xerox",
 [0][0x44 - 1] = "Plus Logic",
-[0][0x45 - 1] = "Western Digital Technologies Inc",
+[0][0x45 - 1] = "SanDisk Technologies Inc",
 [0][0x46 - 1] = "Elan Circuit Tech.",
 [0][0x47 - 1] = "European Silicon Str.",
 [0][0x48 - 1] = "Apple Computer",
@@ -1798,7 +1798,7 @@
 [14][0x16 - 1] = "Chiplego Technology (Shanghai) Co Ltd",
 [14][0x17 - 1] = "StoreSkill",
 [14][0x18 - 1] = "Shenzhen Astou Technology Company",
-[14][0x19 - 1] = "Guangdong LeafFive Technology Limited",
+[14][0x19 - 1] = "Guangdong LeapFive Technology Limited",
 [14][0x1a - 1] = "Jin JuQuan",
 [14][0x1b - 1] = "Huaxuan Technology (Shenzhen) Co Ltd",
 [14][0x1c - 1] = "Gigastone Corporation",
@@ -2049,4 +2049,39 @@
 [16][0x15 - 1] = "Hangzhou Lishu Technology Co Ltd",
 [16][0x16 - 1] = "Tier IV Inc",
 [16][0x17 - 1] = "Wuhan Xuanluzhe Network Technology Co",
+[16][0x18 - 1] = "EA Semi (Shanghai) Limited",
+[16][0x19 - 1] = "Tech Vision Information Technology Co",
+[16][0x1a - 1] = "Zhihe Computing Technology",
+[16][0x1b - 1] = "Beijing Apexichips Tech",
+[16][0x1c - 1] = "Yemas Holdingsl Limited",
+[16][0x1d - 1] = "Eluktronics",
+[16][0x1e - 1] = "Walton Digi-Tech Industries Ltd",
+[16][0x1f - 1] = "Beijing Qixin Gongli Technology Co Ltd",
+[16][0x20 - 1] = "M.RED",
+[16][0x21 - 1] = "Shenzhen Damay Semiconductor Co Ltd",
+[16][0x22 - 1] = "Corelab Tech Singapore Holding PTE LTD",
+[16][0x23 - 1] = "EmBestor Technology Inc",
+[16][0x24 - 1] = "XConn Technologies",
+[16][0x25 - 1] = "Flagchip",
+[16][0x26 - 1] = "CUNNUC",
+[16][0x27 - 1] = "SGMicro",
+[16][0x28 - 1] = "Lanxin Computing (Shenzhen) Technology",
+[16][0x29 - 1] = "FuturePlus Systems LLC",
+[16][0x2a - 1] = "Shenzhen Jielong Storage Technology Co",
+[16][0x2b - 1] = "Precision Planting LLC",
+[16][0x2c - 1] = "Sichuan ZeroneStor Microelectronics Tech",
+[16][0x2d - 1] = "The University of Tokyo",
+[16][0x2e - 1] = "Aodu (Fujian) Information Technology Co",
+[16][0x2f - 1] = "Bytera Memory Inc",
+[16][0x30 - 1] = "XSemitron Technology Inc",
+[16][0x31 - 1] = "Cloud Ridge Ltd",
+[16][0x32 - 1] = "Shenzhen XinChiTai Technology Co Ltd",
+[16][0x33 - 1] = "Shenzhen Xinxin Semiconductor Co Ltd",
+[16][0x34 - 1] = "Shenzhen ShineKing Electronics Co Ltd.",
+[16][0x35 - 1] = "Shenzhen Shande Semiconductor Co. Ltd.",
+[16][0x36 - 1] = "AheadComputing",
+[16][0x37 - 1] = "Beijing Ronghua Kangweiye Technology",
+[16][0x38 - 1] = "Shanghai Yunsilicon Technology Co Ltd",
+[16][0x39 - 1] = "Shenzhen Wolongtai Technology Co Ltd.",
+[16][0x3a - 1] = "Vervesemi Microelectronics",
 /* EOF */

--