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[PATCH]: d5a65e9d98 flash/stm32h7x: Refactor STM32H7 flash register definitions to use enum

[<ge...@op...>]

This is an automated email from Gerrit.

"Ahmed Haoues <ahm...@st...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8888

-- gerrit

commit d5a65e9d983acd592c2ba7f9b4f6abd865bd72cf
Author: HAOUES Ahmed <ahm...@st...>
Date:   Wed Jun 25 15:33:25 2025 +0100

    flash/stm32h7x: Refactor STM32H7 flash register definitions to use enum
    
    Replace individual #define constants for STM32H7 flash registers with an
    enum to improve code readability and maintainability.
    
    Change-Id: Ib35cbdace5c2f4d12aa91c370d6ec0ce348b397f
    Signed-off-by: HAOUES Ahmed <ahm...@st...>

diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c
index c02fae992c..6ecd265957 100644
--- a/src/flash/nor/stm32h7x.c
+++ b/src/flash/nor/stm32h7x.c
@@ -12,27 +12,47 @@
 #include <target/algorithm.h>
 #include <target/cortex_m.h>
 
-
 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
 #define FLASH_ERASE_TIMEOUT 10000
 #define FLASH_WRITE_TIMEOUT 5
+#define MASS_ERASE_TIMEOUT 30000
+
+enum stm32h7_flash_reg_index {
+	STM32_FLASH_ACR_INDEX,
+	STM32_FLASH_KEYR_INDEX,
+	STM32_FLASH_OPTKEYR_INDEX,
+	STM32_FLASH_SR_INDEX,
+	STM32_FLASH_CR_INDEX,
+	STM32_FLASH_ICR_INDEX,
+	STM32_FLASH_CCR_INDEX,
+	STM32_FLASH_OPTCR_INDEX,
+	STM32_FLASH_OPTSR_INDEX,
+	STM32_FLASH_OPTSR_CUR_INDEX,
+	STM32_FLASH_OPTSR_PRG_INDEX,
+	STM32_FLASH_OPTCCR_INDEX,
+	STM32_FLASH_WPSN_CUR_INDEX,
+	STM32_FLASH_WPSN_PRG_INDEX,
+	STM32_FLASH_ISR_INDEX,
+	STM32_FLASH_REG_INDEX_NUM,
+};
 
 /* RM 433 */
 /* Same Flash registers for both banks, */
 /* access depends on Flash Base address */
-#define FLASH_ACR       0x00
-#define FLASH_KEYR      0x04
-#define FLASH_OPTKEYR   0x08
-#define FLASH_CR        0x0C
-#define FLASH_SR        0x10
-#define FLASH_CCR       0x14
-#define FLASH_OPTCR     0x18
-#define FLASH_OPTSR_CUR 0x1C
-#define FLASH_OPTSR_PRG 0x20
-#define FLASH_OPTCCR    0x24
-#define FLASH_WPSN_CUR  0x38
-#define FLASH_WPSN_PRG  0x3C
-
+static const uint32_t stm32h7_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
+	[STM32_FLASH_ACR_INDEX]			= 0x00,
+	[STM32_FLASH_KEYR_INDEX]		= 0x04,
+	[STM32_FLASH_OPTKEYR_INDEX]		= 0x08,
+	[STM32_FLASH_SR_INDEX]			= 0x10,
+	[STM32_FLASH_CR_INDEX]			= 0x0C,
+	[STM32_FLASH_CCR_INDEX]			= 0x14,
+	[STM32_FLASH_OPTCR_INDEX]		= 0x18,
+	[STM32_FLASH_OPTSR_CUR_INDEX]	= 0x1C,
+	[STM32_FLASH_OPTSR_PRG_INDEX]	= 0x20,
+	[STM32_FLASH_OPTCCR_INDEX]		= 0x24,
+	[STM32_FLASH_WPSN_CUR_INDEX]	= 0x38,
+	[STM32_FLASH_WPSN_PRG_INDEX]	= 0x3C
+};
 
 /* FLASH_CR register bits */
 #define FLASH_LOCK     (1 << 0)
@@ -117,6 +137,7 @@ struct stm32h7x_part_info {
 	uint32_t wps_mask;
 	/* function to compute flash_cr register values */
 	uint32_t (*compute_flash_cr)(uint32_t cmd, int snb);
+	int (*get_flash_error_status)(struct flash_bank *bank, uint32_t *status);
 };
 
 struct stm32h7x_flash_bank {
@@ -124,6 +145,7 @@ struct stm32h7x_flash_bank {
 	uint32_t idcode;
 	uint32_t user_bank_size;
 	uint32_t flash_regs_base;    /* Address of flash reg controller */
+	const uint32_t *flash_regs;
 	const struct stm32h7x_part_info *part_info;
 };
 
@@ -161,51 +183,56 @@ static uint32_t stm32h7a_h7bxx_compute_flash_cr(uint32_t cmd, int snb)
 	return cmd | (tmp >> 2) | (snb << 6);
 }
 
+static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status);
+
 static const struct stm32h7x_part_info stm32h7x_parts[] = {
 	{
-	.id					= DEVID_STM32H74_H75XX,
-	.revs				= stm32h74_h75xx_revs,
-	.num_revs			= ARRAY_SIZE(stm32h74_h75xx_revs),
-	.device_str			= "STM32H74x/75x",
-	.page_size_kb		= 128,
-	.block_size			= 32,
-	.max_flash_size_kb	= 2048,
-	.max_bank_size_kb	= 1024,
-	.has_dual_bank		= true,
-	.fsize_addr			= 0x1FF1E880,
-	.wps_group_size		= 1,
-	.wps_mask			= 0xFF,
-	.compute_flash_cr	= stm32h74_h75xx_compute_flash_cr,
+	.id					    = DEVID_STM32H74_H75XX,
+	.revs				    = stm32h74_h75xx_revs,
+	.num_revs			    = ARRAY_SIZE(stm32h74_h75xx_revs),
+	.device_str			    = "STM32H74x/75x",
+	.page_size_kb		    = 128,
+	.block_size			    = 32,
+	.max_flash_size_kb	    = 2048,
+	.max_bank_size_kb	    = 1024,
+	.has_dual_bank		    = true,
+	.fsize_addr			    = 0x1FF1E880,
+	.wps_group_size		    = 1,
+	.wps_mask			    = 0xFF,
+	.compute_flash_cr	    = stm32h74_h75xx_compute_flash_cr,
+	.get_flash_error_status = stm32x_get_flash_status,
 	},
 	{
-	.id					= DEVID_STM32H7A_H7BXX,
-	.revs				= stm32h7a_h7bxx_revs,
-	.num_revs			= ARRAY_SIZE(stm32h7a_h7bxx_revs),
-	.device_str			= "STM32H7Ax/7Bx",
-	.page_size_kb		= 8,
-	.block_size			= 16,
-	.max_flash_size_kb	= 2048,
-	.max_bank_size_kb	= 1024,
-	.has_dual_bank		= true,
-	.fsize_addr			= 0x08FFF80C,
-	.wps_group_size		= 4,
-	.wps_mask			= 0xFFFFFFFF,
-	.compute_flash_cr	= stm32h7a_h7bxx_compute_flash_cr,
+	.id					    = DEVID_STM32H7A_H7BXX,
+	.revs				    = stm32h7a_h7bxx_revs,
+	.num_revs			    = ARRAY_SIZE(stm32h7a_h7bxx_revs),
+	.device_str			    = "STM32H7Ax/7Bx",
+	.page_size_kb		    = 8,
+	.block_size			    = 16,
+	.max_flash_size_kb	    = 2048,
+	.max_bank_size_kb	    = 1024,
+	.has_dual_bank		    = true,
+	.fsize_addr			    = 0x08FFF80C,
+	.wps_group_size		    = 4,
+	.wps_mask			    = 0xFFFFFFFF,
+	.compute_flash_cr	    = stm32h7a_h7bxx_compute_flash_cr,
+	.get_flash_error_status = stm32x_get_flash_status,
 	},
 	{
-	.id					= DEVID_STM32H72_H73XX,
-	.revs				= stm32h72_h73xx_revs,
-	.num_revs			= ARRAY_SIZE(stm32h72_h73xx_revs),
-	.device_str			= "STM32H72x/73x",
-	.page_size_kb		= 128,
-	.block_size			= 32,
-	.max_flash_size_kb	= 1024,
-	.max_bank_size_kb	= 1024,
-	.has_dual_bank		= false,
-	.fsize_addr			= 0x1FF1E880,
-	.wps_group_size		= 1,
-	.wps_mask			= 0xFF,
-	.compute_flash_cr   = stm32h74_h75xx_compute_flash_cr,
+	.id					    = DEVID_STM32H72_H73XX,
+	.revs				    = stm32h72_h73xx_revs,
+	.num_revs			    = ARRAY_SIZE(stm32h72_h73xx_revs),
+	.device_str			    = "STM32H72x/73x",
+	.page_size_kb		    = 128,
+	.block_size			    = 32,
+	.max_flash_size_kb	    = 1024,
+	.max_bank_size_kb	    = 1024,
+	.has_dual_bank		    = false,
+	.fsize_addr			    = 0x1FF1E880,
+	.wps_group_size		    = 1,
+	.wps_mask			    = 0xFF,
+	.compute_flash_cr       = stm32h74_h75xx_compute_flash_cr,
+	.get_flash_error_status = stm32x_get_flash_status,
 	},
 };
 
@@ -244,6 +271,13 @@ static inline int stm32x_read_flash_reg(struct flash_bank *bank, uint32_t reg_of
 	return retval;
 }
 
+static inline int stm32x_read_flash_reg_by_index(struct flash_bank *bank,
+	enum stm32h7_flash_reg_index reg_index, uint32_t *value)
+{
+	struct stm32h7x_flash_bank *stm32h7_info = bank->driver_priv;
+	return stm32x_read_flash_reg(bank, stm32h7_info->flash_regs[reg_index], value);
+}
+
 static inline int stm32x_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
 {
 	uint32_t reg_addr = stm32x_get_flash_reg(bank, reg_offset);
@@ -255,9 +289,16 @@ static inline int stm32x_write_flash_reg(struct flash_bank *bank, uint32_t reg_o
 	return retval;
 }
 
+static inline int stm32x_write_flash_reg_by_index(struct flash_bank *bank,
+	enum stm32h7_flash_reg_index reg_index, uint32_t value)
+{
+	struct stm32h7x_flash_bank *stm32h7_info = bank->driver_priv;
+	return stm32x_write_flash_reg(bank, stm32h7_info->flash_regs[reg_index], value);
+}
+
 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 {
-	return stm32x_read_flash_reg(bank, FLASH_SR, status);
+	return stm32x_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, status);
 }
 
 static int stm32x_wait_flash_op_queue(struct flash_bank *bank, int timeout)
@@ -291,7 +332,7 @@ static int stm32x_wait_flash_op_queue(struct flash_bank *bank, int timeout)
 		if (retval == ERROR_OK)
 			retval = ERROR_FAIL;
 		/* If this operation fails, we ignore it and report the original retval */
-		stm32x_write_flash_reg(bank, FLASH_CCR, status);
+		stm32x_write_flash_reg_by_index(bank, STM32_FLASH_CCR_INDEX, status);
 	}
 	return retval;
 }
@@ -303,7 +344,7 @@ static int stm32x_unlock_reg(struct flash_bank *bank)
 	/* first check if not already unlocked
 	 * otherwise writing on FLASH_KEYR will fail
 	 */
-	int retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl);
+	int retval = stm32x_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -311,15 +352,15 @@ static int stm32x_unlock_reg(struct flash_bank *bank)
 		return ERROR_OK;
 
 	/* unlock flash registers for bank */
-	retval = stm32x_write_flash_reg(bank, FLASH_KEYR, KEY1);
+	retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY1);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = stm32x_write_flash_reg(bank, FLASH_KEYR, KEY2);
+	retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY2);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl);
+	retval = stm32x_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -334,7 +375,7 @@ static int stm32x_unlock_option_reg(struct flash_bank *bank)
 {
 	uint32_t ctrl;
 
-	int retval = stm32x_read_flash_reg(bank, FLASH_OPTCR, &ctrl);
+	int retval = stm32x_read_flash_reg_by_index(bank, STM32_FLASH_OPTCR_INDEX, &ctrl);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -342,15 +383,15 @@ static int stm32x_unlock_option_reg(struct flash_bank *bank)
 		return ERROR_OK;
 
 	/* unlock option registers */
-	retval = stm32x_write_flash_reg(bank, FLASH_OPTKEYR, OPTKEY1);
+	retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY1);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = stm32x_write_flash_reg(bank, FLASH_OPTKEYR, OPTKEY2);
+	retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY2);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = stm32x_read_flash_reg(bank, FLASH_OPTCR, &ctrl);
+	retval = stm32x_read_flash_reg_by_index(bank, STM32_FLASH_OPTCR_INDEX, &ctrl);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -364,12 +405,12 @@ static int stm32x_unlock_option_reg(struct flash_bank *bank)
 
 static inline int stm32x_lock_reg(struct flash_bank *bank)
 {
-	return stm32x_write_flash_reg(bank, FLASH_CR, FLASH_LOCK);
+	return stm32x_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
 }
 
 static inline int stm32x_lock_option_reg(struct flash_bank *bank)
 {
-	return stm32x_write_flash_reg(bank, FLASH_OPTCR, OPT_LOCK);
+	return stm32x_write_flash_reg_by_index(bank, STM32_FLASH_OPTCR_INDEX, OPT_LOCK);
 }
 
 static int stm32x_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
@@ -382,17 +423,17 @@ static int stm32x_write_option(struct flash_bank *bank, uint32_t reg_offset, uin
 		goto flash_options_lock;
 
 	/* write option bytes */
-	retval = stm32x_write_flash_reg(bank, reg_offset, value);
+	retval = stm32x_write_flash_reg_by_index(bank, reg_offset, value);
 	if (retval != ERROR_OK)
 		goto flash_options_lock;
 
 	/* Remove OPT error flag before programming */
-	retval = stm32x_write_flash_reg(bank, FLASH_OPTCCR, OPT_CLR_OPTCHANGEERR);
+	retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_OPTCCR_INDEX, OPT_CLR_OPTCHANGEERR);
 	if (retval != ERROR_OK)
 		goto flash_options_lock;
 
 	/* start programming cycle */
-	retval = stm32x_write_flash_reg(bank, FLASH_OPTCR, OPT_START);
+	retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_OPTCR_INDEX, OPT_START);
 	if (retval != ERROR_OK)
 		goto flash_options_lock;
 
@@ -400,7 +441,7 @@ static int stm32x_write_option(struct flash_bank *bank, uint32_t reg_offset, uin
 	int timeout = FLASH_ERASE_TIMEOUT;
 	uint32_t status;
 	for (;;) {
-		retval = stm32x_read_flash_reg(bank, FLASH_OPTSR_CUR, &status);
+		retval = stm32x_read_flash_reg_by_index(bank, STM32_FLASH_OPTSR_CUR_INDEX, &status);
 		if (retval != ERROR_OK) {
 			LOG_ERROR("stm32x_options_program: failed to read FLASH_OPTSR_CUR");
 			goto flash_options_lock;
@@ -434,7 +475,7 @@ static int stm32x_modify_option(struct flash_bank *bank, uint32_t reg_offset, ui
 {
 	uint32_t data;
 
-	int retval = stm32x_read_flash_reg(bank, reg_offset, &data);
+	int retval = stm32x_read_flash_reg_by_index(bank, reg_offset, &data);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -448,7 +489,7 @@ static int stm32x_protect_check(struct flash_bank *bank)
 	uint32_t protection;
 
 	/* read 'write protection' settings */
-	int retval = stm32x_read_flash_reg(bank, FLASH_WPSN_CUR, &protection);
+	int retval = stm32x_read_flash_reg_by_index(bank, STM32_FLASH_WPSN_CUR_INDEX, &protection);
 	if (retval != ERROR_OK) {
 		LOG_DEBUG("unable to read WPSN_CUR register");
 		return retval;
@@ -488,13 +529,13 @@ static int stm32x_erase(struct flash_bank *bank, unsigned int first,
 	 */
 	for (unsigned int i = first; i <= last; i++) {
 		LOG_DEBUG("erase sector %u", i);
-		retval = stm32x_write_flash_reg(bank, FLASH_CR,
+		retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX,
 				stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64, i));
 		if (retval != ERROR_OK) {
 			LOG_ERROR("Error erase sector %u", i);
 			goto flash_lock;
 		}
-		retval = stm32x_write_flash_reg(bank, FLASH_CR,
+		retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX,
 				stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64 | FLASH_START, i));
 		if (retval != ERROR_OK) {
 			LOG_ERROR("Error erase sector %u", i);
@@ -529,7 +570,7 @@ static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
 	}
 
 	/* read 'write protection' settings */
-	int retval = stm32x_read_flash_reg(bank, FLASH_WPSN_CUR, &protection);
+	int retval = stm32x_read_flash_reg_by_index(bank, STM32_FLASH_WPSN_CUR_INDEX, &protection);
 	if (retval != ERROR_OK) {
 		LOG_DEBUG("unable to read WPSN_CUR register");
 		return retval;
@@ -548,7 +589,7 @@ static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
 	LOG_DEBUG("stm32x_protect, option_bytes written WPSN 0x%" PRIx32, protection);
 
 	/* apply new option value */
-	return stm32x_write_option(bank, FLASH_WPSN_PRG, protection);
+	return stm32x_write_option(bank, STM32_FLASH_WPSN_PRG_INDEX, protection);
 }
 
 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
@@ -641,7 +682,7 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 		if ((flash_sr & FLASH_ERROR) != 0) {
 			LOG_ERROR("flash write failed, FLASH_SR = 0x%08" PRIx32, flash_sr);
 			/* Clear error + EOP flags but report errors */
-			stm32x_write_flash_reg(bank, FLASH_CCR, flash_sr);
+			stm32x_write_flash_reg_by_index(bank, STM32_FLASH_CCR_INDEX, flash_sr);
 			retval = ERROR_FAIL;
 		}
 	}
@@ -711,7 +752,7 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 	4. Wait for flash operations completion
 	*/
 	while (blocks_remaining > 0) {
-		retval = stm32x_write_flash_reg(bank, FLASH_CR,
+		retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX,
 				stm32x_info->part_info->compute_flash_cr(FLASH_PG | FLASH_PSIZE_64, 0));
 		if (retval != ERROR_OK)
 			goto flash_lock;
@@ -769,6 +810,8 @@ static int stm32x_probe(struct flash_bank *bank)
 
 	device_id = stm32x_info->idcode & 0xfff;
 
+	stm32x_info->flash_regs = stm32h7_flash_regs;
+
 	for (unsigned int n = 0; n < ARRAY_SIZE(stm32h7x_parts); n++) {
 		if (device_id == stm32h7x_parts[n].id)
 			stm32x_info->part_info = &stm32h7x_parts[n];
@@ -967,7 +1010,7 @@ static int stm32x_set_rdp(struct flash_bank *bank, enum stm32h7x_opt_rdp new_rdp
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	retval = stm32x_read_flash_reg(bank, FLASH_OPTSR_PRG, &optsr);
+	retval = stm32x_read_flash_reg_by_index(bank, STM32_FLASH_OPTSR_PRG_INDEX, &optsr);
 
 	if (retval != ERROR_OK) {
 		LOG_DEBUG("unable to read FLASH_OPTSR_PRG register");
@@ -997,7 +1040,7 @@ static int stm32x_set_rdp(struct flash_bank *bank, enum stm32h7x_opt_rdp new_rdp
 	optsr = (optsr & ~OPT_RDP_MASK) | (new_rdp << OPT_RDP_POS);
 
 	/* apply new option value */
-	return stm32x_write_option(bank, FLASH_OPTSR_PRG, optsr);
+	return stm32x_write_option(bank, STM32_FLASH_OPTSR_PRG_INDEX, optsr);
 }
 
 COMMAND_HANDLER(stm32x_handle_lock_command)
@@ -1056,17 +1099,17 @@ static int stm32x_mass_erase(struct flash_bank *bank)
 		goto flash_lock;
 
 	/* mass erase flash memory bank */
-	retval = stm32x_write_flash_reg(bank, FLASH_CR,
+	retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX,
 			stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64, 0));
 	if (retval != ERROR_OK)
 		goto flash_lock;
 
-	retval = stm32x_write_flash_reg(bank, FLASH_CR,
+	retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX,
 			stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64 | FLASH_START, 0));
 	if (retval != ERROR_OK)
 		goto flash_lock;
 
-	retval = stm32x_wait_flash_op_queue(bank, 30000);
+	retval = stm32x_wait_flash_op_queue(bank, MASS_ERASE_TIMEOUT);
 	if (retval != ERROR_OK)
 		goto flash_lock;
 
@@ -1110,7 +1153,7 @@ COMMAND_HANDLER(stm32x_handle_option_read_command)
 	uint32_t reg_offset, value;
 
 	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
-	retval = stm32x_read_flash_reg(bank, reg_offset, &value);
+	retval = stm32x_read_flash_reg_by_index(bank, reg_offset, &value);
 	if (retval != ERROR_OK)
 		return retval;
 

-- 

[PATCH]: 3b6fd1f8d8 tcl: stm32mp15x: modify handshake to open debug port, add hwthread

[<ge...@op...>]

This is an automated email from Gerrit.

"Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8984

-- gerrit

commit 3b6fd1f8d8fe866d2e875d83d7fc5dab151465fc
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Jul 4 16:34:29 2025 +0200

    tcl: stm32mp15x: modify handshake to open debug port, add hwthread
    
    Align the target script to the handshake implemented in the latest
    version of stm32wrapper4dbg to get access to the debug port.
    
    Use hwthread with the SMP node.
    
    Allow ignoring/masking some CPU from the configuration with the
    variables EN_<cpu>.
    
    Change-Id: I7117dd7df20b4f6b6e28f911e3e91ee763bdd200
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/st/stm32mp15x.cfg b/tcl/target/st/stm32mp15x.cfg
index bcdda73e90..9f52abaa6e 100644
--- a/tcl/target/st/stm32mp15x.cfg
+++ b/tcl/target/st/stm32mp15x.cfg
@@ -18,6 +18,11 @@ if { [info exists CHIPNAME] } {
 	set _CHIPNAME stm32mp15x
 }
 
+# Set to 0 to prevent CPU examine. Default examine them
+if { ! [info exists EN_CA7_0] } { set EN_CA7_0 1 }
+if { ! [info exists EN_CA7_1] } { set EN_CA7_1 1 }
+if { ! [info exists EN_CM4] }   { set EN_CM4   1 }
+
 if { [info exists CPUTAPID] } {
 	set _CPUTAPID $CPUTAPID
 } else {
@@ -42,20 +47,21 @@ if { [using_jtag] } {
 
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
 
-# FIXME: Cortex-M code requires target accessible during reset, but this is not possible in STM32MP1
-# so defer-examine it until the reset framework get merged
 # NOTE: keep ap-num and dbgbase to speed-up examine after reset
 # NOTE: do not change the order of target create
 target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
 target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
 target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
-target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
-target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000
+target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000 -defer-examine
+target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000 -defer-examine
 target create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
 
 targets $_CHIPNAME.cpu0
 
 target smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1
+$_CHIPNAME.cpu0 configure -rtos hwthread
+$_CHIPNAME.cpu1 configure -rtos hwthread
+
 $_CHIPNAME.cpu0 cortex_a maskisr on
 $_CHIPNAME.cpu1 cortex_a maskisr on
 $_CHIPNAME.cpu0 cortex_a dacrfixup on
@@ -96,7 +102,16 @@ proc axi_nsecure {} {
 
 axi_secure
 
-proc dbgmcu_enable_debug {} {
+# mmw with target selection
+proc target_mmw {target reg setbits clearbits} {
+	set val [eval $target read_memory $reg 32 1]
+	set val [expr {($val & ~$clearbits) | $setbits}]
+	eval $target mww $reg $val
+}
+
+lappend _telnet_autocomplete_skip _enable_debug
+# Uses AP1
+proc _enable_debug {} {
 	# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
 	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
 	# freeze watchdog 1 and 2 on cores halted
@@ -104,30 +119,70 @@ proc dbgmcu_enable_debug {} {
 	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
 }
 
-proc toggle_cpu0_dbg_claim0 {} {
-	# toggle CPU0 DBG_CLAIM[0]
-	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
-	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
+lappend _telnet_autocomplete_skip _handshake_with_wrapper
+# Uses AP1
+proc _handshake_with_wrapper { halt } {
+	set dbgmcu_cr 0
+	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap1 read_memory 0xe0081004 32 1]}
+	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
+		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
+		return
+	}
+
+	if { $halt }  {
+		$::_CHIPNAME.ap1 arp_halt
+		if { $::EN_CA7_0 } {
+			$::_CHIPNAME.ap1 arp_halt
+			$::_CHIPNAME.ap1 mww 0xe00d0300 0
+			target_mmw $::_CHIPNAME.ap1 0xe00d0088 0x00004000 0
+		}
+	}
+
+	$::_CHIPNAME.ap1 mww 0xe0081004 0x7
 }
 
-proc detect_cpu1 {} {
+lappend _telnet_autocomplete_skip _detect_cpu1
+# Uses AP1
+proc _detect_cpu1 {} {
+	if { !$::EN_CA7_1 } { return }
+
 	set cpu1_prsr [$::_CHIPNAME.ap1 read_memory 0xE00D2314 32 1]
 	set dual_core [expr {$cpu1_prsr & 1}]
-	if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
+	if {!$dual_core} {set ::EN_CA7_1 0}
 }
 
-proc rcc_enable_traceclk {} {
+lappend _telnet_autocomplete_skip _rcc_enable_traceclk
+proc _rcc_enable_traceclk {} {
 	$::_CHIPNAME.ap2 mww 0x5000080c 0x301
 }
 
 # FIXME: most of handler below will be removed once reset framework get merged
-$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}}
-$_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}
-$_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
-$_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}
-$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
-$_CHIPNAME.cm4  configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
-$_CHIPNAME.ap1  configure -event examine-start       {dap init}
-$_CHIPNAME.ap2  configure -event examine-start       {dbgmcu_enable_debug}
-$_CHIPNAME.cpu0 configure -event examine-end         {detect_cpu1}
-$_CHIPNAME.ap2  configure -event examine-end         {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine}
+$_CHIPNAME.cm4  configure -event reset-assert        { }
+
+$_CHIPNAME.ap1  configure -event reset-assert-post   { adapter assert srst }
+
+$_CHIPNAME.ap1  configure -event reset-deassert-pre  {
+	adapter deassert srst deassert trst
+	$::_CHIPNAME.ap1 arp_examine
+	_handshake_with_wrapper $halt
+	if { $::EN_CA7_0 } { $::_CHIPNAME.cpu0 arp_examine; if { $halt } { $::_CHIPNAME.cpu0 arp_halt }}
+	if { $::EN_CA7_1 } { $::_CHIPNAME.cpu1 arp_examine; if { $halt } { $::_CHIPNAME.cpu1 arp_halt }}
+	_enable_debug
+}
+
+$_CHIPNAME.ap2  configure -event reset-deassert-pre  {
+	_rcc_enable_traceclk
+	if { $::EN_CM4 } {$::_CHIPNAME.cm4 arp_examine; if { $halt } { $::_CHIPNAME.cm4 arp_halt }}
+}
+
+$_CHIPNAME.ap1 configure -event examine-end          {
+	_enable_debug
+	_detect_cpu1
+	if { $::EN_CA7_0 } { $::_CHIPNAME.cpu0 arp_examine }
+	if { $::EN_CA7_1 } { $::_CHIPNAME.cpu1 arp_examine }
+}
+
+$_CHIPNAME.ap2  configure -event examine-end         {
+	_rcc_enable_traceclk
+	if { $::EN_CM4 } { $::_CHIPNAME.cm4 arp_examine }
+}

-- 

[PATCH]: 35ba4ba066 tcl: move STM32 MPU files in vendor folder

[<ge...@op...>]

This is an automated email from Gerrit.

"Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8982

-- gerrit

commit 35ba4ba066dd979b19f67a2a6e56fb4ab4811214
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Jul 4 16:50:46 2025 +0200

    tcl: move STM32 MPU files in vendor folder
    
    Move the existing files for STM32MP13x and STM32MP15x in the
    folder "st".
    Rename the boards using the correct separator "-" in place of "_".
    
    Change-Id: If8b92f55e3390ebc75df6a2ea09fcf798ea0b8cf
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/board/stm32mp13x_dk.cfg b/tcl/board/st/stm32mp13x-dk.cfg
similarity index 83%
rename from tcl/board/stm32mp13x_dk.cfg
rename to tcl/board/st/stm32mp13x-dk.cfg
index 8ece24844c..2259e0425b 100644
--- a/tcl/board/stm32mp13x_dk.cfg
+++ b/tcl/board/st/stm32mp13x-dk.cfg
@@ -7,6 +7,6 @@ source [find interface/stlink.cfg]
 
 transport select swd
 
-source [find target/stm32mp13x.cfg]
+source [find target/st/stm32mp13x.cfg]
 
 reset_config srst_only
diff --git a/tcl/board/stm32mp15x_dk2.cfg b/tcl/board/st/stm32mp15x-dk2.cfg
similarity index 87%
rename from tcl/board/stm32mp15x_dk2.cfg
rename to tcl/board/st/stm32mp15x-dk2.cfg
index ba1c7f78a6..5d05307812 100644
--- a/tcl/board/stm32mp15x_dk2.cfg
+++ b/tcl/board/st/stm32mp15x-dk2.cfg
@@ -8,6 +8,6 @@ source [find interface/stlink.cfg]
 
 transport select swd
 
-source [find target/stm32mp15x.cfg]
+source [find target/st/stm32mp15x.cfg]
 
 reset_config srst_only
diff --git a/tcl/file_renaming.cfg b/tcl/file_renaming.cfg
index 0a3c7ba65b..b678f95582 100644
--- a/tcl/file_renaming.cfg
+++ b/tcl/file_renaming.cfg
@@ -17,6 +17,8 @@ set _file_renaming {
 	board/nordic_nrf51822_mkit.cfg	board/nordic/nrf51822-mkit.cfg
 	board/nordic_nrf51_dk.cfg		board/nordic/nrf51-dk.cfg
 	board/nordic_nrf52_dk.cfg		board/nordic/nrf52-dk.cfg
+	board/stm32mp13x_dk.cfg			board/st/stm32mp13x-dk.cfg
+	board/stm32mp15x_dk2.cfg		board/st/stm32mp15x-dk2.cfg
 	target/nrf51.cfg	target/nordic/nrf51.cfg
 	target/nrf52.cfg	target/nordic/nrf52.cfg
 	target/nrf53.cfg	target/nordic/nrf53.cfg
diff --git a/tcl/target/stm32mp13x.cfg b/tcl/target/st/stm32mp13x.cfg
similarity index 100%
rename from tcl/target/stm32mp13x.cfg
rename to tcl/target/st/stm32mp13x.cfg
diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/st/stm32mp15x.cfg
similarity index 100%
rename from tcl/target/stm32mp15x.cfg
rename to tcl/target/st/stm32mp15x.cfg

-- 

[PATCH]: 2021e38799 tcl: stm32mp13x: modify handshake to open debug port

[<ge...@op...>]

This is an automated email from Gerrit.

"Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8983

-- gerrit

commit 2021e38799291b7ce200519c9e6e41c77029e2b0
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Jul 4 16:29:47 2025 +0200

    tcl: stm32mp13x: modify handshake to open debug port
    
    Align the target script to the handshake implemented in the latest
    version of stm32wrapper4dbg to get access to the debug port.
    
    Change-Id: Ia1c7773330fda776abb4385331fddbf431d11c39
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/st/stm32mp13x.cfg b/tcl/target/st/stm32mp13x.cfg
index bcf25c9049..171b43fe97 100644
--- a/tcl/target/st/stm32mp13x.cfg
+++ b/tcl/target/st/stm32mp13x.cfg
@@ -46,7 +46,7 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
 # NOTE: do not change the order of target create
 target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
 target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
-target create $_CHIPNAME.cpu cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
+target create $_CHIPNAME.cpu cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000 -defer-examine
 
 $_CHIPNAME.cpu cortex_a maskisr on
 $_CHIPNAME.cpu cortex_a dacrfixup on
@@ -76,27 +76,55 @@ proc axi_nsecure {} {
 
 axi_secure
 
-proc dbgmcu_enable_debug {} {
+# mmw with target selection
+proc target_mmw {target reg setbits clearbits} {
+	set val [eval $target read_memory $reg 32 1]
+	set val [expr {($val & ~$clearbits) | $setbits}]
+	eval $target mww $reg $val
+}
+
+lappend _telnet_autocomplete_skip _enable_debug
+# Uses AP1
+proc _enable_debug {} {
 	# keep clock enabled in low-power
-	## catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000004}
+	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000004}
 	# freeze watchdog 1 and 2 on core halted
 	catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
 	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
 }
 
-proc toggle_cpu_dbg_claim0 {} {
-	# toggle CPU0 DBG_CLAIM[0]
-	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
-	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
+lappend _telnet_autocomplete_skip _handshake_with_wrapper
+# Uses AP1
+proc _handshake_with_wrapper { halt } {
+	set dbgmcu_cr 0
+	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap1 read_memory 0xe0081004 32 1]}
+	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
+		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
+		return
+	}
+
+	if { $halt } {
+		$::_CHIPNAME.ap1 arp_halt
+		$::_CHIPNAME.ap1 mww 0xe00d0300 0
+		target_mmw $::_CHIPNAME.ap1 0xe00d0088 0x00004000 0
+	}
+
+	$::_CHIPNAME.ap1 mww 0xe0081004 0x7
 }
 
 # FIXME: most of handlers below will be removed once reset framework get merged
-$_CHIPNAME.ap1 configure -event reset-deassert-pre {
+$_CHIPNAME.ap1 configure -event reset-assert-post   { adapter assert srst }
+
+$_CHIPNAME.ap1 configure -event reset-deassert-pre  {
 	adapter deassert srst deassert trst
-	catch {dap init}
-	catch {$::_CHIPNAME.dap apid 1}
+	$::_CHIPNAME.ap1 arp_examine
+	_handshake_with_wrapper $halt
+	_enable_debug
+	$::_CHIPNAME.cpu arp_examine
+	if { $halt } { $::_CHIPNAME.cpu arp_halt}
+}
+
+$_CHIPNAME.ap1 configure -event examine-end         {
+	_enable_debug
+	$::_CHIPNAME.cpu arp_examine
 }
-$_CHIPNAME.cpu configure -event reset-deassert-pre  {$::_CHIPNAME.cpu arp_examine}
-$_CHIPNAME.cpu configure -event reset-deassert-post {toggle_cpu_dbg_claim0; dbgmcu_enable_debug}
-$_CHIPNAME.ap1 configure -event examine-start       {dap init}
-$_CHIPNAME.ap1 configure -event examine-end         {dbgmcu_enable_debug}

-- 

[PATCH]: 12e7e1e2bf tcl: add support for stm32mp2xx targets and boards

[<ge...@op...>]

This is an automated email from Gerrit.

"Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8985

-- gerrit

commit 12e7e1e2bf3e5a8d9b15336012fa7a95629a3284
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Jul 4 16:37:38 2025 +0200

    tcl: add support for stm32mp2xx targets and boards
    
    Add support for the targets stm32mp21x, stm32mp23x and stm32mp25x.
    Add support for the boards stm32mp23x-dk and stm32mp25x-dk.
    
    The board stm32mp21x-dk has no configuration file as it only
    provides a generic JTAG/SWD connector for the stm32mp21x SoC.
    
    Change-Id: I0256bebd8a5d5600066d8ae191d83344a35d3d37
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/board/st/stm32mp23x-dk.cfg b/tcl/board/st/stm32mp23x-dk.cfg
new file mode 100644
index 0000000000..1f660f19ed
--- /dev/null
+++ b/tcl/board/st/stm32mp23x-dk.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# MB1605 with stm32mp23x
+# https://www.st.com/en/evaluation-tools/stm32mp257f-dk.html
+
+source [find interface/stlink.cfg]
+
+transport select swd
+
+source [find target/st/stm32mp23x.cfg]
+
+reset_config srst_only
diff --git a/tcl/board/st/stm32mp25x-dk.cfg b/tcl/board/st/stm32mp25x-dk.cfg
new file mode 100644
index 0000000000..182f1d00ce
--- /dev/null
+++ b/tcl/board/st/stm32mp25x-dk.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# MB1605
+# https://www.st.com/en/evaluation-tools/stm32mp257f-dk.html
+
+source [find interface/stlink.cfg]
+
+transport select swd
+
+source [find target/st/stm32mp25x.cfg]
+
+reset_config srst_only
diff --git a/tcl/target/st/stm32mp21x.cfg b/tcl/target/st/stm32mp21x.cfg
new file mode 100644
index 0000000000..22532031ff
--- /dev/null
+++ b/tcl/target/st/stm32mp21x.cfg
@@ -0,0 +1,199 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STMicroelectronics STM32MP21x
+# STM32MP21x devices support both JTAG and SWD transports.
+
+# HLA does not support multi-cores nor custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp21x
+}
+
+# Set to 0 to prevent CPU examine. Default examine them
+if { ! [info exists EN_CA35] } { set EN_CA35 1 }
+if { ! [info exists EN_CM33] } { set EN_CM33 1 }
+
+set _ENDIAN little
+
+# jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x16503041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4 -ircapture 0x01 -irmask 0x0f
+if { [using_jtag] } {
+	swj_newdap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+# define AXI & APB Memory Access Ports
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap0 mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 2
+target create $_CHIPNAME.ap3 mem_ap -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
+
+# define the Cortex-A35
+cti create $_CHIPNAME.cti.a35 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80220000
+target create $_CHIPNAME.a35 aarch64 -dap $_CHIPNAME.dap -ap-num 1 -dbgbase 0x80210000 \
+	-cti $_CHIPNAME.cti.a35 -defer-examine
+
+# define the Cortex-M33
+target create $_CHIPNAME.m33 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
+cti create $_CHIPNAME.cti.m33 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xe0042000
+
+# define the system CTIs
+cti create $_CHIPNAME.cti.sys0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80080000
+cti create $_CHIPNAME.cti.sys1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80090000
+
+swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x800A0000
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80040000
+
+targets $_CHIPNAME.a35
+
+reset_config srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# wait 1 seconds for bootrom
+adapter srst delay 1000
+
+# set CSW for AXI
+$_CHIPNAME.dap apsel 2
+$_CHIPNAME.dap apcsw 0x12800000
+
+# mmw with target selection
+proc target_mmw {target reg setbits clearbits} {
+	set val [eval $target read_memory $reg 32 1]
+	set val [expr {($val & ~$clearbits) | $setbits}]
+	eval $target mww $reg $val
+}
+
+lappend _telnet_autocomplete_skip _enable_debug
+# Uses AP0 and AXI
+proc _enable_debug {} {
+	# Enable DBGMCU clock in RC
+	$::_CHIPNAME.axi mww 0x44200520 0x500
+
+	# set debug enable bits in DBGMCU_CR to get ap3/cm33 visible
+	$::_CHIPNAME.ap0 mww 0x80001004 0x7
+
+	# Freeze watchdogs on CPU halt
+	$::_CHIPNAME.axi mww 0x440a003c 0x00000026
+	$::_CHIPNAME.axi mww 0x440a0040 0x00000038
+}
+
+lappend _telnet_autocomplete_skip _rcc_enable_traceclk
+# Uses AXI
+proc _rcc_enable_traceclk {} {
+	# set bit TRACEEN in RCC_DBGCFGR to clock TPIU
+	target_mmw $::_CHIPNAME.axi 0x44200520 0x200 0
+}
+
+lappend _telnet_autocomplete_skip _handshake_with_wrapper
+# Uses AP0, AP1 and AP3
+proc _handshake_with_wrapper { halt } {
+	set dbgmcu_cr 0
+	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap0 read_memory 0x80001004 32 1]}
+	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
+		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
+		return
+	}
+
+	if { $halt } {
+		if { $::EN_CA35 } {
+			$::_CHIPNAME.ap1 arp_examine
+			$::_CHIPNAME.ap1 arp_halt
+			$::_CHIPNAME.ap1 mww 0x80210300 0
+			target_mmw $::_CHIPNAME.ap1 0x80210088 0x00004000 0
+		}
+		if { $::EN_CM33 } {
+			$::_CHIPNAME.ap3 arp_examine
+			$::_CHIPNAME.ap3 arp_halt
+			$::_CHIPNAME.ap3 mww 0xe000edf0 0xa05f0001
+		}
+	}
+
+	# alert wrapper that debugger is ready
+	$::_CHIPNAME.ap0 mww 0x80001004 0x07
+}
+
+lappend _telnet_autocomplete_skip _enable_dbgmcu_on_devboot
+# In DEV BOOT the BootROM does not completes the sequence to enable the
+# visibility of DBGMCU on AP0.
+# Write a value in DBGMCU_DBG_AUTH_DEV from CID1.
+# Returns 1 if DEV BOOT is detected
+# Uses AP2 (AXI bus)
+proc _enable_dbgmcu_on_devboot {} {
+	$::_CHIPNAME.axi mww 0x44230004 0
+	set boot_pins [expr {[$::_CHIPNAME.axi read_memory 0x44230000 32 1] & 0xf}]
+	if {$boot_pins != 0x3 && $boot_pins != 0xc} {
+		return 0
+	}
+
+	set rifsc_rimc_cr [$::_CHIPNAME.axi read_memory 0x42080c00 32 1]
+	if {$rifsc_rimc_cr != 0x00008710} {
+		echo "RIFSC_RIMC_CR modified, skip activation of DBGMCU"
+		return 1
+	}
+
+	# Enable DBGMCU clock in RC
+	$::_CHIPNAME.axi mww 0x44200520 0x500
+
+	# Change DAP (AXI) CID, write in DBGMCU, set back DAP CID
+	$::_CHIPNAME.axi mww 0x42080c00 0x00008110
+	$::_CHIPNAME.axi mww 0x440A0104 1
+	$::_CHIPNAME.axi mww 0x42080c00 0x00008710
+	return 1
+}
+
+$_CHIPNAME.m33 configure -event reset-assert        { }
+
+$_CHIPNAME.axi configure -event reset-assert-post   { adapter assert srst }
+
+$_CHIPNAME.axi configure -event reset-deassert-pre  {
+	adapter deassert srst deassert trst
+	$::_CHIPNAME.axi arp_examine
+	set is_dev_boot [_enable_dbgmcu_on_devboot]
+	if { !$is_dev_boot } { _handshake_with_wrapper $halt}
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35 } { $::_CHIPNAME.a35 arp_examine; if {$halt} {$::_CHIPNAME.a35 arp_halt} }
+	if { $::EN_CM33 } {
+		$::_CHIPNAME.ap3 arp_examine
+		$::_CHIPNAME.m33 arp_examine
+		if {$halt} {$::_CHIPNAME.ap3 arp_halt; $::_CHIPNAME.m33 arp_halt}
+	}
+}
+
+$_CHIPNAME.axi configure -event examine-end         {
+	set is_dev_boot [_enable_dbgmcu_on_devboot]
+	if {$is_dev_boot} {echo "Dev boot detected"}
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35 } { $::_CHIPNAME.a35 arp_examine }
+	if { $::EN_CM33 } { $::_CHIPNAME.ap3 arp_examine; $::_CHIPNAME.m33 arp_examine }
+}
diff --git a/tcl/target/st/stm32mp23x.cfg b/tcl/target/st/stm32mp23x.cfg
new file mode 100644
index 0000000000..ad148608bc
--- /dev/null
+++ b/tcl/target/st/stm32mp23x.cfg
@@ -0,0 +1,188 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STMicroelectronics STM32MP23x
+# STM32MP23x devices support both JTAG and SWD transports.
+
+# HLA does not support multi-cores nor custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp23x
+}
+
+# Set to 0 to prevent CPU examine. Default examine them
+if { ! [info exists EN_CA35_0] } { set EN_CA35_0 1 }
+if { ! [info exists EN_CA35_1] } { set EN_CA35_1 1 }
+if { ! [info exists EN_CM33] }   { set EN_CM33   1 }
+
+set _ENDIAN little
+
+# jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x16505041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4 -ircapture 0x01 -irmask 0x0f
+if { [using_jtag] } {
+	swj_newdap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+# define AXI & APB Memory Access Ports
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap0 mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 4
+target create $_CHIPNAME.ap8 mem_ap -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+
+# define the first Cortex-A35
+cti create $_CHIPNAME.cti.a35_0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80220000
+target create $_CHIPNAME.a35_0 aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80210000 \
+	-cti $_CHIPNAME.cti.a35_0 -defer-examine
+
+# define the second Cortex-A35
+cti create $_CHIPNAME.cti.a35_1 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80320000
+target create $_CHIPNAME.a35_1 aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80310000 \
+	-cti $_CHIPNAME.cti.a35_1 -defer-examine
+
+# define the Cortex-M33
+target create $_CHIPNAME.m33 cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+cti create $_CHIPNAME.cti.m33 -dap $_CHIPNAME.dap -ap-num 8 -baseaddr 0xe0042000
+
+# define the system CTIs
+cti create $_CHIPNAME.cti.sys0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80090000
+cti create $_CHIPNAME.cti.sys1 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x800a0000
+
+swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x800b0000
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80050000
+
+targets $_CHIPNAME.a35_0
+
+target smp $_CHIPNAME.a35_0 $_CHIPNAME.a35_1
+$_CHIPNAME.a35_0 configure -rtos hwthread
+$_CHIPNAME.a35_1 configure -rtos hwthread
+
+reset_config srst_gates_jtag srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# wait 1 seconds for bootrom
+adapter srst delay 1000
+
+# set CSW for AXI
+$_CHIPNAME.dap apsel 4
+$_CHIPNAME.dap apcsw 0x12800000
+
+# mmw with target selection
+proc target_mmw {target reg setbits clearbits} {
+	set val [eval $target read_memory $reg 32 1]
+	set val [expr {($val & ~$clearbits) | $setbits}]
+	eval $target mww $reg $val
+}
+
+lappend _telnet_autocomplete_skip _enable_debug
+# Uses AP0 and AXI
+proc _enable_debug {} {
+	# set debug enable bits in DBGMCU_CR to get ap8/cm33 visible
+	$::_CHIPNAME.ap0 mww 0x80010004 0x17
+
+	# Freeze watchdogs on CPU halt
+	$::_CHIPNAME.axi mww 0x4a010008 0x00000000
+	$::_CHIPNAME.axi mww 0x4a01003c 0x00000026
+	$::_CHIPNAME.axi mww 0x4a010040 0x00000038
+	$::_CHIPNAME.axi mww 0x4a010044 0x00000400
+	$::_CHIPNAME.axi mww 0x4a010048 0x00000400
+	$::_CHIPNAME.axi mww 0x4a01004c 0x00000600
+}
+
+lappend _telnet_autocomplete_skip _rcc_enable_traceclk
+# Uses AXI
+proc _rcc_enable_traceclk {} {
+	# set bit TRACEEN in RCC_DBGCFGR to clock TPIU
+	target_mmw $::_CHIPNAME.axi 0x44200520 0x200 0
+}
+
+lappend _telnet_autocomplete_skip _handshake_with_wrapper
+# Uses AP0
+proc _handshake_with_wrapper { halt } {
+	set dbgmcu_cr 0
+	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap0 read_memory 0x80010004 32 1]}
+	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
+		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
+		return;
+	}
+
+	if { $halt } {
+		if { $::EN_CA35_0 || $::EN_CA35_1 } {
+			$::_CHIPNAME.ap0 arp_examine
+			$::_CHIPNAME.ap0 arp_halt
+		}
+		if { $::EN_CA35_0 } {
+			$::_CHIPNAME.ap0 mww 0x80210300 0
+			target_mmw $::_CHIPNAME.ap0 0x80210088 0x00004000 0
+		}
+		if { $::EN_CA35_1 } {
+			$::_CHIPNAME.ap0 mww 0x80310300 0
+			target_mmw $::_CHIPNAME.ap0 0x80310088 0x00004000 0
+		}
+		if { $::EN_CM33 } {
+			$::_CHIPNAME.ap8 arp_examine
+			$::_CHIPNAME.ap8 arp_halt
+			$::_CHIPNAME.ap8 mww 0xe000edf0 0xa05f0001
+		}
+	}
+
+	# alert wrapper that debugger is ready
+	$::_CHIPNAME.ap0 mww 0x80010004 0x17
+}
+
+$_CHIPNAME.m33 configure -event reset-assert        { }
+
+$_CHIPNAME.axi configure -event reset-assert-post   { adapter assert srst }
+
+$_CHIPNAME.axi configure -event reset-deassert-pre  {
+	adapter deassert srst deassert trst
+
+	$::_CHIPNAME.ap0 arp_examine
+	_handshake_with_wrapper $halt
+
+	$::_CHIPNAME.axi arp_examine
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35_0 } { $::_CHIPNAME.a35_0 arp_examine;  if {$halt} {$::_CHIPNAME.a35_0 arp_halt} }
+	if { $::EN_CA35_1 } { $::_CHIPNAME.a35_1 arp_examine;  if {$halt} {$::_CHIPNAME.a35_1 arp_halt} }
+	if { $::EN_CM33 }   {
+		$::_CHIPNAME.ap8 arp_examine
+		$::_CHIPNAME.m33 arp_examine
+		if {$halt} {$::_CHIPNAME.m33 arp_halt}
+	}
+}
+
+$_CHIPNAME.axi configure -event examine-end         {
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35_0 } { $::_CHIPNAME.a35_0 arp_examine }
+	if { $::EN_CA35_1 } { $::_CHIPNAME.a35_1 arp_examine }
+	if { $::EN_CM33 }   { $::_CHIPNAME.ap8 arp_examine; $::_CHIPNAME.m33 arp_examine }
+}
diff --git a/tcl/target/st/stm32mp25x.cfg b/tcl/target/st/stm32mp25x.cfg
new file mode 100644
index 0000000000..97802903fb
--- /dev/null
+++ b/tcl/target/st/stm32mp25x.cfg
@@ -0,0 +1,210 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STMicroelectronics STM32MP25x
+# STM32MP25x devices support both JTAG and SWD transports.
+
+# HLA does not support multi-cores nor custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp25x
+}
+
+# Set to 0 to prevent CPU examine. Default examine them
+if { ! [info exists EN_CA35_0] } { set EN_CA35_0 1 }
+if { ! [info exists EN_CA35_1] } { set EN_CA35_1 1 }
+if { ! [info exists EN_CM33] }   { set EN_CM33   1 }
+if { ! [info exists EN_CM0P] }   { set EN_CM0P   1 }
+
+set _ENDIAN little
+
+# jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x16505041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4 -ircapture 0x01 -irmask 0x0f
+if { [using_jtag] } {
+	swj_newdap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+# define AXI & APB Memory Access Ports
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap0 mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 4
+target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
+target create $_CHIPNAME.ap8 mem_ap -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+
+# define the first Cortex-A35
+cti create $_CHIPNAME.cti.a35_0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80220000
+target create $_CHIPNAME.a35_0 aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80210000 \
+	-cti $_CHIPNAME.cti.a35_0 -defer-examine
+
+# define the second Cortex-A35
+cti create $_CHIPNAME.cti.a35_1 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80320000
+target create $_CHIPNAME.a35_1 aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80310000 \
+	-cti $_CHIPNAME.cti.a35_1 -defer-examine
+
+# define the Cortex-M33
+target create $_CHIPNAME.m33 cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+cti create $_CHIPNAME.cti.m33 -dap $_CHIPNAME.dap -ap-num 8 -baseaddr 0xe0042000
+
+# define the Cortex-M0+
+target create $_CHIPNAME.m0p cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
+cti create $_CHIPNAME.cti.m0p -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xf0000000
+
+# define the system CTIs
+cti create $_CHIPNAME.cti.sys0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80090000
+cti create $_CHIPNAME.cti.sys1 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x800a0000
+
+swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x800b0000
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80050000
+
+targets $_CHIPNAME.a35_0
+
+target smp $_CHIPNAME.a35_0 $_CHIPNAME.a35_1
+$_CHIPNAME.a35_0 configure -rtos hwthread
+$_CHIPNAME.a35_1 configure -rtos hwthread
+
+reset_config srst_gates_jtag srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# wait 1 seconds for bootrom
+adapter srst delay 1000
+
+# set CSW for AXI
+$_CHIPNAME.dap apsel 4
+$_CHIPNAME.dap apcsw 0x12800000
+
+# mmw with target selection
+proc target_mmw {target reg setbits clearbits} {
+	set val [eval $target read_memory $reg 32 1]
+	set val [expr {($val & ~$clearbits) | $setbits}]
+	eval $target mww $reg $val
+}
+
+lappend _telnet_autocomplete_skip _enable_ap2_cm0p
+proc _enable_ap2_cm0p {} {
+	# set bits C3LPEN and C3EN in RCC_C3CFGR to enable AP2 and CM0+ clock
+	target_mmw $::_CHIPNAME.axi 0x54200490 6 0
+}
+
+lappend _telnet_autocomplete_skip _enable_debug
+# Uses AP0 and AXI
+proc _enable_debug {} {
+	# set debug enable bits in DBGMCU_CR to get ap2/cm0+ and ap8/cm33 visible
+	# set DBG_SWD_SEL_N bit in DBGMCU_CR to get ap2/cm0+ on main debug interface
+	$::_CHIPNAME.ap0 mww 0x80010004 0x17
+
+	if { $::EN_CM0P } {
+		_enable_ap2_cm0p
+	}
+
+	# Freeze watchdogs on CPU halt
+	$::_CHIPNAME.axi mww 0x4a010008 0x00000000
+	$::_CHIPNAME.axi mww 0x4a01003c 0x00000026
+	$::_CHIPNAME.axi mww 0x4a010040 0x00000038
+	$::_CHIPNAME.axi mww 0x4a010044 0x00000400
+	$::_CHIPNAME.axi mww 0x4a010048 0x00000400
+	$::_CHIPNAME.axi mww 0x4a01004c 0x00000600
+}
+
+lappend _telnet_autocomplete_skip _rcc_enable_traceclk
+# Uses AXI
+proc _rcc_enable_traceclk {} {
+	# set bit TRACEEN in RCC_DBGCFGR to clock TPIU
+	target_mmw $::_CHIPNAME.axi 0x44200520 0x200 0
+}
+
+lappend _telnet_autocomplete_skip _handshake_with_wrapper
+# Uses AP0
+proc _handshake_with_wrapper { halt } {
+	set dbgmcu_cr 0
+	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap0 read_memory 0x80010004 32 1]}
+	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
+		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
+		return;
+	}
+
+	if { $halt } {
+		if { $::EN_CA35_0 || $::EN_CA35_1 } {
+			$::_CHIPNAME.ap0 arp_examine
+			$::_CHIPNAME.ap0 arp_halt
+		}
+		if { $::EN_CA35_0 } {
+			$::_CHIPNAME.ap0 mww 0x80210300 0
+			target_mmw $::_CHIPNAME.ap0 0x80210088 0x00004000 0
+		}
+		if { $::EN_CA35_1 } {
+			$::_CHIPNAME.ap0 mww 0x80310300 0
+			target_mmw $::_CHIPNAME.ap0 0x80310088 0x00004000 0
+		}
+		if { $::EN_CM33 } {
+			$::_CHIPNAME.ap8 arp_examine
+			$::_CHIPNAME.ap8 arp_halt
+			$::_CHIPNAME.ap8 mww 0xe000edf0 0xa05f0001
+		}
+	}
+
+	# alert wrapper that debugger is ready
+	$::_CHIPNAME.ap0 mww 0x80010004 0x17
+}
+
+$_CHIPNAME.m33 configure -event reset-assert        { }
+$_CHIPNAME.m0p configure -event reset-assert        { }
+
+$_CHIPNAME.axi configure -event reset-assert-post   { adapter assert srst }
+
+$_CHIPNAME.axi configure -event reset-deassert-pre  {
+	adapter deassert srst deassert trst
+
+	$::_CHIPNAME.ap0 arp_examine
+	_handshake_with_wrapper $halt
+
+	$::_CHIPNAME.axi arp_examine
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35_0 } { $::_CHIPNAME.a35_0 arp_examine;  if {$halt} {$::_CHIPNAME.a35_0 arp_halt} }
+	if { $::EN_CA35_1 } { $::_CHIPNAME.a35_1 arp_examine;  if {$halt} {$::_CHIPNAME.a35_1 arp_halt} }
+	if { $::EN_CM0P }   { $::_CHIPNAME.ap2 arp_examine; $::_CHIPNAME.m0p arp_examine }
+	if { $::EN_CM33 }   {
+		$::_CHIPNAME.ap8 arp_examine
+		$::_CHIPNAME.m33 arp_examine
+		if {$halt} {$::_CHIPNAME.m33 arp_halt}
+	}
+}
+
+$_CHIPNAME.m0p configure -event examine-start       { _enable_ap2_cm0p }
+
+$_CHIPNAME.axi configure -event examine-end         {
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35_0 } { $::_CHIPNAME.a35_0 arp_examine }
+	if { $::EN_CA35_1 } { $::_CHIPNAME.a35_1 arp_examine }
+	if { $::EN_CM33 }   { $::_CHIPNAME.ap8 arp_examine; $::_CHIPNAME.m33 arp_examine }
+	if { $::EN_CM0P }   { $::_CHIPNAME.ap2 arp_examine; $::_CHIPNAME.m0p arp_examine }
+}

-- 

[PATCH]: 765e6e1a47 flash/nor/stm32l4x: fix permanent write protection on STM32U5

[<ge...@op...>]

This is an automated email from Gerrit.

"Tomas Vanek <va...@fb...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8981

-- gerrit

commit 765e6e1a47c328f42856b1191c54482c204b00a7
Author: Tomas Vanek <va...@fb...>
Date:   Thu Jul 3 06:52:29 2025 +0200

    flash/nor/stm32l4x: fix permanent write protection on STM32U5
    
    Unlike other devices supported by this driver STM32U5 devices
    have a new UNLOCK bit in FLASH_WRP1AR, WRP1BR, WRP2AR, WRP2BR
    registers. Writing zero to this bit makes the write protection
    block permanent with no way to unprotect.
    
    Commit 6554d176e926 ("flash/stm32l4x: support STM32U59/U5Ax devices")
    and later commits with additional U5 devices lack support for
    the UNLOCK bit and therefore makes write protection permanent
    without warning.
    
    Introduce the new bit flag F_WRP_HAS_LOCK and mark U5 devices by it.
    Set UNLOCK bit in stm32l4_write_one_wrpxy() if F_WRP_HAS_LOCK is set.
    
    Change-Id: I26b97d855e094a21540e3377f367520683af2eac
    Signed-off-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index f16333201b..8001aaf006 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -152,6 +152,9 @@
 /* this flag indicates that programming should be done in quad-word
  * the default programming word size is double-word */
 #define F_QUAD_WORD_PROG    BIT(4)
+/* the registers WRPxyR have UNLOCK bit - writing zero locks the write
+ * protection region permanently! */
+#define F_WRP_HAS_LOCK		BIT(5)
 /* end of STM32L4 flags ******************************************************/
 
 
@@ -500,7 +503,8 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .num_revs              = ARRAY_SIZE(stm32u53_u54xx_revs),
 	  .device_str            = "STM32U535/U545",
 	  .max_flash_size_kb     = 512,
-	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
+	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ
+								| F_HAS_L5_FLASH_REGS | F_WRP_HAS_LOCK,
 	  .flash_regs_base       = 0x40022000,
 	  .fsize_addr            = 0x0BFA07A0,
 	  .otp_base              = 0x0BFA0000,
@@ -692,7 +696,8 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .num_revs              = ARRAY_SIZE(stm32u59_u5axx_revs),
 	  .device_str            = "STM32U59/U5Axx",
 	  .max_flash_size_kb     = 4096,
-	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
+	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ
+								| F_HAS_L5_FLASH_REGS | F_WRP_HAS_LOCK,
 	  .flash_regs_base       = 0x40022000,
 	  .fsize_addr            = 0x0BFA07A0,
 	  .otp_base              = 0x0BFA0000,
@@ -704,7 +709,8 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .num_revs              = ARRAY_SIZE(stm32u57_u58xx_revs),
 	  .device_str            = "STM32U57/U58xx",
 	  .max_flash_size_kb     = 2048,
-	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
+	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ
+								| F_HAS_L5_FLASH_REGS | F_WRP_HAS_LOCK,
 	  .flash_regs_base       = 0x40022000,
 	  .fsize_addr            = 0x0BFA07A0,
 	  .otp_base              = 0x0BFA0000,
@@ -716,7 +722,8 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .num_revs              = ARRAY_SIZE(stm32u5f_u5gxx_revs),
 	  .device_str            = "STM32U5F/U5Gxx",
 	  .max_flash_size_kb     = 4096,
-	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
+	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ
+								| F_HAS_L5_FLASH_REGS | F_WRP_HAS_LOCK,
 	  .flash_regs_base       = 0x40022000,
 	  .fsize_addr            = 0x0BFA07A0,
 	  .otp_base              = 0x0BFA0000,
@@ -1287,6 +1294,8 @@ static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *
 	int wrp_end = wrpxy->last - wrpxy->offset;
 
 	uint32_t wrp_value = (wrp_start & stm32l4_info->wrpxxr_mask) | ((wrp_end & stm32l4_info->wrpxxr_mask) << 16);
+	if (stm32l4_info->part_info->flags & F_WRP_HAS_LOCK)
+		wrp_value |= FLASH_WRPXYR_UNLOCK;
 
 	return stm32l4_write_option(bank, stm32l4_info->flash_regs[wrpxy->reg_idx], wrp_value, 0xffffffff);
 }
diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h
index 07b3615a24..1f4f2344f9 100644
--- a/src/flash/nor/stm32l4x.h
+++ b/src/flash/nor/stm32l4x.h
@@ -69,6 +69,9 @@
 #define FLASH_U5_DUALBANK		BIT(21)
 #define FLASH_TZEN				BIT(31)
 
+/* FLASH_WRPxyR register bits */
+#define FLASH_WRPXYR_UNLOCK		BIT(31)
+
 /* FLASH secure block based bank 1/2 register offsets */
 #define FLASH_SECBB1(X) (0x80 + 4 * (X - 1))
 #define FLASH_SECBB2(X) (0xA0 + 4 * (X - 1))

-- 

LLDB20 + stm32mp15x

[Stanislav S. <sta...@gm...>]

Hello,
I'm debugging stm32mp157c MPU, the board named after QSMP  comes from Ka-Ro
Electronics GmbH.
I'm running a debug session from lldb20 and there are a couple issues to
report.

1. When I try to check the sp_hyp register, lldb crashes. It seemed to me
that the problem is lldb itself until I tried to grab registers' descriptor
from openocd. It appears that something is wrong with numbering (see xlm in
the log below). I'm not 100% sure, that sequence must be continuous, I hope
someone can clarify it. If it must, the patch is one string to change
 src/target/arm.h:ARM_VFP_V3_D0 value from  51 to 53. It works well, I also
checked that renumbering of d0-d31 registers does not affect values
displayed during the debug session.

2. The second issue is bound to lldp-dap (+ emacs + dap-mode in my setup),
which tries to dereference any 32 bit register which somehow reminds a
pointer... I have not investigated its heuristics but, for example, CPSR
register with its NZC flags in upper bits excites lldb-dap a lot. This
results in attempts to download a memory chunk from inaccessible memory
(given I have not initialized MMU), such as 0x60000000 or 0x80000000 - stm
does not map these regions. So it leads to stalling the session.
Nevertheless, if CPSR's upper flags bits show up as 0x400...., nothing bad
happens, as soon as 0x40000000 is a valid address for stm's periphery. I
have fixed it with a weird approach, given an alternative of pushing
patches into llvm seems undoable for me. CPSR's register could be marked 64
bit. This immediately cools down lldb's interest to dereference its value
at 32 bit armv7 arch and no attempts to access MPU memory are being
conducted.

Kind regards,
Stan

ws@ws:~ % lldb20 --version
lldb version 20.1.2
ws@ws:~ % lldb20
(lldb) file --arch armv7-none-none qsmp-fsbl
Current executable set to 'qsmp-fsbl' (armv7).
(lldb) gdb-remote 3333
(lldb) target modules load --load --set-pc-to-entry --slide 0
Process 1 stopped
* thread #1, stop reason = signal SIGINT
    frame #0: 0x2ffc2500 qsmp-fsbl`fsbl._start [inlined] arch.goto at
arch.zig:329:5
   326  }
   327
   328  pub inline fn goto(comptime func: anytype) void {
-> 329      asm volatile ("b %[addr]"
   330          :
   331          : [addr] "i" (func),
   332      );
(lldb) process plugin packet send "qXfer:features:read:target.xml:0,10000"
  packet: qXfer:features:read:target.xml:0,10000
response: l<?xml version="1.0"?>
<!DOCTYPE target SYSTEM "gdb-target.dtd">
<target version="1.0">
<architecture>arm</architecture>
<feature name="org.gnu.gdb.arm.core">
<reg name="r0" bitsize="32" regnum="0" save-restore="no" type="uint32"
group="general"/>
<reg name="r1" bitsize="32" regnum="1" save-restore="no" type="uint32"
group="general"/>
<reg name="r2" bitsize="32" regnum="2" save-restore="no" type="uint32"
group="general"/>
<reg name="r3" bitsize="32" regnum="3" save-restore="no" type="uint32"
group="general"/>
<reg name="r4" bitsize="32" regnum="4" save-restore="no" type="uint32"
group="general"/>
<reg name="r5" bitsize="32" regnum="5" save-restore="no" type="uint32"
group="general"/>
<reg name="r6" bitsize="32" regnum="6" save-restore="no" type="uint32"
group="general"/>
<reg name="r7" bitsize="32" regnum="7" save-restore="no" type="uint32"
group="general"/>
<reg name="r8" bitsize="32" regnum="8" save-restore="no" type="uint32"
group="general"/>
<reg name="r9" bitsize="32" regnum="9" save-restore="no" type="uint32"
group="general"/>
<reg name="r10" bitsize="32" regnum="10" save-restore="no" type="uint32"
group="general"/>
<reg name="r11" bitsize="32" regnum="11" save-restore="no" type="uint32"
group="general"/>
<reg name="r12" bitsize="32" regnum="12" save-restore="no" type="uint32"
group="general"/>
<reg name="sp" bitsize="32" regnum="13" save-restore="no" type="data_ptr"
group="general"/>
<reg name="lr" bitsize="32" regnum="14" save-restore="no" type="code_ptr"
group="general"/>
<reg name="pc" bitsize="32" regnum="15" save-restore="no" type="code_ptr"
group="general"/>
<reg name="cpsr" bitsize="32" regnum="25" save-restore="no" type="uint32"
group="general"/>
</feature>
<feature name="net.sourceforge.openocd.banked">
<reg name="sp_usr" bitsize="32" regnum="26" save-restore="no"
type="data_ptr" group="banked"/>
<reg name="lr_usr" bitsize="32" regnum="27" save-restore="no"
type="code_ptr" group="banked"/>
<reg name="r8_fiq" bitsize="32" regnum="28" save-restore="no" type="uint32"
group="banked"/>
<reg name="r9_fiq" bitsize="32" regnum="29" save-restore="no" type="uint32"
group="banked"/>
<reg name="r10_fiq" bitsize="32" regnum="30" save-restore="no"
type="uint32" group="banked"/>
<reg name="r11_fiq" bitsize="32" regnum="31" save-restore="no"
type="uint32" group="banked"/>
<reg name="r12_fiq" bitsize="32" regnum="32" save-restore="no"
type="uint32" group="banked"/>
<reg name="sp_fiq" bitsize="32" regnum="33" save-restore="no"
type="data_ptr" group="banked"/>
<reg name="lr_fiq" bitsize="32" regnum="34" save-restore="no"
type="code_ptr" group="banked"/>
<reg name="sp_irq" bitsize="32" regnum="35" save-restore="no"
type="data_ptr" group="banked"/>
<reg name="lr_irq" bitsize="32" regnum="36" save-restore="no"
type="code_ptr" group="banked"/>
<reg name="sp_svc" bitsize="32" regnum="37" save-restore="no"
type="data_ptr" group="banked"/>
<reg name="lr_svc" bitsize="32" regnum="38" save-restore="no"
type="code_ptr" group="banked"/>
<reg name="sp_abt" bitsize="32" regnum="39" save-restore="no"
type="data_ptr" group="banked"/>
<reg name="lr_abt" bitsize="32" regnum="40" save-restore="no"
type="code_ptr" group="banked"/>
<reg name="sp_und" bitsize="32" regnum="41" save-restore="no"
type="data_ptr" group="banked"/>
<reg name="lr_und" bitsize="32" regnum="42" save-restore="no"
type="code_ptr" group="banked"/>
<reg name="spsr_fiq" bitsize="32" regnum="43" save-restore="no"
type="uint32" group="banked"/>
<reg name="spsr_irq" bitsize="32" regnum="44" save-restore="no"
type="uint32" group="banked"/>
<reg name="spsr_svc" bitsize="32" regnum="45" save-restore="no"
type="uint32" group="banked"/>
<reg name="spsr_abt" bitsize="32" regnum="46" save-restore="no"
type="uint32" group="banked"/>
<reg name="spsr_und" bitsize="32" regnum="47" save-restore="no"
type="uint32" group="banked"/>
<reg name="sp_mon" bitsize="32" regnum="48" save-restore="no"
type="data_ptr" group="banked"/>
<reg name="lr_mon" bitsize="32" regnum="49" save-restore="no"
type="code_ptr" group="banked"/>
<reg name="spsr_mon" bitsize="32" regnum="50" save-restore="no"
type="uint32" group="banked"/>
<reg name="sp_hyp" bitsize="32" regnum="51" save-restore="no"
type="data_ptr" group="banked"/>
<reg name="spsr_hyp" bitsize="32" regnum="52" save-restore="no"
type="uint32" group="banked"/>
</feature>
<feature name="org.gnu.gdb.arm.vfp">
<reg name="d0" bitsize="64" regnum="51" save-restore="no"
type="ieee_double"/>
<reg name="d1" bitsize="64" regnum="52" save-restore="no"
type="ieee_double"/>
<reg name="d2" bitsize="64" regnum="53" save-restore="no"
type="ieee_double"/>
<reg name="d3" bitsize="64" regnum="54" save-restore="no"
type="ieee_double"/>
<reg name="d4" bitsize="64" regnum="55" save-restore="no"
type="ieee_double"/>
<reg name="d5" bitsize="64" regnum="56" save-restore="no"
type="ieee_double"/>
<reg name="d6" bitsize="64" regnum="57" save-restore="no"
type="ieee_double"/>
<reg name="d7" bitsize="64" regnum="58" save-restore="no"
type="ieee_double"/>
<reg name="d8" bitsize="64" regnum="59" save-restore="no"
type="ieee_double"/>
<reg name="d9" bitsize="64" regnum="60" save-restore="no"
type="ieee_double"/>
<reg name="d10" bitsize="64" regnum="61" save-restore="no"
type="ieee_double"/>
<reg name="d11" bitsize="64" regnum="62" save-restore="no"
type="ieee_double"/>
<reg name="d12" bitsize="64" regnum="63" save-restore="no"
type="ieee_double"/>
<reg name="d13" bitsize="64" regnum="64" save-restore="no"
type="ieee_double"/>
<reg name="d14" bitsize="64" regnum="65" save-restore="no"
type="ieee_double"/>
<reg name="d15" bitsize="64" regnum="66" save-restore="no"
type="ieee_double"/>
<reg name="d16" bitsize="64" regnum="67" save-restore="no"
type="ieee_double"/>
<reg name="d17" bitsize="64" regnum="68" save-restore="no"
type="ieee_double"/>
<reg name="d18" bitsize="64" regnum="69" save-restore="no"
type="ieee_double"/>
<reg name="d19" bitsize="64" regnum="70" save-restore="no"
type="ieee_double"/>
<reg name="d20" bitsize="64" regnum="71" save-restore="no"
type="ieee_double"/>
<reg name="d21" bitsize="64" regnum="72" save-restore="no"
type="ieee_double"/>
<reg name="d22" bitsize="64" regnum="73" save-restore="no"
type="ieee_double"/>
<reg name="d23" bitsize="64" regnum="74" save-restore="no"
type="ieee_double"/>
<reg name="d24" bitsize="64" regnum="75" save-restore="no"
type="ieee_double"/>
<reg name="d25" bitsize="64" regnum="76" save-restore="no"
type="ieee_double"/>
<reg name="d26" bitsize="64" regnum="77" save-restore="no"
type="ieee_double"/>
<reg name="d27" bitsize="64" regnum="78" save-restore="no"
type="ieee_double"/>
<reg name="d28" bitsize="64" regnum="79" save-restore="no"
type="ieee_double"/>
<reg name="d29" bitsize="64" regnum="80" save-restore="no"
type="ieee_double"/>
<reg name="d30" bitsize="64" regnum="81" save-restore="no"
type="ieee_double"/>
<reg name="d31" bitsize="64" regnum="82" save-restore="no"
type="ieee_double"/>
<reg name="fpscr" bitsize="32" regnum="83" save-restore="no" type="int"
group="float"/>
</feature>
</target>

(lldb) register read sp_hyp
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/
and include the crash backtrace.
Stack dump:
0.      Program arguments: /usr/local/llvm20/bin/lldb
1.      HandleCommand(command = "register read sp_hyp")
 #0 0x00000008304040a9 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int)
(/usr/local/llvm20/lib/libLLVM.so.20.1+0x44040a9)
 #1 0x0000000830401f55 llvm::sys::RunSignalHandlers()
(/usr/local/llvm20/lib/libLLVM.so.20.1+0x4401f55)
 #2 0x00000008304047b7 (/usr/local/llvm20/lib/libLLVM.so.20.1+0x44047b7)
 #3 0x00000008218064a0 (/lib/libthr.so.3+0x1a4a0)
 #4 0x0000000821805a6b (/lib/libthr.so.3+0x19a6b)
 #5 0x00000008214702d3 ([vdso]+0x2d3)
 #6 0x00000008256c12dc memcpy (/lib/libc.so.7+0x15a2dc)
 #7 0x0000000824625991 (/usr/local/llvm20/lib/liblldb.so.20.1+0xe25991)
 #8 0x000000082462553c (/usr/local/llvm20/lib/liblldb.so.20.1+0xe2553c)
 #9 0x0000000824624f8d (/usr/local/llvm20/lib/liblldb.so.20.1+0xe24f8d)
#10 0x00000008247dac30 (/usr/local/llvm20/lib/liblldb.so.20.1+0xfdac30)
#11 0x00000008247da4ee (/usr/local/llvm20/lib/liblldb.so.20.1+0xfda4ee)
#12 0x0000000824234b31 (/usr/local/llvm20/lib/liblldb.so.20.1+0xa34b31)
#13 0x000000082422524b (/usr/local/llvm20/lib/liblldb.so.20.1+0xa2524b)
#14 0x000000082422993e (/usr/local/llvm20/lib/liblldb.so.20.1+0xa2993e)
#15 0x000000082418c5f0 (/usr/local/llvm20/lib/liblldb.so.20.1+0x98c5f0)
#16 0x000000082416b9e2 (/usr/local/llvm20/lib/liblldb.so.20.1+0x96b9e2)
#17 0x000000082422b8ad (/usr/local/llvm20/lib/liblldb.so.20.1+0xa2b8ad)
#18 0x0000000823e1e0eb lldb::SBDebugger::RunCommandInterpreter(bool, bool)
(/usr/local/llvm20/lib/liblldb.so.20.1+0x61e0eb)
#19 0x000000000020a873 (/usr/local/llvm20/bin/lldb+0x20a873)
#20 0x000000000020b3b9 (/usr/local/llvm20/bin/lldb+0x20b3b9)
#21 0x00000008255ece34 __libc_start1 (/lib/libc.so.7+0x85e34)
LLDB diagnostics will be written to /tmp/diagnostics-19f8fe
Please include the directory content when filing a bug report
Segmentation fault (core dumped)

[openocd:tickets] #456 aducm360 swd could not find MEM-AP

[Den <de...@us...>]

thank you for the information!
so it's not because of the fronts that it doesn't work.
so the problem is something else.


---

**[tickets:#456] aducm360 swd could not find MEM-AP**

**Status:** new
**Milestone:** 0.10.0
**Labels:** aducm360_swd 
**Created:** Tue Jul 01, 2025 01:58 PM UTC by Den
**Last Updated:** Wed Jul 02, 2025 12:19 PM UTC
**Owner:** nobody
**Attachments:**

- [attach.zip](https://sourceforge.net/p/openocd/tickets/456/attachment/attach.zip) (751.5 kB; application/x-zip-compressed)


aducm360 not connect to openocd via jtag-swd.
adapter based on ftdi2232
used original config aducm360.cfg
used my config ftdi_swd.cfg
tested in openocd v10 & v12

command:
openocd.exe -d0 -f \interface\ftdi\ftdi_swd.cfg -f target\aducm360.cfg -c init -c targets -c "reset halt" -c "flash erase 0" -c shutdown

log:
debug_level: 0
cortex_m reset_config vectreset
Error: [aducm360.cpu] Could not find MEM-AP to control the core
    TargetName         Type       Endian TapName            State
--  ------------------ ---------- ------ ------------------ ------------
 0* aducm360.cpu       cortex_m   little aducm360.cpu       unknown
Error: [aducm360.cpu] Could not find MEM-AP to control the core
Error: [aducm360.cpu] Debug AP not available, reset NOT asserted!

in attach log from debug level 3
ftdi_swd.cfg
log saleae logic 1.2.18


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[openocd:tickets] #456 aducm360 swd could not find MEM-AP

[Tomas V. <to...@us...>]

Don't be fooled by this simplified diagram found in ARM documentation: it's so simplified that it's wrong. SWDIO correctly changes on failing SWCLK edge when the adapter transmits and on rising SWCLK edge when SWDP transmits.
See
8690: target/arm_adi: add URLs of latest ARM ADI spec | https://review.openocd.org/c/openocd/+/8690
https://documentation-service.arm.com/static/5ea6eaba9931941038df04ff?token=



---

**[tickets:#456] aducm360 swd could not find MEM-AP**

**Status:** new
**Milestone:** 0.10.0
**Labels:** aducm360_swd 
**Created:** Tue Jul 01, 2025 01:58 PM UTC by Den
**Last Updated:** Wed Jul 02, 2025 11:48 AM UTC
**Owner:** nobody
**Attachments:**

- [attach.zip](https://sourceforge.net/p/openocd/tickets/456/attachment/attach.zip) (751.5 kB; application/x-zip-compressed)


aducm360 not connect to openocd via jtag-swd.
adapter based on ftdi2232
used original config aducm360.cfg
used my config ftdi_swd.cfg
tested in openocd v10 & v12

command:
openocd.exe -d0 -f \interface\ftdi\ftdi_swd.cfg -f target\aducm360.cfg -c init -c targets -c "reset halt" -c "flash erase 0" -c shutdown

log:
debug_level: 0
cortex_m reset_config vectreset
Error: [aducm360.cpu] Could not find MEM-AP to control the core
    TargetName         Type       Endian TapName            State
--  ------------------ ---------- ------ ------------------ ------------
 0* aducm360.cpu       cortex_m   little aducm360.cpu       unknown
Error: [aducm360.cpu] Could not find MEM-AP to control the core
Error: [aducm360.cpu] Debug AP not available, reset NOT asserted!

in attach log from debug level 3
ftdi_swd.cfg
log saleae logic 1.2.18


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[openocd:tickets] #456 aducm360 swd could not find MEM-AP

[Den <de...@us...>]

Judging by the cyclogram from the analyzer, it is possible that the adapter does not correctly set the SWDIO bits in relation to the SWCLK clock signal.
When transmitting from the adapter, the SWDIO bits are set when the SCLK clock signal drops from 1 to 0 (falling edge), although on the found protocol waveforms, the SWDIO data should be set when the difference is from 0 to 1 (rising edge), and read along the falling edge.
At the same time, the device sets the bits on the correct SWCLK edge.
Can someone fix it?
![](https://avatars.mds.yandex.net/i?id=afcf971a16699471bb8a25daee847e52_l-9151021-images-thumbs&n=13)


---

**[tickets:#456] aducm360 swd could not find MEM-AP**

**Status:** new
**Milestone:** 0.10.0
**Labels:** aducm360_swd 
**Created:** Tue Jul 01, 2025 01:58 PM UTC by Den
**Last Updated:** Tue Jul 01, 2025 01:58 PM UTC
**Owner:** nobody
**Attachments:**

- [attach.zip](https://sourceforge.net/p/openocd/tickets/456/attachment/attach.zip) (751.5 kB; application/x-zip-compressed)


aducm360 not connect to openocd via jtag-swd.
adapter based on ftdi2232
used original config aducm360.cfg
used my config ftdi_swd.cfg
tested in openocd v10 & v12

command:
openocd.exe -d0 -f \interface\ftdi\ftdi_swd.cfg -f target\aducm360.cfg -c init -c targets -c "reset halt" -c "flash erase 0" -c shutdown

log:
debug_level: 0
cortex_m reset_config vectreset
Error: [aducm360.cpu] Could not find MEM-AP to control the core
    TargetName         Type       Endian TapName            State
--  ------------------ ---------- ------ ------------------ ------------
 0* aducm360.cpu       cortex_m   little aducm360.cpu       unknown
Error: [aducm360.cpu] Could not find MEM-AP to control the core
Error: [aducm360.cpu] Debug AP not available, reset NOT asserted!

in attach log from debug level 3
ftdi_swd.cfg
log saleae logic 1.2.18


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[openocd:tickets] #456 aducm360 swd could not find MEM-AP

[Den <de...@us...>]

---

**[tickets:#456] aducm360 swd could not find MEM-AP**

**Status:** new
**Milestone:** 0.10.0
**Labels:** aducm360_swd 
**Created:** Tue Jul 01, 2025 01:58 PM UTC by Den
**Last Updated:** Tue Jul 01, 2025 01:58 PM UTC
**Owner:** nobody
**Attachments:**

- [attach.zip](https://sourceforge.net/p/openocd/tickets/456/attachment/attach.zip) (751.5 kB; application/x-zip-compressed)


aducm360 not connect to openocd via jtag-swd.
adapter based on ftdi2232
used original config aducm360.cfg
used my config ftdi_swd.cfg
tested in openocd v10 & v12

command:
openocd.exe -d0 -f \interface\ftdi\ftdi_swd.cfg -f target\aducm360.cfg -c init -c targets -c "reset halt" -c "flash erase 0" -c shutdown

log:
debug_level: 0
cortex_m reset_config vectreset
Error: [aducm360.cpu] Could not find MEM-AP to control the core
    TargetName         Type       Endian TapName            State
--  ------------------ ---------- ------ ------------------ ------------
 0* aducm360.cpu       cortex_m   little aducm360.cpu       unknown
Error: [aducm360.cpu] Could not find MEM-AP to control the core
Error: [aducm360.cpu] Debug AP not available, reset NOT asserted!

in attach log from debug level 3
ftdi_swd.cfg
log saleae logic 1.2.18


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[PATCH]: de35c1b7a2 driver: jtag: rename xlnx-pcie-xvc to xlnx-xvc

[<ge...@op...>]

This is an automated email from Gerrit.

"Nicolas Derumigny <nic...@in...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8980

-- gerrit

commit de35c1b7a201a2e8e6181952cffc9a9ce711fd84
Author: Nicolas Derumigny <nic...@in...>
Date:   Mon Jun 30 11:21:18 2025 +0200

    driver: jtag: rename xlnx-pcie-xvc to xlnx-xvc
    
    Rename xlnx-pcie-xvc.c to xlnx-xvc.c in provision for AXI support
    
    Signed-off-by: Nicolas Derumigny <nic...@in...>
    Change-Id: I287fdcb8edf97f48c6f8614ac4c456f8ba197011

diff --git a/configure.ac b/configure.ac
index 453cbcfb5a..3f79622bf3 100644
--- a/configure.ac
+++ b/configure.ac
@@ -178,7 +178,10 @@ m4_define([LIBJAYLINK_ADAPTERS],
 	[[[jlink], [SEGGER J-Link Programmer], [JLINK]]])
 
 m4_define([PCIE_ADAPTERS],
-	[[[xlnx_pcie_xvc], [Xilinx XVC/PCIe], [XLNX_PCIE_XVC]]])
+	[[[xlnx_pcie_xvc], [Xilinx XVC/PCIe], [XLNX_XVC]]])
+
+m4_define([AXI_ADAPTERS],
+	[[[xlnx_axi_xvc], [Xilinx XVC/AXI], [XLNX_XVC]]])
 
 m4_define([SERIAL_PORT_ADAPTERS],
 	[[[buspirate], [Bus Pirate], [BUS_PIRATE]]])
@@ -336,6 +339,7 @@ AC_ARG_ADAPTERS([
   JTAG_VPI_ADAPTER,
   RSHIM_ADAPTER,
   PCIE_ADAPTERS,
+  AXI_ADAPTERS,
   LIBJAYLINK_ADAPTERS
   ],[auto])
 
@@ -657,6 +661,8 @@ PROCESS_ADAPTERS([RSHIM_ADAPTER], ["x$can_build_rshim" = "xyes"],
 PROCESS_ADAPTERS([AMTJTAGACCEL_ADAPTER], [true], [unused])
 PROCESS_ADAPTERS([HOST_ARM_BITBANG_ADAPTERS], [true], [unused])
 PROCESS_ADAPTERS([HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS], [true], [unused])
+PROCESS_ADAPTERS([PCIE_ADAPTERS], ["x$is_linux" = "xyes" -a "x$use_libgpiod" = "xyes"], [Linux build and libgpiod])
+PROCESS_ADAPTERS([AXI_ADAPTERS], ["x$is_linux" = "xyes" -a "x$use_libgpiod" = "xyes"], [Linux build and libgpiod])
 PROCESS_ADAPTERS([DUMMY_ADAPTER], [true], [unused])
 
 AS_IF([test "x$enable_linuxgpiod" != "xno"], [
@@ -840,7 +846,8 @@ m4_foreach([adapterTuple], [USB1_ADAPTERS,
 	DMEM_ADAPTER,
 	SYSFSGPIO_ADAPTER,
 	REMOTE_BITBANG_ADAPTER,
-	LIBJAYLINK_ADAPTERS, PCIE_ADAPTERS, SERIAL_PORT_ADAPTERS,
+	LIBJAYLINK_ADAPTERS, PCIE_ADAPTERS,
+	AXI_ADAPTERS, SERIAL_PORT_ADAPTERS,
 	LINUXSPIDEV_ADAPTER,
 	VDEBUG_ADAPTER,
 	JTAG_DPI_ADAPTER,
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index b0dd8e3ad1..e55e0478c6 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -179,8 +179,8 @@ endif
 if LINUXSPIDEV
 DRIVERFILES += %D%/linuxspidev.c
 endif
-if XLNX_PCIE_XVC
-DRIVERFILES += %D%/xlnx-pcie-xvc.c
+if XLNX_XVC
+DRIVERFILES += %D%/xlnx-xvc.c
 endif
 if BCM2835GPIO
 DRIVERFILES += %D%/bcm2835gpio.c
diff --git a/src/jtag/drivers/xlnx-pcie-xvc.c b/src/jtag/drivers/xlnx-xvc.c
similarity index 100%
rename from src/jtag/drivers/xlnx-pcie-xvc.c
rename to src/jtag/drivers/xlnx-xvc.c

-- 

[PATCH]: 9845e4f08f tcl/target/max32xxx: Add max3267x support

[<ge...@op...>]

This is an automated email from Gerrit.

"Henrik Mau <hen...@an...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8979

-- gerrit

commit 9845e4f08f54398e519b2717acd1e507c15a15da
Author: Henrik Mau <hen...@an...>
Date:   Mon Jun 30 13:23:23 2025 +0100

    tcl/target/max32xxx: Add max3267x support
    
    Add configuration files for max32670, max32672 and max32675
    
    Change-Id: I073db6294740bf46713134d75f718dfc7338156e
    Signed-off-by: Henrik Mau <hen...@an...>

diff --git a/tcl/target/max32670.cfg b/tcl/target/max32670.cfg
new file mode 100644
index 0000000000..1042bb6b99
--- /dev/null
+++ b/tcl/target/max32670.cfg
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# maxim Integrated OpenOCD target configuration file
+
+# reset pin configuration
+reset_config none
+adapter_nsrst_delay 200
+adapter_nsrst_assert_width 200
+
+# Set flash parameters
+set FLASH_BASE 0x10000000
+set FLASH_SIZE 0x60000
+set FLC_BASE 0x40029000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 96
+set FLASH_OPTIONS 0x01
+
+# Use Serial Wire Debug
+transport select swd
+
+source [find target/max32xxx.cfg]
+
+global rom_bp_enabled
+set rom_bp_enabled "no"
+
+# Override default init_reset{mode} to catch parameter "mode"
+proc init_reset {mode} {
+	global sp_reset_mode
+	set sp_reset_mode $mode
+}
+
+$_CHIPNAME.cpu configure -event reset-deassert-post {
+  global sp_reset_mode
+  global _CHIPNAME
+
+	if { ([string compare $sp_reset_mode "init"] == 0) } {
+    set state "reset"
+    while { [string compare $state "reset"] == 0 } {
+      set state [$_CHIPNAME.cpu curstate]
+      $_CHIPNAME.cpu arp_poll
+      }
+    $_CHIPNAME.cpu arp_halt
+  }
+}
+
+$_CHIPNAME.cpu configure -event reset-assert-pre {
+  global sp_reset_mode
+  global rom_bp_enabled
+
+  if { (([string compare $sp_reset_mode "halt"] == 0) || ([string compare $sp_reset_mode "init"] == 0)) } {
+    halt
+   	if { ([string compare $rom_bp_enabled "yes"] == 0) } {
+      rbp 0x00002174
+      }
+    bp 0x00002174 2 hw
+    set rom_bp_enabled "yes"
+  }
+}
+
+$_CHIPNAME.cpu configure -event halted {
+  global sp_reset_mode
+  global rom_bp_enabled
+
+	if { ([string compare $rom_bp_enabled "yes"] == 0) } {
+    rbp 0x00002174
+    set rom_bp_enabled "no"
+  }
+  set sp_reset_mode none
+}
diff --git a/tcl/target/max32672.cfg b/tcl/target/max32672.cfg
new file mode 100644
index 0000000000..26c7c82dbc
--- /dev/null
+++ b/tcl/target/max32672.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# maxim Integrated OpenOCD target configuration file
+
+# reset pin configuration
+reset_config none
+adapter_nsrst_delay 200
+adapter_nsrst_assert_width 200
+
+# Set flash parameters
+set FLASH_BASE 0x10000000
+set FLASH_SIZE 0x80000
+set FLC_BASE 0x40029000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 96
+set FLASH_OPTIONS 0x01
+
+# Use Serial Wire Debug
+transport select swd
+
+source [find target/max32xxx.cfg]
+
+# Add additional flash bank
+set FLASH_BASE 0x10080000
+set FLC_BASE 0x40029400
+
+flash bank $_CHIPNAME.flash1 max32xxx $FLASH_BASE $FLASH_SIZE 0 0 $_CHIPNAME.cpu \
+$FLC_BASE $FLASH_SECTOR $FLASH_CLK $FLASH_OPTIONS
diff --git a/tcl/target/max32675.cfg b/tcl/target/max32675.cfg
new file mode 100644
index 0000000000..1042bb6b99
--- /dev/null
+++ b/tcl/target/max32675.cfg
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# maxim Integrated OpenOCD target configuration file
+
+# reset pin configuration
+reset_config none
+adapter_nsrst_delay 200
+adapter_nsrst_assert_width 200
+
+# Set flash parameters
+set FLASH_BASE 0x10000000
+set FLASH_SIZE 0x60000
+set FLC_BASE 0x40029000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 96
+set FLASH_OPTIONS 0x01
+
+# Use Serial Wire Debug
+transport select swd
+
+source [find target/max32xxx.cfg]
+
+global rom_bp_enabled
+set rom_bp_enabled "no"
+
+# Override default init_reset{mode} to catch parameter "mode"
+proc init_reset {mode} {
+	global sp_reset_mode
+	set sp_reset_mode $mode
+}
+
+$_CHIPNAME.cpu configure -event reset-deassert-post {
+  global sp_reset_mode
+  global _CHIPNAME
+
+	if { ([string compare $sp_reset_mode "init"] == 0) } {
+    set state "reset"
+    while { [string compare $state "reset"] == 0 } {
+      set state [$_CHIPNAME.cpu curstate]
+      $_CHIPNAME.cpu arp_poll
+      }
+    $_CHIPNAME.cpu arp_halt
+  }
+}
+
+$_CHIPNAME.cpu configure -event reset-assert-pre {
+  global sp_reset_mode
+  global rom_bp_enabled
+
+  if { (([string compare $sp_reset_mode "halt"] == 0) || ([string compare $sp_reset_mode "init"] == 0)) } {
+    halt
+   	if { ([string compare $rom_bp_enabled "yes"] == 0) } {
+      rbp 0x00002174
+      }
+    bp 0x00002174 2 hw
+    set rom_bp_enabled "yes"
+  }
+}
+
+$_CHIPNAME.cpu configure -event halted {
+  global sp_reset_mode
+  global rom_bp_enabled
+
+	if { ([string compare $rom_bp_enabled "yes"] == 0) } {
+    rbp 0x00002174
+    set rom_bp_enabled "no"
+  }
+  set sp_reset_mode none
+}

-- 

[PATCH]: e29badce5a tcl/target/max32680: Add max32680 support

[<ge...@op...>]

This is an automated email from Gerrit.

"Henrik Mau <hen...@an...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8978

-- gerrit

commit e29badce5a3c65e1c24643013f80f532bf2fb444
Author: Henrik Mau <hen...@an...>
Date:   Mon Jun 30 11:53:42 2025 +0100

    tcl/target/max32680: Add max32680 support
    
    Add configuration file for max32680
    
    Change-Id: Ibe290fd6d964ae3355f4e064f65b4510a9cbf5dd
    Signed-off-by: Henrik Mau <hen...@an...>

diff --git a/tcl/target/max32680.cfg b/tcl/target/max32680.cfg
new file mode 100644
index 0000000000..064b5cdd12
--- /dev/null
+++ b/tcl/target/max32680.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Maxim Integrated MAX32655 OpenOCD target configuration file
+
+adapter speed 500
+
+# Set the reset pin configuration
+reset_config srst_only
+adapter srst delay 2
+adapter srst pulse_width 2
+
+# Set flash parameters
+set FLASH_BASE 0x10000000
+set FLASH_SIZE 0x80000
+set FLC_BASE 0x40029000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 100
+set FLASH_OPTIONS 0x01
+
+# Use Serial Wire Debug
+transport select swd
+
+source [find target/max32xxx.cfg]

-- 

[PATCH]: 0d6846113b tcl/target/max32690: Add max32690 support

[<ge...@op...>]

This is an automated email from Gerrit.

"Henrik Mau <hen...@an...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8977

-- gerrit

commit 0d6846113b671cb29eac8a1d085a5a9ca15c6a91
Author: Henrik Mau <hen...@an...>
Date:   Mon Jun 30 11:32:44 2025 +0100

    tcl/target/max32690: Add max32690 support
    
    Add configuration file for max32690
    
    Change-Id: I30d90da176f85feba8369c96e1a0bb82a39eca5f
    Signed-off-by: Henrik Mau <hen...@an...>

diff --git a/tcl/target/max32690.cfg b/tcl/target/max32690.cfg
new file mode 100644
index 0000000000..588ebe7e39
--- /dev/null
+++ b/tcl/target/max32690.cfg
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Maxim Integrated MAX32690 OpenOCD target configuration file
+
+# Set the reset pin configuration
+reset_config srst_only
+adapter srst delay 2
+adapter srst pulse_width 2
+
+# Set flash parameters
+set FLASH_BASE 0x10000000
+set FLASH_SIZE 0x300000
+set FLC_BASE 0x40029000
+set FLASH_SECTOR 0x4000
+set FLASH_CLK 60
+set FLASH_OPTIONS 0x01
+
+# Use Serial Wire Debug
+transport select swd
+
+source [find target/max32xxx.cfg]
+
+# Add additional flash bank
+set FLASH_BASE 0x10300000
+set FLASH_SIZE 0x40000
+set FLC_BASE 0x40029400
+set FLASH_SECTOR 0x2000
+
+flash bank $_CHIPNAME.flash1 max32xxx $FLASH_BASE $FLASH_SIZE 0 0 $_CHIPNAME.cpu \
+$FLC_BASE $FLASH_SECTOR $FLASH_CLK $FLASH_OPTIONS
+
+global rom_bp_enabled
+set rom_bp_enabled "no"
+
+# Override default init_reset{mode} to catch parameter "mode"
+proc init_reset {mode} {
+	global sp_reset_mode
+	set sp_reset_mode $mode
+}
+
+$_CHIPNAME.cpu configure -event reset-deassert-post {
+  global sp_reset_mode
+  global _CHIPNAME
+
+	if { ([string compare $sp_reset_mode "init"] == 0) } {
+    set state "reset"
+    while { [string compare $state "reset"] == 0 } {
+      set state [$_CHIPNAME.cpu curstate]
+      $_CHIPNAME.cpu arp_poll
+      }
+    $_CHIPNAME.cpu arp_halt
+  }
+}
+
+$_CHIPNAME.cpu configure -event reset-assert-pre {
+  global sp_reset_mode
+  global rom_bp_enabled
+
+  if { (([string compare $sp_reset_mode "halt"] == 0) || ([string compare $sp_reset_mode "init"] == 0)) } {
+    halt
+   	if { ([string compare $rom_bp_enabled "yes"] == 0) } {
+      rbp 0x0000FFF4
+      }
+    bp 0x0000FFF4 2 hw
+    set rom_bp_enabled "yes"
+  }
+}
+
+$_CHIPNAME.cpu configure -event halted {
+  global sp_reset_mode
+  global rom_bp_enabled
+
+	if { ([string compare $rom_bp_enabled "yes"] == 0) } {
+    rbp 0x0000FFF4
+    set rom_bp_enabled "no"
+  }
+  set sp_reset_mode none
+}

-- 

[PATCH]: 8b01049032 tcl/target/max32xxx: Update max32xxx tcl files to use new flashing algorithm

[<ge...@op...>]

This is an automated email from Gerrit.

"Henrik Mau <hen...@an...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8976

-- gerrit

commit 8b01049032df7210122ccb005f560c566463aead
Author: Henrik Mau <hen...@an...>
Date:   Mon Jun 30 10:48:04 2025 +0100

    tcl/target/max32xxx: Update max32xxx tcl files to use new flashing algorithm
    
    The max32xxx tcl files have been updated to work with the new flashing
    algorithm. A new max32xxx.cfg file contains common configuration and
    functionality.
    
    Change-Id: Ifaed58836d221ece6192faafa382b30fb72c77a6
    Signed-off-by: Henrik Mau <hen...@an...>

diff --git a/tcl/target/max32620.cfg b/tcl/target/max32620.cfg
index f3a9f84c88..b5bccb3084 100644
--- a/tcl/target/max32620.cfg
+++ b/tcl/target/max32620.cfg
@@ -1,32 +1,20 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 # Maxim Integrated MAX32620 OpenOCD target configuration file
-# www.maximintegrated.com
 
-# adapter speed
-adapter speed 4000
-
-# reset pin configuration
+# Set the reset pin configuration
 reset_config srst_only
+adapter srst delay 200
 
-if {[using_jtag]} {
-    jtag newtap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
-    jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version
-} else {
-    swd newdap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
-}
-
-dap create max32620.dap -chain-position max32620.cpu
+# Set flash parameters
+set FLASH_BASE 0x0
+set FLASH_SIZE 0x200000
+set FLC_BASE 0x40002000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 96
+set FLASH_OPTIONS 0x00
 
-# target configuration
-target create max32620.cpu cortex_m -dap max32620.dap
-max32620.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
+# Setup the reserved TAP
+set RSV_TAP 1
 
-# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
-#   flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst>
-#   max32620 flash base address   0x00000000
-#   max32620 flash size           0x200000 (2MB)
-#   max32620 FLC base address     0x40002000
-#   max32620 sector (page) size   0x2000 (8kB)
-#   max32620 clock speed          96 (MHz)
-flash bank max32620.flash max32xxx 0x00000000 0x200000 0 0 max32620.cpu 0x40002000 0x2000 96
+source [find target/max32xxx.cfg]
\ No newline at end of file
diff --git a/tcl/target/max32625.cfg b/tcl/target/max32625.cfg
index 90eb392668..8a52b0d6b1 100644
--- a/tcl/target/max32625.cfg
+++ b/tcl/target/max32625.cfg
@@ -1,32 +1,20 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 # Maxim Integrated MAX32625 OpenOCD target configuration file
-# www.maximintegrated.com
 
-# adapter speed
-adapter speed 4000
-
-# reset pin configuration
+# Set the reset pin configuration
 reset_config srst_only
+adapter srst delay 200
 
-if {[using_jtag]} {
-    jtag newtap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
-    jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f71197 -ignore-version
-} else {
-    swd newdap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
-}
-
-dap create max32625.dap -chain-position max32625.cpu
+# Set flash parameters
+set FLASH_BASE 0x0
+set FLASH_SIZE 0x80000
+set FLC_BASE 0x40002000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 96
+set FLASH_OPTIONS 0x00
 
-# target configuration
-target create max32625.cpu cortex_m -dap max32625.dap
-max32625.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
+# Setup the reserved TAP
+set RSV_TAP 1
 
-# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
-#   flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst>
-#   max32625 flash base address   0x00000000
-#   max32625 flash size           0x80000 (512k)
-#   max32625 FLC base address     0x40002000
-#   max32625 sector (page) size   0x2000 (8kB)
-#   max32625 clock speed          96 (MHz)
-flash bank max32625.flash max32xxx 0x00000000 0x80000 0 0 max32625.cpu 0x40002000 0x2000 96
+source [find target/max32xxx.cfg]
\ No newline at end of file
diff --git a/tcl/target/max3263x.cfg b/tcl/target/max3263x.cfg
index 852e04af1e..39b6663403 100644
--- a/tcl/target/max3263x.cfg
+++ b/tcl/target/max3263x.cfg
@@ -1,32 +1,40 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 # Maxim Integrated MAX3263X OpenOCD target configuration file
-# www.maximintegrated.com
 
-# adapter speed
-adapter speed 4000
+# Set the reset pin configuration
+reset_config none
 
-# reset pin configuration
-reset_config srst_only
+# Set flash parameters
+set FLASH_BASE 0x0
+set FLASH_SIZE 0x200000
+set FLC_BASE 0x40002000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 96
+set FLASH_OPTIONS 0x00
 
-if {[using_jtag]} {
-    jtag newtap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
-    jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f76197 -ignore-version
-} else {
-    swd newdap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
-}
+# Setup the reserved TAP
+set RSV_TAP 1
+
+source [find target/max32xxx.cfg]
+
+# Create custom reset sequence
+$_CHIPNAME.cpu configure -event reset-init {
 
-dap create max3263x.dap -chain-position max3263x.cpu
+    # Reset the peripherals
+    mww 0x40000848 0xFFFFFFFF
+    mww 0x4000084C 0xFFFFFFFF
 
-# target configuration
-target create max3263x.cpu cortex_m -dap max3263x.dap
-max3263x.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
+    sleep 10
 
-# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
-#   flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst>
-#   max3263x flash base address   0x00000000
-#   max3263x flash size           0x200000 (2MB)
-#   max3263x FLC base address     0x40002000
-#   max3263x sector (page) size   0x2000 (8kB)
-#   max3263x clock speed          96 (MHz)
-flash bank max3263x.flash max32xxx 0x00000000 0x200000 0 0 max3263x.cpu 0x40002000 0x2000 96
+    mww 0x40000848 0x0
+    mww 0x4000084C 0x0
+
+    # Reset the SP
+    set SP_ADDR [mrw 0x0]
+    reg sp $SP_ADDR
+
+    # Reset the PC to the Reset_Handler
+    set RESET_HANDLER_ADDR  [mrw 0x4]
+    reg pc $RESET_HANDLER_ADDR
+}
diff --git a/tcl/target/max32xxx.cfg b/tcl/target/max32xxx.cfg
new file mode 100644
index 0000000000..66c7135731
--- /dev/null
+++ b/tcl/target/max32xxx.cfg
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Maxim Integrated max32xxx OpenOCD drver configuration file
+
+source [find mem_helper.tcl]
+source [find target/swj-dp.tcl]
+
+# Set the adapter speed
+if { [info exists ADAPTER_KHZ] } {
+   set _ADAPTER_KHZ $ADAPTER_KHZ
+} else {
+   set _ADAPTER_KHZ 2000
+}
+adapter speed $_ADAPTER_KHZ
+
+# Target configuration
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME max32xxx
+}
+
+# Add reserved TAP
+if { [using_jtag] && [info exists RSV_TAP] } {
+   jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -ignore-version
+   jtag newtap rsvtap tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version
+} else {
+   swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -ignore-version
+}
+
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_CHIPNAME.cpu cortex_m -dap $_CHIPNAME.dap
+
+# Enable thread-aware debugging
+$_CHIPNAME.cpu configure -rtos auto
+
+# Setup working area
+if { [info exists WORK_START] } {
+   set _WORK_START $WORK_START
+} else {
+   set _WORK_START 0x20005000
+}
+
+if { [info exists WORK_SIZE] } {
+   set _WORK_SIZE $WORK_SIZE
+} else {
+   set _WORK_SIZE 0x8000
+}
+
+$_CHIPNAME.cpu configure -work-area-phys $_WORK_START -work-area-size $_WORK_SIZE
+
+# Configure flash driver
+if { [info exists FLASH_BASE] } {
+   set _FLASH_BASE $FLASH_BASE
+} else {
+   set _FLASH_BASE 0x10000000
+}
+
+if { [info exists FLASH_SIZE] } {
+   set _FLASH_SIZE $FLASH_SIZE
+} else {
+   set _FLASH_SIZE 0x10000
+}
+
+if { [info exists FLC_BASE] } {
+   set _FLC_BASE $FLC_BASE
+} else {
+   set _FLC_BASE 0x40029000
+}
+
+if { [info exists FLASH_SECTOR] } {
+   set _FLASH_SECTOR $FLASH_SECTOR
+} else {
+   set _FLASH_SECTOR 0x2000
+}
+
+if { [info exists FLASH_CLK] } {
+   set _FLASH_CLK $FLASH_CLK
+} else {
+   set _FLASH_CLK 96
+}
+
+# OPTIONS_128                     0x01 /* Perform 128 bit flash writes */
+# OPTIONS_ENC                     0x02 /* Encrypt the flash contents */
+# OPTIONS_AUTH                    0x04 /* Authenticate the flash contents */
+# OPTIONS_COUNT                   0x08 /* Add counter values to authentication */
+# OPTIONS_INTER                   0x10 /* Interleave the authentication and count values*/
+# OPTIONS_RELATIVE_XOR            0x20 /* Only XOR the offset of the address when encrypting */
+# OPTIONS_KEYSIZE                 0x40 /* Use a 256 bit KEY */
+
+if { [info exists FLASH_OPTIONS] } {
+   set _FLASH_OPTIONS $FLASH_OPTIONS
+} else {
+   set _FLASH_OPTIONS 0
+}
+
+flash bank $_CHIPNAME.flash max32xxx $_FLASH_BASE $_FLASH_SIZE 0 0 $_CHIPNAME.cpu \
+$_FLC_BASE $_FLASH_SECTOR $_FLASH_CLK $_FLASH_OPTIONS
+
+# call allow_low_pwr_dbg to set this to 1
+set ALLOW_LOW_PWR_DBG 0
+
+proc allow_low_pwr_dbg {} {
+   global ALLOW_LOW_PWR_DBG
+
+   # set our low-power debug flag
+   set ALLOW_LOW_PWR_DBG 1
+}
+
+# enable debug in case of low-power mode
+proc enable_debug {} {
+   set DBGKEY 0xA05F0000
+   set C_DEBUGEN 0x00000001
+   set C_HALT 0x00000002
+
+   echo "Enable debug to connect in low-power mode"
+
+   # enable debug
+   mww 0xE000EDF0 [expr {$DBGKEY | $C_HALT | $C_DEBUGEN}]
+
+   # allow for time waking up
+   sleep 500
+}
+
+$_CHIPNAME.cpu configure -event reset-deassert-post {
+   global ALLOW_LOW_PWR_DBG
+
+   if { $ALLOW_LOW_PWR_DBG == 1 } {
+      enable_debug
+   }
+}
+
+# first thing called once target examined flag is set
+# $_CHIPNAME.cpu configure -event examine-first {
+#    global ALLOW_LOW_PWR_DBG
+
+#    if { $ALLOW_LOW_PWR_DBG == 1 } {
+#       enable_debug
+#    }
+# }

-- 

MSYS2 has no jimtcl lib package (was: Building openOCD after patch [8383])

[Tomas V. <to...@us...>]

On 26/06/2025 16:13, Ivan Kryvosheia wrote:
> Hi Tomas!
> I have problem building openOCD project after this patch with a change 
> to jimctl
> https://review.openocd.org/c/openocd/+/8383
>
> Before I just used
> ./bootstrap
> git submodule init
> git submodule update
> ./configure
> make -j8
>
> and it worked
> but now I constantly have error with jimtcl
> "checking for jimtcl >= 0.79... no
> checking for jim.h... no"
>
> Am I supposed to apply another steps?
>
> PS: windows, msys2
>
> Thank you a lot!
>
> Best regards,
> Ivan Kryvosheia

The fast workaround is easy - ensure jimtcl source is checked-out in 
jimtcl directory and
./configure --enable-internal-jimtcl

However in future we need to persuade MSYS2 project guys to add a jimtcl 
lib package.
I searched pull requests and issues in 
https://github.com/msys2/MINGW-packages
and didn't found anything relevant.

Any volunteer to describe the issue and possibly create and submit PR?

Tomas

[PATCH]: 98d7b4a87b armv8m: Add support for msplim/psplim for targets with no secext

[<ge...@op...>]

This is an automated email from Gerrit.

"Ivan <Iva...@in...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8887

-- gerrit

commit 98d7b4a87bcc00fa6e994e9fdc0fb978239e7823
Author: kryvosheiaivan <Iva...@in...>
Date:   Thu Jun 26 19:20:39 2025 +0300

    armv8m: Add support for msplim/psplim for targets with no secext
    
    When armv8m does not have security extension, it still has msplim/psplim regs
    implemented, which is described in Cortex-M33 Devices Generic User Guide
    Document ID: 100235_0100_05_en, or at the link:
    https://developer.arm.com/documentation/100230/0002/functional-description/programmers-model/processor-core-registers-summary
    Tested on cyw20829 along with gdb v14.2.1
    
    Change-Id: I4f060e4df742c6773e79ce0481697361202d544c
    Signed-off-by: kryvosheiaivan <Iva...@in...>

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 8eaf70f60a..94cd3f683b 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2716,10 +2716,26 @@ int cortex_m_examine(struct target *target)
 		if (armv7m->fp_feature != FPV5_MVE_F && armv7m->fp_feature != FPV5_MVE_I)
 			armv7m->arm.core_cache->reg_list[ARMV8M_VPR].exist = false;
 
-		if (!cortex_m_has_tz(target))
+		bool cm_has_tz = cortex_m_has_tz(target);
+		if (!cm_has_tz)
 			for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++)
 				armv7m->arm.core_cache->reg_list[idx].exist = false;
 
+		/* The MSPLIM_NS and PSPLIM_NS registers are always present on ARMv8M, regardless of TZ */
+		if (armv7m->arm.arch == ARM_ARCH_V8M) {
+			armv7m->arm.core_cache->reg_list[ARMV8M_MSPLIM_NS].exist = true;
+			armv7m->arm.core_cache->reg_list[ARMV8M_PSPLIM_NS].exist = true;
+
+			/* If TZ is not implemented, rename xSPLIM_NS to simply xSPLIM */
+			if (!cm_has_tz) {
+				const char* feature_name = "armv8m.no.secext";
+				armv7m->arm.core_cache->reg_list[ARMV8M_MSPLIM_NS].name = "msplim";
+				armv7m->arm.core_cache->reg_list[ARMV8M_PSPLIM_NS].name = "psplim";
+				armv7m->arm.core_cache->reg_list[ARMV8M_MSPLIM_NS].feature->name = feature_name;
+				armv7m->arm.core_cache->reg_list[ARMV8M_PSPLIM_NS].feature->name = feature_name;
+			}
+		}
+
 		if (!armv7m->is_hla_target) {
 			if (cortex_m->core_info->flags & CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K)
 				/* Cortex-M3/M4 have 4096 bytes autoincrement range,

-- 

[PATCH]: a6fcd0a653 tcl/board/ti_*_swd_native.cfg: Add explicit transport info

[<ge...@op...>]

This is an automated email from Gerrit.

"Nishanth Menon <nm...@ti...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8975

-- gerrit

commit a6fcd0a653404501c6d0d84f15180adabd7fd6ab
Author: Nishanth Menon <nm...@ti...>
Date:   Mon Jun 23 12:41:04 2025 -0500

    tcl/board/ti_*_swd_native.cfg: Add explicit transport info
    
    We use swd emulation in direct memory operations. Instead of relying
    on deprecated autoselect of transport, explicitly state swd as
    transport scheme.
    
    Change-Id: Iec7e2ad18edd365992cd7ba88558494bccf49fd2
    Signed-off-by: Nishanth Menon <nm...@ti...>

diff --git a/tcl/board/ti_am625_swd_native.cfg b/tcl/board/ti_am625_swd_native.cfg
index dc4b20579d..65314fe5dc 100644
--- a/tcl/board/ti_am625_swd_native.cfg
+++ b/tcl/board/ti_am625_swd_native.cfg
@@ -14,6 +14,7 @@
 
 # We are using dmem, which uses dapdirect_swd transport
 adapter driver dmem
+transport select swd
 
 if { ![info exists SOC] } {
 	set SOC am625
diff --git a/tcl/board/ti_am62a7_swd_native.cfg b/tcl/board/ti_am62a7_swd_native.cfg
index 99fc0b0b38..3d5e892289 100644
--- a/tcl/board/ti_am62a7_swd_native.cfg
+++ b/tcl/board/ti_am62a7_swd_native.cfg
@@ -14,6 +14,7 @@
 
 # We are using dmem, which uses dapdirect_swd transport
 adapter driver dmem
+transport select swd
 
 if { ![info exists SOC] } {
 	set SOC am62a7
diff --git a/tcl/board/ti_am62p_swd_native.cfg b/tcl/board/ti_am62p_swd_native.cfg
index fa549f3585..a8c6bd1204 100644
--- a/tcl/board/ti_am62p_swd_native.cfg
+++ b/tcl/board/ti_am62p_swd_native.cfg
@@ -14,6 +14,7 @@
 
 # We are using dmem, which uses dapdirect_swd transport
 adapter driver dmem
+transport select swd
 
 if { ![info exists SOC] } {
 	set SOC am62p
diff --git a/tcl/board/ti_j721e_swd_native.cfg b/tcl/board/ti_j721e_swd_native.cfg
index 3041c3c345..38316387af 100644
--- a/tcl/board/ti_j721e_swd_native.cfg
+++ b/tcl/board/ti_j721e_swd_native.cfg
@@ -14,6 +14,7 @@
 
 # We are using dmem, which uses dapdirect_swd transport
 adapter driver dmem
+transport select swd
 
 if { ![info exists SOC] } {
         set SOC j721e
diff --git a/tcl/board/ti_j722s_swd_native.cfg b/tcl/board/ti_j722s_swd_native.cfg
index bbe0d508c8..a171ec3586 100644
--- a/tcl/board/ti_j722s_swd_native.cfg
+++ b/tcl/board/ti_j722s_swd_native.cfg
@@ -15,6 +15,7 @@
 
 # We are using dmem, which uses dapdirect_swd transport
 adapter driver dmem
+transport select swd
 
 if { ![info exists SOC] } {
 	set SOC j722s

-- 

[PATCH]: 13cf15ffdc jtag/drivers: dmem: fix build on Linux 32 bits

[<ge...@op...>]

This is an automated email from Gerrit.

"Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8974

-- gerrit

commit 13cf15ffdc6b9fd5ecd52e7db3603f17f0b62dd3
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jun 22 11:03:41 2025 +0200

    jtag/drivers: dmem: fix build on Linux 32 bits
    
    On 32 bits machine both 'uintptr_t' and pointers are 32 bit.
    The cast
    (volatile uint32_t *)((uintptr_t)dmem_emu_virt_base_addr + addr)
    fails with error
            error: cast to pointer from integer of different size
            [-Werror=int-to-pointer-cast]
    in lines 100 and 109 because:
    - 'addr' is a 'uint64_t';
    - adding 'uintptr_t' and 'uint64_t' returns a 64 bit value;
    - cast the 64 bit to 'uint32_t *' is an error.
    
    In the code the value passed to 'addr' is always 32 bit wide, so
    there is no need to pass it as 'uint64_t'.
    
    Change the type of 'addr' to 'uint32_t'.
    Fix also some format string to fit both 32 and 64 bits machines.
    
    Change-Id: I90ff7cd3731cb24a0fc91fe7b69c532b5c698ba0
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/src/jtag/drivers/dmem.c b/src/jtag/drivers/dmem.c
index e50e84aeeb..b5c6a794fa 100644
--- a/src/jtag/drivers/dmem.c
+++ b/src/jtag/drivers/dmem.c
@@ -93,14 +93,14 @@ static bool dmem_is_emulated_ap(struct adiv5_ap *ap, unsigned int *idx)
 	return false;
 }
 
-static void dmem_emu_set_ap_reg(uint64_t addr, uint32_t val)
+static void dmem_emu_set_ap_reg(uint32_t addr, uint32_t val)
 {
 	addr &= ~ARM_APB_PADDR31;
 
 	*(volatile uint32_t *)((uintptr_t)dmem_emu_virt_base_addr + addr) = val;
 }
 
-static uint32_t dmem_emu_get_ap_reg(uint64_t addr)
+static uint32_t dmem_emu_get_ap_reg(uint32_t addr)
 {
 	uint32_t val;
 
@@ -519,7 +519,7 @@ static int dmem_dap_init(void)
 						 MAP_SHARED, dmem_fd,
 						 dmem_mapped_start);
 	if (dmem_map_base == MAP_FAILED) {
-		LOG_ERROR("Mapping address 0x%lx for 0x%lx bytes failed!",
+		LOG_ERROR("Mapping address 0x%zx for 0x%zx bytes failed!",
 			dmem_mapped_start, dmem_mapped_size);
 		goto error_fail;
 	}
@@ -543,7 +543,7 @@ static int dmem_dap_init(void)
 									   MAP_SHARED, dmem_fd,
 									   dmem_mapped_start);
 		if (dmem_emu_map_base == MAP_FAILED) {
-			LOG_ERROR("Mapping EMU address 0x%lx for 0x%lx bytes failed!",
+			LOG_ERROR("Mapping EMU address 0x%" PRIx64 " for 0x%" PRIx64 " bytes failed!",
 					  dmem_emu_base_address, dmem_emu_size);
 			goto error_fail;
 		}

-- 

[PATCH]: 76734b1388 jtag/drivers/cmsis_dap: add new backend cmsis_dap_tcp

[<ge...@op...>]

This is an automated email from Gerrit.

"Brian Kuschak <bku...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8973

-- gerrit

commit 76734b1388535aeff1a87715880b0c6e3945970c
Author: Brian Kuschak <bku...@gm...>
Date:   Wed Jun 11 12:41:04 2025 +0800

    jtag/drivers/cmsis_dap: add new backend cmsis_dap_tcp
    
    Create a new backend for cmsis_dap driver that allows CMSIS-DAP protocol
    to run over TCP/IP instead of USB.
    
    An implementation of the firmware for an SWD programmer that uses this
    cmsis_dap_tcp protocol can be found at the link below.
    https://github.com/bkuschak/cmsis_dap_tcp_esp32
    
    Using this cmsis_dap_tcp backend with the firmware above, flashing a
    64KB image to an STM32 completes in about 8 seconds.
    
    Change-Id: I6e3e45016bd16ef2259561b1046788f5536b0687
    Signed-off-by: Brian Kuschak <bku...@gm...>

diff --git a/configure.ac b/configure.ac
index 4b94716299..22e5e7bd05 100644
--- a/configure.ac
+++ b/configure.ac
@@ -206,6 +206,9 @@ m4_define([HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS],
 	[[imx_gpio], [Bitbanging on NXP IMX processors], [IMX_GPIO]],
 	[[am335xgpio], [Bitbanging on AM335x (as found in Beaglebones)], [AM335XGPIO]]])
 
+m4_define([CMSIS_DAP_TCP_ADAPTER],
+	[[[cmsis_dap_tcp], [CMSIS-DAP v2 compliant dongle (TCP)], [CMSIS_DAP_TCP]]])
+
 # The word 'Adapter' in "Dummy Adapter" below must begin with a capital letter
 # because there is an M4 macro called 'adapter'.
 m4_define([DUMMY_ADAPTER],
@@ -338,7 +341,8 @@ AC_ARG_ADAPTERS([
   JTAG_VPI_ADAPTER,
   RSHIM_ADAPTER,
   PCIE_ADAPTERS,
-  LIBJAYLINK_ADAPTERS
+  LIBJAYLINK_ADAPTERS,
+  CMSIS_DAP_TCP_ADAPTER
   ],[auto])
 
 AC_ARG_ADAPTERS([
@@ -648,6 +652,7 @@ PROCESS_ADAPTERS([LIBFTDI_USB1_ADAPTERS], ["x$use_libftdi" = "xyes" -a "x$use_li
 PROCESS_ADAPTERS([LIBGPIOD_ADAPTERS], ["x$use_libgpiod" = "xyes"], [Linux libgpiod])
 PROCESS_ADAPTERS([SYSFSGPIO_ADAPTER], ["x$is_linux" = "xyes"], [Linux sysfs])
 PROCESS_ADAPTERS([REMOTE_BITBANG_ADAPTER], [true], [unused])
+PROCESS_ADAPTERS([CMSIS_DAP_TCP_ADAPTER], [true], [unused])
 PROCESS_ADAPTERS([LIBJAYLINK_ADAPTERS], ["x$use_internal_libjaylink" = "xyes" -o "x$use_libjaylink" = "xyes"], [libjaylink-0.2])
 PROCESS_ADAPTERS([PCIE_ADAPTERS], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_pci_h" = "xyes"], [Linux build])
 PROCESS_ADAPTERS([SERIAL_PORT_ADAPTERS], ["x$can_build_buspirate" = "xyes"],
@@ -854,6 +859,7 @@ m4_foreach([adapter], [USB1_ADAPTERS,
 	AMTJTAGACCEL_ADAPTER,
 	HOST_ARM_BITBANG_ADAPTERS,
 	HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS,
+	CMSIS_DAP_TCP_ADAPTER,
 	DUMMY_ADAPTER,
 	OPTIONAL_LIBRARIES,
 	COVERAGE],
diff --git a/src/helper/replacements.h b/src/helper/replacements.h
index ecc0e5e955..95322e96ac 100644
--- a/src/helper/replacements.h
+++ b/src/helper/replacements.h
@@ -225,6 +225,20 @@ static inline int socket_select(int max_fd,
 #endif
 }
 
+static inline int socket_timeout(int fd, unsigned long timeout_msec)
+{
+#ifdef _WIN32
+    DWORD timeout = timeout_msec;
+    return setsockopt(fd, SOL_SOCKET, SO_RCVTIMEO, (const char*)&timeout,
+            sizeof(timeout));
+#else
+    struct timeval tv;
+    tv.tv_sec = timeout_msec / 1000;
+    tv.tv_usec = (timeout_msec % 1000) * 1000;
+    return setsockopt(fd, SOL_SOCKET, SO_RCVTIMEO, (const char*)&tv, sizeof(tv));
+#endif
+}
+
 #ifndef HAVE_ELF_H
 
 typedef uint32_t Elf32_Addr;
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index b0dd8e3ad1..0942777145 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -198,6 +198,10 @@ if !CMSIS_DAP_HID
 DRIVERFILES += %D%/cmsis_dap.c
 endif
 endif
+if CMSIS_DAP_TCP
+DRIVERFILES += %D%/cmsis_dap_tcp.c
+DRIVERFILES += %D%/cmsis_dap.c
+endif
 if IMX_GPIO
 DRIVERFILES += %D%/imx_gpio.c
 endif
diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c
index 2bfcfcc2b0..7f8eabeb43 100644
--- a/src/jtag/drivers/cmsis_dap.c
+++ b/src/jtag/drivers/cmsis_dap.c
@@ -52,9 +52,16 @@ const struct cmsis_dap_backend cmsis_dap_hid_backend = {
 };
 #endif
 
+#if BUILD_CMSIS_DAP_TCP == 0
+const struct cmsis_dap_backend cmsis_dap_tcp_backend = {
+	.name = "tcp"
+};
+#endif
+
 static const struct cmsis_dap_backend *const cmsis_dap_backends[] = {
 	&cmsis_dap_usb_backend,
 	&cmsis_dap_hid_backend,
+	&cmsis_dap_tcp_backend,
 };
 
 /* USB Config */
@@ -2272,8 +2279,8 @@ static const struct command_registration cmsis_dap_subcommand_handlers[] = {
 		.name = "backend",
 		.handler = &cmsis_dap_handle_backend_command,
 		.mode = COMMAND_CONFIG,
-		.help = "set the communication backend to use (USB bulk or HID).",
-		.usage = "(auto | usb_bulk | hid)",
+		.help = "set the communication backend to use (USB bulk or HID, or TCP).",
+		.usage = "(auto | usb_bulk | hid | tcp)",
 	},
 	{
 		.name = "quirk",
@@ -2290,6 +2297,15 @@ static const struct command_registration cmsis_dap_subcommand_handlers[] = {
 		.help = "USB bulk backend-specific commands",
 		.usage = "<cmd>",
 	},
+#endif
+#if BUILD_CMSIS_DAP_TCP
+	{
+		.name = "tcp",
+		.chain = cmsis_dap_tcp_subcommand_handlers,
+		.mode = COMMAND_ANY,
+		.help = "TCP backend-specific commands",
+		.usage = "<cmd>",
+	},
 #endif
 	COMMAND_REGISTRATION_DONE
 };
diff --git a/src/jtag/drivers/cmsis_dap.h b/src/jtag/drivers/cmsis_dap.h
index aded0e54a3..1052bd3589 100644
--- a/src/jtag/drivers/cmsis_dap.h
+++ b/src/jtag/drivers/cmsis_dap.h
@@ -78,7 +78,9 @@ struct cmsis_dap_backend {
 
 extern const struct cmsis_dap_backend cmsis_dap_hid_backend;
 extern const struct cmsis_dap_backend cmsis_dap_usb_backend;
+extern const struct cmsis_dap_backend cmsis_dap_tcp_backend;
 extern const struct command_registration cmsis_dap_usb_subcommand_handlers[];
+extern const struct command_registration cmsis_dap_tcp_subcommand_handlers[];
 
 #define REPORT_ID_SIZE   1
 
diff --git a/src/jtag/drivers/cmsis_dap_tcp.c b/src/jtag/drivers/cmsis_dap_tcp.c
new file mode 100644
index 0000000000..b44df9a10e
--- /dev/null
+++ b/src/jtag/drivers/cmsis_dap_tcp.c
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/***************************************************************************
+ *   Provides CMSIS-DAP protocol over a TCP/IP socket.                     *
+ *   UART and SWO are currently unsupported.                               *
+ *                                                                         *
+ *   Copyright (C) 2025 by Brian Kuschak <bku...@gm...>              *
+ *                                                                         *
+ *   Adapted from cmsis_dap_usb_hid.c. Copyright (C) 2013-2018 by:         *
+ *     Mickaël Thomas <mic...@gm...>                                 *
+ *     Maksym Hilliaka <ot...@fr...>                              *
+ *     Phillip Pearson <pp...@my...>                                   *
+ *     Paul Fertser <fer...@gm...>                                  *
+ *     mike brown <mi...@th...>                               *
+ *     Spencer Oliver <sp...@sp...>                               *
+ *                                                                         *
+ *   Example usage:                                                        *
+ *     adapter driver cmsis-dap                                            *
+ *     cmsis-dap backend tcp                                               *
+ *     cmsis-dap tcp host 192.168.1.4                                      *
+ *     cmsis-dap tcp dap_port 4441                                         *
+ *     transport select swd                                                *
+ *     adapter speed 2000                                                  *
+ *                                                                         *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <hidapi.h>
+#include <netdb.h>
+#include <netinet/tcp.h>
+#include <stdbool.h>
+#include <string.h>
+#include <sys/socket.h>
+#include <sys/types.h>
+
+#include "helper/command.h"
+#include "helper/log.h"
+#include "helper/replacements.h"
+#include "helper/system.h"
+#include "cmsis_dap.h"
+
+#define STRINGIFY(x) #x
+
+// If the protocol changes in the future, the SIGNATURE should also be changed.
+#define DAP_PKT_HDR_SIGNATURE   0x00504144  // "DAP"
+#define DAP_PKT_TYPE_REQUEST    0x01
+#define DAP_PKT_TYPE_RESPONSE   0x02
+
+#define CMSIS_DAP_TCP_PORT      4441        // Default. Can be overridden.
+#define CMSIS_DAP_PACKET_SIZE   1024        // Max payload size not including
+                                            // header.
+
+// CMSIS-DAP requests are variable length. With CMSIS-DAP over USB, the
+// transfer sizes are preserved by the USB stack. However, TCP/IP is stream
+// oriented so we perform our own packetization to preserve the boundaries
+// between each request. This short header is prepended to each CMSIS-DAP
+// request and response before being sent over the socket. Little endian format
+// is used for multibyte values.
+struct cmsis_dap_tcp_packet_hdr {
+    uint32_t signature;     // "DAP"
+    uint16_t length;        // Not including header length.
+    uint8_t packet_type;
+    uint8_t reserved;       // Reserved for future use.
+};
+
+struct cmsis_dap_backend_data {
+    int sockfd;
+};
+
+static char *cmsis_dap_tcp_host;
+static char *cmsis_dap_tcp_dap_port = STRINGIFY(CMSIS_DAP_TCP_PORT);
+
+static void cmsis_dap_tcp_close(struct cmsis_dap *dap);
+static int cmsis_dap_tcp_alloc(struct cmsis_dap *dap, unsigned int pkt_sz);
+static void cmsis_dap_tcp_free(struct cmsis_dap *dap);
+
+static int cmsis_dap_tcp_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t
+        pids[], const char *serial)
+{
+    // Ignore vids, pids, serial. We use host and port subcommands instead.
+    (void)vids;
+    (void)pids;
+    (void)serial;
+
+    dap->bdata = malloc(sizeof(struct cmsis_dap_backend_data));
+    if (!dap->bdata) {
+        LOG_ERROR("CMSIS-DAP: unable to allocate memory");
+        return ERROR_FAIL;
+    }
+
+    struct addrinfo hints = {
+        .ai_family = AF_UNSPEC,
+        .ai_socktype = SOCK_STREAM
+    };
+    struct addrinfo *result, *rp;
+    int fd = 0;
+
+    LOG_INFO("CMSIS-DAP: Connecting to %s:%s using TCP backend",
+            cmsis_dap_tcp_host ? cmsis_dap_tcp_host : "localhost",
+            cmsis_dap_tcp_dap_port);
+
+    /* Some of the following code was taken from remote_bitbang.c */
+    /* Obtain address(es) matching host/port */
+    int s = getaddrinfo(cmsis_dap_tcp_host, cmsis_dap_tcp_dap_port, &hints,
+            &result);
+    if (s != 0) {
+        LOG_ERROR("CMSIS-DAP: getaddrinfo: %s\n", gai_strerror(s));
+        free(dap->bdata);
+        return ERROR_FAIL;
+    }
+
+    /* getaddrinfo() returns a list of address structures.
+     Try each address until we successfully connect(2).
+     If socket(2) (or connect(2)) fails, we (close the socket
+     and) try the next address. */
+
+    for (rp = result; rp ; rp = rp->ai_next) {
+        fd = socket(rp->ai_family, rp->ai_socktype, rp->ai_protocol);
+        if (fd == -1)
+            continue;
+
+        if (connect(fd, rp->ai_addr, rp->ai_addrlen) != -1) {
+            LOG_DEBUG("Connected.");
+            break; /* Success */
+        }
+
+        close(fd);
+    }
+
+    freeaddrinfo(result);
+
+    if (!rp) { /* No address succeeded */
+        LOG_ERROR("CMSIS-DAP: unable to connect to device %s:%s",
+            cmsis_dap_tcp_host ? cmsis_dap_tcp_host : "localhost",
+            cmsis_dap_tcp_dap_port);
+        log_socket_error("Failed to connect");
+        free(dap->bdata);
+        dap->bdata = NULL;
+        return ERROR_FAIL;
+    }
+
+    /* Set NODELAY to minimize latency. */
+    int one = 1;
+    /* On Windows optval has to be a const char *. */
+    setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (const char *)&one, sizeof(one));
+
+    dap->bdata->sockfd = fd;
+
+    int retval = cmsis_dap_tcp_alloc(dap, CMSIS_DAP_PACKET_SIZE);
+    if (retval != ERROR_OK) {
+        cmsis_dap_tcp_close(dap);
+        return ERROR_FAIL;
+    }
+    return ERROR_OK;
+}
+
+static void cmsis_dap_tcp_close(struct cmsis_dap *dap)
+{
+    if (close_socket(dap->bdata->sockfd) != 0) {
+        log_socket_error("close_socket");
+    }
+
+    if(dap->bdata)
+        free(dap->bdata);
+    dap->bdata = NULL;
+    cmsis_dap_tcp_free(dap);
+}
+
+static int cmsis_dap_tcp_read(struct cmsis_dap *dap, int transfer_timeout_ms,
+                              enum cmsis_dap_blocking blocking)
+{
+    int wait_ms = (blocking == CMSIS_DAP_NON_BLOCKING) ? 0 :
+        transfer_timeout_ms;
+    socket_timeout(dap->bdata->sockfd, wait_ms);
+
+    if(blocking == CMSIS_DAP_NON_BLOCKING)
+        socket_nonblock(dap->bdata->sockfd);
+    else
+        socket_block(dap->bdata->sockfd);
+
+    // Read the header first to find the length, then read the rest.
+    struct cmsis_dap_tcp_packet_hdr *header = (void*)dap->packet_buffer;
+    int retval = read_socket(dap->bdata->sockfd, dap->packet_buffer,
+            sizeof(*header));
+    LOG_DEBUG_IO("Reading header returned %d", retval);
+
+    if (retval == 0) {
+        return ERROR_TIMEOUT_REACHED;
+    } else if (retval == -1) {
+        if (errno == EAGAIN || errno == EWOULDBLOCK) {
+            return ERROR_TIMEOUT_REACHED;
+        } else {
+            LOG_ERROR("CMSIS-DAP: error reading header");
+            log_socket_error("read_socket");
+            return ERROR_FAIL;
+        }
+    } else if (retval != sizeof(*header)) {
+        log_socket_error("read_socket header short read");
+        return ERROR_FAIL;
+    }
+
+    header->signature = le_to_h_u32((void*)&header->signature);
+    header->length = le_to_h_u16((void*)&header->length);
+
+    if(header->signature != DAP_PKT_HDR_SIGNATURE) {
+        LOG_ERROR("CMSIS-DAP: Unrecognized packet signature 0x%08x",
+                header->signature);
+        return ERROR_FAIL;
+    } else if(header->packet_type != DAP_PKT_TYPE_RESPONSE) {
+        LOG_ERROR("CMSIS-DAP: Unrecognized packet type 0x%02x",
+                header->packet_type);
+        return ERROR_FAIL;
+    } else if(header->length + sizeof(*header) > dap->packet_buffer_size) {
+        LOG_ERROR("CMSIS-DAP: Packet length %d too large to fit.",
+                header->length);
+        return ERROR_FAIL;
+    }
+
+    LOG_DEBUG_IO("Reading %d bytes...", header->length);
+    retval = read_socket(dap->bdata->sockfd, dap->packet_buffer +
+            sizeof(*header), header->length);
+
+    if (retval == 0) {
+        return ERROR_TIMEOUT_REACHED;
+    } else if (retval == -1) {
+        LOG_ERROR("CMSIS-DAP: error reading data");
+        log_socket_error("read_socket");
+        return ERROR_FAIL;
+    } else if (retval != header->length) {
+        log_socket_error("read_socket short read");
+        return ERROR_FAIL;
+    }
+    return retval;
+}
+
+static int cmsis_dap_tcp_write(struct cmsis_dap *dap, int txlen, int
+        timeout_ms)
+{
+    (void) timeout_ms;
+
+    struct cmsis_dap_tcp_packet_hdr *header = (void*)dap->packet_buffer;
+    const unsigned int len = txlen + sizeof(*header);
+    if(len > dap->packet_buffer_size) {
+        LOG_ERROR("CMSIS-DAP: Packet length %d exceeds TCP buffer size!", len);
+        return ERROR_FAIL;
+    }
+
+    /* Set the header values. */
+    h_u32_to_le((void*)&header->signature, DAP_PKT_HDR_SIGNATURE);
+    h_u16_to_le((void*)&header->length, txlen);
+    header->packet_type = DAP_PKT_TYPE_REQUEST;
+    header->reserved = 0;
+
+    /* write data to device */
+    LOG_DEBUG_IO("Writing %d bytes", len);
+    int retval = write_socket(dap->bdata->sockfd, dap->packet_buffer, len);
+    if (retval < 0) {
+        log_socket_error("write_socket");
+        return ERROR_FAIL;
+    } else if (retval != (int)len) {
+        LOG_ERROR("CMSIS-DAP: error writing data");
+        log_socket_error("write_socket short write");
+        return ERROR_FAIL;
+    }
+    return retval;
+}
+
+static int cmsis_dap_tcp_alloc(struct cmsis_dap *dap, unsigned int pkt_sz)
+{
+    // Reserve space for the packet header.
+    struct cmsis_dap_tcp_packet_hdr header;
+    unsigned int packet_buffer_size = pkt_sz + sizeof(header);
+    uint8_t *buf = malloc(packet_buffer_size);
+    if (!buf) {
+        LOG_ERROR("CMSIS-DAP: unable to allocate CMSIS-DAP packet buffer");
+        return ERROR_FAIL;
+    }
+
+    dap->packet_buffer = buf;
+    dap->packet_size = pkt_sz;
+    dap->packet_usable_size = pkt_sz;
+    dap->packet_buffer_size = packet_buffer_size;
+
+    dap->command = dap->packet_buffer + sizeof(header);
+    dap->response = dap->packet_buffer + sizeof(header);
+    return ERROR_OK;
+}
+
+static void cmsis_dap_tcp_free(struct cmsis_dap *dap)
+{
+    free(dap->packet_buffer);
+    dap->packet_buffer = NULL;
+}
+
+static void cmsis_dap_tcp_cancel_all(struct cmsis_dap *dap)
+{
+}
+
+COMMAND_HANDLER(cmsis_dap_handle_tcp_dap_port)
+{
+    if (CMD_ARGC == 1)
+        cmsis_dap_tcp_dap_port = strdup(CMD_ARGV[0]);
+    else
+        LOG_ERROR("CMSIS-DAP: expected exactly one argument to "
+                "cmsis-dap tcp dap_port <port_number>");
+
+    return ERROR_OK;
+}
+
+COMMAND_HANDLER(cmsis_dap_handle_tcp_host)
+{
+    if (CMD_ARGC == 1)
+        cmsis_dap_tcp_host = strdup(CMD_ARGV[0]);
+    else
+        LOG_ERROR("CMSIS-DAP: expected exactly one argument to "
+                "cmsis-dap tcp host <host_name>");
+
+    return ERROR_OK;
+}
+
+const struct command_registration cmsis_dap_tcp_subcommand_handlers[] = {
+    {
+        .name = "host",
+        .handler = &cmsis_dap_handle_tcp_host,
+        .mode = COMMAND_CONFIG,
+        .help = "set the host name to use (for TCP backend only)",
+        .usage = "<host_name>",
+    },
+    {
+        .name = "dap_port",
+        .handler = &cmsis_dap_handle_tcp_dap_port,
+        .mode = COMMAND_CONFIG,
+        .help = "set the port number to use for DAP (for TCP backend only)",
+        .usage = "<port_number>",
+    },
+    COMMAND_REGISTRATION_DONE
+};
+
+const struct cmsis_dap_backend cmsis_dap_tcp_backend = {
+    .name = "tcp",
+    .open = cmsis_dap_tcp_open,
+    .close = cmsis_dap_tcp_close,
+    .read = cmsis_dap_tcp_read,
+    .write = cmsis_dap_tcp_write,
+    .packet_buffer_alloc = cmsis_dap_tcp_alloc,
+    .packet_buffer_free = cmsis_dap_tcp_free,
+    .cancel_all = cmsis_dap_tcp_cancel_all,
+};
diff --git a/tcl/interface/cmsis-dap-tcp.cfg b/tcl/interface/cmsis-dap-tcp.cfg
new file mode 100644
index 0000000000..ddd9971c19
--- /dev/null
+++ b/tcl/interface/cmsis-dap-tcp.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# cmsis-dap-tcp - CMSIS-DAP protocol over TCP/IP.
+#
+# Change the host and dap_port parameters to match your programmer.
+#
+
+adapter driver cmsis-dap
+cmsis-dap backend tcp
+cmsis-dap tcp host 192.168.1.4
+cmsis-dap tcp dap_port 4441

-- 

[PATCH]: b666a44c73 configure.ac: rename M4 macro 'adapter' to prevent accidental conflicts

[<ge...@op...>]

This is an automated email from Gerrit.

"R. Diez <rdi...@rd...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8972

-- gerrit

commit b666a44c73527731cd6620a0df524971b34e0ed2
Author: R. Diez <rdi...@rd...>
Date:   Sat Jun 21 22:05:17 2025 +0200

    configure.ac: rename M4 macro 'adapter' to prevent accidental conflicts
    
    Also remove a comment about such a conflict which had been already noticed.
    
    Change-Id: I6f301ccbd1261ea1c15c44a02d3f34f0cf5cb9f4
    Signed-off-by: R. Diez <rdi...@rd...>

diff --git a/configure.ac b/configure.ac
index 4b94716299..5a05f3171c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -206,8 +206,6 @@ m4_define([HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS],
 	[[imx_gpio], [Bitbanging on NXP IMX processors], [IMX_GPIO]],
 	[[am335xgpio], [Bitbanging on AM335x (as found in Beaglebones)], [AM335XGPIO]]])
 
-# The word 'Adapter' in "Dummy Adapter" below must begin with a capital letter
-# because there is an M4 macro called 'adapter'.
 m4_define([DUMMY_ADAPTER],
 	[[[dummy], [Dummy Adapter], [DUMMY]]])
 
@@ -309,15 +307,15 @@ AC_ARG_ENABLE([dmem],
   [build_dmem=$enableval], [build_dmem=no])
 
 m4_define([AC_ARG_ADAPTERS], [
-  m4_foreach([adapter], [$1],
-	[AC_ARG_ENABLE(ADAPTER_OPT([adapter]),
-		AS_HELP_STRING([--enable-ADAPTER_OPT([adapter])[[[=yes/no/auto]]]],
-			[Enable building support for the ]ADAPTER_DESC([adapter])[ (default is $2)]),
+  m4_foreach([adapterTuple], [$1],
+	[AC_ARG_ENABLE(ADAPTER_OPT([adapterTuple]),
+		AS_HELP_STRING([--enable-ADAPTER_OPT([adapterTuple])[[[=yes/no/auto]]]],
+			[Enable building support for the ]ADAPTER_DESC([adapterTuple])[ (default is $2)]),
 		[case "${enableval}" in
 			yes|no|auto) ;;
-			*) AC_MSG_ERROR([Option --enable-ADAPTER_OPT([adapter]) has invalid value "${enableval}".]) ;;
+			*) AC_MSG_ERROR([Option --enable-ADAPTER_OPT([adapterTuple]) has invalid value "${enableval}".]) ;;
 			esac],
-		[ADAPTER_VAR([adapter])=$2])
+		[ADAPTER_VAR([adapterTuple])=$2])
   ])
 ])
 
@@ -622,21 +620,23 @@ PKG_CHECK_MODULES([LIBJAYLINK], [libjaylink >= 0.2],
 # Arg $3: What prerequisites are missing, to be shown in an error message
 #         if an adapter was requested but cannot be enabled.
 m4_define([PROCESS_ADAPTERS], [
-  m4_foreach([adapter], [$1], [
+  m4_foreach([adapterTuple], [$1], [
 	AS_IF([test $2], [
-		AS_IF([test "x$ADAPTER_VAR([adapter])" != "xno"], [
-			AC_DEFINE([BUILD_]ADAPTER_SYM([adapter]), [1], [1 if you want the ]ADAPTER_DESC([adapter]).)
+		AS_IF([test "x$ADAPTER_VAR([adapterTuple])" != "xno"], [
+			AC_DEFINE([BUILD_]ADAPTER_SYM([adapterTuple]), [1],
+			          [1 if you want the ]ADAPTER_DESC([adapterTuple]).)
 		], [
-			AC_DEFINE([BUILD_]ADAPTER_SYM([adapter]), [0], [0 if you do not want the ]ADAPTER_DESC([adapter]).)
+			AC_DEFINE([BUILD_]ADAPTER_SYM([adapterTuple]), [0],
+			          [0 if you do not want the ]ADAPTER_DESC([adapterTuple]).)
 		])
 	], [
-		AS_IF([test "x$ADAPTER_VAR([adapter])" = "xyes"], [
-			AC_MSG_ERROR([$3 is required for [adapter] "ADAPTER_DESC([adapter])".])
+		AS_IF([test "x$ADAPTER_VAR([adapterTuple])" = "xyes"], [
+			AC_MSG_ERROR([$3 is required for [adapterTuple] "ADAPTER_DESC([adapterTuple])".])
 		])
-		ADAPTER_VAR([adapter])=no
-		AC_DEFINE([BUILD_]ADAPTER_SYM([adapter]), [0], [0 if you do not want the ]ADAPTER_DESC([adapter]).)
+		ADAPTER_VAR([adapterTuple])=no
+		AC_DEFINE([BUILD_]ADAPTER_SYM([adapterTuple]), [0], [0 if you do not want the ]ADAPTER_DESC([adapterTuple]).)
 	])
-	AM_CONDITIONAL(ADAPTER_SYM([adapter]), [test "x$ADAPTER_VAR([adapter])" != "xno"])
+	AM_CONDITIONAL(ADAPTER_SYM([adapterTuple]), [test "x$ADAPTER_VAR([adapterTuple])" != "xno"])
   ])
 ])
 
@@ -839,7 +839,7 @@ echo
 echo
 echo OpenOCD configuration summary
 echo ---------------------------------------------------
-m4_foreach([adapter], [USB1_ADAPTERS,
+m4_foreach([adapterTuple], [USB1_ADAPTERS,
 	HIDAPI_ADAPTERS, HIDAPI_USB1_ADAPTERS, LIBFTDI_ADAPTERS,
 	LIBFTDI_USB1_ADAPTERS,
 	LIBGPIOD_ADAPTERS,
@@ -857,8 +857,8 @@ m4_foreach([adapter], [USB1_ADAPTERS,
 	DUMMY_ADAPTER,
 	OPTIONAL_LIBRARIES,
 	COVERAGE],
-	[s=m4_format(["%-49s"], ADAPTER_DESC([adapter]))
-	AS_CASE([$ADAPTER_VAR([adapter])],
+	[s=m4_format(["%-49s"], ADAPTER_DESC([adapterTuple]))
+	AS_CASE([$ADAPTER_VAR([adapterTuple])],
 		[auto], [
 			echo "$s"yes '(auto)'
 		],
@@ -870,8 +870,8 @@ m4_foreach([adapter], [USB1_ADAPTERS,
 		],
 		[
 			AC_MSG_ERROR(m4_normalize([
-				Error in [adapter] "ADAPTER_ARG([adapter])": Variable "ADAPTER_VAR([adapter])"
-				has invalid value "$ADAPTER_VAR([adapter])".]))
+				Error in [adapterTuple] "ADAPTER_ARG([adapterTuple])": Variable "ADAPTER_VAR([adapterTuple])"
+				has invalid value "$ADAPTER_VAR([adapterTuple])".]))
 	])
 ])
 echo

-- 

[PATCH]: ee2055fa23 configure.ac: show the dmem adapter in the config summary

[<ge...@op...>]

This is an automated email from Gerrit.

"R. Diez <rdi...@rd...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8971

-- gerrit

commit ee2055fa23a972151dc4d18316a3adaa704f33a4
Author: R. Diez <rdi...@rd...>
Date:   Sat Jun 21 21:41:38 2025 +0200

    configure.ac: show the dmem adapter in the config summary
    
    Also enable this adapter by default (auto).
    
    Change-Id: I61597c8572115f838ab0c92021163436eb7b0d59
    Signed-off-by: R. Diez <rdi...@rd...>

diff --git a/configure.ac b/configure.ac
index 4b94716299..e995246a1d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -165,6 +165,9 @@ m4_define([LIBFTDI_USB1_ADAPTERS],
 m4_define([LIBGPIOD_ADAPTERS],
 	[[[linuxgpiod], [Linux GPIO bitbang through libgpiod], [LINUXGPIOD]]])
 
+m4_define([DMEM_ADAPTER],
+	[[[dmem], [CoreSight Direct Memory], [DMEM]]])
+
 m4_define([SYSFSGPIO_ADAPTER],
 	[[[sysfsgpio], [Linux GPIO bitbang through sysfs], [SYSFSGPIO]]])
 
@@ -304,10 +307,6 @@ AS_IF([test "x$debug_malloc" = "xyes" -a "x$have_glibc" = "xyes"], [
   AC_DEFINE([_DEBUG_FREE_SPACE_],[1], [Include malloc free space in logging])
 ])
 
-AC_ARG_ENABLE([dmem],
-  AS_HELP_STRING([--enable-dmem], [Enable building the dmem driver]),
-  [build_dmem=$enableval], [build_dmem=no])
-
 m4_define([AC_ARG_ADAPTERS], [
   m4_foreach([adapter], [$1],
 	[AC_ARG_ENABLE(ADAPTER_OPT([adapter]),
@@ -328,6 +327,7 @@ AC_ARG_ADAPTERS([
   LIBFTDI_ADAPTERS,
   LIBFTDI_USB1_ADAPTERS,
   LIBGPIOD_ADAPTERS,
+  DMEM_ADAPTER,
   SYSFSGPIO_ADAPTER,
   REMOTE_BITBANG_ADAPTER,
   LINUXSPIDEV_ADAPTER,
@@ -505,12 +505,6 @@ AS_IF([test "x$build_parport" = "xyes"], [
   AC_DEFINE([BUILD_PARPORT], [0], [0 if you don't want parport.])
 ])
 
-AS_IF([test "x$build_dmem" = "xyes"], [
-  AC_DEFINE([BUILD_DMEM], [1], [1 if you want to debug via Direct Mem.])
-], [
-  AC_DEFINE([BUILD_DMEM], [0], [0 if you don't want to debug via Direct Mem.])
-])
-
 AS_IF([test "x$ADAPTER_VAR([dummy])" != "xno"], [
   build_bitbang=yes
 ])
@@ -646,6 +640,7 @@ PROCESS_ADAPTERS([HIDAPI_USB1_ADAPTERS], ["x$use_hidapi" = "xyes" -a "x$use_libu
 PROCESS_ADAPTERS([LIBFTDI_ADAPTERS], ["x$use_libftdi" = "xyes"], [libftdi])
 PROCESS_ADAPTERS([LIBFTDI_USB1_ADAPTERS], ["x$use_libftdi" = "xyes" -a "x$use_libusb1" = "xyes"], [libftdi and libusb-1.x])
 PROCESS_ADAPTERS([LIBGPIOD_ADAPTERS], ["x$use_libgpiod" = "xyes"], [Linux libgpiod])
+PROCESS_ADAPTERS([DMEM_ADAPTER], ["x$is_linux" = "xyes"], [Linux /dev/mem])
 PROCESS_ADAPTERS([SYSFSGPIO_ADAPTER], ["x$is_linux" = "xyes"], [Linux sysfs])
 PROCESS_ADAPTERS([REMOTE_BITBANG_ADAPTER], [true], [unused])
 PROCESS_ADAPTERS([LIBJAYLINK_ADAPTERS], ["x$use_internal_libjaylink" = "xyes" -o "x$use_libjaylink" = "xyes"], [libjaylink-0.2])
@@ -744,7 +739,6 @@ AM_CONDITIONAL([USE_LIBFTDI], [test "x$use_libftdi" = "xyes"])
 AM_CONDITIONAL([USE_LIBGPIOD], [test "x$use_libgpiod" = "xyes"])
 AM_CONDITIONAL([USE_HIDAPI], [test "x$use_hidapi" = "xyes"])
 AM_CONDITIONAL([USE_LIBJAYLINK], [test "x$use_libjaylink" = "xyes"])
-AM_CONDITIONAL([DMEM], [test "x$build_dmem" = "xyes"])
 AM_CONDITIONAL([HAVE_CAPSTONE], [test "x$enable_capstone" != "xno"])
 
 AM_CONDITIONAL([INTERNAL_JIMTCL], [test "x$use_internal_jimtcl" = "xyes"])
@@ -843,6 +837,7 @@ m4_foreach([adapter], [USB1_ADAPTERS,
 	HIDAPI_ADAPTERS, HIDAPI_USB1_ADAPTERS, LIBFTDI_ADAPTERS,
 	LIBFTDI_USB1_ADAPTERS,
 	LIBGPIOD_ADAPTERS,
+	DMEM_ADAPTER,
 	SYSFSGPIO_ADAPTER,
 	REMOTE_BITBANG_ADAPTER,
 	LIBJAYLINK_ADAPTERS, PCIE_ADAPTERS, SERIAL_PORT_ADAPTERS,

-- 

[PATCH]: 439c3caf6d helper: types: fix proper return type in example of ARRAY_SIZE()

[<ge...@op...>]

This is an automated email from Gerrit.

"Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8970

-- gerrit

commit 439c3caf6d798661aa77b0f9cdd0631696528479
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 21 12:11:24 2025 +0200

    helper: types: fix proper return type in example of ARRAY_SIZE()
    
    The example in the comment above the declaration of the macro
    ARRAY_SIZE() assigns the value to a variable of type 'unsigned'
    that is not allowed by the coding style (should be 'unsigned int')
    and is not correct since the macro uses 'sizeof()' and the type
    returned is 'size_t'.
    
    Fix the comment.
    
    Change-Id: I18c32b5328a229ab74b56dafab46a064ce5d23c5
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/src/helper/types.h b/src/helper/types.h
index 53249e5b79..b3edd21184 100644
--- a/src/helper/types.h
+++ b/src/helper/types.h
@@ -51,7 +51,7 @@
  * Compute the number of elements of a variable length array.
  * <code>
  * const char *strs[] = { "a", "b", "c" };
- * unsigned num_strs = ARRAY_SIZE(strs);
+ * size_t num_strs = ARRAY_SIZE(strs);
  * </code>
  */
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))

-- 

[PATCH]: 798470fe30 tcl/board: Add config for TMS570LS12x development kit

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8969

-- gerrit

commit 798470fe30a42456ad2d1526d8730dbb2dc091a8
Author: Marc Schink <de...@za...>
Date:   Fri Jun 20 11:18:03 2025 +0200

    tcl/board: Add config for TMS570LS12x development kit
    
    Tested on the corresponding hardware.
    
    Change-Id: Ic98141c450bb981cc7853c93b38195c7930bc7d3
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/tcl/board/ti/launchxl2-tms57012.cfg b/tcl/board/ti/launchxl2-tms57012.cfg
new file mode 100644
index 0000000000..99cb26e204
--- /dev/null
+++ b/tcl/board/ti/launchxl2-tms57012.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Hercules TMS570LS12x LaunchPad Development Kit
+# https://www.ti.com/tool/LAUNCHXL2-TMS57012
+
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+source [find target/ti_tms570ls1x.cfg]

--