openocd-devel — Discuss development of OpenOCD

[PATCH]: 6781417eb9 target/arvm7a: Use 'bool' data type where appropriate

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9008

-- gerrit

commit 6781417eb98d76a4e67339c94f62029409b67e18
Author: Marc Schink <de...@za...>
Date:   Mon Jul 21 06:52:24 2025 +0000

    target/arvm7a:  Use 'bool' data type where appropriate
    
    The variables are already used as boolean value but have the wrong
    data type.
    
    Change-Id: I0f169cac83f6c4094e8d1acb2cb8f1017a96a5d8
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index c5829095e5..9cde67788f 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -139,7 +139,7 @@ int armv7a_read_ttbcr(struct target *target)
 
 	ttbcr_n = ttbcr & 0x7;
 	armv7a->armv7a_mmu.ttbcr = ttbcr;
-	armv7a->armv7a_mmu.cached = 1;
+	armv7a->armv7a_mmu.cached = true;
 
 	for (ttbidx = 0; ttbidx < 2; ttbidx++) {
 		/*  MRC p15,0,<Rt>,c2,c0,ttbidx */
@@ -158,7 +158,7 @@ int armv7a_read_ttbcr(struct target *target)
 	armv7a->armv7a_mmu.ttbr_range[1] = 0xffffffff;
 	armv7a->armv7a_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n);
 	armv7a->armv7a_mmu.ttbr_mask[1] = 0xffffffff << 14;
-	armv7a->armv7a_mmu.cached = 1;
+	armv7a->armv7a_mmu.cached = true;
 
 	retval = armv7a_read_midr(target);
 	if (retval != ERROR_OK)
@@ -187,7 +187,7 @@ int armv7a_handle_cache_info_command(struct command_invocation *cmd,
 
 	int cl;
 
-	if (armv7a_cache->info == -1) {
+	if (!armv7a_cache->info_valid) {
 		command_print(cmd, "cache not yet identified");
 		return ERROR_OK;
 	}
@@ -427,7 +427,7 @@ int armv7a_identify_cache(struct target *target)
 			armv7a_cache_flush_all_data;
 	}
 
-	armv7a->armv7a_mmu.armv7a_cache.info = 1;
+	armv7a->armv7a_mmu.armv7a_cache.info_valid = true;
 done:
 	dpm->finish(dpm);
 	armv7a_read_mpidr(target);
@@ -473,7 +473,7 @@ int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
 	armv7a->arm.target = target;
 	armv7a->arm.common_magic = ARM_COMMON_MAGIC;
 	armv7a->common_magic = ARMV7_COMMON_MAGIC;
-	armv7a->armv7a_mmu.armv7a_cache.info = -1;
+	armv7a->armv7a_mmu.armv7a_cache.info_valid = false;
 	armv7a->armv7a_mmu.armv7a_cache.outer_cache = NULL;
 	armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = NULL;
 	return ERROR_OK;
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 0c5e0f90f6..ae2ccbe2a6 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -58,7 +58,7 @@ struct armv7a_arch_cache {
 
 /* common cache information */
 struct armv7a_cache_common {
-	int info;				/* -1 invalid, else valid */
+	bool info_valid;
 	int loc;				/* level of coherency */
 	uint32_t dminline;			/* minimum d-cache linelen */
 	uint32_t iminline;			/* minimum i-cache linelen */
@@ -72,7 +72,7 @@ struct armv7a_cache_common {
 
 struct armv7a_mmu_common {
 	/* following field mmu working way */
-	int32_t cached;     /* 0: not initialized, 1: initialized */
+	bool cached;
 	uint32_t ttbcr;     /* cache for ttbcr register */
 	uint32_t ttbr[2];
 	uint32_t ttbr_mask[2];
diff --git a/src/target/armv7a_cache_l2x.c b/src/target/armv7a_cache_l2x.c
index bc60e6d193..bdcf8cbbee 100644
--- a/src/target/armv7a_cache_l2x.c
+++ b/src/target/armv7a_cache_l2x.c
@@ -168,7 +168,7 @@ static int arm7a_handle_l2x_cache_info_command(struct command_invocation *cmd,
 {
 	struct armv7a_l2x_cache *l2x_cache = armv7a_cache->outer_cache;
 
-	if (armv7a_cache->info == -1) {
+	if (!armv7a_cache->info_valid) {
 		command_print(cmd, "cache not yet identified");
 		return ERROR_OK;
 	}
diff --git a/src/target/armv7a_mmu.c b/src/target/armv7a_mmu.c
index 43b5dae8ef..ee1592ae80 100644
--- a/src/target/armv7a_mmu.c
+++ b/src/target/armv7a_mmu.c
@@ -214,7 +214,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
 			max_pt_idx -= 1;
 		}
 	} else {
-		if (mmu->cached != 1) {
+		if (!mmu->cached) {
 			LOG_ERROR("TTB not cached!");
 			return ERROR_FAIL;
 		}
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 69bc0920b3..9e1aa44168 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1118,7 +1118,7 @@ static int cortex_a_post_debug_entry(struct target *target)
 	if (!armv7a->is_armv7r)
 		armv7a_read_ttbcr(target);
 
-	if (armv7a->armv7a_mmu.armv7a_cache.info == -1)
+	if (!armv7a->armv7a_mmu.armv7a_cache.info_valid)
 		armv7a_identify_cache(target);
 
 	if (armv7a->is_armv7r) {

-- 

[PATCH]: 53d3f6419f configure.ac: Replace $build_dmem with $enable_dmem

[<ge...@op...>]

This is an automated email from Gerrit.

"R. Diez <rdi...@rd...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9005

-- gerrit

commit 53d3f6419f171f4089b05938c7d8aacd7e44a91d
Author: R. Diez <rdi...@rd...>
Date:   Sun Jul 20 16:31:52 2025 +0200

    configure.ac: Replace $build_dmem with $enable_dmem
    
    dmem uses now the standard option-handling logic,
    which defines $enable_xxx instead of $build_xxx.
    
    Change-Id: I810cf09241089b1dfbec0e2183e64f20050868be
    Signed-off-by: R. Diez <rdi...@rd...>

diff --git a/configure.ac b/configure.ac
index 453cbcfb5a..cc090e0370 100644
--- a/configure.ac
+++ b/configure.ac
@@ -388,7 +388,7 @@ AS_CASE([$host_os],
       ])
     ])
 
-    AS_IF([test "x$build_dmem" = "xyes"], [
+    AS_IF([test "x$enable_dmem" != "xno"], [
       AC_MSG_ERROR([dmem is only available on linux])
     ])
 ])

-- 

[PATCH]: d241863384 configure.ac: Turn parpoart-ppdev/-giveio warnings into errors.

[<ge...@op...>]

This is an automated email from Gerrit.

"R. Diez <rdi...@rd...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9004

-- gerrit

commit d241863384afc85927505fa28a31506e55dd7522
Author: R. Diez <rdi...@rd...>
Date:   Sun Jul 20 12:12:36 2025 +0200

    configure.ac: Turn parpoart-ppdev/-giveio warnings into errors.
    
    Otherwise, it is easy to miss configuration errors.
    
    Change-Id: I889d2c1cc0150f4d7f178daf4509f7943ebfd4de
    Signed-off-by: R. Diez <rdi...@rd...>

diff --git a/configure.ac b/configure.ac
index 7ce412f57c..a1b18f4bc1 100644
--- a/configure.ac
+++ b/configure.ac
@@ -410,9 +410,8 @@ AS_CASE(["${host_cpu}"],
   [i?86|x86*], [],
   [
     AS_IF([test "x$parport_use_ppdev" = "xno"], [
-      AC_MSG_WARN([--disable-parport-ppdev is not supported by the host CPU])
+      AC_MSG_ERROR([--disable-parport-ppdev is not supported by the host CPU])
     ])
-    parport_use_ppdev=yes
 ])
 
 can_build_buspirate=yes
@@ -426,9 +425,8 @@ AS_CASE([$host_os],
       [is_mingw=yes],[is_mingw=no])
     AS_IF([test "x$is_mingw" = "xyes"], [
       AS_IF([test "x$parport_use_giveio" = "xno"], [
-        AC_MSG_WARN([--disable-parport-giveio is not supported by MinGW32 hosts])
+        AC_MSG_ERROR([--disable-parport-giveio is not supported by MinGW32 hosts])
       ])
-      parport_use_giveio=yes
       is_cygwin=no
     ], [
       is_cygwin=yes
@@ -444,9 +442,8 @@ AS_CASE([$host_os],
     parport_use_ppdev=no
 
     AS_IF([test "x$parport_use_giveio" = "xno"], [
-      AC_MSG_WARN([--disable-parport-giveio is not supported by MinGW32 hosts])
+      AC_MSG_ERROR([--disable-parport-giveio is not supported by MinGW32 hosts])
     ])
-    parport_use_giveio=yes
 
     AS_IF([test "x$ADAPTER_VAR([buspirate])" = "xyes"], [
       AC_MSG_ERROR([The Bus Pirate adapter is currently not supported by MinGW32 hosts.])
@@ -461,15 +458,13 @@ AS_CASE([$host_os],
     is_darwin=yes
 
     AS_IF([test "x$parport_use_giveio" = "xyes"], [
-      AC_MSG_WARN([--enable-parport-giveio cannot be used by Darwin hosts])
+      AC_MSG_ERROR([--enable-parport-giveio cannot be used by Darwin hosts])
     ])
-    parport_use_giveio=no
   ],
   [
     AS_IF([test "x$parport_use_giveio" = "xyes"], [
-      AC_MSG_WARN([--enable-parport-giveio cannot be used by ]$host[ hosts])
+      AC_MSG_ERROR([--enable-parport-giveio cannot be used by ]$host[ hosts])
     ])
-    parport_use_giveio=no
 ])
 
 AS_IF([test "x$is_cygwin" = "xyes"], [

-- 

[PATCH]: dd01f05287 configure.ac: show the parallel port adapter in the config summary

[<ge...@op...>]

This is an automated email from Gerrit.

"R. Diez <rdi...@rd...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9003

-- gerrit

commit dd01f05287ddcd9f680b38d1b5ee568ed2d19064
Author: R. Diez <rdi...@rd...>
Date:   Sun Jul 20 11:18:35 2025 +0200

    configure.ac: show the parallel port adapter in the config summary
    
    Use the same processing logic as most other enable/disable options.
    
    Change-Id: I994963fdab32a09c191f2e29620c9540136f980c
    Signed-off-by: R. Diez <rdi...@rd...>

diff --git a/configure.ac b/configure.ac
index 453cbcfb5a..7ce412f57c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -183,6 +183,9 @@ m4_define([PCIE_ADAPTERS],
 m4_define([SERIAL_PORT_ADAPTERS],
 	[[[buspirate], [Bus Pirate], [BUS_PIRATE]]])
 
+m4_define([PARALLEL_PORT_ADAPTER],
+	[[[parport], [PC Parallel Port], [PARPORT]]])
+
 m4_define([LINUXSPIDEV_ADAPTER],
 	[[[linuxspidev], [Linux spidev driver], [LINUXSPIDEV]]])
 m4_define([VDEBUG_ADAPTER],
@@ -330,6 +333,7 @@ AC_ARG_ADAPTERS([
   REMOTE_BITBANG_ADAPTER,
   LINUXSPIDEV_ADAPTER,
   SERIAL_PORT_ADAPTERS,
+  PARALLEL_PORT_ADAPTER,
   DUMMY_ADAPTER,
   VDEBUG_ADAPTER,
   JTAG_DPI_ADAPTER,
@@ -353,10 +357,6 @@ AC_ARG_ADAPTERS([
 AC_ARG_ADAPTERS([HOST_ARM_BITBANG_ADAPTERS],[no])
 AC_ARG_ADAPTERS([HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS],[no])
 
-AC_ARG_ENABLE([parport],
-  AS_HELP_STRING([--enable-parport], [Enable building the pc parallel port driver]),
-  [build_parport=$enableval], [build_parport=no])
-
 AC_ARG_ENABLE([parport_ppdev],
   AS_HELP_STRING([--disable-parport-ppdev],
       [Disable use of ppdev (/dev/parportN) for parport (for x86 only)]),
@@ -496,13 +496,6 @@ AS_IF([test "x$is_darwin" = "xyes"], [
     AC_DEFINE([IS_DARWIN], [0], [0 if not building for Darwin.])
 ])
 
-AS_IF([test "x$build_parport" = "xyes"], [
-  build_bitbang=yes
-  AC_DEFINE([BUILD_PARPORT], [1], [1 if you want parport.])
-], [
-  AC_DEFINE([BUILD_PARPORT], [0], [0 if you don't want parport.])
-])
-
 AS_IF([test "x$ADAPTER_VAR([dummy])" != "xno"], [
   build_bitbang=yes
 ])
@@ -647,6 +640,7 @@ PROCESS_ADAPTERS([LIBJAYLINK_ADAPTERS], ["x$use_internal_libjaylink" = "xyes" -o
 PROCESS_ADAPTERS([PCIE_ADAPTERS], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_pci_h" = "xyes"], [Linux build])
 PROCESS_ADAPTERS([SERIAL_PORT_ADAPTERS], ["x$can_build_buspirate" = "xyes"],
                                          [internal error: validation should happen beforehand])
+PROCESS_ADAPTERS([PARALLEL_PORT_ADAPTER], [true], [unused])
 PROCESS_ADAPTERS([LINUXSPIDEV_ADAPTER], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_spi_spidev_h" = "xyes"],
                                         [Linux spidev])
 PROCESS_ADAPTERS([VDEBUG_ADAPTER], [true], [unused])
@@ -724,7 +718,6 @@ AS_IF([test "x$enable_esp_usb_jtag" != "xno"], [
 ])
 
 AM_CONDITIONAL([RELEASE], [test "x$build_release" = "xyes"])
-AM_CONDITIONAL([PARPORT], [test "x$build_parport" = "xyes"])
 AM_CONDITIONAL([GIVEIO], [test "x$parport_use_giveio" = "xyes"])
 AM_CONDITIONAL([BITBANG], [test "x$build_bitbang" = "xyes"])
 AM_CONDITIONAL([USB_BLASTER_DRIVER], [test "x$enable_usb_blaster" != "xno" -o "x$enable_usb_blaster_2" != "xno"])
@@ -841,6 +834,7 @@ m4_foreach([adapterTuple], [USB1_ADAPTERS,
 	SYSFSGPIO_ADAPTER,
 	REMOTE_BITBANG_ADAPTER,
 	LIBJAYLINK_ADAPTERS, PCIE_ADAPTERS, SERIAL_PORT_ADAPTERS,
+	PARALLEL_PORT_ADAPTER,
 	LINUXSPIDEV_ADAPTER,
 	VDEBUG_ADAPTER,
 	JTAG_DPI_ADAPTER,

-- 

[PATCH]: 304f475773 configure.ac: Remove useless --enable-verbose-usb-io

[<ge...@op...>]

This is an automated email from Gerrit.

"R. Diez <rdi...@rd...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9002

-- gerrit

commit 304f475773cba241daaf6c44a54658a11c471495
Author: R. Diez <rdi...@rd...>
Date:   Sun Jul 20 10:39:02 2025 +0200

    configure.ac: Remove useless --enable-verbose-usb-io
    
    _DEBUG_USB_IO_ was not actually used anywhere.
    
    Change-Id: I1a98db7c7b03a89cc9347c0a66ec2106d2168c3f
    Signed-off-by: R. Diez <rdi...@rd...>

diff --git a/configure.ac b/configure.ac
index 453cbcfb5a..1f80e5793b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -259,34 +259,21 @@ AS_IF([test "x$enable_gcov" = "xyes"], [
   AC_DEFINE([USE_GCOV], [0], [0 to leave coverage collection disabled.])
 ])
 
-# set default verbose options, overridden by following options
-debug_usb_io=no
+# set default for debug_usb_comms, overridden by following options
 debug_usb_comms=no
 
 AC_ARG_ENABLE([verbose],
   AS_HELP_STRING([--enable-verbose],
       [Enable verbose JTAG I/O messages (for debugging).]),
   [
-  debug_usb_io=$enableval
   debug_usb_comms=$enableval
   ], [])
 
-AC_ARG_ENABLE([verbose_usb_io],
-  AS_HELP_STRING([--enable-verbose-usb-io],
-      [Enable verbose USB I/O messages (for debugging)]),
-  [debug_usb_io=$enableval], [])
-
 AC_ARG_ENABLE([verbose_usb_comms],
   AS_HELP_STRING([--enable-verbose-usb-comms],
       [Enable verbose USB communication messages (for debugging)]),
   [debug_usb_comms=$enableval], [])
 
-AC_MSG_CHECKING([whether to enable verbose USB I/O messages]);
-AC_MSG_RESULT([$debug_usb_io])
-AS_IF([test "x$debug_usb_io" = "xyes"], [
-  AC_DEFINE([_DEBUG_USB_IO_],[1], [Print verbose USB I/O messages])
-])
-
 AC_MSG_CHECKING([whether to enable verbose USB communication messages]);
 AC_MSG_RESULT([$debug_usb_comms])
 AS_IF([test "x$debug_usb_comms" = "xyes"], [

-- 

Re: Proposal: Improve Semihosting EXIT Behavior

[Liviu I. <il...@li...>]

> On 14 Jul 2025, at 13:02, Marek Vrbka <mar...@co...> wrote:
> 
> Hello all,
> I'd like to propose improvements to OpenOCD's semihosting behavior for the SYS_EXIT and SYS_EXIT_EXTENDED syscalls.
> Currently, if GDB is not connected and the target calls `SYS_EXIT` or `SYS_EXIT_EXTENDED` (with the appropriate parameter):
>     • If GDB is not connected - OpenOCD calls `exit(code)` immediately, without any cleanup. I believe this should be fixed - OpenOCD should go trough the standard shutdown sequence.
>     • If GDB is connected - message is printed and target is either halted or resumed depending on `arm semihosting_resexit`.
> I would like to make these improvements:
> 1. Avoid the direct call to `exit()`
> 2. Introduce a new command: `arm semihosting_exit_behavior`
> The options would be:
>     • `always_halt`
>     • `always_exit`
>     • `exit_if_no_gdb`
> 3. Introduce commands to get the program exit code in Tcl scripts:
>     • `arm semihosting_has_program_exited` - would return true if the semihosting exit already happened
>     • `arm semihosting_exit_code` - returns exit code (from `SYS_EXIT_EXTENDED`)
> Would you be in favor of this proposal? I welcome any comments.


Just be sure that in the default configuration the exit code is finally passed to exit().

The original Arm semihosting use case was intended to run portable unit tests without a debugger (like gdb) connected, and the exit code 0 is paramount to know that the test passed.


Regards,

Liviu

Proposal: Improve Semihosting EXIT Behavior

[Marek V. <mar...@co...>]

Hello all,

I'd like to propose improvements to OpenOCD's semihosting behavior for 
the SYS_EXIT and SYS_EXIT_EXTENDED syscalls.

Currently, if GDB is not connected and the target calls `SYS_EXIT` or 
`SYS_EXIT_EXTENDED` (with the appropriate parameter):

  * If GDB is not connected - OpenOCD calls `exit(code)` immediately,
    without any cleanup. I believe this should be fixed - OpenOCD should
    go trough the standard shutdown sequence.
  * If GDB is connected - message is printed and target is either halted
    or resumed depending on `arm semihosting_resexit`.

I would like to make these improvements:

1. Avoid the direct call to `exit()`

2. Introduce a new command: `arm semihosting_exit_behavior`

The options would be:

  * `always_halt`
  * `always_exit`
  * `exit_if_no_gdb`

3. Introduce commands to get the program exit code in Tcl scripts:

  * `arm semihosting_has_program_exited` - would return true if the
    semihosting exit already happened
  * `arm semihosting_exit_code` - returns exit code (from
    `SYS_EXIT_EXTENDED`)

Would you be in favor of this proposal? I welcome any comments.

Thank you,

Marek Vrbka

[PATCH]: c2b1f72794 flash/nor/stm32lx: Add 'option_{write, read}' functions

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8999

-- gerrit

commit c2b1f727942870d158f58ed9b188bedfb43ff5f8
Author: Marc Schink <de...@za...>
Date:   Sun Jul 13 14:00:50 2025 +0000

    flash/nor/stm32lx: Add 'option_{write,read}' functions
    
    Add functions to read and write the option bytes, inspired by the
    stm32l4x driver.
    
    Tested on STM32L072CZ, including regression tests for 'stm32lx (un)lock'.
    
    Change-Id: I73298e1a668b3f604cbe558422495719832644e8
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index fb4664f3db..22095d4b27 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -8256,6 +8256,40 @@ Level is 2 which can't be unlocked at all).
 The @var{num} parameter is a value shown by @command{flash banks}.
 @end deffn
 
+@deffn {Command} {stm32lx option_read} num reg_offset
+Reads an option byte register from the device.
+The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset} is the register offset of the option byte to read.
+
+For example to read the FLASH_OPTR register:
+@example
+stm32lx option_read 0 0x0
+# Option Register (for STM32L0): 0xaa
+@end example
+
+The above example will read out the first 16-bit of the FLASH_OPTR register which contains the RDP and WPRMOD value.
+@end deffn
+
+@deffn {Command} {stm324x option_write} num reg_offset value [reg_mask]
+Write an option byte register of the device.
+The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset} is the register offset of the option byte to write.
+@var{value} is the 16-bit value that is written into the register.
+The complementary value for the option byte register is calculated automatically.
+@var{reg_mask} is the mask to apply when writing the register (only bits with a '1' will be touched).
+
+@emph{Note:} To modify an entire 32-bit option byte register, two individual write operations are necessary.
+
+For example, to modify the first 16-bit of the FLASH_OPTR register use the following command:
+
+@example
+stm32lx option_write 0 0x00 0x100 0x100
+@end example
+
+The above example sets bit 8 (WPRMOD) on the FLASH_OPTR option byte register which enables PCROP.
+Due to the applied mask, all other bits are not changed.
+
+@emph{Note:} To apply the option bytes change immediately, use @command{stm32lx option_load}.
+@end deffn
+
 @deffn {Command} {stm32lx option_load} num
 Forces a re-load of the option byte registers.
 This command will cause a system reset of the device.
diff --git a/src/flash/nor/stm32lx.c b/src/flash/nor/stm32lx.c
index bf283239c0..69e66e6c67 100644
--- a/src/flash/nor/stm32lx.c
+++ b/src/flash/nor/stm32lx.c
@@ -17,6 +17,7 @@
 
 #include "imp.h"
 #include <helper/binarybuffer.h>
+#include <helper/align.h>
 #include <target/algorithm.h>
 #include <target/armv7m.h>
 #include <target/cortex_m.h>
@@ -82,8 +83,8 @@
 /* option bytes */
 #define OPTION_BYTES_ADDRESS 0x1FF80000
 
-#define OPTION_BYTE_0_PR1 0xFFFF0000
-#define OPTION_BYTE_0_PR0 0xFF5500AA
+#define OPTION_BYTE_0_PR1 0x0000
+#define OPTION_BYTE_0_PR0 0x00AA
 
 static int stm32lx_unlock_program_memory(struct flash_bank *bank);
 static int stm32lx_lock_program_memory(struct flash_bank *bank);
@@ -95,6 +96,8 @@ static int stm32lx_lock(struct flash_bank *bank);
 static int stm32lx_unlock(struct flash_bank *bank);
 static int stm32lx_mass_erase(struct flash_bank *bank);
 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int timeout);
+static int stm32lx_write_option(struct flash_bank *bank, uint32_t reg_offset,
+	uint16_t value, uint16_t mask);
 static int stm32lx_update_part_info(struct flash_bank *bank, uint16_t flash_size_in_kb);
 
 struct stm32lx_rev {
@@ -375,6 +378,76 @@ COMMAND_HANDLER(stm32lx_handle_option_load_command)
 	return ERROR_OK;
 }
 
+COMMAND_HANDLER(stm32lx_handle_option_read_command)
+{
+	if (CMD_ARGC != 2)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	struct flash_bank *bank;
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	uint32_t reg_offset;
+
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
+
+	if (!IS_ALIGNED(reg_offset, 4)) {
+		command_print(CMD, "register offset must be word aligned");
+		return ERROR_COMMAND_ARGUMENT_INVALID;
+	}
+
+	uint16_t value;
+	retval = target_read_u16(bank->target, OPTION_BYTES_ADDRESS + reg_offset,
+		&value);
+
+	if (retval != ERROR_OK) {
+		command_print(CMD, "failed to read option bytes");
+		return retval;
+	}
+
+	command_print(CMD, "0x%" PRIx16 "", value);
+
+	return retval;
+}
+
+COMMAND_HANDLER(stm32lx_handle_option_write_command)
+{
+	if (CMD_ARGC != 3 && CMD_ARGC != 4)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	struct flash_bank *bank;
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	uint32_t reg_offset;
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
+
+	uint16_t value;
+	COMMAND_PARSE_NUMBER(u16, CMD_ARGV[2], value);
+
+	if (!IS_ALIGNED(reg_offset, 4)) {
+		command_print(CMD, "register offset must be word aligned");
+		return ERROR_COMMAND_ARGUMENT_INVALID;
+	}
+
+	uint16_t mask = 0xffff;
+
+	if (CMD_ARGC > 3)
+		COMMAND_PARSE_NUMBER(u16, CMD_ARGV[3], mask);
+
+	retval = stm32lx_write_option(bank, reg_offset, value, mask);
+	if (retval != ERROR_OK) {
+		command_print(CMD, "failed to write option bytes");
+		return retval;
+	}
+
+	return ERROR_OK;
+}
+
 static int stm32lx_protect_check(struct flash_bank *bank)
 {
 	int retval;
@@ -949,6 +1022,20 @@ static const struct command_registration stm32lx_exec_command_handlers[] = {
 		.usage = "bank_id",
 		.help = "Force re-load of device options (will cause device reset).",
 	},
+	{
+		.name = "option_read",
+		.handler = stm32lx_handle_option_read_command,
+		.mode = COMMAND_EXEC,
+		.usage = "bank_id reg_offset",
+		.help = "Read & Display device option bytes.",
+	},
+	{
+		.name = "option_write",
+		.handler = stm32lx_handle_option_write_command,
+		.mode = COMMAND_EXEC,
+		.usage = "bank_id reg_offset value [mask]",
+		.help = "Write device option bit fields with provided value.",
+	},
 	COMMAND_REGISTRATION_DONE
 };
 
@@ -1282,9 +1369,9 @@ static int stm32lx_obl_launch(struct flash_bank *bank)
 	return tries ? ERROR_OK : ERROR_FAIL;
 }
 
-static int stm32lx_lock(struct flash_bank *bank)
+static int stm32lx_write_option(struct flash_bank *bank, uint32_t reg_offset,
+	uint16_t value, uint16_t mask)
 {
-	int retval;
 	struct target *target = bank->target;
 
 	if (target->state != TARGET_HALTED) {
@@ -1292,34 +1379,23 @@ static int stm32lx_lock(struct flash_bank *bank)
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	retval = stm32lx_unlock_options_bytes(bank);
-	if (retval != ERROR_OK)
-		return retval;
+	uint32_t option_data;
+	int retval = target_read_u32(target, OPTION_BYTES_ADDRESS + reg_offset,
+		&option_data);
 
-	/* set the RDP protection level to 1 */
-	retval = target_write_u32(target, OPTION_BYTES_ADDRESS, OPTION_BYTE_0_PR1);
 	if (retval != ERROR_OK)
 		return retval;
 
-	return ERROR_OK;
-}
-
-static int stm32lx_unlock(struct flash_bank *bank)
-{
-	int retval;
-	struct target *target = bank->target;
-
-	if (target->state != TARGET_HALTED) {
-		LOG_ERROR("Target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
 	retval = stm32lx_unlock_options_bytes(bank);
 	if (retval != ERROR_OK)
 		return retval;
 
-	/* set the RDP protection level to 0 */
-	retval = target_write_u32(target, OPTION_BYTES_ADDRESS, OPTION_BYTE_0_PR0);
+	option_data = (option_data & ~mask) | (value & mask);
+	// Calculate the complementary value for both option bytes.
+	option_data = (~(option_data & 0xffff)) << 16 | (option_data & 0xffff);
+
+	retval = target_write_u32(target, OPTION_BYTES_ADDRESS + reg_offset,
+		option_data);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -1330,6 +1406,19 @@ static int stm32lx_unlock(struct flash_bank *bank)
 	return ERROR_OK;
 }
 
+
+static int stm32lx_lock(struct flash_bank *bank)
+{
+	// Set the RDP protection level to 1.
+	return stm32lx_write_option(bank, 0x00, OPTION_BYTE_0_PR1, 0x00ff);
+}
+
+static int stm32lx_unlock(struct flash_bank *bank)
+{
+	// Set the RDP protection level to 0.
+	return stm32lx_write_option(bank, 0x00, OPTION_BYTE_0_PR0, 0x00ff);
+}
+
 static int stm32lx_mass_erase(struct flash_bank *bank)
 {
 	int retval;

-- 

[PATCH]: 158241d03b flash/nor/stm32h7x: Rework 'option_read' output

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9001

-- gerrit

commit 158241d03baab09d7deec4d812bce3e5f659048f
Author: Marc Schink <de...@za...>
Date:   Sun Jul 13 19:56:55 2025 +0000

    flash/nor/stm32h7x: Rework 'option_read' output
    
    Remove the verbose command output to enable processing with Tcl.
    
    Change-Id: Ic552747b78e4c095a267275e0affd3b9643657b4
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c
index c02fae992c..cc22dbd040 100644
--- a/src/flash/nor/stm32h7x.c
+++ b/src/flash/nor/stm32h7x.c
@@ -1114,8 +1114,7 @@ COMMAND_HANDLER(stm32x_handle_option_read_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32,
-			stm32x_get_flash_reg(bank, reg_offset), value);
+	command_print(CMD, "0x%" PRIx32, value);
 
 	return retval;
 }

-- 

[PATCH]: 10ebb2a375 flash/nor/stm32l4x: Rework 'option_read' output

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9000

-- gerrit

commit 10ebb2a37505dbb7f3726bf85f3a0b2bfa17dfb3
Author: Marc Schink <de...@za...>
Date:   Sun Jul 13 19:56:45 2025 +0000

    flash/nor/stm32l4x: Rework 'option_read' output
    
    Remove the verbose command output to enable processing with Tcl.
    
    Change-Id: I97c2ffbd7bbbb3064a98f8977373f6c48272e71e
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 22095d4b27..7b0db14776 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -8357,8 +8357,8 @@ is the register offset of the Option byte to read.
 For example to read the FLASH_OPTR register:
 @example
 stm32l4x option_read 0 0x20
-# Option Register (for STM32L4x): <0x40022020> = 0xffeff8aa
-# Option Register (for STM32WBx): <0x58004020> = ...
+# Option Register (for STM32L4x): 0xffeff8aa
+# Option Register (for STM32WBx): ...
 # The correct flash base address will be used automatically
 @end example
 
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index 8001aaf006..44590c7482 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -2409,17 +2409,16 @@ COMMAND_HANDLER(stm32l4_handle_option_read_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	uint32_t reg_offset, reg_addr;
+	uint32_t reg_offset;
 	uint32_t value = 0;
 
 	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
-	reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
 
 	retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
 	if (retval != ERROR_OK)
 		return retval;
 
-	command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
+	command_print(CMD, "0x%" PRIx32, value);
 
 	return retval;
 }

-- 

[PATCH]: aa7d54dd94 flash/nor/stm32lx: Add 'option_load' command

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8998

-- gerrit

commit aa7d54dd9440ec8b8c792c0065cc715cc464de25
Author: Marc Schink <de...@za...>
Date:   Mon Jul 14 07:01:58 2025 +0000

    flash/nor/stm32lx: Add 'option_load' command
    
    Add command to re-load option bytes.
    
    Change-Id: I5653f2222a48af1fe0332d4bdc3552e481e375d0
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 6d607d697f..fb4664f3db 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -8255,6 +8255,12 @@ data). This is the only way to unlock a protected flash (unless RDP
 Level is 2 which can't be unlocked at all).
 The @var{num} parameter is a value shown by @command{flash banks}.
 @end deffn
+
+@deffn {Command} {stm32lx option_load} num
+Forces a re-load of the option byte registers.
+This command will cause a system reset of the device.
+The @var{num} parameter is a value shown by @command{flash banks}.
+@end deffn
 @end deffn
 
 @deffn {Flash Driver} {stm32l4x}
diff --git a/src/flash/nor/stm32lx.c b/src/flash/nor/stm32lx.c
index 1459e942d1..bf283239c0 100644
--- a/src/flash/nor/stm32lx.c
+++ b/src/flash/nor/stm32lx.c
@@ -90,6 +90,7 @@ static int stm32lx_lock_program_memory(struct flash_bank *bank);
 static int stm32lx_enable_write_half_page(struct flash_bank *bank);
 static int stm32lx_erase_sector(struct flash_bank *bank, int sector);
 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank);
+static int stm32lx_obl_launch(struct flash_bank *bank);
 static int stm32lx_lock(struct flash_bank *bank);
 static int stm32lx_unlock(struct flash_bank *bank);
 static int stm32lx_mass_erase(struct flash_bank *bank);
@@ -354,6 +355,26 @@ COMMAND_HANDLER(stm32lx_handle_unlock_command)
 	return retval;
 }
 
+COMMAND_HANDLER(stm32lx_handle_option_load_command)
+{
+	if (CMD_ARGC != 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	struct flash_bank *bank;
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = stm32lx_obl_launch(bank);
+	if (retval != ERROR_OK) {
+		command_print(CMD, "failed to load option bytes");
+		return retval;
+	}
+
+	return ERROR_OK;
+}
+
 static int stm32lx_protect_check(struct flash_bank *bank)
 {
 	int retval;
@@ -921,6 +942,13 @@ static const struct command_registration stm32lx_exec_command_handlers[] = {
 		.usage = "bank_id",
 		.help = "Lower the readout protection from Level 1 to 0.",
 	},
+	{
+		.name = "option_load",
+		.handler = stm32lx_handle_option_load_command,
+		.mode = COMMAND_EXEC,
+		.usage = "bank_id",
+		.help = "Force re-load of device options (will cause device reset).",
+	},
 	COMMAND_REGISTRATION_DONE
 };
 

-- 

[PATCH]: 285f6bb5fd tcl/board: add mikroe/clicker4-stm32f745vg

[<ge...@op...>]

This is an automated email from Gerrit.

"Ondřej Hošek <ond...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8997

-- gerrit

commit 285f6bb5fdd84729370cb42322d64986c67becd9
Author: Ondřej Hošek <ond...@gm...>
Date:   Mon Jul 14 00:12:19 2025 +0200

    tcl/board: add mikroe/clicker4-stm32f745vg
    
    Add a board configuration file for the MikroElektronika Clicker 4 for
    STM32F745VG (MIKROE-6331), which contains their CMSIS-DAP-compatible
    on-board CODEGRIP programmer.
    
    Place this into its own subdirectory, since MikroElektronika has quite a
    few boards in their portfolio.
    
    Change-Id: If24ca286d65e024f3c3a8522b67727e268ab0bc9
    Signed-off-by: Ondřej Hošek <ond...@gm...>

diff --git a/tcl/board/mikroe/clicker4-stm32f745vg.cfg b/tcl/board/mikroe/clicker4-stm32f745vg.cfg
new file mode 100644
index 0000000000..9ccd948801
--- /dev/null
+++ b/tcl/board/mikroe/clicker4-stm32f745vg.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a MikroElektronika Click 4 board with a single STM32F745VG chip
+# and an on-board CODEGRIP debugger.
+# https://www.mikroe.com/clicker-4-for-stm32f745vgt6
+
+source [find interface/cmsis-dap.cfg]
+transport select jtag
+adapter speed 4000
+
+source [find target/stm32f7x.cfg]

-- 

[PATCH]: d57958aa47 helper/log: Rework 'debug_level' command

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8996

-- gerrit

commit d57958aa4768835f0abdc8918310aa908fd1a2a8
Author: Marc Schink <de...@za...>
Date:   Sun Jul 13 09:05:40 2025 +0200

    helper/log: Rework 'debug_level' command
    
    The patch changes the following:
    
     - Use correct return value ERROR_COMMAND_ARGUMENT_INVALID is case an
       invalid debug level is provided.
     - Do not echo the selected debug level.
     - Remove the 'debug_level: ' prefix when the debug level is shown.
       This makes processing via Tcl easier.
     - Use command_print() in order to provide the error message to the
       caller.
    
    Change-Id: Ida84a58c61060497fc36a1926eec7dd30c66cd72
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/helper/log.c b/src/helper/log.c
index 8f7ab00397..7b48554b75 100644
--- a/src/helper/log.c
+++ b/src/helper/log.c
@@ -207,18 +207,19 @@ void log_printf_lf(enum log_levels level,
 
 COMMAND_HANDLER(handle_debug_level_command)
 {
-	if (CMD_ARGC == 1) {
+	if (!CMD_ARGC) {
+		command_print(CMD, "%i", debug_level);
+	} else if (CMD_ARGC == 1) {
 		int new_level;
 		COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], new_level);
 		if ((new_level > LOG_LVL_DEBUG_IO) || (new_level < LOG_LVL_SILENT)) {
-			LOG_ERROR("level must be between %d and %d", LOG_LVL_SILENT, LOG_LVL_DEBUG_IO);
-			return ERROR_COMMAND_SYNTAX_ERROR;
+			command_print(CMD, "level must be between %d and %d", LOG_LVL_SILENT, LOG_LVL_DEBUG_IO);
+			return ERROR_COMMAND_ARGUMENT_INVALID;
 		}
 		debug_level = new_level;
-	} else if (CMD_ARGC > 1)
+	} else {
 		return ERROR_COMMAND_SYNTAX_ERROR;
-
-	command_print(CMD, "debug_level: %i", debug_level);
+	}
 
 	return ERROR_OK;
 }

-- 

[PATCH]: c07fdaa87e rtt: Fix check for available down-channels

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8995

-- gerrit

commit c07fdaa87e55dc7e30e350447820a843baafa58f
Author: Marc Schink <de...@za...>
Date:   Fri Jul 11 14:39:45 2025 +0200

    rtt: Fix check for available down-channels
    
    The number of up-channels is erroneously checked instead of the number
    of down-channels.
    
    Change-Id: Iff5348387b3466ed66f34df81e1039918608ac77
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/rtt/rtt.c b/src/rtt/rtt.c
index 15b9a373a5..3c7a966a79 100644
--- a/src/rtt/rtt.c
+++ b/src/rtt/rtt.c
@@ -288,7 +288,7 @@ int rtt_set_polling_interval(unsigned int interval)
 int rtt_write_channel(unsigned int channel_index, const uint8_t *buffer,
 		size_t *length)
 {
-	if (channel_index >= rtt.ctrl.num_up_channels) {
+	if (channel_index >= rtt.ctrl.num_down_channels) {
 		LOG_WARNING("rtt: Down-channel %u is not available", channel_index);
 		return ERROR_OK;
 	}

-- 

[PATCH]: 3753f3787f adapter/stlink: Hide '(re)connect' message

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8994

-- gerrit

commit 3753f3787f9566c1dad00fe84c2aaa8fa11b27eb
Author: Marc Schink <de...@za...>
Date:   Fri Jul 11 10:36:16 2025 +0200

    adapter/stlink: Hide '(re)connect' message
    
    Print a debug message rather than an info message because this
    information is not of importance for normal users.
    
    While at it, fix the 'EMBEDDED_FUNCTION_NAME' checkpatch issue.
    
    Change-Id: I9d458a6dd6818fdedc488e39d2daa6d72a21b743
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c
index 5ee1f85261..70a73eeb95 100644
--- a/src/jtag/drivers/stlink_usb.c
+++ b/src/jtag/drivers/stlink_usb.c
@@ -4194,7 +4194,7 @@ static int stlink_dap_op_connect(struct adiv5_dap *dap)
 	uint32_t idcode;
 	int retval;
 
-	LOG_INFO("stlink_dap_op_connect(%sconnect)", dap->do_reconnect ? "re" : "");
+	LOG_DEBUG("%s(%sconnect)", __func__, dap->do_reconnect ? "re" : "");
 
 	/* Check if we should reset srst already when connecting, but not if reconnecting. */
 	if (!dap->do_reconnect) {

-- 

[PATCH]: 0ea8c76579 rtt: Consider target endianness

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8993

-- gerrit

commit 0ea8c76579de0f1f42e0964f79aee1946c60a41b
Author: Marc Schink <de...@za...>
Date:   Tue Jul 8 07:17:19 2025 +0000

    rtt: Consider target endianness
    
    Consider target endianness when reading control block and channel
    information. Current implementation fails on big-endian devices.
    
    Tested on TMS570 (big-endian) and on nRF52 (little-endian).
    
    Note that in its current implementation RTT does not work properly on
    TMS570 due to its missing support for background memory access.
    
    Change-Id: Iab58804c42c85a932a750201a69ded35cebedd5d
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/target/rtt.c b/src/target/rtt.c
index 5ce049ae18..a8ab24a60b 100644
--- a/src/target/rtt.c
+++ b/src/target/rtt.c
@@ -37,12 +37,12 @@ static int read_rtt_channel(struct target *target,
 		return ret;
 
 	channel->address = address;
-	channel->name_addr = buf_get_u32(buf + 0, 0, 32);
-	channel->buffer_addr = buf_get_u32(buf + 4, 0, 32);
-	channel->size = buf_get_u32(buf + 8, 0, 32);
-	channel->write_pos = buf_get_u32(buf + 12, 0, 32);
-	channel->read_pos = buf_get_u32(buf + 16, 0, 32);
-	channel->flags = buf_get_u32(buf + 20, 0, 32);
+	channel->name_addr = target_buffer_get_u32(target, buf + 0);
+	channel->buffer_addr = target_buffer_get_u32(target, buf + 4);
+	channel->size = target_buffer_get_u32(target, buf + 8);
+	channel->write_pos = target_buffer_get_u32(target, buf + 12);
+	channel->read_pos = target_buffer_get_u32(target, buf + 16);
+	channel->flags = target_buffer_get_u32(target, buf + 20);
 
 	return ERROR_OK;
 }
@@ -230,10 +230,8 @@ int target_rtt_read_control_block(struct target *target,
 
 	memcpy(ctrl->id, buf, RTT_CB_MAX_ID_LENGTH);
 	ctrl->id[RTT_CB_MAX_ID_LENGTH - 1] = '\0';
-	ctrl->num_up_channels = buf_get_u32(buf + RTT_CB_MAX_ID_LENGTH + 0,
-		0, 32);
-	ctrl->num_down_channels = buf_get_u32(buf + RTT_CB_MAX_ID_LENGTH + 4,
-		0, 32);
+	ctrl->num_up_channels = target_buffer_get_u32(target, buf + RTT_CB_MAX_ID_LENGTH + 0);
+	ctrl->num_down_channels = target_buffer_get_u32(target, buf + RTT_CB_MAX_ID_LENGTH + 4);
 
 	return ERROR_OK;
 }

-- 

[PATCH]: 4867b41059 target: Use 'bool' data type for {i, d_u}_cache_enabled

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8992

-- gerrit

commit 4867b41059001a2ab9724a84de7efd07796868c0
Author: Marc Schink <de...@za...>
Date:   Wed Jul 9 12:06:59 2025 +0000

    target: Use 'bool' data type for {i,d_u}_cache_enabled
    
    The variables are already used as boolean value but have the wrong
    data type.
    
    Change-Id: Ia4c63d04fdd61bfd48e353fde9984b0e6cefbd8b
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 51ef1a82ac..d1ff023d98 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -1105,9 +1105,9 @@ static int aarch64_post_debug_entry(struct target *target)
 		armv8->armv8_mmu.mmu_enabled = aarch64->system_control_reg & 0x1U;
 	}
 	armv8->armv8_mmu.armv8_cache.d_u_cache_enabled =
-		(aarch64->system_control_reg & 0x4U) ? 1 : 0;
+		aarch64->system_control_reg & 0x4U;
 	armv8->armv8_mmu.armv8_cache.i_cache_enabled =
-		(aarch64->system_control_reg & 0x1000U) ? 1 : 0;
+		aarch64->system_control_reg & 0x1000U;
 	return ERROR_OK;
 }
 
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index c708c1daad..933b49bebc 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -199,8 +199,9 @@ static int arm720t_post_debug_entry(struct target *target)
 	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 
 	arm720t->armv4_5_mmu.mmu_enabled = arm720t->cp15_control_reg & 0x1U;
-	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
-	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
+	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
+		arm720t->cp15_control_reg & 0x4U;
+	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = false;
 
 	/* save i/d fault status and address register */
 	retval = arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
@@ -355,8 +356,8 @@ static int arm720t_soft_reset_halt(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 	arm720t->armv4_5_mmu.mmu_enabled = false;
-	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
-	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
+	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = false;
+	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = false;
 
 	retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 	if (retval != ERROR_OK)
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 4f19affac5..4dd5763539 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -427,9 +427,9 @@ int arm920t_post_debug_entry(struct target *target)
 
 	arm920t->armv4_5_mmu.mmu_enabled = arm920t->cp15_control_reg & 0x1U;
 	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
-		(arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
+		arm920t->cp15_control_reg & 0x4U;
 	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
-		(arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
+		arm920t->cp15_control_reg & 0x1000U;
 
 	/* save i/d fault status and address register
 	 * FIXME use opcode macros */
@@ -778,8 +778,8 @@ int arm920t_soft_reset_halt(struct target *target)
 
 	arm920t_disable_mmu_caches(target, 1, 1, 1);
 	arm920t->armv4_5_mmu.mmu_enabled = false;
-	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
-	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
+	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = false;
+	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = false;
 
 	return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 }
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 8c31765e1b..587f25061f 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -441,8 +441,10 @@ static int arm926ejs_post_debug_entry(struct target *target)
 	}
 
 	arm926ejs->armv4_5_mmu.mmu_enabled = arm926ejs->cp15_control_reg & 0x1U;
-	arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
-	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
+	arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
+		arm926ejs->cp15_control_reg & 0x4U;
+	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
+		arm926ejs->cp15_control_reg & 0x1000U;
 
 	/* save i/d fault status and address register */
 	retval = arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
@@ -576,8 +578,8 @@ int arm926ejs_soft_reset_halt(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 	arm926ejs->armv4_5_mmu.mmu_enabled = false;
-	arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
-	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
+	arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = false;
+	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = false;
 
 	return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 }
diff --git a/src/target/armv4_5_cache.h b/src/target/armv4_5_cache.h
index 3659941e52..63fbdff33a 100644
--- a/src/target/armv4_5_cache.h
+++ b/src/target/armv4_5_cache.h
@@ -24,8 +24,8 @@ struct armv4_5_cache_common {
 	int separate;	/* separate caches or unified cache */
 	struct armv4_5_cachesize d_u_size;	/* data cache */
 	struct armv4_5_cachesize i_size; /* instruction cache */
-	int i_cache_enabled;
-	int d_u_cache_enabled;
+	bool i_cache_enabled;
+	bool d_u_cache_enabled;
 };
 
 int armv4_5_identify_cache(uint32_t cache_type_reg,
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 69e223ddb2..0c5e0f90f6 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -63,8 +63,8 @@ struct armv7a_cache_common {
 	uint32_t dminline;			/* minimum d-cache linelen */
 	uint32_t iminline;			/* minimum i-cache linelen */
 	struct armv7a_arch_cache arch[6];	/* cache info, L1 - L7 */
-	int i_cache_enabled;
-	int d_u_cache_enabled;
+	bool i_cache_enabled;
+	bool d_u_cache_enabled;
 	/* outer unified cache if some */
 	struct armv7a_l2x_cache *outer_cache;
 	int (*flush_all_data_cache)(struct target *target);
diff --git a/src/target/armv8.h b/src/target/armv8.h
index 32c0dc32be..51b8b00cd4 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -156,8 +156,8 @@ struct armv8_cache_common {
 	uint32_t iminline;
 	uint32_t dminline;
 	struct armv8_arch_cache arch[6];	/* cache info, L1 - L7 */
-	int i_cache_enabled;
-	int d_u_cache_enabled;
+	bool i_cache_enabled;
+	bool d_u_cache_enabled;
 
 	/* l2 external unified cache if some */
 	void *l2_cache;
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index d694ec0f28..69bc0920b3 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1127,9 +1127,9 @@ static int cortex_a_post_debug_entry(struct target *target)
 		armv7a->armv7a_mmu.mmu_enabled = cortex_a->cp15_control_reg & 0x1U;
 	}
 	armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled =
-		(cortex_a->cp15_control_reg & 0x4U) ? 1 : 0;
+		cortex_a->cp15_control_reg & 0x4U;
 	armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled =
-		(cortex_a->cp15_control_reg & 0x1000U) ? 1 : 0;
+		cortex_a->cp15_control_reg & 0x1000U;
 	cortex_a->curr_mode = armv7a->arm.core_mode;
 
 	/* switch to SVC mode to read DACR */
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 7eaef6b8c8..783628b128 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -984,9 +984,9 @@ static int xscale_debug_entry(struct target *target)
 		buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
 	xscale->armv4_5_mmu.mmu_enabled = xscale->cp15_control_reg & 0x1U;
 	xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
-		(xscale->cp15_control_reg & 0x4U) ? 1 : 0;
+		xscale->cp15_control_reg & 0x4U;
 	xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
-		(xscale->cp15_control_reg & 0x1000U) ? 1 : 0;
+		xscale->cp15_control_reg & 0x1000U;
 
 	/* tracing enabled, read collected trace data */
 	if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {

-- 

[PATCH]: 6f89bd4b49 target: Use 'bool' data type for 'mmu_enabled'

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8988

-- gerrit

commit 6f89bd4b49ff68297ade78b191ec95b32725c223
Author: Marc Schink <de...@za...>
Date:   Wed Jul 9 11:31:37 2025 +0000

    target: Use 'bool' data type for 'mmu_enabled'
    
    The variables are already used in some parts of the code as boolean
    value but have the wrong data type.
    
    Change-Id: I2c4955a6ed463fabf63a1dbd79145cb63bc7a99c
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 101cb14408..f6fc6db4e6 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -1100,10 +1100,9 @@ static int aarch64_post_debug_entry(struct target *target)
 		armv8_read_mpidr(armv8);
 	}
 	if (armv8->is_armv8r) {
-		armv8->armv8_mmu.mmu_enabled = 0;
+		armv8->armv8_mmu.mmu_enabled = false;
 	} else {
-		armv8->armv8_mmu.mmu_enabled =
-			(aarch64->system_control_reg & 0x1U) ? 1 : 0;
+		armv8->armv8_mmu.mmu_enabled = aarch64->system_control_reg & 0x1U;
 	}
 	armv8->armv8_mmu.armv8_cache.d_u_cache_enabled =
 		(aarch64->system_control_reg & 0x4U) ? 1 : 0;
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index d1433dde72..c9ee62d3d1 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -198,7 +198,7 @@ static int arm720t_post_debug_entry(struct target *target)
 		return retval;
 	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 
-	arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
+	arm720t->armv4_5_mmu.mmu_enabled = arm720t->cp15_control_reg & 0x1U;
 	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
 	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
@@ -354,7 +354,7 @@ static int arm720t_soft_reset_halt(struct target *target)
 	retval = arm720t_disable_mmu_caches(target, 1, 1, 1);
 	if (retval != ERROR_OK)
 		return retval;
-	arm720t->armv4_5_mmu.mmu_enabled = 0;
+	arm720t->armv4_5_mmu.mmu_enabled = false;
 	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
@@ -407,7 +407,7 @@ static int arm720t_init_arch_info(struct target *target,
 	arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
 	arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
 	arm720t->armv4_5_mmu.has_tiny_pages = 0;
-	arm720t->armv4_5_mmu.mmu_enabled = 0;
+	arm720t->armv4_5_mmu.mmu_enabled = false;
 
 	return ERROR_OK;
 }
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 95cfd7ceb2..9faae9a474 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -425,8 +425,7 @@ int arm920t_post_debug_entry(struct target *target)
 			&arm920t->armv4_5_mmu.armv4_5_cache);
 	}
 
-	arm920t->armv4_5_mmu.mmu_enabled =
-		(arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
+	arm920t->armv4_5_mmu.mmu_enabled = arm920t->cp15_control_reg & 0x1U;
 	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
 		(arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
 	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
@@ -778,7 +777,7 @@ int arm920t_soft_reset_halt(struct target *target)
 	arm->pc->valid = true;
 
 	arm920t_disable_mmu_caches(target, 1, 1, 1);
-	arm920t->armv4_5_mmu.mmu_enabled = 0;
+	arm920t->armv4_5_mmu.mmu_enabled = false;
 	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
@@ -819,7 +818,7 @@ static int arm920t_init_arch_info(struct target *target,
 	arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
 	arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
 	arm920t->armv4_5_mmu.has_tiny_pages = 1;
-	arm920t->armv4_5_mmu.mmu_enabled = 0;
+	arm920t->armv4_5_mmu.mmu_enabled = false;
 
 	/* disabling linefills leads to lockups, so keep them enabled for now
 	 * this doesn't affect correctness, but might affect timing issues, if
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 0531106562..922b02013f 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -440,7 +440,7 @@ static int arm926ejs_post_debug_entry(struct target *target)
 		armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 	}
 
-	arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
+	arm926ejs->armv4_5_mmu.mmu_enabled = arm926ejs->cp15_control_reg & 0x1U;
 	arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
 	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
 
@@ -575,7 +575,7 @@ int arm926ejs_soft_reset_halt(struct target *target)
 	retval = arm926ejs_disable_mmu_caches(target, 1, 1, 1);
 	if (retval != ERROR_OK)
 		return retval;
-	arm926ejs->armv4_5_mmu.mmu_enabled = 0;
+	arm926ejs->armv4_5_mmu.mmu_enabled = false;
 	arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
@@ -689,7 +689,7 @@ int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm
 	arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
 	arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
 	arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
-	arm926ejs->armv4_5_mmu.mmu_enabled = 0;
+	arm926ejs->armv4_5_mmu.mmu_enabled = false;
 
 	arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
 
diff --git a/src/target/armv4_5_mmu.h b/src/target/armv4_5_mmu.h
index 774f1056eb..bb30e807f4 100644
--- a/src/target/armv4_5_mmu.h
+++ b/src/target/armv4_5_mmu.h
@@ -21,7 +21,7 @@ struct armv4_5_mmu_common {
 	int (*enable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
 	struct armv4_5_cache_common armv4_5_cache;
 	int has_tiny_pages;
-	int mmu_enabled;
+	bool mmu_enabled;
 };
 
 int armv4_5_mmu_translate_va(struct target *target,
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 2706c4629b..69e223ddb2 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -81,7 +81,7 @@ struct armv7a_mmu_common {
 	int (*read_physical_memory)(struct target *target, target_addr_t address, uint32_t size,
 			uint32_t count, uint8_t *buffer);
 	struct armv7a_cache_common armv7a_cache;
-	uint32_t mmu_enabled;
+	bool mmu_enabled;
 };
 
 struct armv7a_common {
diff --git a/src/target/armv8.h b/src/target/armv8.h
index 64ca5ec9d4..32c0dc32be 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -179,7 +179,7 @@ struct armv8_mmu_common {
 	int (*read_physical_memory)(struct target *target, target_addr_t address,
 			uint32_t size, uint32_t count, uint8_t *buffer);
 	struct armv8_cache_common armv8_cache;
-	uint32_t mmu_enabled;
+	bool mmu_enabled;
 };
 
 struct armv8_common {
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 2ebbf65774..3d979bbabd 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1122,10 +1122,9 @@ static int cortex_a_post_debug_entry(struct target *target)
 		armv7a_identify_cache(target);
 
 	if (armv7a->is_armv7r) {
-		armv7a->armv7a_mmu.mmu_enabled = 0;
+		armv7a->armv7a_mmu.mmu_enabled = false;
 	} else {
-		armv7a->armv7a_mmu.mmu_enabled =
-			(cortex_a->cp15_control_reg & 0x1U) ? 1 : 0;
+		armv7a->armv7a_mmu.mmu_enabled = cortex_a->cp15_control_reg & 0x1U;
 	}
 	armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled =
 		(cortex_a->cp15_control_reg & 0x4U) ? 1 : 0;
diff --git a/src/target/fa526.c b/src/target/fa526.c
index d832d3e7d1..254e5be6e3 100644
--- a/src/target/fa526.c
+++ b/src/target/fa526.c
@@ -315,7 +315,7 @@ static int fa526_init_arch_info(struct target *target,
 	arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
 	arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
 	arm920t->armv4_5_mmu.has_tiny_pages = 1;
-	arm920t->armv4_5_mmu.mmu_enabled = 0;
+	arm920t->armv4_5_mmu.mmu_enabled = false;
 
 	/* disabling linefills leads to lockups, so keep them enabled for now
 	 * this doesn't affect correctness, but might affect timing issues, if
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 84318a905f..b3d43ec7e9 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -982,7 +982,7 @@ static int xscale_debug_entry(struct target *target)
 	xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
 	xscale->cp15_control_reg =
 		buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
-	xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0;
+	xscale->armv4_5_mmu.mmu_enabled = xscale->cp15_control_reg & 0x1U;
 	xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
 		(xscale->cp15_control_reg & 0x4U) ? 1 : 0;
 	xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
@@ -3007,7 +3007,7 @@ static int xscale_init_arch_info(struct target *target,
 	xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches;
 	xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
 	xscale->armv4_5_mmu.has_tiny_pages = 1;
-	xscale->armv4_5_mmu.mmu_enabled = 0;
+	xscale->armv4_5_mmu.mmu_enabled = false;
 
 	return ERROR_OK;
 }

-- 

[PATCH]: b6ccd28df4 target/cortex_a: Use 'bool' data type for cortex_a_*_memaccess()

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8990

-- gerrit

commit b6ccd28df4ef9be98925883d424a571d3ec2a513
Author: Marc Schink <de...@za...>
Date:   Tue Jul 8 13:52:43 2025 +0000

    target/cortex_a: Use 'bool' data type for cortex_a_*_memaccess()
    
    Use 'bool' because it is the appropriate data type.
    
    Change-Id: I543b153fe5f6af4d20988b95eb17f2357e706a76
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index b2cb75b98f..42d01c3ac1 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -109,13 +109,13 @@ static int cortex_a_restore_cp15_control_reg(struct target *target)
  * If !phys_access, switch to SVC mode and make sure MMU is on
  * If phys_access, switch off mmu
  */
-static int cortex_a_prep_memaccess(struct target *target, int phys_access)
+static int cortex_a_prep_memaccess(struct target *target, bool phys_access)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct cortex_a_common *cortex_a = target_to_cortex_a(target);
 	bool mmu_enabled = false;
 
-	if (phys_access == 0) {
+	if (!phys_access) {
 		arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
 		cortex_a_mmu(target, &mmu_enabled);
 		if (mmu_enabled)
@@ -139,12 +139,12 @@ static int cortex_a_prep_memaccess(struct target *target, int phys_access)
  * If !phys_access, switch to previous mode
  * If phys_access, restore MMU setting
  */
-static int cortex_a_post_memaccess(struct target *target, int phys_access)
+static int cortex_a_post_memaccess(struct target *target, bool phys_access)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct cortex_a_common *cortex_a = target_to_cortex_a(target);
 
-	if (phys_access == 0) {
+	if (!phys_access) {
 		if (cortex_a->dacrfixup_mode == CORTEX_A_DACRFIXUP_ON) {
 			/* restore */
 			armv7a->arm.mcr(target, 15,
@@ -2770,9 +2770,9 @@ static int cortex_a_read_phys_memory(struct target *target,
 		address, size, count);
 
 	/* read memory through the CPU */
-	cortex_a_prep_memaccess(target, 1);
+	cortex_a_prep_memaccess(target, true);
 	retval = cortex_a_read_cpu_memory(target, address, size, count, buffer);
-	cortex_a_post_memaccess(target, 1);
+	cortex_a_post_memaccess(target, true);
 
 	return retval;
 }
@@ -2786,9 +2786,9 @@ static int cortex_a_read_memory(struct target *target, target_addr_t address,
 	LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
 		address, size, count);
 
-	cortex_a_prep_memaccess(target, 0);
+	cortex_a_prep_memaccess(target, false);
 	retval = cortex_a_read_cpu_memory(target, address, size, count, buffer);
-	cortex_a_post_memaccess(target, 0);
+	cortex_a_post_memaccess(target, false);
 
 	return retval;
 }
@@ -2806,9 +2806,9 @@ static int cortex_a_write_phys_memory(struct target *target,
 		address, size, count);
 
 	/* write memory through the CPU */
-	cortex_a_prep_memaccess(target, 1);
+	cortex_a_prep_memaccess(target, true);
 	retval = cortex_a_write_cpu_memory(target, address, size, count, buffer);
-	cortex_a_post_memaccess(target, 1);
+	cortex_a_post_memaccess(target, true);
 
 	return retval;
 }
@@ -2822,9 +2822,9 @@ static int cortex_a_write_memory(struct target *target, target_addr_t address,
 	LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
 		address, size, count);
 
-	cortex_a_prep_memaccess(target, 0);
+	cortex_a_prep_memaccess(target, false);
 	retval = cortex_a_write_cpu_memory(target, address, size, count, buffer);
-	cortex_a_post_memaccess(target, 0);
+	cortex_a_post_memaccess(target, false);
 	return retval;
 }
 

-- 

[PATCH]: becb3dbcaa target: Use 'bool' data type in mmu()

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8989

-- gerrit

commit becb3dbcaa0ab528593866fa5014e1bcd1acb40c
Author: Marc Schink <de...@za...>
Date:   Wed Jul 9 11:37:30 2025 +0000

    target: Use 'bool' data type in mmu()
    
    The variable is already used in some parts of the code as boolean value
    but have the wrong data type.
    
    Change-Id: I50ccbf84c6f33a3034de989789c6b17312458ea8
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index f6fc6db4e6..51ef1a82ac 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -50,7 +50,7 @@ static int aarch64_set_hybrid_breakpoint(struct target *target,
 	struct breakpoint *breakpoint);
 static int aarch64_unset_breakpoint(struct target *target,
 	struct breakpoint *breakpoint);
-static int aarch64_mmu(struct target *target, int *enabled);
+static int aarch64_mmu(struct target *target, bool *enabled);
 static int aarch64_virt2phys(struct target *target,
 	target_addr_t virt, target_addr_t *phys);
 static int aarch64_read_cpu_memory(struct target *target,
@@ -2528,7 +2528,7 @@ static int aarch64_read_phys_memory(struct target *target,
 static int aarch64_read_memory(struct target *target, target_addr_t address,
 	uint32_t size, uint32_t count, uint8_t *buffer)
 {
-	int mmu_enabled = 0;
+	bool mmu_enabled = false;
 	int retval;
 
 	/* determine if MMU was enabled on target stop */
@@ -2565,7 +2565,7 @@ static int aarch64_write_phys_memory(struct target *target,
 static int aarch64_write_memory(struct target *target, target_addr_t address,
 	uint32_t size, uint32_t count, const uint8_t *buffer)
 {
-	int mmu_enabled = 0;
+	bool mmu_enabled = false;
 	int retval;
 
 	/* determine if MMU was enabled on target stop */
@@ -2876,7 +2876,7 @@ static void aarch64_deinit_target(struct target *target)
 	free(aarch64);
 }
 
-static int aarch64_mmu(struct target *target, int *enabled)
+static int aarch64_mmu(struct target *target, bool *enabled)
 {
 	struct aarch64_common *aarch64 = target_to_aarch64(target);
 	struct armv8_common *armv8 = &aarch64->armv8_common;
@@ -2885,7 +2885,7 @@ static int aarch64_mmu(struct target *target, int *enabled)
 		return ERROR_TARGET_NOT_HALTED;
 	}
 	if (armv8->is_armv8r)
-		*enabled = 0;
+		*enabled = false;
 	else
 		*enabled = target_to_aarch64(target)->armv8_common.armv8_mmu.mmu_enabled;
 	return ERROR_OK;
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index c9ee62d3d1..c708c1daad 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -238,7 +238,7 @@ static int arm720t_arch_state(struct target *target)
 	return ERROR_OK;
 }
 
-static int arm720_mmu(struct target *target, int *enabled)
+static int arm720_mmu(struct target *target, bool *enabled)
 {
 	if (target->state != TARGET_HALTED) {
 		LOG_TARGET_ERROR(target, "not halted");
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 9faae9a474..4f19affac5 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -529,7 +529,7 @@ int arm920t_arch_state(struct target *target)
 	return ERROR_OK;
 }
 
-static int arm920_mmu(struct target *target, int *enabled)
+static int arm920_mmu(struct target *target, bool *enabled)
 {
 	if (target->state != TARGET_HALTED) {
 		LOG_TARGET_ERROR(target, "not halted");
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 922b02013f..8c31765e1b 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -749,7 +749,7 @@ static int arm926ejs_virt2phys(struct target *target, target_addr_t virtual, tar
 	return ERROR_OK;
 }
 
-static int arm926ejs_mmu(struct target *target, int *enabled)
+static int arm926ejs_mmu(struct target *target, bool *enabled)
 {
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 3d979bbabd..b2cb75b98f 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -68,7 +68,7 @@ static int cortex_a_unset_breakpoint(struct target *target,
 	struct breakpoint *breakpoint);
 static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
 	uint32_t value, uint32_t *dscr);
-static int cortex_a_mmu(struct target *target, int *enabled);
+static int cortex_a_mmu(struct target *target, bool *enabled);
 static int cortex_a_mmu_modify(struct target *target, int enable);
 static int cortex_a_virt2phys(struct target *target,
 	target_addr_t virt, target_addr_t *phys);
@@ -113,7 +113,7 @@ static int cortex_a_prep_memaccess(struct target *target, int phys_access)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct cortex_a_common *cortex_a = target_to_cortex_a(target);
-	int mmu_enabled = 0;
+	bool mmu_enabled = false;
 
 	if (phys_access == 0) {
 		arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
@@ -153,7 +153,7 @@ static int cortex_a_post_memaccess(struct target *target, int phys_access)
 		}
 		arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
 	} else {
-		int mmu_enabled = 0;
+		bool mmu_enabled = false;
 		cortex_a_mmu(target, &mmu_enabled);
 		if (mmu_enabled)
 			cortex_a_mmu_modify(target, 1);
@@ -3249,7 +3249,7 @@ static void cortex_a_deinit_target(struct target *target)
 	free(cortex_a);
 }
 
-static int cortex_a_mmu(struct target *target, int *enabled)
+static int cortex_a_mmu(struct target *target, bool *enabled)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 
@@ -3259,7 +3259,7 @@ static int cortex_a_mmu(struct target *target, int *enabled)
 	}
 
 	if (armv7a->is_armv7r)
-		*enabled = 0;
+		*enabled = false;
 	else
 		*enabled = target_to_cortex_a(target)->armv7a_common.armv7a_mmu.mmu_enabled;
 
@@ -3270,7 +3270,7 @@ static int cortex_a_virt2phys(struct target *target,
 	target_addr_t virt, target_addr_t *phys)
 {
 	int retval;
-	int mmu_enabled = 0;
+	bool mmu_enabled = false;
 
 	/*
 	 * If the MMU was not enabled at debug entry, there is no
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 11ef8f9b92..4ba0122ab0 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -1520,10 +1520,10 @@ static int riscv_target_resume(struct target *target, bool current,
 			debug_execution, false);
 }
 
-static int riscv_mmu(struct target *target, int *enabled)
+static int riscv_mmu(struct target *target, bool *enabled)
 {
 	if (!riscv_enable_virt2phys) {
-		*enabled = 0;
+		*enabled = false;
 		return ERROR_OK;
 	}
 
@@ -1542,7 +1542,7 @@ static int riscv_mmu(struct target *target, int *enabled)
 
 	if ((get_field(mstatus, MSTATUS_MPRV) ? get_field(mstatus, MSTATUS_MPP) : priv) == PRV_M) {
 		LOG_DEBUG("SATP/MMU ignored in Machine mode (mstatus=0x%" PRIx64 ").", mstatus);
-		*enabled = 0;
+		*enabled = false;
 		return ERROR_OK;
 	}
 
@@ -1550,16 +1550,16 @@ static int riscv_mmu(struct target *target, int *enabled)
 	if (riscv_get_register(target, &satp, GDB_REGNO_SATP) != ERROR_OK) {
 		LOG_DEBUG("Couldn't read SATP.");
 		/* If we can't read SATP, then there must not be an MMU. */
-		*enabled = 0;
+		*enabled = false;
 		return ERROR_OK;
 	}
 
 	if (get_field(satp, RISCV_SATP_MODE(riscv_xlen(target))) == SATP_MODE_OFF) {
 		LOG_DEBUG("MMU is disabled.");
-		*enabled = 0;
+		*enabled = false;
 	} else {
 		LOG_DEBUG("MMU is enabled.");
-		*enabled = 1;
+		*enabled = true;
 	}
 
 	return ERROR_OK;
@@ -1674,7 +1674,7 @@ static int riscv_address_translate(struct target *target,
 
 static int riscv_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
 {
-	int enabled;
+	bool enabled;
 	if (riscv_mmu(target, &enabled) == ERROR_OK) {
 		if (!enabled)
 			return ERROR_FAIL;
diff --git a/src/target/target.c b/src/target/target.c
index 995adbc9d3..1428fac913 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -650,9 +650,9 @@ static int identity_virt2phys(struct target *target,
 	return ERROR_OK;
 }
 
-static int no_mmu(struct target *target, int *enabled)
+static int no_mmu(struct target *target, bool *enabled)
 {
-	*enabled = 0;
+	*enabled = false;
 	return ERROR_OK;
 }
 
@@ -1978,7 +1978,7 @@ int target_alloc_working_area_try(struct target *target, uint32_t size, struct w
 	/* Reevaluate working area address based on MMU state*/
 	if (!target->working_areas) {
 		int retval;
-		int enabled;
+		bool enabled;
 
 		retval = target->type->mmu(target, &enabled);
 		if (retval != ERROR_OK)
diff --git a/src/target/target_type.h b/src/target/target_type.h
index a146fab763..ccbe03a476 100644
--- a/src/target/target_type.h
+++ b/src/target/target_type.h
@@ -264,7 +264,7 @@ struct target_type {
 	int (*write_phys_memory)(struct target *target, target_addr_t phys_address,
 			uint32_t size, uint32_t count, const uint8_t *buffer);
 
-	int (*mmu)(struct target *target, int *enabled);
+	int (*mmu)(struct target *target, bool *enabled);
 
 	/* after reset is complete, the target can check if things are properly set up.
 	 *
diff --git a/src/target/x86_32_common.c b/src/target/x86_32_common.c
index 8cca9a5e91..f6dc71bacd 100644
--- a/src/target/x86_32_common.c
+++ b/src/target/x86_32_common.c
@@ -96,7 +96,7 @@ int x86_32_common_init_arch_info(struct target *t, struct x86_32_common *x86_32)
 	return ERROR_OK;
 }
 
-int x86_32_common_mmu(struct target *t, int *enabled)
+int x86_32_common_mmu(struct target *t, bool *enabled)
 {
 	*enabled = true;
 	return ERROR_OK;
diff --git a/src/target/x86_32_common.h b/src/target/x86_32_common.h
index e232747697..7e8672ea00 100644
--- a/src/target/x86_32_common.h
+++ b/src/target/x86_32_common.h
@@ -299,7 +299,7 @@ int x86_32_get_gdb_reg_list(struct target *t,
 			enum target_register_class reg_class);
 int x86_32_common_init_arch_info(struct target *target,
 			struct x86_32_common *x86_32);
-int x86_32_common_mmu(struct target *t, int *enabled);
+int x86_32_common_mmu(struct target *t, bool *enabled);
 int x86_32_common_virt2phys(struct target *t, target_addr_t address, target_addr_t *physical);
 int x86_32_common_read_phys_mem(struct target *t, target_addr_t phys_address,
 			uint32_t size, uint32_t count, uint8_t *buffer);
diff --git a/src/target/xscale.c b/src/target/xscale.c
index b3d43ec7e9..7eaef6b8c8 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -3126,7 +3126,7 @@ static int xscale_virt2phys(struct target *target,
 	return ERROR_OK;
 }
 
-static int xscale_mmu(struct target *target, int *enabled)
+static int xscale_mmu(struct target *target, bool *enabled)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index 3366623d64..1a402743fa 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -1556,7 +1556,7 @@ int xtensa_get_gdb_reg_list(struct target *target,
 	return ERROR_OK;
 }
 
-int xtensa_mmu_is_enabled(struct target *target, int *enabled)
+int xtensa_mmu_is_enabled(struct target *target, bool *enabled)
 {
 	struct xtensa *xtensa = target_to_xtensa(target);
 	*enabled = xtensa->core_config->mmu.itlb_entries_count > 0 ||
diff --git a/src/target/xtensa/xtensa.h b/src/target/xtensa/xtensa.h
index a920f77cdf..daa88b10d1 100644
--- a/src/target/xtensa/xtensa.h
+++ b/src/target/xtensa/xtensa.h
@@ -392,7 +392,7 @@ int xtensa_step(struct target *target, bool current, target_addr_t address,
 		bool handle_breakpoints);
 int xtensa_do_step(struct target *target, bool current, target_addr_t address,
 		bool handle_breakpoints);
-int xtensa_mmu_is_enabled(struct target *target, int *enabled);
+int xtensa_mmu_is_enabled(struct target *target, bool *enabled);
 int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 int xtensa_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer);
 int xtensa_write_memory(struct target *target,

-- 

[PATCH]: 4cbd8ca856 target/cortex_a: Use 'bool' data type in cortex_a_mmu_modify()

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8991

-- gerrit

commit 4cbd8ca856eb3e745cf64d9a8a956328db364b8c
Author: Marc Schink <de...@za...>
Date:   Wed Jul 9 11:45:23 2025 +0000

    target/cortex_a: Use 'bool' data type in cortex_a_mmu_modify()
    
    The variables are already used as boolean value but have the wrong
    data type.
    
    Change-Id: Ia1660751063993fcf46c86246e93a75089629ab5
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 42d01c3ac1..d694ec0f28 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -69,7 +69,7 @@ static int cortex_a_unset_breakpoint(struct target *target,
 static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
 	uint32_t value, uint32_t *dscr);
 static int cortex_a_mmu(struct target *target, bool *enabled);
-static int cortex_a_mmu_modify(struct target *target, int enable);
+static int cortex_a_mmu_modify(struct target *target, bool enable);
 static int cortex_a_virt2phys(struct target *target,
 	target_addr_t virt, target_addr_t *phys);
 static int cortex_a_read_cpu_memory(struct target *target,
@@ -119,7 +119,7 @@ static int cortex_a_prep_memaccess(struct target *target, bool phys_access)
 		arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
 		cortex_a_mmu(target, &mmu_enabled);
 		if (mmu_enabled)
-			cortex_a_mmu_modify(target, 1);
+			cortex_a_mmu_modify(target, true);
 		if (cortex_a->dacrfixup_mode == CORTEX_A_DACRFIXUP_ON) {
 			/* overwrite DACR to all-manager */
 			armv7a->arm.mcr(target, 15,
@@ -129,7 +129,7 @@ static int cortex_a_prep_memaccess(struct target *target, bool phys_access)
 	} else {
 		cortex_a_mmu(target, &mmu_enabled);
 		if (mmu_enabled)
-			cortex_a_mmu_modify(target, 0);
+			cortex_a_mmu_modify(target, false);
 	}
 	return ERROR_OK;
 }
@@ -156,7 +156,7 @@ static int cortex_a_post_memaccess(struct target *target, bool phys_access)
 		bool mmu_enabled = false;
 		cortex_a_mmu(target, &mmu_enabled);
 		if (mmu_enabled)
-			cortex_a_mmu_modify(target, 1);
+			cortex_a_mmu_modify(target, true);
 	}
 	return ERROR_OK;
 }
@@ -165,12 +165,12 @@ static int cortex_a_post_memaccess(struct target *target, bool phys_access)
 /*  modify cp15_control_reg in order to enable or disable mmu for :
  *  - virt2phys address conversion
  *  - read or write memory in phys or virt address */
-static int cortex_a_mmu_modify(struct target *target, int enable)
+static int cortex_a_mmu_modify(struct target *target, bool enable)
 {
 	struct cortex_a_common *cortex_a = target_to_cortex_a(target);
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	int retval = ERROR_OK;
-	int need_write = 0;
+	bool need_write = false;
 
 	if (enable) {
 		/*  if mmu enabled at target stop and mmu not enable */
@@ -180,12 +180,12 @@ static int cortex_a_mmu_modify(struct target *target, int enable)
 		}
 		if ((cortex_a->cp15_control_reg_curr & 0x1U) == 0) {
 			cortex_a->cp15_control_reg_curr |= 0x1U;
-			need_write = 1;
+			need_write = true;
 		}
 	} else {
 		if ((cortex_a->cp15_control_reg_curr & 0x1U) == 0x1U) {
 			cortex_a->cp15_control_reg_curr &= ~0x1U;
-			need_write = 1;
+			need_write = true;
 		}
 	}
 
@@ -3285,7 +3285,7 @@ static int cortex_a_virt2phys(struct target *target,
 	}
 
 	/* mmu must be enable in order to get a correct translation */
-	retval = cortex_a_mmu_modify(target, 1);
+	retval = cortex_a_mmu_modify(target, true);
 	if (retval != ERROR_OK)
 		return retval;
 	return armv7a_mmu_translate_va_pa(target, (uint32_t)virt,

-- 

[PATCH]: 259e221583 target/xtensa: fix unaligned memory read on retry

[<ge...@op...>]

This is an automated email from Gerrit.

"Samuel Obuch <sam...@es...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8987

-- gerrit

commit 259e2215839a557ce42ba854b883d99f818dabae
Author: Samuel Obuch <sam...@es...>
Date:   Tue Jul 8 22:04:08 2025 +0200

    target/xtensa: fix unaligned memory read on retry
    
    When we read unaligned memory there is an offset in the albuff buffer,
    that we account for when copying back to original buffer. But in case
    the first access failed, the retry call already removed the offset,
    so doing it a second time shifts the returned memory.
    
    Change-Id: Ie255c367ca6a001bfe7038a76cf8a6443e398c51
    Signed-off-by: Samuel Obuch <sam...@es...>

diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index 3366623d64..a0500b44e5 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -2071,13 +2071,16 @@ int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t si
 		if (xtensa->probe_lsddr32p == -1)
 			xtensa->probe_lsddr32p = 1;
 		xtensa->suppress_dsr_errors = prev_suppress;
+		if (bswap)
+			buf_bswap32(albuff, albuff, addrend_al - addrstart_al);
+		memcpy(buffer, albuff + (address & 3), (size * count));
 	}
 	if (res != ERROR_OK) {
 		if (xtensa->probe_lsddr32p != 0) {
 			/* Disable fast memory access instructions and retry before reporting an error */
 			LOG_TARGET_DEBUG(target, "Disabling LDDR32.P/SDDR32.P");
 			xtensa->probe_lsddr32p = 0;
-			res = xtensa_read_memory(target, address, size, count, albuff);
+			res = xtensa_read_memory(target, address, size, count, buffer);
 			bswap = false;
 		} else {
 			LOG_TARGET_WARNING(target, "Failed reading %d bytes at address "TARGET_ADDR_FMT,
@@ -2085,9 +2088,6 @@ int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t si
 		}
 	}
 
-	if (bswap)
-		buf_bswap32(albuff, albuff, addrend_al - addrstart_al);
-	memcpy(buffer, albuff + (address & 3), (size * count));
 	free(albuff);
 	return res;
 }

-- 

[PATCH]: 29a24a52cb adapter/xds110: Hide '(dis)connected' message

[<ge...@op...>]

This is an automated email from Gerrit.

"zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8986

-- gerrit

commit 29a24a52cb16f35422bce44b6f6ec0b1f331b798
Author: Marc Schink <de...@za...>
Date:   Tue Jul 8 07:57:27 2025 +0000

    adapter/xds110: Hide '(dis)connected' message
    
    Print a debug message rather than an info message because this
    information is not of importance for normal users.
    
    Change-Id: Ie91565df455ffc0bfe976d1782dd4318bfd2d30b
    Signed-off-by: Marc Schink <de...@za...>

diff --git a/src/jtag/drivers/xds110.c b/src/jtag/drivers/xds110.c
index d1bb705908..6b3ca5cfb6 100644
--- a/src/jtag/drivers/xds110.c
+++ b/src/jtag/drivers/xds110.c
@@ -428,7 +428,7 @@ static bool usb_connect(void)
 
 	/* Log the results */
 	if (result == 0)
-		LOG_INFO("XDS110: connected");
+		LOG_DEBUG("XDS110: connected");
 	else
 		LOG_ERROR("XDS110: failed to connect");
 
@@ -448,7 +448,7 @@ static void usb_disconnect(void)
 		xds110.ctx = NULL;
 	}
 
-	LOG_INFO("XDS110: disconnected");
+	LOG_DEBUG("XDS110: disconnected");
 }
 
 static bool usb_read(unsigned char *buffer, int size, int *bytes_read,

-- 

[PATCH]: 266d5d5f7f flash/stm32h7x: support STM32H7R/H7Sx

[<ge...@op...>]

This is an automated email from Gerrit.

"Ahmed Haoues <ahm...@st...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8890

-- gerrit

commit 266d5d5f7f75604522f86043f60bb192835e7f42
Author: HAOUES Ahmed <ahm...@st...>
Date:   Thu Jul 3 17:38:20 2025 +0100

    flash/stm32h7x: support STM32H7R/H7Sx
    
    The STM32H7R/H7Sx has a flash size up to 64 Kb
    Change-Id: I2e9d80758d1bc88defdd6bbd1787026373b39fa4
    Signed-off-by: HAOUES Ahmed <ahm...@st...>

diff --git a/contrib/loaders/flash/stm32/stm32h7rx.S b/contrib/loaders/flash/stm32/stm32h7rx.S
new file mode 100644
index 0000000000..bfc4929d09
--- /dev/null
+++ b/contrib/loaders/flash/stm32/stm32h7rx.S
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ *   Copyright (C) 2017 by STMicroelectronics                              *
+ ***************************************************************************/
+
+	.text
+	.syntax unified
+	.cpu cortex-m4
+	.thumb
+
+/*
+ * Code limitations:
+ * The workarea must have size multiple of 4 bytes, since R/W
+ * operations are all at 32 bits.
+ * The workarea must be big enough to contain rp, wp and data, thus the minimum
+ * workarea size is: min_wa_size = sizeof(rp, wp, data) = 4 + 4 + sizeof(data).
+ *  - for 0x450 devices: sizeof(data) = 32 bytes, thus min_wa_size = 40 bytes.
+ *  - for 0x480 devices: sizeof(data) = 16 bytes, thus min_wa_size = 24 bytes.
+ * To benefit from concurrent host write-to-buffer and target
+ * write-to-flash, the workarea must be way bigger than the minimum.
+ *
+ * To avoid confusions the write word size is got from .block_size member of
+ * struct stm32h7x_part_info defined in stm32h7x.c
+*/
+
+/*
+ * Params :
+ * r0 = workarea start, status (out)
+ * r1 = workarea end
+ * r2 = target address
+ * r3 = count (of write words)
+ * r4 = size of write word
+ * r5 = flash reg base
+ *
+ * Clobbered:
+ * r6 - rp
+ * r7 - wp, status, tmp
+ * r8 - loop index, tmp
+ */
+
+#define STM32_FLASH_CR_OFFSET	0x10	/* offset of CR register in FLASH struct */
+#define STM32_FLASH_SR_OFFSET	0x14	/* offset of SR register in FLASH struct */
+#define STM32_FLASH_ICR_OFFSET	0x28	/* offset of SR register in FLASH struct */
+#define STM32_CR_PROG			0x00000002	/* PG */
+#define STM32_SR_QW_MASK		0x00000004	/* QW */
+#define STM32_SR_ERROR_MASK		0x1F2E0000	/* DBECCERR | SNECCERR | RDSERR | RDPERR | OPERR
+											   | INCERR | STRBERR | PGSERR | WRPERR */
+
+	.thumb_func
+	.global _start
+_start:
+	ldr		r6, [r0, #4]		/* read rp */
+
+wait_fifo:
+	ldr		r7, [r0, #0]		/* read wp */
+	cbz		r7, exit			/* abort if wp == 0, status = 0 */
+	subs	r7, r7, r6			/* number of bytes available for read in r7 */
+	ittt	mi					/* if wrapped around */
+	addmi	r7, r1				/* add size of buffer */
+	submi	r7, r0
+	submi	r7, #8
+	cmp		r7, r4				/* wait until data buffer is full */
+	bcc		wait_fifo
+
+	mov		r7, #STM32_CR_PROG
+	str		r7, [r5, #STM32_FLASH_CR_OFFSET]
+
+	mov		r8, #4
+	udiv	r8, r4, r8			/* number of words is size of write word divided by 4*/
+write_flash:
+	dsb
+	ldr		r7, [r6], #0x04		/* read one word from src, increment ptr */
+	str		r7, [r2], #0x04		/* write one word to dst, increment ptr */
+	dsb
+	cmp		r6, r1				/* if rp >= end of buffer ... */
+	it		cs
+	addcs	r6, r0, #8			/* ... then wrap at buffer start */
+	subs	r8, r8, #1			/* decrement loop index */
+	bne		write_flash			/* loop if not done */
+
+busy:
+	ldr		r7, [r5, #STM32_FLASH_SR_OFFSET]
+	tst		r7, #STM32_SR_QW_MASK
+	bne		busy				/* operation in progress, wait ... */
+
+	ldr		r7, [r5, #STM32_FLASH_ICR_OFFSET]
+	ldr		r8, =STM32_SR_ERROR_MASK
+	tst		r7, r8
+	bne		error				/* fail... */
+
+	str		r6, [r0, #4]		/* store rp */
+	subs	r3, r3, #1			/* decrement count */
+	bne		wait_fifo			/* loop if not done */
+	b		exit
+
+error:
+	movs	r8, #0
+	str		r8, [r0, #4]		/* set rp = 0 on error */
+
+exit:
+	mov		r0, r7				/* return status in r0 */
+	bkpt	#0x00
+
+	.pool
diff --git a/contrib/loaders/flash/stm32/stm32h7rx.inc b/contrib/loaders/flash/stm32/stm32h7rx.inc
new file mode 100644
index 0000000000..feecab6230
--- /dev/null
+++ b/contrib/loaders/flash/stm32/stm32h7rx.inc
@@ -0,0 +1,8 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
+0x46,0x68,0x07,0x68,0x77,0xb3,0xbf,0x1b,0x42,0xbf,0x7f,0x18,0x3f,0x1a,0x08,0x3f,
+0xa7,0x42,0xf6,0xd3,0x4f,0xf0,0x02,0x07,0x2f,0x61,0x4f,0xf0,0x04,0x08,0xb4,0xfb,
+0xf8,0xf8,0xbf,0xf3,0x4f,0x8f,0x56,0xf8,0x04,0x7b,0x42,0xf8,0x04,0x7b,0xbf,0xf3,
+0x4f,0x8f,0x8e,0x42,0x28,0xbf,0x00,0xf1,0x08,0x06,0xb8,0xf1,0x01,0x08,0xf0,0xd1,
+0x6f,0x69,0x17,0xf0,0x04,0x0f,0xfb,0xd1,0xaf,0x6a,0xdf,0xf8,0x1c,0x80,0x17,0xea,
+0x08,0x0f,0x03,0xd1,0x46,0x60,0x01,0x3b,0xd3,0xd1,0x03,0xe0,0x5f,0xf0,0x00,0x08,
+0xc0,0xf8,0x04,0x80,0x38,0x46,0x00,0xbe,0x00,0x00,0x2e,0x1f,
diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c
index 362b2c2d52..e1c86bd6ec 100644
--- a/src/flash/nor/stm32h7x.c
+++ b/src/flash/nor/stm32h7x.c
@@ -54,6 +54,18 @@ static const uint32_t stm32h7_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
 	[STM32_FLASH_WPSN_PRG_INDEX]	= 0x3C
 };
 
+static const uint32_t stm32h7rs_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
+	[STM32_FLASH_ACR_INDEX]			= 0x00,
+	[STM32_FLASH_KEYR_INDEX]		= 0x04,
+	[STM32_FLASH_OPTKEYR_INDEX]		= 0x100,
+	[STM32_FLASH_SR_INDEX]			= 0x14,
+	[STM32_FLASH_CR_INDEX]			= 0x10,
+	[STM32_FLASH_ICR_INDEX]			= 0x28,
+	[STM32_FLASH_OPTCR_INDEX]		= 0x104,
+	[STM32_FLASH_OPTSR_INDEX]		= 0x10C,
+	[STM32_FLASH_ISR_INDEX]			= 0x24,
+};
+
 /* FLASH_CR register bits */
 #define FLASH_LOCK     (1 << 0)
 #define FLASH_PG       (1 << 1)
@@ -66,6 +78,19 @@ static const uint32_t stm32h7_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
 #define FLASH_FW       (1 << 6)
 #define FLASH_START    (1 << 7)
 
+/* FLASH_ISR register bits for H7RS */
+#define FLASH_CRCRDERRF	(1 << 28) /* CRC read error flag */
+#define FLASH_CRCENDF	(1 << 27) /* CRC end flag */
+#define FLASH_DBECCERRF	(1 << 26) /* ECC double error flag */
+#define FLASH_SNECCERRF	(1 << 25) /* ECC single error flag */
+#define FLASH_RDSERRF	(1 << 24) /* Read security error flag */
+#define FLASH_INCERRF	(1 << 21) /* Inconsistency error flag */
+#define FLASH_OBLERRF	(1 << 20) /* Option byte loading error flag */
+#define FLASH_STRBERRF	(1 << 19) /* Strobe error flag */
+#define FLASH_PGSERRF	(1 << 18) /* Programming sequence error flag */
+#define FLASH_WRPERRF	(1 << 17) /* Write protection error flag */
+#define FLASH_EOPF		(1 << 16) /* End-of-program flag */
+
 /* FLASH_SR register bits */
 #define FLASH_BSY      (1 << 0)  /* Operation in progress */
 #define FLASH_QW       (1 << 2)  /* Operation queue in progress */
@@ -81,6 +106,9 @@ static const uint32_t stm32h7_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
 
 #define FLASH_ERROR (FLASH_WRPERR | FLASH_PGSERR | FLASH_STRBERR | FLASH_INCERR | FLASH_OPERR | \
 					 FLASH_RDPERR | FLASH_RDSERR | FLASH_SNECCERR | FLASH_DBECCERR)
+/* Possible errors for H7RS */
+#define FLASH_ERROR_H7RS (FLASH_CRCRDERRF | FLASH_CRCENDF | FLASH_DBECCERRF | FLASH_SNECCERRF| FLASH_RDSERRF | \
+					 FLASH_INCERRF | FLASH_OBLERRF | FLASH_STRBERRF | FLASH_PGSERRF | FLASH_WRPERRF | FLASH_EOPF)
 
 /* FLASH_OPTCR register bits */
 #define OPT_LOCK       (1 << 0)
@@ -113,6 +141,7 @@ static const uint32_t stm32h7_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
 #define DEVID_STM32H74_H75XX    0x450
 #define DEVID_STM32H7A_H7BXX    0x480
 #define DEVID_STM32H72_H73XX    0x483
+#define DEVID_STM32H7R_H7SXX	0x485
 
 struct stm32h7_rev {
 	uint16_t rev;
@@ -167,12 +196,16 @@ static const struct stm32h7_rev stm32h72_h73xx_revs[] = {
 	{ 0x1000, "A" }, { 0x1001, "Z" },
 };
 
+static const struct stm32h7_rev stm32h7r_h7sxx_revs[] = {
+	{ 0x1000, "A" }, { 0x2000, "B" },
+};
+
 static uint32_t stm32h74_h75xx_compute_flash_cr(uint32_t cmd, int snb)
 {
 	return cmd | (snb << 8);
 }
 
-static uint32_t stm32h7a_h7bxx_compute_flash_cr(uint32_t cmd, int snb)
+static uint32_t stm32h7a_h7b_h7r_h7sxx_compute_flash_cr(uint32_t cmd, int snb)
 {
 	/* save FW and START bits, to be right shifted by 2 bits later */
 	const uint32_t tmp = cmd & (FLASH_FW | FLASH_START);
@@ -184,6 +217,7 @@ static uint32_t stm32h7a_h7bxx_compute_flash_cr(uint32_t cmd, int snb)
 }
 
 static inline int stm32h7_get_flash_status(struct flash_bank *bank, uint32_t *status);
+static inline int stm32h7rs_get_flash_status(struct flash_bank *bank, uint32_t *status);
 
 static const struct stm32h7_part_info stm32h7_parts[] = {
 	{
@@ -215,7 +249,7 @@ static const struct stm32h7_part_info stm32h7_parts[] = {
 	.fsize_addr			    = 0x08FFF80C,
 	.wps_group_size		    = 4,
 	.wps_mask			    = 0xFFFFFFFF,
-	.compute_flash_cr	    = stm32h7a_h7bxx_compute_flash_cr,
+	.compute_flash_cr	    = stm32h7a_h7b_h7r_h7sxx_compute_flash_cr,
 	.get_flash_error_status = stm32h7_get_flash_status,
 	},
 	{
@@ -234,6 +268,22 @@ static const struct stm32h7_part_info stm32h7_parts[] = {
 	.compute_flash_cr       = stm32h74_h75xx_compute_flash_cr,
 	.get_flash_error_status = stm32h7_get_flash_status,
 	},
+	{
+	.id						= DEVID_STM32H7R_H7SXX,
+	.revs					= stm32h7r_h7sxx_revs,
+	.num_revs				= ARRAY_SIZE(stm32h7r_h7sxx_revs),
+	.device_str				= "STM32H7Rx/7Sx",
+	.page_size_kb			= 8,
+	.block_size				= 16,
+	.max_flash_size_kb		= 64,
+	.max_bank_size_kb		= 64,
+	.has_dual_bank			= false,
+	.fsize_addr				= 0x08FFF80C,
+	.wps_group_size			= 1,
+	.wps_mask				= 0xFF,
+	.compute_flash_cr		= stm32h7a_h7b_h7r_h7sxx_compute_flash_cr,
+	.get_flash_error_status	= stm32h7rs_get_flash_status,
+	},
 };
 
 /* flash bank stm32x <base> <size> 0 0 <target#> */
@@ -301,10 +351,19 @@ static inline int stm32h7_get_flash_status(struct flash_bank *bank, uint32_t *st
 	return stm32h7_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, status);
 }
 
+static inline int stm32h7rs_get_flash_status(struct flash_bank *bank, uint32_t *status)
+{
+	return stm32h7_read_flash_reg_by_index(bank, STM32_FLASH_ISR_INDEX, status);
+}
+
 static int stm32h7_wait_flash_op_queue(struct flash_bank *bank, int timeout)
 {
 	uint32_t status;
 	int retval;
+	struct stm32h7_flash_bank *stm32h7_info = bank->driver_priv;
+	uint32_t device_id = stm32h7_info->idcode & 0xFFF;
+	int flash_clear_status_index;
+	uint32_t flash_error;
 
 	/* wait for flash operations completion */
 	for (;;) {
@@ -322,17 +381,26 @@ static int stm32h7_wait_flash_op_queue(struct flash_bank *bank, int timeout)
 		alive_sleep(1);
 	}
 
+	if (device_id == DEVID_STM32H7R_H7SXX) {
+			flash_error = FLASH_ERROR_H7RS;
+			flash_clear_status_index = STM32_FLASH_ICR_INDEX;
+
+	} else {
+			flash_error = FLASH_ERROR;
+			flash_clear_status_index = STM32_FLASH_CCR_INDEX;
+	}
+
 	if (status & FLASH_WRPERR) {
-		LOG_ERROR("wait_flash_op_queue, WRPERR detected");
+		LOG_ERROR("wait_flash_op_queue, write protection error");
 		retval = ERROR_FAIL;
 	}
 
 	/* Clear error + EOP flags but report errors */
-	if (status & FLASH_ERROR) {
+	if (status & flash_error) {
 		if (retval == ERROR_OK)
 			retval = ERROR_FAIL;
 		/* If this operation fails, we ignore it and report the original retval */
-		stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_CCR_INDEX, status);
+		stm32h7_write_flash_reg_by_index(bank, flash_clear_status_index, status);
 	}
 	return retval;
 }
@@ -597,6 +665,9 @@ static int stm32h7_write_block(struct flash_bank *bank, const uint8_t *buffer,
 {
 	struct target *target = bank->target;
 	struct stm32h7_flash_bank *stm32h7_info = bank->driver_priv;
+	uint32_t device_id = stm32h7_info->idcode & 0XFFF;
+	int flash_clear_status_index;
+	uint32_t flash_error;
 	/*
 	 * If the size of the data part of the buffer is not a multiple of .block_size, we get
 	 * "corrupted fifo read" pointer in target_run_flash_async_algorithm()
@@ -614,18 +685,38 @@ static int stm32h7_write_block(struct flash_bank *bank, const uint8_t *buffer,
 #include "../../../contrib/loaders/flash/stm32/stm32h7x.inc"
 	};
 
-	if (target_alloc_working_area(target, sizeof(stm32h7_flash_write_code),
+	static const uint8_t stm32h7rs_flash_write_code[] = {
+#include "../../../contrib/loaders/flash/stm32/stm32h7rx.inc"
+	};
+
+	if (device_id == DEVID_STM32H7R_H7SXX) {
+		if (target_alloc_working_area(target, sizeof(stm32h7rs_flash_write_code),
 			&write_algorithm) != ERROR_OK) {
-		LOG_WARNING("no working area available, can't do block memory writes");
-		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
-	}
+			LOG_WARNING("no working area available, can't do block memory writes");
+			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+		}
 
-	retval = target_write_buffer(target, write_algorithm->address,
-			sizeof(stm32h7_flash_write_code),
-			stm32h7_flash_write_code);
-	if (retval != ERROR_OK) {
-		target_free_working_area(target, write_algorithm);
-		return retval;
+		retval = target_write_buffer(target, write_algorithm->address,
+				sizeof(stm32h7rs_flash_write_code),
+				stm32h7rs_flash_write_code);
+		if (retval != ERROR_OK) {
+			target_free_working_area(target, write_algorithm);
+			return retval;
+		}
+	} else {
+		if (target_alloc_working_area(target, sizeof(stm32h7_flash_write_code),
+				&write_algorithm) != ERROR_OK) {
+			LOG_WARNING("no working area available, can't do block memory writes");
+			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+		}
+
+		retval = target_write_buffer(target, write_algorithm->address,
+				sizeof(stm32h7_flash_write_code),
+				stm32h7_flash_write_code);
+		if (retval != ERROR_OK) {
+			target_free_working_area(target, write_algorithm);
+			return retval;
+		}
 	}
 
 	/* memory buffer */
@@ -676,13 +767,22 @@ static int stm32h7_write_block(struct flash_bank *bank, const uint8_t *buffer,
 
 		uint32_t flash_sr = buf_get_u32(reg_params[0].value, 0, 32);
 
+		if (device_id == DEVID_STM32H7R_H7SXX) {
+			flash_error = FLASH_ERROR_H7RS;
+			flash_clear_status_index = STM32_FLASH_ICR_INDEX;
+
+		} else {
+			flash_error = FLASH_ERROR;
+			flash_clear_status_index = STM32_FLASH_CCR_INDEX;
+		}
+
 		if (flash_sr & FLASH_WRPERR)
 			LOG_ERROR("flash memory write protected");
 
-		if ((flash_sr & FLASH_ERROR) != 0) {
-			LOG_ERROR("flash write failed, FLASH_SR = 0x%08" PRIx32, flash_sr);
+		if ((flash_sr & flash_error) != 0) {
+			LOG_ERROR("flash write failed, status = 0x%08" PRIx32, flash_sr);
 			/* Clear error + EOP flags but report errors */
-			stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_CCR_INDEX, flash_sr);
+			stm32h7_write_flash_reg_by_index(bank, flash_clear_status_index, flash_sr);
 			retval = ERROR_FAIL;
 		}
 	}
@@ -809,8 +909,11 @@ static int stm32h7_probe(struct flash_bank *bank)
 	LOG_DEBUG("device id = 0x%08" PRIx32, stm32h7_info->idcode);
 
 	device_id = stm32h7_info->idcode & 0xfff;
-
-	stm32h7_info->flash_regs = stm32h7_flash_regs;
+	if (device_id == DEVID_STM32H7R_H7SXX) {
+		stm32h7_info->flash_regs = stm32h7rs_flash_regs;
+	} else {
+		stm32h7_info->flash_regs = stm32h7_flash_regs;
+	}
 
 	for (unsigned int n = 0; n < ARRAY_SIZE(stm32h7_parts); n++) {
 		if (device_id == stm32h7_parts[n].id)
@@ -871,6 +974,7 @@ static int stm32h7_probe(struct flash_bank *bank)
 			flash_size_in_kb /= 2;
 		break;
 	case DEVID_STM32H72_H73XX:
+	case DEVID_STM32H7R_H7SXX:
 		break;
 	default:
 		LOG_ERROR("unsupported device");
diff --git a/tcl/target/stm32h7rx.cfg b/tcl/target/stm32h7rx.cfg
new file mode 100644
index 0000000000..d584723f36
--- /dev/null
+++ b/tcl/target/stm32h7rx.cfg
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32h7x family
+
+#
+# stm32h7 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32h7x
+}
+
+# Issue a warning when hla is used, and fallback to single core configuration
+if { [using_hla] } {
+	echo "Error : hla does not support multicore debugging"
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+	  set _CPUTAPID 0x6ba00477
+   } {
+      set _CPUTAPID 0x6ba02477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+target create $_CHIPNAME.ap0 mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 1
+# test ram area
+$_CHIPNAME.cpu0 configure -work-area-phys 0x24000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0
+
+# Make sure that cpu0 is selected
+targets $_CHIPNAME.cpu0
+
+# Clock after reset is HSI at 64 MHz, no need of PLL
+adapter speed 1800
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+# use hardware reset
+#
+# The STM32H7 does not support connect_assert_srst mode because the AXI is
+# unavailable while SRST is asserted, and that is used to access the DBGMCU
+# component at 0x5C001000 in the examine-end event handler.
+#
+# It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead
+# of the default AP0, and that works with SRST asserted; however, nonzero AP
+# usage does not work with HLA, so is not done by default. That change could be
+# made in a local configuration file if connect_assert_srst mode is needed for
+# a specific application and a non-HLA adapter is in use.
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+	$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
+
+   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+   # makes the data access cacheable. This allows reading and writing data in the
+   # CPU cache from the debugger, which is far more useful than going straight to
+   # RAM when operating on typical variables, and is generally no worse when
+   # operating on special memory locations.
+   $_CHIPNAME.dap apcsw 0x08000000 0x08000000
+}
+
+$_CHIPNAME.cpu0 configure -event examine-end {
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	stm32h7x_dbgmcu_mmw 0x004 0x00000007 0
+
+	# Enable clock for tracing
+	# DBGMCU_CR |= TRACECLKEN
+	stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
+}
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	# Clock after reset is HSI at 64 MHz, no need of PLL
+	adapter speed 4000
+}
+
+# get _CHIPNAME from current target
+proc stm32h7x_get_chipname {} {
+	set t [target current]
+	set sep [string last "." $t]
+	if {$sep == -1} {
+		return $t
+	}
+	return [string range $t 0 [expr {$sep - 1}]]
+}
+
+# like mrw, but with target selection
+proc stm32h7x_mrw {used_target reg} {
+	return [$used_target read_memory $reg 32 1]
+}
+
+# like mmw, but with target selection
+proc stm32h7x_mmw {used_target reg setbits clearbits} {
+	set old [stm32h7x_mrw $used_target $reg]
+	set new [expr {($old & ~$clearbits) | $setbits}]
+	$used_target mww $reg $new
+}
+
+# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base
+# this procedure will use the mem_ap on AP2 whenever possible
+proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
+	set _CHIPNAME [stm32h7x_get_chipname]
+	set used_target [target current]
+	set reg_addr [expr {0x5C001000 + $reg_offset}]
+
+	stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
+}

-- 

[PATCH]: f2bd8b09b3 flash/stm32h7x: Rename functions and variable names

[<ge...@op...>]

This is an automated email from Gerrit.

"Ahmed Haoues <ahm...@st...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8889

-- gerrit

commit f2bd8b09b385133345b389469f5e074b91c7e0f3
Author: HAOUES Ahmed <ahm...@st...>
Date:   Tue Jul 1 13:54:12 2025 +0100

    flash/stm32h7x: Rename functions and variable names
    
    Prepare support for STM32H7R/S
    Rename methods to follow the STM32l4 driver naming
    
    Change-Id: Iad14ba89a48a63c158dae05a53dcbf92f6fe2f53
    Signed-off-by: HAOUES Ahmed <ahm...@st...>

diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c
index 6ecd265957..362b2c2d52 100644
--- a/src/flash/nor/stm32h7x.c
+++ b/src/flash/nor/stm32h7x.c
@@ -114,18 +114,18 @@ static const uint32_t stm32h7_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
 #define DEVID_STM32H7A_H7BXX    0x480
 #define DEVID_STM32H72_H73XX    0x483
 
-struct stm32h7x_rev {
+struct stm32h7_rev {
 	uint16_t rev;
 	const char *str;
 };
 
-/* stm32h7x_part_info permits the store each device information and specificities.
+/* stm32h7_part_info permits the store each device information and specificities.
  * the default unit is byte unless the suffix '_kb' is used. */
 
-struct stm32h7x_part_info {
+struct stm32h7_part_info {
 	uint16_t id;
 	const char *device_str;
-	const struct stm32h7x_rev *revs;
+	const struct stm32h7_rev *revs;
 	size_t num_revs;
 	unsigned int page_size_kb;
 	unsigned int block_size;    /* flash write word size in bytes */
@@ -140,30 +140,30 @@ struct stm32h7x_part_info {
 	int (*get_flash_error_status)(struct flash_bank *bank, uint32_t *status);
 };
 
-struct stm32h7x_flash_bank {
+struct stm32h7_flash_bank {
 	bool probed;
 	uint32_t idcode;
 	uint32_t user_bank_size;
 	uint32_t flash_regs_base;    /* Address of flash reg controller */
 	const uint32_t *flash_regs;
-	const struct stm32h7x_part_info *part_info;
+	const struct stm32h7_part_info *part_info;
 };
 
-enum stm32h7x_opt_rdp {
+enum stm32h7_opt_rdp {
 	OPT_RDP_L0 = 0xaa,
 	OPT_RDP_L1 = 0x00,
 	OPT_RDP_L2 = 0xcc
 };
 
-static const struct stm32h7x_rev stm32h74_h75xx_revs[] = {
+static const struct stm32h7_rev stm32h74_h75xx_revs[] = {
 	{ 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2001, "X"  }, { 0x2003, "V"  },
 };
 
-static const struct stm32h7x_rev stm32h7a_h7bxx_revs[] = {
+static const struct stm32h7_rev stm32h7a_h7bxx_revs[] = {
 	{ 0x1000, "A"},
 };
 
-static const struct stm32h7x_rev stm32h72_h73xx_revs[] = {
+static const struct stm32h7_rev stm32h72_h73xx_revs[] = {
 	{ 0x1000, "A" }, { 0x1001, "Z" },
 };
 
@@ -183,9 +183,9 @@ static uint32_t stm32h7a_h7bxx_compute_flash_cr(uint32_t cmd, int snb)
 	return cmd | (tmp >> 2) | (snb << 6);
 }
 
-static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status);
+static inline int stm32h7_get_flash_status(struct flash_bank *bank, uint32_t *status);
 
-static const struct stm32h7x_part_info stm32h7x_parts[] = {
+static const struct stm32h7_part_info stm32h7_parts[] = {
 	{
 	.id					    = DEVID_STM32H74_H75XX,
 	.revs				    = stm32h74_h75xx_revs,
@@ -200,7 +200,7 @@ static const struct stm32h7x_part_info stm32h7x_parts[] = {
 	.wps_group_size		    = 1,
 	.wps_mask			    = 0xFF,
 	.compute_flash_cr	    = stm32h74_h75xx_compute_flash_cr,
-	.get_flash_error_status = stm32x_get_flash_status,
+	.get_flash_error_status = stm32h7_get_flash_status,
 	},
 	{
 	.id					    = DEVID_STM32H7A_H7BXX,
@@ -216,7 +216,7 @@ static const struct stm32h7x_part_info stm32h7x_parts[] = {
 	.wps_group_size		    = 4,
 	.wps_mask			    = 0xFFFFFFFF,
 	.compute_flash_cr	    = stm32h7a_h7bxx_compute_flash_cr,
-	.get_flash_error_status = stm32x_get_flash_status,
+	.get_flash_error_status = stm32h7_get_flash_status,
 	},
 	{
 	.id					    = DEVID_STM32H72_H73XX,
@@ -232,37 +232,37 @@ static const struct stm32h7x_part_info stm32h7x_parts[] = {
 	.wps_group_size		    = 1,
 	.wps_mask			    = 0xFF,
 	.compute_flash_cr       = stm32h74_h75xx_compute_flash_cr,
-	.get_flash_error_status = stm32x_get_flash_status,
+	.get_flash_error_status = stm32h7_get_flash_status,
 	},
 };
 
 /* flash bank stm32x <base> <size> 0 0 <target#> */
 
-FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
+FLASH_BANK_COMMAND_HANDLER(stm32h7_flash_bank_command)
 {
-	struct stm32h7x_flash_bank *stm32x_info;
+	struct stm32h7_flash_bank *stm32h7_info;
 
 	if (CMD_ARGC < 6)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	stm32x_info = malloc(sizeof(struct stm32h7x_flash_bank));
-	bank->driver_priv = stm32x_info;
+	stm32h7_info = malloc(sizeof(struct stm32h7_flash_bank));
+	bank->driver_priv = stm32h7_info;
 
-	stm32x_info->probed = false;
-	stm32x_info->user_bank_size = bank->size;
+	stm32h7_info->probed = false;
+	stm32h7_info->user_bank_size = bank->size;
 
 	return ERROR_OK;
 }
 
-static inline uint32_t stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
+static inline uint32_t stm32h7_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
 {
-	struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
-	return reg_offset + stm32x_info->flash_regs_base;
+	struct stm32h7_flash_bank *stm32h7_info = bank->driver_priv;
+	return reg_offset + stm32h7_info->flash_regs_base;
 }
 
-static inline int stm32x_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
+static inline int stm32h7_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
 {
-	uint32_t reg_addr = stm32x_get_flash_reg(bank, reg_offset);
+	uint32_t reg_addr = stm32h7_get_flash_reg(bank, reg_offset);
 	int retval = target_read_u32(bank->target, reg_addr, value);
 
 	if (retval != ERROR_OK)
@@ -271,16 +271,16 @@ static inline int stm32x_read_flash_reg(struct flash_bank *bank, uint32_t reg_of
 	return retval;
 }
 
-static inline int stm32x_read_flash_reg_by_index(struct flash_bank *bank,
+static inline int stm32h7_read_flash_reg_by_index(struct flash_bank *bank,
 	enum stm32h7_flash_reg_index reg_index, uint32_t *value)
 {
-	struct stm32h7x_flash_bank *stm32h7_info = bank->driver_priv;
-	return stm32x_read_flash_reg(bank, stm32h7_info->flash_regs[reg_index], value);
+	struct stm32h7_flash_bank *stm32h7_info = bank->driver_priv;
+	return stm32h7_read_flash_reg(bank, stm32h7_info->flash_regs[reg_index], value);
 }
 
-static inline int stm32x_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
+static inline int stm32h7_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
 {
-	uint32_t reg_addr = stm32x_get_flash_reg(bank, reg_offset);
+	uint32_t reg_addr = stm32h7_get_flash_reg(bank, reg_offset);
 	int retval = target_write_u32(bank->target, reg_addr, value);
 
 	if (retval != ERROR_OK)
@@ -289,26 +289,26 @@ static inline int stm32x_write_flash_reg(struct flash_bank *bank, uint32_t reg_o
 	return retval;
 }
 
-static inline int stm32x_write_flash_reg_by_index(struct flash_bank *bank,
+static inline int stm32h7_write_flash_reg_by_index(struct flash_bank *bank,
 	enum stm32h7_flash_reg_index reg_index, uint32_t value)
 {
-	struct stm32h7x_flash_bank *stm32h7_info = bank->driver_priv;
-	return stm32x_write_flash_reg(bank, stm32h7_info->flash_regs[reg_index], value);
+	struct stm32h7_flash_bank *stm32h7_info = bank->driver_priv;
+	return stm32h7_write_flash_reg(bank, stm32h7_info->flash_regs[reg_index], value);
 }
 
-static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
+static inline int stm32h7_get_flash_status(struct flash_bank *bank, uint32_t *status)
 {
-	return stm32x_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, status);
+	return stm32h7_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, status);
 }
 
-static int stm32x_wait_flash_op_queue(struct flash_bank *bank, int timeout)
+static int stm32h7_wait_flash_op_queue(struct flash_bank *bank, int timeout)
 {
 	uint32_t status;
 	int retval;
 
 	/* wait for flash operations completion */
 	for (;;) {
-		retval = stm32x_get_flash_status(bank, &status);
+		retval = stm32h7_get_flash_status(bank, &status);
 		if (retval != ERROR_OK)
 			return retval;
 
@@ -332,19 +332,19 @@ static int stm32x_wait_flash_op_queue(struct flash_bank *bank, int timeout)
 		if (retval == ERROR_OK)
 			retval = ERROR_FAIL;
 		/* If this operation fails, we ignore it and report the original retval */
-		stm32x_write_flash_reg_by_index(bank, STM32_FLASH_CCR_INDEX, status);
+		stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_CCR_INDEX, status);
 	}
 	return retval;
 }
 
-static int stm32x_unlock_reg(struct flash_bank *bank)
+static int stm32h7_unlock_reg(struct flash_bank *bank)
 {
 	uint32_t ctrl;
 
 	/* first check if not already unlocked
 	 * otherwise writing on FLASH_KEYR will fail
 	 */
-	int retval = stm32x_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
+	int retval = stm32h7_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -352,15 +352,15 @@ static int stm32x_unlock_reg(struct flash_bank *bank)
 		return ERROR_OK;
 
 	/* unlock flash registers for bank */
-	retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY1);
+	retval = stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY1);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY2);
+	retval = stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY2);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = stm32x_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
+	retval = stm32h7_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -371,11 +371,11 @@ static int stm32x_unlock_reg(struct flash_bank *bank)
 	return ERROR_OK;
 }
 
-static int stm32x_unlock_option_reg(struct flash_bank *bank)
+static int stm32h7_unlock_option_reg(struct flash_bank *bank)
 {
 	uint32_t ctrl;
 
-	int retval = stm32x_read_flash_reg_by_index(bank, STM32_FLASH_OPTCR_INDEX, &ctrl);
+	int retval = stm32h7_read_flash_reg_by_index(bank, STM32_FLASH_OPTCR_INDEX, &ctrl);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -383,15 +383,15 @@ static int stm32x_unlock_option_reg(struct flash_bank *bank)
 		return ERROR_OK;
 
 	/* unlock option registers */
-	retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY1);
+	retval = stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY1);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY2);
+	retval = stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY2);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = stm32x_read_flash_reg_by_index(bank, STM32_FLASH_OPTCR_INDEX, &ctrl);
+	retval = stm32h7_read_flash_reg_by_index(bank, STM32_FLASH_OPTCR_INDEX, &ctrl);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -403,37 +403,37 @@ static int stm32x_unlock_option_reg(struct flash_bank *bank)
 	return ERROR_OK;
 }
 
-static inline int stm32x_lock_reg(struct flash_bank *bank)
+static inline int stm32h7_lock_reg(struct flash_bank *bank)
 {
-	return stm32x_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
+	return stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
 }
 
-static inline int stm32x_lock_option_reg(struct flash_bank *bank)
+static inline int stm32h7_lock_option_reg(struct flash_bank *bank)
 {
-	return stm32x_write_flash_reg_by_index(bank, STM32_FLASH_OPTCR_INDEX, OPT_LOCK);
+	return stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_OPTCR_INDEX, OPT_LOCK);
 }
 
-static int stm32x_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
+static int stm32h7_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
 {
 	int retval, retval2;
 
 	/* unlock option bytes for modification */
-	retval = stm32x_unlock_option_reg(bank);
+	retval = stm32h7_unlock_option_reg(bank);
 	if (retval != ERROR_OK)
 		goto flash_options_lock;
 
 	/* write option bytes */
-	retval = stm32x_write_flash_reg_by_index(bank, reg_offset, value);
+	retval = stm32h7_write_flash_reg_by_index(bank, reg_offset, value);
 	if (retval != ERROR_OK)
 		goto flash_options_lock;
 
 	/* Remove OPT error flag before programming */
-	retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_OPTCCR_INDEX, OPT_CLR_OPTCHANGEERR);
+	retval = stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_OPTCCR_INDEX, OPT_CLR_OPTCHANGEERR);
 	if (retval != ERROR_OK)
 		goto flash_options_lock;
 
 	/* start programming cycle */
-	retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_OPTCR_INDEX, OPT_START);
+	retval = stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_OPTCR_INDEX, OPT_START);
 	if (retval != ERROR_OK)
 		goto flash_options_lock;
 
@@ -441,9 +441,9 @@ static int stm32x_write_option(struct flash_bank *bank, uint32_t reg_offset, uin
 	int timeout = FLASH_ERASE_TIMEOUT;
 	uint32_t status;
 	for (;;) {
-		retval = stm32x_read_flash_reg_by_index(bank, STM32_FLASH_OPTSR_CUR_INDEX, &status);
+		retval = stm32h7_read_flash_reg_by_index(bank, STM32_FLASH_OPTSR_CUR_INDEX, &status);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("stm32x_options_program: failed to read FLASH_OPTSR_CUR");
+			LOG_ERROR("stm32h7_options_program: failed to read FLASH_OPTSR_CUR");
 			goto flash_options_lock;
 		}
 		if ((status & OPT_BSY) == 0)
@@ -464,32 +464,32 @@ static int stm32x_write_option(struct flash_bank *bank, uint32_t reg_offset, uin
 	}
 
 flash_options_lock:
-	retval2 = stm32x_lock_option_reg(bank);
+	retval2 = stm32h7_lock_option_reg(bank);
 	if (retval2 != ERROR_OK)
 		LOG_ERROR("error during the lock of flash options");
 
 	return (retval == ERROR_OK) ? retval2 : retval;
 }
 
-static int stm32x_modify_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
+static int stm32h7_modify_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
 {
 	uint32_t data;
 
-	int retval = stm32x_read_flash_reg_by_index(bank, reg_offset, &data);
+	int retval = stm32h7_read_flash_reg_by_index(bank, reg_offset, &data);
 	if (retval != ERROR_OK)
 		return retval;
 
 	data = (data & ~mask) | (value & mask);
 
-	return stm32x_write_option(bank, reg_offset, data);
+	return stm32h7_write_option(bank, reg_offset, data);
 }
 
-static int stm32x_protect_check(struct flash_bank *bank)
+static int stm32h7_protect_check(struct flash_bank *bank)
 {
 	uint32_t protection;
 
 	/* read 'write protection' settings */
-	int retval = stm32x_read_flash_reg_by_index(bank, STM32_FLASH_WPSN_CUR_INDEX, &protection);
+	int retval = stm32h7_read_flash_reg_by_index(bank, STM32_FLASH_WPSN_CUR_INDEX, &protection);
 	if (retval != ERROR_OK) {
 		LOG_DEBUG("unable to read WPSN_CUR register");
 		return retval;
@@ -501,10 +501,10 @@ static int stm32x_protect_check(struct flash_bank *bank)
 	return ERROR_OK;
 }
 
-static int stm32x_erase(struct flash_bank *bank, unsigned int first,
+static int stm32h7_erase(struct flash_bank *bank, unsigned int first,
 		unsigned int last)
 {
-	struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
+	struct stm32h7_flash_bank *stm32h7_info = bank->driver_priv;
 	int retval, retval2;
 
 	assert(first < bank->num_sectors);
@@ -513,7 +513,7 @@ static int stm32x_erase(struct flash_bank *bank, unsigned int first,
 	if (bank->target->state != TARGET_HALTED)
 		return ERROR_TARGET_NOT_HALTED;
 
-	retval = stm32x_unlock_reg(bank);
+	retval = stm32h7_unlock_reg(bank);
 	if (retval != ERROR_OK)
 		goto flash_lock;
 
@@ -529,19 +529,19 @@ static int stm32x_erase(struct flash_bank *bank, unsigned int first,
 	 */
 	for (unsigned int i = first; i <= last; i++) {
 		LOG_DEBUG("erase sector %u", i);
-		retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX,
-				stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64, i));
+		retval = stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX,
+				stm32h7_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64, i));
 		if (retval != ERROR_OK) {
 			LOG_ERROR("Error erase sector %u", i);
 			goto flash_lock;
 		}
-		retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX,
-				stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64 | FLASH_START, i));
+		retval = stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX,
+				stm32h7_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64 | FLASH_START, i));
 		if (retval != ERROR_OK) {
 			LOG_ERROR("Error erase sector %u", i);
 			goto flash_lock;
 		}
-		retval = stm32x_wait_flash_op_queue(bank, FLASH_ERASE_TIMEOUT);
+		retval = stm32h7_wait_flash_op_queue(bank, FLASH_ERASE_TIMEOUT);
 
 		if (retval != ERROR_OK) {
 			LOG_ERROR("erase time-out or operation error sector %u", i);
@@ -550,18 +550,18 @@ static int stm32x_erase(struct flash_bank *bank, unsigned int first,
 	}
 
 flash_lock:
-	retval2 = stm32x_lock_reg(bank);
+	retval2 = stm32h7_lock_reg(bank);
 	if (retval2 != ERROR_OK)
 		LOG_ERROR("error during the lock of flash");
 
 	return (retval == ERROR_OK) ? retval2 : retval;
 }
 
-static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
+static int stm32h7_protect(struct flash_bank *bank, int set, unsigned int first,
 		unsigned int last)
 {
 	struct target *target = bank->target;
-	struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
+	struct stm32h7_flash_bank *stm32h7_info = bank->driver_priv;
 	uint32_t protection;
 
 	if (target->state != TARGET_HALTED) {
@@ -570,7 +570,7 @@ static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
 	}
 
 	/* read 'write protection' settings */
-	int retval = stm32x_read_flash_reg_by_index(bank, STM32_FLASH_WPSN_CUR_INDEX, &protection);
+	int retval = stm32h7_read_flash_reg_by_index(bank, STM32_FLASH_WPSN_CUR_INDEX, &protection);
 	if (retval != ERROR_OK) {
 		LOG_DEBUG("unable to read WPSN_CUR register");
 		return retval;
@@ -584,24 +584,24 @@ static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
 	}
 
 	/* apply WRPSN mask */
-	protection &= stm32x_info->part_info->wps_mask;
+	protection &= stm32h7_info->part_info->wps_mask;
 
-	LOG_DEBUG("stm32x_protect, option_bytes written WPSN 0x%" PRIx32, protection);
+	LOG_DEBUG("stm32h7_protect, option_bytes written WPSN 0x%" PRIx32, protection);
 
 	/* apply new option value */
-	return stm32x_write_option(bank, STM32_FLASH_WPSN_PRG_INDEX, protection);
+	return stm32h7_write_option(bank, STM32_FLASH_WPSN_PRG_INDEX, protection);
 }
 
-static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
+static int stm32h7_write_block(struct flash_bank *bank, const uint8_t *buffer,
 		uint32_t offset, uint32_t count)
 {
 	struct target *target = bank->target;
-	struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
+	struct stm32h7_flash_bank *stm32h7_info = bank->driver_priv;
 	/*
 	 * If the size of the data part of the buffer is not a multiple of .block_size, we get
 	 * "corrupted fifo read" pointer in target_run_flash_async_algorithm()
 	 */
-	uint32_t data_size = 512 * stm32x_info->part_info->block_size;
+	uint32_t data_size = 512 * stm32h7_info->part_info->block_size;
 	uint32_t buffer_size = 8 + data_size;
 	struct working_area *write_algorithm;
 	struct working_area *source;
@@ -610,19 +610,19 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 	struct armv7m_algorithm armv7m_info;
 	int retval = ERROR_OK;
 
-	static const uint8_t stm32x_flash_write_code[] = {
+	static const uint8_t stm32h7_flash_write_code[] = {
 #include "../../../contrib/loaders/flash/stm32/stm32h7x.inc"
 	};
 
-	if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
+	if (target_alloc_working_area(target, sizeof(stm32h7_flash_write_code),
 			&write_algorithm) != ERROR_OK) {
 		LOG_WARNING("no working area available, can't do block memory writes");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
 	retval = target_write_buffer(target, write_algorithm->address,
-			sizeof(stm32x_flash_write_code),
-			stm32x_flash_write_code);
+			sizeof(stm32h7_flash_write_code),
+			stm32h7_flash_write_code);
 	if (retval != ERROR_OK) {
 		target_free_working_area(target, write_algorithm);
 		return retval;
@@ -658,13 +658,13 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 	buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
 	buf_set_u32(reg_params[2].value, 0, 32, address);
 	buf_set_u32(reg_params[3].value, 0, 32, count);
-	buf_set_u32(reg_params[4].value, 0, 32, stm32x_info->part_info->block_size);
-	buf_set_u32(reg_params[5].value, 0, 32, stm32x_info->flash_regs_base);
+	buf_set_u32(reg_params[4].value, 0, 32, stm32h7_info->part_info->block_size);
+	buf_set_u32(reg_params[5].value, 0, 32, stm32h7_info->flash_regs_base);
 
 	retval = target_run_flash_async_algorithm(target,
 						  buffer,
 						  count,
-						  stm32x_info->part_info->block_size,
+						  stm32h7_info->part_info->block_size,
 						  0, NULL,
 						  ARRAY_SIZE(reg_params), reg_params,
 						  source->address, source->size,
@@ -672,7 +672,7 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 						  &armv7m_info);
 
 	if (retval == ERROR_FLASH_OPERATION_FAILED) {
-		LOG_ERROR("error executing stm32h7x flash write algorithm");
+		LOG_ERROR("error executing stm32h7 flash write algorithm");
 
 		uint32_t flash_sr = buf_get_u32(reg_params[0].value, 0, 32);
 
@@ -682,7 +682,7 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 		if ((flash_sr & FLASH_ERROR) != 0) {
 			LOG_ERROR("flash write failed, FLASH_SR = 0x%08" PRIx32, flash_sr);
 			/* Clear error + EOP flags but report errors */
-			stm32x_write_flash_reg_by_index(bank, STM32_FLASH_CCR_INDEX, flash_sr);
+			stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_CCR_INDEX, flash_sr);
 			retval = ERROR_FAIL;
 		}
 	}
@@ -699,11 +699,11 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 	return retval;
 }
 
-static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
+static int stm32h7_write(struct flash_bank *bank, const uint8_t *buffer,
 		uint32_t offset, uint32_t count)
 {
 	struct target *target = bank->target;
-	struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
+	struct stm32h7_flash_bank *stm32h7_info = bank->driver_priv;
 	uint32_t address = bank->base + offset;
 	int retval, retval2;
 
@@ -713,20 +713,20 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 	}
 
 	/* should be enforced via bank->write_start_alignment */
-	assert(!(offset % stm32x_info->part_info->block_size));
+	assert(!(offset % stm32h7_info->part_info->block_size));
 
 	/* should be enforced via bank->write_end_alignment */
-	assert(!(count % stm32x_info->part_info->block_size));
+	assert(!(count % stm32h7_info->part_info->block_size));
 
-	retval = stm32x_unlock_reg(bank);
+	retval = stm32h7_unlock_reg(bank);
 	if (retval != ERROR_OK)
 		goto flash_lock;
 
-	uint32_t blocks_remaining = count / stm32x_info->part_info->block_size;
+	uint32_t blocks_remaining = count / stm32h7_info->part_info->block_size;
 
 	/* multiple words (n * .block_size) to be programmed in block */
 	if (blocks_remaining) {
-		retval = stm32x_write_block(bank, buffer, offset, blocks_remaining);
+		retval = stm32h7_write_block(bank, buffer, offset, blocks_remaining);
 		if (retval != ERROR_OK) {
 			if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 				/* if block write failed (no sufficient working area),
@@ -734,8 +734,8 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 				LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 			}
 		} else {
-			buffer += blocks_remaining * stm32x_info->part_info->block_size;
-			address += blocks_remaining * stm32x_info->part_info->block_size;
+			buffer += blocks_remaining * stm32h7_info->part_info->block_size;
+			address += blocks_remaining * stm32h7_info->part_info->block_size;
 			blocks_remaining = 0;
 		}
 		if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
@@ -752,33 +752,33 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 	4. Wait for flash operations completion
 	*/
 	while (blocks_remaining > 0) {
-		retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX,
-				stm32x_info->part_info->compute_flash_cr(FLASH_PG | FLASH_PSIZE_64, 0));
+		retval = stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX,
+				stm32h7_info->part_info->compute_flash_cr(FLASH_PG | FLASH_PSIZE_64, 0));
 		if (retval != ERROR_OK)
 			goto flash_lock;
 
-		retval = target_write_buffer(target, address, stm32x_info->part_info->block_size, buffer);
+		retval = target_write_buffer(target, address, stm32h7_info->part_info->block_size, buffer);
 		if (retval != ERROR_OK)
 			goto flash_lock;
 
-		retval = stm32x_wait_flash_op_queue(bank, FLASH_WRITE_TIMEOUT);
+		retval = stm32h7_wait_flash_op_queue(bank, FLASH_WRITE_TIMEOUT);
 		if (retval != ERROR_OK)
 			goto flash_lock;
 
-		buffer += stm32x_info->part_info->block_size;
-		address += stm32x_info->part_info->block_size;
+		buffer += stm32h7_info->part_info->block_size;
+		address += stm32h7_info->part_info->block_size;
 		blocks_remaining--;
 	}
 
 flash_lock:
-	retval2 = stm32x_lock_reg(bank);
+	retval2 = stm32h7_lock_reg(bank);
 	if (retval2 != ERROR_OK)
 		LOG_ERROR("error during the lock of flash");
 
 	return (retval == ERROR_OK) ? retval2 : retval;
 }
 
-static int stm32x_read_id_code(struct flash_bank *bank, uint32_t *id)
+static int stm32h7_read_id_code(struct flash_bank *bank, uint32_t *id)
 {
 	/* read stm32 device id register */
 	int retval = target_read_u32(bank->target, DBGMCU_IDCODE_REGISTER, id);
@@ -787,52 +787,52 @@ static int stm32x_read_id_code(struct flash_bank *bank, uint32_t *id)
 	return ERROR_OK;
 }
 
-static int stm32x_probe(struct flash_bank *bank)
+static int stm32h7_probe(struct flash_bank *bank)
 {
 	struct target *target = bank->target;
-	struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
+	struct stm32h7_flash_bank *stm32h7_info = bank->driver_priv;
 	uint16_t flash_size_in_kb;
 	uint32_t device_id;
 
-	stm32x_info->probed = false;
-	stm32x_info->part_info = NULL;
+	stm32h7_info->probed = false;
+	stm32h7_info->part_info = NULL;
 
 	if (!target_was_examined(target)) {
 		LOG_ERROR("Target not examined yet");
 		return ERROR_TARGET_NOT_EXAMINED;
 	}
 
-	int retval = stm32x_read_id_code(bank, &stm32x_info->idcode);
+	int retval = stm32h7_read_id_code(bank, &stm32h7_info->idcode);
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_DEBUG("device id = 0x%08" PRIx32, stm32x_info->idcode);
+	LOG_DEBUG("device id = 0x%08" PRIx32, stm32h7_info->idcode);
 
-	device_id = stm32x_info->idcode & 0xfff;
+	device_id = stm32h7_info->idcode & 0xfff;
 
-	stm32x_info->flash_regs = stm32h7_flash_regs;
+	stm32h7_info->flash_regs = stm32h7_flash_regs;
 
-	for (unsigned int n = 0; n < ARRAY_SIZE(stm32h7x_parts); n++) {
-		if (device_id == stm32h7x_parts[n].id)
-			stm32x_info->part_info = &stm32h7x_parts[n];
+	for (unsigned int n = 0; n < ARRAY_SIZE(stm32h7_parts); n++) {
+		if (device_id == stm32h7_parts[n].id)
+			stm32h7_info->part_info = &stm32h7_parts[n];
 	}
-	if (!stm32x_info->part_info) {
+	if (!stm32h7_info->part_info) {
 		LOG_WARNING("Cannot identify target as a STM32H7xx family.");
 		return ERROR_FAIL;
 	} else {
-		LOG_INFO("Device: %s", stm32x_info->part_info->device_str);
+		LOG_INFO("Device: %s", stm32h7_info->part_info->device_str);
 	}
 
 	/* update the address of controller */
 	if (bank->base == FLASH_BANK0_ADDRESS)
-		stm32x_info->flash_regs_base = FLASH_REG_BASE_B0;
+		stm32h7_info->flash_regs_base = FLASH_REG_BASE_B0;
 	else if (bank->base == FLASH_BANK1_ADDRESS)
-		stm32x_info->flash_regs_base = FLASH_REG_BASE_B1;
+		stm32h7_info->flash_regs_base = FLASH_REG_BASE_B1;
 	else {
 		LOG_WARNING("Flash register base not defined for bank %u", bank->bank_number);
 		return ERROR_FAIL;
 	}
-	LOG_DEBUG("flash_regs_base: 0x%" PRIx32, stm32x_info->flash_regs_base);
+	LOG_DEBUG("flash_regs_base: 0x%" PRIx32, stm32h7_info->flash_regs_base);
 
 	/* get flash size from target */
 	/* STM32H74x/H75x, the second core (Cortex-M4) cannot read the flash size */
@@ -841,19 +841,19 @@ static int stm32x_probe(struct flash_bank *bank)
 			&& cortex_m_get_impl_part(target) == CORTEX_M4_PARTNO)
 		LOG_WARNING("%s cannot read the flash size register", target_name(target));
 	else
-		retval = target_read_u16(target, stm32x_info->part_info->fsize_addr, &flash_size_in_kb);
+		retval = target_read_u16(target, stm32h7_info->part_info->fsize_addr, &flash_size_in_kb);
 
 	if (retval != ERROR_OK) {
 		/* read error when device has invalid value, set max flash size */
-		flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
+		flash_size_in_kb = stm32h7_info->part_info->max_flash_size_kb;
 		LOG_INFO("assuming %" PRIu16 "k flash", flash_size_in_kb);
 	} else
 		LOG_INFO("flash size probed value %" PRIu16 "k", flash_size_in_kb);
 
 	/* setup bank size */
 	const uint32_t bank1_base = FLASH_BANK0_ADDRESS;
-	const uint32_t bank2_base = bank1_base + stm32x_info->part_info->max_bank_size_kb * 1024;
-	bool has_dual_bank = stm32x_info->part_info->has_dual_bank;
+	const uint32_t bank2_base = bank1_base + stm32h7_info->part_info->max_bank_size_kb * 1024;
+	bool has_dual_bank = stm32h7_info->part_info->has_dual_bank;
 
 	switch (device_id) {
 	case DEVID_STM32H74_H75XX:
@@ -903,27 +903,27 @@ static int stm32x_probe(struct flash_bank *bank)
 
 	/* if the user sets the size manually then ignore the probed value
 	 * this allows us to work around devices that have an invalid flash size register value */
-	if (stm32x_info->user_bank_size) {
+	if (stm32h7_info->user_bank_size) {
 		LOG_INFO("ignoring flash probed value, using configured bank size");
-		flash_size_in_kb = stm32x_info->user_bank_size / 1024;
+		flash_size_in_kb = stm32h7_info->user_bank_size / 1024;
 	} else if (flash_size_in_kb == 0xffff) {
 		/* die flash size */
-		flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
+		flash_size_in_kb = stm32h7_info->part_info->max_flash_size_kb;
 	}
 
 	/* did we assign flash size? */
 	assert(flash_size_in_kb != 0xffff);
 	bank->size = flash_size_in_kb * 1024;
-	bank->write_start_alignment = stm32x_info->part_info->block_size;
-	bank->write_end_alignment = stm32x_info->part_info->block_size;
+	bank->write_start_alignment = stm32h7_info->part_info->block_size;
+	bank->write_end_alignment = stm32h7_info->part_info->block_size;
 
 	/* setup sectors */
-	bank->num_sectors = flash_size_in_kb / stm32x_info->part_info->page_size_kb;
+	bank->num_sectors = flash_size_in_kb / stm32h7_info->part_info->page_size_kb;
 	assert(bank->num_sectors > 0);
 
 	free(bank->sectors);
 
-	bank->sectors = alloc_block_array(0, stm32x_info->part_info->page_size_kb * 1024,
+	bank->sectors = alloc_block_array(0, stm32h7_info->part_info->page_size_kb * 1024,
 			bank->num_sectors);
 
 	if (!bank->sectors) {
@@ -932,7 +932,7 @@ static int stm32x_probe(struct flash_bank *bank)
 	}
 
 	/* setup protection blocks */
-	const uint32_t wpsn = stm32x_info->part_info->wps_group_size;
+	const uint32_t wpsn = stm32h7_info->part_info->wps_group_size;
 	assert(bank->num_sectors % wpsn == 0);
 
 	bank->num_prot_blocks = bank->num_sectors / wpsn;
@@ -940,7 +940,7 @@ static int stm32x_probe(struct flash_bank *bank)
 
 	free(bank->prot_blocks);
 
-	bank->prot_blocks = alloc_block_array(0, stm32x_info->part_info->page_size_kb * wpsn * 1024,
+	bank->prot_blocks = alloc_block_array(0, stm32h7_info->part_info->page_size_kb * wpsn * 1024,
 			bank->num_prot_blocks);
 
 	if (!bank->prot_blocks) {
@@ -948,28 +948,28 @@ static int stm32x_probe(struct flash_bank *bank)
 		return ERROR_FAIL;
 	}
 
-	stm32x_info->probed = true;
+	stm32h7_info->probed = true;
 	return ERROR_OK;
 }
 
-static int stm32x_auto_probe(struct flash_bank *bank)
+static int stm32h7_auto_probe(struct flash_bank *bank)
 {
-	struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
+	struct stm32h7_flash_bank *stm32h7_info = bank->driver_priv;
 
-	if (stm32x_info->probed)
+	if (stm32h7_info->probed)
 		return ERROR_OK;
 
-	return stm32x_probe(bank);
+	return stm32h7_probe(bank);
 }
 
 /* This method must return a string displaying information about the bank */
-static int stm32x_get_info(struct flash_bank *bank, struct command_invocation *cmd)
+static int stm32h7_get_info(struct flash_bank *bank, struct command_invocation *cmd)
 {
-	struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
-	const struct stm32h7x_part_info *info = stm32x_info->part_info;
+	struct stm32h7_flash_bank *stm32h7_info = bank->driver_priv;
+	const struct stm32h7_part_info *info = stm32h7_info->part_info;
 
-	if (!stm32x_info->probed) {
-		int retval = stm32x_probe(bank);
+	if (!stm32h7_info->probed) {
+		int retval = stm32h7_probe(bank);
 		if (retval != ERROR_OK) {
 			command_print_sameline(cmd, "Unable to find bank information.");
 			return retval;
@@ -978,7 +978,7 @@ static int stm32x_get_info(struct flash_bank *bank, struct command_invocation *c
 
 	if (info) {
 		const char *rev_str = NULL;
-		uint16_t rev_id = stm32x_info->idcode >> 16;
+		uint16_t rev_id = stm32h7_info->idcode >> 16;
 
 		for (unsigned int i = 0; i < info->num_revs; i++)
 			if (rev_id == info->revs[i].rev)
@@ -986,11 +986,11 @@ static int stm32x_get_info(struct flash_bank *bank, struct command_invocation *c
 
 		if (rev_str) {
 			command_print_sameline(cmd, "%s - Rev: %s",
-				stm32x_info->part_info->device_str, rev_str);
+				stm32h7_info->part_info->device_str, rev_str);
 		} else {
 			command_print_sameline(cmd,
 				 "%s - Rev: unknown (0x%04" PRIx16 ")",
-				stm32x_info->part_info->device_str, rev_id);
+				stm32h7_info->part_info->device_str, rev_id);
 		}
 	} else {
 		command_print_sameline(cmd, "Cannot identify target as a STM32H7x");
@@ -999,7 +999,7 @@ static int stm32x_get_info(struct flash_bank *bank, struct command_invocation *c
 	return ERROR_OK;
 }
 
-static int stm32x_set_rdp(struct flash_bank *bank, enum stm32h7x_opt_rdp new_rdp)
+static int stm32h7_set_rdp(struct flash_bank *bank, enum stm32h7_opt_rdp new_rdp)
 {
 	struct target *target = bank->target;
 	uint32_t optsr, cur_rdp;
@@ -1010,7 +1010,7 @@ static int stm32x_set_rdp(struct flash_bank *bank, enum stm32h7x_opt_rdp new_rdp
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	retval = stm32x_read_flash_reg_by_index(bank, STM32_FLASH_OPTSR_PRG_INDEX, &optsr);
+	retval = stm32h7_read_flash_reg_by_index(bank, STM32_FLASH_OPTSR_PRG_INDEX, &optsr);
 
 	if (retval != ERROR_OK) {
 		LOG_DEBUG("unable to read FLASH_OPTSR_PRG register");
@@ -1040,10 +1040,10 @@ static int stm32x_set_rdp(struct flash_bank *bank, enum stm32h7x_opt_rdp new_rdp
 	optsr = (optsr & ~OPT_RDP_MASK) | (new_rdp << OPT_RDP_POS);
 
 	/* apply new option value */
-	return stm32x_write_option(bank, STM32_FLASH_OPTSR_PRG_INDEX, optsr);
+	return stm32h7_write_option(bank, STM32_FLASH_OPTSR_PRG_INDEX, optsr);
 }
 
-COMMAND_HANDLER(stm32x_handle_lock_command)
+COMMAND_HANDLER(stm32h7_handle_lock_command)
 {
 	if (CMD_ARGC < 1)
 		return ERROR_COMMAND_SYNTAX_ERROR;
@@ -1053,7 +1053,7 @@ COMMAND_HANDLER(stm32x_handle_lock_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = stm32x_set_rdp(bank, OPT_RDP_L1);
+	retval = stm32h7_set_rdp(bank, OPT_RDP_L1);
 
 	if (retval != ERROR_OK)
 		command_print(CMD, "%s failed to lock device", bank->driver->name);
@@ -1063,7 +1063,7 @@ COMMAND_HANDLER(stm32x_handle_lock_command)
 	return retval;
 }
 
-COMMAND_HANDLER(stm32x_handle_unlock_command)
+COMMAND_HANDLER(stm32h7_handle_unlock_command)
 {
 	if (CMD_ARGC < 1)
 		return ERROR_COMMAND_SYNTAX_ERROR;
@@ -1073,7 +1073,7 @@ COMMAND_HANDLER(stm32x_handle_unlock_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = stm32x_set_rdp(bank, OPT_RDP_L0);
+	retval = stm32h7_set_rdp(bank, OPT_RDP_L0);
 
 	if (retval != ERROR_OK)
 		command_print(CMD, "%s failed to unlock device", bank->driver->name);
@@ -1083,45 +1083,45 @@ COMMAND_HANDLER(stm32x_handle_unlock_command)
 	return retval;
 }
 
-static int stm32x_mass_erase(struct flash_bank *bank)
+static int stm32h7_mass_erase(struct flash_bank *bank)
 {
 	int retval, retval2;
 	struct target *target = bank->target;
-	struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
+	struct stm32h7_flash_bank *stm32h7_info = bank->driver_priv;
 
 	if (target->state != TARGET_HALTED) {
 		LOG_ERROR("Target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	retval = stm32x_unlock_reg(bank);
+	retval = stm32h7_unlock_reg(bank);
 	if (retval != ERROR_OK)
 		goto flash_lock;
 
 	/* mass erase flash memory bank */
-	retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX,
-			stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64, 0));
+	retval = stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX,
+			stm32h7_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64, 0));
 	if (retval != ERROR_OK)
 		goto flash_lock;
 
-	retval = stm32x_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX,
-			stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64 | FLASH_START, 0));
+	retval = stm32h7_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX,
+			stm32h7_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64 | FLASH_START, 0));
 	if (retval != ERROR_OK)
 		goto flash_lock;
 
-	retval = stm32x_wait_flash_op_queue(bank, MASS_ERASE_TIMEOUT);
+	retval = stm32h7_wait_flash_op_queue(bank, MASS_ERASE_TIMEOUT);
 	if (retval != ERROR_OK)
 		goto flash_lock;
 
 flash_lock:
-	retval2 = stm32x_lock_reg(bank);
+	retval2 = stm32h7_lock_reg(bank);
 	if (retval2 != ERROR_OK)
 		LOG_ERROR("error during the lock of flash");
 
 	return (retval == ERROR_OK) ? retval2 : retval;
 }
 
-COMMAND_HANDLER(stm32x_handle_mass_erase_command)
+COMMAND_HANDLER(stm32h7_handle_mass_erase_command)
 {
 	if (CMD_ARGC != 1)
 		return ERROR_COMMAND_SYNTAX_ERROR;
@@ -1131,7 +1131,7 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = stm32x_mass_erase(bank);
+	retval = stm32h7_mass_erase(bank);
 	if (retval == ERROR_OK)
 		command_print(CMD, "stm32h7x mass erase complete");
 	else
@@ -1140,7 +1140,7 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command)
 	return retval;
 }
 
-COMMAND_HANDLER(stm32x_handle_option_read_command)
+COMMAND_HANDLER(stm32h7_handle_option_read_command)
 {
 	if (CMD_ARGC != 2)
 		return ERROR_COMMAND_SYNTAX_ERROR;
@@ -1153,17 +1153,17 @@ COMMAND_HANDLER(stm32x_handle_option_read_command)
 	uint32_t reg_offset, value;
 
 	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
-	retval = stm32x_read_flash_reg_by_index(bank, reg_offset, &value);
+	retval = stm32h7_read_flash_reg_by_index(bank, reg_offset, &value);
 	if (retval != ERROR_OK)
 		return retval;
 
 	command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32,
-			stm32x_get_flash_reg(bank, reg_offset), value);
+			stm32h7_get_flash_reg(bank, reg_offset), value);
 
 	return retval;
 }
 
-COMMAND_HANDLER(stm32x_handle_option_write_command)
+COMMAND_HANDLER(stm32h7_handle_option_write_command)
 {
 	if (CMD_ARGC != 3 && CMD_ARGC != 4)
 		return ERROR_COMMAND_SYNTAX_ERROR;
@@ -1180,41 +1180,41 @@ COMMAND_HANDLER(stm32x_handle_option_write_command)
 	if (CMD_ARGC > 3)
 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], mask);
 
-	return stm32x_modify_option(bank, reg_offset, value, mask);
+	return stm32h7_modify_option(bank, reg_offset, value, mask);
 }
 
-static const struct command_registration stm32h7x_exec_command_handlers[] = {
+static const struct command_registration stm32h7_exec_command_handlers[] = {
 	{
 		.name = "lock",
-		.handler = stm32x_handle_lock_command,
+		.handler = stm32h7_handle_lock_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id",
 		.help = "Lock entire flash device.",
 	},
 	{
 		.name = "unlock",
-		.handler = stm32x_handle_unlock_command,
+		.handler = stm32h7_handle_unlock_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id",
 		.help = "Unlock entire protected flash device.",
 	},
 	{
 		.name = "mass_erase",
-		.handler = stm32x_handle_mass_erase_command,
+		.handler = stm32h7_handle_mass_erase_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id",
 		.help = "Erase entire flash device.",
 	},
 	{
 		.name = "option_read",
-		.handler = stm32x_handle_option_read_command,
+		.handler = stm32h7_handle_option_read_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id reg_offset",
 		.help = "Read and display device option bytes.",
 	},
 	{
 		.name = "option_write",
-		.handler = stm32x_handle_option_write_command,
+		.handler = stm32h7_handle_option_write_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id reg_offset value [mask]",
 		.help = "Write device option bit fields with provided value.",
@@ -1222,29 +1222,29 @@ static const struct command_registration stm32h7x_exec_command_handlers[] = {
 	COMMAND_REGISTRATION_DONE
 };
 
-static const struct command_registration stm32h7x_command_handlers[] = {
+static const struct command_registration stm32h7_command_handlers[] = {
 	{
 		.name = "stm32h7x",
 		.mode = COMMAND_ANY,
 		.help = "stm32h7x flash command group",
 		.usage = "",
-		.chain = stm32h7x_exec_command_handlers,
+		.chain = stm32h7_exec_command_handlers,
 	},
 	COMMAND_REGISTRATION_DONE
 };
 
 const struct flash_driver stm32h7x_flash = {
 	.name = "stm32h7x",
-	.commands = stm32h7x_command_handlers,
-	.flash_bank_command = stm32x_flash_bank_command,
-	.erase = stm32x_erase,
-	.protect = stm32x_protect,
-	.write = stm32x_write,
+	.commands = stm32h7_command_handlers,
+	.flash_bank_command = stm32h7_flash_bank_command,
+	.erase = stm32h7_erase,
+	.protect = stm32h7_protect,
+	.write = stm32h7_write,
 	.read = default_flash_read,
-	.probe = stm32x_probe,
-	.auto_probe = stm32x_auto_probe,
+	.probe = stm32h7_probe,
+	.auto_probe = stm32h7_auto_probe,
 	.erase_check = default_flash_blank_check,
-	.protect_check = stm32x_protect_check,
-	.info = stm32x_get_info,
+	.protect_check = stm32h7_protect_check,
+	.info = stm32h7_get_info,
 	.free_driver_priv = default_flash_free_driver_priv,
 };

--