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|
From: R. D. <rdi...@rd...> - 2025-12-04 21:32:45
|
Hallo Paul: >> I uploaded Patchset 4 half an hour ago, Jenkins appended "Verified >> +1" shortly afterwards, but I got no e-mail about it. I believe you >> also get no e-mail if the build fails. >> >> Build failure notifications are relatively important because, if you >> patch fails the build, no reviewer is probably going to bother >> reviewing the patch until the author at least fixes the build. >> >> As the patch author, you may assume that the CI system needs some >> time, and that you will get an e-mail sooner or later, so you may >> forget about your patch (at least temporarily, we are all busy >> people). This is what happened to me with this particular >> patch. Even if you remember later, a timely build failure >> notification would still help because you are more likely to have >> the code fresh in you head. On 12.11.24 11:20, Paul Fertser wrote: > I fully agree! The relevant configuration knob found and tweaked, hope > it works properly now. > > For the reference, before the big software upgrade few years ago > Jenkins was using "gerrit review" commands to post results and that > used default nofication level "all". Then it was switched to Gerrit > REST API and started to honour a somewhat hidden "Notification Level" > setting in the "Miscellaneous" section which somehow was set to > "none". > [...] I am having the same problem again, this time with the following patch: https://review.openocd.org/c/openocd/+/9281 I have checked my spam folder to no avail. Has something changed in Gerrit again? Thanks in advance, rdiez |
|
From: Daniel G. <dgo...@os...> - 2025-12-04 07:06:11
|
Hello,
To follow up, please disregard the previous email. After further
examination I discovered a potential issue in my JTAG driver code that
is probably causing this issue and needs further review.
Thanks,
Daniel Goehring
Ampere Computing
On 12/3/2025 11:15 PM, Daniel Goehring wrote:
> Hello,
>
> To provide context for my question, for OpenOCD, most of the JTAG
> drivers adhere to the following convention for the "reset" callback...
>
> static int jtag_driver_reset(int trst, int srst)
>
> and
>
> struct adapter_driver jtag_driver_adapter_driver = {
> .name = "jtag_driver",
> .transport_ids = TRANSPORT_JTAG,
> .transport_preferred_id = TRANSPORT_JTAG,
> .commands = jtag_driver_command_handlers,
>
> .init = jtag_driver_init,
> .quit = jtag_driver_quit,
> .reset = jtag_driver_reset,
> ...
>
> During OpenOCD startup, I see the "jtag_driver_reset" procedure called
> to assert "trst", but the follow-up call to de-assert "trst" doesn't
> happen.
>
> For example, these are excerpts from a debug log showing that "trst"
> gets asserted, but never de-asserted. Is there something in the
> OpenOCD board configuration file that I'm missing to instruct OpenOCD
> to de-assert TRST after it's been asserted?
>
> Debug: 55 21 jtag_driver.c:338 jtag_driver_reset(): JTAG DRIVER DEBUG:
> reset trst: 0 srst 0 << TRST DE-ASSERTED
> Debug: 56 21 core.c:843 jtag_add_reset(): SRST line released
> Debug: 57 21 core.c:868 jtag_add_reset(): TRST line released
> Debug: 58 21 core.c:334 jtag_call_event_callbacks(): jtag event: TAP
> reset
> ...
> Debug: 67 224 core.c:334 jtag_call_event_callbacks(): jtag event: TAP
> reset
> Debug: 68 224 jtag_driver.c:338 jtag_driver_reset(): JTAG DRIVER
> DEBUG: reset trst: 1 srst 0 << TRST ASSERTED
> Info : 69 224 jtag_driver.c:348 jtag_driver_reset(): JTAG DRIVER INFO:
> Successfully reset JTAG state machine
> Debug: 70 224 jtag_driver.c:349 jtag_driver_reset(): tap_set_state(RESET)
> Debug: 71 224 core.c:991 default_interface_jtag_execute_queue(): JTAG
> TLR RESET to RESET
> Debug: 72 224 core.c:1248 jtag_examine_chain(): DR scan interrogation
> for IDCODE/BYPASS
> Debug: 73 224 core.c:334 jtag_call_event_callbacks(): jtag event: TAP
> reset
> ...
> Debug: 80 225 jtag_driver.c:338 jtag_driver_reset(): JTAG DRIVER
> DEBUG: reset trst: 1 srst 0 << TRST ASSERTED
> Info : 81 225 jtag_driver.c:348 jtag_driver_reset(): JTAG DRIVER INFO:
> Successfully reset JTAG state machine
> Debug: 82 225 jtag_driver.c:349 jtag_driver_reset(): tap_set_state(RESET)
> Debug: 86 225 core.c:991 default_interface_jtag_execute_queue(): JTAG
> TLR RESET to RESET
> ...
> Debug: 186 247 core.c:334 jtag_call_event_callbacks(): jtag event: TAP
> reset
> Debug: 187 247 jtag_driver.c:338 jtag_driver_reset(): JTAG DRIVER
> DEBUG: reset trst: 1 srst 0 << TRST ASSERTED
> Info : 188 247 jtag_driver.c:348 jtag_driver_reset(): JTAG DRIVER
> INFO: Successfully reset JTAG state machine
> Debug: 189 247 jtag_driver.c:349 jtag_driver_reset():
> tap_set_state(RESET)
> Debug: 190 247 core.c:991 default_interface_jtag_execute_queue(): JTAG
> TLR RESET to RESET
> Debug: 191 247 core.c:1248 jtag_examine_chain(): DR scan interrogation
> for IDCODE/BYPASS
> Debug: 192 247 core.c:334 jtag_call_event_callbacks(): jtag event: TAP
> reset
> ...
> Debug: 199 248 jtag_driver.c:338 jtag_driver_reset(): JTAG DRIVER
> DEBUG: reset trst: 1 srst 0 << TRST ASSERTED
> Info : 200 248 jtag_driver.c:348 jtag_driver_reset(): JTAG DRIVER
> INFO: Successfully reset JTAG state machine
> Debug: 201 248 jtag_driver.c:349 jtag_driver_reset():
> tap_set_state(RESET)
>
> Any insight as is appreciated.
>
> Thanks,
>
> Daniel Goehring
>
> Ampere Computing
>
>
|
|
From: Daniel G. <dgo...@os...> - 2025-12-04 06:51:10
|
Hello,
To provide context for my question, for OpenOCD, most of the JTAG
drivers adhere to the following convention for the "reset" callback...
static int jtag_driver_reset(int trst, int srst)
and
struct adapter_driver jtag_driver_adapter_driver = {
.name = "jtag_driver",
.transport_ids = TRANSPORT_JTAG,
.transport_preferred_id = TRANSPORT_JTAG,
.commands = jtag_driver_command_handlers,
.init = jtag_driver_init,
.quit = jtag_driver_quit,
.reset = jtag_driver_reset,
...
During OpenOCD startup, I see the "jtag_driver_reset" procedure called
to assert "trst", but the follow-up call to de-assert "trst" doesn't happen.
For example, these are excerpts from a debug log showing that "trst"
gets asserted, but never de-asserted. Is there something in the OpenOCD
board configuration file that I'm missing to instruct OpenOCD to
de-assert TRST after it's been asserted?
Debug: 55 21 jtag_driver.c:338 jtag_driver_reset(): JTAG DRIVER DEBUG:
reset trst: 0 srst 0 << TRST DE-ASSERTED
Debug: 56 21 core.c:843 jtag_add_reset(): SRST line released
Debug: 57 21 core.c:868 jtag_add_reset(): TRST line released
Debug: 58 21 core.c:334 jtag_call_event_callbacks(): jtag event: TAP reset
...
Debug: 67 224 core.c:334 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 68 224 jtag_driver.c:338 jtag_driver_reset(): JTAG DRIVER DEBUG:
reset trst: 1 srst 0 << TRST ASSERTED
Info : 69 224 jtag_driver.c:348 jtag_driver_reset(): JTAG DRIVER INFO:
Successfully reset JTAG state machine
Debug: 70 224 jtag_driver.c:349 jtag_driver_reset(): tap_set_state(RESET)
Debug: 71 224 core.c:991 default_interface_jtag_execute_queue(): JTAG
TLR RESET to RESET
Debug: 72 224 core.c:1248 jtag_examine_chain(): DR scan interrogation
for IDCODE/BYPASS
Debug: 73 224 core.c:334 jtag_call_event_callbacks(): jtag event: TAP reset
...
Debug: 80 225 jtag_driver.c:338 jtag_driver_reset(): JTAG DRIVER DEBUG:
reset trst: 1 srst 0 << TRST ASSERTED
Info : 81 225 jtag_driver.c:348 jtag_driver_reset(): JTAG DRIVER INFO:
Successfully reset JTAG state machine
Debug: 82 225 jtag_driver.c:349 jtag_driver_reset(): tap_set_state(RESET)
Debug: 86 225 core.c:991 default_interface_jtag_execute_queue(): JTAG
TLR RESET to RESET
...
Debug: 186 247 core.c:334 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 187 247 jtag_driver.c:338 jtag_driver_reset(): JTAG DRIVER DEBUG:
reset trst: 1 srst 0 << TRST ASSERTED
Info : 188 247 jtag_driver.c:348 jtag_driver_reset(): JTAG DRIVER INFO:
Successfully reset JTAG state machine
Debug: 189 247 jtag_driver.c:349 jtag_driver_reset(): tap_set_state(RESET)
Debug: 190 247 core.c:991 default_interface_jtag_execute_queue(): JTAG
TLR RESET to RESET
Debug: 191 247 core.c:1248 jtag_examine_chain(): DR scan interrogation
for IDCODE/BYPASS
Debug: 192 247 core.c:334 jtag_call_event_callbacks(): jtag event: TAP reset
...
Debug: 199 248 jtag_driver.c:338 jtag_driver_reset(): JTAG DRIVER DEBUG:
reset trst: 1 srst 0 << TRST ASSERTED
Info : 200 248 jtag_driver.c:348 jtag_driver_reset(): JTAG DRIVER INFO:
Successfully reset JTAG state machine
Debug: 201 248 jtag_driver.c:349 jtag_driver_reset(): tap_set_state(RESET)
Any insight as is appreciated.
Thanks,
Daniel Goehring
Ampere Computing
|
|
From: Marc S. <de...@za...> - 2025-12-01 20:17:31
|
I have the same issue. I briefly looked into the error with Paul. It's probably a problem with Ubuntu's Launchpad ID. Best regards, Marc On Mon, 2025-12-01 at 19:25 +0100, R. Diez wrote: > Hi all: > > I cannot sign in to Gerrit with Ubuntu's Launchpad ID anymore. I get > the usual page on Launchpad: > > The site has requested some personal information, please choose what > you would like to share: > ... > [ Yes, log me in ] > > When I click on the button, I then get redirected to this URL: > > https://review.openocd.org/SignInFailure,SIGN_IN,Local+signature+verification+failed > > The page content is just one line of text: > > Not Found > > Thanks in advance, > rdiez |
|
From: R. D. <rdi...@rd...> - 2025-12-01 18:50:00
|
Hi all: I cannot sign in to Gerrit with Ubuntu's Launchpad ID anymore. I get the usual page on Launchpad: The site has requested some personal information, please choose what you would like to share: ... [ Yes, log me in ] When I click on the button, I then get redirected to this URL: https://review.openocd.org/SignInFailure,SIGN_IN,Local+signature+verification+failed The page content is just one line of text: Not Found Thanks in advance, rdiez |
|
From: <ge...@op...> - 2025-11-30 08:42:19
|
This is an automated email from Gerrit. "Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9279 -- gerrit commit a47bd16365e7d2bc2d44c4bcdb759270b7df3c00 Author: Antonio Borneo <bor...@gm...> Date: Sun Nov 30 09:29:20 2025 +0100 tcl: file_renaming: drop automatic replecement check With 'proc find' able to handle the replacement of '_' to '-', drop the now unnecessary hardcoded renames. Change-Id: I67fe3b5de8bad7611b2229fed8d2eefee848eb81 Signed-off-by: Antonio Borneo <bor...@gm...> diff --git a/tcl/file_renaming.cfg b/tcl/file_renaming.cfg index 1603e23213..3a5294c3f4 100644 --- a/tcl/file_renaming.cfg +++ b/tcl/file_renaming.cfg @@ -14,28 +14,14 @@ # board, chip, cpld, cpu, fpga, interface, target, test, tools set _file_renaming { - board/nordic_nrf51822_mkit.cfg board/nordic/nrf51822-mkit.cfg - board/nordic_nrf51_dk.cfg board/nordic/nrf51-dk.cfg - board/nordic_nrf52_dk.cfg board/nordic/nrf52-dk.cfg board/omap2420_h4.cfg board/ti/omap2420-h4.cfg board/stm32mp13x_dk.cfg board/st/stm32mp135f-dk.cfg board/stm32mp15x_dk2.cfg board/st/stm32mp157f-dk2.cfg board/sifive-hifive1-revb.cfg board/sifive/hifive1-rev-b.cfg - board/ti_am437x_idk.cfg board/ti/am437x-idk.cfg - board/ti_am43xx_evm.cfg board/ti/am43xx-evm.cfg board/ti_beagleboard.cfg board/beagle/beagleboard.cfg board/ti_beagleboard_xm.cfg board/beagle/beagleboard-xm.cfg board/ti_beaglebone_black.cfg board/beagle/beaglebone-black.cfg board/ti_beaglebone.cfg board/beagle/beaglebone.cfg - board/ti_cc13x0_launchpad.cfg board/ti/cc13x0-launchpad.cfg - board/ti_cc13x2_launchpad.cfg board/ti/cc13x2-launchpad.cfg - board/ti_cc26x0_launchpad.cfg board/ti/cc26x0-launchpad.cfg - board/ti_cc26x2_launchpad.cfg board/ti/cc26x2-launchpad.cfg - board/ti_cc3200_launchxl.cfg board/ti/cc3200-launchxl.cfg - board/ti_cc3220sf_launchpad.cfg board/ti/cc3220sf-launchpad.cfg - board/ti_cc32xx_launchpad.cfg board/ti/cc32xx-launchpad.cfg - board/ti_msp432_launchpad.cfg board/ti/msp432-launchpad.cfg - board/ti_pandaboard_es.cfg board/ti/pandaboard-es.cfg interface/chameleon.cfg interface/parport/chameleon.cfg interface/flashlink.cfg interface/parport/flashlink.cfg } -- |
|
From: <ge...@op...> - 2025-11-30 08:42:19
|
This is an automated email from Gerrit. "Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9280 -- gerrit commit b51332beaa58ab17eb8c509e4f555cb19e2462a8 Author: Antonio Borneo <bor...@gm...> Date: Sun Nov 30 09:32:38 2025 +0100 tcl: file_renaming: add missing rename ti_beaglebone-base Add the file renaming still not covered. Change-Id: I74e22b3b66a27b9618356272553331ef3ada50cb Signed-off-by: Antonio Borneo <bor...@gm...> diff --git a/tcl/file_renaming.cfg b/tcl/file_renaming.cfg index 3a5294c3f4..a522471f9e 100644 --- a/tcl/file_renaming.cfg +++ b/tcl/file_renaming.cfg @@ -20,6 +20,7 @@ set _file_renaming { board/sifive-hifive1-revb.cfg board/sifive/hifive1-rev-b.cfg board/ti_beagleboard.cfg board/beagle/beagleboard.cfg board/ti_beagleboard_xm.cfg board/beagle/beagleboard-xm.cfg + board/ti_beaglebone-base.cfg board/beagle/beaglebone-base.cfg board/ti_beaglebone_black.cfg board/beagle/beaglebone-black.cfg board/ti_beaglebone.cfg board/beagle/beaglebone.cfg interface/chameleon.cfg interface/parport/chameleon.cfg -- |
|
From: <ge...@op...> - 2025-11-30 08:42:13
|
This is an automated email from Gerrit. "Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9278 -- gerrit commit 960b8252d8d25db8b246e8e55057f7e4532e06ab Author: Antonio Borneo <bor...@gm...> Date: Sun Nov 30 09:25:48 2025 +0100 startup.tcl: extend the file search among rename The renaming of boards and targets is often requiring the simple replacement of '_' with '-'. To avoid listing such replacements in 'tcl/file_renaming.cfg', add the automatic check in 'proc find' allowing till two replacements of '_' with '-'. Change-Id: I2623ea78d9c61d86189afcae2553c2910bda8389 Signed-off-by: Antonio Borneo <bor...@gm...> diff --git a/src/helper/startup.tcl b/src/helper/startup.tcl index 89ed71b900..be01d71b3d 100644 --- a/src/helper/startup.tcl +++ b/src/helper/startup.tcl @@ -31,23 +31,39 @@ proc find {filename} { # - path/to/a/certain/vendor_config_file # - path/to/a/certain/vendor-config_file - # replaced with + # replaced either with # - path/to/a/certain/vendor/config_file + # or + # - path/to/a/certain/vendor/config-file regsub {([/\\])([^/\\_-]*)[_-]([^/\\]*$)} $filename "\\1\\2\\1\\3" f if {[catch {_find_internal $f} t]==0} { echo "WARNING: '$filename' is deprecated, use '$f' instead" return $t } + regsub {([/\\])([^/\\_]*)_([^/\\]*$)} $f "\\1\\2-\\3" f + regsub {([/\\])([^/\\_]*)_([^/\\]*$)} $f "\\1\\2-\\3" f + if {[catch {_find_internal $f} t]==0} { + echo "WARNING: '$filename' is deprecated, use '$f' instead" + return $t + } foreach vendor {nordic ti sifive st} { # - path/to/a/certain/config_file - # replaced with + # replaced either with # - path/to/a/certain/${vendor}/config_file + # or + # - path/to/a/certain/${vendor}/config-file regsub {([/\\])([^/\\]*$)} $filename "\\1$vendor\\1\\2" f if {[catch {_find_internal $f} t]==0} { echo "WARNING: '$filename' is deprecated, use '$f' instead" return $t } + regsub {([/\\])([^/\\_]*)_([^/\\]*$)} $f "\\1\\2-\\3" f + regsub {([/\\])([^/\\_]*)_([^/\\]*$)} $f "\\1\\2-\\3" f + if {[catch {_find_internal $f} t]==0} { + echo "WARNING: '$filename' is deprecated, use '$f' instead" + return $t + } } # at last, check for explicit renaming -- |
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From: <ge...@op...> - 2025-11-29 20:35:18
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This is an automated email from Gerrit. "Tomas Vanek <va...@fb...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9275 -- gerrit commit 112ecba8697b11db340d54f7a35454bc952b0054 Author: Tomas Vanek <va...@fb...> Date: Sat Nov 29 20:16:29 2025 +0100 target/riscv: add target_was_examined() checks If a RISC-V target does not pass the initial examination some commands fail by assert() or log lot of hardly understandable errors. Check if target was examined otherwise fail early. Although command_print() is preferred in OpenOCD commands, use LOG_TARGET_ERROR() if the rest of command uses the same. Change-Id: I615e48f348a0f3bdaf71630a2fcd6fc7665115d5 Signed-off-by: Tomas Vanek <va...@fb...> diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 8054a1c9b7..fc59468b7b 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -5007,6 +5007,11 @@ COMMAND_HANDLER(riscv_itrigger) struct target *target = get_current_target(CMD_CTX); const int ITRIGGER_UNIQUE_ID = -CSR_TDATA1_TYPE_ITRIGGER; + if (!target_was_examined(target)) { + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; + } + if (riscv_enumerate_triggers(target) != ERROR_OK) return ERROR_FAIL; @@ -5072,6 +5077,11 @@ COMMAND_HANDLER(riscv_icount) struct target *target = get_current_target(CMD_CTX); const int ICOUNT_UNIQUE_ID = -CSR_TDATA1_TYPE_ICOUNT; + if (!target_was_examined(target)) { + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; + } + if (riscv_enumerate_triggers(target) != ERROR_OK) return ERROR_FAIL; @@ -5137,6 +5147,11 @@ COMMAND_HANDLER(riscv_etrigger) struct target *target = get_current_target(CMD_CTX); const int ETRIGGER_UNIQUE_ID = -CSR_TDATA1_TYPE_ETRIGGER; + if (!target_was_examined(target)) { + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; + } + if (riscv_enumerate_triggers(target) != ERROR_OK) return ERROR_FAIL; @@ -5194,6 +5209,11 @@ COMMAND_HANDLER(riscv_etrigger) COMMAND_HANDLER(handle_repeat_read) { struct target *target = get_current_target(CMD_CTX); + if (!target_was_examined(target)) { + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; + } + RISCV_INFO(r); if (CMD_ARGC < 2 || CMD_ARGC > 3) @@ -5408,6 +5428,11 @@ COMMAND_HANDLER(riscv_exec_progbuf) struct target *target = get_current_target(CMD_CTX); + if (!target_was_examined(target)) { + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; + } + RISCV_INFO(r); if (r->dtm_version != DTM_DTMCS_VERSION_1_0) { LOG_TARGET_ERROR(target, "exec_progbuf: Program buffer is " @@ -5514,6 +5539,11 @@ static COMMAND_HELPER(report_reserved_triggers, struct target *target) COMMAND_HANDLER(handle_reserve_trigger) { struct target *target = get_current_target(CMD_CTX); + if (!target_was_examined(target)) { + command_print(CMD, "Error: Target not examined"); + return ERROR_TARGET_NOT_EXAMINED; + } + if (CMD_ARGC == 0) return CALL_COMMAND_HANDLER(report_reserved_triggers, target); diff --git a/src/target/riscv/riscv_reg.c b/src/target/riscv/riscv_reg.c index ba1bc2a858..21bda2b4a7 100644 --- a/src/target/riscv/riscv_reg.c +++ b/src/target/riscv/riscv_reg.c @@ -918,6 +918,11 @@ void riscv_reg_cache_invalidate_all(struct target *target) int riscv_reg_set(struct target *target, enum gdb_regno regid, riscv_reg_t value) { + if (!target_was_examined(target)) { + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; + } + return riscv_set_or_write_register(target, regid, value, /* write_through */ false); } @@ -935,6 +940,11 @@ int riscv_reg_set(struct target *target, enum gdb_regno regid, int riscv_reg_write(struct target *target, enum gdb_regno regid, riscv_reg_t value) { + if (!target_was_examined(target)) { + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; + } + return riscv_set_or_write_register(target, regid, value, /* write_through */ true); } @@ -952,6 +962,11 @@ int riscv_reg_write(struct target *target, enum gdb_regno regid, int riscv_reg_get(struct target *target, riscv_reg_t *value, enum gdb_regno regid) { + if (!target_was_examined(target)) { + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; + } + RISCV_INFO(r); assert(r); if (r->dtm_version == DTM_DTMCS_VERSION_0_11) -- |
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From: <ge...@op...> - 2025-11-29 20:35:13
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This is an automated email from Gerrit. "Tomas Vanek <va...@fb...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9276 -- gerrit commit e0475cc97848e9c4abbe87a32dcdb6d88bfd3b23 Author: Tomas Vanek <va...@fb...> Date: Thu Aug 8 21:03:28 2024 +0200 target/riscv: do not set DTM_DTMCS_VERSION_UNKNOWN on examine fail Proper version is necessary for target deinit or future re-examinations. Poisoning the version number causes memory leak in riscv_deinit_target(). Signed-off-by: Tomas Vanek <va...@fb...> Change-Id: Ie63ae83626c3fd7498669cb2898309f1c5d4d112 diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index fc59468b7b..c5090f9c42 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2500,7 +2500,7 @@ static int riscv_examine(struct target *target) examine_status = tt->examine(target); if (examine_status != ERROR_OK) - goto examine_fail; + return examine_status; return ERROR_OK; -- |
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From: <ge...@op...> - 2025-11-29 20:35:13
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This is an automated email from Gerrit. "Tomas Vanek <va...@fb...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9277 -- gerrit commit 19d8c50b755f86be90d2ba1001063733168f34ea Author: Tomas Vanek <va...@fb...> Date: Sat Feb 3 10:22:11 2024 +0100 target/riscv: respect DM_DMSTATUS_ALLUNAVAIL bit during examine Do not throw nonsense errors if a hart has DM_DMSTATUS_ALLUNAVAIL set. Postpone examination till DM_DMSTATUS_ALLUNAVAIL is cleared. Signed-off-by: Tomas Vanek <va...@fb...> Change-Id: I94ccf5cc80e104abb606c7c3798ff70bd8f8e707 diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 6fa5e025be..8963a8e896 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -2121,6 +2121,12 @@ static int examine(struct target *target) if (riscv_get_hart_state(target, &state_at_examine_start) != ERROR_OK) return ERROR_FAIL; + if (state_at_examine_start == RISCV_STATE_UNAVAILABLE) { + target->state = TARGET_UNAVAILABLE; + LOG_TARGET_INFO(target, "unavailable."); + return ERROR_FAIL; + } + RISCV_INFO(r); const bool hart_halted_at_examine_start = state_at_examine_start == RISCV_STATE_HALTED; if (!hart_halted_at_examine_start) { -- |
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From: <ge...@op...> - 2025-11-29 20:21:07
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This is an automated email from Gerrit. "Tomas Vanek <va...@fb...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9274 -- gerrit commit b93e27d7cf9d788d555d3853aea468b458e307fe Author: Tomas Vanek <va...@fb...> Date: Sat Nov 29 21:13:27 2025 +0100 target: add couple of target examined checks Add check to target_step() to be like target_resume() and target_halt(). Add checks to handle_target_get_reg() and handle_target_set_reg() to behave similarly as reg command. Change-Id: I7bfbba9e8e89461897ecd7f20a6628a015a57625 Signed-off-by: Tomas Vanek <va...@fb...> diff --git a/src/target/target.c b/src/target/target.c index bb02d94be5..d55c43d355 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -1424,6 +1424,11 @@ int target_step(struct target *target, { int retval; + if (!target_was_examined(target)) { + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; + } + target_call_event_callbacks(target, TARGET_EVENT_STEP_START); retval = target->type->step(target, current, address, handle_breakpoints); @@ -4725,6 +4730,11 @@ COMMAND_HANDLER(handle_target_get_reg) if (CMD_ARGC < 1 || CMD_ARGC > 2) return ERROR_COMMAND_SYNTAX_ERROR; + if (target->state != TARGET_HALTED) { + command_print(CMD, "Error: [%s] not halted", target_name(target)); + return ERROR_TARGET_NOT_HALTED; + } + bool force = false; Jim_Obj *next_argv = CMD_JIMTCL_ARGV[0]; @@ -4783,6 +4793,11 @@ COMMAND_HANDLER(handle_set_reg_command) if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; + if (target->state != TARGET_HALTED) { + command_print(CMD, "Error: [%s] not halted", target_name(target)); + return ERROR_TARGET_NOT_HALTED; + } + int tmp; #if JIM_VERSION >= 80 Jim_Obj **dict = Jim_DictPairs(CMD_CTX->interp, CMD_JIMTCL_ARGV[0], &tmp); -- |
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From: <ge...@op...> - 2025-11-29 20:21:07
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This is an automated email from Gerrit. "Tomas Vanek <va...@fb...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9273 -- gerrit commit 037b83ad0cd17d4c3cf7fb9fecce2e958c76b031 Author: Tomas Vanek <va...@fb...> Date: Sat Nov 29 20:45:19 2025 +0100 target: log target and return proper error if target not examined While on it remove two copy pasta comments. Change-Id: I66613741d64781c31d5195c9b52e8a30c56bb405 Signed-off-by: Tomas Vanek <va...@fb...> diff --git a/src/target/target.c b/src/target/target.c index ababa57fbd..bb02d94be5 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -490,7 +490,7 @@ int target_poll(struct target *target) /* We can't poll until after examine */ if (!target_was_examined(target)) { /* Fail silently lest we pollute the log */ - return ERROR_FAIL; + return ERROR_TARGET_NOT_EXAMINED; } retval = target->type->poll(target); @@ -516,10 +516,10 @@ int target_poll(struct target *target) int target_halt(struct target *target) { int retval; - /* We can't poll until after examine */ + if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } retval = target->type->halt(target); @@ -567,10 +567,9 @@ int target_resume(struct target *target, bool current, target_addr_t address, { int retval; - /* We can't poll until after examine */ if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } target_call_event_callbacks(target, TARGET_EVENT_RESUME_START); @@ -751,8 +750,8 @@ const char *target_type_name(const struct target *target) static int target_soft_reset_halt(struct target *target) { if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } if (!target->type->soft_reset_halt) { LOG_ERROR("Target %s does not support soft_reset_halt", @@ -789,7 +788,8 @@ int target_run_algorithm(struct target *target, int retval = ERROR_FAIL; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); + LOG_TARGET_ERROR(target, "not examined"); + retval = ERROR_TARGET_NOT_EXAMINED; goto done; } if (!target->type->run_algorithm) { @@ -830,7 +830,8 @@ int target_start_algorithm(struct target *target, int retval = ERROR_FAIL; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); + LOG_TARGET_ERROR(target, "not examined"); + retval = ERROR_TARGET_NOT_EXAMINED; goto done; } if (!target->type->start_algorithm) { @@ -1248,8 +1249,8 @@ int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer) { if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } if (!target->type->read_memory) { LOG_ERROR("Target %s doesn't support read_memory", target_name(target)); @@ -1262,8 +1263,8 @@ int target_read_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer) { if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } if (!target->type->read_phys_memory) { LOG_ERROR("Target %s doesn't support read_phys_memory", target_name(target)); @@ -1276,8 +1277,8 @@ int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } if (!target->type->write_memory) { LOG_ERROR("Target %s doesn't support write_memory", target_name(target)); @@ -1290,8 +1291,8 @@ int target_write_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } if (!target->type->write_phys_memory) { LOG_ERROR("Target %s doesn't support write_phys_memory", target_name(target)); @@ -1382,7 +1383,8 @@ int target_get_gdb_reg_list(struct target *target, int result = ERROR_FAIL; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); + LOG_TARGET_ERROR(target, "not examined"); + result = ERROR_TARGET_NOT_EXAMINED; goto done; } @@ -2354,8 +2356,8 @@ int target_write_buffer(struct target *target, target_addr_t address, uint32_t s size, address); if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } if (size == 0) @@ -2419,8 +2421,8 @@ int target_read_buffer(struct target *target, target_addr_t address, uint32_t si size, address); if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } if (size == 0) @@ -2480,8 +2482,8 @@ int target_checksum_memory(struct target *target, target_addr_t address, uint32_ uint32_t i; uint32_t checksum = 0; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } if (!target->type->checksum_memory) { LOG_ERROR("Target %s doesn't support checksum_memory", target_name(target)); @@ -2522,8 +2524,8 @@ int target_blank_check_memory(struct target *target, uint8_t erased_value) { if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } if (!target->type->blank_check_memory) @@ -2536,8 +2538,8 @@ int target_read_u64(struct target *target, target_addr_t address, uint64_t *valu { uint8_t value_buf[8]; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } int retval = target_read_memory(target, address, 8, 1, value_buf); @@ -2560,8 +2562,8 @@ int target_read_u32(struct target *target, target_addr_t address, uint32_t *valu { uint8_t value_buf[4]; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } int retval = target_read_memory(target, address, 4, 1, value_buf); @@ -2584,8 +2586,8 @@ int target_read_u16(struct target *target, target_addr_t address, uint16_t *valu { uint8_t value_buf[2]; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } int retval = target_read_memory(target, address, 2, 1, value_buf); @@ -2607,8 +2609,8 @@ int target_read_u16(struct target *target, target_addr_t address, uint16_t *valu int target_read_u8(struct target *target, target_addr_t address, uint8_t *value) { if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } int retval = target_read_memory(target, address, 1, 1, value); @@ -2631,8 +2633,8 @@ int target_write_u64(struct target *target, target_addr_t address, uint64_t valu int retval; uint8_t value_buf[8]; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64, @@ -2652,8 +2654,8 @@ int target_write_u32(struct target *target, target_addr_t address, uint32_t valu int retval; uint8_t value_buf[4]; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32, @@ -2673,8 +2675,8 @@ int target_write_u16(struct target *target, target_addr_t address, uint16_t valu int retval; uint8_t value_buf[2]; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx16, @@ -2693,8 +2695,8 @@ int target_write_u8(struct target *target, target_addr_t address, uint8_t value) { int retval; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%2.2" PRIx8, @@ -2712,8 +2714,8 @@ int target_write_phys_u64(struct target *target, target_addr_t address, uint64_t int retval; uint8_t value_buf[8]; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64, @@ -2733,8 +2735,8 @@ int target_write_phys_u32(struct target *target, target_addr_t address, uint32_t int retval; uint8_t value_buf[4]; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32, @@ -2754,8 +2756,8 @@ int target_write_phys_u16(struct target *target, target_addr_t address, uint16_t int retval; uint8_t value_buf[2]; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx16, @@ -2774,8 +2776,8 @@ int target_write_phys_u8(struct target *target, target_addr_t address, uint8_t v { int retval; if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); - return ERROR_FAIL; + LOG_TARGET_ERROR(target, "not examined"); + return ERROR_TARGET_NOT_EXAMINED; } LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%2.2" PRIx8, @@ -3032,7 +3034,7 @@ COMMAND_HANDLER(handle_reg_command) struct target *target = get_current_target(CMD_CTX); if (!target_was_examined(target)) { - LOG_ERROR("Target not examined yet"); + command_print(CMD, "Error: [%s] not examined", target_name(target)); return ERROR_TARGET_NOT_EXAMINED; } struct reg *reg = NULL; -- |
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From: <ge...@op...> - 2025-11-29 10:02:16
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This is an automated email from Gerrit. "Tomas Vanek <va...@fb...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9272 -- gerrit commit 3efc0fa67a4c731a96b3b67164b6eeed81b1ea6c Author: Tomas Vanek <va...@fb...> Date: Sat Nov 29 09:37:58 2025 +0100 gdb_server: preserve gdb monitor command output from Tcl events target_call_timer_callbacks_now() in gdb_query_packet() may result in Tcl event execution. The event output replaces the desired command output. Call target_call_timer_callbacks_now() as late as Tcl return message of monitor command is gathered. Change-Id: Id1c2304fc9b218ceade02e9ae8eff5bd814baa38 Signed-off-by: Tomas Vanek <va...@fb...> diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c index a989bda578..b7ac8f257d 100644 --- a/src/server/gdb_server.c +++ b/src/server/gdb_server.c @@ -2822,7 +2822,6 @@ static int gdb_query_packet(struct connection *connection, cmd_ctx->current_target_override = saved_target_override; current_gdb_connection = NULL; - target_call_timer_callbacks_now(); gdb_connection->output_flag = GDB_OUTPUT_NO; free(cmd); if (retval == JIM_RETURN) @@ -2836,6 +2835,9 @@ static int gdb_query_packet(struct connection *connection, } else { retmsg = strdup(cretmsg); } + + target_call_timer_callbacks_now(); + if (!retmsg) return ERROR_GDB_BUFFER_TOO_SMALL; -- |
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From: <ge...@op...> - 2025-11-28 12:30:43
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This is an automated email from Gerrit. "zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9271 -- gerrit commit 789c2d056dc071076ddbb8ba58ede9e66881728b Author: Marc Schink <de...@za...> Date: Fri Nov 28 13:29:58 2025 +0100 tcl/target: Move GigaDevice configs into vendor directory Move the configuration files into a dedicated vendor folder as required by the developer guidelines. Change-Id: I9ed39e32b6281a9cb8510914690f3f7751b795c8 Signed-off-by: Marc Schink <de...@za...> diff --git a/src/helper/startup.tcl b/src/helper/startup.tcl index 89ed71b900..1fc54900a3 100644 --- a/src/helper/startup.tcl +++ b/src/helper/startup.tcl @@ -39,7 +39,7 @@ proc find {filename} { return $t } - foreach vendor {nordic ti sifive st} { + foreach vendor {nordic ti sifive st gigadevice} { # - path/to/a/certain/config_file # replaced with # - path/to/a/certain/${vendor}/config_file diff --git a/tcl/target/gd32e23x.cfg b/tcl/target/gigadevice/gd32e23x.cfg similarity index 100% rename from tcl/target/gd32e23x.cfg rename to tcl/target/gigadevice/gd32e23x.cfg diff --git a/tcl/target/gd32vf103.cfg b/tcl/target/gigadevice/gd32vf103.cfg similarity index 100% rename from tcl/target/gd32vf103.cfg rename to tcl/target/gigadevice/gd32vf103.cfg -- |
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From: <ge...@op...> - 2025-11-28 10:55:42
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This is an automated email from Gerrit. "Tomas Vanek <va...@fb...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9270 -- gerrit commit 5cfe46ff2300a59970685c0ad8f9b20c23290173 Author: Tomas Vanek <va...@fb...> Date: Fri Nov 28 11:53:14 2025 +0100 target/cortex_a: avoid adding of error return codes The arithmetic addition of the returned error codes was used as a lazy man's logical or. Handle error passing properly. Change-Id: I01f012c2f96131a47be9504ac56d28ea28990626 Signed-off-by: Tomas Vanek <va...@fb...> diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 3d8603a4ba..d47eb11bdf 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -671,18 +671,22 @@ static struct target *get_cortex_a(struct target *target, int32_t coreid) } return target; } + static int cortex_a_halt(struct target *target); static int cortex_a_halt_smp(struct target *target) { - int retval = 0; + int retval = ERROR_OK; struct target_list *head; foreach_smp_target(head, target->smp_targets) { struct target *curr = head->target; if ((curr != target) && (curr->state != TARGET_HALTED) - && target_was_examined(curr)) - retval += cortex_a_halt(curr); + && target_was_examined(curr)) { + int retval1 = cortex_a_halt(curr); + if (retval == ERROR_OK) + retval = retval1; // save the first error and continue loop + } } return retval; } @@ -692,12 +696,12 @@ static int update_halt_gdb(struct target *target) struct target *gdb_target = NULL; struct target_list *head; struct target *curr; - int retval = 0; + int retval = ERROR_OK; if (target->gdb_service && target->gdb_service->core[0] == -1) { target->gdb_service->target = target; target->gdb_service->core[0] = target->coreid; - retval += cortex_a_halt_smp(target); + retval = cortex_a_halt_smp(target); } if (target->gdb_service) -- |
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From: <ge...@op...> - 2025-11-28 10:38:15
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This is an automated email from Gerrit. "Tomas Vanek <va...@fb...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9269 -- gerrit commit 0c97a09e3c8c935910e9826927c1cfe93dec9c02 Author: Tomas Vanek <va...@fb...> Date: Fri Nov 28 11:25:03 2025 +0100 target/aarch64, armv8: avoid adding of error return codes The arithmetic addition of the returned error codes was used as a lazy man's logical or. Handle error passing properly. Change-Id: I05f6d575dd7acb49cc3b3ca20b0e0b1f37d77ffe Signed-off-by: Tomas Vanek <va...@fb...> diff --git a/src/target/aarch64.c b/src/target/aarch64.c index ed9cb48aa7..bd3e26429f 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -2682,16 +2682,18 @@ static int aarch64_examine_first(struct target *target) retval = mem_ap_read_u32(armv8->debug_ap, armv8->debug_base + CPUV8_DBG_MEMFEATURE0, &tmp0); - retval += mem_ap_read_u32(armv8->debug_ap, - armv8->debug_base + CPUV8_DBG_MEMFEATURE0 + 4, &tmp1); + if (retval == ERROR_OK) + retval = mem_ap_read_u32(armv8->debug_ap, + armv8->debug_base + CPUV8_DBG_MEMFEATURE0 + 4, &tmp1); if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "Memory Model Type"); return retval; } retval = mem_ap_read_u32(armv8->debug_ap, armv8->debug_base + CPUV8_DBG_DBGFEATURE0, &tmp2); - retval += mem_ap_read_u32(armv8->debug_ap, - armv8->debug_base + CPUV8_DBG_DBGFEATURE0 + 4, &tmp3); + if (retval == ERROR_OK) + retval = mem_ap_read_u32(armv8->debug_ap, + armv8->debug_base + CPUV8_DBG_DBGFEATURE0 + 4, &tmp3); if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "ID_AA64DFR0_EL1"); return retval; diff --git a/src/target/armv8.c b/src/target/armv8.c index 47a380c9d5..11d55cdb48 100644 --- a/src/target/armv8.c +++ b/src/target/armv8.c @@ -205,7 +205,9 @@ static int armv8_read_ttbcr(struct target *target) retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_TCR_EL3, 0), &ttbcr); - retval += dpm->instr_read_data_r0_64(dpm, + if (retval != ERROR_OK) + goto done; + retval = dpm->instr_read_data_r0_64(dpm, ARMV8_MRS(SYSTEM_TTBR0_EL3, 0), &armv8->ttbr_base); if (retval != ERROR_OK) @@ -218,7 +220,9 @@ static int armv8_read_ttbcr(struct target *target) retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_TCR_EL2, 0), &ttbcr); - retval += dpm->instr_read_data_r0_64(dpm, + if (retval != ERROR_OK) + goto done; + retval = dpm->instr_read_data_r0_64(dpm, ARMV8_MRS(SYSTEM_TTBR0_EL2, 0), &armv8->ttbr_base); if (retval != ERROR_OK) @@ -234,12 +238,14 @@ static int armv8_read_ttbcr(struct target *target) retval = dpm->instr_read_data_r0_64(dpm, ARMV8_MRS(SYSTEM_TCR_EL1, 0), &ttbcr_64); + if (retval != ERROR_OK) + goto done; armv8->va_size = 64 - (ttbcr_64 & 0x3F); armv8->pa_size = armv8_pa_size((ttbcr_64 >> 32) & 7); armv8->page_size = (ttbcr_64 >> 14) & 3; armv8->armv8_mmu.ttbr1_used = (((ttbcr_64 >> 16) & 0x3F) != 0) ? 1 : 0; armv8->armv8_mmu.ttbr0_mask = 0x0000FFFFFFFFFFFFULL; - retval += dpm->instr_read_data_r0_64(dpm, + retval = dpm->instr_read_data_r0_64(dpm, ARMV8_MRS(SYSTEM_TTBR0_EL1 | (armv8->armv8_mmu.ttbr1_used), 0), &armv8->ttbr_base); if (retval != ERROR_OK) -- |
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From: <ge...@op...> - 2025-11-27 08:25:54
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This is an automated email from Gerrit. "Zane Liang <zhe...@sp...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9225 -- gerrit commit 2defbdfdaa1d6f47a2e1c8efe2a81d468ffd4097 Author: liangzhen <zhe...@sp...> Date: Thu Nov 27 15:59:17 2025 +0800 target/riscv: fix misa register extension usage Introduce the `riscv detect_misa` command, which temporarily enables all MISA extensions and transmits the target description. When accessing a register, if the register depends on a specific extension, its availability will be verified based on the current value of the misa register. Change-Id: I83d321046edb6df2c24711a8b47a6abd140f2947 Signed-off-by: liangzhen <zhe...@sp...> diff --git a/doc/openocd.texi b/doc/openocd.texi index 57f8703ad1..f124179a86 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -12037,6 +12037,11 @@ using the @var{riscv exec_progbuf} command to execute fences or CMO instructions (RISC-V Cache Management Operations). @end deffn +@deffn {Command} {riscv detect_misa} [on|off] +When on (default), during initialization, OpenOCD will reads the misa register, +sets it to all ones, and checks which extensions are supported. +@end deffn + @section ARC Architecture @cindex ARC diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 6fa5e025be..baaf2d7ff1 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1394,7 +1394,7 @@ static int fpr_read_progbuf(struct target *target, uint64_t *value, struct riscv_program program; riscv_program_init(&program, target); - if (riscv_supports_extension(target, 'D') && riscv_xlen(target) < 64) { + if (riscv_supports_extension(target, 'D', true) && riscv_xlen(target) < 64) { /* There are no instructions to move all the bits from a * register, so we need to use some scratch RAM. */ @@ -1403,7 +1403,7 @@ static int fpr_read_progbuf(struct target *target, uint64_t *value, return internal_register_read64_progbuf_scratch(target, &program, value); } if (riscv_program_insert(&program, - riscv_supports_extension(target, 'D') ? + riscv_supports_extension(target, 'D', true) ? fmv_x_d(S0, freg) : fmv_x_w(S0, freg)) != ERROR_OK) return ERROR_FAIL; @@ -1493,7 +1493,7 @@ static int fpr_write_progbuf(struct target *target, enum gdb_regno number, struct riscv_program program; riscv_program_init(&program, target); - if (riscv_supports_extension(target, 'D') && riscv_xlen(target) < 64) { + if (riscv_supports_extension(target, 'D', true) && riscv_xlen(target) < 64) { /* There are no instructions to move all the bits from a register, * so we need to use some scratch RAM. */ @@ -1506,7 +1506,7 @@ static int fpr_write_progbuf(struct target *target, enum gdb_regno number, return ERROR_FAIL; if (riscv_program_insert(&program, - riscv_supports_extension(target, 'D') ? + riscv_supports_extension(target, 'D', true) ? fmv_d_x(freg, S0) : fmv_w_x(freg, S0)) != ERROR_OK) return ERROR_FAIL; diff --git a/src/target/riscv/riscv-013_reg.c b/src/target/riscv/riscv-013_reg.c index b2b1a921f2..ad23ca3e28 100644 --- a/src/target/riscv/riscv-013_reg.c +++ b/src/target/riscv/riscv-013_reg.c @@ -19,7 +19,7 @@ static int riscv013_reg_get(struct reg *reg) /* TODO: Hack to deal with gdb that thinks these registers still exist. */ if (reg->number > GDB_REGNO_XPR15 && reg->number <= GDB_REGNO_XPR31 && - riscv_supports_extension(target, 'E')) { + riscv_supports_extension(target, 'E', true)) { buf_set_u64(reg->value, 0, reg->size, 0); return ERROR_OK; } @@ -54,7 +54,7 @@ static int riscv013_reg_set(struct reg *reg, uint8_t *buf) /* TODO: Hack to deal with gdb that thinks these registers still exist. */ if (reg->number > GDB_REGNO_XPR15 && reg->number <= GDB_REGNO_XPR31 && - riscv_supports_extension(target, 'E') && + riscv_supports_extension(target, 'E', true) && buf_get_u64(buf, 0, reg->size) == 0) return ERROR_OK; @@ -139,7 +139,7 @@ static int examine_vlenb(struct target *target) riscv_reg_t vlenb_val; if (riscv_reg_get(target, &vlenb_val, GDB_REGNO_VLENB) != ERROR_OK) { - if (riscv_supports_extension(target, 'V')) + if (riscv_supports_extension(target, 'V', true)) LOG_TARGET_WARNING(target, "Couldn't read vlenb; vector register access won't work."); r->vlenb = 0; return riscv_reg_impl_set_exist(target, GDB_REGNO_VLENB, false); @@ -184,7 +184,7 @@ unsigned int mxl_to_xlen(enum misa_mxl mxl) return 0; } -static int check_misa_mxl(const struct target *target) +static int check_misa(struct target *target) { RISCV_INFO(r); @@ -247,6 +247,25 @@ static int check_misa_mxl(const struct target *target) /* Display this as early as possible to help people who are using * really slow simulators. */ LOG_TARGET_DEBUG(target, " XLEN=%d, misa=0x%" PRIx64, riscv_xlen(target), r->misa); + + if (r->detect_misa) { + const riscv_reg_t misa_extensions_mask = (riscv_reg_t)(0x1 << 25) - 1; + riscv_reg_t misa = set_field(r->misa, misa_extensions_mask, misa_extensions_mask); + if (riscv_reg_set(target, GDB_REGNO_MISA, misa) != ERROR_OK) + return ERROR_FAIL; + + if (riscv_reg_get(target, &misa, GDB_REGNO_MISA) != ERROR_OK) + return ERROR_FAIL; + + if (misa != r->misa) { + LOG_TARGET_DEBUG(target, "Detected misa=0x%" PRIx64 "does not " + "equal to origin misa=0x%" PRIx64, misa, r->misa); + if (riscv_reg_set(target, GDB_REGNO_MISA, r->misa) != ERROR_OK) + return ERROR_FAIL; + r->misa = misa; + } + } + return ERROR_OK; } @@ -261,7 +280,7 @@ static int examine_misa(struct target *target) res = riscv_reg_get(target, &r->misa, GDB_REGNO_MISA); if (res != ERROR_OK) return res; - return check_misa_mxl(target); + return check_misa(target); } static int examine_mtopi(struct target *target) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 8054a1c9b7..ba0b0df8e3 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1165,7 +1165,8 @@ struct match_triggers_tdata1_fields { static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t2(struct target *target, struct trigger *trigger) { - RISCV_INFO(r); + bool misa_s = riscv_supports_extension(target, 'S', true); + bool misa_u = riscv_supports_extension(target, 'U', true); struct match_triggers_tdata1_fields result = { .common = @@ -1173,8 +1174,8 @@ static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t2( field_value(CSR_MCONTROL_DMODE(riscv_xlen(target)), 1) | field_value(CSR_MCONTROL_ACTION, CSR_MCONTROL_ACTION_DEBUG_MODE) | field_value(CSR_MCONTROL_M, 1) | - field_value(CSR_MCONTROL_S, !!(r->misa & BIT('S' - 'A'))) | - field_value(CSR_MCONTROL_U, !!(r->misa & BIT('U' - 'A'))) | + field_value(CSR_MCONTROL_S, misa_s) | + field_value(CSR_MCONTROL_U, misa_u) | field_value(CSR_MCONTROL_EXECUTE, trigger->is_execute) | field_value(CSR_MCONTROL_LOAD, trigger->is_read) | field_value(CSR_MCONTROL_STORE, trigger->is_write), @@ -1200,9 +1201,9 @@ static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t2( static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t6(struct target *target, struct trigger *trigger) { - bool misa_s = riscv_supports_extension(target, 'S'); - bool misa_u = riscv_supports_extension(target, 'U'); - bool misa_h = riscv_supports_extension(target, 'H'); + bool misa_s = riscv_supports_extension(target, 'S', true); + bool misa_u = riscv_supports_extension(target, 'U', true); + bool misa_h = riscv_supports_extension(target, 'H', true); struct match_triggers_tdata1_fields result = { .common = @@ -2192,8 +2193,8 @@ static int verify_loadstore(struct target *target, const riscv_insn_t instruction, bool *is_read) { uint32_t opcode = get_opcode(instruction); - bool misa_f = riscv_supports_extension(target, 'F'); - bool misa_d = riscv_supports_extension(target, 'D'); + bool misa_f = riscv_supports_extension(target, 'F', true); + bool misa_d = riscv_supports_extension(target, 'D', true); enum watchpoint_rw rw; switch (opcode) { @@ -5576,6 +5577,18 @@ COMMAND_HANDLER(handle_riscv_virt2phys_mode) return ERROR_OK; } +COMMAND_HANDLER(riscv_detect_misa) +{ + struct target *target = get_current_target(CMD_CTX); + RISCV_INFO(r); + + if (CMD_ARGC != 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + COMMAND_PARSE_ON_OFF(CMD_ARGV[0], r->detect_misa); + return ERROR_OK; +} + static const struct command_registration riscv_exec_command_handlers[] = { { .name = "dump_sample_buf", @@ -5838,6 +5851,14 @@ static const struct command_registration riscv_exec_command_handlers[] = { "When off, users need to take care of memory coherency themselves, for example by using " "`riscv exec_progbuf` to execute fence or CMO instructions." }, + { + .name = "detect_misa", + .handler = riscv_detect_misa, + .mode = COMMAND_CONFIG, + .usage = "[on|off]", + .help = "When on (default), during initialization, OpenOCD will reads the misa register, sets it to " + "all ones, and checks which extensions are supported." + }, { .chain = smp_command_handlers }, @@ -5978,6 +5999,8 @@ static void riscv_info_init(struct target *target, struct riscv_info *r) r->wp_allow_napot_trigger = true; r->autofence = true; + + r->detect_misa = true; } static int riscv_resume_go_all_harts(struct target *target) @@ -6044,7 +6067,7 @@ static int riscv_step_rtos_hart(struct target *target) return ERROR_OK; } -bool riscv_supports_extension(const struct target *target, char letter) +bool riscv_supports_extension(struct target *target, char letter, bool current) { RISCV_INFO(r); unsigned int num; @@ -6054,6 +6077,14 @@ bool riscv_supports_extension(const struct target *target, char letter) num = letter - 'A'; else return false; + + if (current) { + riscv_reg_t misa; + if (riscv_reg_get(target, &misa, GDB_REGNO_MISA) != ERROR_OK) + return false; + return misa & BIT(num); + } + return r->misa & BIT(num); } diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 2a0a9b95f0..186fb68241 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -365,6 +365,8 @@ struct riscv_info { bool wp_allow_ge_lt_trigger; bool autofence; + + bool detect_misa; }; enum riscv_priv_mode { @@ -457,7 +459,7 @@ int riscv_openocd_step( /*** RISC-V Interface ***/ -bool riscv_supports_extension(const struct target *target, char letter); +bool riscv_supports_extension(struct target *target, char letter, bool current); /* Returns XLEN for the given (or current) hart. */ unsigned int riscv_xlen(const struct target *target); diff --git a/src/target/riscv/riscv_reg.c b/src/target/riscv/riscv_reg.c index ba1bc2a858..096bed52ca 100644 --- a/src/target/riscv/riscv_reg.c +++ b/src/target/riscv/riscv_reg.c @@ -259,7 +259,7 @@ static bool gdb_regno_caller_save(uint32_t regno) (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31); } -static struct reg_data_type *gdb_regno_reg_data_type(const struct target *target, +static struct reg_data_type *gdb_regno_reg_data_type(struct target *target, uint32_t regno) { if (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) { @@ -284,7 +284,7 @@ static struct reg_data_type *gdb_regno_reg_data_type(const struct target *target .type_class = REG_TYPE_CLASS_UNION, {.reg_type_union = &single_double_union} }; - return riscv_supports_extension(target, 'D') ? + return riscv_supports_extension(target, 'D', false) ? &type_ieee_single_double : &type_ieee_single; } @@ -314,10 +314,10 @@ static const char *gdb_regno_group(uint32_t regno) return "custom"; } -uint32_t gdb_regno_size(const struct target *target, uint32_t regno) +uint32_t gdb_regno_size(struct target *target, uint32_t regno) { if (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) - return riscv_supports_extension(target, 'D') ? 64 : 32; + return riscv_supports_extension(target, 'D', false) ? 64 : 32; if (regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31) return riscv_vlenb(target) * 8; if (regno == GDB_REGNO_PRIV) @@ -365,7 +365,7 @@ static bool is_known_standard_csr(unsigned int csr_num) return is_csr_in_buf[csr_num]; } -bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno) +bool riscv_reg_impl_gdb_regno_exist(struct target *target, uint32_t regno) { switch (regno) { case GDB_REGNO_VLENB: @@ -383,9 +383,9 @@ bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno) regno == GDB_REGNO_PRIV) return true; if (regno > GDB_REGNO_XPR15 && regno <= GDB_REGNO_XPR31) - return !riscv_supports_extension(target, 'E'); + return !riscv_supports_extension(target, 'E', false); if (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) - return riscv_supports_extension(target, 'F'); + return riscv_supports_extension(target, 'F', false); if (regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31) return vlenb_exists(target); if (regno >= GDB_REGNO_COUNT) @@ -396,7 +396,7 @@ bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno) case CSR_FFLAGS: case CSR_FRM: case CSR_FCSR: - return riscv_supports_extension(target, 'F'); + return riscv_supports_extension(target, 'F', false); case CSR_VSTART: case CSR_VXSAT: case CSR_VXRM: @@ -414,14 +414,14 @@ bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno) case CSR_SCAUSE: case CSR_STVAL: case CSR_SATP: - return riscv_supports_extension(target, 'S'); + return riscv_supports_extension(target, 'S', false); case CSR_MEDELEG: case CSR_MIDELEG: /* "In systems with only M-mode, or with both M-mode and * U-mode but without U-mode trap support, the medeleg and * mideleg registers should not exist." */ - return riscv_supports_extension(target, 'S') || - riscv_supports_extension(target, 'N'); + return riscv_supports_extension(target, 'S', false) || + riscv_supports_extension(target, 'N', false); case CSR_PMPCFG1: case CSR_PMPCFG3: @@ -489,7 +489,7 @@ bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno) case CSR_MHPMCOUNTER31H: return riscv_xlen(target) == 32; case CSR_MCOUNTEREN: - return riscv_supports_extension(target, 'U'); + return riscv_supports_extension(target, 'U', false); /* Interrupts M-Mode CSRs. */ case CSR_MISELECT: case CSR_MIREG: @@ -503,21 +503,21 @@ bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno) case CSR_MVIPH: return reg_exists(target, GDB_REGNO_MTOPI) && riscv_xlen(target) == 32 && - riscv_supports_extension(target, 'S'); + riscv_supports_extension(target, 'S', false); /* Interrupts S-Mode CSRs. */ case CSR_SISELECT: case CSR_SIREG: case CSR_STOPI: return reg_exists(target, GDB_REGNO_MTOPI) && - riscv_supports_extension(target, 'S'); + riscv_supports_extension(target, 'S', false); case CSR_STOPEI: return reg_exists(target, GDB_REGNO_MTOPEI) && - riscv_supports_extension(target, 'S'); + riscv_supports_extension(target, 'S', false); case CSR_SIEH: case CSR_SIPH: return reg_exists(target, GDB_REGNO_MTOPI) && riscv_xlen(target) == 32 && - riscv_supports_extension(target, 'S'); + riscv_supports_extension(target, 'S', false); /* Interrupts Hypervisor and VS CSRs. */ case CSR_HVIEN: case CSR_HVICTL: @@ -527,10 +527,10 @@ bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno) case CSR_VSIREG: case CSR_VSTOPI: return reg_exists(target, GDB_REGNO_MTOPI) && - riscv_supports_extension(target, 'H'); + riscv_supports_extension(target, 'H', false); case CSR_VSTOPEI: return reg_exists(target, GDB_REGNO_MTOPEI) && - riscv_supports_extension(target, 'H'); + riscv_supports_extension(target, 'H', false); case CSR_HIDELEGH: case CSR_HVIENH: case CSR_HVIPH: @@ -540,7 +540,7 @@ bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno) case CSR_VSIPH: return reg_exists(target, GDB_REGNO_MTOPI) && riscv_xlen(target) == 32 && - riscv_supports_extension(target, 'H'); + riscv_supports_extension(target, 'H', false); } return is_known_standard_csr(csr_number); } diff --git a/src/target/riscv/riscv_reg_impl.h b/src/target/riscv/riscv_reg_impl.h index 17e66935be..76a7d03219 100644 --- a/src/target/riscv/riscv_reg_impl.h +++ b/src/target/riscv/riscv_reg_impl.h @@ -44,7 +44,7 @@ int riscv_reg_impl_init_cache_entry(struct target *target, uint32_t regno, * For most registers, returns whether they exist or not. * For some registers the "exist" bit should be set explicitly. */ -bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno); +bool riscv_reg_impl_gdb_regno_exist(struct target *target, uint32_t regno); /** Mark register as existing or not. */ int riscv_reg_impl_set_exist(const struct target *target, -- |
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From: Brandon A. <bal...@te...> - 2025-11-26 16:44:40
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Hi Tomas, Thanks for your reply! I mean that one can access the standard RISCV debug module/debug module interface through JTAG, however the standard DTM JTAG registers are not available (i.e. the Debug Module Interface Access and DTM Control and Status registers). There is a non-standard JTAG IR which can be used to access the DM/DMI. Thanks again, Brandon On Wed, Nov 26, 2025 at 9:17 AM Tomas Vanek <to...@us...> wrote: > Brandon, > > could you tell us more what you mean by "The target's JTAG interface does > expose a mechanism for creating memory accesses"? > > BTW See also recent discussion > https://sourceforge.net/p/openocd/mailman/openocd-devel/thread/CAAj6DX2tjx5893gJYK_LhWFAOt_J6XTG32DRkie4Wvw14h-_3A%40mail.gmail.com/#msg59241351 > about DM access over ADI MEM-AP > > Tomas > > > On 25/11/2025 17:56, Brandon Altieri wrote: > > Hello, > > I have a custom RISCV target that I need to enable OpenOCD (and more > specifically, gdb) support for. The target does not implement/use the > standard RISCV Debug Transport Module. > > Wondering if I can get some guidance on where to start here - I'm not so > sure if I'm able to simply override a couple functions (e.g. > dmi_write/dmi_read, dtmcs_scan, etc.) to enable this? The target's JTAG > interface does expose a mechanism for creating memory accesses where the > DM is reachable. > > Thanks in Advance, > > Brandon Altieri > > > |
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From: <ge...@op...> - 2025-11-26 15:31:43
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This is an automated email from Gerrit. "Holger Mößinger <gi...@ho...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9268 -- gerrit commit 7549c47647eb49cbca7a2c595a2e322ba246b994 Author: Holger Mößinger (hm2dev) <gi...@ho...> Date: Wed Nov 26 15:51:56 2025 +0100 tcl/board/nordic/* Unify nrf5xx recover functions Rewrite common.cfg to provide _nrf_check_ap_lock and _nrf_ctrl_ap_recover functions that can also be used for nrf54l.cfg. Add nrf54l_check_ap_lock and nrf54l_recover to nrf54l.cfg. Successfully tested on nRF54L15 hardware. Rewrite nrf52.cfg to use the functions from common.cfg. Update nrf91.cfg and nrf53.cfg to adapt to the changed parameter list of _nrf_check_ap_lock and _nrf_ctrl_ap_recover in common.cfg. Change-Id: I9083197d6365d31a6532a9ad39f9c958f3e75f07 Signed-off-by: Holger Mößinger (hm2dev) <gi...@ho...> diff --git a/tcl/target/nordic/common.cfg b/tcl/target/nordic/common.cfg index 2ae5011e4e..c34484b5eb 100644 --- a/tcl/target/nordic/common.cfg +++ b/tcl/target/nordic/common.cfg @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # -# Nordic nRF52, nRF53 and nRF91 CTRL-AP handling +# Nordic nRF52, nRF53, nRF91 and nrf54l CTRL-AP handling # if { [using_hla] } { @@ -14,68 +14,84 @@ if { [using_hla] } { } else { # Test if debug/MEM-AP is locked by UICR APPROTECT - proc _nrf_check_ap_lock { ctrl_ap_num unlocked_value } { + proc _nrf_check_ap_lock { ctrl_ap_num app_protect_register unlocked_value } { + set cmdname [lindex [info level 1] 0] + set recover_script_name [lindex [split $cmdname "_"] 0]_recover + set target [target current] + set dap [$target cget -dap] - set err [catch {set APPROTECTSTATUS [$dap apreg $ctrl_ap_num 0xc]}] - if {$err == 0 && $APPROTECTSTATUS < $unlocked_value} { - echo "" - echo "****** WARNING ******" - echo "\[$target\] device has AP lock engaged (see UICR APPROTECT register)." - echo "Debug access is denied." - echo "Use 'nrfxx_recover' to erase and unlock the device." - echo "" + set err [catch {set APPROTECTSTATUS [$dap apreg $ctrl_ap_num $app_protect_register]}] + if {$err == 0 && $APPROTECTSTATUS > $unlocked_value} { + echo "Warn : \[$cmdname\] " + echo "Warn : \[$cmdname\] ****** WARNING ******" + echo "Warn : \[$cmdname\] $target has AP lock engaged (see UICR APPROTECT register)." + echo "Warn : \[$cmdname\] Debug access is denied." + echo "Warn : \[$cmdname\] Use '${recover_script_name}' to erase and unlock the device." + echo "Warn : \[$cmdname\] " poll off return 1 + } else { + echo "Info : \[$cmdname\] Debug access on $target is allowed." } return 0 } # Mass erase and unlock the device using proprietary nRF CTRL-AP - proc _nrf_ctrl_ap_recover { ctrl_ap_num {is_cpunet 0} } { + proc _nrf_ctrl_ap_recover { ctrl_ap_num idr_value app_protect_register ready_to_reset_status reset_triger_value {is_cpunet 0} } { + + set cmdname [lindex [info level 1] 0] + set target [target current] set dap [$target cget -dap] set IDR [$dap apreg $ctrl_ap_num 0xfc] - if {$IDR != 0x12880000} { - echo "Error: Cannot access nRF CTRL-AP!" + if {$IDR != $idr_value} { + echo "Error: \[$cmdname\] Cannot access $target CTRL-AP!" return } poll off - - # Reset and trigger ERASEALL task - $dap apreg $ctrl_ap_num 4 0 + + set APPROTECTSTATUS [$dap apreg $ctrl_ap_num $app_protect_register] + if {$APPROTECTSTATUS == 0x0} { + echo "Info : \[$cmdname\] $target not locked. Skipping recovery." + return + } + + # Trigger the Erase all $dap apreg $ctrl_ap_num 4 1 - + for {set i 0} {1} {incr i} { - set ERASEALLSTATUS [$dap apreg $ctrl_ap_num 8] - if {$ERASEALLSTATUS == 0} { - echo "\[$target\] device has been successfully erased and unlocked." + set ERASEALLSTATUS [$dap apreg $ctrl_ap_num 0x8] + if {$ERASEALLSTATUS == $ready_to_reset_status} { + echo "Info : \[$cmdname\] $target is erased ready for reset." break } if {$i == 0} { - echo "Waiting for chip erase..." + echo "Info : \[$cmdname\] Waiting up to 5 seconds for $target to be erased and ready to reset..." } - if {$i >= 150} { - echo "Error: \[$target\] recovery failed." + if {$i >= 50} { + echo "Error: \[$cmdname\] $target recovery failed." break } sleep 100 } + + # Trigger the reset + $dap apreg $ctrl_ap_num 0 $reset_triger_value - # Assert reset - $dap apreg $ctrl_ap_num 0 1 + _nrf_check_ap_lock 2 $app_protect_register 0 # Deassert reset $dap apreg $ctrl_ap_num 0 0 - # Reset ERASEALL task + # Reset ERASEALL task $dap apreg $ctrl_ap_num 4 0 if { $is_cpunet } { - reset init } else { + reset init sleep 100 $target arp_examine poll on @@ -84,3 +100,6 @@ if { [using_hla] } { lappend _telnet_autocomplete_skip _nrf_check_ap_lock _nrf_ctrl_ap_recover } + + + \ No newline at end of file diff --git a/tcl/target/nordic/nrf52.cfg b/tcl/target/nordic/nrf52.cfg index 0703b18862..c5b5194aad 100644 --- a/tcl/target/nordic/nrf52.cfg +++ b/tcl/target/nordic/nrf52.cfg @@ -53,67 +53,22 @@ if { [using_hla] } { flash bank $_CHIPNAME.flash nrf5 0x00000000 0 1 1 $_TARGETNAME flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 1 1 $_TARGETNAME +source [find target/nordic/common.cfg] + # Test if MEM-AP is locked by UICR APPROTECT proc nrf52_check_ap_lock {} { - set dap [[target current] cget -dap] - set err [catch {set APPROTECTSTATUS [$dap apreg 1 0xc]}] - if {$err == 0 && $APPROTECTSTATUS != 1} { - echo "****** WARNING ******" - echo "nRF52 device has AP lock engaged (see UICR APPROTECT register)." - echo "Debug access is denied." - echo "Use 'nrf52_recover' to erase and unlock the device." - echo "" - poll off - } + #_nrf_check_ap_lock { ctrl_ap_num app_protect_register unlocked_value } + _nrf_check_ap_lock 1 0xc 0 } +add_help_text nrf52_check_ap_lock "Check lock status of nrf52" + # Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #1) # http://www.ebyte.com produces modules with nRF52 locked by default, # use nrf52_recover to enable flashing and debug. proc nrf52_recover {} { - set target [target current] - set dap [$target cget -dap] - - set IDR [$dap apreg 1 0xfc] - if {$IDR != 0x02880000} { - echo "Error: Cannot access nRF52 CTRL-AP!" - return - } - - poll off - - # Reset and trigger ERASEALL task - $dap apreg 1 4 0 - $dap apreg 1 4 1 - - for {set i 0} {1} {incr i} { - set ERASEALLSTATUS [$dap apreg 1 8] - if {$ERASEALLSTATUS == 0} { - echo "$target device has been successfully erased and unlocked." - break - } - if {$i == 0} { - echo "Waiting for chip erase..." - } - if {$i >= 150} { - echo "Error: $target recovery failed." - break - } - sleep 100 - } - - # Assert reset - $dap apreg 1 0 1 - - # Deassert reset - $dap apreg 1 0 0 - - # Reset ERASEALL task - $dap apreg 1 4 0 - - sleep 100 - $target arp_examine - poll on + #_nrf_ctrl_ap_recover { ctrl_ap_num idr_value app_protect_register ready_to_reset_status reset_triger_value {is_cpunet 0} } + _nrf_ctrl_ap_recover 1 0x02880000 0xc 0 1 0 } add_help_text nrf52_recover "Mass erase and unlock nRF52 device" diff --git a/tcl/target/nordic/nrf53.cfg b/tcl/target/nordic/nrf53.cfg index 0dcfd55eca..9bd98b1a13 100644 --- a/tcl/target/nordic/nrf53.cfg +++ b/tcl/target/nordic/nrf53.cfg @@ -79,8 +79,8 @@ if { ![using_hla] } { $_TARGETNAME_APP cortex_m reset_config sysresetreq $_TARGETNAME_NET cortex_m reset_config sysresetreq - $_TARGETNAME_APP configure -event examine-fail { _nrf_check_ap_lock 2 3 } - $_TARGETNAME_NET configure -event examine-fail { _nrf_check_ap_lock 3 3 } + $_TARGETNAME_APP configure -event examine-fail { _nrf_check_ap_lock 2 0xc 3 } + $_TARGETNAME_NET configure -event examine-fail { _nrf_check_ap_lock 3 0xc 3 } $_TARGETNAME_NET configure -event gdb-attach "_nrf53_cpunet_gdb_attach $_CHIPNAME" @@ -120,7 +120,7 @@ if { ![using_hla] } { $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 1 set err [catch {$_TARGETNAME_NET arp_examine}] if { $err } { - if { ![_nrf_check_ap_lock 3 3] } { + if { ![_nrf_check_ap_lock 3 0xc 3] } { echo "Error: \[$_TARGETNAME_NET\] examination failed" } return @@ -132,15 +132,17 @@ if { ![using_hla] } { $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0 $_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 0 } - + # Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #2 or #3) proc nrf53_cpuapp_recover {} { - _nrf_ctrl_ap_recover 2 + #_nrf_ctrl_ap_recover { ctrl_ap_num idr_value app_protect_register ready_to_reset_status reset_triger_value {is_cpunet 0} } + _nrf_ctrl_ap_recover 2 0x12880000 0xc 0 1 0 } add_help_text nrf53_cpuapp_recover "Mass erase flash and unlock nRF53 application CPU" proc nrf53_recover {} { - _nrf_ctrl_ap_recover 3 1 + #_nrf_ctrl_ap_recover { ctrl_ap_num idr_value app_protect_register ready_to_reset_status reset_triger_value {is_cpunet 0} } + _nrf_ctrl_ap_recover 3 0x12880000 0xc 0 1 1 } add_help_text nrf53_recover "Mass erase all device flash and unlock nRF53" } diff --git a/tcl/target/nordic/nrf54l.cfg b/tcl/target/nordic/nrf54l.cfg index 3e14055f14..eabd96a8b1 100644 --- a/tcl/target/nordic/nrf54l.cfg +++ b/tcl/target/nordic/nrf54l.cfg @@ -57,11 +57,36 @@ target create $_CHIPNAME.aux mem_ap -dap $_CHIPNAME.dap -ap-num 1 $_CHIPNAME.dap apsel 1 $_CHIPNAME.dap apcsw 0x01000000 0x01000000 +# Keep adapter speed less or equal 2000 kHz or flash programming fails! adapter speed 1000 # Use main processor as default target. targets $_TARGETNAME -if {![using_hla]} { +source [find target/nordic/common.cfg] + +#flash bank $_CHIPNAME.flash nrf54 0x00000000 0 0 0 $_TARGETNAME +#flash bank $_CHIPNAME.ficr nrf54 0x00FFC000 0 0 0 $_TARGETNAME +#flash bank $_CHIPNAME.uicr nrf54 0x00FFD000 0 0 0 $_TARGETNAME +#flash bank $_CHIPNAME.sicr nrf54 0x00FFE000 0 0 0 $_TARGETNAME + +#flash bank $_CHIPNAME.ext 0x00000000 0x01000000 2 2 $_TARGETNAME + +if { ![using_hla] } { + $_TARGETNAME cortex_m reset_config sysresetreq -} + $_TARGETNAME configure -event examine-fail nrf54l_check_ap_lock + + proc nrf54l_check_ap_lock {} { + #_nrf_check_ap_lock { ctrl_ap_num app_protect_register unlocked_value } + _nrf_check_ap_lock 2 0x14 0 + } + add_help_text nrf54l_check_ap_lock "Check lock status of nrf54l" + + proc nrf54l_recover {} { + #_nrf_ctrl_ap_recover { ctrl_ap_num idr_value app_protect_register ready_to_reset_status reset_triger_value {is_cpunet 0} } + _nrf_ctrl_ap_recover 2 0x32880000 0x14 1 2 1 + } + add_help_text nrf54l_recover "Mass erase all device flash and unlock nRF54l" + +} \ No newline at end of file diff --git a/tcl/target/nordic/nrf91.cfg b/tcl/target/nordic/nrf91.cfg index 64ed864e75..e806d42d9c 100644 --- a/tcl/target/nordic/nrf91.cfg +++ b/tcl/target/nordic/nrf91.cfg @@ -52,12 +52,13 @@ flash bank $_CHIPNAME.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME if { ![using_hla] } { $_TARGETNAME cortex_m reset_config sysresetreq - - $_TARGETNAME configure -event examine-fail { _nrf_check_ap_lock 4 3 } + + $_TARGETNAME configure -event examine-fail { _nrf_check_ap_lock 4 0xc 3 } } # Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #4) proc nrf91_recover {} { - _nrf_ctrl_ap_recover 4 + #_nrf_ctrl_ap_recover { ctrl_ap_num idr_value app_protect_register ready_to_reset_status reset_triger_value {is_cpunet 0} } + _nrf_ctrl_ap_recover 4 0x12880000 0xc 0 1 1 } add_help_text nrf91_recover "Mass erase and unlock nRF91 device" -- |
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From: Tomas V. <to...@us...> - 2025-11-26 14:15:56
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Brandon, could you tell us more what you mean by "The target's JTAG interface does expose a mechanism for creating memory accesses"? BTW See also recent discussion https://sourceforge.net/p/openocd/mailman/openocd-devel/thread/CAAj6DX2tjx5893gJYK_LhWFAOt_J6XTG32DRkie4Wvw14h-_3A%40mail.gmail.com/#msg59241351 about DM access over ADI MEM-AP Tomas On 25/11/2025 17:56, Brandon Altieri wrote: > Hello, > > I have a custom RISCV target that I need to enable OpenOCD (and more > specifically, gdb) support for. The target does not implement/use the > standard RISCV Debug Transport Module. > > Wondering if I can get some guidance on where to start here - I'm not > so sure if I'm able to simply override a couple functions (e.g. > dmi_write/dmi_read, dtmcs_scan, etc.) to enable this? The target's > JTAG interface does expose a mechanism for creating memory accesses > where the DM is reachable. > > Thanks in Advance, > > Brandon Altieri > |
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From: Evgeniy N. <evg...@sy...> - 2025-11-26 11:38:52
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Hi! IMHO, the best place to start is batch interface (target/riscv/batch.h). Currently all DMI operations go through here. This will not be enough though, there is also `dtmcs_scan()`. It's use is pretty specific to JTAG DTM. There is one use in `riscv.c` during examination to determine the version of the JTAG DTM and based on this figure out whether it's a RISC-V Debug Spec 0.11 or RISC-V Debug Spec 0.13+ target. It is also used twice in `riscv-013.c`. The first use is during examination to determine `abits` so that we can address the Debug Module on the DMI bus. The second one resets the DMI busy sticky error state. It seems to me you can just drop these calls to `dtmcs_scan()` for the prototype implementation. Please, consider sharing your efforts -- I would like to abstract the notion of RISC-V DTM into a separate object some time later. Looking at an alternative implementation will be of great help to figure out the interface to implement. Best regards, Evgeniy Naydanov ________________________________ From: Brandon Altieri <bal...@te...> Sent: Tuesday, November 25, 2025 7:56:40 PM To: ope...@li... Cc: Nicholas Chin Subject: Support for RISCV Target Without DTM Hello, I have a custom RISCV target that I need to enable OpenOCD (and more specifically, gdb) support for. The target does not implement/use the standard RISCV Debug Transport Module. Wondering if I can get some guidance on where to start here - I'm not so sure if I'm able to simply override a couple functions (e.g. dmi_write/dmi_read, dtmcs_scan, etc.) to enable this? The target's JTAG interface does expose a mechanism for creating memory accesses where the DM is reachable. Thanks in Advance, Brandon Altieri |
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From: Brandon A. <bal...@te...> - 2025-11-25 17:59:16
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Hello, I have a custom RISCV target that I need to enable OpenOCD (and more specifically, gdb) support for. The target does not implement/use the standard RISCV Debug Transport Module. Wondering if I can get some guidance on where to start here - I'm not so sure if I'm able to simply override a couple functions (e.g. dmi_write/dmi_read, dtmcs_scan, etc.) to enable this? The target's JTAG interface does expose a mechanism for creating memory accesses where the DM is reachable. Thanks in Advance, Brandon Altieri |
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From: <ge...@op...> - 2025-11-25 07:19:21
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This is an automated email from Gerrit. "zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9267 -- gerrit commit 0cdc9de8c1dc1cf916d094f86ec76d032db9f45f Author: Marc Schink <de...@za...> Date: Tue Nov 11 17:39:23 2025 +0100 adapter/gpio: Use command_print() instead of LOG_ERROR() Use command_print() in order to provide an error message to the caller. While at it, fix the return values. Change-Id: I0f8d3466ab2729d8cca6cf4c1cff51d67982c373 Signed-off-by: Marc Schink <de...@za...> diff --git a/src/jtag/adapter.c b/src/jtag/adapter.c index c30a26c87b..3f94ffec7f 100644 --- a/src/jtag/adapter.c +++ b/src/jtag/adapter.c @@ -957,8 +957,8 @@ COMMAND_HANDLER(adapter_gpio_config_handler) int gpio_idx = get_gpio_index(CMD_ARGV[0]); if (gpio_idx == -1) { - LOG_ERROR("adapter has no gpio named %s", CMD_ARGV[0]); - return ERROR_COMMAND_SYNTAX_ERROR; + command_print(CMD, "adapter has no gpio named %s", CMD_ARGV[0]); + return ERROR_COMMAND_ARGUMENT_INVALID; } if (CMD_ARGC == 1) { @@ -1077,9 +1077,9 @@ COMMAND_HANDLER(adapter_gpio_config_handler) } } - LOG_ERROR("illegal option for adapter %s %s: %s", + command_print(CMD, "illegal option for adapter %s %s: %s", CMD_NAME, gpio_map[gpio_idx].name, CMD_ARGV[i]); - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_COMMAND_ARGUMENT_INVALID; } /* Force swdio_dir init state to be compatible with swdio init state */ -- |
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From: <ge...@op...> - 2025-11-22 21:08:57
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This is an automated email from Gerrit. "Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9266 -- gerrit commit 8cbe10664925176d2ea836b2855b18b64fc7ca29 Author: Antonio Borneo <bor...@gm...> Date: Sat Nov 22 22:03:10 2025 +0100 server: fix a new double free() By reorganizing the free() of the service and its subfields, the patch reported in 'fixes' exposes a new double free(). Issue detected by 'scan-build'. Fix it. Fixes: 5ff384be086a ("semihosting: fix memory leak and double free") Change-Id: Ief4262e98c9ecdca39d4e2d77e7a0ea87cfa198c Signed-off-by: Antonio Borneo <bor...@gm...> diff --git a/src/server/server.c b/src/server/server.c index 494fd9da30..81d79d41b1 100644 --- a/src/server/server.c +++ b/src/server/server.c @@ -378,7 +378,6 @@ int remove_service(const char *name, const char *port) if (tmp->type != CONNECTION_STDINOUT) close_socket(tmp->fd); - free(tmp->priv); free_service(tmp); return ERROR_OK; -- |
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