openocd-devel — Discuss development of OpenOCD

[PATCH] Add cfi_spansion_write_words() function to speed up programming. - uses Unlock Bypass programming mode for a 45-50% speedup - hacks buffered write buffersize for spansion to allow 1024 byte buffers

[John M. <jg...@ma...>]

Signed-off-by: John McCarthy <jg...@ma...>
---
 src/flash/cfi.c |   72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 71 insertions(+), 1 deletions(-)

diff --git src/flash/cfi.c src/flash/cfi.c
index 5801109..4f87463 100644
--- src/flash/cfi.c
+++ src/flash/cfi.c
@@ -1595,7 +1595,7 @@ int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
 	return ERROR_OK;
 }
 
-int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
+int cfi_spansion_write_words_Buffered(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
 {
 	cfi_flash_bank_t *cfi_info = bank->driver_priv;
 	target_t *target = bank->target;
@@ -1663,6 +1663,66 @@ int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount,
 	return ERROR_OK;
 }
 
+int cfi_spansion_write_words_UnlockBypass(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
+{
+	u32 i;
+	int retval = ERROR_OK;
+	cfi_flash_bank_t *cfi_info = bank->driver_priv;
+	cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
+	target_t *target = bank->target;
+	u8 command[8];
+
+	/* Enter Unlock Bypass mode */
+	cfi_command(bank, 0xaa, command);
+	target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
+
+	cfi_command(bank, 0x55, command);
+	target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
+
+	cfi_command(bank, 0x20, command);
+	target->type->write_memory(target, flash_address(bank, 0, 0), bank->bus_width, 1, command);
+
+	for (i=0; i<wordcount; i++) {
+		cfi_command(bank, 0xA0, command);
+		target->type->write_memory(target, flash_address(bank, 0, 0), bank->bus_width, 1, command);
+
+		target->type->write_memory(target, address, bank->bus_width, 1, word);
+
+		if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
+		{
+			LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
+			retval = ERROR_FLASH_OPERATION_FAILED;
+			break;
+		}
+
+		word    += bank->bus_width;
+		address += bank->bus_width;
+	}
+
+	/* Exit Unlock Bypass mode */
+	cfi_command(bank, 0x90, command);
+	target->type->write_memory(target, flash_address(bank, 0, 0), bank->bus_width, 1, command);
+
+	cfi_command(bank, 0x00, command);
+	target->type->write_memory(target, flash_address(bank, 0, 0), bank->bus_width, 1, command);
+
+	return retval;
+}
+
+int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
+{
+	cfi_flash_bank_t *cfi_info = bank->driver_priv;
+
+	/*
+	 * TODO: detect flash parts with support for neither Buffered
+	 * nor UnlockBypass and return ERROR_FLASH_OPERATION_FAILED.
+	 */
+	if(cfi_info->max_buf_write_size == 0)
+		return cif_spansion_write_words_UnlockBypass(bank, word, wordcount, address);
+	else
+		return cif_spansion_write_words_Buffered(bank, word, wordcount, address);
+}
+
 int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
 {
 	cfi_flash_bank_t *cfi_info = bank->driver_priv;
@@ -1801,6 +1861,15 @@ int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 			u32 buffermask = buffersize-1;
 			u32 bufferwsize;
 
+			if(cfi_info->max_buf_write_size == 0 && cfi_info->pri_id == 2) {
+				/*
+ 				 * Spansion hack to allow Unlock Bypass writes on chips
+  				 * that don't support buffered writes
+  				 */
+				buffersize = 1UL << 10;
+				buffermask = buffersize-1;
+			}
+
 			switch(bank->chip_width)
 			{
 			case 4 : bufferwsize = buffersize / 4; break;
@@ -1810,6 +1879,7 @@ int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 				LOG_ERROR("Unsupported chip width %d", bank->chip_width);
 				return ERROR_FLASH_OPERATION_FAILED;
 			}
+			LOG_INFO("Using cfi_write_words with buffer size %u words (%u bytes)", bufferwsize, buffersize);
 
 			/* fall back to memory writes */
 			while (count >= bank->bus_width)
-- 
1.5.4.3


--=-uPA0ZKWhAY2SZc0vwnSX
Content-Disposition: attachment; filename=0007-Fix-typo-in-cfi_spansion_write_words-wrapper.patch
Content-Type: application/mbox; name=0007-Fix-typo-in-cfi_spansion_write_words-wrapper.patch
Content-Transfer-Encoding: 7bit

[PATCH] Don't retry failed DMA attempts - if this fails either we're making an invalid memory reference or we don't know what has happened - in either case it's better to fail right awway

[John M. <jg...@ma...>]

Signed-off-by: John McCarthy <jg...@ma...>
---
 src/target/mips32_dmaacc.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git src/target/mips32_dmaacc.h src/target/mips32_dmaacc.h
index 2383ee9..443fef8 100644
--- src/target/mips32_dmaacc.h
+++ src/target/mips32_dmaacc.h
@@ -32,7 +32,7 @@
 #define EJTAG_CTRL_DMA_WORD        0x00000100
 #define EJTAG_CTRL_DMA_TRIPLEBYTE  0x00000180
 
-#define RETRY_ATTEMPTS	4
+#define RETRY_ATTEMPTS	0
 
 extern int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);
 extern int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);
-- 
1.5.4.3


--=-fEFIwyACH0JLjaJO7JHF--

[PATCH] Make ejtag_info->ejtag_ctrl mostly readonly. - we never want to write back the value we've read from this register - should only set or clear bits explicitly - rename all ejtag_ctrl temps to ejtag_ctrl for consistancy

[John M. <jg...@ma...>]

Signed-off-by: John McCarthy <jg...@ma...>
---
 src/target/mips32_dmaacc.c |  108 ++++++++++++++++++++++----------------------
 src/target/mips32_pracc.c  |   22 +++++----
 src/target/mips_ejtag.c    |   13 +++---
 src/target/mips_m4k.c      |   13 +++---
 4 files changed, 80 insertions(+), 76 deletions(-)

diff --git src/target/mips32_dmaacc.c src/target/mips32_dmaacc.c
index 7ca6c29..ddcfb97 100644
--- src/target/mips32_dmaacc.c
+++ src/target/mips32_dmaacc.c
@@ -44,7 +44,7 @@
 static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data)
 {
 	u32 v;
-	u32 ctrl_reg;
+	u32 ejtag_ctrl;
 	int   retries = RETRY_ATTEMPTS;
 
 begin_ejtag_dma_read:
@@ -56,14 +56,14 @@ begin_ejtag_dma_read:
 
 	// Initiate DMA Read & set DSTRT
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-	ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-	mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
 	// Wait for DSTRT to Clear
 	do {
-		ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-		mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-	} while(ctrl_reg & EJTAG_CTRL_DSTRT);
+		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	// Read Data
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
@@ -71,9 +71,9 @@ begin_ejtag_dma_read:
 
 	// Clear DMA & Check DERR
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-	ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-	mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-	if (ctrl_reg  & EJTAG_CTRL_DERR)
+	ejtag_ctrl = ejtag_info->ejtag_ctrl;
+	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
 			printf("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
@@ -88,7 +88,7 @@ begin_ejtag_dma_read:
 static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data)
 {
 	u32 v;
-	u32 ctrl_reg;
+	u32 ejtag_ctrl;
 	int   retries = RETRY_ATTEMPTS;
 
 begin_ejtag_dma_read_h:
@@ -100,14 +100,14 @@ begin_ejtag_dma_read_h:
 
 	// Initiate DMA Read & set DSTRT
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-	ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-	mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
 	// Wait for DSTRT to Clear
 	do {
-		ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-		mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-	} while(ctrl_reg & EJTAG_CTRL_DSTRT);
+		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	// Read Data
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
@@ -115,9 +115,9 @@ begin_ejtag_dma_read_h:
 
 	// Clear DMA & Check DERR
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-	ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-	mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-	if (ctrl_reg  & EJTAG_CTRL_DERR)
+	ejtag_ctrl = ejtag_info->ejtag_ctrl;
+	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
 			printf("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
@@ -136,7 +136,7 @@ begin_ejtag_dma_read_h:
 static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, u8 *data)
 {
 	u32 v;
-	u32 ctrl_reg;
+	u32 ejtag_ctrl;
 	int   retries = RETRY_ATTEMPTS;
 
 begin_ejtag_dma_read_b:
@@ -148,14 +148,14 @@ begin_ejtag_dma_read_b:
 
 	// Initiate DMA Read & set DSTRT
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-	ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-	mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
 	// Wait for DSTRT to Clear
 	do {
-		ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-		mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-	} while(ctrl_reg & EJTAG_CTRL_DSTRT);
+		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	// Read Data
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
@@ -163,9 +163,9 @@ begin_ejtag_dma_read_b:
 
 	// Clear DMA & Check DERR
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-	ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-	mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-	if (ctrl_reg  & EJTAG_CTRL_DERR)
+	ejtag_ctrl = ejtag_info->ejtag_ctrl;
+	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
 			printf("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
@@ -188,7 +188,7 @@ begin_ejtag_dma_read_b:
 static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
 {
 	u32 v;
-	u32 ctrl_reg;
+	u32 ejtag_ctrl;
 	int   retries = RETRY_ATTEMPTS;
 
 begin_ejtag_dma_write:
@@ -205,20 +205,20 @@ begin_ejtag_dma_write:
 
 	// Initiate DMA Write & set DSTRT
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-	ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-	mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
 	// Wait for DSTRT to Clear
 	do {
-		ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-		mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-	} while(ctrl_reg & EJTAG_CTRL_DSTRT);
+		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	// Clear DMA & Check DERR
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-	ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-	mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-	if (ctrl_reg  & EJTAG_CTRL_DERR)
+	ejtag_ctrl = ejtag_info->ejtag_ctrl;
+	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
 			printf("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
@@ -233,7 +233,7 @@ begin_ejtag_dma_write:
 static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
 {
 	u32 v;
-	u32 ctrl_reg;
+	u32 ejtag_ctrl;
 	int   retries = RETRY_ATTEMPTS;
 
 
@@ -255,20 +255,20 @@ begin_ejtag_dma_write_h:
 
 	// Initiate DMA Write & set DSTRT
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-	ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-	mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
 	// Wait for DSTRT to Clear
 	do {
-		ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-		mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-	} while(ctrl_reg & EJTAG_CTRL_DSTRT);
+		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	// Clear DMA & Check DERR
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-	ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-	mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-	if (ctrl_reg  & EJTAG_CTRL_DERR)
+	ejtag_ctrl = ejtag_info->ejtag_ctrl;
+	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
 			printf("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
@@ -283,7 +283,7 @@ begin_ejtag_dma_write_h:
 static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
 {
 	u32 v;
-	u32 ctrl_reg;
+	u32 ejtag_ctrl;
 	int   retries = RETRY_ATTEMPTS;
 
 
@@ -306,20 +306,20 @@ begin_ejtag_dma_write_b:
 
 	// Initiate DMA Write & set DSTRT
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-	ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-	mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
 	// Wait for DSTRT to Clear
 	do {
-		ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-		mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-	} while(ctrl_reg & EJTAG_CTRL_DSTRT);
+		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	// Clear DMA & Check DERR
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-	ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-	mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-	if (ctrl_reg  & EJTAG_CTRL_DERR)
+	ejtag_ctrl = ejtag_info->ejtag_ctrl;
+	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
 			printf("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
diff --git src/target/mips32_pracc.c src/target/mips32_pracc.c
index 5f8b0ce..8e17e05 100644
--- src/target/mips32_pracc.c
+++ src/target/mips32_pracc.c
@@ -47,7 +47,7 @@ static int wait_for_pracc_rw(mips_ejtag_t *ejtag_info, u32 *ctrl)
 	while (1) 
 	{
 		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-		ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
+		ejtag_ctrl = ejtag_info->ejtag_ctrl;
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 		if (ejtag_ctrl & EJTAG_CTRL_PRACC)
 			break;
@@ -61,8 +61,9 @@ static int wait_for_pracc_rw(mips_ejtag_t *ejtag_info, u32 *ctrl)
 
 static int mips32_pracc_exec_read(mips32_pracc_context *ctx, u32 address)
 {
+	mips_ejtag_t *ejtag_info = ctx->ejtag_info;
 	int offset;
-	u32 ctrl, data;
+	u32 ejtag_ctrl, data;
 
 	if ((address >= MIPS32_PRACC_PARAM_IN)
 		&& (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4))
@@ -102,25 +103,26 @@ static int mips32_pracc_exec_read(mips32_pracc_context *ctx, u32 address)
 	mips_ejtag_drscan_32(ctx->ejtag_info, &data);
 
 	/* Clear the access pending bit (let the processor eat!) */
-	ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
+	ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
 	mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL);
-	mips_ejtag_drscan_32(ctx->ejtag_info, &ctrl);
+	mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl);
 	
 	return ERROR_OK;
 }
 
 static int mips32_pracc_exec_write(mips32_pracc_context *ctx, u32 address)
 {
-	u32 ctrl,data;
+	u32 ejtag_ctrl,data;
 	int offset;
+	mips_ejtag_t *ejtag_info = ctx->ejtag_info;
 	
 	mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL);
 	mips_ejtag_drscan_32(ctx->ejtag_info, &data);
 	
 	/* Clear access pending bit */
-	ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
+	ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
 	mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL);
-	mips_ejtag_drscan_32(ctx->ejtag_info, &ctrl);
+	mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl);
 	
 	if ((address >= MIPS32_PRACC_PARAM_IN)
 		&& (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4))
@@ -150,7 +152,7 @@ static int mips32_pracc_exec_write(mips32_pracc_context *ctx, u32 address)
 
 int mips32_pracc_exec( mips_ejtag_t *ejtag_info, int code_len, u32 *code, int num_param_in, u32 *param_in, int num_param_out, u32 *param_out, int cycle)
 {
-	u32 ctrl;
+	u32 ejtag_ctrl;
 	u32 address, data;
 	mips32_pracc_context ctx;
 	int retval;
@@ -167,7 +169,7 @@ int mips32_pracc_exec( mips_ejtag_t *ejtag_info, int code_len, u32 *code, int nu
 	
 	while (1)
 	{
-		if ((retval = wait_for_pracc_rw(ejtag_info, &ctrl)) != ERROR_OK)
+		if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK)
 			return retval;
 		
 		address = data = 0;
@@ -175,7 +177,7 @@ int mips32_pracc_exec( mips_ejtag_t *ejtag_info, int code_len, u32 *code, int nu
 		mips_ejtag_drscan_32(ejtag_info, &address);
 		
 		/* Check for read or write */
-		if (ctrl & EJTAG_CTRL_PRNW)
+		if (ejtag_ctrl & EJTAG_CTRL_PRNW)
 		{
 			if ((retval = mips32_pracc_exec_write(&ctx, address)) != ERROR_OK)
 				return retval;
diff --git src/target/mips_ejtag.c src/target/mips_ejtag.c
index 6e6bd93..09470b0 100644
--- src/target/mips_ejtag.c
+++ src/target/mips_ejtag.c
@@ -194,18 +194,19 @@ int mips_ejtag_config_step(mips_ejtag_t *ejtag_info, int enable_step)
 
 int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info)
 {
+	u32 ejtag_ctrl;
 	jtag_add_end_state(TAP_RTI);
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 	
 	/* set debug break bit */
-	ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV | EJTAG_CTRL_JTAGBRK;
-	mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
+	ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
+	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	
 	/* break bit will be cleared by hardware */
-	ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
-	mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
-	LOG_DEBUG("ejtag_ctrl: 0x%8.8x", ejtag_info->ejtag_ctrl);
-	if((ejtag_info->ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
+	ejtag_ctrl = ejtag_info->ejtag_ctrl;
+	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+	LOG_DEBUG("ejtag_ctrl: 0x%8.8x", ejtag_ctrl);
+	if((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
 		LOG_DEBUG("Failed to enter Debug Mode!");
 	
 	return ERROR_OK;
diff --git src/target/mips_m4k.c src/target/mips_m4k.c
index 3508ebd..be7f59e 100644
--- src/target/mips_m4k.c
+++ src/target/mips_m4k.c
@@ -132,13 +132,14 @@ int mips_m4k_poll(target_t *target)
 	int retval;
 	mips32_common_t *mips32 = target->arch_info;
 	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+	u32 ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	
 	/* read ejtag control reg */
 	jtag_add_end_state(TAP_RTI);
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-	mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
+	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	
-	if (ejtag_info->ejtag_ctrl & EJTAG_CTRL_BRKST)
+	if (ejtag_ctrl & EJTAG_CTRL_BRKST)
 	{
 		if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 		{
@@ -167,19 +168,19 @@ int mips_m4k_poll(target_t *target)
 		target->state = TARGET_RUNNING;
 	}
 	
-	if (ejtag_info->ejtag_ctrl & EJTAG_CTRL_ROCC)
+	if (ejtag_ctrl & EJTAG_CTRL_ROCC)
 	{
 		/* we have detected a reset, clear flag
 		 * otherwise ejtag will not work */
 		jtag_add_end_state(TAP_RTI);
-		ejtag_info->ejtag_ctrl &= ~EJTAG_CTRL_ROCC;
+		ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
 		
 		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-		mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
+		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 		LOG_DEBUG("Reset Detected");
 	}
 	
-//	LOG_DEBUG("ctrl=0x%08X", ejtag_info->ejtag_ctrl);
+//	LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
 	
 	return ERROR_OK;
 }
-- 
1.5.4.3


--=-fEFIwyACH0JLjaJO7JHF
Content-Disposition: attachment; filename=0005-Don-t-retry-failed-DMA-attempts.patch
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[PATCH] Issue peripheral reset as well as system reset. - seems to make BMC5352 happier out of reset

[John M. <jg...@ma...>]

Signed-off-by: John McCarthy <jg...@ma...>
---
 src/target/mips_m4k.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git src/target/mips_m4k.c src/target/mips_m4k.c
index fc4c27e..7bc67e6 100644
--- src/target/mips_m4k.c
+++ src/target/mips_m4k.c
@@ -256,7 +256,7 @@ int mips_m4k_assert_reset(target_t *target)
 	}
 	
 	if (strcmp(target->variant, "ejtag_srst") == 0) {
-		u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST;
+		u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
 		LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
 		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-- 
1.5.4.3


--=-jQXXyjaE2kP0Sf0RqNT3--