openocd-devel — Discuss development of OpenOCD

[PATCH 4/7] semihosting: move semihosting cmd to arm cmd group

[Spencer O. <nt...@us...>]

Move arm7_9 semihosting to the arm cmd group - now arm semihosting.
Add setup_semihosting callback for configuring core semihosting support.

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/target/arm.h           |    2 +
 src/target/arm7_9_common.c |   60 +++++++++++--------------------------------
 src/target/armv4_5.c       |   48 +++++++++++++++++++++++++++++++++++
 src/target/armv7m.c        |    3 --
 4 files changed, 66 insertions(+), 47 deletions(-)

diff --git a/src/target/arm.h b/src/target/arm.h
index 6b304e9..ee4bd76 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -132,6 +132,8 @@ struct arm {
 	/** Value to be returned by semihosting SYS_ERRNO request. */
 	int semihosting_errno;
 
+	int (*setup_semihosting)(struct target *target, int enable);
+
 	/** Backpointer to the target. */
 	struct target *target;
 
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 2176729..f9deb83 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2834,54 +2834,32 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
 	return ERROR_OK;
 }
 
-COMMAND_HANDLER(handle_arm7_9_semihosting_command)
+int arm7_9_setup_semihosting(struct target *target, int enable)
 {
-	struct target *target = get_current_target(CMD_CTX);
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
 	if (!is_arm7_9(arm7_9))
 	{
-		command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
+		LOG_USER("current target isn't an ARM7/ARM9 target");
 		return ERROR_TARGET_INVALID;
 	}
 
-	if (CMD_ARGC > 0)
-	{
-		int semihosting;
-
-		COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
-
-		if (!target_was_examined(target))
-		{
-			LOG_ERROR("Target not examined yet");
-			return ERROR_FAIL;
-		}
-
-		if (arm7_9->has_vector_catch) {
-			struct reg *vector_catch = &arm7_9->eice_cache
-					->reg_list[EICE_VEC_CATCH];
-
-			if (!vector_catch->valid)
-				embeddedice_read_reg(vector_catch);
-			buf_set_u32(vector_catch->value, 2, 1, semihosting);
-			embeddedice_store_reg(vector_catch);
-		} else {
-			/* TODO: allow optional high vectors and/or BKPT_HARD */
-			if (semihosting)
-				breakpoint_add(target, 8, 4, BKPT_SOFT);
-			else
-				breakpoint_remove(target, 8); 
-		}
-
-		/* FIXME never let that "catch" be dropped! */
-		arm7_9->armv4_5_common.is_semihosting = semihosting;
+	if (arm7_9->has_vector_catch) {
+		struct reg *vector_catch = &arm7_9->eice_cache
+				->reg_list[EICE_VEC_CATCH];
 
+		if (!vector_catch->valid)
+			embeddedice_read_reg(vector_catch);
+		buf_set_u32(vector_catch->value, 2, 1, enable);
+		embeddedice_store_reg(vector_catch);
+	} else {
+		/* TODO: allow optional high vectors and/or BKPT_HARD */
+		if (enable)
+			breakpoint_add(target, 8, 4, BKPT_SOFT);
+		else
+			breakpoint_remove(target, 8);
 	}
 
-	command_print(CMD_CTX, "semihosting is %s",
-			arm7_9->armv4_5_common.is_semihosting
-			? "enabled" : "disabled");
-
 	return ERROR_OK;
 }
 
@@ -2906,6 +2884,7 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
 	armv4_5->read_core_reg = arm7_9_read_core_reg;
 	armv4_5->write_core_reg = arm7_9_write_core_reg;
 	armv4_5->full_context = arm7_9_full_context;
+	armv4_5->setup_semihosting = arm7_9_setup_semihosting;
 
 	retval = arm_init_arch_info(target, armv4_5);
 	if (retval != ERROR_OK)
@@ -2939,13 +2918,6 @@ static const struct command_registration arm7_9_any_command_handlers[] = {
 		.usage = "['enable'|'disable']",
 		.help = "use DCC downloads for larger memory writes",
 	},
-	{
-		"semihosting",
-		.handler = handle_arm7_9_semihosting_command,
-		.mode = COMMAND_EXEC,
-		.usage = "['enable'|'disable']",
-		.help = "activate support for semihosting operations",
-	},
 	COMMAND_REGISTRATION_DONE
 };
 const struct command_registration arm7_9_command_handlers[] = {
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index a4a15b4..5d814f2 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -794,6 +794,47 @@ usage:
 	return retval;
 }
 
+COMMAND_HANDLER(handle_arm_semihosting_command)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	struct arm *arm = target ? target_to_arm(target) : NULL;
+
+	if (!is_arm(arm)) {
+		command_print(CMD_CTX, "current target isn't an ARM");
+		return ERROR_FAIL;
+	}
+
+	if (CMD_ARGC > 0)
+	{
+		int semihosting;
+
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
+
+		if (!target_was_examined(target))
+		{
+			LOG_ERROR("Target not examined yet");
+			return ERROR_FAIL;
+		}
+
+		if (arm->setup_semihosting)
+		{
+			if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
+				LOG_ERROR("Failed to Configure semihosting");
+				return ERROR_FAIL;
+			}
+
+			/* FIXME never let that "catch" be dropped! */
+			arm->is_semihosting = semihosting;
+		}
+	}
+
+	command_print(CMD_CTX, "semihosting is %s",
+			arm->is_semihosting
+			? "enabled" : "disabled");
+
+	return ERROR_OK;
+}
+
 static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 {
 	struct command_context *context;
@@ -959,6 +1000,13 @@ static const struct command_registration arm_exec_command_handlers[] = {
 		.help = "read coprocessor register",
 		.usage = "cpnum op1 CRn op2 CRm",
 	},
+	{
+		"semihosting",
+		.handler = handle_arm_semihosting_command,
+		.mode = COMMAND_EXEC,
+		.usage = "['enable'|'disable']",
+		.help = "activate support for semihosting operations",
+	},
 
 	COMMAND_REGISTRATION_DONE
 };
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index ec11176..056ac7b 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -878,9 +878,6 @@ static const struct command_registration armv7m_exec_command_handlers[] = {
 };
 const struct command_registration armv7m_command_handlers[] = {
 	{
-		.chain = arm_command_handlers,
-	},
-	{
 		.name = "dap",
 		.mode = COMMAND_EXEC,
 		.help = "Cortex DAP command group",
-- 
1.6.5.1.1367.gcd48


--------------060608010801070405080908--

[PATCH 3/7] armv7m: add missing command chain

[Spencer O. <nt...@us...>]

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/target/armv7m.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 056ac7b..ec11176 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -878,6 +878,9 @@ static const struct command_registration armv7m_exec_command_handlers[] = {
 };
 const struct command_registration armv7m_command_handlers[] = {
 	{
+		.chain = arm_command_handlers,
+	},
+	{
 		.name = "dap",
 		.mode = COMMAND_EXEC,
 		.help = "Cortex DAP command group",
-- 
1.6.5.1.1367.gcd48


--------------070300060308020002060004--

[PATCH 5/7] docs: rename arm7_9 semihosting to arm semihosting

[Spencer O. <nt...@us...>]

Signed-off-by: Spencer Oliver <nt...@us...>
---
 doc/openocd.texi |   24 ++++++++++++------------
 1 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 61e39b2..9951ec7 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6004,6 +6004,18 @@ Display a table of all banked core registers, fetching the current value from ev
 core mode if necessary.
 @end deffn
 
+@deffn Command {arm semihosting} [@option{enable}|@option{disable}]
+@cindex ARM semihosting
+Display status of semihosting, after optionally changing that status.
+
+Semihosting allows for code executing on an ARM target to use the
+I/O facilities on the host computer i.e. the system where OpenOCD
+is running. The target application must be linked against a library
+implementing the ARM semihosting convention that forwards operation
+requests by using a special SVC instruction that is trapped at the
+Supervisor Call vector by OpenOCD.
+@end deffn
+
 @section ARMv4 and ARMv5 Architecture
 @cindex ARMv4
 @cindex ARMv5
@@ -6056,18 +6068,6 @@ cables (FT2232), but might be unsafe if used with targets running at very low
 speeds, like the 32kHz startup clock of an AT91RM9200.
 @end deffn
 
-@deffn Command {arm7_9 semihosting} [@option{enable}|@option{disable}]
-@cindex ARM semihosting
-Display status of semihosting, after optionally changing that status.
-
-Semihosting allows for code executing on an ARM target to use the
-I/O facilities on the host computer i.e. the system where OpenOCD
-is running. The target application must be linked against a library
-implementing the ARM semihosting convention that forwards operation
-requests by using a special SVC instruction that is trapped at the
-Supervisor Call vector by OpenOCD.
-@end deffn
-
 @subsection ARM720T specific commands
 @cindex ARM720T
 
-- 
1.6.5.1.1367.gcd48


--------------060608050700030906040403--

[PATCH 2/7] MIPS: add mips algorithm support

[Spencer O. <nt...@us...>]

 - add mips support for target algorithms.
 - added handlers for target_checksum_memory and target_blank_check_memory.
 - clean up long lines

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/target/mips32.c       |  315 ++++++++++++++++++++++++++++++++++++++++++++-
 src/target/mips32.h       |   10 ++
 src/target/mips32_pracc.c |    3 +-
 src/target/mips_m4k.c     |  146 ++++++++++-----------
 4 files changed, 392 insertions(+), 82 deletions(-)

diff --git a/src/target/mips32.c b/src/target/mips32.c
index 5bb4104..b0cb79c 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -27,6 +27,8 @@
 #endif
 
 #include "mips32.h"
+#include "breakpoints.h"
+#include "algorithm.h"
 #include "register.h"
 
 char* mips32_core_reg_list[] =
@@ -319,9 +321,168 @@ int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, s
 	return ERROR_OK;
 }
 
-int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
+/* run to exit point. return error if exit point was not reached. */
+static int mips32_run_and_wait(struct target *target, uint32_t entry_point,
+		int timeout_ms, uint32_t exit_point, struct mips32_common *mips32)
 {
-	/*TODO*/
+	uint32_t pc;
+	int retval;
+	/* This code relies on the target specific  resume() and  poll()->debug_entry()
+	 * sequence to write register values to the processor and the read them back */
+	if ((retval = target_resume(target, 0, entry_point, 0, 1)) != ERROR_OK)
+	{
+		return retval;
+	}
+
+	retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
+	/* If the target fails to halt due to the breakpoint, force a halt */
+	if (retval != ERROR_OK || target->state != TARGET_HALTED)
+	{
+		if ((retval = target_halt(target)) != ERROR_OK)
+			return retval;
+		if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
+		{
+			return retval;
+		}
+		return ERROR_TARGET_TIMEOUT;
+	}
+
+	pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
+	if (pc != exit_point)
+	{
+		LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
+		return ERROR_TARGET_TIMEOUT;
+	}
+
+	return ERROR_OK;
+}
+
+int mips32_run_algorithm(struct target *target, int num_mem_params,
+		struct mem_param *mem_params, int num_reg_params,
+		struct reg_param *reg_params, uint32_t entry_point,
+		uint32_t exit_point, int timeout_ms, void *arch_info)
+{
+	struct mips32_common *mips32 = target_to_mips32(target);
+	struct mips32_algorithm *mips32_algorithm_info = arch_info;
+	enum mips32_isa_mode isa_mode = mips32->isa_mode;
+
+	uint32_t context[MIPS32NUMCOREREGS];
+	int i;
+	int retval = ERROR_OK;
+
+	LOG_DEBUG("Running algorithm");
+
+	/* NOTE: mips32_run_algorithm requires that each algorithm uses a software breakpoint
+	 * at the exit point */
+
+	if (mips32->common_magic != MIPS32_COMMON_MAGIC)
+	{
+		LOG_ERROR("current target isn't a MIPS32 target");
+		return ERROR_TARGET_INVALID;
+	}
+
+	if (target->state != TARGET_HALTED)
+	{
+		LOG_WARNING("target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	/* refresh core register cache */
+	for (unsigned i = 0; i < MIPS32NUMCOREREGS; i++)
+	{
+		if (!mips32->core_cache->reg_list[i].valid)
+			mips32->read_core_reg(target, i);
+		context[i] = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
+	}
+
+	for (i = 0; i < num_mem_params; i++)
+	{
+		if ((retval = target_write_buffer(target, mem_params[i].address,
+				mem_params[i].size, mem_params[i].value)) != ERROR_OK)
+		{
+			return retval;
+		}
+	}
+
+	for (int i = 0; i < num_reg_params; i++)
+	{
+		struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
+
+		if (!reg)
+		{
+			LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+			return ERROR_INVALID_ARGUMENTS;
+		}
+
+		if (reg->size != reg_params[i].size)
+		{
+			LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
+					reg_params[i].reg_name);
+			return ERROR_INVALID_ARGUMENTS;
+		}
+
+		mips32_set_core_reg(reg, reg_params[i].value);
+	}
+
+	mips32->isa_mode = mips32_algorithm_info->isa_mode;
+
+	retval = mips32_run_and_wait(target, entry_point, timeout_ms, exit_point, mips32);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	for (i = 0; i < num_mem_params; i++)
+	{
+		if (mem_params[i].direction != PARAM_OUT)
+		{
+			if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size,
+					mem_params[i].value)) != ERROR_OK)
+			{
+				return retval;
+			}
+		}
+	}
+
+	for (i = 0; i < num_reg_params; i++)
+	{
+		if (reg_params[i].direction != PARAM_OUT)
+		{
+			struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
+			if (!reg)
+			{
+				LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+				return ERROR_INVALID_ARGUMENTS;
+			}
+
+			if (reg->size != reg_params[i].size)
+			{
+				LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
+						reg_params[i].reg_name);
+				return ERROR_INVALID_ARGUMENTS;
+			}
+
+			buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
+		}
+	}
+
+	/* restore everything we saved before */
+	for (i = 0; i < MIPS32NUMCOREREGS; i++)
+	{
+		uint32_t regvalue;
+		regvalue = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
+		if (regvalue != context[i])
+		{
+			LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
+				mips32->core_cache->reg_list[i].name, context[i]);
+			buf_set_u32(mips32->core_cache->reg_list[i].value,
+					0, 32, context[i]);
+			mips32->core_cache->reg_list[i].valid = 1;
+			mips32->core_cache->reg_list[i].dirty = 1;
+		}
+	}
+
+	mips32->isa_mode = isa_mode;
+
 	return ERROR_OK;
 }
 
@@ -397,7 +558,8 @@ int mips32_configure_break_unit(struct target *target)
 			return retval;
 	}
 
-	LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
+	LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,
+			mips32->num_data_bpoints);
 
 	mips32->bp_scanned = 1;
 
@@ -441,3 +603,150 @@ int mips32_enable_interrupts(struct target *target, int enable)
 
 	return ERROR_OK;
 }
+
+int mips32_checksum_memory(struct target *target, uint32_t address,
+		uint32_t count, uint32_t* checksum)
+{
+	struct working_area *crc_algorithm;
+	struct reg_param reg_params[2];
+	struct mips32_algorithm mips32_info;
+	int retval;
+	uint32_t i;
+
+	static const uint32_t mips_crc_code[] =
+	{
+		0x248C0000,		/* addiu 	$t4, $a0, 0 */
+		0x24AA0000,		/* addiu	$t2, $a1, 0 */
+		0x2404FFFF,		/* addiu	$a0, $zero, 0xffffffff */
+		0x10000010,		/* beq		$zero, $zero, ncomp */
+		0x240B0000,		/* addiu	$t3, $zero, 0 */
+						/* nbyte: */
+		0x81850000,		/* lb		$a1, ($t4) */
+		0x218C0001,		/* addi		$t4, $t4, 1 */
+		0x00052E00,		/* sll		$a1, $a1, 24 */
+		0x3C0204C1,		/* lui		$v0, 0x04c1 */
+		0x00852026,		/* xor		$a0, $a0, $a1 */
+		0x34471DB7,		/* ori		$a3, $v0, 0x1db7 */
+		0x00003021,		/* addu		$a2, $zero, $zero */
+						/* loop: */
+		0x00044040,		/* sll		$t0, $a0, 1 */
+		0x24C60001,		/* addiu	$a2, $a2, 1 */
+		0x28840000,		/* slti		$a0, $a0, 0 */
+		0x01074826,		/* xor		$t1, $t0, $a3 */
+		0x0124400B,		/* movn		$t0, $t1, $a0 */
+		0x28C30008,		/* slti		$v1, $a2, 8 */
+		0x1460FFF9,		/* bne		$v1, $zero, loop */
+		0x01002021,		/* addu		$a0, $t0, $zero */
+						/* ncomp: */
+		0x154BFFF0,		/* bne		$t2, $t3, nbyte */
+		0x256B0001,		/* addiu	$t3, $t3, 1 */
+		0x7000003F,		/* sdbbp */
+	};
+
+	/* make sure we have a working area */
+	if (target_alloc_working_area(target, sizeof(mips_crc_code), &crc_algorithm) != ERROR_OK)
+	{
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	}
+
+	/* convert flash writing code into a buffer in target endianness */
+	for (i = 0; i < ARRAY_SIZE(mips_crc_code); i++)
+		target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), mips_crc_code[i]);
+
+	mips32_info.common_magic = MIPS32_COMMON_MAGIC;
+	mips32_info.isa_mode = MIPS32_ISA_MIPS32;
+
+	init_reg_param(&reg_params[0], "a0", 32, PARAM_IN_OUT);
+	buf_set_u32(reg_params[0].value, 0, 32, address);
+
+	init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT);
+	buf_set_u32(reg_params[1].value, 0, 32, count);
+
+	if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
+			crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code)-4), 10000,
+			&mips32_info)) != ERROR_OK)
+	{
+		destroy_reg_param(&reg_params[0]);
+		destroy_reg_param(&reg_params[1]);
+		target_free_working_area(target, crc_algorithm);
+		return 0;
+	}
+
+	*checksum = buf_get_u32(reg_params[0].value, 0, 32);
+
+	destroy_reg_param(&reg_params[0]);
+	destroy_reg_param(&reg_params[1]);
+
+	target_free_working_area(target, crc_algorithm);
+
+	return ERROR_OK;
+}
+
+/** Checks whether a memory region is zeroed. */
+int mips32_blank_check_memory(struct target *target,
+		uint32_t address, uint32_t count, uint32_t* blank)
+{
+	struct working_area *erase_check_algorithm;
+	struct reg_param reg_params[3];
+	struct mips32_algorithm mips32_info;
+	int retval;
+	uint32_t i;
+
+	static const uint32_t erase_check_code[] =
+	{
+						/* nbyte: */
+		0x80880000,		/* lb		$t0, ($a0) */
+		0x00C83024,		/* and		$a2, $a2, $t0 */
+		0x24A5FFFF,		/* addiu	$a1, $a1, -1 */
+		0x14A0FFFC,		/* bne		$a1, $zero, nbyte */
+		0x24840001,		/* addiu	$a0, $a0, 1 */
+		0x7000003F		/* sdbbp */
+	};
+
+	/* make sure we have a working area */
+	if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
+	{
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	}
+
+	/* convert flash writing code into a buffer in target endianness */
+	for (i = 0; i < ARRAY_SIZE(erase_check_code); i++)
+	{
+		target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t),
+				erase_check_code[i]);
+	}
+
+	mips32_info.common_magic = MIPS32_COMMON_MAGIC;
+	mips32_info.isa_mode = MIPS32_ISA_MIPS32;
+
+	init_reg_param(&reg_params[0], "a0", 32, PARAM_OUT);
+	buf_set_u32(reg_params[0].value, 0, 32, address);
+
+	init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT);
+	buf_set_u32(reg_params[1].value, 0, 32, count);
+
+	init_reg_param(&reg_params[2], "a2", 32, PARAM_IN_OUT);
+	buf_set_u32(reg_params[2].value, 0, 32, 0xff);
+
+	if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
+			erase_check_algorithm->address,
+			erase_check_algorithm->address + (sizeof(erase_check_code)-2),
+			10000, &mips32_info)) != ERROR_OK)
+	{
+		destroy_reg_param(&reg_params[0]);
+		destroy_reg_param(&reg_params[1]);
+		destroy_reg_param(&reg_params[2]);
+		target_free_working_area(target, erase_check_algorithm);
+		return 0;
+	}
+
+	*blank = buf_get_u32(reg_params[2].value, 0, 32);
+
+	destroy_reg_param(&reg_params[0]);
+	destroy_reg_param(&reg_params[1]);
+	destroy_reg_param(&reg_params[2]);
+
+	target_free_working_area(target, erase_check_algorithm);
+
+	return ERROR_OK;
+}
diff --git a/src/target/mips32.h b/src/target/mips32.h
index b731c68..94d29ff 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -85,6 +85,12 @@ struct mips32_core_reg
 	struct mips32_common *mips32_common;
 };
 
+struct mips32_algorithm
+{
+	int common_magic;
+	enum mips32_isa_mode isa_mode;
+};
+
 #define MIPS32_OP_BEQ	0x04
 #define MIPS32_OP_BNE	0x05
 #define MIPS32_OP_ADDI	0x08
@@ -164,5 +170,9 @@ int mips32_register_commands(struct command_context *cmd_ctx);
 
 int mips32_get_gdb_reg_list(struct target *target,
 		struct reg **reg_list[], int *reg_list_size);
+int mips32_checksum_memory(struct target *target, uint32_t address,
+		uint32_t count, uint32_t* checksum);
+int mips32_blank_check_memory(struct target *target,
+		uint32_t address, uint32_t count, uint32_t* blank);
 
 #endif	/*MIPS32_H*/
diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index 7d91d42..f20c69e 100644
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -206,7 +206,8 @@ static int mips32_pracc_exec_write(struct mips32_pracc_context *ctx, uint32_t ad
 	return ERROR_OK;
 }
 
-int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_t *code, int num_param_in, uint32_t *param_in, int num_param_out, uint32_t *param_out, int cycle)
+int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_t *code,
+		int num_param_in, uint32_t *param_in, int num_param_out, uint32_t *param_out, int cycle)
 {
 	uint32_t ejtag_ctrl;
 	uint32_t address, data;
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 5f5aa72..f581ddf 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -32,61 +32,6 @@
 #include "target_type.h"
 #include "register.h"
 
-/* cli handling */
-
-/* forward declarations */
-int mips_m4k_poll(struct target *target);
-int mips_m4k_halt(struct target *target);
-int mips_m4k_soft_reset_halt(struct target *target);
-int mips_m4k_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
-int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints);
-int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target);
-int mips_m4k_target_create(struct target *target, Jim_Interp *interp);
-
-int mips_m4k_examine(struct target *target);
-int mips_m4k_assert_reset(struct target *target);
-int mips_m4k_deassert_reset(struct target *target);
-int mips_m4k_checksum_memory(struct target *target, uint32_t address, uint32_t size, uint32_t *checksum);
-
-struct target_type mips_m4k_target =
-{
-	.name = "mips_m4k",
-
-	.poll = mips_m4k_poll,
-	.arch_state = mips32_arch_state,
-
-	.target_request_data = NULL,
-
-	.halt = mips_m4k_halt,
-	.resume = mips_m4k_resume,
-	.step = mips_m4k_step,
-
-	.assert_reset = mips_m4k_assert_reset,
-	.deassert_reset = mips_m4k_deassert_reset,
-	.soft_reset_halt = mips_m4k_soft_reset_halt,
-
-	.get_gdb_reg_list = mips32_get_gdb_reg_list,
-
-	.read_memory = mips_m4k_read_memory,
-	.write_memory = mips_m4k_write_memory,
-	.bulk_write_memory = mips_m4k_bulk_write_memory,
-	.checksum_memory = mips_m4k_checksum_memory,
-	.blank_check_memory = NULL,
-
-	.run_algorithm = mips32_run_algorithm,
-
-	.add_breakpoint = mips_m4k_add_breakpoint,
-	.remove_breakpoint = mips_m4k_remove_breakpoint,
-	.add_watchpoint = mips_m4k_add_watchpoint,
-	.remove_watchpoint = mips_m4k_remove_watchpoint,
-
-	.target_create = mips_m4k_target_create,
-	.init_target = mips_m4k_init_target,
-	.examine = mips_m4k_examine,
-};
-
 int mips_m4k_examine_debug_reason(struct target *target)
 {
 	uint32_t break_status;
@@ -148,13 +93,8 @@ int mips_m4k_debug_entry(struct target *target)
 	/* default to mips32 isa, it will be changed below if required */
 	mips32->isa_mode = MIPS32_ISA_MIPS32;
 
-	if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
-	{
-		if (buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32) & 0x01)
-		{
-			/* core is running mips16e isa */
-			mips32->isa_mode = MIPS32_ISA_MIPS16E;
-		}
+	if (ejtag_info->impcode & EJTAG_IMP_MIPS16) {
+		mips32->isa_mode = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1);
 	}
 
 	LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
@@ -396,6 +336,10 @@ int mips_m4k_resume(struct target *target, int current, uint32_t address, int ha
 		mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 	}
 
+	if (ejtag_info->impcode & EJTAG_IMP_MIPS16) {
+		buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
+	}
+
 	resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
 
 	mips32_restore_context(target);
@@ -457,9 +401,12 @@ int mips_m4k_step(struct target *target, int current, uint32_t address, int hand
 		buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 
 	/* the front-end may request us not to handle breakpoints */
-	if (handle_breakpoints)
-		if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
+	if (handle_breakpoints) {
+		breakpoint = breakpoint_find(target,
+				buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
+		if (breakpoint)
 			mips_m4k_unset_breakpoint(target, breakpoint);
+	}
 
 	/* restore context */
 	mips32_restore_context(target);
@@ -545,7 +492,8 @@ int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint
 		{
 			uint32_t verify = 0xffffffff;
 
-			if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
+			if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
+					breakpoint->orig_instr)) != ERROR_OK)
 			{
 				return retval;
 			}
@@ -568,7 +516,8 @@ int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint
 		{
 			uint16_t verify = 0xffff;
 
-			if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
+			if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
+					breakpoint->orig_instr)) != ERROR_OK)
 			{
 				return retval;
 			}
@@ -633,13 +582,15 @@ int mips_m4k_unset_breakpoint(struct target *target, struct breakpoint *breakpoi
 			uint32_t current_instr;
 
 			/* check that user program has not modified breakpoint instruction */
-			if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
+			if ((retval = target_read_memory(target, breakpoint->address, 4, 1,
+					(uint8_t*)&current_instr)) != ERROR_OK)
 			{
 				return retval;
 			}
 			if (current_instr == MIPS32_SDBBP)
 			{
-				if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+				if ((retval = target_write_memory(target, breakpoint->address, 4, 1,
+						breakpoint->orig_instr)) != ERROR_OK)
 				{
 					return retval;
 				}
@@ -650,14 +601,16 @@ int mips_m4k_unset_breakpoint(struct target *target, struct breakpoint *breakpoi
 			uint16_t current_instr;
 
 			/* check that user program has not modified breakpoint instruction */
-			if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
+			if ((retval = target_read_memory(target, breakpoint->address, 2, 1,
+					(uint8_t*)&current_instr)) != ERROR_OK)
 			{
 				return retval;
 			}
 
 			if (current_instr == MIPS16_SDBBP)
 			{
-				if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+				if ((retval = target_write_memory(target, breakpoint->address, 2, 1,
+						breakpoint->orig_instr)) != ERROR_OK)
 				{
 					return retval;
 				}
@@ -886,12 +839,14 @@ int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size,
 	return ERROR_OK;
 }
 
-int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size,
+		uint32_t count, uint8_t *buffer)
 {
 	struct mips32_common *mips32 = target_to_mips32(target);
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 
-	LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
+	LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
+			address, size, count);
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -920,7 +875,8 @@ int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target)
 	return ERROR_OK;
 }
 
-int mips_m4k_init_arch_info(struct target *target, struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
+int mips_m4k_init_arch_info(struct target *target, struct mips_m4k_common *mips_m4k,
+		struct jtag_tap *tap)
 {
 	struct mips32_common *mips32 = &mips_m4k->mips32_common;
 
@@ -973,7 +929,8 @@ int mips_m4k_examine(struct target *target)
 	return ERROR_OK;
 }
 
-int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
+int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
+		uint32_t count, uint8_t *buffer)
 {
 	struct mips32_common *mips32 = target_to_mips32(target);
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
@@ -1012,7 +969,8 @@ int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, uint32_t
 		}
 	}
 
-	retval = mips32_pracc_fastdata_xfer(ejtag_info, source, write, address, count, (uint32_t*) buffer);
+	retval = mips32_pracc_fastdata_xfer(ejtag_info, source, write, address,
+			count, (uint32_t*) buffer);
 	if (retval != ERROR_OK)
 	{
 		/* FASTDATA access failed, try normal memory write */
@@ -1026,7 +984,39 @@ int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, uint32_t
 	return retval;
 }
 
-int mips_m4k_checksum_memory(struct target *target, uint32_t address, uint32_t size, uint32_t *checksum)
+struct target_type mips_m4k_target =
 {
-	return ERROR_FAIL; /* use bulk read method */
-}
+	.name = "mips_m4k",
+
+	.poll = mips_m4k_poll,
+	.arch_state = mips32_arch_state,
+
+	.target_request_data = NULL,
+
+	.halt = mips_m4k_halt,
+	.resume = mips_m4k_resume,
+	.step = mips_m4k_step,
+
+	.assert_reset = mips_m4k_assert_reset,
+	.deassert_reset = mips_m4k_deassert_reset,
+	.soft_reset_halt = mips_m4k_soft_reset_halt,
+
+	.get_gdb_reg_list = mips32_get_gdb_reg_list,
+
+	.read_memory = mips_m4k_read_memory,
+	.write_memory = mips_m4k_write_memory,
+	.bulk_write_memory = mips_m4k_bulk_write_memory,
+	.checksum_memory = mips32_checksum_memory,
+	.blank_check_memory = mips32_blank_check_memory,
+
+	.run_algorithm = mips32_run_algorithm,
+
+	.add_breakpoint = mips_m4k_add_breakpoint,
+	.remove_breakpoint = mips_m4k_remove_breakpoint,
+	.add_watchpoint = mips_m4k_add_watchpoint,
+	.remove_watchpoint = mips_m4k_remove_watchpoint,
+
+	.target_create = mips_m4k_target_create,
+	.init_target = mips_m4k_init_target,
+	.examine = mips_m4k_examine,
+};
-- 
1.6.5.1.1367.gcd48


--------------050403090802010308050200--

[PATCH 1/7] ARMv7M: use software breakpoints for algorithms

[Spencer O. <nt...@us...>]

 - armv7m_run_algorithm now requires all algorithms to use
   a software breakpoint at their exit address
 - updated all algorithms to support this

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/flash/nor/at91sam3.c  |    4 +---
 src/flash/nor/lpc2000.c   |    2 +-
 src/flash/nor/stellaris.c |    3 +--
 src/flash/nor/stm32x.c    |    3 +--
 src/target/armv7m.c       |   23 +++++------------------
 5 files changed, 9 insertions(+), 26 deletions(-)

diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index 1b2f27c..5f013ed 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -2046,9 +2046,7 @@ sam3_page_write_opcodes[] = {
 	0x10,0xf0,0x01,0x0f,
 	//  41 0024 FBD0     		beq	.L4
 	0xfb,0xd0,
-	//  42              	.done:
-	//  43 0026 FEE7     		b	.done
-	0xfe,0xe7
+	0x00,0xBE     				/* bkpt #0 */
 };
 
 
diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index fc2b1cf..6674f17 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -267,7 +267,7 @@ static int lpc2000_iap_call(struct flash_bank *bank, int code, uint32_t param_ta
 				target_buffer_set_u32(target, jump_gate,
 						ARMV4_5_T_BX(12));
 				target_buffer_set_u32(target, jump_gate + 4,
-						ARMV4_5_T_B(0xfffffe));
+						ARMV5_T_BKPT(0));
 				break;
 			case lpc2000_v1:
 			case lpc2000_v2:
diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c
index 107b1c6..e5618b9 100644
--- a/src/flash/nor/stellaris.c
+++ b/src/flash/nor/stellaris.c
@@ -805,8 +805,7 @@ static const uint8_t stellaris_write_code[] =
 	0x04,0x36,			/* adds	r6, r6, #4 */
 	0x96,0x42,			/* cmp	r6, r2 */
 	0xF4,0xD1,			/* bne	mainloop */
-						/* exit: */
-	0xFE,0xE7,			/* b exit */
+	0x00,0xBE,     		/* bkpt #0 */
 /* pFLASH_CTRL_BASE: */
 	0x00,0xD0,0x0F,0x40,	/* .word	0x400FD000 */
 /* FLASHWRITECMD: */
diff --git a/src/flash/nor/stm32x.c b/src/flash/nor/stm32x.c
index bfdd3cd..53fc4ea 100644
--- a/src/flash/nor/stm32x.c
+++ b/src/flash/nor/stm32x.c
@@ -459,8 +459,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t
 		0x01, 0xD1,					/* bne	exit */
 		0x01, 0x3A,					/* subs	r2, r2, #1 */
 		0xED, 0xD1,					/* bne	write */
-									/* exit: */
-		0xFE, 0xE7,					/* b exit */
+		0x00, 0xBE,     			/* bkpt #0 */
 		0x10, 0x20, 0x02, 0x40,		/* STM32_FLASH_CR:	.word 0x40022010 */
 		0x0C, 0x20, 0x02, 0x40		/* STM32_FLASH_SR:	.word 0x4002200C */
 	};
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 466c0b2..056ac7b 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -338,6 +338,9 @@ int armv7m_run_algorithm(struct target *target,
 	int retval = ERROR_OK;
 	uint32_t context[ARMV7M_NUM_REGS];
 
+	/* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
+	 * at the exit point */
+
 	if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 	{
 		LOG_ERROR("current target isn't an ARMV7M target");
@@ -395,22 +398,8 @@ int armv7m_run_algorithm(struct target *target,
 		armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
 	}
 
-	/* REVISIT speed things up (3% or so in one case) by requiring
-	 * algorithms to include a BKPT instruction at each exit point.
-	 * This eliminates overheads of adding/removing a breakpoint.
-	 */
-
-	/* ARMV7M always runs in Thumb state */
-	if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
-	{
-		LOG_ERROR("can't add breakpoint to finish algorithm execution");
-		return ERROR_TARGET_FAILURE;
-	}
-
 	retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m);
 
-	breakpoint_remove(target, exit_point);
-
 	if (retval != ERROR_OK)
 	{
 		return retval;
@@ -594,8 +583,7 @@ int armv7m_checksum_memory(struct target *target,
 								/* ncomp: */
 		0x429C,					/* cmp	r4, r3 */
 		0xD1E9,					/* bne	nbyte */
-								/* end: */
-		0xE7FE,					/* b	end */
+		0xBE00,     			/* bkpt #0 */
 		0x1DB7, 0x04C1			/* CRC32XOR:	.word 0x04C11DB7 */
 	};
 
@@ -659,8 +647,7 @@ int armv7m_blank_check_memory(struct target *target,
 		0xEA02, 0x0203,		/* and  r2, r2, r3 */
 		0x3901,				/* subs	r1, r1, #1 */
 		0xD1F9,				/* bne	loop */
-		/* end: */
-		0xE7FE,				/* b	end */
+		0xBE00,     		/* bkpt #0 */
 	};
 
 	/* make sure we have a working area */
-- 
1.6.5.1.1367.gcd48


--------------060200060203000205020905--

[PATCH 2/2] STR9xpec: issue warning when unlocking device

[Spencer O. <nt...@us...>]

Issue warning to user when unlocking or writing the option bytes.
The new settings will not take effect until a target reset.

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/flash/nor/str9xpec.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/src/flash/nor/str9xpec.c b/src/flash/nor/str9xpec.c
index f0e11a5..243336a 100644
--- a/src/flash/nor/str9xpec.c
+++ b/src/flash/nor/str9xpec.c
@@ -915,6 +915,10 @@ COMMAND_HANDLER(str9xpec_handle_flash_options_write_command)
 	if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
 		return ERROR_FLASH_OPERATION_FAILED;
 
+	command_print(CMD_CTX, "str9xpec write options complete.\n"
+			"INFO: a reset or power cycle is required "
+			"for the new settings to take effect.");
+
 	return ERROR_OK;
 }
 
@@ -1077,6 +1081,10 @@ COMMAND_HANDLER(str9xpec_handle_flash_unlock_command)
 	if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
 		return ERROR_FLASH_OPERATION_FAILED;
 
+	command_print(CMD_CTX, "str9xpec unlocked.\n"
+			"INFO: a reset or power cycle is required "
+			"for the new settings to take effect.");
+
 	return ERROR_OK;
 }
 
-- 
1.6.5.1.1367.gcd48


--------------020707050500030308010408--

[PATCH 1/2] STM32x: issue warning when unlocking device (bug #16)

[Spencer O. <nt...@us...>]

Issue warning to user when unlocking or writing the option bytes.
The new settings will not take effect until a target reset.

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/flash/nor/stm32x.c |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/flash/nor/stm32x.c b/src/flash/nor/stm32x.c
index eaa3a0e..bfdd3cd 100644
--- a/src/flash/nor/stm32x.c
+++ b/src/flash/nor/stm32x.c
@@ -978,7 +978,9 @@ COMMAND_HANDLER(stm32x_handle_unlock_command)
 		return ERROR_OK;
 	}
 
-	command_print(CMD_CTX, "stm32x unlocked");
+	command_print(CMD_CTX, "stm32x unlocked.\n"
+			"INFO: a reset or power cycle is required "
+			"for the new settings to take effect.");
 
 	return ERROR_OK;
 }
@@ -1114,7 +1116,9 @@ COMMAND_HANDLER(stm32x_handle_options_write_command)
 		return ERROR_OK;
 	}
 
-	command_print(CMD_CTX, "stm32x write options complete");
+	command_print(CMD_CTX, "stm32x write options complete.\n"
+				"INFO: a reset or power cycle is required "
+				"for the new settings to take effect.");
 
 	return ERROR_OK;
 }
-- 
1.6.5.1.1367.gcd48


--------------010608000707060207000705--

[PATCH] CMD: duplicate cmd error msg

[Spencer O. <nt...@us...>]

When registering cmds we report duplicate attempts to register a cmd
as a LOG_ERROR.
Some situations need this, such as when registering dual flash banks.
http://www.mail-archive.com/ope...@li.../msg11152.html

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/helper/command.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/src/helper/command.c b/src/helper/command.c
index ebd9aa6..3625508 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -375,7 +375,10 @@ struct command* register_command(struct command_context *context,
 	struct command *c = command_find(*head, name);
 	if (NULL != c)
 	{
-		LOG_ERROR("command '%s' is already registered in '%s' context",
+		/* TODO: originally we treated attempting to register a cmd twice as an error
+		 * Sometimes we need this behaviour, such as with flash banks.
+		 * http://www.mail-archive.com/ope...@li.../msg11152.html */
+		LOG_DEBUG("command '%s' is already registered in '%s' context",
 				name, parent ? parent->name : "<global>");
 		return c;
 	}
-- 
1.6.5.1.1367.gcd48


--------------020102060800050305020000--

[PATCH] JTAG: fix bug when no interface connected

[Spencer O. <nt...@us...>]

 - fix coredump when OpenOCD is started without a jtag interface connected,

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/jtag/core.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/jtag/core.c b/src/jtag/core.c
index 8a580e9..551fa95 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -1623,6 +1623,8 @@ bool jtag_will_verify_capture_ir()
 
 int jtag_power_dropout(int *dropout)
 {
+	if (jtag == NULL)
+		return ERROR_FAIL;
 	return jtag->power_dropout(dropout);
 }
 
-- 
1.6.5.1.1367.gcd48


--------------070502010100030600050704--

[PATCH 3/3] ARM semihosting: document ARMv7M semihosting

[Spencer O. <nt...@us...>]

Signed-off-by: Spencer Oliver <nt...@us...>
---
 doc/openocd.texi |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 38fa92f..2b6828a 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6422,6 +6422,17 @@ must also be explicitly enabled.
 This finishes by listing the current vector catch configuration.
 @end deffn
 
+@deffn Command {cortex_m3 semihosting} [@option{enable}|@option{disable}]
+@cindex ARM semihosting
+Display status of semihosting, after optionally changing that status.
+
+Semihosting allows for code executing on an ARM target to use the
+I/O facilities on the host computer i.e. the system where OpenOCD
+is running. The target application must be linked against a library
+implementing the ARM semihosting convention that forwards operation
+requests by using a special bkpt instruction that is trapped by OpenOCD.
+@end deffn
+
 @anchor{Software Debug Messages and Tracing}
 @section Software Debug Messages and Tracing
 @cindex Linux-ARM DCC support
-- 
1.6.5.1.1367.gcd48


--------------010002020909090707060505--

[PATCH 2/3] ARM semihosting: add ARMv7M semihosting support

[Spencer O. <nt...@us...>]

Add ARMv7M support to current arm semihosting implementation.

armv7m_arch_state will now show semihosting status.

CortexM3 semihosting command added.

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/target/arm_semihosting.c |   47 ++++++++++++++++++++++++++++++++++++++++++
 src/target/arm_semihosting.h |    1 +
 src/target/armv7m.c          |    8 +++---
 src/target/armv7m.h          |    1 +
 src/target/cortex_m3.c       |   44 ++++++++++++++++++++++++++++++++++++++-
 5 files changed, 96 insertions(+), 5 deletions(-)

diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index 438084e..9c4a3ce 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -39,6 +39,8 @@
 
 #include "arm.h"
 #include "armv4_5.h"
+#include "armv7m.h"
+#include "cortex_m3.h"
 #include "register.h"
 #include "arm_semihosting.h"
 #include <helper/binarybuffer.h>
@@ -494,5 +496,50 @@ int armv4_5_semihosting(struct target *target, int *retval)
 	return 1;
 }
 
+int armv7m_semihosting(struct target *target, int *retval)
+{
+	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+	struct armv7m_common *armv7m = &cortex_m3->armv7m;
+	uint32_t pc;
+	struct reg *r;
+	uint16_t insn;
+	int result;
+
+	if (!armv7m->semi_hosting_info.is_semihosting)
+		return 0;
+
+	if (target->debug_reason != DBG_REASON_BREAKPOINT)
+		return 0;
+
+	r = &armv7m->core_cache->reg_list[ARMV7M_PC];
+	pc = buf_get_u32(r->value, 0, 32);
+
+	pc &= ~1;
+	*retval = target_read_u16(target, pc, &insn);
+	if (*retval != ERROR_OK)
+		return 1;
+
+	/* bkpt 0xAB */
+	if (insn != 0xBEAB)
+		return 0;
+
+	*retval = do_semihosting(target,
+			buf_get_u32(armv7m->core_cache->reg_list[0].value, 0, 32),
+			buf_get_u32(armv7m->core_cache->reg_list[1].value, 0, 32),
+			&armv7m->semi_hosting_info,
+			&result);
+
+	if (*retval != ERROR_OK)
+		return 1;
+
+	/* resume execution, this will be pc+2 to skip over the
+	 * bkpt instruction */
+
+	/* return result in R0 */
+	buf_set_u32(armv7m->core_cache->reg_list[0].value, 0, 32, result);
+	armv7m->core_cache->reg_list[0].dirty = 1;
+
+	*retval = target_resume(target, 1, 0, 0, 0);
+
 	return 1;
 }
diff --git a/src/target/arm_semihosting.h b/src/target/arm_semihosting.h
index c7c992b..bc308e5 100644
--- a/src/target/arm_semihosting.h
+++ b/src/target/arm_semihosting.h
@@ -31,5 +31,6 @@ struct arm_semi_hosting {
 };
 
 int armv4_5_semihosting(struct target *target, int *retval);
+int armv7m_semihosting(struct target *target, int *retval);
 
 #endif
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index edfcdf9..c6efe51 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -473,20 +473,20 @@ int armv7m_run_algorithm(struct target *target,
 int armv7m_arch_state(struct target *target)
 {
 	struct armv7m_common *armv7m = target_to_armv7m(target);
-	uint32_t ctrl, sp;
+	uint32_t ctrl;
 
 	ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
-	sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
 
 	LOG_USER("target halted due to %s, current mode: %s %s\n"
-		"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32,
+		"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s",
 		debug_reason_name(target),
 		armv7m_mode_strings[armv7m->core_mode],
 		armv7m_exception_string(armv7m->exception_number),
 		buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
 		buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32),
 		(ctrl & 0x02) ? 'p' : 'm',
-		sp);
+		buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32),
+		armv7m->semi_hosting_info.is_semihosting ? ", semihosting" : "");
 
 	return ERROR_OK;
 }
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 9787e30..d470507 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -105,6 +105,7 @@ struct armv7m_common
 	enum armv7m_mode core_mode;
 	int exception_number;
 	struct swjdp_common swjdp_info;
+	struct arm_semi_hosting semi_hosting_info;
 
 	uint32_t demcr;
 
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 3f34769..b77f578 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -38,7 +38,7 @@
 #include "arm_disassembler.h"
 #include "register.h"
 #include "arm_opcodes.h"
-
+#include "arm_semihosting.h"
 
 /* NOTE:  most of this should work fine for the Cortex-M1 and
  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
@@ -464,6 +464,9 @@ static int cortex_m3_poll(struct target *target)
 			if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 				return retval;
 
+			if (armv7m_semihosting(target, &retval) != 0)
+				return retval;
+
 			target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 		}
 		if (prev_target_state == TARGET_DEBUG_RUNNING)
@@ -2025,6 +2028,38 @@ COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
 	return ERROR_OK;
 }
 
+COMMAND_HANDLER(handle_cortex_m3_semihosting_command)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+	int retval;
+
+	retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (CMD_ARGC > 0)
+	{
+		int semihosting;
+
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
+
+		if (!target_was_examined(target))
+		{
+			LOG_ERROR("Target not examined yet");
+			return ERROR_FAIL;
+		}
+
+		cortex_m3->armv7m.semi_hosting_info.is_semihosting = semihosting;
+	}
+
+	command_print(CMD_CTX, "semihosting is %s",
+			cortex_m3->armv7m.semi_hosting_info.is_semihosting
+			? "enabled" : "disabled");
+
+	return ERROR_OK;
+}
+
 static const struct command_registration cortex_m3_exec_command_handlers[] = {
 	{
 		.name = "disassemble",
@@ -2047,6 +2082,13 @@ static const struct command_registration cortex_m3_exec_command_handlers[] = {
 		.help = "configure hardware vectors to trigger debug entry",
 		.usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
 	},
+	{
+		.name = "semihosting",
+		.handler = handle_cortex_m3_semihosting_command,
+		.mode = COMMAND_EXEC,
+		.help = "activate support for semihosting operations",
+		.usage = "['enable'|'disable']",
+	},
 	COMMAND_REGISTRATION_DONE
 };
 static const struct command_registration cortex_m3_command_handlers[] = {
-- 
1.6.5.1.1367.gcd48


--------------000503090604030306070703--

[PATCH 1/3] ARM semihosting: split do_semihosting

[Spencer O. <nt...@us...>]

Remove any target specific code from do_semihosting.

Add arm_semi_hosting structure to hold semihosting variables.

Rename arm_semihosting to armv4_5_semihosting, ready for armv7m
semihosting support.

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/helper/system.h          |    1 -
 src/target/arm.h             |    9 +--
 src/target/arm7_9_common.c   |    8 +-
 src/target/arm_semihosting.c |  169 ++++++++++++++++++++++-------------------
 src/target/arm_semihosting.h |   11 +++-
 src/target/armv4_5.c         |    2 +-
 src/target/target.h          |    1 -
 7 files changed, 109 insertions(+), 92 deletions(-)

diff --git a/src/helper/system.h b/src/helper/system.h
index 8ff3532..f03c850 100644
--- a/src/helper/system.h
+++ b/src/helper/system.h
@@ -51,7 +51,6 @@
 #include <winsock2.h>
 #include <ws2tcpip.h>
 #include <sys/types.h>
-#include <sys/stat.h>
 #endif
 // --- platform specific headers ---
 
diff --git a/src/target/arm.h b/src/target/arm.h
index 988266e..54fd698 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -28,7 +28,7 @@
 
 #include <helper/command.h>
 #include "target.h"
-
+#include "arm_semihosting.h"
 
 /**
  * @file
@@ -108,11 +108,8 @@ struct arm {
 	/** Flag reporting unavailability of the BKPT instruction. */
 	bool is_armv4;
 
-	/** Flag reporting whether semihosting is active. */
-	bool is_semihosting;
-
-	/** Value to be returned by semihosting SYS_ERRNO request. */
-	int semihosting_errno;
+	/** info about semi hosting config. */
+	struct arm_semi_hosting semi_hosting_info;
 
 	/** Backpointer to the target. */
 	struct target *target;
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 509e91e..81ea81c 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -896,7 +896,7 @@ int arm7_9_poll(struct target *target)
 			if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 				return retval;
 
-			if (arm_semihosting(target, &retval) != 0)
+			if (armv4_5_semihosting(target, &retval) != 0)
 				return retval;
 
 			if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
@@ -2866,16 +2866,16 @@ COMMAND_HANDLER(handle_arm7_9_semihosting_command)
 			if (semihosting)
 				breakpoint_add(target, 8, 4, BKPT_SOFT);
 			else
-				breakpoint_remove(target, 8); 
+				breakpoint_remove(target, 8);
 		}
 
 		/* FIXME never let that "catch" be dropped! */
-		arm7_9->armv4_5_common.is_semihosting = semihosting;
+		arm7_9->armv4_5_common.semi_hosting_info.is_semihosting = semihosting;
 
 	}
 
 	command_print(CMD_CTX, "semihosting is %s",
-			arm7_9->armv4_5_common.is_semihosting
+			arm7_9->armv4_5_common.semi_hosting_info.is_semihosting
 			? "enabled" : "disabled");
 
 	return ERROR_OK;
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index 9b853d9..438084e 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -60,15 +60,11 @@ static int open_modeflags[12] = {
 	O_RDWR | O_CREAT | O_APPEND | O_BINARY
 };
 
-static int do_semihosting(struct target *target)
+static int do_semihosting(struct target *target, uint32_t r0, uint32_t r1,
+		struct arm_semi_hosting *info, int *result)
 {
-	struct arm *armv4_5 = target_to_arm(target);
-	uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
-	uint32_t r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
-	uint32_t lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, ARM_MODE_SVC, 14).value, 0, 32);
-	uint32_t spsr = buf_get_u32(armv4_5->spsr->value, 0, 32);;
 	uint8_t params[16];
-	int retval, result;
+	int retval;
 
 	/*
 	 * TODO: lots of security issues are not considered yet, such as:
@@ -96,19 +92,19 @@ static int do_semihosting(struct target *target)
 				fn[l] = 0;
 				if (strcmp((char *)fn, ":tt") == 0) {
 					if (m < 4)
-						result = dup(STDIN_FILENO);
+						*result = dup(STDIN_FILENO);
 					else
-						result = dup(STDOUT_FILENO);
+						*result = dup(STDOUT_FILENO);
 				} else {
 					/* cygwin requires the permission setting
 					 * otherwise it will fail to reopen a previously
 					 * written file */
-					result = open((char *)fn, open_modeflags[m], 0644);
+					*result = open((char *)fn, open_modeflags[m], 0644);
 				}
-				armv4_5->semihosting_errno =  errno;
+				info->semihosting_errno =  errno;
 			} else {
-				result = -1;
-				armv4_5->semihosting_errno = EINVAL;
+				*result = -1;
+				info->semihosting_errno = EINVAL;
 			}
 		}
 		break;
@@ -119,8 +115,8 @@ static int do_semihosting(struct target *target)
 			return retval;
 		else {
 			int fd = target_buffer_get_u32(target, params+0);
-			result = close(fd);
-			armv4_5->semihosting_errno = errno;
+			*result = close(fd);
+			info->semihosting_errno = errno;
 		}
 		break;
 
@@ -131,7 +127,7 @@ static int do_semihosting(struct target *target)
 			if (retval != ERROR_OK)
 				return retval;
 			putchar(c);
-			result = 0;
+			*result = 0;
 		}
 		break;
 
@@ -145,7 +141,7 @@ static int do_semihosting(struct target *target)
 				break;
 			putchar(c);
 		} while (1);
-		result = 0;
+		*result = 0;
 		break;
 
 	case 0x05:	/* SYS_WRITE */
@@ -158,18 +154,18 @@ static int do_semihosting(struct target *target)
 			size_t l = target_buffer_get_u32(target, params+8);
 			uint8_t *buf = malloc(l);
 			if (!buf) {
-				result = -1;
-				armv4_5->semihosting_errno = ENOMEM;
+				*result = -1;
+				info->semihosting_errno = ENOMEM;
 			} else {
 				retval = target_read_buffer(target, a, l, buf);
 				if (retval != ERROR_OK) {
 					free(buf);
 					return retval;
 				}
-				result = write(fd, buf, l);
-				armv4_5->semihosting_errno = errno;
-				if (result >= 0)
-					result = l - result;
+				*result = write(fd, buf, l);
+				info->semihosting_errno = errno;
+				if (*result >= 0)
+					*result = l - *result;
 				free(buf);
 			}
 		}
@@ -185,18 +181,18 @@ static int do_semihosting(struct target *target)
 			ssize_t l = target_buffer_get_u32(target, params+8);
 			uint8_t *buf = malloc(l);
 			if (!buf) {
-				result = -1;
-				armv4_5->semihosting_errno = ENOMEM;
+				*result = -1;
+				info->semihosting_errno = ENOMEM;
 			} else {
-				result = read(fd, buf, l);
-				armv4_5->semihosting_errno = errno;
-				if (result >= 0) {
-					retval = target_write_buffer(target, a, result, buf);
+				*result = read(fd, buf, l);
+				info->semihosting_errno = errno;
+				if (*result >= 0) {
+					retval = target_write_buffer(target, a, *result, buf);
 					if (retval != ERROR_OK) {
 						free(buf);
 						return retval;
 					}
-					result = l - result;
+					*result = l - *result;
 				}
 				free(buf);
 			}
@@ -204,21 +200,21 @@ static int do_semihosting(struct target *target)
 		break;
 
 	case 0x07:	/* SYS_READC */
-		result = getchar();
+		*result = getchar();
 		break;
 
 	case 0x08:	/* SYS_ISERROR */
 		retval = target_read_memory(target, r1, 4, 1, params);
 		if (retval != ERROR_OK)
 			return retval;
-		result = (target_buffer_get_u32(target, params+0) != 0);
+		*result = (target_buffer_get_u32(target, params+0) != 0);
 		break;
 
 	case 0x09:	/* SYS_ISTTY */
 		retval = target_read_memory(target, r1, 4, 1, params);
 		if (retval != ERROR_OK)
 			return retval;
-		result = isatty(target_buffer_get_u32(target, params+0));
+		*result = isatty(target_buffer_get_u32(target, params+0));
 		break;
 
 	case 0x0a:	/* SYS_SEEK */
@@ -228,10 +224,10 @@ static int do_semihosting(struct target *target)
 		else {
 			int fd = target_buffer_get_u32(target, params+0);
 			off_t pos = target_buffer_get_u32(target, params+4);
-			result = lseek(fd, pos, SEEK_SET);
-			armv4_5->semihosting_errno = errno;
-			if (result == pos)
-				result = 0;
+			*result = lseek(fd, pos, SEEK_SET);
+			info->semihosting_errno = errno;
+			if (*result == pos)
+				*result = 0;
 		}
 		break;
 
@@ -242,13 +238,13 @@ static int do_semihosting(struct target *target)
 		else {
 			int fd = target_buffer_get_u32(target, params+0);
 			struct stat buf;
-			result = fstat(fd, &buf);
-			if (result == -1) {
-				armv4_5->semihosting_errno = errno;
-				result = -1;
+			*result = fstat(fd, &buf);
+			if (*result == -1) {
+				info->semihosting_errno = errno;
+				*result = -1;
 				break;
 			}
-			result = buf.st_size;
+			*result = buf.st_size;
 		}
 		break;
 
@@ -265,11 +261,11 @@ static int do_semihosting(struct target *target)
 				if (retval != ERROR_OK)
 					return retval;
 				fn[l] = 0;
-				result = remove((char *)fn);
-				armv4_5->semihosting_errno =  errno;
+				*result = remove((char *)fn);
+				info->semihosting_errno =  errno;
 			} else {
-				result = -1;
-				armv4_5->semihosting_errno = EINVAL;
+				*result = -1;
+				info->semihosting_errno = EINVAL;
 			}
 		}
 		break;
@@ -293,21 +289,21 @@ static int do_semihosting(struct target *target)
 					return retval;
 				fn1[l1] = 0;
 				fn2[l2] = 0;
-				result = rename((char *)fn1, (char *)fn2);
-				armv4_5->semihosting_errno =  errno;
+				*result = rename((char *)fn1, (char *)fn2);
+				info->semihosting_errno =  errno;
 			} else {
-				result = -1;
-				armv4_5->semihosting_errno = EINVAL;
+				*result = -1;
+				info->semihosting_errno = EINVAL;
 			}
 		}
 		break;
 
 	case 0x11:	/* SYS_TIME */
-		result = time(NULL);
+		*result = time(NULL);
 		break;
 
 	case 0x13:	/* SYS_ERRNO */
-		result = armv4_5->semihosting_errno;
+		*result = info->semihosting_errno;
 		break;
 
 	case 0x15:	/* SYS_GET_CMDLINE */
@@ -320,12 +316,12 @@ static int do_semihosting(struct target *target)
 			char *arg = "foobar";
 			uint32_t s = strlen(arg) + 1;
 			if (l < s)
-				result = -1;
+				*result = -1;
 			else {
 				retval = target_write_buffer(target, a, s, (void*)arg);
 				if (retval != ERROR_OK)
 					return retval;
-				result = 0;
+				*result = 0;
 			}
 		}
 		break;
@@ -341,7 +337,7 @@ static int do_semihosting(struct target *target)
 			retval = target_write_memory(target, a, 4, 4, params);
 			if (retval != ERROR_OK)
 				return retval;
-			result = 0;
+			*result = 0;
 		}
 		break;
 
@@ -382,28 +378,11 @@ static int do_semihosting(struct target *target)
 	default:
 		fprintf(stderr, "semihosting: unsupported call %#x\n",
 				(unsigned) r0);
-		result = -1;
-		armv4_5->semihosting_errno = ENOTSUP;
+		*result = -1;
+		info->semihosting_errno = ENOTSUP;
 	}
 
-	/* resume execution to the original mode */
-
-	/* return value in R0 */
-	buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, result);
-	armv4_5->core_cache->reg_list[0].dirty = 1;
-
-	/* LR --> PC */
-	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, lr);
-	armv4_5->core_cache->reg_list[15].dirty = 1;
-
-	/* saved PSR --> current PSR */
-	buf_set_u32(armv4_5->cpsr->value, 0, 32, spsr);
-	armv4_5->cpsr->dirty = 1;
-	armv4_5->core_mode = spsr & 0x1f;
-	if (spsr & 0x20)
-		armv4_5->core_state = ARM_STATE_THUMB;
-
-	return target_resume(target, 1, 0, 0, 0);
+	return ERROR_OK;
 }
 
 /**
@@ -419,13 +398,14 @@ static int do_semihosting(struct target *target)
  * @param retval Pointer to a location where the return code will be stored
  * @return non-zero value if a request was processed or an error encountered
  */
-int arm_semihosting(struct target *target, int *retval)
+int armv4_5_semihosting(struct target *target, int *retval)
 {
 	struct arm *arm = target_to_arm(target);
 	uint32_t pc, lr, spsr;
 	struct reg *r;
+	int result;
 
-	if (!arm->is_semihosting || arm->core_mode != ARM_MODE_SVC)
+	if (!arm->semi_hosting_info.is_semihosting || arm->core_mode != ARM_MODE_SVC)
 		return 0;
 
 	/* Check for PC == 0x00000008 or 0xffff0008: Supervisor Call vector. */
@@ -480,6 +460,39 @@ int arm_semihosting(struct target *target, int *retval)
 			return 0;
 	}
 
-	*retval = do_semihosting(target);
+	lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache, ARM_MODE_SVC, 14).value, 0, 32);
+	spsr = buf_get_u32(arm->spsr->value, 0, 32);
+
+	*retval = do_semihosting(target,
+			buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32),
+			buf_get_u32(arm->core_cache->reg_list[1].value, 0, 32),
+			&arm->semi_hosting_info,
+			&result);
+
+	if (*retval != ERROR_OK)
+		return 1;
+
+	/* resume execution to the original mode */
+
+	/* return value in R0 */
+	buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, result);
+	arm->core_cache->reg_list[0].dirty = 1;
+
+	/* LR --> PC */
+	buf_set_u32(arm->core_cache->reg_list[15].value, 0, 32, lr);
+	arm->core_cache->reg_list[15].dirty = 1;
+
+	/* saved PSR --> current PSR */
+	buf_set_u32(arm->cpsr->value, 0, 32, spsr);
+	arm->cpsr->dirty = 1;
+	arm->core_mode = spsr & 0x1f;
+	if (spsr & 0x20)
+		arm->core_state = ARM_STATE_THUMB;
+
+	*retval = target_resume(target, 1, 0, 0, 0);
+
+	return 1;
+}
+
 	return 1;
 }
diff --git a/src/target/arm_semihosting.h b/src/target/arm_semihosting.h
index 80cad39..c7c992b 100644
--- a/src/target/arm_semihosting.h
+++ b/src/target/arm_semihosting.h
@@ -21,6 +21,15 @@
 #ifndef ARM_SEMIHOSTING_H
 #define ARM_SEMIHOSTING_H
 
-int arm_semihosting(struct target *target, int *retval);
+struct arm_semi_hosting {
+
+	/** Flag reporting whether semihosting is active. */
+	bool is_semihosting;
+
+	/** Value to be returned by semihosting SYS_ERRNO request. */
+	int semihosting_errno;
+};
+
+int armv4_5_semihosting(struct target *target, int *retval);
 
 #endif
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index c7b7367..1dcfe88 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -600,7 +600,7 @@ int arm_arch_state(struct target *target)
 			buf_get_u32(armv4_5->cpsr->value, 0, 32),
 			buf_get_u32(armv4_5->core_cache->reg_list[15].value,
 					0, 32),
-			armv4_5->is_semihosting ? ", semihosting" : "");
+			armv4_5->semi_hosting_info.is_semihosting ? ", semihosting" : "");
 
 	return ERROR_OK;
 }
diff --git a/src/target/target.h b/src/target/target.h
index da91d46..0131575 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -36,7 +36,6 @@ struct watchpoint;
 struct mem_param;
 struct reg_param;
 
-
 /*
  * TARGET_UNKNOWN = 0: we don't know anything about the target yet
  * TARGET_RUNNING = 1: the target is executing user code
-- 
1.6.5.1.1367.gcd48


--------------030702080507060305070104--

[PATCH] Clang support

[Alex A. <ale...@sp...>]

---
 src/helper/log.h    |    2 +-
 src/helper/system.h |    5 +++++
 2 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/src/helper/log.h b/src/helper/log.h
index ebcb8a1..b887e0c 100644
--- a/src/helper/log.h
+++ b/src/helper/log.h
@@ -111,7 +111,7 @@ extern int debug_level;
 #define LOG_LEVEL_IS(FOO)  ((debug_level) >=3D (FOO))
=20
 #define LOG_DEBUG(expr ...) \
-               ((debug_level >=3D LOG_LVL_DEBUG) ? log_printf_lf (LOG_LVL_=
DEBUG, __FILE__, __LINE__, __FUNCTION__, expr) , 0 : 0)
+               do {if (debug_level >=3D LOG_LVL_DEBUG) log_printf_lf (LOG_=
LVL_DEBUG, __FILE__, __LINE__, __FUNCTION__, expr);} while (0)
=20
 #define LOG_INFO(expr ...) \
                log_printf_lf (LOG_LVL_INFO, __FILE__, __LINE__, __FUNCTION=
__, expr)
diff --git a/src/helper/system.h b/src/helper/system.h
index 169df1c..77a867a 100644
--- a/src/helper/system.h
+++ b/src/helper/system.h
@@ -83,4 +83,9 @@
 #include <fcntl.h>
 #endif
=20
+#ifndef true
+#define true -1
+#define false 0
+#endif
+
 #endif // SYSTEM_H
--=20
1.6.6

[PATCH 2/2] ARM semihosting: win32 and cygwin fixes

[Spencer O. <nt...@us...>]

Cygwin would fail to reopen a previously written file if the mode is
not given.

Simplified converting the open flags and made sure the win32 O_BINARY
bit is set.

Added define for systems that do not support O_BINARY.

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/helper/replacements.h    |    6 ++++++
 src/target/arm_semihosting.c |   36 +++++++++++++++++++++---------------
 2 files changed, 27 insertions(+), 15 deletions(-)

diff --git a/src/helper/replacements.h b/src/helper/replacements.h
index 2b3ea73..3598dd9 100644
--- a/src/helper/replacements.h
+++ b/src/helper/replacements.h
@@ -40,6 +40,12 @@
 #define ENOTSUP 134		/* Not supported */
 #endif
 
+/* for systems that do not support O_BINARY
+ * linux being one of them */
+#ifndef O_BINARY
+#define O_BINARY 0
+#endif
+
 #ifndef HAVE_SYS_TIME_H
 
 #ifndef _TIMEVAL_DEFINED
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index 1d0acd6..be90702 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -2,6 +2,9 @@
  *   Copyright (C) 2009 by Marvell Technology Group Ltd.                   *
  *   Written by Nicolas Pitre <ni...@ma...>                           *
  *                                                                         *
+ *   Copyright (C) 2010 by Spencer Oliver                                  *
+ *   sp...@sp...                                                  *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -41,6 +44,20 @@
 #include <helper/binarybuffer.h>
 #include <helper/log.h>
 
+static int open_modeflags[12] = {
+	O_RDONLY,
+	O_RDONLY | O_BINARY,
+	O_RDWR,
+	O_RDWR | O_BINARY,
+	O_WRONLY | O_CREAT | O_TRUNC,
+	O_WRONLY | O_CREAT | O_TRUNC | O_BINARY,
+	O_RDWR | O_CREAT | O_TRUNC,
+	O_RDWR | O_CREAT | O_TRUNC | O_BINARY,
+	O_WRONLY | O_CREAT | O_APPEND,
+	O_WRONLY | O_CREAT | O_APPEND | O_BINARY,
+	O_RDWR | O_CREAT | O_APPEND,
+	O_RDWR | O_CREAT | O_APPEND | O_BINARY
+};
 
 static int do_semihosting(struct target *target)
 {
@@ -72,28 +89,17 @@ static int do_semihosting(struct target *target)
 			uint32_t l = target_buffer_get_u32(target, params+8);
 			if (l <= 255 && m <= 11) {
 				uint8_t fn[256];
-				int mode;
 				retval = target_read_memory(target, a, 1, l, fn);
 				if (retval != ERROR_OK)
 					return retval;
 				fn[l] = 0;
-				if (m & 0x2)
-					mode = O_RDWR;
-				else if (m & 0xc)
-					mode = O_WRONLY;
-				else
-					mode = O_RDONLY;
-				if (m >= 8)
-					mode |= O_CREAT|O_APPEND;
-				else if (m >= 4)
-					mode |= O_CREAT|O_TRUNC;
 				if (strcmp((char *)fn, ":tt") == 0) {
-					if ((mode & 3) == 0)
-						result = dup(0);
+					if (m < 4)
+						result = STDIN_FILENO;
 					else
-						result = dup(1);
+						result = STDOUT_FILENO;
 				} else
-					result = open((char *)fn, mode);
+					result = open((char *)fn, open_modeflags[m], 0644);
 				armv4_5->semihosting_errno =  errno;
 			} else {
 				result = -1;
-- 
1.6.5.1.1367.gcd48


--------------070804070800010304070305--

[PATCH 1/2] ARM semihosting: fix writing to stdout

[Spencer O. <nt...@us...>]

SYS_FLEN would be called before a write on a descriptor to check its size.
Currently lseek would fail with -1 when given the stdout/stderr descriptor.
Changing to use fstat seems to be the standard way of handling this.

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/helper/system.h          |    2 ++
 src/target/arm_semihosting.c |   12 ++++--------
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/src/helper/system.h b/src/helper/system.h
index 169df1c..af19d01 100644
--- a/src/helper/system.h
+++ b/src/helper/system.h
@@ -50,6 +50,8 @@
 #ifdef _WIN32
 #include <winsock2.h>
 #include <ws2tcpip.h>
+#include <sys/types.h>
+#include <sys/stat.h>
 #endif
 // --- platform specific headers ---
 
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index f4244c8..1d0acd6 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -230,18 +230,14 @@ static int do_semihosting(struct target *target)
 			return retval;
 		else {
 			int fd = target_buffer_get_u32(target, params+0);
-			off_t cur = lseek(fd, 0, SEEK_CUR);
-			if (cur == (off_t)-1) {
+			struct stat buf;
+			result = fstat(fd, &buf);
+			if (result == -1) {
 				armv4_5->semihosting_errno = errno;
 				result = -1;
 				break;
 			}
-			result = lseek(fd, 0, SEEK_END);
-			armv4_5->semihosting_errno = errno;
-			if (lseek(fd, cur, SEEK_SET) == (off_t)-1) {
-				armv4_5->semihosting_errno = errno;
-				result = -1;
-			}
+			result = buf.st_size;
 		}
 		break;
 
-- 
1.6.5.1.1367.gcd48


--------------040706080807030202010705--

[PATCH 2/2] ARM semihosting: document ARMv7M semihosting

[Spencer O. <nt...@us...>]

Signed-off-by: Spencer Oliver <nt...@us...>
---
 doc/openocd.texi |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 05b6f4e..342a4a2 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6341,6 +6341,17 @@ must also be explicitly enabled.
 This finishes by listing the current vector catch configuration.
 @end deffn
 
+@deffn Command {cortex_m3 semihosting} [@option{enable}|@option{disable}]
+@cindex ARM semihosting
+Display status of semihosting, after optionally changing that status.
+
+Semihosting allows for code executing on an ARM target to use the
+I/O facilities on the host computer i.e. the system where OpenOCD
+is running. The target application must be linked against a library
+implementing the ARM semihosting convention that forwards operation
+requests by using a special bkpt instruction that is trapped by OpenOCD.
+@end deffn
+
 @anchor{Software Debug Messages and Tracing}
 @section Software Debug Messages and Tracing
 @cindex Linux-ARM DCC support
-- 
1.6.5.1.1367.gcd48


--------------070406060409020106020107--

[PATCH 1/2] ARM semihosting: add armv7m support

[Spencer O. <nt...@us...>]

This adds semihosting support for the ARMv7M profile devices.
Currently only been verified on the Cortex-M3 against codesourcery toolchains.

Fix issue with printing to stdout/stderr:
caused by a incorrect SYS_FLEN syscall, fstat is now called rather than lseek.

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/helper/system.h          |    2 +
 src/target/arm.h             |    9 +--
 src/target/arm7_9_common.c   |    8 +-
 src/target/arm_semihosting.c |  148 ++++++++++++++++++++++++++++--------------
 src/target/arm_semihosting.h |   17 +++++-
 src/target/armv4_5.c         |    2 +-
 src/target/armv7m.c          |    8 +-
 src/target/armv7m.h          |    1 +
 src/target/cortex_m3.c       |   44 ++++++++++++-
 src/target/target.h          |    1 -
 10 files changed, 172 insertions(+), 68 deletions(-)

diff --git a/src/helper/system.h b/src/helper/system.h
index 169df1c..af19d01 100644
--- a/src/helper/system.h
+++ b/src/helper/system.h
@@ -50,6 +50,8 @@
 #ifdef _WIN32
 #include <winsock2.h>
 #include <ws2tcpip.h>
+#include <sys/types.h>
+#include <sys/stat.h>
 #endif
 // --- platform specific headers ---
 
diff --git a/src/target/arm.h b/src/target/arm.h
index 988266e..54fd698 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -28,7 +28,7 @@
 
 #include <helper/command.h>
 #include "target.h"
-
+#include "arm_semihosting.h"
 
 /**
  * @file
@@ -108,11 +108,8 @@ struct arm {
 	/** Flag reporting unavailability of the BKPT instruction. */
 	bool is_armv4;
 
-	/** Flag reporting whether semihosting is active. */
-	bool is_semihosting;
-
-	/** Value to be returned by semihosting SYS_ERRNO request. */
-	int semihosting_errno;
+	/** info about semi hosting config. */
+	struct arm_semi_hosting semi_hosting_info;
 
 	/** Backpointer to the target. */
 	struct target *target;
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 509e91e..81ea81c 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -896,7 +896,7 @@ int arm7_9_poll(struct target *target)
 			if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 				return retval;
 
-			if (arm_semihosting(target, &retval) != 0)
+			if (armv4_5_semihosting(target, &retval) != 0)
 				return retval;
 
 			if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
@@ -2866,16 +2866,16 @@ COMMAND_HANDLER(handle_arm7_9_semihosting_command)
 			if (semihosting)
 				breakpoint_add(target, 8, 4, BKPT_SOFT);
 			else
-				breakpoint_remove(target, 8); 
+				breakpoint_remove(target, 8);
 		}
 
 		/* FIXME never let that "catch" be dropped! */
-		arm7_9->armv4_5_common.is_semihosting = semihosting;
+		arm7_9->armv4_5_common.semi_hosting_info.is_semihosting = semihosting;
 
 	}
 
 	command_print(CMD_CTX, "semihosting is %s",
-			arm7_9->armv4_5_common.is_semihosting
+			arm7_9->armv4_5_common.semi_hosting_info.is_semihosting
 			? "enabled" : "disabled");
 
 	return ERROR_OK;
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index f4244c8..434868a 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -36,19 +36,17 @@
 
 #include "arm.h"
 #include "armv4_5.h"
+#include "armv7m.h"
+#include "cortex_m3.h"
 #include "register.h"
 #include "arm_semihosting.h"
 #include <helper/binarybuffer.h>
 #include <helper/log.h>
 
-
-static int do_semihosting(struct target *target)
+static int do_semihosting(struct target *target, struct arm_semi_hosting *info)
 {
-	struct arm *armv4_5 = target_to_arm(target);
-	uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
-	uint32_t r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
-	uint32_t lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, ARM_MODE_SVC, 14).value, 0, 32);
-	uint32_t spsr = buf_get_u32(armv4_5->spsr->value, 0, 32);;
+	uint32_t r0 = buf_get_u32(info->core_cache->reg_list[0].value, 0, 32);
+	uint32_t r1 = buf_get_u32(info->core_cache->reg_list[1].value, 0, 32);
 	uint8_t params[16];
 	int retval, result;
 
@@ -94,10 +92,10 @@ static int do_semihosting(struct target *target)
 						result = dup(1);
 				} else
 					result = open((char *)fn, mode);
-				armv4_5->semihosting_errno =  errno;
+				info->semihosting_errno =  errno;
 			} else {
 				result = -1;
-				armv4_5->semihosting_errno = EINVAL;
+				info->semihosting_errno = EINVAL;
 			}
 		}
 		break;
@@ -109,7 +107,7 @@ static int do_semihosting(struct target *target)
 		else {
 			int fd = target_buffer_get_u32(target, params+0);
 			result = close(fd);
-			armv4_5->semihosting_errno = errno;
+			info->semihosting_errno = errno;
 		}
 		break;
 
@@ -148,7 +146,7 @@ static int do_semihosting(struct target *target)
 			uint8_t *buf = malloc(l);
 			if (!buf) {
 				result = -1;
-				armv4_5->semihosting_errno = ENOMEM;
+				info->semihosting_errno = ENOMEM;
 			} else {
 				retval = target_read_buffer(target, a, l, buf);
 				if (retval != ERROR_OK) {
@@ -156,7 +154,7 @@ static int do_semihosting(struct target *target)
 					return retval;
 				}
 				result = write(fd, buf, l);
-				armv4_5->semihosting_errno = errno;
+				info->semihosting_errno = errno;
 				if (result >= 0)
 					result = l - result;
 				free(buf);
@@ -175,10 +173,10 @@ static int do_semihosting(struct target *target)
 			uint8_t *buf = malloc(l);
 			if (!buf) {
 				result = -1;
-				armv4_5->semihosting_errno = ENOMEM;
+				info->semihosting_errno = ENOMEM;
 			} else {
 				result = read(fd, buf, l);
-				armv4_5->semihosting_errno = errno;
+				info->semihosting_errno = errno;
 				if (result > 0) {
 					retval = target_write_buffer(target, a, result, buf);
 					if (retval != ERROR_OK) {
@@ -218,7 +216,7 @@ static int do_semihosting(struct target *target)
 			int fd = target_buffer_get_u32(target, params+0);
 			off_t pos = target_buffer_get_u32(target, params+4);
 			result = lseek(fd, pos, SEEK_SET);
-			armv4_5->semihosting_errno = errno;
+			info->semihosting_errno = errno;
 			if (result == pos)
 				result = 0;
 		}
@@ -230,18 +228,14 @@ static int do_semihosting(struct target *target)
 			return retval;
 		else {
 			int fd = target_buffer_get_u32(target, params+0);
-			off_t cur = lseek(fd, 0, SEEK_CUR);
-			if (cur == (off_t)-1) {
-				armv4_5->semihosting_errno = errno;
+			struct stat buf;
+			result = fstat(fd, &buf);
+			if (result == -1) {
+				info->semihosting_errno = errno;
 				result = -1;
 				break;
 			}
-			result = lseek(fd, 0, SEEK_END);
-			armv4_5->semihosting_errno = errno;
-			if (lseek(fd, cur, SEEK_SET) == (off_t)-1) {
-				armv4_5->semihosting_errno = errno;
-				result = -1;
-			}
+			result = buf.st_size;
 		}
 		break;
 
@@ -259,10 +253,10 @@ static int do_semihosting(struct target *target)
 					return retval;
 				fn[l] = 0;
 				result = remove((char *)fn);
-				armv4_5->semihosting_errno =  errno;
+				info->semihosting_errno =  errno;
 			} else {
 				result = -1;
-				armv4_5->semihosting_errno = EINVAL;
+				info->semihosting_errno = EINVAL;
 			}
 		}
 		break;
@@ -287,10 +281,10 @@ static int do_semihosting(struct target *target)
 				fn1[l1] = 0;
 				fn2[l2] = 0;
 				result = rename((char *)fn1, (char *)fn2);
-				armv4_5->semihosting_errno =  errno;
+				info->semihosting_errno =  errno;
 			} else {
 				result = -1;
-				armv4_5->semihosting_errno = EINVAL;
+				info->semihosting_errno = EINVAL;
 			}
 		}
 		break;
@@ -300,7 +294,7 @@ static int do_semihosting(struct target *target)
 		break;
 
 	case 0x13:	/* SYS_ERRNO */
-		result = armv4_5->semihosting_errno;
+		result = info->semihosting_errno;
 		break;
 
 	case 0x15:	/* SYS_GET_CMDLINE */
@@ -376,27 +370,12 @@ static int do_semihosting(struct target *target)
 		fprintf(stderr, "semihosting: unsupported call %#x\n",
 				(unsigned) r0);
 		result = -1;
-		armv4_5->semihosting_errno = ENOTSUP;
+		info->semihosting_errno = ENOTSUP;
 	}
 
-	/* resume execution to the original mode */
-
-	/* return value in R0 */
-	buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, result);
-	armv4_5->core_cache->reg_list[0].dirty = 1;
-
-	/* LR --> PC */
-	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, lr);
-	armv4_5->core_cache->reg_list[15].dirty = 1;
-
-	/* saved PSR --> current PSR */
-	buf_set_u32(armv4_5->cpsr->value, 0, 32, spsr);
-	armv4_5->cpsr->dirty = 1;
-	armv4_5->core_mode = spsr & 0x1f;
-	if (spsr & 0x20)
-		armv4_5->core_state = ARM_STATE_THUMB;
+	info->result = result;
 
-	return target_resume(target, 1, 0, 0, 0);
+	return ERROR_OK;
 }
 
 /**
@@ -412,13 +391,13 @@ static int do_semihosting(struct target *target)
  * @param retval Pointer to a location where the return code will be stored
  * @return non-zero value if a request was processed or an error encountered
  */
-int arm_semihosting(struct target *target, int *retval)
+int armv4_5_semihosting(struct target *target, int *retval)
 {
 	struct arm *arm = target_to_arm(target);
 	uint32_t pc, lr, spsr;
 	struct reg *r;
 
-	if (!arm->is_semihosting || arm->core_mode != ARM_MODE_SVC)
+	if (!arm->semi_hosting_info.is_semihosting || arm->core_mode != ARM_MODE_SVC)
 		return 0;
 
 	/* Check for PC == 0x00000008 or 0xffff0008: Supervisor Call vector. */
@@ -473,6 +452,75 @@ int arm_semihosting(struct target *target, int *retval)
 			return 0;
 	}
 
-	*retval = do_semihosting(target);
+	lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache, ARM_MODE_SVC, 14).value, 0, 32);
+	spsr = buf_get_u32(arm->spsr->value, 0, 32);
+
+	arm->semi_hosting_info.core_cache = arm->core_cache;
+
+	if ((*retval = do_semihosting(target, &arm->semi_hosting_info)) != ERROR_OK)
+		return 0;
+
+	/* resume execution to the original mode */
+
+	/* return value in R0 */
+	buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, arm->semi_hosting_info.result);
+	arm->core_cache->reg_list[0].dirty = 1;
+
+	/* LR --> PC */
+	buf_set_u32(arm->core_cache->reg_list[15].value, 0, 32, lr);
+	arm->core_cache->reg_list[15].dirty = 1;
+
+	/* saved PSR --> current PSR */
+	buf_set_u32(arm->cpsr->value, 0, 32, spsr);
+	arm->cpsr->dirty = 1;
+	arm->core_mode = spsr & 0x1f;
+	if (spsr & 0x20)
+		arm->core_state = ARM_STATE_THUMB;
+
+	*retval = target_resume(target, 1, 0, 0, 0);
+
+	return 1;
+}
+
+int armv7m_semihosting(struct target *target, int *retval)
+{
+	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+	struct armv7m_common *armv7m = &cortex_m3->armv7m;
+	uint32_t pc;
+	struct reg *r;
+	uint16_t insn;
+
+	if (!armv7m->semi_hosting_info.is_semihosting)
+		return 0;
+
+	if (target->debug_reason != DBG_REASON_BREAKPOINT)
+		return 0;
+
+	r = &armv7m->core_cache->reg_list[ARMV7M_PC];
+	pc = buf_get_u32(r->value, 0, 32);
+
+	pc &= ~1;
+	*retval = target_read_u16(target, pc, &insn);
+	if (*retval != ERROR_OK)
+		return 1;
+
+	/* bkpt 0xAB */
+	if (insn != 0xBEAB)
+		return 0;
+
+	armv7m->semi_hosting_info.core_cache = armv7m->core_cache;
+
+	if ((*retval = do_semihosting(target, &armv7m->semi_hosting_info)) != ERROR_OK)
+		return 0;
+
+	/* resume execution, this will be pc+2 to skip over the
+	 * bkpt instruction */
+
+	/* return result in R0 */
+	buf_set_u32(armv7m->core_cache->reg_list[0].value, 0, 32, armv7m->semi_hosting_info.result);
+	armv7m->core_cache->reg_list[0].dirty = 1;
+
+	*retval = target_resume(target, 1, 0, 0, 0);
+
 	return 1;
 }
diff --git a/src/target/arm_semihosting.h b/src/target/arm_semihosting.h
index 80cad39..a2d4e0c 100644
--- a/src/target/arm_semihosting.h
+++ b/src/target/arm_semihosting.h
@@ -21,6 +21,21 @@
 #ifndef ARM_SEMIHOSTING_H
 #define ARM_SEMIHOSTING_H
 
-int arm_semihosting(struct target *target, int *retval);
+struct arm_semi_hosting {
+
+	/** Flag reporting whether semihosting is active. */
+	bool is_semihosting;
+
+	/** Value to be returned by semihosting SYS_ERRNO request. */
+	int semihosting_errno;
+
+	/** Value holding semi hosting result. */
+	int result;
+
+	struct reg_cache *core_cache;
+};
+
+int armv4_5_semihosting(struct target *target, int *retval);
+int armv7m_semihosting(struct target *target, int *retval);
 
 #endif
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index c7b7367..1dcfe88 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -600,7 +600,7 @@ int arm_arch_state(struct target *target)
 			buf_get_u32(armv4_5->cpsr->value, 0, 32),
 			buf_get_u32(armv4_5->core_cache->reg_list[15].value,
 					0, 32),
-			armv4_5->is_semihosting ? ", semihosting" : "");
+			armv4_5->semi_hosting_info.is_semihosting ? ", semihosting" : "");
 
 	return ERROR_OK;
 }
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index c172a27..7650c14 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -473,20 +473,20 @@ int armv7m_run_algorithm(struct target *target,
 int armv7m_arch_state(struct target *target)
 {
 	struct armv7m_common *armv7m = target_to_armv7m(target);
-	uint32_t ctrl, sp;
+	uint32_t ctrl;
 
 	ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
-	sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
 
 	LOG_USER("target halted due to %s, current mode: %s %s\n"
-		"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32,
+		"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s",
 		debug_reason_name(target),
 		armv7m_mode_strings[armv7m->core_mode],
 		armv7m_exception_string(armv7m->exception_number),
 		buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
 		buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32),
 		(ctrl & 0x02) ? 'p' : 'm',
-		sp);
+		buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32),
+		armv7m->semi_hosting_info.is_semihosting ? ", semihosting" : "");
 
 	return ERROR_OK;
 }
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 9787e30..d470507 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -105,6 +105,7 @@ struct armv7m_common
 	enum armv7m_mode core_mode;
 	int exception_number;
 	struct swjdp_common swjdp_info;
+	struct arm_semi_hosting semi_hosting_info;
 
 	uint32_t demcr;
 
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index adce4d9..0230824 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -38,7 +38,7 @@
 #include "arm_disassembler.h"
 #include "register.h"
 #include "arm_opcodes.h"
-
+#include "arm_semihosting.h"
 
 /* NOTE:  most of this should work fine for the Cortex-M1 and
  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
@@ -449,6 +449,9 @@ static int cortex_m3_poll(struct target *target)
 			if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 				return retval;
 
+			if (armv7m_semihosting(target, &retval) != 0)
+				return retval;
+
 			target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 		}
 		if (prev_target_state == TARGET_DEBUG_RUNNING)
@@ -2010,6 +2013,38 @@ COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
 	return ERROR_OK;
 }
 
+COMMAND_HANDLER(handle_cortex_m3_semihosting_command)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+	int retval;
+
+	retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (CMD_ARGC > 0)
+	{
+		int semihosting;
+
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
+
+		if (!target_was_examined(target))
+		{
+			LOG_ERROR("Target not examined yet");
+			return ERROR_FAIL;
+		}
+
+		cortex_m3->armv7m.semi_hosting_info.is_semihosting = semihosting;
+	}
+
+	command_print(CMD_CTX, "semihosting is %s",
+			cortex_m3->armv7m.semi_hosting_info.is_semihosting
+			? "enabled" : "disabled");
+
+	return ERROR_OK;
+}
+
 static const struct command_registration cortex_m3_exec_command_handlers[] = {
 	{
 		.name = "disassemble",
@@ -2032,6 +2067,13 @@ static const struct command_registration cortex_m3_exec_command_handlers[] = {
 		.help = "configure hardware vectors to trigger debug entry",
 		.usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
 	},
+	{
+		.name = "semihosting",
+		.handler = handle_cortex_m3_semihosting_command,
+		.mode = COMMAND_EXEC,
+		.help = "activate support for semihosting operations",
+		.usage = "['enable'|'disable']",
+	},
 	COMMAND_REGISTRATION_DONE
 };
 static const struct command_registration cortex_m3_command_handlers[] = {
diff --git a/src/target/target.h b/src/target/target.h
index da91d46..0131575 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -36,7 +36,6 @@ struct watchpoint;
 struct mem_param;
 struct reg_param;
 
-
 /*
  * TARGET_UNKNOWN = 0: we don't know anything about the target yet
  * TARGET_RUNNING = 1: the target is executing user code
-- 
1.6.5.1.1367.gcd48


--------------010708040704050309040302--

[PATCH] BUILD: remove cygwin build warnings

[Spencer O. <nt...@us...>]

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/target/cortex_m3.c    |    4 ++--
 src/target/mips32_pracc.c |    2 +-
 src/target/mips_m4k.c     |    2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 762e318..adce4d9 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -1675,8 +1675,8 @@ static int cortex_m3_examine(struct target *target)
 			return retval;
 
 		if (((cpuid >> 4) & 0xc3f) == 0xc23)
-			LOG_DEBUG("Cortex-M3 r%dp%d processor detected",
-				(cpuid >> 20) & 0xf, (cpuid >> 0) & 0xf);
+			LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
+				(uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
 		LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
 
 		/* NOTE: FPB and DWT are both optional. */
diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index 11d5a43..7d91d42 100644
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -968,7 +968,7 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
 	/* write program into RAM */
 	mips32_pracc_write_mem32(ejtag_info, source->address, ARRAY_SIZE(handler_code), handler_code);
 
-	LOG_DEBUG("%s using 0x%.8x for write handler\n", __func__, source->address);
+	LOG_DEBUG("%s using 0x%.8" PRIx32 " for write handler\n", __func__, source->address);
 
 	jmp_code[1] |= UPPER16(source->address);
 	jmp_code[2] |= LOWER16(source->address);
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 1a65c50..5f5aa72 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -981,7 +981,7 @@ int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, uint32_t
 	int retval;
 	int write = 1;
 
-	LOG_DEBUG("address: 0x%8.8x, count: 0x%8.8x", address, count);
+	LOG_DEBUG("address: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, count);
 
 	if (target->state != TARGET_HALTED)
 	{
-- 
1.6.5.1.1367.gcd48


--------------040804000902030405020505--

[PATCH] ARMV7M: handle bkpt instruction on resume/step

[Spencer O. <nt...@us...>]

Skip over a bkpt instruction if found on resume/step.
Only software breakpoints known to openod are handled.
So this handles the special case of a user added bkpt, eg. semi-hosting.

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/target/armv7m.c    |   38 ++++++++++++++++++++++++++++++++++++++
 src/target/armv7m.h    |    2 ++
 src/target/cortex_m3.c |   25 +++++++++++++++++++++++--
 3 files changed, 63 insertions(+), 2 deletions(-)

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 233fb95..c172a27 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -694,6 +694,44 @@ int armv7m_blank_check_memory(struct target *target,
 	return ERROR_OK;
 }
 
+int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
+{
+	struct armv7m_common *armv7m = target_to_armv7m(target);
+	struct reg *r = armv7m->core_cache->reg_list + 15;
+	bool result = false;
+
+
+	/* if we halted last time due to a bkpt instruction
+	 * then we have to manually step over it, otherwise
+	 * the core will break again */
+
+	if (target->debug_reason == DBG_REASON_BREAKPOINT)
+	{
+		uint16_t op;
+		uint32_t pc = buf_get_u32(r->value, 0, 32);
+
+		pc &= ~1;
+		if (target_read_u16(target, pc, &op) == ERROR_OK)
+		{
+			if ((op & 0xFF00) == 0xBE00)
+			{
+				pc = buf_get_u32(r->value, 0, 32) + 2;
+				buf_set_u32(r->value, 0, 32, pc);
+				r->dirty = true;
+				r->valid = true;
+				result = true;
+				LOG_DEBUG("Skipping over BKPT instruction");
+			}
+		}
+	}
+
+	if (inst_found) {
+		*inst_found = result;
+	}
+
+	return ERROR_OK;
+}
+
 /*--------------------------------------------------------------------------*/
 
 /*
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 86caae2..9787e30 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -171,6 +171,8 @@ int armv7m_checksum_memory(struct target *target,
 int armv7m_blank_check_memory(struct target *target,
 		uint32_t address, uint32_t count, uint32_t* blank);
 
+int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found);
+
 extern const struct command_registration armv7m_command_handlers[];
 
 #endif /* ARMV7M_H */
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 48f8114..762e318 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -638,6 +638,16 @@ static int cortex_m3_resume(struct target *target, int current,
 		r->valid = true;
 	}
 
+	/* if we halted last time due to a bkpt instruction
+	 * then we have to manually step over it, otherwise
+	 * the core will break again */
+
+	if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
+			&& !debug_execution)
+	{
+		armv7m_maybe_skip_bkpt_inst(target, NULL);
+	}
+
 	resume_pc = buf_get_u32(r->value, 0, 32);
 
 	armv7m_restore_context(target);
@@ -690,6 +700,7 @@ static int cortex_m3_step(struct target *target, int current,
 	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 	struct breakpoint *breakpoint = NULL;
 	struct reg *pc = armv7m->core_cache->reg_list + 15;
+	bool bkpt_inst_found = false;
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -709,14 +720,23 @@ static int cortex_m3_step(struct target *target, int current,
 			cortex_m3_unset_breakpoint(target, breakpoint);
 	}
 
+	armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
+
 	target->debug_reason = DBG_REASON_SINGLESTEP;
 
 	armv7m_restore_context(target);
 
 	target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 
-	/* set step and clear halt */
-	cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
+	/* if no bkpt instruction is found at pc then we can perform
+	 * a normal step, otherwise we have to manually step over the bkpt
+	 * instruction - as such simulate a step */
+	if (bkpt_inst_found == false)
+	{
+		/* set step and clear halt */
+		cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
+	}
+
 	mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 
 	/* registers are now invalid */
@@ -735,6 +755,7 @@ static int cortex_m3_step(struct target *target, int current,
 	LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 			" nvic_icsr = 0x%" PRIx32,
 			cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
+
 	return ERROR_OK;
 }
 
-- 
1.6.5.1.1367.gcd48


--------------050201020101070700050804--

[PATCH] GDB: change gdb_breakpoint_override to COMMAND_ANY

[Spencer O. <nt...@us...>]

 - enable gdb_breakpoint_override to be used within config script.

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/server/gdb_server.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 8018e6f..26f868b 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -2466,7 +2466,7 @@ static const struct command_registration gdb_command_handlers[] = {
 	{
 		.name = "gdb_breakpoint_override",
 		.handler = handle_gdb_breakpoint_override_command,
-		.mode = COMMAND_EXEC,
+		.mode = COMMAND_ANY,
 		.help = "Display or specify type of breakpoint "
 			"to be used by gdb 'break' commands.",
 		.usage = "('hard'|'soft'|'disable')"
-- 
1.6.5.1.1367.gcd48


--------------050002090107040106030902--

[PATCH] atmega128: implement EEPROM flashing

[Paul F. <fer...@gm...>]

This patch implements flashing EEPROM over JTAG, represented as bank 1.
Tested on atmega128.

Signed-off-by: Paul Fertser <fer...@gm...>
---
 src/flash/nor/avrf.c   |   87 +++++++++++++++++++++++++++++++++++++++++++----
 src/flash/nor/avrf.h   |    7 ++++
 tcl/target/mega128.cfg |    6 +++-
 3 files changed, 91 insertions(+), 9 deletions(-)

diff --git a/src/flash/nor/avrf.c b/src/flash/nor/avrf.c
index 6c2d17f..2a67a08 100644
--- a/src/flash/nor/avrf.c
+++ b/src/flash/nor/avrf.c
@@ -180,11 +180,61 @@ static int avr_jtagprg_writeflashpage(struct avr_common *avr, uint8_t *page_buf,
 	return ERROR_OK;
 }
 
+static int avr_jtagprg_writeeeprompage(struct avr_common *avr, uint8_t *page_buf, uint32_t buf_size, uint32_t addr, uint32_t page_size)
+{
+	uint32_t i, poll_value;
+
+	avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+	avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2311, AVR_JTAG_REG_ProgrammingCommand_Len);
+	
+	// load addr high byte
+	avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x0700 | ((addr >> 8) & 0xFF), AVR_JTAG_REG_ProgrammingCommand_Len);
+	for (i = 0; i < page_size; i++)
+	{
+		// load addr low byte
+		avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x0300 | (addr & 0xFF), AVR_JTAG_REG_ProgrammingCommand_Len);
+		addr++;
+
+		if (i < buf_size)
+		{
+			avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x1300 | page_buf[i], AVR_JTAG_REG_ProgrammingCommand_Len);
+		}
+		else
+		{
+			avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x13FF, AVR_JTAG_REG_ProgrammingCommand_Len);
+		}
+		// latch data
+		avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+		avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x7700, AVR_JTAG_REG_ProgrammingCommand_Len);
+		avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+	}
+
+	// write page
+	avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3300, AVR_JTAG_REG_ProgrammingCommand_Len);
+	avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3100, AVR_JTAG_REG_ProgrammingCommand_Len);
+	avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3300, AVR_JTAG_REG_ProgrammingCommand_Len);
+	avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3300, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+	do {
+		poll_value = 0;
+		avr_jtag_senddat(avr->jtag_info.tap, &poll_value, 0x3300, AVR_JTAG_REG_ProgrammingCommand_Len);
+		if (ERROR_OK != mcu_execute_queue())
+		{
+			return ERROR_FAIL;
+		}
+		LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
+	} while (!(poll_value & 0x0200));
+	
+	return ERROR_OK;
+}
+
+
 FLASH_BANK_COMMAND_HANDLER(avrf_flash_bank_command)
 {
 	struct avrf_flash_bank *avrf_info;
+	int is_flash;
 
-	if (CMD_ARGC < 6)
+	if (CMD_ARGC < 7)
 	{
 		LOG_WARNING("incomplete flash_bank avr configuration");
 		return ERROR_FLASH_BANK_INVALID;
@@ -194,6 +244,8 @@ FLASH_BANK_COMMAND_HANDLER(avrf_flash_bank_command)
 	bank->driver_priv = avrf_info;
 
 	avrf_info->probed = 0;
+	COMMAND_PARSE_NUMBER(int, CMD_ARGV[6], is_flash);
+	avrf_info->type = is_flash;
 
 	return ERROR_OK;
 }
@@ -248,7 +300,14 @@ static int avrf_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset,
 		{
 			cur_buffer_size = count;
 		}
-		avr_jtagprg_writeflashpage(avr, buffer + cur_size, cur_buffer_size, offset + cur_size, page_size);
+		if (((struct avrf_flash_bank*)(bank->driver_priv))->type == FLASH)
+		{
+			avr_jtagprg_writeflashpage(avr, buffer + cur_size, cur_buffer_size, offset + cur_size, page_size );
+		}
+		else
+		{
+			avr_jtagprg_writeeeprompage(avr, buffer + cur_size, cur_buffer_size, offset + cur_size, page_size );
+		}
 		count -= cur_buffer_size;
 		cur_size += cur_buffer_size;
 
@@ -302,16 +361,28 @@ static int avrf_probe(struct flash_bank *bank)
 
 	if (avr_info != NULL)
 	{
+		int page_size;
+		int page_num;
+
+		if (avrf_info->type == FLASH) {
+			page_size = avr_info->flash_page_size;
+			page_num = avr_info->flash_page_num;
+		} else {
+			page_size = avr_info->eeprom_page_size;
+			page_num = avr_info->eeprom_page_num;
+		}
+		
 		// chip found
 		bank->base = 0x00000000;
-		bank->size = (avr_info->flash_page_size * avr_info->flash_page_num);
-		bank->num_sectors = avr_info->flash_page_num;
-		bank->sectors = malloc(sizeof(struct flash_sector) * avr_info->flash_page_num);
 
-		for (i = 0; i < avr_info->flash_page_num; i++)
+		bank->size = (page_size * page_num);
+		bank->num_sectors = page_num;
+		bank->sectors = malloc(sizeof(struct flash_sector) * page_num);
+
+		for (i = 0; i < page_num; i++)
 		{
-			bank->sectors[i].offset = i * avr_info->flash_page_size;
-			bank->sectors[i].size = avr_info->flash_page_size;
+			bank->sectors[i].offset = i * page_size;
+			bank->sectors[i].size = page_size;
 			bank->sectors[i].is_erased = -1;
 			bank->sectors[i].is_protected = 1;
 		}
diff --git a/src/flash/nor/avrf.h b/src/flash/nor/avrf.h
index 1a69e86..43bd523 100644
--- a/src/flash/nor/avrf.h
+++ b/src/flash/nor/avrf.h
@@ -30,10 +30,17 @@ struct avrf_type
 	int eeprom_page_num;
 };
 
+enum flash_type
+{
+	FLASH,
+	EEPROM
+};
+	
 struct avrf_flash_bank
 {
 	int ppage_size;
 	int probed;
+	enum flash_type type;
 };
 
 #endif /* AVRF_H */
diff --git a/tcl/target/mega128.cfg b/tcl/target/mega128.cfg
index 2cf31d6..94bbfd2 100644
--- a/tcl/target/mega128.cfg
+++ b/tcl/target/mega128.cfg
@@ -23,7 +23,10 @@ target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
 #$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
 
 set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
+# flash
+flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME 0
+# eeprom
+flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME 1
 
 #to use it, script will be like:
 #init
@@ -36,6 +39,7 @@ flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
 #poll
 #avr mass_erase 0
 #flash write_image E:/Versaloon/Software/CAMERAPROTOCOLAGENT.hex
+#flash write_bank 1 E:/Versaloon/Software/CAMERAPROTOCOLAGENT.eeprom.bin 0
 #reset run
 #shutdown
 #
-- 
1.5.6.5


--cPi+lWm09sJ+d57q--

[PATCH] ARMv7: use software breakpoints for algorithms

[Spencer O. <nt...@us...>]

 - armv7m_run_algorithm now requires all algorithms to use
   a software breakpoint at their exit address
 - updated all algorithms to support this

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/flash/nor/at91sam3.c  |    4 +---
 src/flash/nor/lpc2000.c   |    2 +-
 src/flash/nor/stellaris.c |    3 +--
 src/flash/nor/stm32x.c    |    3 +--
 src/target/armv7m.c       |   23 +++++------------------
 5 files changed, 9 insertions(+), 26 deletions(-)

diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index 5dacf6f..699f493 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -2046,9 +2046,7 @@ sam3_page_write_opcodes[] = {
 	0x10,0xf0,0x01,0x0f,
 	//  41 0024 FBD0     		beq	.L4
 	0xfb,0xd0,
-	//  42              	.done:
-	//  43 0026 FEE7     		b	.done
-	0xfe,0xe7
+	0x00,0xBE     				/* bkpt #0 */
 };
 
 
diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index ae0a384..ac76493 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -267,7 +267,7 @@ static int lpc2000_iap_call(struct flash_bank *bank, int code, uint32_t param_ta
 				target_buffer_set_u32(target, jump_gate,
 						ARMV4_5_T_BX(12));
 				target_buffer_set_u32(target, jump_gate + 4,
-						ARMV4_5_T_B(0xfffffe));
+						ARMV5_T_BKPT(0));
 				break;
 			case lpc2000_v1:
 			case lpc2000_v2:
diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c
index 8d35f9b..8083f60 100644
--- a/src/flash/nor/stellaris.c
+++ b/src/flash/nor/stellaris.c
@@ -805,8 +805,7 @@ static const uint8_t stellaris_write_code[] =
 	0x04,0x36,			/* adds	r6, r6, #4 */
 	0x96,0x42,			/* cmp	r6, r2 */
 	0xF4,0xD1,			/* bne	mainloop */
-						/* exit: */
-	0xFE,0xE7,			/* b exit */
+	0x00,0xBE,     		/* bkpt #0 */
 /* pFLASH_CTRL_BASE: */
 	0x00,0xD0,0x0F,0x40,	/* .word	0x400FD000 */
 /* FLASHWRITECMD: */
diff --git a/src/flash/nor/stm32x.c b/src/flash/nor/stm32x.c
index 75dcf3b..d45df9c 100644
--- a/src/flash/nor/stm32x.c
+++ b/src/flash/nor/stm32x.c
@@ -459,8 +459,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t
 		0x01, 0xD1,					/* bne	exit */
 		0x01, 0x3A,					/* subs	r2, r2, #1 */
 		0xED, 0xD1,					/* bne	write */
-									/* exit: */
-		0xFE, 0xE7,					/* b exit */
+		0x00, 0xBE,     			/* bkpt #0 */
 		0x10, 0x20, 0x02, 0x40,		/* STM32_FLASH_CR:	.word 0x40022010 */
 		0x0C, 0x20, 0x02, 0x40		/* STM32_FLASH_SR:	.word 0x4002200C */
 	};
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 233fb95..3972df5 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -338,6 +338,9 @@ int armv7m_run_algorithm(struct target *target,
 	int retval = ERROR_OK;
 	uint32_t context[ARMV7M_NUM_REGS];
 
+	/* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
+	 * at the exit point */
+
 	if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 	{
 		LOG_ERROR("current target isn't an ARMV7M target");
@@ -395,22 +398,8 @@ int armv7m_run_algorithm(struct target *target,
 		armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
 	}
 
-	/* REVISIT speed things up (3% or so in one case) by requiring
-	 * algorithms to include a BKPT instruction at each exit point.
-	 * This eliminates overheads of adding/removing a breakpoint.
-	 */
-
-	/* ARMV7M always runs in Thumb state */
-	if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
-	{
-		LOG_ERROR("can't add breakpoint to finish algorithm execution");
-		return ERROR_TARGET_FAILURE;
-	}
-
 	retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m);
 
-	breakpoint_remove(target, exit_point);
-
 	if (retval != ERROR_OK)
 	{
 		return retval;
@@ -582,8 +571,7 @@ int armv7m_checksum_memory(struct target *target,
 								/* ncomp: */
 		0x429C,					/* cmp	r4, r3 */
 		0xD1E9,					/* bne	nbyte */
-								/* end: */
-		0xE7FE,					/* b	end */
+		0xBE00,     			/* bkpt #0 */
 		0x1DB7, 0x04C1			/* CRC32XOR:	.word 0x04C11DB7 */
 	};
 
@@ -647,8 +635,7 @@ int armv7m_blank_check_memory(struct target *target,
 		0xEA02, 0x0203,		/* and  r2, r2, r3 */
 		0x3901,				/* subs	r1, r1, #1 */
 		0xD1F9,				/* bne	loop */
-		/* end: */
-		0xE7FE,				/* b	end */
+		0xBE00,     		/* bkpt #0 */
 	};
 
 	/* make sure we have a working area */
-- 
1.6.5.1.1367.gcd48


--------------080900020404070406080808--

[PATCH] MIPS: add mips algorithm support

[Spencer O. <nt...@us...>]

 - add mips support for target algorithms.
 - added handlers for target_checksum_memory and target_blank_check_memory.

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/target/mips32.c   |  302 ++++++++++++++++++++++++++++++++++++++++++++++++-
 src/target/mips32.h   |   10 ++
 src/target/mips_m4k.c |   22 ++---
 3 files changed, 318 insertions(+), 16 deletions(-)

diff --git a/src/target/mips32.c b/src/target/mips32.c
index 5bb4104..841e456 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -27,6 +27,8 @@
 #endif
 
 #include "mips32.h"
+#include "breakpoints.h"
+#include "algorithm.h"
 #include "register.h"
 
 char* mips32_core_reg_list[] =
@@ -319,9 +321,164 @@ int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, s
 	return ERROR_OK;
 }
 
-int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
+/* run to exit point. return error if exit point was not reached. */
+static int mips32_run_and_wait(struct target *target, uint32_t entry_point,
+		int timeout_ms, uint32_t exit_point, struct mips32_common *mips32)
 {
-	/*TODO*/
+	uint32_t pc;
+	int retval;
+	/* This code relies on the target specific  resume() and  poll()->debug_entry()
+	 * sequence to write register values to the processor and the read them back */
+	if ((retval = target_resume(target, 0, entry_point, 0, 1)) != ERROR_OK)
+	{
+		return retval;
+	}
+
+	retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
+	/* If the target fails to halt due to the breakpoint, force a halt */
+	if (retval != ERROR_OK || target->state != TARGET_HALTED)
+	{
+		if ((retval = target_halt(target)) != ERROR_OK)
+			return retval;
+		if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
+		{
+			return retval;
+		}
+		return ERROR_TARGET_TIMEOUT;
+	}
+
+	pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
+	if (pc != exit_point)
+	{
+		LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
+		return ERROR_TARGET_TIMEOUT;
+	}
+
+	return ERROR_OK;
+}
+
+int mips32_run_algorithm(struct target *target, int num_mem_params,
+		struct mem_param *mem_params, int num_reg_params,
+		struct reg_param *reg_params, uint32_t entry_point,
+		uint32_t exit_point, int timeout_ms, void *arch_info)
+{
+	struct mips32_common *mips32 = target_to_mips32(target);
+	struct mips32_algorithm *mips32_algorithm_info = arch_info;
+	enum mips32_isa_mode isa_mode = mips32->isa_mode;
+
+	uint32_t context[MIPS32NUMCOREREGS];
+	int i;
+	int retval = ERROR_OK;
+
+	LOG_DEBUG("Running algorithm");
+
+	/* NOTE: mips32_run_algorithm requires that each algorithm uses a software breakpoint
+	 * at the exit point */
+
+	if (mips32->common_magic != MIPS32_COMMON_MAGIC)
+	{
+		LOG_ERROR("current target isn't a MIPS32 target");
+		return ERROR_TARGET_INVALID;
+	}
+
+	if (target->state != TARGET_HALTED)
+	{
+		LOG_WARNING("target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	/* refresh core register cache */
+	for (unsigned i = 0; i < MIPS32NUMCOREREGS; i++)
+	{
+		if (!mips32->core_cache->reg_list[i].valid)
+			mips32->read_core_reg(target, i);
+		context[i] = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
+	}
+
+	for (i = 0; i < num_mem_params; i++)
+	{
+		if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
+		{
+			return retval;
+		}
+	}
+
+	for (int i = 0; i < num_reg_params; i++)
+	{
+		struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
+
+		if (!reg)
+		{
+			LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+			return ERROR_INVALID_ARGUMENTS;
+		}
+
+		if (reg->size != reg_params[i].size)
+		{
+			LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
+			return ERROR_INVALID_ARGUMENTS;
+		}
+
+		mips32_set_core_reg(reg, reg_params[i].value);
+	}
+
+	mips32->isa_mode = mips32_algorithm_info->isa_mode;
+
+	retval = mips32_run_and_wait(target, entry_point, timeout_ms, exit_point, mips32);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	for (i = 0; i < num_mem_params; i++)
+	{
+		if (mem_params[i].direction != PARAM_OUT)
+		{
+			if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
+			{
+				return retval;
+			}
+		}
+	}
+
+	for (i = 0; i < num_reg_params; i++)
+	{
+		if (reg_params[i].direction != PARAM_OUT)
+		{
+			struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
+			if (!reg)
+			{
+				LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+				return ERROR_INVALID_ARGUMENTS;
+			}
+
+			if (reg->size != reg_params[i].size)
+			{
+				LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
+				return ERROR_INVALID_ARGUMENTS;
+			}
+
+			buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
+		}
+	}
+
+	/* restore everything we saved before */
+	for (i = 0; i < MIPS32NUMCOREREGS; i++)
+	{
+		uint32_t regvalue;
+		regvalue = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
+		if (regvalue != context[i])
+		{
+			LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
+				mips32->core_cache->reg_list[i].name, context[i]);
+			buf_set_u32(mips32->core_cache->reg_list[i].value,
+					0, 32, context[i]);
+			mips32->core_cache->reg_list[i].valid = 1;
+			mips32->core_cache->reg_list[i].dirty = 1;
+		}
+	}
+
+	mips32->isa_mode = isa_mode;
+
 	return ERROR_OK;
 }
 
@@ -441,3 +598,144 @@ int mips32_enable_interrupts(struct target *target, int enable)
 
 	return ERROR_OK;
 }
+
+int mips32_checksum_memory(struct target *target, uint32_t address,
+		uint32_t count, uint32_t* checksum)
+{
+	struct working_area *crc_algorithm;
+	struct reg_param reg_params[2];
+	struct mips32_algorithm mips32_info;
+	int retval;
+	uint32_t i;
+
+	static const uint32_t mips_crc_code[] =
+	{
+		0x248C0000,		/* addiu 	$t4, $a0, 0 */
+		0x24AA0000,		/* addiu	$t2, $a1, 0 */
+		0x2404FFFF,		/* addiu	$a0, $zero, 0xffffffff */
+		0x10000010,		/* beq		$zero, $zero, ncomp */
+		0x240B0000,		/* addiu	$t3, $zero, 0 */
+						/* nbyte: */
+		0x81850000,		/* lb		$a1, ($t4) */
+		0x218C0001,		/* addi		$t4, $t4, 1 */
+		0x00052E00,		/* sll		$a1, $a1, 24 */
+		0x3C0204C1,		/* lui		$v0, 0x04c1 */
+		0x00852026,		/* xor		$a0, $a0, $a1 */
+		0x34471DB7,		/* ori		$a3, $v0, 0x1db7 */
+		0x00003021,		/* addu		$a2, $zero, $zero */
+						/* loop: */
+		0x00044040,		/* sll		$t0, $a0, 1 */
+		0x24C60001,		/* addiu	$a2, $a2, 1 */
+		0x28840000,		/* slti		$a0, $a0, 0 */
+		0x01074826,		/* xor		$t1, $t0, $a3 */
+		0x0124400B,		/* movn		$t0, $t1, $a0 */
+		0x28C30008,		/* slti		$v1, $a2, 8 */
+		0x1460FFF9,		/* bne		$v1, $zero, loop */
+		0x01002021,		/* addu		$a0, $t0, $zero */
+						/* ncomp: */
+		0x154BFFF0,		/* bne		$t2, $t3, nbyte */
+		0x256B0001,		/* addiu	$t3, $t3, 1 */
+		0x7000003F,		/* sdbbp */
+	};
+
+	/* make sure we have a working area */
+	if (target_alloc_working_area(target, sizeof(mips_crc_code), &crc_algorithm) != ERROR_OK)
+	{
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	}
+
+	/* convert flash writing code into a buffer in target endianness */
+	for (i = 0; i < ARRAY_SIZE(mips_crc_code); i++)
+		target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), mips_crc_code[i]);
+
+	mips32_info.common_magic = MIPS32_COMMON_MAGIC;
+	mips32_info.isa_mode = MIPS32_ISA_MIPS32;
+
+	init_reg_param(&reg_params[0], "a0", 32, PARAM_IN_OUT);
+	buf_set_u32(reg_params[0].value, 0, 32, address);
+
+	init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT);
+	buf_set_u32(reg_params[1].value, 0, 32, count);
+
+	if ((retval = target_run_algorithm(target, 0, NULL, 0, NULL,
+			crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code)-4), 10000, &mips32_info)) != ERROR_OK)
+	{
+		destroy_reg_param(&reg_params[0]);
+		destroy_reg_param(&reg_params[1]);
+		target_free_working_area(target, crc_algorithm);
+		return 0;
+	}
+
+	*checksum = buf_get_u32(reg_params[0].value, 0, 32);
+
+	destroy_reg_param(&reg_params[0]);
+	destroy_reg_param(&reg_params[1]);
+
+	target_free_working_area(target, crc_algorithm);
+
+	return ERROR_OK;
+}
+
+/** Checks whether a memory region is zeroed. */
+int mips32_blank_check_memory(struct target *target,
+		uint32_t address, uint32_t count, uint32_t* blank)
+{
+	struct working_area *erase_check_algorithm;
+	struct reg_param reg_params[3];
+	struct mips32_algorithm mips32_info;
+	int retval;
+	uint32_t i;
+
+	static const uint32_t erase_check_code[] =
+	{
+						/* nbyte: */
+		0x80880000,		/* lb		$t0, ($a0) */
+		0x00C83024,		/* and		$a2, $a2, $t0 */
+		0x24A5FFFF,		/* addiu	$a1, $a1, -1 */
+		0x14A0FFFC,		/* bne		$a1, $zero, nbyte */
+		0x24840001,		/* addiu	$a0, $a0, 1 */
+		0x7000003F		/* sdbbp */
+	};
+
+	/* make sure we have a working area */
+	if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
+	{
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	}
+
+	/* convert flash writing code into a buffer in target endianness */
+	for (i = 0; i < ARRAY_SIZE(erase_check_code); i++)
+		target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t), erase_check_code[i]);
+
+	mips32_info.common_magic = MIPS32_COMMON_MAGIC;
+	mips32_info.isa_mode = MIPS32_ISA_MIPS32;
+
+	init_reg_param(&reg_params[0], "a0", 32, PARAM_OUT);
+	buf_set_u32(reg_params[0].value, 0, 32, address);
+
+	init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT);
+	buf_set_u32(reg_params[1].value, 0, 32, count);
+
+	init_reg_param(&reg_params[2], "a2", 32, PARAM_IN_OUT);
+	buf_set_u32(reg_params[2].value, 0, 32, 0xff);
+
+	if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
+			erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &mips32_info)) != ERROR_OK)
+	{
+		destroy_reg_param(&reg_params[0]);
+		destroy_reg_param(&reg_params[1]);
+		destroy_reg_param(&reg_params[2]);
+		target_free_working_area(target, erase_check_algorithm);
+		return 0;
+	}
+
+	*blank = buf_get_u32(reg_params[2].value, 0, 32);
+
+	destroy_reg_param(&reg_params[0]);
+	destroy_reg_param(&reg_params[1]);
+	destroy_reg_param(&reg_params[2]);
+
+	target_free_working_area(target, erase_check_algorithm);
+
+	return ERROR_OK;
+}
diff --git a/src/target/mips32.h b/src/target/mips32.h
index b731c68..94d29ff 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -85,6 +85,12 @@ struct mips32_core_reg
 	struct mips32_common *mips32_common;
 };
 
+struct mips32_algorithm
+{
+	int common_magic;
+	enum mips32_isa_mode isa_mode;
+};
+
 #define MIPS32_OP_BEQ	0x04
 #define MIPS32_OP_BNE	0x05
 #define MIPS32_OP_ADDI	0x08
@@ -164,5 +170,9 @@ int mips32_register_commands(struct command_context *cmd_ctx);
 
 int mips32_get_gdb_reg_list(struct target *target,
 		struct reg **reg_list[], int *reg_list_size);
+int mips32_checksum_memory(struct target *target, uint32_t address,
+		uint32_t count, uint32_t* checksum);
+int mips32_blank_check_memory(struct target *target,
+		uint32_t address, uint32_t count, uint32_t* blank);
 
 #endif	/*MIPS32_H*/
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 1a65c50..2e88ca0 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -72,8 +72,8 @@ struct target_type mips_m4k_target =
 	.read_memory = mips_m4k_read_memory,
 	.write_memory = mips_m4k_write_memory,
 	.bulk_write_memory = mips_m4k_bulk_write_memory,
-	.checksum_memory = mips_m4k_checksum_memory,
-	.blank_check_memory = NULL,
+	.checksum_memory = mips32_checksum_memory,
+	.blank_check_memory = mips32_blank_check_memory,
 
 	.run_algorithm = mips32_run_algorithm,
 
@@ -148,13 +148,8 @@ int mips_m4k_debug_entry(struct target *target)
 	/* default to mips32 isa, it will be changed below if required */
 	mips32->isa_mode = MIPS32_ISA_MIPS32;
 
-	if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
-	{
-		if (buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32) & 0x01)
-		{
-			/* core is running mips16e isa */
-			mips32->isa_mode = MIPS32_ISA_MIPS16E;
-		}
+	if (ejtag_info->impcode & EJTAG_IMP_MIPS16) {
+		mips32->isa_mode = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1);
 	}
 
 	LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
@@ -396,6 +391,10 @@ int mips_m4k_resume(struct target *target, int current, uint32_t address, int ha
 		mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 	}
 
+	if (ejtag_info->impcode & EJTAG_IMP_MIPS16) {
+		buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
+	}
+
 	resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
 
 	mips32_restore_context(target);
@@ -1025,8 +1024,3 @@ int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, uint32_t
 
 	return retval;
 }
-
-int mips_m4k_checksum_memory(struct target *target, uint32_t address, uint32_t size, uint32_t *checksum)
-{
-	return ERROR_FAIL; /* use bulk read method */
-}
-- 
1.6.5.1.1367.gcd48


--------------080201070403000603060908--

[PATCH] MIPS: update arch_info access to match other targets

[Spencer O. <nt...@us...>]

 - add target_to_mips32 and target_to_m4k to match test of codebase.
 - mips32_arch_state now shows if processer is running mips16e isa.

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/target/mips32.c       |   46 +++++++++++++++---------------
 src/target/mips32.h       |   17 ++++++++++-
 src/target/mips32_pracc.c |    4 +-
 src/target/mips_ejtag.c   |   19 ++++++------
 src/target/mips_ejtag.h   |   14 +++++++--
 src/target/mips_m4k.c     |   68 ++++++++++++++++++++++++++------------------
 src/target/mips_m4k.h     |    7 ++++
 7 files changed, 107 insertions(+), 68 deletions(-)

diff --git a/src/target/mips32.c b/src/target/mips32.c
index 0f6f9b0..5bb4104 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -38,6 +38,11 @@ char* mips32_core_reg_list[] =
 	"status", "lo", "hi", "badvaddr", "cause", "pc"
 };
 
+const char *mips_isa_strings[] =
+{
+	"MIPS32", "MIPS16e"
+};
+
 struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
 {
 	{0, NULL, NULL},
@@ -103,7 +108,7 @@ int mips32_get_core_reg(struct reg *reg)
 	int retval;
 	struct mips32_core_reg *mips32_reg = reg->arch_info;
 	struct target *target = mips32_reg->target;
-	struct mips32_common *mips32_target = target->arch_info;
+	struct mips32_common *mips32_target = target_to_mips32(target);
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -139,7 +144,7 @@ int mips32_read_core_reg(struct target *target, int num)
 	struct mips32_core_reg *mips_core_reg;
 
 	/* get pointers to arch-specific information */
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 
 	if ((num < 0) || (num >= MIPS32NUMCOREREGS))
 		return ERROR_INVALID_ARGUMENTS;
@@ -159,7 +164,7 @@ int mips32_write_core_reg(struct target *target, int num)
 	struct mips32_core_reg *mips_core_reg;
 
 	/* get pointers to arch-specific information */
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 
 	if ((num < 0) || (num >= MIPS32NUMCOREREGS))
 		return ERROR_INVALID_ARGUMENTS;
@@ -177,7 +182,7 @@ int mips32_write_core_reg(struct target *target, int num)
 int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
 {
 	/* get pointers to arch-specific information */
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 	int i;
 
 	/* include floating point registers */
@@ -203,7 +208,7 @@ int mips32_save_context(struct target *target)
 	int i;
 
 	/* get pointers to arch-specific information */
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 
 	/* read core registers */
@@ -225,7 +230,7 @@ int mips32_restore_context(struct target *target)
 	int i;
 
 	/* get pointers to arch-specific information */
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 
 	for (i = 0; i < MIPS32NUMCOREREGS; i++)
@@ -244,15 +249,10 @@ int mips32_restore_context(struct target *target)
 
 int mips32_arch_state(struct target *target)
 {
-	struct mips32_common *mips32 = target->arch_info;
-
-	if (mips32->common_magic != MIPS32_COMMON_MAGIC)
-	{
-		LOG_ERROR("BUG: called for a non-MIPS32 target");
-		return ERROR_FAIL;
-	}
+	struct mips32_common *mips32 = target_to_mips32(target);
 
-	LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
+	LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32 "",
+		mips_isa_strings[mips32->isa_mode],
 		debug_reason_name(target),
 		buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
 
@@ -267,7 +267,7 @@ static const struct reg_arch_type mips32_reg_type = {
 struct reg_cache *mips32_build_reg_cache(struct target *target)
 {
 	/* get pointers to arch-specific information */
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 
 	int num_regs = MIPS32NUMCOREREGS;
 	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
@@ -327,7 +327,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_p
 
 int mips32_examine(struct target *target)
 {
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 
 	if (!target_was_examined(target))
 	{
@@ -347,7 +347,7 @@ int mips32_examine(struct target *target)
 int mips32_configure_break_unit(struct target *target)
 {
 	/* get pointers to arch-specific information */
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 	int retval;
 	uint32_t dcr, bpinfo;
 	int i;
@@ -359,7 +359,7 @@ int mips32_configure_break_unit(struct target *target)
 	if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
 		return retval;
 
-	if (dcr & (1 << 16))
+	if (dcr & EJTAG_DCR_IB)
 	{
 		/* get number of inst breakpoints */
 		if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
@@ -378,7 +378,7 @@ int mips32_configure_break_unit(struct target *target)
 			return retval;
 	}
 
-	if (dcr & (1 << 17))
+	if (dcr & EJTAG_DCR_DB)
 	{
 		/* get number of data breakpoints */
 		if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
@@ -416,19 +416,19 @@ int mips32_enable_interrupts(struct target *target, int enable)
 
 	if (enable)
 	{
-		if (!(dcr & (1 << 4)))
+		if (!(dcr & EJTAG_DCR_INTE))
 		{
 			/* enable interrupts */
-			dcr |= (1 << 4);
+			dcr |= EJTAG_DCR_INTE;
 			update = 1;
 		}
 	}
 	else
 	{
-		if (dcr & (1 << 4))
+		if (dcr & EJTAG_DCR_INTE)
 		{
 			/* disable interrupts */
-			dcr &= ~(1 << 4);
+			dcr &= ~EJTAG_DCR_INTE;
 			update = 1;
 		}
 	}
diff --git a/src/target/mips32.h b/src/target/mips32.h
index 4fe61bc..b731c68 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -26,7 +26,6 @@
 #include "target.h"
 #include "mips32_pracc.h"
 
-
 #define MIPS32_COMMON_MAGIC		0xB320B320
 
 /* offsets into mips32 core register cache */
@@ -36,10 +35,17 @@ enum
 	MIPS32NUMCOREREGS
 };
 
+enum mips32_isa_mode
+{
+	MIPS32_ISA_MIPS32 = 0,
+	MIPS32_ISA_MIPS16E = 1,
+};
+
+extern const char *mips_isa_strings[];
+
 struct mips32_comparator
 {
 	int used;
-	//int type;
 	uint32_t bp_value;
 	uint32_t reg_address;
 };
@@ -51,6 +57,7 @@ struct mips32_common
 	struct reg_cache *core_cache;
 	struct mips_ejtag ejtag_info;
 	uint32_t core_regs[MIPS32NUMCOREREGS];
+	enum mips32_isa_mode isa_mode;
 
 	int bp_scanned;
 	int num_inst_bpoints;
@@ -65,6 +72,12 @@ struct mips32_common
 	int (*write_core_reg)(struct target *target, int num);
 };
 
+static inline struct mips32_common *
+target_to_mips32(struct target *target)
+{
+	return target->arch_info;
+}
+
 struct mips32_core_reg
 {
 	uint32_t num;
diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index 52d31bd..11d5a43 100644
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -810,7 +810,7 @@ int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs)
 		MIPS32_LW(2,36*4,1),							/* lw $2,36*4($1) */
 		MIPS32_MTC0(2,13,0),							/* move $2 to cause*/
 		MIPS32_LW(2,37*4,1),							/* lw $2,37*4($1) */
-		MIPS32_MTC0(2,24,0),							/* move $2 to pc */
+		MIPS32_MTC0(2,24,0),							/* move $2 to depc (pc) */
 
 		MIPS32_LW(2,2*4,1),								/* lw $2,2*4($1) */
 		MIPS32_LW(1,0,15),								/* lw $1,($15) */
@@ -884,7 +884,7 @@ int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs)
 		MIPS32_SW(2,35*4,1),							/* sw $2,35*4($1) */
 		MIPS32_MFC0(2,13,0),							/* move cause to $2 */
 		MIPS32_SW(2,36*4,1),							/* sw $2,36*4($1) */
-		MIPS32_MFC0(2,24,0),							/* move pc to $2 */
+		MIPS32_MFC0(2,24,0),							/* move depc (pc) to $2 */
 		MIPS32_SW(2,37*4,1),							/* sw $2,37*4($1) */
 
 		MIPS32_LW(2,0,15),								/* lw $2,($15) */
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 58bd392..336adb5 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -264,16 +264,15 @@ int mips_ejtag_init(struct mips_ejtag *ejtag_info)
 			break;
 	}
 	LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
-		ejtag_info->impcode & (1 << 28) ? " R3k":    " R4k",
-		ejtag_info->impcode & (1 << 24) ? " DINT":   "",
-		ejtag_info->impcode & (1 << 22) ? " ASID_8": "",
-		ejtag_info->impcode & (1 << 21) ? " ASID_6": "",
-		ejtag_info->impcode & (1 << 16) ? " MIPS16": "",
-		ejtag_info->impcode & (1 << 14) ? " noDMA":  " DMA",
-		ejtag_info->impcode & (1 << 0)  ? " MIPS64": " MIPS32"
-);
-
-	if ((ejtag_info->impcode & (1 << 14)) == 0)
+		ejtag_info->impcode & EJTAG_IMP_R3K ? " R3k" : " R4k",
+		ejtag_info->impcode & EJTAG_IMP_DINT ? " DINT" : "",
+		ejtag_info->impcode & (1 << 22) ? " ASID_8" : "",
+		ejtag_info->impcode & (1 << 21) ? " ASID_6" : "",
+		ejtag_info->impcode & EJTAG_IMP_MIPS16 ? " MIPS16" : "",
+		ejtag_info->impcode & EJTAG_IMP_NODMA ? " noDMA" : " DMA",
+		ejtag_info->impcode & EJTAG_DCR_MIPS64  ? " MIPS64" : " MIPS32");
+
+	if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0)
 		LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
 
 	/* set initial state for ejtag control reg */
diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index e9da39e..2f62f2b 100644
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -40,7 +40,7 @@
 #define EJTAG_INST_TCBDATA		0x12
 #define EJTAG_INST_BYPASS		0xFF
 
-/* debug control register bits ECR */
+/* ejtag control register bits ECR */
 #define EJTAG_CTRL_TOF			(1 << 1)
 #define EJTAG_CTRL_TIF			(1 << 2)
 #define EJTAG_CTRL_BRKST		(1 << 3)
@@ -87,11 +87,20 @@
 #define EJTAG_DEBUG_DBD			(1 << 31)
 
 /* implementaion register bits */
+#define EJTAG_IMP_R3K			(1 << 28)
+#define EJTAG_IMP_DINT			(1 << 24)
 #define EJTAG_IMP_NODMA			(1 << 14)
 #define EJTAG_IMP_MIPS16		(1 << 16)
+#define EJTAG_DCR_MIPS64		(1 << 0)
 
-/* breakpoint support */
+/* Debug Control Register DCR */
 #define EJTAG_DCR				0xFF300000
+#define EJTAG_DCR_ENM			(1 << 29)
+#define EJTAG_DCR_DB			(1 << 17)
+#define EJTAG_DCR_IB			(1 << 16)
+#define EJTAG_DCR_INTE			(1 << 4)
+
+/* breakpoint support */
 #define EJTAG_IBS				0xFF301000
 #define EJTAG_IBA1				0xFF301100
 #define EJTAG_DBS				0xFF302000
@@ -107,7 +116,6 @@ struct mips_ejtag
 	struct jtag_tap *tap;
 	uint32_t impcode;
 	uint32_t idcode;
-	/*int use_dma;*/
 	uint32_t ejtag_ctrl;
 };
 
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index f229690..1a65c50 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -107,12 +107,12 @@ int mips_m4k_examine_debug_reason(struct target *target)
 		}
 
 		/* get info about data breakpoint support */
-		if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
+		if ((retval = target_read_u32(target, EJTAG_DBS, &break_status)) != ERROR_OK)
 			return retval;
 		if (break_status & 0x1f)
 		{
 			/* we have halted on a  breakpoint */
-			if ((retval = target_write_u32(target, 0xFF302000, 0)) != ERROR_OK)
+			if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
 				return retval;
 			target->debug_reason = DBG_REASON_WATCHPOINT;
 		}
@@ -123,14 +123,14 @@ int mips_m4k_examine_debug_reason(struct target *target)
 
 int mips_m4k_debug_entry(struct target *target)
 {
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 	uint32_t debug_reg;
 
 	/* read debug register */
 	mips_ejtag_read_debug(ejtag_info, &debug_reg);
 
-	/* make sure break uit configured */
+	/* make sure break unit configured */
 	mips32_configure_break_unit(target);
 
 	/* attempt to find halt reason */
@@ -145,9 +145,21 @@ int mips_m4k_debug_entry(struct target *target)
 
 	mips32_save_context(target);
 
+	/* default to mips32 isa, it will be changed below if required */
+	mips32->isa_mode = MIPS32_ISA_MIPS32;
+
+	if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
+	{
+		if (buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32) & 0x01)
+		{
+			/* core is running mips16e isa */
+			mips32->isa_mode = MIPS32_ISA_MIPS16E;
+		}
+	}
+
 	LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
-		*(uint32_t*)(mips32->core_cache->reg_list[MIPS32_PC].value),
-		  target_state_name(target));
+			buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
+			target_state_name(target));
 
 	return ERROR_OK;
 }
@@ -155,7 +167,7 @@ int mips_m4k_debug_entry(struct target *target)
 int mips_m4k_poll(struct target *target)
 {
 	int retval;
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 	uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
 
@@ -215,7 +227,7 @@ int mips_m4k_poll(struct target *target)
 
 int mips_m4k_halt(struct target *target)
 {
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 
 	LOG_DEBUG("target->state: %s",
@@ -260,7 +272,7 @@ int mips_m4k_halt(struct target *target)
 
 int mips_m4k_assert_reset(struct target *target)
 {
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 
 	LOG_DEBUG("target->state: %s",
@@ -339,7 +351,7 @@ int mips_m4k_soft_reset_halt(struct target *target)
 
 int mips_m4k_single_step_core(struct target *target)
 {
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 
 	/* configure single step mode */
@@ -358,7 +370,7 @@ int mips_m4k_single_step_core(struct target *target)
 
 int mips_m4k_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
 {
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 	struct breakpoint *breakpoint = NULL;
 	uint32_t resume_pc;
@@ -430,7 +442,7 @@ int mips_m4k_resume(struct target *target, int current, uint32_t address, int ha
 int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
 {
 	/* get pointers to arch-specific information */
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 	struct breakpoint *breakpoint = NULL;
 
@@ -494,7 +506,7 @@ void mips_m4k_enable_breakpoints(struct target *target)
 
 int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 	struct mips32_comparator * comparator_list = mips32->inst_break_list;
 	int retval;
 
@@ -585,8 +597,8 @@ int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint
 int mips_m4k_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
 	/* get pointers to arch-specific information */
-	struct mips32_common *mips32 = target->arch_info;
-	struct mips32_comparator * comparator_list = mips32->inst_break_list;
+	struct mips32_common *mips32 = target_to_mips32(target);
+	struct mips32_comparator *comparator_list = mips32->inst_break_list;
 	int retval;
 
 	if (!breakpoint->set)
@@ -659,7 +671,7 @@ int mips_m4k_unset_breakpoint(struct target *target, struct breakpoint *breakpoi
 
 int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 
 	if (breakpoint->type == BKPT_HARD)
 	{
@@ -680,7 +692,7 @@ int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint
 int mips_m4k_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
 	/* get pointers to arch-specific information */
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -701,8 +713,8 @@ int mips_m4k_remove_breakpoint(struct target *target, struct breakpoint *breakpo
 
 int mips_m4k_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
 {
-	struct mips32_common *mips32 = target->arch_info;
-	struct mips32_comparator * comparator_list = mips32->data_break_list;
+	struct mips32_common *mips32 = target_to_mips32(target);
+	struct mips32_comparator *comparator_list = mips32->data_break_list;
 	int wp_num = 0;
 	/*
 	 * watchpoint enabled, ignore all byte lanes in value register
@@ -769,8 +781,8 @@ int mips_m4k_set_watchpoint(struct target *target, struct watchpoint *watchpoint
 int mips_m4k_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
 {
 	/* get pointers to arch-specific information */
-	struct mips32_common *mips32 = target->arch_info;
-	struct mips32_comparator * comparator_list = mips32->data_break_list;
+	struct mips32_common *mips32 = target_to_mips32(target);
+	struct mips32_comparator *comparator_list = mips32->data_break_list;
 
 	if (!watchpoint->set)
 	{
@@ -794,7 +806,7 @@ int mips_m4k_unset_watchpoint(struct target *target, struct watchpoint *watchpoi
 
 int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 {
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 
 	if (mips32->num_data_bpoints_avail < 1)
 	{
@@ -811,7 +823,7 @@ int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint
 int mips_m4k_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
 {
 	/* get pointers to arch-specific information */
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -844,7 +856,7 @@ void mips_m4k_enable_watchpoints(struct target *target)
 
 int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 
 	LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
@@ -876,7 +888,7 @@ int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size,
 
 int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 
 	LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
@@ -923,7 +935,7 @@ int mips_m4k_init_arch_info(struct target *target, struct mips_m4k_common *mips_
 
 int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
 {
-	struct mips_m4k_common *mips_m4k = calloc(1,sizeof(struct mips_m4k_common));
+	struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
 
 	mips_m4k_init_arch_info(target, mips_m4k, target->tap);
 
@@ -933,7 +945,7 @@ int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
 int mips_m4k_examine(struct target *target)
 {
 	int retval;
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 	uint32_t idcode = 0;
 
@@ -963,7 +975,7 @@ int mips_m4k_examine(struct target *target)
 
 int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
 {
-	struct mips32_common *mips32 = target->arch_info;
+	struct mips32_common *mips32 = target_to_mips32(target);
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 	struct working_area *source;
 	int retval;
diff --git a/src/target/mips_m4k.h b/src/target/mips_m4k.h
index c5f9be2..4fe14a0 100644
--- a/src/target/mips_m4k.h
+++ b/src/target/mips_m4k.h
@@ -35,6 +35,13 @@ struct mips_m4k_common
 	struct mips32_common mips32_common;
 };
 
+static inline struct mips_m4k_common *
+target_to_m4k(struct target *target)
+{
+	return container_of(target->arch_info,
+			struct mips_m4k_common, mips32_common);
+}
+
 int mips_m4k_bulk_write_memory(struct target *target,
 		uint32_t address, uint32_t count, uint8_t *buffer);
 
-- 
1.6.5.1.1367.gcd48


--------------090707090006010006040401--

[PATCH 1/4] parport: output port as hex rather than dec

[Spencer O. <nt...@us...>]

Signed-off-by: Spencer Oliver <nt...@us...>
---
 src/jtag/drivers/parport.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/jtag/drivers/parport.c b/src/jtag/drivers/parport.c
index 7ff675b..d8c511e 100644
--- a/src/jtag/drivers/parport.c
+++ b/src/jtag/drivers/parport.c
@@ -425,7 +425,7 @@ COMMAND_HANDLER(parport_handle_parport_port_command)
 		}
 	}
 
-	command_print(CMD_CTX, "parport port = %u", parport_port);
+	command_print(CMD_CTX, "parport port = 0x%" PRIx16 "", parport_port);
 
 	return ERROR_OK;
 }
-- 
1.6.5.1.1367.gcd48


--------------070709040409060906050005--