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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-846-geb6f2745b

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- Log -----------------------------------------------------------------
commit eb6f2745b7d9924d0dddeab91c1743867c4e812c
Author: Sergey Matsievskiy <mat...@gm...>
Date:   Wed Sep 18 20:12:48 2024 +0300

    flash/nor: add DesignWare SPI controller driver
    
    Driver for DesignWare SPI controller, found on many SoCs (see compatible
    list in Linux device tree bindings
    Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml). This
    implementation only supports MIPS as it was the only one available for the
    tests, however, adding support for other architectures should require only
    few adjustments. Driver relies on flash/nor/spi.h to find Flash chip info.
    Driver internal functions support 24bit addressing mode, but due to
    limitations of flash/nor/spi.h, it is not used. The reported writing speed
    is about 60kb/s.
    Lint, sanitizer and valgrind reported warnings were not related to the
    driver.
    
    Change-Id: Id3df5626ab88055f034f74f274823051dedefeb1
    Signed-off-by: Sergey Matsievskiy <mat...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8400
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/contrib/loaders/flash/dw-spi/Makefile b/contrib/loaders/flash/dw-spi/Makefile
new file mode 100644
index 000000000..e86827882
--- /dev/null
+++ b/contrib/loaders/flash/dw-spi/Makefile
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+TOOLCHAIN:=mipsel-linux-gnu-
+CC:=$(TOOLCHAIN)gcc
+OBJCOPY:=$(TOOLCHAIN)objcopy
+CFLAGS:=-O2 -Wall -Wextra -fpic -Wno-int-to-pointer-cast
+SRC=dw-spi.c
+OBJ=$(patsubst %.c, %.o,$(SRC))
+
+# sparx-iv
+ifeq ($(TOOLCHAIN),mipsel-linux-gnu-)
+	CFLAGS+= -march=24kec
+endif
+
+all: \
+	$(TOOLCHAIN)transaction.inc \
+	$(TOOLCHAIN)erase.inc \
+	$(TOOLCHAIN)check_fill.inc \
+	$(TOOLCHAIN)program.inc \
+	$(TOOLCHAIN)read.inc
+
+$(TOOLCHAIN)%.bin: $(OBJ)
+	$(OBJCOPY) --dump-section .$*=$@ $<
+
+%.inc: %.bin
+	xxd -i > $@ < $<
+
+.PHONY: clean
+clean:
+	rm -rf .ccls-cache
+	find . \( \
+	-iname "*.o" \
+	-o -iname "*.bin" \
+	-o -iname "*.inc" \
+	\) -delete
diff --git a/contrib/loaders/flash/dw-spi/dw-spi.c b/contrib/loaders/flash/dw-spi/dw-spi.c
new file mode 100644
index 000000000..66b743913
--- /dev/null
+++ b/contrib/loaders/flash/dw-spi/dw-spi.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/**
+ * @file
+ * Helper functions for DesignWare SPI Core driver.
+ * These helpers are loaded into CPU and execute Flash manipulation algorithms
+ * at full CPU speed. Due to inability to control nCS pin, this is the only way
+ * to communicate with Flash chips connected via DW SPI serial interface.
+ *
+ * In order to avoid using stack, all functions used in helpers are inlined.
+ * Software breakpoints are used to terminate helpers.
+ *
+ * Pushing byte to TX FIFO does not make byte immediately available in RX FIFO
+ * and nCS is only asserted when TX FIFO is not empty. General approach is to
+ * fill TX FIFO with as many bytes as possible, at the same time reading
+ * available bytes from RX FIFO.
+ *
+ * This file contains helper functions.
+ */
+
+#include "dw-spi.h"
+
+#include "../../../../src/flash/nor/dw-spi-helper.h"
+
+/**
+ * @brief Generic flash transaction.
+ *
+ * @param[in] arg: Function arguments.
+ */
+__attribute__((section(".transaction"))) void
+transaction(struct dw_spi_transaction *arg)
+{
+	register uint8_t *buffer_tx = (uint8_t *)arg->buffer;
+	register uint8_t *buffer_rx = buffer_tx;
+	register uint32_t size = arg->size;
+	register volatile uint8_t *status = (uint8_t *)arg->status_reg;
+	register volatile uint8_t *data = (uint8_t *)arg->data_reg;
+
+	wait_tx_finish(status);
+	flush_rx(status, data);
+
+	for (; size > 0; size--) {
+		send_u8(status, data, *buffer_tx++);
+		if (arg->read_flag && rx_available(status))
+			*buffer_rx++ = rcv_byte(data);
+	}
+
+	// Pushed all data to TX FIFO. Read bytes left in RX FIFO.
+	if (arg->read_flag) {
+		while (buffer_rx < buffer_tx) {
+			wait_rx_available(status);
+			*buffer_rx++ = rcv_byte(data);
+		}
+	}
+
+	RETURN;
+}
+
+/**
+ * @brief Check flash sectors are filled with pattern. Primary use for
+ * checking sector erase state.
+ *
+ * @param[in] arg: Function arguments.
+ */
+__attribute__((section(".check_fill"))) void
+check_fill(struct dw_spi_check_fill *arg)
+{
+	register uint32_t tx_size;
+	register uint32_t rx_size;
+	register uint32_t dummy_count;
+	register uint8_t filled;
+	register uint8_t *fill_status_array = (uint8_t *)arg->fill_status_array;
+	register volatile uint8_t *status = (uint8_t *)arg->status_reg;
+	register volatile uint8_t *data = (uint8_t *)arg->data_reg;
+
+	for (; arg->sector_count > 0; arg->sector_count--,
+								  arg->address += arg->sector_size,
+								  fill_status_array++) {
+		wait_tx_finish(status);
+		flush_rx(status, data);
+
+		/*
+		 * Command byte and address bytes make up for dummy_count number of
+		 * bytes, that must be skipped in RX FIFO before actual data arrives.
+		 */
+		send_u8(status, data, arg->read_cmd);
+		if (arg->four_byte_mode) {
+			dummy_count = 1 + 4; // Command byte + 4 address bytes
+			send_u32(status, data, arg->address);
+		} else {
+			dummy_count = 1 + 3; // Command byte + 3 address bytes
+			send_u24(status, data, arg->address);
+		}
+
+		for (tx_size = arg->sector_size, rx_size = arg->sector_size, filled = 1;
+			 tx_size > 0; tx_size--) {
+			send_u8(status, data, 0); // Dummy write to push out read data.
+			if (rx_available(status)) {
+				if (dummy_count > 0) {
+					// Read data not arrived yet.
+					rcv_byte(data);
+					dummy_count--;
+				} else {
+					if (rcv_byte(data) != arg->pattern) {
+						filled = 0;
+						break;
+					}
+					rx_size--;
+				}
+			}
+		}
+		if (filled) {
+			for (; rx_size > 0; rx_size--) {
+				wait_rx_available(status);
+				if (rcv_byte(data) != arg->pattern) {
+					filled = 0;
+					break;
+				}
+			}
+		}
+		*fill_status_array = filled;
+	}
+
+	RETURN;
+}
+
+/**
+ * @brief Erase flash sectors.
+ *
+ * @param[in] arg: Function arguments.
+ */
+__attribute__((section(".erase"))) void
+erase(struct dw_spi_erase *arg)
+{
+	register uint32_t address = arg->address;
+	register uint32_t count = arg->sector_count;
+	register volatile uint8_t *status = (uint8_t *)arg->status_reg;
+	register volatile uint8_t *data = (uint8_t *)arg->data_reg;
+
+	for (; count > 0; count--, address += arg->sector_size) {
+		write_enable(status, data, arg->write_enable_cmd);
+		wait_write_enable(status, data, arg->read_status_cmd,
+						  arg->write_enable_mask);
+
+		erase_sector(status, data, arg->erase_sector_cmd, address,
+					 arg->four_byte_mode);
+		wait_busy(status, data, arg->read_status_cmd, arg->busy_mask);
+	}
+
+	RETURN;
+}
+
+/**
+ * @brief Flash program.
+ *
+ * @param[in] arg: Function arguments.
+ */
+__attribute__((section(".program"))) void
+program(struct dw_spi_program *arg)
+{
+	register uint8_t *buffer = (uint8_t *)arg->buffer;
+	register uint32_t buffer_size = arg->buffer_size;
+	register volatile uint8_t *status = (uint8_t *)arg->status_reg;
+	register volatile uint8_t *data = (uint8_t *)arg->data_reg;
+	register uint32_t page_size;
+
+	while (buffer_size > 0) {
+		write_enable(status, data, arg->write_enable_cmd);
+		wait_write_enable(status, data, arg->read_status_cmd,
+						  arg->write_enable_mask);
+
+		wait_tx_finish(status);
+
+		send_u8(status, data, arg->program_cmd);
+		if (arg->four_byte_mode)
+			send_u32(status, data, arg->address);
+		else
+			send_u24(status, data, arg->address);
+
+		for (page_size = MIN(arg->page_size, buffer_size); page_size > 0;
+			 page_size--, buffer_size--) {
+			send_u8(status, data, *buffer++);
+		}
+		arg->address += arg->page_size;
+		wait_busy(status, data, arg->read_status_cmd, arg->busy_mask);
+	}
+
+	RETURN;
+}
+
+/**
+ * @brief Read data from flash.
+ *
+ * @param[in] arg: Function arguments.
+ */
+__attribute__((section(".read"))) void
+read(struct dw_spi_read *arg)
+{
+	register uint32_t tx_size = arg->buffer_size;
+	register uint32_t rx_size = arg->buffer_size;
+	register uint32_t dummy_count;
+	register uint8_t *buffer = (uint8_t *)arg->buffer;
+	register volatile uint8_t *status = (uint8_t *)arg->status_reg;
+	register volatile uint8_t *data = (uint8_t *)arg->data_reg;
+
+	wait_tx_finish(status);
+	flush_rx(status, data);
+
+	/*
+	 * Command byte and address bytes make up for dummy_count number of
+	 * bytes, that must be skipped in RX FIFO before actual data arrives.
+	 */
+	send_u8(status, data, arg->read_cmd);
+	if (arg->four_byte_mode) {
+		dummy_count = 1 + 4; // Command byte + 4 address bytes
+		send_u32(status, data, arg->address);
+	} else {
+		dummy_count = 1 + 3; // Command byte + 3 address bytes
+		send_u24(status, data, arg->address);
+	}
+
+	for (; tx_size > 0; tx_size--) {
+		send_u8(status, data, 0); // Dummy write to push out read data.
+		if (rx_available(status)) {
+			if (dummy_count > 0) {
+				rcv_byte(data);
+				dummy_count--;
+			} else {
+				*buffer++ = rcv_byte(data);
+				rx_size--;
+			}
+		}
+	}
+	while (rx_size > 0) {
+		wait_rx_available(status);
+		if (dummy_count > 0) {
+			// Read data not arrived yet.
+			rcv_byte(data);
+			dummy_count--;
+		} else {
+			*buffer++ = rcv_byte(data);
+			rx_size--;
+		}
+	}
+
+	RETURN;
+}
diff --git a/contrib/loaders/flash/dw-spi/dw-spi.h b/contrib/loaders/flash/dw-spi/dw-spi.h
new file mode 100644
index 000000000..9efa768e6
--- /dev/null
+++ b/contrib/loaders/flash/dw-spi/dw-spi.h
@@ -0,0 +1,313 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/**
+ * @file
+ * Helper functions for DesignWare SPI Core driver.
+ * These helpers are loaded into CPU and execute Flash manipulation algorithms
+ * at full CPU speed. Due to inability to control nCS pin, this is the only way
+ * to communicate with Flash chips connected via DW SPI serial interface.
+ *
+ * In order to avoid using stack, all functions used in helpers are inlined.
+ * Software breakpoints are used to terminate helpers.
+ *
+ * This file contains functions, common to helpers.
+ */
+
+#ifndef _DW_SPI_H_
+#define _DW_SPI_H_
+
+#include <stdint.h>
+#include <sys/param.h>
+
+#include "../../../../src/helper/types.h"
+
+/**
+ * @brief SI busy status bit.
+ *
+ * Set when serial transfer is in progress, cleared when master is idle or
+ * disabled.
+ */
+#define DW_SPI_STATUS_BUSY 0x01
+
+/**
+ * @brief SI TX FIFO not full status bit.
+ *
+ * Set when TX FIFO has room for one or more data-word.
+ */
+#define DW_SPI_STATUS_TFNF 0x02
+
+/**
+ * @brief SI TX FIFO empty status bit.
+ */
+#define DW_SPI_STATUS_TFE 0x04
+
+/**
+ * @brief SI RX FIFO not empty status bit.
+ */
+#define DW_SPI_STATUS_RFNE 0x08
+
+/**
+ * @brief Return from helper function.
+ */
+#define RETURN            \
+	do {                  \
+		asm("sdbbp\n\t"); \
+		return;           \
+	} while (0)
+
+/**
+ * @brief Append byte to TX FIFO.
+ *
+ * For each transferred byte, DW SPI controller receives a byte into RX FIFO.
+ * Slave data are read by pushing dummy bytes to TX FIFO.
+ *
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] byte: Data to push.
+ */
+__attribute__((always_inline)) static inline void
+_send_byte(volatile uint8_t *dr, uint8_t byte)
+{
+	*dr = byte;
+}
+
+/**
+ * @brief Get byte from RX FIFO.
+ *
+ * Reading RX byte removes it from RX FIFO.
+ *
+ * @param[in] dr: Pointer to DR register.
+ * @return RX FIFO byte.
+ */
+__attribute__((always_inline)) static inline uint8_t
+rcv_byte(volatile uint8_t *dr)
+{
+	return *dr;
+}
+
+/**
+ * @brief Check transmission is currently in progress.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @retval 1: Transmission is in progress.
+ * @retval 0: Controller is idle or off.
+ */
+__attribute__((always_inline)) static inline int
+tx_in_progress(volatile uint8_t *sr)
+{
+	return (*sr ^ DW_SPI_STATUS_TFE) & (DW_SPI_STATUS_BUSY | DW_SPI_STATUS_TFE);
+}
+
+/**
+ * @brief Wait for controller to finish previous transaction.
+ *
+ * @param[in] sr: Pointer to SR register.
+ */
+__attribute__((always_inline)) static inline void
+wait_tx_finish(volatile uint8_t *sr)
+{
+	while (tx_in_progress(sr))
+		;
+}
+
+/**
+ * @brief Wait for room in TX FIFO.
+ *
+ * @param[in] sr: Pointer to SR register.
+ */
+__attribute__((always_inline)) static inline void
+wait_tx_available(volatile uint8_t *sr)
+{
+	while (!(*sr & DW_SPI_STATUS_TFNF))
+		;
+}
+
+/**
+ * @brief Check for data available in RX FIFO.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @retval 1: Data available.
+ * @retval 0: No data available.
+ */
+__attribute__((always_inline)) static inline int
+rx_available(volatile uint8_t *sr)
+{
+	return *sr & DW_SPI_STATUS_RFNE;
+}
+
+/**
+ * @brief Wait for data in RX FIFO.
+ *
+ * @param[in] sr: Pointer to SR register.
+ */
+__attribute__((always_inline)) static inline void
+wait_rx_available(volatile uint8_t *sr)
+{
+	while (!rx_available(sr))
+		;
+}
+
+/**
+ * @brief Flush RX FIFO.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ */
+__attribute__((always_inline)) static inline void
+flush_rx(volatile uint8_t *sr, volatile uint8_t *dr)
+{
+	while (*sr & DW_SPI_STATUS_RFNE)
+		*dr;
+}
+
+/**
+ * @brief Append variable number of bytes to TX FIFO.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] word: Data to append.
+ * @param[in] bytes: Number of bytes to append.
+ */
+__attribute__((always_inline)) static inline void
+_send_bytes(volatile uint8_t *sr, volatile uint8_t *dr, uint32_t word,
+			int bytes)
+{
+	for (register int i = bytes - 1; i >= 0; i--) {
+		wait_tx_available(sr);
+		_send_byte(dr, (word >> (i * 8)) & 0xff);
+	}
+}
+
+/**
+ * @brief Append 8 bit value to TX FIFO.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] word: Data to push.
+ */
+__attribute__((always_inline)) static inline void
+send_u8(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t byte)
+{
+	wait_tx_available(sr);
+	_send_byte(dr, byte);
+}
+
+/**
+ * @brief Append 24 bit value to TX FIFO.
+ *
+ * Used to send Flash addresses in 24 bit mode.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] word: Data to push.
+ */
+__attribute__((always_inline)) static inline void
+send_u24(volatile uint8_t *sr, volatile uint8_t *dr, uint32_t word)
+{
+	_send_bytes(sr, dr, word, 3);
+}
+
+/**
+ * @brief Append 32 bit value to TX FIFO.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] word: Data to push.
+ */
+__attribute__((always_inline)) static inline void
+send_u32(volatile uint8_t *sr, volatile uint8_t *dr, uint32_t word)
+{
+	_send_bytes(sr, dr, word, 4);
+}
+
+/**
+ * @brief Read chip status register.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] stat_cmd: Read status command.
+ * @return Chip status.
+ */
+__attribute__((always_inline)) static inline uint8_t
+read_status(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t stat_cmd)
+{
+	wait_tx_finish(sr);
+	flush_rx(sr, dr);
+	/*
+	 * Don't bother with wait_tx_available() as TX FIFO is empty
+	 * and we only send two bytes.
+	 */
+	_send_byte(dr, stat_cmd);
+	_send_byte(dr, 0); // Dummy write to push out read data.
+	wait_rx_available(sr);
+	rcv_byte(dr); // Dummy read to skip command byte.
+	wait_rx_available(sr);
+	return rcv_byte(dr);
+}
+
+/**
+ * @brief Enable Flash chip write.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] we_cmd: Write enable command.
+ */
+__attribute__((always_inline)) static inline void
+write_enable(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t we_cmd)
+{
+	wait_tx_finish(sr);
+	_send_byte(dr, we_cmd);
+}
+
+/**
+ * @brief Erase Flash sector.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] erase_cmd: Erase sector cmd.
+ * @param[in] address: Sector address.
+ * @param[in] four_byte_mode: Device is in 32 bit mode flag.
+ */
+__attribute__((always_inline)) static inline void
+erase_sector(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t erase_cmd,
+			 uint32_t address, uint8_t four_byte_mode)
+{
+	wait_tx_finish(sr);
+	_send_byte(dr, erase_cmd);
+	if (four_byte_mode)
+		send_u32(sr, dr, address);
+	else
+		send_u24(sr, dr, address);
+}
+
+/**
+ * @brief Wait for write enable flag.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] stat_cmd: Read status command.
+ * @param[in] we_mask: Write enable status mask.
+ */
+__attribute__((always_inline)) static inline void
+wait_write_enable(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t stat_cmd,
+				  uint8_t we_mask)
+{
+	while (!(read_status(sr, dr, stat_cmd) & we_mask))
+		;
+}
+
+/**
+ * @brief Wait while flash is busy.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] stat_cmd: Read status command.
+ * @param[in] busy_mask: Flash busy mask.
+ */
+__attribute__((always_inline)) static inline void
+wait_busy(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t stat_cmd,
+		  uint8_t busy_mask)
+{
+	while (read_status(sr, dr, stat_cmd) & busy_mask)
+		;
+}
+
+#endif // _DW_SPI_H_
diff --git a/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-check_fill.inc b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-check_fill.inc
new file mode 100644
index 000000000..94c732fe5
--- /dev/null
+++ b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-check_fill.inc
@@ -0,0 +1,39 @@
+  0x0b, 0x00, 0x82, 0x88, 0x1f, 0x00, 0x8a, 0x88, 0x0f, 0x00, 0x83, 0x88,
+  0x17, 0x00, 0x86, 0x88, 0x08, 0x00, 0x82, 0x98, 0x1c, 0x00, 0x8a, 0x98,
+  0x0c, 0x00, 0x83, 0x98, 0x14, 0x00, 0x86, 0x98, 0x25, 0x38, 0x80, 0x00,
+  0x54, 0x00, 0x40, 0x10, 0xf8, 0xff, 0x09, 0x24, 0x00, 0x00, 0x64, 0x90,
+  0x05, 0x00, 0x84, 0x30, 0x04, 0x00, 0x84, 0x38, 0xfc, 0xff, 0x80, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30,
+  0x07, 0x00, 0x40, 0x50, 0x25, 0x00, 0xe5, 0x90, 0x00, 0x00, 0xc2, 0x90,
+  0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0xfc, 0xff, 0x40, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x25, 0x00, 0xe5, 0x90, 0x00, 0x00, 0x62, 0x90,
+  0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0xc5, 0xa0, 0x26, 0x00, 0xe2, 0x90, 0x45, 0x00, 0x40, 0x10,
+  0x03, 0x00, 0xe8, 0x88, 0x00, 0x00, 0xe8, 0x98, 0x18, 0x00, 0x05, 0x24,
+  0x00, 0x00, 0x62, 0x90, 0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10,
+  0x06, 0x10, 0xa8, 0x00, 0xff, 0x00, 0x42, 0x30, 0xf8, 0xff, 0xa5, 0x24,
+  0x00, 0x00, 0xc2, 0xa0, 0xf8, 0xff, 0xa9, 0x14, 0x05, 0x00, 0x0b, 0x24,
+  0x07, 0x00, 0xe8, 0x88, 0x04, 0x00, 0xe8, 0x98, 0x1e, 0x00, 0x00, 0x11,
+  0x25, 0x28, 0x00, 0x01, 0x00, 0x00, 0x62, 0x90, 0x02, 0x00, 0x42, 0x30,
+  0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xa0,
+  0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0x06, 0x00, 0x40, 0x50,
+  0xff, 0xff, 0xa5, 0x24, 0x00, 0x00, 0xc2, 0x90, 0x25, 0x00, 0x60, 0x51,
+  0x24, 0x00, 0xec, 0x90, 0xff, 0xff, 0x6b, 0x25, 0xff, 0xff, 0xa5, 0x24,
+  0xf1, 0xff, 0xa0, 0x14, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x51,
+  0x01, 0x00, 0x04, 0x24, 0x24, 0x00, 0xe5, 0x90, 0x00, 0x00, 0x62, 0x90,
+  0x08, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0xc2, 0x90, 0xff, 0x00, 0x42, 0x30, 0x04, 0x00, 0xa2, 0x14,
+  0xff, 0xff, 0x08, 0x25, 0xf7, 0xff, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x04, 0x24, 0x00, 0x00, 0x44, 0xa1, 0x0b, 0x00, 0xe2, 0x88,
+  0x01, 0x00, 0x4a, 0x25, 0x08, 0x00, 0xe2, 0x98, 0xff, 0xff, 0x42, 0x24,
+  0x0b, 0x00, 0xe2, 0xa8, 0x08, 0x00, 0xe2, 0xb8, 0x03, 0x00, 0xe4, 0x88,
+  0x07, 0x00, 0xe5, 0x88, 0x00, 0x00, 0xe4, 0x98, 0x04, 0x00, 0xe5, 0x98,
+  0x21, 0x20, 0x85, 0x00, 0x03, 0x00, 0xe4, 0xa8, 0xae, 0xff, 0x40, 0x14,
+  0x00, 0x00, 0xe4, 0xb8, 0x3f, 0x00, 0x00, 0x70, 0x08, 0x00, 0xe0, 0x03,
+  0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x42, 0x30, 0xed, 0xff, 0x82, 0x55,
+  0x00, 0x00, 0x44, 0xa1, 0xd9, 0xff, 0x00, 0x10, 0xff, 0xff, 0x08, 0x25,
+  0x00, 0x00, 0xe8, 0x98, 0x10, 0x00, 0x05, 0x24, 0x00, 0x00, 0x62, 0x90,
+  0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, 0x06, 0x10, 0xa8, 0x00,
+  0xff, 0x00, 0x42, 0x30, 0xf8, 0xff, 0xa5, 0x24, 0x00, 0x00, 0xc2, 0xa0,
+  0xf8, 0xff, 0xa9, 0x14, 0x04, 0x00, 0x0b, 0x24, 0xbc, 0xff, 0x00, 0x10,
+  0x07, 0x00, 0xe8, 0x88
diff --git a/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-erase.inc b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-erase.inc
new file mode 100644
index 000000000..b72c7ea44
--- /dev/null
+++ b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-erase.inc
@@ -0,0 +1,39 @@
+  0x0b, 0x00, 0x88, 0x88, 0x25, 0x28, 0x80, 0x00, 0x03, 0x00, 0x86, 0x88,
+  0x0f, 0x00, 0x82, 0x88, 0x17, 0x00, 0x84, 0x88, 0x08, 0x00, 0xa8, 0x98,
+  0x00, 0x00, 0xa6, 0x98, 0x0c, 0x00, 0xa2, 0x98, 0x5f, 0x00, 0x00, 0x11,
+  0x14, 0x00, 0xa4, 0x98, 0xf8, 0xff, 0x07, 0x24, 0x1d, 0x00, 0xa9, 0x90,
+  0x00, 0x00, 0x43, 0x90, 0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38,
+  0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0xa0,
+  0x1c, 0x00, 0xaa, 0x90, 0x1f, 0x00, 0xa9, 0x90, 0x00, 0x00, 0x43, 0x90,
+  0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38, 0xfc, 0xff, 0x60, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30,
+  0x06, 0x00, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90,
+  0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0xfc, 0xff, 0x60, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0xa0, 0x00, 0x00, 0x80, 0xa0,
+  0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90, 0x00, 0x00, 0x43, 0x90,
+  0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x83, 0x90, 0x24, 0x18, 0x23, 0x01, 0xe4, 0xff, 0x60, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0xaa, 0x90, 0x21, 0x00, 0xa9, 0x90,
+  0x00, 0x00, 0x43, 0x90, 0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38,
+  0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0xa0,
+  0x31, 0x00, 0x20, 0x11, 0x10, 0x00, 0x09, 0x24, 0x18, 0x00, 0x09, 0x24,
+  0x00, 0x00, 0x43, 0x90, 0x02, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10,
+  0x06, 0x18, 0x26, 0x01, 0xff, 0x00, 0x63, 0x30, 0xf8, 0xff, 0x29, 0x25,
+  0xf9, 0xff, 0x27, 0x15, 0x00, 0x00, 0x83, 0xa0, 0x1c, 0x00, 0xaa, 0x90,
+  0x20, 0x00, 0xa9, 0x90, 0x00, 0x00, 0x43, 0x90, 0x05, 0x00, 0x63, 0x30,
+  0x04, 0x00, 0x63, 0x38, 0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0x06, 0x00, 0x60, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90, 0x00, 0x00, 0x43, 0x90,
+  0x08, 0x00, 0x63, 0x30, 0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x8a, 0xa0, 0x00, 0x00, 0x80, 0xa0, 0x00, 0x00, 0x43, 0x90,
+  0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x83, 0x90, 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30,
+  0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90,
+  0x24, 0x18, 0x23, 0x01, 0xe4, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00,
+  0x07, 0x00, 0xa3, 0x88, 0xff, 0xff, 0x08, 0x25, 0x04, 0x00, 0xa3, 0x98,
+  0xa4, 0xff, 0x00, 0x15, 0x21, 0x30, 0xc3, 0x00, 0x3f, 0x00, 0x00, 0x70,
+  0x08, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x90,
+  0x02, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, 0x06, 0x18, 0x26, 0x01,
+  0xff, 0x00, 0x63, 0x30, 0xf8, 0xff, 0x29, 0x25, 0xf9, 0xff, 0x27, 0x15,
+  0x00, 0x00, 0x83, 0xa0, 0xd1, 0xff, 0x00, 0x10, 0x1c, 0x00, 0xaa, 0x90
diff --git a/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-program.inc b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-program.inc
new file mode 100644
index 000000000..31500e01d
--- /dev/null
+++ b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-program.inc
@@ -0,0 +1,51 @@
+  0x13, 0x00, 0x88, 0x88, 0x25, 0x30, 0x80, 0x00, 0x0b, 0x00, 0x85, 0x88,
+  0x17, 0x00, 0x82, 0x88, 0x1f, 0x00, 0x84, 0x88, 0x10, 0x00, 0xc8, 0x98,
+  0x08, 0x00, 0xc5, 0x98, 0x14, 0x00, 0xc2, 0x98, 0x1c, 0x00, 0xc4, 0x98,
+  0x78, 0x00, 0x00, 0x11, 0xf8, 0xff, 0x07, 0x24, 0x25, 0x00, 0xc9, 0x90,
+  0x00, 0x00, 0x43, 0x90, 0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38,
+  0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0xa0,
+  0x24, 0x00, 0xca, 0x90, 0x27, 0x00, 0xc9, 0x90, 0x00, 0x00, 0x43, 0x90,
+  0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38, 0xfc, 0xff, 0x60, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30,
+  0x06, 0x00, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90,
+  0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0xfc, 0xff, 0x60, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0xa0, 0x00, 0x00, 0x80, 0xa0,
+  0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90, 0x00, 0x00, 0x43, 0x90,
+  0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x83, 0x90, 0x24, 0x18, 0x23, 0x01, 0xe4, 0xff, 0x60, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x90, 0x05, 0x00, 0x63, 0x30,
+  0x04, 0x00, 0x63, 0x38, 0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00,
+  0x26, 0x00, 0xc9, 0x90, 0x00, 0x00, 0x43, 0x90, 0x02, 0x00, 0x63, 0x30,
+  0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0xa0,
+  0x29, 0x00, 0xc3, 0x90, 0x47, 0x00, 0x60, 0x10, 0x03, 0x00, 0xca, 0x88,
+  0x00, 0x00, 0xca, 0x98, 0x18, 0x00, 0x09, 0x24, 0x00, 0x00, 0x43, 0x90,
+  0x02, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, 0x06, 0x18, 0x2a, 0x01,
+  0xff, 0x00, 0x63, 0x30, 0xf8, 0xff, 0x29, 0x25, 0x00, 0x00, 0x83, 0xa0,
+  0xf8, 0xff, 0x27, 0x15, 0x25, 0x58, 0x00, 0x01, 0x07, 0x00, 0xc3, 0x88,
+  0x04, 0x00, 0xc3, 0x98, 0x2b, 0x48, 0x03, 0x01, 0x0a, 0x58, 0x69, 0x00,
+  0x0d, 0x00, 0x60, 0x11, 0x21, 0x50, 0xab, 0x00, 0x00, 0x00, 0xa9, 0x90,
+  0x01, 0x00, 0xa5, 0x24, 0x00, 0x00, 0x43, 0x90, 0x02, 0x00, 0x63, 0x30,
+  0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0xa0,
+  0xf9, 0xff, 0xaa, 0x54, 0x00, 0x00, 0xa9, 0x90, 0x07, 0x00, 0xc3, 0x88,
+  0x23, 0x40, 0x0b, 0x01, 0x04, 0x00, 0xc3, 0x98, 0x03, 0x00, 0xc9, 0x88,
+  0x00, 0x00, 0xc9, 0x98, 0x21, 0x18, 0x23, 0x01, 0x03, 0x00, 0xc3, 0xa8,
+  0x00, 0x00, 0xc3, 0xb8, 0x24, 0x00, 0xca, 0x90, 0x28, 0x00, 0xc9, 0x90,
+  0x00, 0x00, 0x43, 0x90, 0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38,
+  0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x90,
+  0x08, 0x00, 0x63, 0x30, 0x06, 0x00, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x83, 0x90, 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30,
+  0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0xa0,
+  0x00, 0x00, 0x80, 0xa0, 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30,
+  0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90,
+  0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90, 0x24, 0x18, 0x23, 0x01,
+  0xe4, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x8b, 0xff, 0x00, 0x55,
+  0x25, 0x00, 0xc9, 0x90, 0x3f, 0x00, 0x00, 0x70, 0x08, 0x00, 0xe0, 0x03,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xca, 0x98, 0x10, 0x00, 0x09, 0x24,
+  0x00, 0x00, 0x43, 0x90, 0x02, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10,
+  0x06, 0x18, 0x2a, 0x01, 0xff, 0x00, 0x63, 0x30, 0xf8, 0xff, 0x29, 0x25,
+  0x00, 0x00, 0x83, 0xa0, 0xf8, 0xff, 0x27, 0x15, 0x25, 0x58, 0x00, 0x01,
+  0x07, 0x00, 0xc3, 0x88, 0x04, 0x00, 0xc3, 0x98, 0x2b, 0x48, 0x03, 0x01,
+  0x0a, 0x58, 0x69, 0x00, 0xbb, 0xff, 0x60, 0x15, 0x21, 0x50, 0xab, 0x00,
+  0xc6, 0xff, 0x00, 0x10, 0x03, 0x00, 0xc9, 0x88
diff --git a/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-read.inc b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-read.inc
new file mode 100644
index 000000000..3f18b7c2e
--- /dev/null
+++ b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-read.inc
@@ -0,0 +1,33 @@
+  0x0f, 0x00, 0x87, 0x88, 0x07, 0x00, 0x88, 0x88, 0x13, 0x00, 0x83, 0x88,
+  0x1b, 0x00, 0x85, 0x88, 0x0c, 0x00, 0x87, 0x98, 0x04, 0x00, 0x88, 0x98,
+  0x10, 0x00, 0x83, 0x98, 0x18, 0x00, 0x85, 0x98, 0x00, 0x00, 0x62, 0x90,
+  0x05, 0x00, 0x42, 0x30, 0x04, 0x00, 0x42, 0x38, 0xfc, 0xff, 0x40, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30,
+  0x07, 0x00, 0x40, 0x50, 0x20, 0x00, 0x86, 0x90, 0x00, 0x00, 0xa2, 0x90,
+  0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0xfc, 0xff, 0x40, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x86, 0x90, 0x00, 0x00, 0x62, 0x90,
+  0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0xa6, 0xa0, 0x21, 0x00, 0x82, 0x90, 0x35, 0x00, 0x40, 0x10,
+  0x03, 0x00, 0x82, 0x88, 0x18, 0x00, 0x06, 0x24, 0xf8, 0xff, 0x09, 0x24,
+  0x00, 0x00, 0x82, 0x98, 0x25, 0x20, 0x40, 0x00, 0x00, 0x00, 0x62, 0x90,
+  0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, 0x06, 0x10, 0xc4, 0x00,
+  0xff, 0x00, 0x42, 0x30, 0xf8, 0xff, 0xc6, 0x24, 0xf9, 0xff, 0xc9, 0x14,
+  0x00, 0x00, 0xa2, 0xa0, 0x05, 0x00, 0x06, 0x24, 0x23, 0x00, 0xe0, 0x10,
+  0x25, 0x20, 0xe0, 0x00, 0x00, 0x00, 0x62, 0x90, 0x02, 0x00, 0x42, 0x30,
+  0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xa0,
+  0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0x06, 0x00, 0x40, 0x50,
+  0xff, 0xff, 0x84, 0x24, 0x00, 0x00, 0xa2, 0x90, 0x14, 0x00, 0xc0, 0x50,
+  0x00, 0x00, 0x02, 0xa1, 0xff, 0xff, 0xc6, 0x24, 0xff, 0xff, 0x84, 0x24,
+  0xf1, 0xff, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0xe0, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30,
+  0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa2, 0x90,
+  0x03, 0x00, 0xc0, 0x50, 0xff, 0xff, 0xe7, 0x24, 0xf8, 0xff, 0x00, 0x10,
+  0xff, 0xff, 0xc6, 0x24, 0x06, 0x00, 0xe0, 0x10, 0x00, 0x00, 0x02, 0xa1,
+  0xf4, 0xff, 0x00, 0x10, 0x01, 0x00, 0x08, 0x25, 0xff, 0xff, 0xe7, 0x24,
+  0xec, 0xff, 0x00, 0x10, 0x01, 0x00, 0x08, 0x25, 0x3f, 0x00, 0x00, 0x70,
+  0x08, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x06, 0x24,
+  0xf8, 0xff, 0x09, 0x24, 0x00, 0x00, 0x82, 0x98, 0x25, 0x20, 0x40, 0x00,
+  0x00, 0x00, 0x62, 0x90, 0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10,
+  0x06, 0x10, 0xc4, 0x00, 0xff, 0x00, 0x42, 0x30, 0xf8, 0xff, 0xc6, 0x24,
+  0xf9, 0xff, 0xc9, 0x14, 0x00, 0x00, 0xa2, 0xa0, 0xcc, 0xff, 0x00, 0x10,
+  0x04, 0x00, 0x06, 0x24
diff --git a/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-transaction.inc b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-transaction.inc
new file mode 100644
index 000000000..384dbadb1
--- /dev/null
+++ b/contrib/loaders/flash/dw-spi/mipsel-linux-gnu-transaction.inc
@@ -0,0 +1,21 @@
+  0x03, 0x00, 0x85, 0x88, 0x0b, 0x00, 0x88, 0x88, 0x0f, 0x00, 0x83, 0x88,
+  0x17, 0x00, 0x86, 0x88, 0x00, 0x00, 0x85, 0x98, 0x08, 0x00, 0x88, 0x98,
+  0x0c, 0x00, 0x83, 0x98, 0x14, 0x00, 0x86, 0x98, 0x00, 0x00, 0x62, 0x90,
+  0x05, 0x00, 0x42, 0x30, 0x04, 0x00, 0x42, 0x38, 0xfc, 0xff, 0x40, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30,
+  0x06, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x90,
+  0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0xfc, 0xff, 0x40, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00,
+  0x25, 0x38, 0xa0, 0x00, 0x21, 0x40, 0x05, 0x01, 0x00, 0x00, 0xa9, 0x90,
+  0x01, 0x00, 0xa5, 0x24, 0x00, 0x00, 0x62, 0x90, 0x02, 0x00, 0x42, 0x30,
+  0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc9, 0xa0,
+  0x1c, 0x00, 0x82, 0x90, 0x08, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0x04, 0x00, 0x40, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x90, 0x01, 0x00, 0xe7, 0x24,
+  0xff, 0xff, 0xe2, 0xa0, 0xef, 0xff, 0xa8, 0x54, 0x00, 0x00, 0xa9, 0x90,
+  0x1c, 0x00, 0x82, 0x90, 0x0c, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x2b, 0x10, 0xe8, 0x00, 0x09, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x90, 0x01, 0x00, 0xe7, 0x24,
+  0xf9, 0xff, 0x07, 0x15, 0xff, 0xff, 0xe2, 0xa0, 0x3f, 0x00, 0x00, 0x70,
+  0x08, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 47a6f69eb..2ec49a4c0 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6421,6 +6421,75 @@ flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
 @end example
 @end deffn
 
+@deffn {Flash Driver} {dw-spi}
+@cindex DesignWare SPI controller driver
+@cindex DW-SPI
+Driver for SPI NOR flash chips connected via DesignWare SPI Core, used
+in number of MCUs.
+Currently, only MIPS M4K CPU architecture is supported.
+
+The flash size is autodetected based on the table of known JEDEC IDs hardcoded
+in the OpenOCD sources. When flash size is set to @var{0}, probed Flash
+size is used.
+
+This driver requires configuring DRAM controller first, setting up a
+working area big enough to hold read/write buffers and switching Flash
+chip to 32bit mode via Tcl commands.
+
+@quotation Note
+If chip contains Boot controller, its 24/32bit setting must match
+Flash chip. If Flash chip's reset line is not connected to JTAG adapter,
+CPU reset may cause these configurations to be out of sync.
+@end quotation
+
+
+Mandatory driver's arguments are
+
+@itemize
+@item @var{-freq} ... core frequency in Hz, used in communication speed
+calculation.
+@item @var{-simc} ... @var{SIMC} register block absolute address.
+This value is the same as for Linux's driver device tree register field.
+@item @var{-spi_mst} ... @var{SPI_MST} register address. When available,
+it is used for switching between SPI Boot and Master controllers. This
+value is the same as for Linux's driver device tree register field
+second argument. Set to @var{0} if SPI Boot controller not available.
+@item @var{-if_owner_offset} ... offset of @var{if_owner} field inside
+@var{SPI_MST} register. Set to @var{0} if SPI Boot controller not available.
+@end itemize
+
+Optional driver's arguments are
+
+@itemize
+@item @var{-speed} ... SPI device communication speed in Hz. Minimal
+speed depends on the @var{-freq} variable and has the value of
+@var{freq/0xfffe}. The default value is @var{1000000}.
+@item @var{-chip_select} ... Chip select pin. The default value
+is @var{0}.
+@item @var{-timeout} ... flash communication timeout in
+seconds. The default value is @var{600}.
+@end itemize
+
+For some SoCs there are shortcuts for mandatory arguments
+
+@itemize
+@item @var{-jaguar2} ... configuration for MSCC Jaguar2 SoC family.
+@item @var{-ocelot} ... configuration for MSCC Ocelot SoC family.
+@end itemize
+
+Driver provides shortcut arguments for MSCC @var{-jaguar2} and
+@var{-ocelot} network switch SOCs, which set the correct values for @var{-freq},
+@var{-simc}, @var{-spi_mst} and @var{-if_owner_offset} arguments.
+
+Example of equivalent configurations for Jaguar2 SoC
+
+@example
+flash bank $_FLASHNAME dw-spi 0x40000000 0x02000000 4 4 $_TARGETNAME -freq 250000000 -simc 0x70101000 -spi_mst 0x70000024 -if_owner_offset 6 -speed 3000000
+flash bank $_FLASHNAME dw-spi 0x40000000 0x02000000 4 4 $_TARGETNAME -jaguar2 -speed 3000000
+@end example
+
+@end deffn
+
 @subsection Internal Flash (Microcontrollers)
 
 @deffn {Flash Driver} {aduc702x}
diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am
index afa11e7d4..829687761 100644
--- a/src/flash/nor/Makefile.am
+++ b/src/flash/nor/Makefile.am
@@ -26,6 +26,7 @@ NOR_DRIVERS = \
 	%D%/cc26xx.c \
 	%D%/cfi.c \
 	%D%/dsp5680xx_flash.c \
+	%D%/dw-spi.c \
 	%D%/efm32.c \
 	%D%/em357.c \
 	%D%/eneispif.c \
@@ -89,6 +90,7 @@ NORHEADERS = \
 	%D%/cc26xx.h \
 	%D%/cfi.h \
 	%D%/driver.h \
+	%D%/dw-spi-helper.h \
 	%D%/imp.h \
 	%D%/non_cfi.h \
 	%D%/ocl.h \
diff --git a/src/flash/nor/driver.h b/src/flash/nor/driver.h
index 211661e21..852a55a11 100644
--- a/src/flash/nor/driver.h
+++ b/src/flash/nor/driver.h
@@ -254,6 +254,7 @@ extern const struct flash_driver cc26xx_flash;
 extern const struct flash_driver cc3220sf_flash;
 extern const struct flash_driver cfi_flash;
 extern const struct flash_driver dsp5680xx_flash;
+extern const struct flash_driver dw_spi_flash;
 extern const struct flash_driver efm32_flash;
 extern const struct flash_driver em357_flash;
 extern const struct flash_driver eneispif_flash;
diff --git a/src/flash/nor/drivers.c b/src/flash/nor/drivers.c
index dd9995ecb..ce97b8150 100644
--- a/src/flash/nor/drivers.c
+++ b/src/flash/nor/drivers.c
@@ -31,6 +31,7 @@ static const struct flash_driver * const flash_drivers[] = {
 	&cc26xx_flash,
 	&cfi_flash,
 	&dsp5680xx_flash,
+	&dw_spi_flash,
 	&efm32_flash,
 	&em357_flash,
 	&eneispif_flash,
diff --git a/src/flash/nor/dw-spi-helper.h b/src/flash/nor/dw-spi-helper.h
new file mode 100644
index 000000000..d3537557b
--- /dev/null
+++ b/src/flash/nor/dw-spi-helper.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/**
+ * @file
+ * Driver for SPI NOR flash chips connected via DesignWare SPI Core.
+ *
+ * In order to avoid using stack, all helper function arguments are packed
+ * into a single struct, passed by pointer.
+ *
+ * Pointers are represented by 64 bit integers to make structs compatible
+ * with 64 bit targets.
+ *
+ * This file contains helper function argument structures.
+ */
+
+#ifndef OPENOCD_FLASH_NOR_DW_SPI_HELPER_H
+#define OPENOCD_FLASH_NOR_DW_SPI_HELPER_H
+
+#include <stdint.h>
+
+/**
+ * @brief Arguments for transaction helper function.
+ */
+struct dw_spi_transaction {
+	uint64_t buffer;
+	///< Pointer to data buffer to send over SPI.
+	///< Return values are stored in place of output data when
+	///< dw_spi_transaction::read_flag is 1.
+	uint32_t size; ///< Size of dw_spi_transaction::buffer.
+	uint64_t status_reg; ///< Pointer to SR register.
+	uint64_t data_reg; ///< Pointer to DR register.
+	uint8_t read_flag;
+	///< When 1, store RX FIFO data to dw_spi_transaction::buffer.
+} __attribute__((packed));
+
+/**
+ * @brief Arguments for check_fill helper function.
+ */
+struct dw_spi_check_fill {
+	uint32_t address; ///< Starting address. Sector aligned.
+	uint32_t sector_size; ///< Sector size.
+	uint32_t sector_count; ///< Number of sectors to check.
+	uint64_t status_reg; ///< Pointer to SR register.
+	uint64_t data_reg; ///< Pointer to DR register.
+	uint64_t fill_status_array;
+	///< Pointer to array describing sectors fill status.
+	///< 1 if filled, 0 if not filled.
+	uint8_t pattern; ///< Fill pattern.
+	uint8_t read_cmd; ///< Read data command.
+	uint8_t four_byte_mode; ///< Four byte addressing mode flag.
+} __attribute__((packed));
+
+/**
+ * @brief Arguments for erase helper function.
+ */
+struct dw_spi_erase {
+	uint32_t address; ///< First sector address. Sector aligned.
+	uint32_t sector_size; ///< Sector size.
+	uint32_t sector_count; ///< Number of sectors to erase.
+	uint64_t status_reg; ///< Pointer to SR register.
+	uint64_t data_reg; ///< Pointer to DR register.
+	uint8_t read_status_cmd; ///< Read status command.
+	uint8_t write_enable_cmd; ///< Write enable command.
+	uint8_t erase_sector_cmd; ///< Erase sector command.
+	uint8_t write_enable_mask; ///< Write enable mask.
+	uint8_t busy_mask; ///< Busy mask.
+	uint8_t four_byte_mode; ///< Four byte addressing mode flag.
+} __attribute__((packed));
+
+/**
+ * @brief Arguments for program helper function.
+ */
+struct dw_spi_program {
+	uint32_t address;
+	///< First page address. Page aligned when write is crossing
+	///< the page boundary.
+	uint32_t page_size; ///< Page size.
+	uint64_t buffer; ///< Data buffer pointer.
+	uint32_t buffer_size; ///< Size of dw_spi_program::buffer.
+	uint64_t status_reg; ///< Pointer to SR register.
+	uint64_t data_reg; ///< Pointer to DR register.
+	uint8_t read_status_cmd; ///< Read status command.
+	uint8_t write_enable_cmd; ///< Write enable command.
+	uint8_t program_cmd; ///< Program command.
+	uint8_t write_enable_mask; ///< Write enable mask.
+	uint8_t busy_mask; ///< Busy mask.
+	uint8_t four_byte_mode; ///< Four byte addressing mode flag.
+} __attribute__((packed));
+
+/**
+ * @brief Arguments for read helper function.
+ */
+struct dw_spi_read {
+	uint32_t address; ///< First sector address.
+	uint64_t buffer; ///< Data buffer pointer.
+	uint32_t buffer_size; ///< Size of dw_spi_read::buffer.
+	uint64_t status_reg; ///< Pointer to SR register.
+	uint64_t data_reg; ///< Pointer to DR register.
+	uint8_t read_cmd; ///< Read data command.
+	uint8_t four_byte_mode; ///< Four byte addressing mode flag.
+} __attribute__((packed));
+
+#endif /* OPENOCD_FLASH_NOR_DW_SPI_HELPER_H */
diff --git a/src/flash/nor/dw-spi.c b/src/flash/nor/dw-spi.c
new file mode 100644
index 000000000..e1965477e
--- /dev/null
+++ b/src/flash/nor/dw-spi.c
@@ -0,0 +1,1608 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/**
+ * @file
+ * Driver for SPI NOR flash chips connected via DesignWare SPI Core.
+ * Controller's Linux driver is located at drivers/spi/spi-dw-mmio.c.
+ * DW-SPI is used in a number of processors, including Microsemi Jaguar2 and
+ * Ocelot switch chips.
+ *
+ * Serial interface (SI) nCS0 pin, which is usually connected to the external
+ * flash, cannot be controlled via GPIO controller: it is asserted only when
+ * TX FIFO is not empty. Since JTAG is not fast enough to fill TX FIFO and
+ * collect data from RX FIFO at the same time even on the slowest SPI clock
+ * speeds, driver can only operate using functions, loaded in target's memory.
+ * Therefore, it requires the user to set up DRAM controller and provide
+ * work-area.
+ *
+ * In Microsemi devices, serial interface pins may be governed either
+ * by Boot or Master controller. For these devices, additional configuration of
+ * spi_mst address is required to switch between the two.
+ *
+ * Currently supported devices typically have much more RAM then NOR Flash
+ * (Jaguar2 reference design has 256MB RAM and 32MB NOR Flash), so supporting
+ * work-area sizes smaller then transfer buffer seems like the unnecessary
+ * complication.
+ *
+ * This code was tested on Jaguar2 VSC7448 connected to Macronix MX25L25635F.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "dw-spi-helper.h"
+#include "imp.h"
+#include "spi.h"
+
+#include <helper/bits.h>
+#include <helper/time_support.h>
+#include <target/algorithm.h>
+#include <target/breakpoints.h>
+#include <target/mips32.h>
+#include <target/target_type.h>
+
+/**
+ * @brief IP block placement map.
+ *
+ * Used for dynamic definition of the register map.
+ *
+ * IP block is used on different chips and placed in different locations.
+ * This structure defines some implementation specific variables.
+ */
+struct dw_spi_regmap {
+	uint32_t freq; ///< Clock frequency.
+	target_addr_t simc; ///< Absolute offset of SIMC register block.
+	target_addr_t spi_mst;
+	///< Absolute offset of ICPU_CFG:SPI_MST register. 0 if not available.
+	uint8_t si_if_owner_offset;
+	///< Offset of \ref si_mode bits in ICPU_CFG:SPI_MST.
+};
+
+/**
+ * @brief Register map for Jaguar2 switch devices.
+ */
+static const struct dw_spi_regmap jaguar2_regmap = {
+	.freq = 250000000UL,
+	.simc = 0x70101000UL,
+	.spi_mst = 0x70000024UL,
+	.si_if_owner_offset = 6,
+};
+
+/**
+ * @brief Register map for Ocelot switch devices.
+ */
+static const struct dw_spi_regmap ocelot_regmap = {
+	.freq = 250000000UL,
+	.simc = 0x70101000UL,
+	.spi_mst = 0x70000024UL,
+	.si_if_owner_offset = 4,
+};
+
+#define DW_SPI_IF_OWNER_WIDTH 2 ///< IF owner register field width.
+
+/**
+ * @brief Owner of the SI interface.
+ */
+enum dw_spi_si_mode {
+	DW_SPI_SI_MODE_BOOT = 1,
+	///< Boot controller maps contents of SPI Flash to memory in read-only mode.
+	DW_SPI_SI_MODE_MASTER = 2,
+	///< SPI controller mode for reading/writing SPI Flash.
+};
+
+#define DW_SPI_REG_CTRLR0 0x00 ///< General configuration register.
+#define DW_SPI_REG_SIMCEN 0x08 ///< Master controller enable register.
+#define DW_SPI_REG_SER 0x10 ///< Slave select register.
+#define DW_SPI_REG_BAUDR 0x14 ///< Baud rate configuration register.
+#define DW_SPI_REG_SR 0x28 ///< Status register.
+#define DW_SPI_REG_IMR 0x2c ///< Interrupt configuration register.
+#define DW_SPI_REG_DR 0x60 ///< Data register.
+
+#define DW_SPI_REG_CTRLR0_DFS(x) ((x) & GENMASK(3, 0)) ///< Data frame size.
+#define DW_SPI_REG_CTRLR0_FRF(x) (((x) << 4) & GENMASK(5, 4)) ///< SI protocol.
+#define DW_SPI_REG_CTRLR0_SCPH(x) ((!!(x)) << 6) ///< Probe position.
+#define DW_SPI_REG_CTRLR0_SCPOL(x) ((!!(x)) << 7) ///< Probe polarity.
+#define DW_SPI_REG_CTRLR0_TMOD(x) (((x) << 8) & GENMASK(9, 8)) ///< SI mode.
+#define DW_SPI_REG_SIMCEN_SIMCEN(x) (!!(x)) ///< Controller enable.
+#define DW_SPI_REG_SER_SER(x) ((x) & GENMASK(15, 0)) ///< Slave select bitmask.
+#define DW_SPI_REG_BAUDR_SCKDV(x) ((x) & GENMASK(15, 0)) ///< Clock divisor.
+
+/**
+ * @brief Driver private state.
+ */
+struct dw_spi_driver {
+	bool probed; ///< Bank is probed.
+	uint32_t id; ///< Chip ID.
+	unsigned int speed; ///< Flash speed.
+	unsigned int timeout; ///< Flash timeout in milliseconds.
+	uint8_t chip_select_bitmask; ///< Chip select bitmask.
+	bool four_byte_mode; ///< Flash chip is in 32bit address mode.
+	enum dw_spi_si_mode saved_ctrl_mode;
+	///< Previously selected controller mode.
+	struct dw_spi_regmap regmap; ///< SI controller regmap.
+	const struct flash_device *spi_flash; ///< SPI flash device info.
+};
+
+/**
+ * @brief Register used to pass argument struct to helper functions.
+ */
+#define DW_SPI_ARG_REG "r4"
+
+/**
+ * @brief Default timeout value in ms for flash transaction jobs.
+ */
+#define DW_SPI_TIMEOUT_DEFAULT (600 * 1000)
+
+/**
+ * @brief Timeout value in ms for short flash transactions,
+ * e.g. reading flash ID and status register.
+ */
+#define DW_SPI_TIMEOUT_TRANSACTION 1000
+
+/**
+ * @brief Select SI interface owner.
+ *
+ * Mode selection is skipped if Boot controller not available on target
+ * (i.e. spi_mst command argument is not configured).
+ *
+ * @param[in] bank: Flash bank.
+ * @param[in] mode: New controller mode.
+ * @return Command execution status.
+ */
+static int
+dw_spi_ctrl_mode(const struct flash_bank *const bank, enum dw_spi_si_mode mode)
+{
+	struct target *const target = bank->target;
+	const struct dw_spi_driver *const driver = bank->driver_priv;
+	const struct dw_spi_regmap *const regmap = &driver->regmap;
+
+	if (!regmap->spi_mst)
+		return ERROR_OK;
+
+	uint32_t ctrl;
+	int ret = target_read_u32(target, regmap->spi_mst, &ctrl);
+	if (ret) {
+		LOG_ERROR("DW SPI SPI:MST register read error");
+		return ret;
+	}
+	ctrl &= ~GENMASK(DW_SPI_IF_OWNER_WIDTH + driver->regmap.si_if_owner_offset,
+					 driver->regmap.si_if_owner_offset);
+	ctrl |= mode << driver->regmap.si_if_owner_offset;
+
+	ret = target_write_u32(target, regmap->spi_mst, ctrl);
+	if (ret)
+		LOG_ERROR("DW SPI controller mode configuration error");
+
+	return ret;
+}
+
+/**
+ * @brief Select master controller as SI interface owner.
+ *
+ * Previous interface owner is restored via dw_spi_ctrl_mode_restore() function.
+ * Mode selection is skipped if Boot controller not available on target
+ * (i.e. spi_mst command argument is not configured).
+ *
+ * @param[in] bank: Flash bank.
+ * @param[in] mode: New controller mode.
+ * @return Command execution status.
+ */
+static int
+dw_spi_ctrl_mode_configure(const struct flash_bank *const bank,
+						   enum dw_spi_si_mode mode)
+{
+	struct target *const target = bank->target;
+	struct dw_spi_driver *const driver = bank->driver_priv;
+	const struct dw_spi_regmap *const regmap = &driver->regmap;
+
+	if (!regmap->spi_mst)
+		return ERROR_OK;
+
+	uint32_t ctrl;
+	int ret = target_read_u32(target, regmap->spi_mst, &ctrl);
+	if (ret) {
+		LOG_ERROR("DW SPI controller mode query error");
+		return ret;
+	}
+	driver->saved_ctrl_mode =
+		(enum dw_spi_si_mode)((ctrl >> driver->regmap.si_if_owner_offset) &
+							  GENMASK(DW_SPI_IF_OWNER_WIDTH, 0));
+
+	return dw_spi_ctrl_mode(bank, mode);
+}
+
+/**
+ * @brief Restore SI controller mode.
+ *
+ * Restore initially configured SI controller mode. Undo configuration done by
+ * dw_spi_ctrl_mode_configure() function.
+ * Mode selection is skipped if Boot controller not available on target
+ * (i.e. spi_mst command argument is not configured).
+ *
+ * @param[in] bank: Flash bank.
+ * @return Command execution status.
+ */
+static int
+dw_spi_ctrl_mode_restore(const struct flash_bank *const bank)
+{
+	const struct dw_spi_driver *const driver = bank->driver_priv;
+
+	return dw_spi_ctrl_mode(bank, driver->saved_ctrl_mode);
+}
+
+/**
+ * @brief Enable master controller.
+ *
+ * Configuration of the master controller must be done when it is disabled.
+ *
+ * @param[in] bank: Flash bank.
+ * @param[in] value: New enable state.
+ * @return Command execution status.
+ */
+static int
+dw_spi_master_ctrl_enable(const struct flash_bank *const bank, bool value)
+{
+	struct target *const target = bank->target;
+	const struct dw_spi_driver *const driver = bank->driver_priv;
+	const struct dw_spi_regmap *const regmap = &driver->regmap;
+
+	int ret = target_write_u32(target, regmap->simc + DW_SPI_REG_SIMCEN,
+							   DW_SPI_REG_SIMCEN_SIMCEN(value));
+	if (ret)
+		LOG_ERROR("DW SPI master controller enable flag configuration error");
+
+	return ret;
+}
+
+/**
+ * @brief Configure SI transfer mode.
+ *
+ * @param[in] bank: Flash bank.
+ * @return Command execution status.
+ */
+static int
+dw_spi_ctrl_configure_si(const struct flash_bank *const bank)
+{
+	struct target *const target = bank->target;
+	const struct dw_spi_driver *const driver = bank->driver_priv;
+	const struct dw_spi_regmap *const regmap = &driver->regmap;
+
+	// 8 bit frame; Motorola protocol; middle lo probe; TX RX mode
+	const uint32_t mode = DW_SPI_REG_CTRLR0_DFS(0x7) |
+						  DW_SPI_REG_CTRLR0_FRF(0) |
+						  DW_SPI_REG_CTRLR0_SCPH(0) |
+						  DW_SPI_REG_CTRLR0_SCPOL(0) |
+						  DW_SPI_REG_CTRLR0_TMOD(0);
+
+	int ret = target_write_u32(target, regmap->simc + DW_SPI_REG_CTRLR0, mode);
+	if (ret) {
+		LOG_ERROR("DW SPI master controller configuration query error");
+		return ret;
+	}
+
+	ret = target_write_u32(target, regmap->simc + DW_SPI_REG_SER,
+						   DW_SPI_REG_SER_SER(driver->chip_select_bitmask));
+	if (ret)
+		LOG_ERROR("DW SPI slave select configuration error");
+
+	return ret;
+}
+
+/**
+ * @brief Configure SI transfer speed.
+ *
+ * @param[in] bank: Flash bank.
+ * @return Command execution status.
+ */
+static int
+dw_spi_ctrl_configure_speed(const struct flash_bank *const bank)
+{
+	struct target *const target = bank->target;
+	const struct dw_spi_driver *const driver = bank->driver_priv;
+	const struct dw_spi_regmap *const regmap = &driver->regmap;
+
+	// divisor LSB must be zero
+	const uint16_t div = MIN((regmap->freq / driver->speed), 0xfffe) & 0xfffe;
+
+	int ret = target_write_u32(target, regmap->simc + DW_SPI_REG_BAUDR,
+							   DW_SPI_REG_BAUDR_SCKDV(div));
+	if (ret) {
+		LOG_ERROR("DW SPI speed configuration error");
+		return ret;
+	}
+
+	unsigned int speed = regmap->freq / div;
+	LOG_DEBUG("DW SPI setting NOR controller speed to %u kHz", speed / 1000);
+
+	return ret;
+}
+
+/**
+ * @brief Disable SI master controller interrupts.
+ *
+ * @param[in] bank: Flash bank.
+ * @return Command execution status.
+ */
+static int
+dw_spi_ctrl_disable_interrupts(const struct flash_bank *const bank)
+{
+	struct target *const target = bank->target;
+	const struct dw_spi_driver *const driver = bank->driver_priv;
+	const struct dw_spi_regmap *const regmap = &driver->regmap;
+
+	int ret = target_write_u32(target, regmap->simc + DW_SPI_REG_IMR, 0);
+	if (ret)
+		LOG_ERROR("DW SPI disable interrupts error");
+
+	return ret;
+}
+
+/**
+ * @brief Do data transaction.
+ *
+ * Buffer data are sent and replaced with received data. Total buffer size
+ * is a sum of TX and RX messages. RX portion of the buffer is initially
+ * filled with dummy values, which get replaced by the message.
+ *
+ * @param[in] bank: Flash bank.
+ * @param[in,out] buffer: Data buffer. If \p read flag is set, buffer is
+ * filled with received data.
+ * @param[in] size: \p buffer size.
+ * @param[in] read: The read flag. If set to true, read values will override
+ * \p buffer.
+ * @return Command execution status.
+ */
+static int
+dw_spi_ctrl_transaction(const struct flash_bank *const bank,
+						uint8_t *const buffer, size_t size, bool read)
+{
+	struct target *const target = bank->target;
+	const struct dw_spi_driver *const driver = bank->driver_priv;
+	const struct dw_spi_regmap *const regmap = &driver->regmap;
+
+	static const uint8_t target_code[] = {
+#include "../../../contrib/loaders/flash/dw-spi/mipsel-linux-gnu-transaction.inc"
+	};
+	const size_t target_code_size = sizeof(target_code);
+	const size_t total_working_area_size =
+		target_code_size + sizeof(struct dw_spi_transaction) + size;
+
+	// allocate working area, memory args and data buffer
+	struct working_area *helper;
+	int ret = target_alloc_working_area(target, target_code_size, &helper);
+	if (ret) {
+		LOG_ERROR("DW SPI could not allocate working area. Need %zx",
+				  total_working_area_size);
+		goto err_helper;
+	}
+
+	struct working_area *helper_args;
+	ret = target_alloc_working_area(target, sizeof(struct dw_spi_transaction),
+									&helper_args);
+	if (ret) {
+		LOG_ERROR("DW SPI could not allocate working area. Need %zx",
+				  total_working_area_size);
+		goto err_helper_args;
+	}
+
+	struct working_area *target_buffer;
+	ret = target_alloc_working_area(target, size, &target_buffer);
+	if (ret) {
+		LOG_ERROR("DW SPI could not allocate working area. Need %zx",
+				  total_working_area_size);
+		goto err_target_buffer;
+	}
+
+	// write algorithm code and buffer to working areas
+	ret = target_write_buffer(target, helper->address, target_code_size,
+							  target_code);
+	if (ret) {
+		LOG_ERROR("DW SPI writing to working area error");
+		goto err_write_buffer;
+	}
+
+	ret = target_write_buffer(target, target_buffer->address, size, buffer);
+	if (ret) {
+		LOG_ERROR("DW SPI writing to working area error");
+		goto err_write_buffer;
+	}
+
+	// prepare helper execution
+	struct mips32_algorithm mips32_algo = { .common_magic = MIPS32_COMMON_MAGIC,
+											.isa_mode = MIPS32_ISA_MIPS32 };
+
+	struct reg_param reg_param;
+	init_reg_param(&reg_param, DW_SPI_ARG_REG, 32, PARAM_OUT);
+	struct mem_param mem_param;
+	init_mem_param(&mem_param, helper_args->address, helper_args->size,
+				   PARAM_OUT);
+
+	// Set the arguments for the helper
+	buf_set_u32(reg_param.value, 0, 32, helper_args->address);
+
+	struct dw_spi_transaction *helper_args_val =
+		(struct dw_spi_transaction *)mem_param.value;
+	target_buffer_set_u32(target, (uint8_t *)&helper_args_val->buffer,
+						  target_buffer->address);
+	target_buffer_set_u32(target, (uint8_t *)&helper_args_val->size, size);
+	target_buffer_set_u32(target, (uint8_t *)&helper_args_val->status_reg,
+						  regmap->simc + DW_SPI_REG_SR);
+	target_buffer_set_u32(target, (uint8_t *)&helper_args_val->data_reg,
+						  regmap->simc + DW_SPI_REG_DR);
+	helper_args_val->read_flag = read;
+
+	ret = target_run_algorithm(target, 1, &mem_param, 1, &reg_param,
+							   helper->address, 0, DW_SPI_TIMEOUT_TRANSACTION,
+							   &mips32_algo);
+
+	if (ret) {
+		LOG_ERROR("DW SPI flash algorithm error");
+		goto cleanup;
+	}
+
+	if (read) {
+		ret = target_read_buffer(target, target_buffer->address, size, buffer);
+		if (ret)
+			LOG_ERROR("DW SPI target buffer read error");
+	}
+
+cleanup:
+	destroy_reg_param(&reg_param);
+	destroy_mem_param(&mem_param);
+
+err_write_buffer:
+	target_free_working_area(target, target_buffer);
+err_target_buffer:
+	target_free_working_area(target, helper_args);
+err_helper_args:
+	target_free_working_area(target, helper);
+err_helper:
+
+	return ret;
+}
+
+/**
+ * @brief Check that selected region is filled with pattern.
+ *
+ * This function is used for Flash erase checking.
+ *
+ * @param[in] bank: Flash bank.
+ * @param[in] address: Starting address. Sector aligned.
+ * @param[in] sector_size: Size of sector.
+ * @param[in] sector_count: Number of sectors.
+ * @param[in] pattern: Fill pattern.
+ * @param[in] read_cmd: Flash read command.
+ * @param[out] buffer: Filled flag array. Must hold \p sector_count number
+ * of entries.
+ * @return Command execution status.
+ */
+static int
+dw_spi_ctrl_check_sectors_fill(const struct flash_bank *const bank,
+							   uint32_t address, size_t sector_size,
+							   size_t sector_count, uint8_t pattern,
+							   uint8_t read_cmd, uint8_t *buffer)
+{
+	struct target *const target = bank->target;
+	const struct dw_spi_driver *const driver = bank->driver_priv;
+	const struct dw_spi_regmap *const regmap = &driver->regmap;
+
+	static const uint8_t target_code[] = {
+#include "../../../contrib/loaders/flash/dw-spi/mipsel-linux-gnu-check_fill.inc"
+	};
+	const size_t target_code_size = sizeof(target_code);
+	const size_t total_working_area_size =
+		target_code_size + sizeof(struct dw_spi_check_fill) + sector_count;
+
+	// allocate working area, memory args and data buffer
+	struct working_area *helper;
+	int ret = target_alloc_working_area(target, target_code_size, &helper);
+	if (ret) {
+		LOG_ERROR("DW SPI could not allocate working area. Need %zx",
+				  total_working_area_size);
+		goto err_helper;
+	}
+
+	struct working_area *helper_args;
+	ret = target_alloc_working_area(target, sizeof(struct dw_spi_check_fill),
+									&helper_args);
+	if (ret) {
+		LOG_ERROR("DW SPI could not allocate working area. Need %zx",
+				  total_working_area_size);
+		goto err_helper_args;
+	}
+
+	struct working_area *target_buffer;
+	ret = target_alloc_working_area(target, sector_count, &target_buffer);
+	if (ret) {
+		LOG_ERROR("DW SPI could not allocate working area. Need %zx",
+				  total_working_area_size);
+		goto err_target_buffer;
+	}
+
+	// write algorithm code and buffer to working areas
+	ret = target_write_buffer(target, helper->address, target_code_size,
+							  target_code);
+	if (ret) {
+		LOG_ERROR("DW SPI writing to working area error");
+		goto err_write_buffer;
+	}
+
+	// prepare helper execution
+	struct mips32_algorithm mips32_algo = { .common_magic = MIPS32_COMMON_MAGIC,
+											.isa_mode = MIPS32_ISA_MIPS32 };
+
+	struct reg_param reg_param;
+	init_reg_param(&reg_param, DW_SPI_ARG_REG, 32, PARAM_OUT);
+	struct mem_param mem_param;
+	init_mem_param(&mem_param, helper_args->address, helper_args->size,
+				   PARAM_OUT);
+
+	// Set the arguments for the helper
+	buf_set_u32(reg_param.value, 0, 32, helper_args->address);
+
+	struct dw_spi_check_fill *helper_args_val =
+		(struct dw_spi_check_fill *)mem_param.value;
+	target_buffer_set_u32(target, (uint8_t *)&helper_args_val->address,
+						  address);
+	target_buffer_set_u32(target, (uint8_t *)&helper_args_val->sector_size,
+						  sector_size);
+	target_buffer_set_u32(target, (uint8_t *)&helper_args_val->sector_count,
+						  sector_count);
+	target_buffer_set_u32(target, (uint8_t *)&helper_args_val->status_reg,
+						  regmap->simc + DW_SPI_REG_SR);
+	target_buffer_set_u32(target, (uint8_t *)&helper_args_val->data_reg,
+						  regmap->simc + DW_SPI_REG_DR);
+	target_buffer_set_u32(target,
+						  (uint8_t *)&helper_args_val->fill_status_array,
+						  target_buffer->address);
+	helper_args_val->pattern = pattern;
+	helper_args_val->read_cmd = read_cmd;
+	helper_args_val->four_byte_mode = driver->four_byte_mode;
+
+	ret = target_run_algorithm(target, 1, &mem_param, 1, &reg_param,
+							   helper->address, 0, driver->timeout,
+							   &mips32_algo);
+
+	if (ret) {
+		LOG_ERROR("DW SPI flash algorithm error");
+		goto cleanup;
+	}
+
+	ret = target_read_buffer(target, target_buffer->address, sector_count,
+							 buffer);
+	if (ret)
+		LOG_ERROR("DW SPI target buffer read error");
+
+cleanup:
+	destroy_reg_param(&reg_param);
+	destroy_mem_param(&mem_param);
+
+err_write_buffer:
+	target_free_working_area(target, target_buffer);
+err_target_buffer:
+	target_free_working_area(target, helper_args);
+err_helper_args:
+	target_fr...
 
[truncated message content]

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-845-gce38758e3

[openocd-gerrit <ope...@us...>]

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       via  ce38758e3df929d5b27947ab7b987cc319a628aa (commit)
      from  a510d51a78f14fbb8416037a587ce1bfc6016d24 (commit)

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- Log -----------------------------------------------------------------
commit ce38758e3df929d5b27947ab7b987cc319a628aa
Author: Paul Fertser <fer...@gm...>
Date:   Tue Nov 26 23:16:15 2024 +0200

    rtos: chibios: replace malloc+sprintf with alloc_printf
    
    This makes it safer and simpler at the same time.
    
    Signed-off-by: Paul Fertser <fer...@gm...>
    Change-Id: Ie294f1f6033ffc9f46b39210e2f7fc2f648e80ac
    Reviewed-on: https://review.openocd.org/c/openocd/+/8598
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/rtos/chibios.c b/src/rtos/chibios.c
index f4ee33a49..af590c2cb 100644
--- a/src/rtos/chibios.c
+++ b/src/rtos/chibios.c
@@ -421,9 +421,11 @@ static int chibios_update_threads(struct rtos *rtos)
 		else
 			state_desc = "Unknown";
 
-		curr_thrd_details->extra_info_str = malloc(strlen(
-					state_desc)+8);
-		sprintf(curr_thrd_details->extra_info_str, "State: %s", state_desc);
+		curr_thrd_details->extra_info_str = alloc_printf("State: %s", state_desc);
+		if (!curr_thrd_details->extra_info_str) {
+			LOG_ERROR("Could not allocate space for thread state description");
+			return -1;
+		}
 
 		curr_thrd_details->exists = true;
 

-----------------------------------------------------------------------

Summary of changes:
 src/rtos/chibios.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)


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[openocd-gerrit <ope...@us...>]

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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit a510d51a78f14fbb8416037a587ce1bfc6016d24
Author: Marc Schink <de...@za...>
Date:   Wed Jun 26 15:50:45 2024 +0200

    bootstrap: Do not set up Git submodules by default
    
    Building OpenOCD with jimtcl and libjaylink Git submodules is deprecated
    and will be removed in the upcoming releases. The remaining 'git2cl'
    submodule is only required during the OpenOCD release process.
    
    Only set up Git submodules when the 'with-submodules' argument is used,
    for example during the OpenOCD release process or for the transition
    period until all submodules are replaced by external dependencies.
    
    We keep the existing 'nosubmodule' argument in order to not break
    automatic testing with Jenkins.
    
    Change-Id: Ia4fd765e3a2d6b2c40b084a1ffdf919d5f4f35bb
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8381
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: R. Diez <rdi...@rd...>

diff --git a/bootstrap b/bootstrap
index 9dfdc41ac..0ee26d4ed 100755
--- a/bootstrap
+++ b/bootstrap
@@ -15,19 +15,21 @@ else
     exit 1
 fi
 
-SKIP_SUBMODULE=0
+WITH_SUBMODULES=0
 
 case "$#" in
     0) ;;
-    1) if [ "$1" = "nosubmodule" ]; then
-           SKIP_SUBMODULE=1
-       else
+    1) if [ "$1" = "with-submodules" ]; then
+           WITH_SUBMODULES=1
+       elif [ "$1" = "nosubmodule" ]; then
+           WITH_SUBMODULES=0
+       elif [ -n "$1" ]; then
            echo "$0: Illegal argument $1" >&2
-           echo "USAGE: $0 [nosubmodule]" >&2
+           echo "USAGE: $0 [with-submodules]" >&2
            exit 1
        fi;;
    *)  echo "$0: Wrong number of command-line arguments." >&2
-       echo "USAGE: $0 [nosubmodule]" >&2
+       echo "USAGE: $0 [with-submodules]" >&2
        exit 1;;
 esac
 
@@ -42,12 +44,12 @@ autoheader --warnings=all
 automake --warnings=all --gnu --add-missing --copy
 )
 
-if [ "$SKIP_SUBMODULE" -ne 0 ]; then
-    echo "Skipping submodule setup"
-else
+if [ "$WITH_SUBMODULES" -ne 0 ]; then
     echo "Setting up submodules"
     git submodule sync
     git submodule update --init
+else
+    echo "Skipping submodule setup"
 fi
 
 if [ -x src/jtag/drivers/libjaylink/autogen.sh ]; then

-----------------------------------------------------------------------

Summary of changes:
 bootstrap | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)


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- Log -----------------------------------------------------------------
commit 77c904fd13c08077cafd0845107506db408b5bb1
Author: Marc Schink <de...@za...>
Date:   Tue Jul 2 17:12:46 2024 +0200

    Deprecate jimtcl Git submodule
    
    jimtcl was integrated as Git submodule for convenience and probably also
    because packages were not widely available at the time. Today, jimtcl is
    available in many popular package repositories [1] and the integration
    as Git submodule adds unnecessary complexity to the OpenOCD build
    process. For details, see the discussion on the mailing list in [2].
    
    Disable the jimtcl Git submodule by default and announce it as
    deprecated feature that will be removed in the next release. This gives
    package maintainers time to adapt to the change and, if necessary,
    build a package for jimtcl.
    
    [1] https://repology.org/project/jimtcl/versions
    [2] https://sourceforge.net/p/openocd/mailman/message/58786630/
    
    Change-Id: I07930ac07f7d7a6317c08b21dc118f4f128b331c
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8380
    Tested-by: jenkins
    Reviewed-by: Paul Fertser <fer...@gm...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/configure.ac b/configure.ac
index a558650b3..4b10aabd5 100644
--- a/configure.ac
+++ b/configure.ac
@@ -399,8 +399,8 @@ AS_CASE([$host_os],
 ])
 
 AC_ARG_ENABLE([internal-jimtcl],
-  AS_HELP_STRING([--disable-internal-jimtcl], [Disable building internal jimtcl]),
-  [use_internal_jimtcl=$enableval], [use_internal_jimtcl=yes])
+  AS_HELP_STRING([--enable-internal-jimtcl], [Enable building internal jimtcl (deprecated)]),
+  [use_internal_jimtcl=$enableval], [use_internal_jimtcl=no])
 
 AC_ARG_ENABLE([jimtcl-maintainer],
   AS_HELP_STRING([--enable-jimtcl-maintainer], [Enable maintainer mode when building internal jimtcl]),
@@ -878,6 +878,10 @@ AS_IF([test "x$enable_jlink" != "xno"], [
   ]])
 )
 
+AS_IF([test "x$use_internal_jimtcl" = "xyes"], [
+  AC_MSG_WARN([Using the internal jimtcl is deprecated and will not be possible in the future.])
+])
+
 echo
 echo
 echo OpenOCD configuration summary

-----------------------------------------------------------------------

Summary of changes:
 configure.ac | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)


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- Log -----------------------------------------------------------------
commit fceccde0b394cff9127dca13708ef689094c9975
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Feb 19 20:11:07 2024 -0600

    helper/log: Fix build using _DEBUG_FREE_SPACE_
    
    The glibc API 'mallinfo' is deprecated and the new 'mallinfo2'
    should be used from glibc 2.33 (2021-02-01).
    
    Throw an error when '--enable-malloc-logging' is used on systems
    that compile without glibc.
    Detect the glibc version and, for backward compatibility, define
    'mallinfo2' as the old 'mallinfo'. Define a macro for the format
    of 'fordblks'.
    
    Change-Id: I68bff7b1b58f0ec2669db0b911f19c1c5a26ed30
    Reported-by: Steven J. Hill <ste...@ko...>
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8589
    Tested-by: jenkins

diff --git a/src/helper/log.c b/src/helper/log.c
index e02556b6d..8f7ab0039 100644
--- a/src/helper/log.c
+++ b/src/helper/log.c
@@ -30,6 +30,18 @@
 #else
 #error "malloc.h is required to use --enable-malloc-logging"
 #endif
+
+#ifdef __GLIBC__
+#if __GLIBC_PREREQ(2, 33)
+#define FORDBLKS_FORMAT " %zu"
+#else
+/* glibc older than 2.33 (2021-02-01) use mallinfo(). Overwrite it */
+#define mallinfo2 mallinfo
+#define FORDBLKS_FORMAT " %d"
+#endif
+#else
+#error "GNU glibc is required to use --enable-malloc-logging"
+#endif
 #endif
 
 int debug_level = LOG_LVL_INFO;
@@ -105,12 +117,11 @@ static void log_puts(enum log_levels level,
 		/* print with count and time information */
 		int64_t t = timeval_ms() - start;
 #ifdef _DEBUG_FREE_SPACE_
-		struct mallinfo info;
-		info = mallinfo();
+		struct mallinfo2 info = mallinfo2();
 #endif
 		fprintf(log_output, "%s%d %" PRId64 " %s:%d %s()"
 #ifdef _DEBUG_FREE_SPACE_
-			" %d"
+			FORDBLKS_FORMAT
 #endif
 			": %s", log_strings[level + 1], count, t, file, line, function,
 #ifdef _DEBUG_FREE_SPACE_

-----------------------------------------------------------------------

Summary of changes:
 src/helper/log.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)


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- Log -----------------------------------------------------------------
commit 8038e2f7548792a090bdd255ec6bfbf4128fead7
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Nov 17 22:46:15 2024 +0100

    configure: allow --enable-malloc-logging only with glibc
    
    The feature for 'malloc-logging' uses functionalities that are
    available only in GNU libc.
    
    Detect in 'configure' if OpenOCD is being compiled with glibc.
    Set the macro '_DEBUG_FREE_SPACE_' only in case of glibc.
    
    Change-Id: I43e9b87c7ad47171cfe3e7c1e5f96f11e19f98d0
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8592
    Tested-by: jenkins

diff --git a/configure.ac b/configure.ac
index fc1e20ef8..a558650b3 100644
--- a/configure.ac
+++ b/configure.ac
@@ -57,6 +57,11 @@ AC_CHECK_TYPE([Elf64_Ehdr],
 	AC_DEFINE([HAVE_ELF64], [1], [Define to 1 if the system has the type 'Elf64_Ehdr'.]),
 	[], [[#include <elf.h>]])
 
+AC_MSG_CHECKING([for glibc])
+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[#include <features.h>]], [[int v = __GLIBC__;return 0;]])],
+	[have_glibc=yes], [have_glibc=no])
+AC_MSG_RESULT($have_glibc)
+
 AC_CHECK_HEADERS([fcntl.h])
 AC_CHECK_HEADERS([malloc.h])
 AC_CHECK_HEADERS([netdb.h])
@@ -262,7 +267,7 @@ AC_ARG_ENABLE([malloc_logging],
 
 AC_MSG_CHECKING([whether to enable malloc free space logging]);
 AC_MSG_RESULT([$debug_malloc])
-AS_IF([test "x$debug_malloc" = "xyes"], [
+AS_IF([test "x$debug_malloc" = "xyes" -a "x$have_glibc" = "xyes"], [
   AC_DEFINE([_DEBUG_FREE_SPACE_],[1], [Include malloc free space in logging])
 ])
 

-----------------------------------------------------------------------

Summary of changes:
 configure.ac | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)


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commit ac18b8cd6a3f21b97f942efdbb0ec2f362bb132b
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Nov 17 21:35:45 2024 +0100

    configure: make more robust the check for elf 64
    
    The check if 'elf.h' defines the type 'Elf64_Ehdr' is currently
    done through 'grep' on the file. While there is no false positive,
    so far, such test could incorrectly find the text inside a comment
    or in a block guarded by #if/#endif.
    
    Use the autoconf macro AC_CHECK_TYPE() to detect if the type is
    properly declared.
    
    Change-Id: Ibb74db3d90ac6d1589b9dc1e5a7ae59e47945e78
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8591
    Tested-by: jenkins

diff --git a/configure.ac b/configure.ac
index 49054288f..fc1e20ef8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -52,9 +52,11 @@ AC_SEARCH_LIBS([openpty], [util])
 
 AC_CHECK_HEADERS([sys/socket.h])
 AC_CHECK_HEADERS([elf.h])
-AC_EGREP_HEADER(Elf64_Ehdr, [elf.h], [
-  AC_DEFINE([HAVE_ELF64], [1], [Define to 1 if the system has the type `Elf64_Ehdr'.])
-])
+
+AC_CHECK_TYPE([Elf64_Ehdr],
+	AC_DEFINE([HAVE_ELF64], [1], [Define to 1 if the system has the type 'Elf64_Ehdr'.]),
+	[], [[#include <elf.h>]])
+
 AC_CHECK_HEADERS([fcntl.h])
 AC_CHECK_HEADERS([malloc.h])
 AC_CHECK_HEADERS([netdb.h])

commit 345473f3ceaf6a1241f62354e31eeababfc56588
Author: Evgeniy Naydanov <evg...@sy...>
Date:   Tue Dec 17 18:13:00 2024 +0300

    helper/options: handle errors in `-l`
    
    Before the patch an error in opening the log file (e.g. can't write a
    file) was ignored when specified via `-l`.
    E.g.:
    ```
    > touch log
    > chmod -w log
    > openocd -l log -c shutdown
    ...
    failed to open output log "log"
    shutdown command invoked
    > echo $?
    0
    ```
    
    After the patch:
    ```
    ...
    > openocd -l log -c shutdown
    ...
    failed to open output log "log"
    > echo $?
    1
    ```
    
    Change-Id: Ibab45f580dc46a499bf967c4afad071f9c2972a2
    Signed-off-by: Evgeniy Naydanov <evg...@sy...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8666
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/helper/options.c b/src/helper/options.c
index 9e332cc8c..50977a610 100644
--- a/src/helper/options.c
+++ b/src/helper/options.c
@@ -303,8 +303,12 @@ int parse_cmdline_args(struct command_context *cmd_ctx, int argc, char *argv[])
 				break;
 			}
 			case 'l':		/* --log_output | -l */
-				command_run_linef(cmd_ctx, "log_output %s", optarg);
+			{
+				int retval = command_run_linef(cmd_ctx, "log_output %s", optarg);
+				if (retval != ERROR_OK)
+					return retval;
 				break;
+			}
 			case 'c':		/* --command | -c */
 				add_config_command(optarg);
 				break;

-----------------------------------------------------------------------

Summary of changes:
 configure.ac         | 8 +++++---
 src/helper/options.c | 6 +++++-
 2 files changed, 10 insertions(+), 4 deletions(-)


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- Log -----------------------------------------------------------------
commit 778d2dc4bb982ffa00f5fbd343346555fcbf9113
Author: Evgeniy Naydanov <evg...@sy...>
Date:   Fri Jan 17 18:03:40 2025 +0300

    helper/options: drop redundant argument checks
    
    In case the option is passed with a single `:` in `optstring` argument,
    the call to `getopt_long()` should return `?`.
    
    Therefore the check on `optarg` is redundand in case of `l` and `c`.
    
    Change-Id: I1ac176fdae449a34db0a0496b69a9ea65ccd6aec
    Signed-off-by: Evgeniy Naydanov <evg...@sy...>
    Reported-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8718
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/helper/options.c b/src/helper/options.c
index 61a101469..9e332cc8c 100644
--- a/src/helper/options.c
+++ b/src/helper/options.c
@@ -303,12 +303,10 @@ int parse_cmdline_args(struct command_context *cmd_ctx, int argc, char *argv[])
 				break;
 			}
 			case 'l':		/* --log_output | -l */
-				if (optarg)
-					command_run_linef(cmd_ctx, "log_output %s", optarg);
+				command_run_linef(cmd_ctx, "log_output %s", optarg);
 				break;
 			case 'c':		/* --command | -c */
-				if (optarg)
-				    add_config_command(optarg);
+				add_config_command(optarg);
 				break;
 			default:  /* '?' */
 				/* getopt will emit an error message, all we have to do is bail. */

-----------------------------------------------------------------------

Summary of changes:
 src/helper/options.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)


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commit 0b97973bfbb980f987ec8e0e8d8ad32c85e9e5b0
Author: Marek Vrbka <mar...@co...>
Date:   Mon Jan 13 10:28:15 2025 +0100

    vdebug: Fix socket comparison warning on Windows
    
    On GCC version 13.2,
    the previous code emitted the following warning on Windows:
    
    openocd/src/jtag/drivers/vdebug.c:254:19: warning: comparison of integer expressions of different signedness: 'int' and 'long long unsigned int' [-Wsign-compare]
      254 |         if (hsock == INVALID_SOCKET)
    
    This patch fixes it and brings it in line with other socket handling code.
    
    Change-Id: I7e05f83c6905cfaf66b68e8988c783e80cee4a48
    Signed-off-by: Marek Vrbka <mar...@co...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8717
    Tested-by: jenkins
    Reviewed-by: Jan Matyas <jan...@co...>
    Reviewed-by: Jacek Wuwer <jac...@gm...>
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: R. Diez <rdi...@rd...>

diff --git a/src/jtag/drivers/vdebug.c b/src/jtag/drivers/vdebug.c
index 691e576e5..20819f70b 100644
--- a/src/jtag/drivers/vdebug.c
+++ b/src/jtag/drivers/vdebug.c
@@ -252,7 +252,7 @@ static int vdebug_socket_open(char *server_addr, uint32_t port)
 
 #ifdef _WIN32
 	hsock = socket(AF_INET, SOCK_STREAM, IPPROTO_IP);
-	if (hsock == INVALID_SOCKET)
+	if (hsock < 0)
 		rc = vdebug_socket_error();
 #elif defined __CYGWIN__
 	/* SO_RCVLOWAT unsupported on CYGWIN */

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/vdebug.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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commit 77f9da76264d4970faf22a40a31fc66fa7543b57
Author: Tomas Vanek <va...@fb...>
Date:   Fri Jan 17 18:02:50 2025 +0100

    flash/nor/kinetis: fix assertion during flash write
    
    If the device has at lest one FlexNVM bank and it is set as EE backup
    only, the bank has no protection blocks.
    
    kinetis_fill_fcf() collects protection data from all banks before
    flash write of the sector containing FCF block. In case it encountered
    a FlexNVM bank with no protection blocks assert failed.
    
    Failed flash write of previously erased FCF block could cause
    engaging debugging lock (if the device was run or reset).
    
    Skip banks with zero protection blocks.
    Replace assert() by LOG_ERROR() as we have to finish FCF write.
    
    Change-Id: Ibe7e7ec6d0db4453b8a53c8256987621b809c99d
    Signed-off-by: Tomas Vanek <va...@fb...>
    Suggested-by: Jasper v. Blanckenburg <ja...@us...>
    Fixes: https://sourceforge.net/p/openocd/tickets/448/
    Reviewed-on: https://review.openocd.org/c/openocd/+/8719
    Tested-by: jenkins
    Reviewed-by: Jasper v. Blanckenburg <ja...@me...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c
index 2f88b9c1f..85c306bd4 100644
--- a/src/flash/nor/kinetis.c
+++ b/src/flash/nor/kinetis.c
@@ -1489,7 +1489,22 @@ static int kinetis_fill_fcf(struct flash_bank *bank, uint8_t *fcf)
 
 		kinetis_auto_probe(bank_iter);
 
-		assert(bank_iter->prot_blocks);
+		if (bank_iter->num_prot_blocks == 0) {
+			if (k_bank->flash_class == FC_PFLASH) {
+				LOG_ERROR("BUG: PFLASH bank %u has no protection blocks",
+						  bank_idx);
+			} else {
+				LOG_DEBUG("skipping FLEX_NVM bank %u with no prot blocks (EE bkp only)",
+						  bank_idx);
+			}
+			continue;
+		}
+
+		if (!bank_iter->prot_blocks) {
+			LOG_ERROR("BUG: bank %u has NULL protection blocks array",
+					  bank_idx);
+			continue;
+		}
 
 		if (k_bank->flash_class == FC_PFLASH) {
 			for (unsigned int i = 0; i < bank_iter->num_prot_blocks; i++) {

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/kinetis.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)


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commit 3099547069896ccff054d64bac6041fe1e20add9
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Sep 16 13:45:19 2024 +0200

    OpenOCD: fix code indentation
    
    Fix checkpatch errors
    
            ERROR:SUSPECT_CODE_INDENT: suspect code indent for
            conditional statements
    
    Change-Id: I94d4fa5720c25dd2fb0334a824cd9026babcce4e
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8497
    Tested-by: jenkins

diff --git a/src/flash/nor/fespi.c b/src/flash/nor/fespi.c
index 6c4e8a928..395722cb5 100644
--- a/src/flash/nor/fespi.c
+++ b/src/flash/nor/fespi.c
@@ -751,9 +751,9 @@ static int fespi_probe(struct flash_bank *bank)
 				target_device->name, bank->base);
 
 	} else {
-	  LOG_DEBUG("Assuming FESPI as specified at address " TARGET_ADDR_FMT
-			  " with ctrl at " TARGET_ADDR_FMT, fespi_info->ctrl_base,
-			  bank->base);
+		LOG_DEBUG("Assuming FESPI as specified at address " TARGET_ADDR_FMT
+				  " with ctrl at " TARGET_ADDR_FMT, fespi_info->ctrl_base,
+				  bank->base);
 	}
 
 	/* read and decode flash ID; returns in SW mode */
diff --git a/src/flash/nor/kinetis_ke.c b/src/flash/nor/kinetis_ke.c
index e4dffa6d5..8207504b5 100644
--- a/src/flash/nor/kinetis_ke.c
+++ b/src/flash/nor/kinetis_ke.c
@@ -1005,7 +1005,7 @@ static int kinetis_ke_write(struct flash_bank *bank, const uint8_t *buffer,
 
 	result = kinetis_ke_stop_watchdog(bank->target);
 	if (result != ERROR_OK)
-			return result;
+		return result;
 
 	result = kinetis_ke_prepare_flash(bank);
 	if (result != ERROR_OK)
diff --git a/src/flash/nor/niietcm4.c b/src/flash/nor/niietcm4.c
index 0c36e2c96..aaf072655 100644
--- a/src/flash/nor/niietcm4.c
+++ b/src/flash/nor/niietcm4.c
@@ -311,7 +311,7 @@ static int niietcm4_uflash_page_erase(struct flash_bank *bank, int page_num, int
 	/* status check */
 	retval = niietcm4_uopstatus_check(bank);
 	if (retval != ERROR_OK)
-			return retval;
+		return retval;
 
 	return retval;
 }
@@ -394,7 +394,7 @@ COMMAND_HANDLER(niietcm4_handle_uflash_read_byte_command)
 	uint32_t uflash_data;
 
 	if (strcmp("info", CMD_ARGV[0]) == 0)
-			uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ_IFB;
+		uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ_IFB;
 	else if (strcmp("main", CMD_ARGV[0]) == 0)
 		uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ;
 	else
@@ -539,7 +539,7 @@ COMMAND_HANDLER(niietcm4_handle_uflash_erase_command)
 	int mem_type;
 
 	if (strcmp("info", CMD_ARGV[0]) == 0)
-			mem_type = 1;
+		mem_type = 1;
 	else if (strcmp("main", CMD_ARGV[0]) == 0)
 		mem_type = 0;
 	else
diff --git a/src/flash/nor/psoc4.c b/src/flash/nor/psoc4.c
index 1064fa93d..72cf0ee05 100644
--- a/src/flash/nor/psoc4.c
+++ b/src/flash/nor/psoc4.c
@@ -384,15 +384,15 @@ static int psoc4_get_silicon_id(struct flash_bank *bank, uint32_t *silicon_id, u
 	 * bit 7..0   family ID (lowest 8 bits)
 	 */
 	if (silicon_id)
-			*silicon_id = ((part0 & 0x0000ffff) << 16)
-				    | ((part0 & 0x00ff0000) >> 8)
-				    | (part1 & 0x000000ff);
+		*silicon_id = ((part0 & 0x0000ffff) << 16)
+					  | ((part0 & 0x00ff0000) >> 8)
+					  | (part1 & 0x000000ff);
 
 	if (family_id)
-			*family_id = part1 & 0x0fff;
+		*family_id = part1 & 0x0fff;
 
 	if (protection)
-			*protection = (part1 >> 12) & 0x0f;
+		*protection = (part1 >> 12) & 0x0f;
 
 	return ERROR_OK;
 }
diff --git a/src/helper/log.c b/src/helper/log.c
index 9ad00ce62..e02556b6d 100644
--- a/src/helper/log.c
+++ b/src/helper/log.c
@@ -272,10 +272,10 @@ void log_init(void)
 	if (debug_env) {
 		int value;
 		int retval = parse_int(debug_env, &value);
-		if (retval == ERROR_OK &&
-				debug_level >= LOG_LVL_SILENT &&
-				debug_level <= LOG_LVL_DEBUG_IO)
-				debug_level = value;
+		if (retval == ERROR_OK
+				&& debug_level >= LOG_LVL_SILENT
+				&& debug_level <= LOG_LVL_DEBUG_IO)
+			debug_level = value;
 	}
 
 	if (!log_output)
diff --git a/src/rtos/hwthread.c b/src/rtos/hwthread.c
index 1890a3d87..c9f1a1792 100644
--- a/src/rtos/hwthread.c
+++ b/src/rtos/hwthread.c
@@ -154,9 +154,8 @@ static int hwthread_update_threads(struct rtos *rtos)
 				if (curr->debug_reason == DBG_REASON_SINGLESTEP) {
 					current_reason = curr->debug_reason;
 					current_thread = tid;
-				} else
-				/* multiple breakpoints, prefer gdbs' threadid */
-				if (curr->debug_reason == DBG_REASON_BREAKPOINT) {
+				} else if (curr->debug_reason == DBG_REASON_BREAKPOINT) {
+					/* multiple breakpoints, prefer gdbs' threadid */
 					if (tid == rtos->current_threadid)
 						current_thread = tid;
 				}
@@ -176,8 +175,7 @@ static int hwthread_update_threads(struct rtos *rtos)
 						curr->debug_reason == DBG_REASON_BREAKPOINT) {
 					current_reason = curr->debug_reason;
 					current_thread = tid;
-				} else
-				if (curr->debug_reason == DBG_REASON_DBGRQ) {
+				} else if (curr->debug_reason == DBG_REASON_DBGRQ) {
 					if (tid == rtos->current_threadid)
 						current_thread = tid;
 				}
diff --git a/src/rtos/linux.c b/src/rtos/linux.c
index 7517ec7a9..5467988f3 100644
--- a/src/rtos/linux.c
+++ b/src/rtos/linux.c
@@ -624,7 +624,7 @@ static struct threads *liste_add_task(struct threads *task_list, struct threads
 {
 	t->next = NULL;
 
-	if (!*last)
+	if (!*last) {
 		if (!task_list) {
 			task_list = t;
 			return task_list;
@@ -637,7 +637,8 @@ static struct threads *liste_add_task(struct threads *task_list, struct threads
 			temp->next = t;
 			*last = t;
 			return task_list;
-		} else {
+		}
+	} else {
 		(*last)->next = t;
 		*last = t;
 		return task_list;
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 9f122070a..3cc813005 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -2908,9 +2908,9 @@ static int aarch64_jim_configure(struct target *target, struct jim_getopt_info *
 
 	pc = (struct aarch64_private_config *)target->private_config;
 	if (!pc) {
-			pc = calloc(1, sizeof(struct aarch64_private_config));
-			pc->adiv5_config.ap_num = DP_APSEL_INVALID;
-			target->private_config = pc;
+		pc = calloc(1, sizeof(struct aarch64_private_config));
+		pc->adiv5_config.ap_num = DP_APSEL_INVALID;
+		target->private_config = pc;
 	}
 
 	/*
diff --git a/src/target/arc.c b/src/target/arc.c
index 5c08c5664..0c111d553 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -388,7 +388,7 @@ static int arc_build_reg_cache(struct target *target)
 	}
 
 	list_for_each_entry(reg_desc, &arc->aux_reg_descriptions, list) {
-		 CHECK_RETVAL(arc_init_reg(target, &reg_list[i],  reg_desc, i));
+		CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, i));
 
 		LOG_TARGET_DEBUG(target, "reg n=%3li name=%3s group=%s feature=%s", i,
 			reg_list[i].name, reg_list[i].group,
@@ -464,7 +464,7 @@ static int arc_build_bcr_reg_cache(struct target *target)
 	}
 
 	list_for_each_entry(reg_desc, &arc->bcr_reg_descriptions, list) {
-		 CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, gdb_regnum));
+		CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, gdb_regnum));
 		/* BCRs always semantically, they are just read-as-zero, if there is
 		 * not real register. */
 		reg_list[i].exist = true;
@@ -719,14 +719,14 @@ static int arc_configure(struct target *target)
 	LOG_TARGET_DEBUG(target, "Configuring ARC ICCM and DCCM");
 
 	/* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */
-	if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true) &&
-	    arc_reg_get_by_name(target->reg_cache, "aux_dccm", true))
-				CHECK_RETVAL(arc_configure_dccm(target));
+	if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true)
+		    && arc_reg_get_by_name(target->reg_cache, "aux_dccm", true))
+		CHECK_RETVAL(arc_configure_dccm(target));
 
 	/* Configuring ICCM if ICCM_BUILD and AUX_ICCM are known registers. */
-	if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true) &&
-	    arc_reg_get_by_name(target->reg_cache, "aux_iccm", true))
-				CHECK_RETVAL(arc_configure_iccm(target));
+	if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true)
+			&& arc_reg_get_by_name(target->reg_cache, "aux_iccm", true))
+		CHECK_RETVAL(arc_configure_iccm(target));
 
 	return ERROR_OK;
 }
@@ -1067,9 +1067,7 @@ static int arc_poll(struct target *target)
 			LOG_TARGET_DEBUG(target, "Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
 						"target is still running");
 		}
-
 	} else if (target->state == TARGET_DEBUG_RUNNING) {
-
 		target->state = TARGET_HALTED;
 		LOG_TARGET_DEBUG(target, "ARC core is in debug running mode");
 
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index ceec3619b..a258c7fd4 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1301,11 +1301,11 @@ int arm_get_gdb_reg_list(struct target *target,
 		*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
 
 		for (i = 0; i < 16; i++)
-				(*reg_list)[i] = arm_reg_current(arm, i);
+			(*reg_list)[i] = arm_reg_current(arm, i);
 
 		/* For GDB compatibility, take FPA registers size into account and zero-fill it*/
 		for (i = 16; i < 24; i++)
-				(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
+			(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
 		(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
 
 		(*reg_list)[25] = arm->cpsr;
@@ -1330,25 +1330,25 @@ int arm_get_gdb_reg_list(struct target *target,
 		*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
 
 		for (i = 0; i < 16; i++)
-				(*reg_list)[i] = arm_reg_current(arm, i);
+			(*reg_list)[i] = arm_reg_current(arm, i);
 
 		for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
-				int reg_index = arm->core_cache->reg_list[i].number;
+			int reg_index = arm->core_cache->reg_list[i].number;
 
-				if (arm_core_regs[i].mode == ARM_MODE_MON
+			if (arm_core_regs[i].mode == ARM_MODE_MON
 					&& arm->core_type != ARM_CORE_TYPE_SEC_EXT
 					&& arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
-					continue;
-				if (arm_core_regs[i].mode == ARM_MODE_HYP
+				continue;
+			if (arm_core_regs[i].mode == ARM_MODE_HYP
 					&& arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
-					continue;
-				(*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
+				continue;
+			(*reg_list)[reg_index] = &arm->core_cache->reg_list[i];
 		}
 
 		/* When we supply the target description, there is no need for fake FPA */
 		for (i = 16; i < 24; i++) {
-				(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
-				(*reg_list)[i]->size = 0;
+			(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
+			(*reg_list)[i]->size = 0;
 		}
 		(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
 		(*reg_list)[24]->size = 0;
diff --git a/src/target/armv7a_mmu.c b/src/target/armv7a_mmu.c
index c4d294eae..43b5dae8e 100644
--- a/src/target/armv7a_mmu.c
+++ b/src/target/armv7a_mmu.c
@@ -260,8 +260,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
 		/* skip empty entries in the first level table */
 		if ((first_lvl_descriptor & 3) == 0) {
 			pt_idx++;
-		} else
-		if ((first_lvl_descriptor & 0x40002) == 2) {
+		} else if ((first_lvl_descriptor & 0x40002) == 2) {
 			/* section descriptor */
 			uint32_t va_range = 1024*1024-1; /* 1MB range */
 			uint32_t va_start = pt_idx << 20;
@@ -273,8 +272,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
 			LOG_USER("SECT: VA[%8.8"PRIx32" -- %8.8"PRIx32"]: PA[%8.8"PRIx32" -- %8.8"PRIx32"] %s",
 				va_start, va_end, pa_start, pa_end, l1_desc_bits_to_string(first_lvl_descriptor, afe));
 			pt_idx++;
-		} else
-		if ((first_lvl_descriptor & 0x40002) == 0x40002) {
+		} else if ((first_lvl_descriptor & 0x40002) == 0x40002) {
 			/* supersection descriptor */
 			uint32_t va_range = 16*1024*1024-1; /* 16MB range */
 			uint32_t va_start = pt_idx << 20;
@@ -310,8 +308,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
 				if ((second_lvl_descriptor & 3) == 0) {
 					/* skip entry */
 					pt2_idx++;
-				} else
-				if ((second_lvl_descriptor & 3) == 1) {
+				} else if ((second_lvl_descriptor & 3) == 1) {
 					/* large page */
 					uint32_t va_range = 64*1024-1; /* 64KB range */
 					uint32_t va_start = (pt_idx << 20) + (pt2_idx << 12);
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 88534d962..50a9f4688 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -1966,7 +1966,7 @@ int armv8_get_gdb_reg_list(struct target *target,
 			*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
 
 			for (i = 0; i < *reg_list_size; i++)
-					(*reg_list)[i] = armv8_reg_current(arm, i);
+				(*reg_list)[i] = armv8_reg_current(arm, i);
 			return ERROR_OK;
 
 		case REG_CLASS_ALL:
@@ -1974,7 +1974,7 @@ int armv8_get_gdb_reg_list(struct target *target,
 			*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
 
 			for (i = 0; i < *reg_list_size; i++)
-					(*reg_list)[i] = armv8_reg_current(arm, i);
+				(*reg_list)[i] = armv8_reg_current(arm, i);
 
 			return ERROR_OK;
 
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 086aafe19..bfe698051 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1324,21 +1324,21 @@ static int cortex_a_set_breakpoint(struct target *target,
 			brp_list[brp_i].value);
 	} else if (breakpoint->type == BKPT_SOFT) {
 		uint8_t code[4];
-		/* length == 2: Thumb breakpoint */
-		if (breakpoint->length == 2)
+		if (breakpoint->length == 2) {
+			/* length == 2: Thumb breakpoint */
 			buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
-		else
-		/* length == 3: Thumb-2 breakpoint, actual encoding is
-		 * a regular Thumb BKPT instruction but we replace a
-		 * 32bit Thumb-2 instruction, so fix-up the breakpoint
-		 * length
-		 */
-		if (breakpoint->length == 3) {
+		} else if (breakpoint->length == 3) {
+			/* length == 3: Thumb-2 breakpoint, actual encoding is
+			 * a regular Thumb BKPT instruction but we replace a
+			 * 32bit Thumb-2 instruction, so fix-up the breakpoint
+			 * length
+			 */
 			buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
 			breakpoint->length = 4;
-		} else
+		} else {
 			/* length == 4, normal ARM breakpoint */
 			buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
+		}
 
 		retval = target_read_memory(target,
 				breakpoint->address & 0xFFFFFFFE,
@@ -1348,8 +1348,7 @@ static int cortex_a_set_breakpoint(struct target *target,
 			return retval;
 
 		/* make sure data cache is cleaned & invalidated down to PoC */
-		armv7a_cache_flush_virt(target, breakpoint->address,
-						breakpoint->length);
+		armv7a_cache_flush_virt(target, breakpoint->address, breakpoint->length);
 
 		retval = target_write_memory(target,
 				breakpoint->address & 0xFFFFFFFE,
@@ -1358,10 +1357,8 @@ static int cortex_a_set_breakpoint(struct target *target,
 			return retval;
 
 		/* update i-cache at breakpoint location */
-		armv7a_l1_d_cache_inval_virt(target, breakpoint->address,
-					breakpoint->length);
-		armv7a_l1_i_cache_inval_virt(target, breakpoint->address,
-						 breakpoint->length);
+		armv7a_l1_d_cache_inval_virt(target, breakpoint->address, breakpoint->length);
+		armv7a_l1_i_cache_inval_virt(target, breakpoint->address, breakpoint->length);
 
 		breakpoint->is_set = true;
 	}
diff --git a/src/target/mips32.c b/src/target/mips32.c
index dd40558a1..fcb7042cb 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -2357,7 +2357,7 @@ COMMAND_HANDLER(mips32_handle_scan_delay_command)
 	if (CMD_ARGC == 1)
 		COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
 	else if (CMD_ARGC > 1)
-			return ERROR_COMMAND_SYNTAX_ERROR;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 
 	command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
 	if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index ad9808961..1543de355 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -1397,7 +1397,7 @@ COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
 	if (CMD_ARGC == 1)
 		COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
 	else if (CMD_ARGC > 1)
-			return ERROR_COMMAND_SYNTAX_ERROR;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 
 	command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
 	if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
diff --git a/src/target/stm8.c b/src/target/stm8.c
index 2b3466dac..fb5c81f06 100644
--- a/src/target/stm8.c
+++ b/src/target/stm8.c
@@ -689,15 +689,13 @@ static int stm8_write_flash(struct target *target, enum mem_type type,
 			if (stm8->flash_ncr2)
 				stm8_write_u8(target, stm8->flash_ncr2, ~(PRG + opt));
 			blocksize = blocksize_param;
-		} else
-		if ((bytecnt >= 4) && ((address & 0x3) == 0)) {
+		} else if ((bytecnt >= 4) && ((address & 0x3) == 0)) {
 			if (stm8->flash_cr2)
 				stm8_write_u8(target, stm8->flash_cr2, WPRG + opt);
 			if (stm8->flash_ncr2)
 				stm8_write_u8(target, stm8->flash_ncr2, ~(WPRG + opt));
 			blocksize = 4;
-		} else
-		if (blocksize != 1) {
+		} else if (blocksize != 1) {
 			if (stm8->flash_cr2)
 				stm8_write_u8(target, stm8->flash_cr2, opt);
 			if (stm8->flash_ncr2)
@@ -1552,8 +1550,8 @@ static int stm8_set_watchpoint(struct target *target,
 	}
 
 	if (watchpoint->length != 1) {
-			LOG_ERROR("Only watchpoints of length 1 are supported");
-			return ERROR_TARGET_UNALIGNED_ACCESS;
+		LOG_ERROR("Only watchpoints of length 1 are supported");
+		return ERROR_TARGET_UNALIGNED_ACCESS;
 	}
 
 	enum hw_break_type enable = 0;
diff --git a/src/xsvf/xsvf.c b/src/xsvf/xsvf.c
index 74a4dcfde..88275043e 100644
--- a/src/xsvf/xsvf.c
+++ b/src/xsvf/xsvf.c
@@ -749,10 +749,10 @@ COMMAND_HANDLER(handle_xsvf_command)
 				int delay;
 
 				if (read(xsvf_fd, &wait_local, 1) < 0
-					|| read(xsvf_fd, &end, 1) < 0
-					|| read(xsvf_fd, delay_buf, 4) < 0) {
-						do_abort = 1;
-						break;
+						|| read(xsvf_fd, &end, 1) < 0
+						|| read(xsvf_fd, delay_buf, 4) < 0) {
+					do_abort = 1;
+					break;
 				}
 
 				wait_state = xsvf_to_tap(wait_local);

commit 8e89a8af63f242290c800d6f640b432d3af9ec89
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Dec 30 12:14:24 2024 +0100

    target: cortex_m: add support of ARMv8.1-M register 'vpr'
    
    The register 'vpr' is present when MVFR1.MVE is not zero.
    For the moment, reuse the existing flag 'fp_feature'. To be
    reviewed for the case of MVE supported without floating point.
    
    The documentation of GDB [1] reports that the register 'vpr'
    should be represented as 3 fields.
    
    Tested on Cortex-M55 based STM32N6570.
    
    Change-Id: I8737a24d01a13eeb09a0f2075b96be400f9f91c6
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Link: [1] https://sourceware.org/gdb/download/onlinedocs/gdb.html/ARM-Features.html#M_002dprofile-Vector-Extension-_0028MVE_0029
    Reviewed-on: https://review.openocd.org/c/openocd/+/8681
    Tested-by: jenkins

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index b4473c30a..440ca49d1 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -65,6 +65,28 @@ const int armv7m_msp_reg_map[ARMV7M_NUM_CORE_REGS] = {
 	ARMV7M_XPSR,
 };
 
+static struct reg_data_type_bitfield armv8m_vpr_bits[] = {
+	{  0, 15, REG_TYPE_UINT },
+	{ 16, 19, REG_TYPE_UINT },
+	{ 20, 23, REG_TYPE_UINT },
+};
+
+static struct reg_data_type_flags_field armv8m_vpr_fields[] = {
+	{ "P0",     armv8m_vpr_bits + 0, armv8m_vpr_fields + 1, },
+	{ "MASK01", armv8m_vpr_bits + 1, armv8m_vpr_fields + 2, },
+	{ "MASK23", armv8m_vpr_bits + 2, NULL },
+};
+
+static struct reg_data_type_flags armv8m_vpr_flags[] = {
+	{ 4, armv8m_vpr_fields },
+};
+
+static struct reg_data_type armv8m_flags_vpr[] = {
+	{ REG_TYPE_ARCH_DEFINED, "vpr_reg", REG_TYPE_CLASS_FLAGS,
+		{ .reg_type_flags = armv8m_vpr_flags },
+	},
+};
+
 /*
  * These registers are not memory-mapped.  The ARMv7-M profile includes
  * memory mapped registers too, such as for the NVIC (interrupt controller)
@@ -158,6 +180,8 @@ static const struct {
 	{ ARMV7M_D15, "d15", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
 
 	{ ARMV7M_FPSCR, "fpscr", 32, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp", NULL, },
+
+	{ ARMV8M_VPR, "vpr", 32, REG_TYPE_INT, "float", "org.gnu.gdb.arm.m-profile-mve", armv8m_flags_vpr, },
 };
 
 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
@@ -273,6 +297,9 @@ uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
 	case ARMV7M_FPSCR:
 		return ARMV7M_REGSEL_FPSCR;
 
+	case ARMV8M_VPR:
+		return ARMV8M_REGSEL_VPR;
+
 	case ARMV7M_D0 ... ARMV7M_D15:
 		return ARMV7M_REGSEL_S0 + 2 * (arm_reg_id - ARMV7M_D0);
 
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 2878dd1c7..86c45f7f2 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -62,6 +62,7 @@ enum {
 	ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL = 0x14,
 	ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S = 0x22,
 	ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS = 0x23,
+	ARMV8M_REGSEL_VPR = 0x24,
 	ARMV7M_REGSEL_FPSCR = 0x21,
 
 	/* 32bit Floating-point registers */
@@ -196,12 +197,15 @@ enum {
 	/* Floating-point status register */
 	ARMV7M_FPSCR,
 
+	/* Vector Predication Status and Control Register */
+	ARMV8M_VPR,
+
 	/* for convenience add registers' block delimiters */
 	ARMV7M_LAST_REG,
 	ARMV7M_CORE_FIRST_REG = ARMV7M_R0,
 	ARMV7M_CORE_LAST_REG = ARMV7M_XPSR,
 	ARMV7M_FPU_FIRST_REG = ARMV7M_D0,
-	ARMV7M_FPU_LAST_REG = ARMV7M_FPSCR,
+	ARMV7M_FPU_LAST_REG = ARMV8M_VPR,
 	ARMV8M_FIRST_REG = ARMV8M_MSP_NS,
 	ARMV8M_LAST_REG = ARMV8M_CONTROL_NS,
 };
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index fa95fcbc7..2cea203a2 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2708,6 +2708,10 @@ int cortex_m_examine(struct target *target)
 			for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++)
 				armv7m->arm.core_cache->reg_list[idx].exist = false;
 
+		/* TODO: MVE can be present without floating points. Revisit this test */
+		if (armv7m->fp_feature != FPV5_MVE_F && armv7m->fp_feature != FPV5_MVE_I)
+			armv7m->arm.core_cache->reg_list[ARMV8M_VPR].exist = false;
+
 		if (!cortex_m_has_tz(target))
 			for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++)
 				armv7m->arm.core_cache->reg_list[idx].exist = false;

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/fespi.c      |  6 +++---
 src/flash/nor/kinetis_ke.c |  2 +-
 src/flash/nor/niietcm4.c   |  6 +++---
 src/flash/nor/psoc4.c      | 10 +++++-----
 src/helper/log.c           |  8 ++++----
 src/rtos/hwthread.c        |  8 +++-----
 src/rtos/linux.c           |  5 +++--
 src/target/aarch64.c       |  6 +++---
 src/target/arc.c           | 18 ++++++++----------
 src/target/armv4_5.c       | 22 +++++++++++-----------
 src/target/armv7a_mmu.c    |  9 +++------
 src/target/armv7m.c        | 27 +++++++++++++++++++++++++++
 src/target/armv7m.h        |  6 +++++-
 src/target/armv8.c         |  4 ++--
 src/target/cortex_a.c      | 29 +++++++++++++----------------
 src/target/cortex_m.c      |  4 ++++
 src/target/mips32.c        |  2 +-
 src/target/mips_m4k.c      |  2 +-
 src/target/stm8.c          | 10 ++++------
 src/xsvf/xsvf.c            |  8 ++++----
 20 files changed, 108 insertions(+), 84 deletions(-)


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- Log -----------------------------------------------------------------
commit 41f7d18161592cf3e2e6f51f0ef36d345aeed2e0
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Dec 30 12:10:28 2024 +0100

    target: armv7m: add support of per register data_type
    
    Extend the struct armv7m_regs to include the optional pointer
    to a struct reg_data_type.
    
    Update armv7m_build_reg_cache() to check for the new optional
    field and to use it.
    
    Change-Id: I57c7f9abefd614308be8aa8419d687477b44679d
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8680
    Tested-by: jenkins

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 49a8a4bba..b4473c30a 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -80,30 +80,31 @@ static const struct {
 	enum reg_type type;
 	const char *group;
 	const char *feature;
+	struct reg_data_type *data_type;
 } armv7m_regs[] = {
-	{ ARMV7M_R0, "r0", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
-	{ ARMV7M_R1, "r1", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
-	{ ARMV7M_R2, "r2", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
-	{ ARMV7M_R3, "r3", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
-	{ ARMV7M_R4, "r4", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
-	{ ARMV7M_R5, "r5", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
-	{ ARMV7M_R6, "r6", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
-	{ ARMV7M_R7, "r7", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
-	{ ARMV7M_R8, "r8", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
-	{ ARMV7M_R9, "r9", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
-	{ ARMV7M_R10, "r10", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
-	{ ARMV7M_R11, "r11", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
-	{ ARMV7M_R12, "r12", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
-	{ ARMV7M_R13, "sp", 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.m-profile" },
-	{ ARMV7M_R14, "lr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
-	{ ARMV7M_PC, "pc", 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.m-profile" },
-	{ ARMV7M_XPSR, "xpsr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
-
-	{ ARMV7M_MSP, "msp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
-	{ ARMV7M_PSP, "psp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
+	{ ARMV7M_R0, "r0", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+	{ ARMV7M_R1, "r1", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+	{ ARMV7M_R2, "r2", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+	{ ARMV7M_R3, "r3", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+	{ ARMV7M_R4, "r4", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+	{ ARMV7M_R5, "r5", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+	{ ARMV7M_R6, "r6", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+	{ ARMV7M_R7, "r7", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+	{ ARMV7M_R8, "r8", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+	{ ARMV7M_R9, "r9", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+	{ ARMV7M_R10, "r10", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+	{ ARMV7M_R11, "r11", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+	{ ARMV7M_R12, "r12", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+	{ ARMV7M_R13, "sp", 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+	{ ARMV7M_R14, "lr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+	{ ARMV7M_PC, "pc", 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+	{ ARMV7M_XPSR, "xpsr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile", NULL, },
+
+	{ ARMV7M_MSP, "msp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system", NULL, },
+	{ ARMV7M_PSP, "psp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system", NULL, },
 
 	/* A working register for packing/unpacking special regs, hidden from gdb */
-	{ ARMV7M_PMSK_BPRI_FLTMSK_CTRL, "pmsk_bpri_fltmsk_ctrl", 32, REG_TYPE_INT, NULL, NULL },
+	{ ARMV7M_PMSK_BPRI_FLTMSK_CTRL, "pmsk_bpri_fltmsk_ctrl", 32, REG_TYPE_INT, NULL, NULL, NULL },
 
 	/* WARNING: If you use armv7m_write_core_reg() on one of 4 following
 	 * special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL
@@ -111,52 +112,52 @@ static const struct {
 	 * To trigger write to CPU HW register, add
 	 *		armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,);
 	 */
-	{ ARMV7M_PRIMASK, "primask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-	{ ARMV7M_BASEPRI, "basepri", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-	{ ARMV7M_FAULTMASK, "faultmask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-	{ ARMV7M_CONTROL, "control", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
+	{ ARMV7M_PRIMASK, "primask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system", NULL, },
+	{ ARMV7M_BASEPRI, "basepri", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system", NULL, },
+	{ ARMV7M_FAULTMASK, "faultmask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system", NULL, },
+	{ ARMV7M_CONTROL, "control", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system", NULL, },
 
 	/* ARMv8-M security extension (TrustZone) specific registers */
-	{ ARMV8M_MSP_NS, "msp_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
-	{ ARMV8M_PSP_NS, "psp_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
-	{ ARMV8M_MSP_S, "msp_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
-	{ ARMV8M_PSP_S, "psp_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
-	{ ARMV8M_MSPLIM_S, "msplim_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
-	{ ARMV8M_PSPLIM_S, "psplim_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
-	{ ARMV8M_MSPLIM_NS, "msplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
-	{ ARMV8M_PSPLIM_NS, "psplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
-
-	{ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, "pmsk_bpri_fltmsk_ctrl_s", 32, REG_TYPE_INT, NULL, NULL },
-	{ ARMV8M_PRIMASK_S, "primask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
-	{ ARMV8M_BASEPRI_S, "basepri_s", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
-	{ ARMV8M_FAULTMASK_S, "faultmask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
-	{ ARMV8M_CONTROL_S, "control_s", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
-
-	{ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS, "pmsk_bpri_fltmsk_ctrl_ns", 32, REG_TYPE_INT, NULL, NULL },
-	{ ARMV8M_PRIMASK_NS, "primask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
-	{ ARMV8M_BASEPRI_NS, "basepri_ns", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
-	{ ARMV8M_FAULTMASK_NS, "faultmask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
-	{ ARMV8M_CONTROL_NS, "control_ns", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+	{ ARMV8M_MSP_NS, "msp_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext", NULL, },
+	{ ARMV8M_PSP_NS, "psp_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext", NULL, },
+	{ ARMV8M_MSP_S, "msp_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext", NULL, },
+	{ ARMV8M_PSP_S, "psp_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext", NULL, },
+	{ ARMV8M_MSPLIM_S, "msplim_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext", NULL, },
+	{ ARMV8M_PSPLIM_S, "psplim_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext", NULL, },
+	{ ARMV8M_MSPLIM_NS, "msplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext", NULL, },
+	{ ARMV8M_PSPLIM_NS, "psplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext", NULL, },
+
+	{ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, "pmsk_bpri_fltmsk_ctrl_s", 32, REG_TYPE_INT, NULL, NULL, NULL, },
+	{ ARMV8M_PRIMASK_S, "primask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext", NULL, },
+	{ ARMV8M_BASEPRI_S, "basepri_s", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext", NULL, },
+	{ ARMV8M_FAULTMASK_S, "faultmask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext", NULL, },
+	{ ARMV8M_CONTROL_S, "control_s", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext", NULL, },
+
+	{ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS, "pmsk_bpri_fltmsk_ctrl_ns", 32, REG_TYPE_INT, NULL, NULL, NULL, },
+	{ ARMV8M_PRIMASK_NS, "primask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext", NULL, },
+	{ ARMV8M_BASEPRI_NS, "basepri_ns", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext", NULL, },
+	{ ARMV8M_FAULTMASK_NS, "faultmask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext", NULL, },
+	{ ARMV8M_CONTROL_NS, "control_ns", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext", NULL, },
 
 	/* FPU registers */
-	{ ARMV7M_D0, "d0", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-	{ ARMV7M_D1, "d1", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-	{ ARMV7M_D2, "d2", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-	{ ARMV7M_D3, "d3", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-	{ ARMV7M_D4, "d4", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-	{ ARMV7M_D5, "d5", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-	{ ARMV7M_D6, "d6", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-	{ ARMV7M_D7, "d7", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-	{ ARMV7M_D8, "d8", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-	{ ARMV7M_D9, "d9", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-	{ ARMV7M_D10, "d10", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-	{ ARMV7M_D11, "d11", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-	{ ARMV7M_D12, "d12", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-	{ ARMV7M_D13, "d13", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-	{ ARMV7M_D14, "d14", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-	{ ARMV7M_D15, "d15", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-
-	{ ARMV7M_FPSCR, "fpscr", 32, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp" },
+	{ ARMV7M_D0, "d0", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
+	{ ARMV7M_D1, "d1", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
+	{ ARMV7M_D2, "d2", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
+	{ ARMV7M_D3, "d3", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
+	{ ARMV7M_D4, "d4", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
+	{ ARMV7M_D5, "d5", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
+	{ ARMV7M_D6, "d6", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
+	{ ARMV7M_D7, "d7", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
+	{ ARMV7M_D8, "d8", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
+	{ ARMV7M_D9, "d9", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
+	{ ARMV7M_D10, "d10", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
+	{ ARMV7M_D11, "d11", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
+	{ ARMV7M_D12, "d12", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
+	{ ARMV7M_D13, "d13", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
+	{ ARMV7M_D14, "d14", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
+	{ ARMV7M_D15, "d15", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
+
+	{ ARMV7M_FPSCR, "fpscr", 32, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp", NULL, },
 };
 
 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
@@ -811,10 +812,14 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
 			LOG_TARGET_ERROR(target, "unable to allocate feature list");
 
 		reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
-		if (reg_list[i].reg_data_type)
-			reg_list[i].reg_data_type->type = armv7m_regs[i].type;
-		else
+		if (reg_list[i].reg_data_type) {
+			if (armv7m_regs[i].data_type)
+				*reg_list[i].reg_data_type = *armv7m_regs[i].data_type;
+			else
+				reg_list[i].reg_data_type->type = armv7m_regs[i].type;
+		} else {
 			LOG_TARGET_ERROR(target, "unable to allocate reg type list");
+		}
 	}
 
 	arm->cpsr = reg_list + ARMV7M_XPSR;

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv7m.c | 137 +++++++++++++++++++++++++++-------------------------
 1 file changed, 71 insertions(+), 66 deletions(-)


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- Log -----------------------------------------------------------------
commit 83e0293f7ba3604b4ad98b3a8101388e3e52f9fe
Author: Richard Pasek <rp...@go...>
Date:   Wed Dec 11 00:43:57 2024 -0500

    Add Linux SPI device SWD adapter support
    
    To alleviate the need to bitbang SWD, I've written a SWD SPI
    implementation. This code is inspired by the work of lu...@ap...
    as shown at github.com/lupyuen/openocd-spi but with the desire to be
    more generic. This implementation makes use of the more common 4 wire
    SPI port using full duplex transfers to be able to capture the SWD ACK
    bits when a SWD TX operation is in progress.
    
    TEST:
      Connects successfully with the following combinations:
      Hosts:
        Raspberry Pi 4B
        Unnamed Qualcomm SoC with QUPv3 based SPI port
      Targets:
        Raspberry Pi 2040
        Nordic nRF52840
        NXP RT500
    
    Change-Id: Ic2f38a1806085d527e6f999a3d15aea6f32d1019
    Signed-off-by: Richard Pasek <rp...@go...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8645
    Reviewed-by: Tomas Vanek <va...@fb...>
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: zapb <de...@za...>
    Tested-by: jenkins

diff --git a/configure.ac b/configure.ac
index db47dcba6..49054288f 100644
--- a/configure.ac
+++ b/configure.ac
@@ -163,6 +163,9 @@ m4_define([PCIE_ADAPTERS],
 m4_define([SERIAL_PORT_ADAPTERS],
 	[[[buspirate], [Bus Pirate], [BUS_PIRATE]]])
 
+m4_define([LINUXSPIDEV_ADAPTER],
+	[[[linuxspidev], [Linux spidev driver], [LINUXSPIDEV]]])
+
 # The word 'Adapter' in "Dummy Adapter" below must begin with a capital letter
 # because there is an M4 macro called 'adapter'.
 m4_define([DUMMY_ADAPTER],
@@ -289,6 +292,7 @@ AC_ARG_ADAPTERS([
   LIBFTDI_ADAPTERS,
   LIBFTDI_USB1_ADAPTERS,
   LIBGPIOD_ADAPTERS,
+  LINUXSPIDEV_ADAPTER,
   SERIAL_PORT_ADAPTERS,
   DUMMY_ADAPTER,
   PCIE_ADAPTERS,
@@ -726,6 +730,7 @@ PROCESS_ADAPTERS([LIBJAYLINK_ADAPTERS], ["x$use_internal_libjaylink" = "xyes" -o
 PROCESS_ADAPTERS([PCIE_ADAPTERS], ["x$is_linux" = "xyes"], [Linux build])
 PROCESS_ADAPTERS([SERIAL_PORT_ADAPTERS], ["x$can_build_buspirate" = "xyes"],
                                          [internal error: validation should happen beforehand])
+PROCESS_ADAPTERS([LINUXSPIDEV_ADAPTER], ["x$is_linux" = "xyes"], [Linux spidev])
 PROCESS_ADAPTERS([DUMMY_ADAPTER], [true], [unused])
 
 AS_IF([test "x$enable_linuxgpiod" != "xno"], [
@@ -875,6 +880,7 @@ m4_foreach([adapter], [USB1_ADAPTERS,
 	LIBFTDI_USB1_ADAPTERS,
 	LIBGPIOD_ADAPTERS,
 	LIBJAYLINK_ADAPTERS, PCIE_ADAPTERS, SERIAL_PORT_ADAPTERS,
+	LINUXSPIDEV_ADAPTER,
 	DUMMY_ADAPTER,
 	OPTIONAL_LIBRARIES,
 	COVERAGE],
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 7c5f84c55..47a6f69eb 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -614,6 +614,9 @@ emulation model of target hardware.
 @item @b{xlnx_pcie_xvc}
 @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
 
+@item @b{linuxspidev}
+@* A SPI based SWD driver using Linux SPI devices.
+
 @item @b{linuxgpiod}
 @* A bitbang JTAG driver using Linux GPIO through library libgpiod.
 
@@ -3401,6 +3404,70 @@ See @file{interface/beaglebone-swd-native.cfg} for a sample configuration file.
 
 @end deffn
 
+@deffn {Interface Driver} {linuxspidev}
+Linux provides userspace access to SPI through spidev. Full duplex SPI
+transactions are used to simultaneously read and write to/from the target to
+emulate the SWD transport.
+
+@deffn {Config Command} {spidev path} path
+Specifies the path to the spidev device.
+@end deffn
+
+@deffn {Config Command} {spidev mode} value
+Set the mode of the spi port with optional bit flags (default=3).
+See /usr/include/linux/spi/spidev.h for all of the SPI mode options.
+@end deffn
+
+@deffn {Config Command} {spidev queue_entries} value
+Set the maximum number of queued transactions per spi exchange (default=64).
+More queued transactions may offer greater performance when the target doesn't
+need to wait. On the contrary higher numbers will reduce performance when the
+target requests a wait as all queued transactions will need to be exchanged
+before spidev can see the wait request.
+@end deffn
+
+See @file{tcl/interface/spidev_example.cfg} for a sample configuration file.
+
+Electrical connections:
+@example
++--------------+                +--------------+
+|              |     1K         |              |
+|          MOSI|---/\/\/\---+   |              |
+|     Host     |            |   |    Target    |
+|          MISO|------------+---|SWDIO         |
+|              |                |              |
+|           SCK|----------------|SWDCLK        |
+|              |                |              |
++--------------+                +--------------+
+@end example
+
+The 1K resistor works well with most MCUs up to 3 MHz. A lower resistance
+could be used to achieve higher speeds granted that the target SWDIO pin has
+enough drive strength to pull the signal high while being pulled low by this
+resistor.
+
+If you are having trouble here are some tips:
+
+@itemize @bullet
+
+@item @b{Make sure MISO and MOSI are tied together with a 1K resistor.}
+MISO should be attached to the target.
+
+@item @b{Make sure that your host and target are using the same I/O voltage}
+(for example both are using 3.3 volts).
+
+@item @b{Your host's SPI port may not idle low.}
+This will lead to an additional clock edge being sent to the target, causing
+the host and target being 1 clock off from each other. Try setting
+SPI_MOSI_IDLE_LOW in spi_mode. Try using a different spi_mode (0 - 3).
+
+@item @b{Your target may pull SWDIO and/or SWDCLK high.}
+This will create an extra edge when the host releases control of the SPI port
+at the end of a transaction. You'll need to confirm this with a scope or meter.
+Try installing 10K resistors on SWDIO and SWDCLK to ground to stop this.
+
+@end itemize
+@end deffn
 
 @deffn {Interface Driver} {linuxgpiod}
 Linux provides userspace access to GPIO through libgpiod since Linux kernel
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index da0663fd4..ec233b247 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -176,6 +176,9 @@ endif
 if SYSFSGPIO
 DRIVERFILES += %D%/sysfsgpio.c
 endif
+if LINUXSPIDEV
+DRIVERFILES += %D%/linuxspidev.c
+endif
 if XLNX_PCIE_XVC
 DRIVERFILES += %D%/xlnx-pcie-xvc.c
 endif
diff --git a/src/jtag/drivers/linuxspidev.c b/src/jtag/drivers/linuxspidev.c
new file mode 100644
index 000000000..737d2bef8
--- /dev/null
+++ b/src/jtag/drivers/linuxspidev.c
@@ -0,0 +1,622 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/* Copyright (C) 2020 by Lup Yuen Lee <lu...@ap...>
+ * Copyright (C) 2024 by Richard Pasek <rp...@go...>
+ */
+
+/**
+ * @file
+ * Implementation of SWD protocol with a Linux SPI device.
+ */
+
+/* Uncomment to log SPI exchanges (very verbose, slows things down a lot)
+ *
+ * A quick note on interpreting SPI exchange messages:
+ *
+ * This implementation works by performing SPI exchanges with MOSI and MISO
+ * tied together with a 1K resistor. This combined signal becomes SWDIO.
+ *
+ * Since we are performing SPI exchanges, (reading and writing at the same
+ * time) this means when the target isn't driving SWDIO, what is written by
+ * the host should also be read by the host.
+ *
+ * On SWD writes:
+ *   The TX and RX data should match except for the ACK bits from the target
+ *     swd write reg exchange: len=6
+ *      tx_buf=C5 02 40 00 02 2C
+ *      rx_buf=C5 42 40 00 02 2C
+ *                ^
+ *                |
+ *          ACK from target
+ *
+ * On SWD reads:
+ *   Only the command byte should match
+ *     swd read reg exchange: len=6
+ *      tx_buf=B1 00 00 00 00 00
+ *      rx_buf=B1 40 20 00 00 F8
+ *             ^^
+ *             ||
+ *     Command packet from host
+ *
+ */
+// #define LOG_SPI_EXCHANGE
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stdint.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <string.h>
+#include <fcntl.h>
+#include <sys/ioctl.h>
+#include <linux/spi/spidev.h>
+#include <jtag/adapter.h>
+#include <jtag/swd.h>
+#include <jtag/interface.h>
+#include <jtag/commands.h>
+
+// Number of bits per SPI exchange
+#define SPI_BITS 8
+
+// Time in uS after the last bit of transfer before deselecting the device
+#define SPI_DESELECT_DELAY 0
+
+// Maximum number of SWD transactions to queue together in a SPI exchange
+#define MAX_QUEUE_ENTRIES 64
+
+#define CMD_BITS 8
+#define TURN_BITS 1
+#define ACK_BITS 3
+#define DATA_BITS 32
+#define PARITY_BITS 1
+
+#define SWD_WR_BITS (CMD_BITS + TURN_BITS + ACK_BITS + TURN_BITS + DATA_BITS + PARITY_BITS)
+#define SWD_RD_BITS (CMD_BITS + TURN_BITS + ACK_BITS + DATA_BITS + PARITY_BITS + TURN_BITS)
+#define SWD_OP_BITS (MAX(SWD_WR_BITS, SWD_RD_BITS))
+#define SWD_OP_BYTES (DIV_ROUND_UP(SWD_OP_BITS, SPI_BITS))
+
+#define AP_DELAY_CLOCKS 8
+#define AP_DELAY_BYTES (DIV_ROUND_UP(AP_DELAY_CLOCKS, SPI_BITS))
+
+#define END_IDLE_CLOCKS 8
+#define END_IDLE_BYTES (DIV_ROUND_UP(END_IDLE_CLOCKS, SPI_BITS))
+
+// File descriptor for SPI device
+static int spi_fd = -1;
+
+// SPI Configuration
+static char *spi_path;
+static uint32_t spi_mode = SPI_MODE_3; // Note: SPI in LSB mode is not often supported. We'll flip LSB to MSB ourselves.
+static uint32_t spi_speed;
+
+struct queue_info {
+	unsigned int buf_idx;
+	uint32_t *rx_ptr;
+};
+
+static int queue_retval;
+static unsigned int max_queue_entries;
+static unsigned int queue_fill;
+static unsigned int queue_buf_fill;
+static unsigned int queue_buf_size;
+static struct queue_info *queue_infos;
+static uint8_t *queue_tx_buf;
+static uint8_t *queue_rx_buf;
+static uint8_t *tx_flip_buf;
+
+static int spidev_swd_switch_seq(enum swd_special_seq seq);
+static void spidev_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk);
+
+static void spi_exchange(const uint8_t *tx_data, uint8_t *rx_data, unsigned int len)
+{
+#ifdef LOG_SPI_EXCHANGE
+	LOG_OUTPUT("exchange: len=%u\n", len);
+#endif // LOG_SPI_EXCHANGE
+
+	if (len == 0) {
+		LOG_DEBUG("exchange with no length");
+		return;
+	}
+
+	if (!tx_data && !rx_data) {
+		LOG_DEBUG("exchange with no valid tx or rx pointers");
+		return;
+	}
+
+	if (len > queue_buf_size) {
+		LOG_ERROR("exchange too large len=%u ", len);
+		return;
+	}
+
+	if (tx_data) {
+		// Reverse LSB to MSB
+		for (unsigned int i = 0; i < len; i++)
+			tx_flip_buf[i] = flip_u32(tx_data[i], 8);
+
+#ifdef LOG_SPI_EXCHANGE
+		if (len != 0) {
+			LOG_OUTPUT(" tx_buf=");
+			for (unsigned int i = 0; i < len; i++)
+				LOG_OUTPUT("%.2" PRIx8 " ", tx_flip_buf[i]);
+		}
+		LOG_OUTPUT("\n");
+#endif // LOG_SPI_EXCHANGE
+	}
+	// Transmit the MSB buffer to SPI device.
+	struct spi_ioc_transfer tr = {
+		/* The following must be cast to unsigned long to compile correctly on
+		 * 32 and 64 bit machines (as is done in the spidev examples in Linux
+		 * kernel code in tools/spi/).
+		 */
+		.tx_buf = (unsigned long)(tx_data ? tx_flip_buf : NULL),
+		.rx_buf = (unsigned long)rx_data,
+		.len = len,
+		.delay_usecs = SPI_DESELECT_DELAY,
+		.speed_hz = spi_speed,
+		.bits_per_word = SPI_BITS,
+	};
+	int ret = ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr);
+
+	if (ret < 1) {
+		LOG_ERROR("exchange failed");
+		return;
+	}
+
+	if (rx_data) {
+#ifdef LOG_SPI_EXCHANGE
+		if (len != 0) {
+			LOG_OUTPUT(" rx_buf=");
+			for (unsigned int i = 0; i < len; i++)
+				LOG_OUTPUT("%.2" PRIx8 " ", rx_data[i]);
+		}
+		LOG_OUTPUT("\n");
+#endif // LOG_SPI_EXCHANGE
+
+		// Reverse MSB to LSB
+		for (unsigned int i = 0; i < len; i++)
+			rx_data[i] = flip_u32(rx_data[i], 8);
+	}
+}
+
+static int spidev_speed(int speed)
+{
+	uint32_t tmp_speed = speed;
+
+	int ret = ioctl(spi_fd, SPI_IOC_WR_MAX_SPEED_HZ, &tmp_speed);
+	if (ret == -1) {
+		LOG_ERROR("Failed to set SPI %d speed", speed);
+		return ERROR_FAIL;
+	}
+
+	spi_speed = speed;
+
+	return ERROR_OK;
+}
+
+static int spidev_speed_div(int speed, int *khz)
+{
+	*khz = speed / 1000;
+	return ERROR_OK;
+}
+
+static int spidev_khz(int khz, int *jtag_speed)
+{
+	if (khz == 0) {
+		LOG_DEBUG("RCLK not supported");
+		return ERROR_FAIL;
+	}
+
+	*jtag_speed = khz * 1000;
+	return ERROR_OK;
+}
+
+static void spidev_free_queue(void)
+{
+	max_queue_entries = 0;
+	queue_buf_size = 0;
+
+	free(queue_infos);
+	queue_infos = NULL;
+
+	free(queue_tx_buf);
+	queue_tx_buf = NULL;
+
+	free(queue_rx_buf);
+	queue_rx_buf = NULL;
+
+	free(tx_flip_buf);
+	tx_flip_buf = NULL;
+}
+
+static int spidev_alloc_queue(unsigned int new_queue_entries)
+{
+	if (queue_fill || queue_buf_fill) {
+		LOG_ERROR("Can't realloc allocate queue when queue is in use");
+		return ERROR_FAIL;
+	}
+
+	unsigned int new_queue_buf_size =
+		(new_queue_entries * (SWD_OP_BYTES + AP_DELAY_BYTES)) + END_IDLE_BYTES;
+
+	queue_infos = realloc(queue_infos, sizeof(struct queue_info) * new_queue_entries);
+	if (!queue_infos)
+		goto realloc_fail;
+
+	queue_tx_buf = realloc(queue_tx_buf, new_queue_buf_size);
+	if (!queue_tx_buf)
+		goto realloc_fail;
+
+	queue_rx_buf = realloc(queue_rx_buf, new_queue_buf_size);
+	if (!queue_rx_buf)
+		goto realloc_fail;
+
+	tx_flip_buf = realloc(tx_flip_buf, new_queue_buf_size);
+	if (!tx_flip_buf)
+		goto realloc_fail;
+
+	max_queue_entries = new_queue_entries;
+	queue_buf_size = new_queue_buf_size;
+
+	LOG_DEBUG("Set queue entries to %u (buffers %u bytes)", max_queue_entries, queue_buf_size);
+
+	return ERROR_OK;
+
+realloc_fail:
+	spidev_free_queue();
+
+	LOG_ERROR("Couldn't allocate queue. Out of memory.");
+	return ERROR_FAIL;
+}
+
+static int spidev_init(void)
+{
+	LOG_INFO("SPI SWD driver");
+
+	if (spi_fd >= 0)
+		return ERROR_OK;
+
+	if (!spi_path) {
+		LOG_ERROR("Path to spidev not set");
+		return ERROR_JTAG_INIT_FAILED;
+	}
+
+	// Open SPI device.
+	spi_fd = open(spi_path, O_RDWR);
+	if (spi_fd < 0) {
+		LOG_ERROR("Failed to open SPI port at %s", spi_path);
+		return ERROR_JTAG_INIT_FAILED;
+	}
+
+	// Set SPI mode.
+	int ret = ioctl(spi_fd, SPI_IOC_WR_MODE32, &spi_mode);
+	if (ret == -1) {
+		LOG_ERROR("Failed to set SPI mode 0x%" PRIx32, spi_mode);
+		return ERROR_JTAG_INIT_FAILED;
+	}
+
+	// Set SPI bits per word.
+	uint32_t spi_bits = SPI_BITS;
+	ret = ioctl(spi_fd, SPI_IOC_WR_BITS_PER_WORD, &spi_bits);
+	if (ret == -1) {
+		LOG_ERROR("Failed to set SPI %" PRIu8 " bits per transfer", spi_bits);
+		return ERROR_JTAG_INIT_FAILED;
+	}
+
+	LOG_INFO("Opened SPI device at %s in mode 0x%" PRIx32 " with %" PRIu8 " bits ",
+		spi_path, spi_mode, spi_bits);
+
+	// Set SPI read and write max speed.
+	int speed;
+	ret = adapter_get_speed(&speed);
+	if (ret != ERROR_OK) {
+		LOG_ERROR("Failed to get adapter speed");
+		return ERROR_JTAG_INIT_FAILED;
+	}
+
+	ret = spidev_speed(speed);
+	if (ret != ERROR_OK)
+		return ERROR_JTAG_INIT_FAILED;
+
+	if (max_queue_entries == 0) {
+		ret = spidev_alloc_queue(MAX_QUEUE_ENTRIES);
+		if (ret != ERROR_OK)
+			return ERROR_JTAG_INIT_FAILED;
+	}
+
+	return ERROR_OK;
+}
+
+static int spidev_quit(void)
+{
+	spidev_free_queue();
+
+	if (spi_fd < 0)
+		return ERROR_OK;
+
+	close(spi_fd);
+	spi_fd = -1;
+	return ERROR_OK;
+}
+
+static int spidev_swd_init(void)
+{
+	LOG_DEBUG("spidev_swd_init");
+	return ERROR_OK;
+}
+
+static int spidev_swd_execute_queue(unsigned int end_idle_bytes)
+{
+	LOG_DEBUG_IO("Executing %u queued transactions", queue_fill);
+
+	if (queue_retval != ERROR_OK) {
+		LOG_DEBUG_IO("Skipping due to previous errors: %d", queue_retval);
+		goto skip;
+	}
+
+	/* A transaction must be followed by another transaction or at least 8 idle
+	 * cycles to ensure that data is clocked through the AP. Since the tx
+	 * buffer is zeroed after each queue run, every byte added to the buffer
+	 * fill will add on an additional 8 idle cycles.
+	 */
+	queue_buf_fill += end_idle_bytes;
+
+	spi_exchange(queue_tx_buf, queue_rx_buf, queue_buf_fill);
+
+	for (unsigned int queue_idx = 0; queue_idx < queue_fill; queue_idx++) {
+		unsigned int buf_idx = queue_infos[queue_idx].buf_idx;
+		uint8_t *tx_ptr = &queue_tx_buf[buf_idx];
+		uint8_t *rx_ptr = &queue_rx_buf[buf_idx];
+		uint8_t cmd = buf_get_u32(tx_ptr, 0, CMD_BITS);
+		bool read = cmd & SWD_CMD_RNW ? true : false;
+		int ack = buf_get_u32(rx_ptr, CMD_BITS + TURN_BITS, ACK_BITS);
+		uint32_t data = read ?
+			buf_get_u32(rx_ptr, CMD_BITS + TURN_BITS + ACK_BITS, DATA_BITS) :
+			buf_get_u32(tx_ptr, CMD_BITS + TURN_BITS + ACK_BITS + TURN_BITS, DATA_BITS);
+
+		// Devices do not reply to DP_TARGETSEL write cmd, ignore received ack
+		bool check_ack = swd_cmd_returns_ack(cmd);
+
+		LOG_CUSTOM_LEVEL((check_ack && ack != SWD_ACK_OK) ? LOG_LVL_DEBUG : LOG_LVL_DEBUG_IO,
+				"%s%s %s %s reg %X = %08" PRIx32,
+				check_ack ? "" : "ack ignored ",
+				ack == SWD_ACK_OK ? "OK" :
+				ack == SWD_ACK_WAIT ? "WAIT" :
+				ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
+				cmd & SWD_CMD_APNDP ? "AP" : "DP",
+				read ? "read" : "write",
+				(cmd & SWD_CMD_A32) >> 1,
+				data);
+
+		if (ack != SWD_ACK_OK && check_ack) {
+			queue_retval = swd_ack_to_error_code(ack);
+			goto skip;
+
+		} else if (read) {
+			int parity = buf_get_u32(rx_ptr, CMD_BITS + TURN_BITS + ACK_BITS + DATA_BITS, PARITY_BITS);
+
+			if (parity != parity_u32(data)) {
+				LOG_ERROR("SWD Read data parity mismatch");
+				queue_retval = ERROR_FAIL;
+				goto skip;
+			}
+
+			if (queue_infos[queue_idx].rx_ptr)
+				*queue_infos[queue_idx].rx_ptr = data;
+		}
+	}
+
+skip:
+	// Clear everything in the queue
+	queue_fill = 0;
+	queue_buf_fill = 0;
+	memset(queue_infos, 0, sizeof(queue_infos[0]) * max_queue_entries);
+	memset(queue_tx_buf, 0, queue_buf_size);
+	memset(queue_rx_buf, 0, queue_buf_size);
+
+	int retval = queue_retval;
+	queue_retval = ERROR_OK;
+
+	return retval;
+}
+
+static int spidev_swd_run_queue(void)
+{
+	/* Since we are unsure if another SWD transaction will follow the
+	 * transactions we are just about to execute, we need to add on 8 idle
+	 * cycles.
+	 */
+	return spidev_swd_execute_queue(END_IDLE_BYTES);
+}
+
+static void spidev_swd_queue_cmd(uint8_t cmd, uint32_t *dst, uint32_t data, uint32_t ap_delay_clk)
+{
+	unsigned int swd_op_bytes = DIV_ROUND_UP(SWD_OP_BITS + ap_delay_clk, SPI_BITS);
+
+	if (queue_fill >= max_queue_entries ||
+	    queue_buf_fill + swd_op_bytes + END_IDLE_BYTES > queue_buf_size) {
+		/* Not enough room in the queue. Run the queue. No idle bytes are
+		 * needed because we are going to execute transactions right after
+		 * the queue is emptied.
+		 */
+		queue_retval = spidev_swd_execute_queue(0);
+	}
+
+	if (queue_retval != ERROR_OK)
+		return;
+
+	uint8_t *tx_ptr = &queue_tx_buf[queue_buf_fill];
+
+	cmd |= SWD_CMD_START | SWD_CMD_PARK;
+
+	buf_set_u32(tx_ptr, 0, CMD_BITS, cmd);
+
+	if (cmd & SWD_CMD_RNW) {
+		// Queue a read transaction
+		queue_infos[queue_fill].rx_ptr = dst;
+	} else {
+		// Queue a write transaction
+		buf_set_u32(tx_ptr,
+			CMD_BITS + TURN_BITS + ACK_BITS + TURN_BITS, DATA_BITS, data);
+		buf_set_u32(tx_ptr,
+			CMD_BITS + TURN_BITS + ACK_BITS + TURN_BITS + DATA_BITS, PARITY_BITS, parity_u32(data));
+	}
+
+	queue_infos[queue_fill].buf_idx = queue_buf_fill;
+
+	/* Add idle cycles after AP accesses to avoid WAIT. Buffer is already
+	 * zeroed so we just need to advance the pointer to add idle cycles.
+	 */
+	queue_buf_fill += swd_op_bytes;
+
+	queue_fill++;
+}
+
+static void spidev_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk)
+{
+	assert(cmd & SWD_CMD_RNW);
+	spidev_swd_queue_cmd(cmd, value, 0, ap_delay_clk);
+}
+
+static void spidev_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk)
+{
+	assert(!(cmd & SWD_CMD_RNW));
+	spidev_swd_queue_cmd(cmd, NULL, value, ap_delay_clk);
+}
+
+static int spidev_swd_switch_seq(enum swd_special_seq seq)
+{
+	switch (seq) {
+	case LINE_RESET:
+		LOG_DEBUG_IO("SWD line reset");
+		spi_exchange(swd_seq_line_reset, NULL, swd_seq_line_reset_len / SPI_BITS);
+		break;
+	case JTAG_TO_SWD:
+		LOG_DEBUG("JTAG-to-SWD");
+		spi_exchange(swd_seq_jtag_to_swd, NULL, swd_seq_jtag_to_swd_len / SPI_BITS);
+		break;
+	case JTAG_TO_DORMANT:
+		LOG_DEBUG("JTAG-to-DORMANT");
+		spi_exchange(swd_seq_jtag_to_dormant, NULL, swd_seq_jtag_to_dormant_len / SPI_BITS);
+		break;
+	case SWD_TO_JTAG:
+		LOG_DEBUG("SWD-to-JTAG");
+		spi_exchange(swd_seq_swd_to_jtag, NULL, swd_seq_swd_to_jtag_len / SPI_BITS);
+		break;
+	case SWD_TO_DORMANT:
+		LOG_DEBUG("SWD-to-DORMANT");
+		spi_exchange(swd_seq_swd_to_dormant, NULL, swd_seq_swd_to_dormant_len / SPI_BITS);
+		break;
+	case DORMANT_TO_SWD:
+		LOG_DEBUG("DORMANT-to-SWD");
+		spi_exchange(swd_seq_dormant_to_swd, NULL, swd_seq_dormant_to_swd_len / SPI_BITS);
+		break;
+	case DORMANT_TO_JTAG:
+		LOG_DEBUG("DORMANT-to-JTAG");
+		spi_exchange(swd_seq_dormant_to_jtag, NULL, swd_seq_dormant_to_jtag_len / SPI_BITS);
+		break;
+	default:
+		LOG_ERROR("Sequence %d not supported", seq);
+		return ERROR_FAIL;
+	}
+
+	return ERROR_OK;
+}
+
+COMMAND_HANDLER(spidev_handle_path_command)
+{
+	if (CMD_ARGC != 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	free(spi_path);
+	spi_path = strdup(CMD_ARGV[0]);
+	if (!spi_path) {
+		LOG_ERROR("Out of memory");
+		return ERROR_FAIL;
+	}
+
+	return ERROR_OK;
+}
+
+COMMAND_HANDLER(spidev_handle_mode_command)
+{
+	if (CMD_ARGC != 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], spi_mode);
+	return ERROR_OK;
+}
+
+COMMAND_HANDLER(spidev_handle_queue_entries_command)
+{
+	uint32_t new_queue_entries;
+
+	if (CMD_ARGC != 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_queue_entries);
+
+	return spidev_alloc_queue(new_queue_entries);
+}
+
+const struct swd_driver spidev_swd = {
+	.init = spidev_swd_init,
+	.switch_seq = spidev_swd_switch_seq,
+	.read_reg = spidev_swd_read_reg,
+	.write_reg = spidev_swd_write_reg,
+	.run = spidev_swd_run_queue,
+};
+
+static const struct command_registration spidev_subcommand_handlers[] = {
+	{
+		.name = "path",
+		.handler = &spidev_handle_path_command,
+		.mode = COMMAND_CONFIG,
+		.help = "set the path to the spidev device",
+		.usage = "path_to_spidev",
+	},
+	{
+		.name = "mode",
+		.handler = &spidev_handle_mode_command,
+		.mode = COMMAND_CONFIG,
+		.help = "set the mode of the spi port with optional bit flags (default=3)",
+		.usage = "mode",
+	},
+	{
+		.name = "queue_entries",
+		.handler = &spidev_handle_queue_entries_command,
+		.mode = COMMAND_CONFIG,
+		.help = "set the queue entry size (default=64)",
+		.usage = "queue_entries",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration spidev_command_handlers[] = {
+	{
+		.name = "spidev",
+		.mode = COMMAND_ANY,
+		.help = "perform spidev management",
+		.chain = spidev_subcommand_handlers,
+		.usage = "",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
+// Only SWD transport supported
+static const char *const spidev_transports[] = { "swd", NULL };
+
+struct adapter_driver linuxspidev_adapter_driver = {
+	.name = "linuxspidev",
+	.transports = spidev_transports,
+	.commands = spidev_command_handlers,
+
+	.init = spidev_init,
+	.quit = spidev_quit,
+	.speed = spidev_speed,
+	.khz = spidev_khz,
+	.speed_div = spidev_speed_div,
+
+	.swd_ops = &spidev_swd,
+};
diff --git a/src/jtag/interface.h b/src/jtag/interface.h
index b448851dc..f69326492 100644
--- a/src/jtag/interface.h
+++ b/src/jtag/interface.h
@@ -386,6 +386,7 @@ extern struct adapter_driver jtag_dpi_adapter_driver;
 extern struct adapter_driver jtag_vpi_adapter_driver;
 extern struct adapter_driver kitprog_adapter_driver;
 extern struct adapter_driver linuxgpiod_adapter_driver;
+extern struct adapter_driver linuxspidev_adapter_driver;
 extern struct adapter_driver opendous_adapter_driver;
 extern struct adapter_driver openjtag_adapter_driver;
 extern struct adapter_driver osbdm_adapter_driver;
diff --git a/src/jtag/interfaces.c b/src/jtag/interfaces.c
index 67f0838e3..e49bd9e0f 100644
--- a/src/jtag/interfaces.c
+++ b/src/jtag/interfaces.c
@@ -123,6 +123,9 @@ struct adapter_driver *adapter_drivers[] = {
 #if BUILD_LINUXGPIOD == 1
 		&linuxgpiod_adapter_driver,
 #endif
+#if BUILD_LINUXSPIDEV == 1
+		&linuxspidev_adapter_driver,
+#endif
 #if BUILD_XLNX_PCIE_XVC == 1
 		&xlnx_pcie_xvc_adapter_driver,
 #endif
diff --git a/tcl/interface/spidev_example.cfg b/tcl/interface/spidev_example.cfg
new file mode 100644
index 000000000..2354c781b
--- /dev/null
+++ b/tcl/interface/spidev_example.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Example config for using Linux spidev as a SWD adapter.
+
+adapter driver linuxspidev
+adapter speed 3000
+spidev path "/dev/spidev0.0"
+spidev mode 3
+spidev queue_entries 64

-----------------------------------------------------------------------

Summary of changes:
 configure.ac                     |   6 +
 doc/openocd.texi                 |  67 +++++
 src/jtag/drivers/Makefile.am     |   3 +
 src/jtag/drivers/linuxspidev.c   | 622 +++++++++++++++++++++++++++++++++++++++
 src/jtag/interface.h             |   1 +
 src/jtag/interfaces.c            |   3 +
 tcl/interface/spidev_example.cfg |   9 +
 7 files changed, 711 insertions(+)
 create mode 100644 src/jtag/drivers/linuxspidev.c
 create mode 100644 tcl/interface/spidev_example.cfg


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- Log -----------------------------------------------------------------
commit 26f2df80c3f9ac54fc488ed26f6320904881c0d4
Author: Antonio Borneo <bor...@gm...>
Date:   Tue Dec 31 14:47:02 2024 +0100

    helper: list: rename macro clashing with sys/queue.h
    
    The macro named LIST_HEAD() clashed with a macro of same name in
    the GNU libc file sys/queue.h.
    This causes a warning in MacOS build due to some other system file
    including sys/queue.h.
    
    Rename LIST_HEAD() as OOCD_LIST_HEAD().
    
    Checkpatch-ignore: MACRO_ARG_REUSE
    Change-Id: Ic653edec77425a58251d64f56c9f5f6c645ba0cd
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reported-by: Andrew Shelley <ash...@bt...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8683
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>
    Reviewed-by: Andy <and...@gm...>

diff --git a/contrib/list_example.c b/contrib/list_example.c
index 4fcfcdf34..1f28dc2db 100644
--- a/contrib/list_example.c
+++ b/contrib/list_example.c
@@ -12,7 +12,7 @@
 #include <assert.h>
 #include <helper/list.h>
 
-static LIST_HEAD(threads);
+static OOCD_LIST_HEAD(threads);
 
 struct thread {
 	int id;
diff --git a/src/helper/list.h b/src/helper/list.h
index 47290c260..ba07f1556 100644
--- a/src/helper/list.h
+++ b/src/helper/list.h
@@ -46,7 +46,7 @@ struct list_head {
 
 #define LIST_HEAD_INIT(name) { &(name), &(name) }
 
-#define LIST_HEAD(name) \
+#define OOCD_LIST_HEAD(name) \
 	struct list_head name = LIST_HEAD_INIT(name)
 
 static inline void
diff --git a/src/server/telnet_server.c b/src/server/telnet_server.c
index 7818af2db..2c3f76980 100644
--- a/src/server/telnet_server.c
+++ b/src/server/telnet_server.c
@@ -570,7 +570,7 @@ static void telnet_auto_complete(struct connection *connection)
 		struct list_head lh;
 	};
 
-	LIST_HEAD(matches);
+	OOCD_LIST_HEAD(matches);
 
 	/* - user command sequence, either at line beginning
 	 *   or we start over after these characters ';', '[', '{'
diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index fee1a2485..c9ed5b948 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -431,7 +431,7 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap)
 	struct dap_cmd *el, *tmp, *prev = NULL;
 	int found_wait = 0;
 	int64_t time_now;
-	LIST_HEAD(replay_list);
+	OOCD_LIST_HEAD(replay_list);
 
 	/* make sure all queued transactions are complete */
 	retval = jtag_execute_queue();
diff --git a/src/target/arm_cti.c b/src/target/arm_cti.c
index 88eec832e..b2f78eef7 100644
--- a/src/target/arm_cti.c
+++ b/src/target/arm_cti.c
@@ -25,7 +25,7 @@ struct arm_cti {
 	struct adiv5_ap *ap;
 };
 
-static LIST_HEAD(all_cti);
+static OOCD_LIST_HEAD(all_cti);
 
 const char *arm_cti_name(struct arm_cti *self)
 {
diff --git a/src/target/arm_dap.c b/src/target/arm_dap.c
index 9f4afae74..c5bd6ccd4 100644
--- a/src/target/arm_dap.c
+++ b/src/target/arm_dap.c
@@ -18,7 +18,7 @@
 #include "transport/transport.h"
 #include "jtag/interface.h"
 
-static LIST_HEAD(all_dap);
+static OOCD_LIST_HEAD(all_dap);
 
 extern struct adapter_driver *adapter_driver;
 
diff --git a/src/target/arm_tpiu_swo.c b/src/target/arm_tpiu_swo.c
index c14fd5fc8..e20cd5927 100644
--- a/src/target/arm_tpiu_swo.c
+++ b/src/target/arm_tpiu_swo.c
@@ -126,7 +126,7 @@ struct arm_tpiu_swo_priv_connection {
 	struct arm_tpiu_swo_object *obj;
 };
 
-static LIST_HEAD(all_tpiu_swo);
+static OOCD_LIST_HEAD(all_tpiu_swo);
 
 #define ARM_TPIU_SWO_TRACE_BUF_SIZE	4096
 
diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c
index 8c3861080..efc076c99 100644
--- a/src/target/openrisc/or1k.c
+++ b/src/target/openrisc/or1k.c
@@ -27,8 +27,8 @@
 #include "or1k.h"
 #include "or1k_du.h"
 
-LIST_HEAD(tap_list);
-LIST_HEAD(du_list);
+OOCD_LIST_HEAD(tap_list);
+OOCD_LIST_HEAD(du_list);
 
 static int or1k_remove_breakpoint(struct target *target,
 				  struct breakpoint *breakpoint);
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 658c1fd9d..bb450ce62 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -214,7 +214,7 @@ typedef struct {
 	dm013_info_t *dm;
 } riscv013_info_t;
 
-static LIST_HEAD(dm_list);
+static OOCD_LIST_HEAD(dm_list);
 
 static riscv013_info_t *get_info(const struct target *target)
 {
diff --git a/src/target/target.c b/src/target/target.c
index 1fc8baf2c..8deab8f34 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -108,10 +108,10 @@ struct target *all_targets;
 static struct target_event_callback *target_event_callbacks;
 static struct target_timer_callback *target_timer_callbacks;
 static int64_t target_timer_next_event_value;
-static LIST_HEAD(target_reset_callback_list);
-static LIST_HEAD(target_trace_callback_list);
+static OOCD_LIST_HEAD(target_reset_callback_list);
+static OOCD_LIST_HEAD(target_trace_callback_list);
 static const int polling_interval = TARGET_DEFAULT_POLLING_INTERVAL;
-static LIST_HEAD(empty_smp_targets);
+static OOCD_LIST_HEAD(empty_smp_targets);
 
 enum nvp_assert {
 	NVP_DEASSERT,

-----------------------------------------------------------------------

Summary of changes:
 contrib/list_example.c       | 2 +-
 src/helper/list.h            | 2 +-
 src/server/telnet_server.c   | 2 +-
 src/target/adi_v5_jtag.c     | 2 +-
 src/target/arm_cti.c         | 2 +-
 src/target/arm_dap.c         | 2 +-
 src/target/arm_tpiu_swo.c    | 2 +-
 src/target/openrisc/or1k.c   | 4 ++--
 src/target/riscv/riscv-013.c | 2 +-
 src/target/target.c          | 6 +++---
 10 files changed, 13 insertions(+), 13 deletions(-)


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- Log -----------------------------------------------------------------
commit 0ed03df6e95bc336bbece000ffbe4028f70369d8
Author: R. Diez <rdi...@ya...>
Date:   Thu Nov 28 21:47:34 2024 +0100

    amend angie build definitions to fix make dist
    
    "make dist" was broken because GNU Make was using a built-in rule
    to try to build angie from angie.c . This is a limitation in Automake
    when you add a whole subdir with the same name to EXTRA_DIST.
    The Automake doc actually discourages adding whole subdirs.
    
    Change-Id: I85ea4ecbd529b060c70f83bcfda7522e1730480d
    Signed-off-by: R. Diez <rdi...@ya...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8600
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index 8be834859..da0663fd4 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -10,10 +10,8 @@ noinst_LTLIBRARIES += %D%/libocdjtagdrivers.la
 %C%_libocdjtagdrivers_la_CPPFLAGS = $(AM_CPPFLAGS)
 
 ULINK_FIRMWARE = %D%/OpenULINK
-ANGIE_FILES = %D%/angie
 
 EXTRA_DIST += $(ULINK_FIRMWARE) \
-	$(ANGIE_FILES) \
 	%D%/usb_blaster/README.CheapClone \
 	%D%/Makefile.rlink \
 	%D%/rlink_call.m4 \
@@ -125,12 +123,17 @@ ulinkdir = $(pkgdatadir)/OpenULINK
 dist_ulink_DATA = $(ULINK_FIRMWARE)/ulink_firmware.hex
 %C%_libocdjtagdrivers_la_LIBADD += -lm
 endif
+
 if ANGIE
-DRIVERFILES += %D%/angie.c
-angiedir = $(pkgdatadir)/angie
-dist_angie_DATA = $(ANGIE_FILES)/angie_firmware.bin $(ANGIE_FILES)/angie_bitstream.bit
-%C%_libocdjtagdrivers_la_LIBADD += -lm
+  angiedir = $(pkgdatadir)/angie  # This is only for dist_angie_DATA.
+  DRIVERFILES     += %D%/angie.c
+  DRIVERFILES     += %D%/angie/include/msgtypes.h
+  EXTRA_DIST      += %D%/angie/README
+  dist_angie_DATA  = %D%/angie/angie_firmware.bin
+  dist_angie_DATA += %D%/angie/angie_bitstream.bit
+  %C%_libocdjtagdrivers_la_LIBADD += -lm
 endif
+
 if VSLLINK
 DRIVERFILES += %D%/versaloon/usbtoxxx/usbtogpio.c
 DRIVERFILES += %D%/versaloon/usbtoxxx/usbtojtagraw.c

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/Makefile.am | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)


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commit 8b5ea720da530d375cc5c5d4a66fb48768a421de
Author: R. Diez <rdi...@ya...>
Date:   Sun Nov 3 12:06:05 2024 +0100

    make bitbang_interface const
    
    Change-Id: I5e187250d231aeefc7a206b7f7917c3b2e858d5a
    Signed-off-by: R. Diez <rdi...@ya...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8535
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/jtag/drivers/am335xgpio.c b/src/jtag/drivers/am335xgpio.c
index 9bb7ea7d1..05a73aa53 100644
--- a/src/jtag/drivers/am335xgpio.c
+++ b/src/jtag/drivers/am335xgpio.c
@@ -283,7 +283,7 @@ static int am335xgpio_blink(bool on)
 	return ERROR_OK;
 }
 
-static struct bitbang_interface am335xgpio_bitbang = {
+static const struct bitbang_interface am335xgpio_bitbang = {
 	.read = am335xgpio_read,
 	.write = am335xgpio_write,
 	.swdio_read = am335xgpio_swdio_read,
diff --git a/src/jtag/drivers/at91rm9200.c b/src/jtag/drivers/at91rm9200.c
index ba9ee5e34..57dd54c11 100644
--- a/src/jtag/drivers/at91rm9200.c
+++ b/src/jtag/drivers/at91rm9200.c
@@ -104,7 +104,7 @@ static int at91rm9200_write(int tck, int tms, int tdi);
 static int at91rm9200_init(void);
 static int at91rm9200_quit(void);
 
-static struct bitbang_interface at91rm9200_bitbang = {
+static const struct bitbang_interface at91rm9200_bitbang = {
 	.read = at91rm9200_read,
 	.write = at91rm9200_write,
 	.blink = NULL,
diff --git a/src/jtag/drivers/bitbang.c b/src/jtag/drivers/bitbang.c
index 42234a6f7..0a49feb00 100644
--- a/src/jtag/drivers/bitbang.c
+++ b/src/jtag/drivers/bitbang.c
@@ -37,7 +37,7 @@ static int bitbang_stableclocks(unsigned int num_cycles);
 
 static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk);
 
-struct bitbang_interface *bitbang_interface;
+const struct bitbang_interface *bitbang_interface;
 
 /* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work!
  *
diff --git a/src/jtag/drivers/bitbang.h b/src/jtag/drivers/bitbang.h
index 82405eb8a..d6fd95e27 100644
--- a/src/jtag/drivers/bitbang.h
+++ b/src/jtag/drivers/bitbang.h
@@ -67,6 +67,6 @@ extern const struct swd_driver bitbang_swd;
 
 int bitbang_execute_queue(struct jtag_command *cmd_queue);
 
-extern struct bitbang_interface *bitbang_interface;
+extern const struct bitbang_interface *bitbang_interface;
 
 #endif /* OPENOCD_JTAG_DRIVERS_BITBANG_H */
diff --git a/src/jtag/drivers/dummy.c b/src/jtag/drivers/dummy.c
index 4fe598fe3..315e03697 100644
--- a/src/jtag/drivers/dummy.c
+++ b/src/jtag/drivers/dummy.c
@@ -77,7 +77,7 @@ static int dummy_led(bool on)
 	return ERROR_OK;
 }
 
-static struct bitbang_interface dummy_bitbang = {
+static const struct bitbang_interface dummy_bitbang = {
 		.read = &dummy_read,
 		.write = &dummy_write,
 		.blink = &dummy_led,
diff --git a/src/jtag/drivers/ep93xx.c b/src/jtag/drivers/ep93xx.c
index c3e841d37..ae35f4ac0 100644
--- a/src/jtag/drivers/ep93xx.c
+++ b/src/jtag/drivers/ep93xx.c
@@ -55,7 +55,7 @@ struct adapter_driver ep93xx_adapter_driver = {
 	.jtag_ops = &ep93xx_interface,
 };
 
-static struct bitbang_interface ep93xx_bitbang = {
+static const struct bitbang_interface ep93xx_bitbang = {
 	.read = ep93xx_read,
 	.write = ep93xx_write,
 	.blink = NULL,
diff --git a/src/jtag/drivers/imx_gpio.c b/src/jtag/drivers/imx_gpio.c
index d44b1278c..7aefbeb8a 100644
--- a/src/jtag/drivers/imx_gpio.c
+++ b/src/jtag/drivers/imx_gpio.c
@@ -82,7 +82,7 @@ static int imx_gpio_swd_write(int swclk, int swdio);
 static int imx_gpio_init(void);
 static int imx_gpio_quit(void);
 
-static struct bitbang_interface imx_gpio_bitbang = {
+static const struct bitbang_interface imx_gpio_bitbang = {
 	.read = imx_gpio_read,
 	.write = imx_gpio_write,
 	.swdio_read = imx_gpio_swdio_read,
diff --git a/src/jtag/drivers/linuxgpiod.c b/src/jtag/drivers/linuxgpiod.c
index fa14e42d6..5ffbf4d2f 100644
--- a/src/jtag/drivers/linuxgpiod.c
+++ b/src/jtag/drivers/linuxgpiod.c
@@ -191,7 +191,7 @@ static int linuxgpiod_blink(bool on)
 	return retval;
 }
 
-static struct bitbang_interface linuxgpiod_bitbang = {
+static const struct bitbang_interface linuxgpiod_bitbang = {
 	.read = linuxgpiod_read,
 	.write = linuxgpiod_write,
 	.swdio_read = linuxgpiod_swdio_read,
diff --git a/src/jtag/drivers/parport.c b/src/jtag/drivers/parport.c
index bdd338895..f3478db51 100644
--- a/src/jtag/drivers/parport.c
+++ b/src/jtag/drivers/parport.c
@@ -255,7 +255,7 @@ static int parport_get_giveio_access(void)
 }
 #endif
 
-static struct bitbang_interface parport_bitbang = {
+static const struct bitbang_interface parport_bitbang = {
 	.read = &parport_read,
 	.write = &parport_write,
 	.blink = &parport_led,
diff --git a/src/jtag/drivers/remote_bitbang.c b/src/jtag/drivers/remote_bitbang.c
index 91a8532b7..037c1f27f 100644
--- a/src/jtag/drivers/remote_bitbang.c
+++ b/src/jtag/drivers/remote_bitbang.c
@@ -278,7 +278,7 @@ static int remote_bitbang_swd_write(int swclk, int swdio)
 	return remote_bitbang_queue(c, NO_FLUSH);
 }
 
-static struct bitbang_interface remote_bitbang_bitbang = {
+static const struct bitbang_interface remote_bitbang_bitbang = {
 	.buf_size = sizeof(remote_bitbang_recv_buf) - 1,
 	.sample = &remote_bitbang_sample,
 	.read_sample = &remote_bitbang_read_sample,
diff --git a/src/jtag/drivers/sysfsgpio.c b/src/jtag/drivers/sysfsgpio.c
index a5f5fd3ac..c47754bd1 100644
--- a/src/jtag/drivers/sysfsgpio.c
+++ b/src/jtag/drivers/sysfsgpio.c
@@ -565,7 +565,7 @@ struct adapter_driver sysfsgpio_adapter_driver = {
 	.swd_ops = &bitbang_swd,
 };
 
-static struct bitbang_interface sysfsgpio_bitbang = {
+static const struct bitbang_interface sysfsgpio_bitbang = {
 	.read = sysfsgpio_read,
 	.write = sysfsgpio_write,
 	.swdio_read = sysfsgpio_swdio_read,

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/am335xgpio.c     | 2 +-
 src/jtag/drivers/at91rm9200.c     | 2 +-
 src/jtag/drivers/bitbang.c        | 2 +-
 src/jtag/drivers/bitbang.h        | 2 +-
 src/jtag/drivers/dummy.c          | 2 +-
 src/jtag/drivers/ep93xx.c         | 2 +-
 src/jtag/drivers/imx_gpio.c       | 2 +-
 src/jtag/drivers/linuxgpiod.c     | 2 +-
 src/jtag/drivers/parport.c        | 2 +-
 src/jtag/drivers/remote_bitbang.c | 2 +-
 src/jtag/drivers/sysfsgpio.c      | 2 +-
 11 files changed, 11 insertions(+), 11 deletions(-)


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- Log -----------------------------------------------------------------
commit d4b3b4ea82ba6d34b050a1cc068e0b105533e2f2
Author: Tomas Vanek <va...@fb...>
Date:   Tue Dec 10 13:48:53 2024 +0100

    target: free private_config if target initialisation fails
    
    Fixes private_config memory leak when xx_deinit_target() is not called
    
    Signed-off-by: Tomas Vanek <va...@fb...>
    Change-Id: Ie7cce7f24af24695e7d2c1cd1882474c6863b80d
    Reviewed-on: https://review.openocd.org/c/openocd/+/8642
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>

diff --git a/src/target/target.c b/src/target/target.c
index 6c474899a..1fc8baf2c 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -5848,6 +5848,7 @@ static int target_create(struct jim_getopt_info *goi)
 		free(target->gdb_port_override);
 		free(target->trace_info);
 		free(target->type);
+		free(target->private_config);
 		free(target);
 		return e;
 	}
@@ -5865,6 +5866,7 @@ static int target_create(struct jim_getopt_info *goi)
 		free(target->gdb_port_override);
 		free(target->trace_info);
 		free(target->type);
+		free(target->private_config);
 		free(target);
 		return JIM_ERR;
 	}
@@ -5878,6 +5880,7 @@ static int target_create(struct jim_getopt_info *goi)
 			free(target->gdb_port_override);
 			free(target->trace_info);
 			free(target->type);
+			free(target->private_config);
 			free(target);
 			return JIM_ERR;
 		}

-----------------------------------------------------------------------

Summary of changes:
 src/target/target.c | 3 +++
 1 file changed, 3 insertions(+)


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commit cf115c1e2b670ea8b4606cde0c9b5db735a08742
Author: Tomas Vanek <va...@fb...>
Date:   Tue Dec 10 08:53:49 2024 +0100

    drivers/cmsis_dap_usb_bulk: allow waiting for bulk write
    
    No driver directly working with the USB hardware needs additional
    time to complete the write op, they always return transfer complete
    status immediately after submitting the transfer.
    
    Although there is implemented correct waiting path in cmsis_dap_usb_write()
    it was marked by error logs to catch any suspicious behaviour during
    debugging of asynchronous libusb transfers.
    
    However there are drivers which need waiting to finish write op:
    at least usbipd-win, IP tunnelled USB driver, was reported
    to flood the log with the related errors.
    
    Change LOG_ERROR to LOG_DEBUG_IO in the code waiting to finish write op.
    
    Reported-by: Quentis Ghyll <que...@gm...>
    Signed-off-by: Tomas Vanek <va...@fb...>
    Change-Id: Iedf2c96d851f22e694efaf13a2d6a2a408cee1ad
    Reviewed-on: https://review.openocd.org/c/openocd/+/8640
    Tested-by: jenkins

diff --git a/src/jtag/drivers/cmsis_dap_usb_bulk.c b/src/jtag/drivers/cmsis_dap_usb_bulk.c
index 50d4a9f8d..8fbcb029d 100644
--- a/src/jtag/drivers/cmsis_dap_usb_bulk.c
+++ b/src/jtag/drivers/cmsis_dap_usb_bulk.c
@@ -532,7 +532,7 @@ static int cmsis_dap_usb_write(struct cmsis_dap *dap, int txlen, int timeout_ms)
 	tr = &dap->bdata->command_transfers[dap->pending_fifo_put_idx];
 
 	if (tr->status == CMSIS_DAP_TRANSFER_PENDING) {
-		LOG_ERROR("busy command USB transfer at %u", dap->pending_fifo_put_idx);
+		LOG_DEBUG_IO("busy command USB transfer at %u", dap->pending_fifo_put_idx);
 		struct timeval tv = {
 			.tv_sec = timeout_ms / 1000,
 			.tv_usec = timeout_ms % 1000 * 1000
@@ -547,7 +547,7 @@ static int cmsis_dap_usb_write(struct cmsis_dap *dap, int txlen, int timeout_ms)
 		tr->status = CMSIS_DAP_TRANSFER_IDLE;
 	}
 	if (tr->status == CMSIS_DAP_TRANSFER_COMPLETED) {
-		LOG_ERROR("USB write: late transfer competed");
+		LOG_DEBUG_IO("USB write: late transfer competed");
 		tr->status = CMSIS_DAP_TRANSFER_IDLE;
 	}
 	if (tr->status != CMSIS_DAP_TRANSFER_IDLE) {

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/cmsis_dap_usb_bulk.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


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- Log -----------------------------------------------------------------
commit 23796efa38019515e6338bb4beaa793a537a00e0
Author: Tomas Vanek <va...@fb...>
Date:   Tue Dec 10 08:26:48 2024 +0100

    drivers/cmsis_dap: use blocking flag instead of wait timeout
    
    CMSIS-DAP bulk backend read op used two timeouts: transfer timeout
    used in libusb_fill_bulk_transfer() and wait timeout used optionally
    in libusb_handle_events_timeout_completed().
    
    The real usage is limited to two cases only:
    1) blocking read: the same timeout is used for both transfer
    and wait
    2) non-blocking read: transfer timeout is used in
    libusb_fill_bulk_transfer(),
    libusb_handle_events_timeout_completed() is called with zero timeout.
    
    Use blocking flag as read op parameter to distinguish between
    these two cases.
    
    See also [1]
    
    Link: [1] 8596: jtag: cmsis_dap: include helper/time_support.h | https://review.openocd.org/c/openocd/+/8596
    Signed-off-by: Tomas Vanek <va...@fb...>
    Change-Id: Ia755f17dc72bb9ce8e02065fee6a064f8eec6661
    Reviewed-on: https://review.openocd.org/c/openocd/+/8639
    Tested-by: jenkins
    Reviewed-by: Paul Fertser <fer...@gm...>

diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c
index 2f776cb38..e9fd93ad1 100644
--- a/src/jtag/drivers/cmsis_dap.c
+++ b/src/jtag/drivers/cmsis_dap.c
@@ -225,12 +225,6 @@ struct pending_scan_result {
 	unsigned int buffer_offset;
 };
 
-/* Read mode */
-enum cmsis_dap_blocking {
-	CMSIS_DAP_NON_BLOCKING,
-	CMSIS_DAP_BLOCKING
-};
-
 /* Each block in FIFO can contain up to pending_queue_len transfers */
 static unsigned int pending_queue_len;
 static unsigned int tfer_max_command_size;
@@ -321,7 +315,7 @@ static void cmsis_dap_flush_read(struct cmsis_dap *dap)
 	 * USB close/open so we need to flush up to 64 old packets
 	 * to be sure all buffers are empty */
 	for (i = 0; i < 64; i++) {
-		int retval = dap->backend->read(dap, 10, NULL);
+		int retval = dap->backend->read(dap, 10, CMSIS_DAP_BLOCKING);
 		if (retval == ERROR_TIMEOUT_REACHED)
 			break;
 	}
@@ -338,7 +332,7 @@ static int cmsis_dap_xfer(struct cmsis_dap *dap, int txlen)
 	if (dap->pending_fifo_block_count) {
 		LOG_ERROR("pending %u blocks, flushing", dap->pending_fifo_block_count);
 		while (dap->pending_fifo_block_count) {
-			dap->backend->read(dap, 10, NULL);
+			dap->backend->read(dap, 10, CMSIS_DAP_BLOCKING);
 			dap->pending_fifo_block_count--;
 		}
 		dap->pending_fifo_put_idx = 0;
@@ -351,7 +345,7 @@ static int cmsis_dap_xfer(struct cmsis_dap *dap, int txlen)
 		return retval;
 
 	/* get reply */
-	retval = dap->backend->read(dap, LIBUSB_TIMEOUT_MS, NULL);
+	retval = dap->backend->read(dap, LIBUSB_TIMEOUT_MS, CMSIS_DAP_BLOCKING);
 	if (retval < 0)
 		return retval;
 
@@ -885,7 +879,7 @@ static void cmsis_dap_swd_read_process(struct cmsis_dap *dap, enum cmsis_dap_blo
 
 	if (queued_retval != ERROR_OK) {
 		/* keep reading blocks until the pipeline is empty */
-		retval = dap->backend->read(dap, 10, NULL);
+		retval = dap->backend->read(dap, 10, CMSIS_DAP_BLOCKING);
 		if (retval == ERROR_TIMEOUT_REACHED || retval == 0) {
 			/* timeout means that we flushed the pipeline,
 			 * we can safely discard remaining pending requests */
@@ -896,11 +890,7 @@ static void cmsis_dap_swd_read_process(struct cmsis_dap *dap, enum cmsis_dap_blo
 	}
 
 	/* get reply */
-	struct timeval tv = {
-		.tv_sec = 0,
-		.tv_usec = 0
-	};
-	retval = dap->backend->read(dap, LIBUSB_TIMEOUT_MS, blocking ? NULL : &tv);
+	retval = dap->backend->read(dap, LIBUSB_TIMEOUT_MS, blocking);
 	bool timeout = (retval == ERROR_TIMEOUT_REACHED || retval == 0);
 	if (timeout && blocking == CMSIS_DAP_NON_BLOCKING)
 		return;
diff --git a/src/jtag/drivers/cmsis_dap.h b/src/jtag/drivers/cmsis_dap.h
index e47697d1f..aded0e54a 100644
--- a/src/jtag/drivers/cmsis_dap.h
+++ b/src/jtag/drivers/cmsis_dap.h
@@ -58,12 +58,18 @@ struct cmsis_dap {
 	bool trace_enabled;
 };
 
+/* Read mode */
+enum cmsis_dap_blocking {
+	CMSIS_DAP_NON_BLOCKING,
+	CMSIS_DAP_BLOCKING
+};
+
 struct cmsis_dap_backend {
 	const char *name;
 	int (*open)(struct cmsis_dap *dap, uint16_t vids[], uint16_t pids[], const char *serial);
 	void (*close)(struct cmsis_dap *dap);
 	int (*read)(struct cmsis_dap *dap, int transfer_timeout_ms,
-			    struct timeval *wait_timeout);
+				enum cmsis_dap_blocking blocking);
 	int (*write)(struct cmsis_dap *dap, int len, int timeout_ms);
 	int (*packet_buffer_alloc)(struct cmsis_dap *dap, unsigned int pkt_sz);
 	void (*packet_buffer_free)(struct cmsis_dap *dap);
diff --git a/src/jtag/drivers/cmsis_dap_usb_bulk.c b/src/jtag/drivers/cmsis_dap_usb_bulk.c
index 8d0cb544d..50d4a9f8d 100644
--- a/src/jtag/drivers/cmsis_dap_usb_bulk.c
+++ b/src/jtag/drivers/cmsis_dap_usb_bulk.c
@@ -441,7 +441,7 @@ static void LIBUSB_CALL cmsis_dap_usb_callback(struct libusb_transfer *transfer)
 }
 
 static int cmsis_dap_usb_read(struct cmsis_dap *dap, int transfer_timeout_ms,
-							  struct timeval *wait_timeout)
+							  enum cmsis_dap_blocking blocking)
 {
 	int transferred = 0;
 	int err;
@@ -464,20 +464,23 @@ static int cmsis_dap_usb_read(struct cmsis_dap *dap, int transfer_timeout_ms,
 		}
 	}
 
-	struct timeval tv = {
-		.tv_sec = transfer_timeout_ms / 1000,
-		.tv_usec = transfer_timeout_ms % 1000 * 1000
-	};
+	struct timeval tv;
+	if (blocking == CMSIS_DAP_NON_BLOCKING) {
+		tv.tv_sec = 0;
+		tv.tv_usec = 0;
+	} else {
+		tv.tv_sec = transfer_timeout_ms / 1000;
+		tv.tv_usec = transfer_timeout_ms % 1000 * 1000;
+	}
 
 	while (tr->status == CMSIS_DAP_TRANSFER_PENDING) {
-		err = libusb_handle_events_timeout_completed(dap->bdata->usb_ctx,
-												 wait_timeout ? wait_timeout : &tv,
+		err = libusb_handle_events_timeout_completed(dap->bdata->usb_ctx, &tv,
 												 &tr->status);
 		if (err) {
 			LOG_ERROR("error handling USB events: %s", libusb_strerror(err));
 			return ERROR_FAIL;
 		}
-		if (wait_timeout)
+		if (tv.tv_sec == 0 && tv.tv_usec == 0)
 			break;
 	}
 
diff --git a/src/jtag/drivers/cmsis_dap_usb_hid.c b/src/jtag/drivers/cmsis_dap_usb_hid.c
index aeec685b9..a4058ec80 100644
--- a/src/jtag/drivers/cmsis_dap_usb_hid.c
+++ b/src/jtag/drivers/cmsis_dap_usb_hid.c
@@ -206,17 +206,13 @@ static void cmsis_dap_hid_close(struct cmsis_dap *dap)
 }
 
 static int cmsis_dap_hid_read(struct cmsis_dap *dap, int transfer_timeout_ms,
-							  struct timeval *wait_timeout)
+							  enum cmsis_dap_blocking blocking)
 {
-	int timeout_ms;
-	if (wait_timeout)
-		timeout_ms = wait_timeout->tv_usec / 1000 + wait_timeout->tv_sec * 1000;
-	else
-		timeout_ms = transfer_timeout_ms;
+	int wait_ms = (blocking == CMSIS_DAP_NON_BLOCKING) ? 0 : transfer_timeout_ms;
 
 	int retval = hid_read_timeout(dap->bdata->dev_handle,
 								  dap->packet_buffer, dap->packet_buffer_size,
-								  timeout_ms);
+								  wait_ms);
 	if (retval == 0) {
 		return ERROR_TIMEOUT_REACHED;
 	} else if (retval == -1) {

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/cmsis_dap.c          | 20 +++++---------------
 src/jtag/drivers/cmsis_dap.h          |  8 +++++++-
 src/jtag/drivers/cmsis_dap_usb_bulk.c | 19 +++++++++++--------
 src/jtag/drivers/cmsis_dap_usb_hid.c  | 10 +++-------
 4 files changed, 26 insertions(+), 31 deletions(-)


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- Log -----------------------------------------------------------------
commit 250ab1008b4d5f9520066df28170c42fc8b40af4
Author: David (Pololu) <dev...@po...>
Date:   Wed Dec 18 13:49:00 2024 -0800

    flash/stm32l4x: add STM32C071xx support
    
    I successfully programmed a NUCLEO-C071RB with these changes.
    
    Change-Id: Ib57a77fa18f8a0e8c882e2250d6111c588d76887
    Signed-off-by: David (Pololu) <dev...@po...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8525
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 594f7a7f0..7c5f84c55 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -8001,7 +8001,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
 @end deffn
 
 @deffn {Flash Driver} {stm32l4x}
-All members of the STM32 G0, G4, L4, L4+, L5, U0, U5, WB and WL
+All members of the STM32 C0, G0, G4, L4, L4+, L5, U0, U5, WB and WL
 microcontroller families from STMicroelectronics include internal flash
 and use ARM Cortex-M0+, M4 and M33 cores.
 The driver automatically recognizes a number of these chips using
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index d2e8f3050..3062fca72 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -303,6 +303,10 @@ static const struct stm32l4_rev stm32c03xx_revs[] = {
 	{ 0x1000, "A" }, { 0x1001, "Z" },
 };
 
+static const struct stm32l4_rev stm32c071xx_revs[] = {
+	{ 0x1001, "Z" },
+};
+
 static const struct stm32l4_rev stm32g05_g06xx_revs[] = {
 	{ 0x1000, "A" },
 };
@@ -442,6 +446,18 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .otp_base              = 0x1FFF7000,
 	  .otp_size              = 1024,
 	},
+	{
+	  .id                    = DEVID_STM32C071XX,
+	  .revs                  = stm32c071xx_revs,
+	  .num_revs              = ARRAY_SIZE(stm32c071xx_revs),
+	  .device_str            = "STM32C071xx",
+	  .max_flash_size_kb     = 128,
+	  .flags                 = F_NONE,
+	  .flash_regs_base       = 0x40022000,
+	  .fsize_addr            = 0x1FFF75A0,
+	  .otp_base              = 0x1FFF7000,
+	  .otp_size              = 1024,
+	},
 	{
 	  .id                    = DEVID_STM32U53_U54XX,
 	  .revs                  = stm32u53_u54xx_revs,
@@ -1989,6 +2005,7 @@ static int stm32l4_probe(struct flash_bank *bank)
 	case DEVID_STM32L43_L44XX:
 	case DEVID_STM32C01XX:
 	case DEVID_STM32C03XX:
+	case DEVID_STM32C071XX:
 	case DEVID_STM32G05_G06XX:
 	case DEVID_STM32G07_G08XX:
 	case DEVID_STM32U031XX:
diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h
index b1e8f9870..f152c9f30 100644
--- a/src/flash/nor/stm32l4x.h
+++ b/src/flash/nor/stm32l4x.h
@@ -108,6 +108,7 @@
 #define DEVID_STM32U57_U58XX	0x482
 #define DEVID_STM32U073_U083XX	0x489
 #define DEVID_STM32WBA5X		0x492
+#define DEVID_STM32C071XX		0x493
 #define DEVID_STM32WB1XX		0x494
 #define DEVID_STM32WB5XX		0x495
 #define DEVID_STM32WB3XX		0x496
diff --git a/tcl/board/st_nucleo_c0.cfg b/tcl/board/st_nucleo_c0.cfg
new file mode 100644
index 000000000..7d0767592
--- /dev/null
+++ b/tcl/board/st_nucleo_c0.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32c0x.cfg]
+
+reset_config srst_only

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi                                   |  2 +-
 src/flash/nor/stm32l4x.c                           | 17 +++++++++++++++++
 src/flash/nor/stm32l4x.h                           |  1 +
 tcl/board/{st_nucleo_wb55.cfg => st_nucleo_c0.cfg} |  6 +-----
 4 files changed, 20 insertions(+), 6 deletions(-)
 copy tcl/board/{st_nucleo_wb55.cfg => st_nucleo_c0.cfg} (58%)


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- Log -----------------------------------------------------------------
commit 5233312ea5725dfcb8b8e0baee103017531ba54f
Author: Antonio Borneo <bor...@gm...>
Date:   Tue Dec 31 10:38:28 2024 +0100

    configure: fix dependency of bitbang from dummy adapter
    
    The commit bb2fc63357a0 ("configure.ac: enable the Dummy adapter
    by default") breaks the building dependency between bitbang code
    and dummy adapter.
    
    Fix it.
    
    Change-Id: I47587ef61d6b57b2547f6c2600d8404cad87f584
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reported-by: Jonathan Forrest <jon...@gm...>
    Fixes: bb2fc63357a0 ("configure.ac: enable the Dummy adapter by default")
    BugLink: https://sourceforge.net/p/openocd/tickets/446/
    Reviewed-on: https://review.openocd.org/c/openocd/+/8682
    Reviewed-by: Andrzej Sierżęga <as...@gm...>
    Tested-by: jenkins
    Reviewed-by: Andy <and...@gm...>

diff --git a/configure.ac b/configure.ac
index b353bced7..db47dcba6 100644
--- a/configure.ac
+++ b/configure.ac
@@ -513,7 +513,7 @@ AS_IF([test "x$build_dmem" = "xyes"], [
   AC_DEFINE([BUILD_DMEM], [0], [0 if you don't want to debug via Direct Mem.])
 ])
 
-AS_IF([test "x$ADAPTER_VAR([dummy])" = "xyes"], [
+AS_IF([test "x$ADAPTER_VAR([dummy])" != "xno"], [
   build_bitbang=yes
 ])
 

-----------------------------------------------------------------------

Summary of changes:
 configure.ac | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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- Log -----------------------------------------------------------------
commit 4f2744d0fede64504ae4e9f9913eebc55c915d9a
Author: Marc Schink <de...@za...>
Date:   Wed Oct 23 12:56:37 2024 +0200

    target/arc: Use LOG_TARGET_xxx()
    
    Use LOG_TARGET_xxx() for log messages as it is used for other targets.
    
    While at it, rework the log messages, for example by removing spaces
    or punctuation marks at the end of the message.
    
    Change-Id: I3dd4314d354b5628144f98325540926981778616
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8665
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/arc.c b/src/target/arc.c
index 28ce93947..5c08c5664 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -61,7 +61,7 @@ static int arc_single_step_core(struct target *target);
 void arc_reg_data_type_add(struct target *target,
 		struct arc_reg_data_type *data_type)
 {
-	LOG_DEBUG("Adding %s reg_data_type", data_type->data_type.id);
+	LOG_TARGET_DEBUG(target, "Adding %s reg_data_type", data_type->data_type.id);
 	struct arc_common *arc = target_to_arc(target);
 	assert(arc);
 
@@ -104,7 +104,7 @@ static int arc_reset_caches_states(struct target *target)
 {
 	struct arc_common *arc = target_to_arc(target);
 
-	LOG_DEBUG("Resetting internal variables of caches states");
+	LOG_TARGET_DEBUG(target, "Resetting internal variables of caches states");
 
 	/* Reset caches states. */
 	arc->dcache_flushed = false;
@@ -127,7 +127,7 @@ static int arc_init_arch_info(struct target *target, struct arc_common *arc,
 
 	/* The only allowed ir_length is 4 for ARC jtag. */
 	if (tap->ir_length != 4) {
-		LOG_ERROR("ARC jtag instruction length should be equal to 4");
+		LOG_TARGET_ERROR(target, "ARC jtag instruction length should be equal to 4");
 		return ERROR_FAIL;
 	}
 
@@ -146,7 +146,7 @@ static int arc_init_arch_info(struct target *target, struct arc_common *arc,
 		sizeof(*std_types));
 
 	if (!std_types) {
-		LOG_ERROR("Unable to allocate memory");
+		LOG_TARGET_ERROR(target, "Unable to allocate memory");
 		return ERROR_FAIL;
 	}
 
@@ -205,7 +205,7 @@ int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
 	}
 	arc->num_regs += 1;
 
-	LOG_DEBUG(
+	LOG_TARGET_DEBUG(target,
 			"added register {name=%s, num=0x%" PRIx32 ", type=%s%s%s%s}",
 			arc_reg->name, arc_reg->arch_num, arc_reg->data_type->id,
 			arc_reg->is_core ? ", core" : "",  arc_reg->is_bcr ? ", bcr" : "",
@@ -227,7 +227,7 @@ static int arc_get_register(struct reg *reg)
 	uint32_t value;
 
 	if (reg->valid) {
-		LOG_DEBUG("Get register (cached) gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
+		LOG_TARGET_DEBUG(target, "Get register (cached) gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
 				reg->number, desc->name, target_buffer_get_u32(target, reg->value));
 		return ERROR_OK;
 	}
@@ -235,7 +235,7 @@ static int arc_get_register(struct reg *reg)
 	if (desc->is_core) {
 		/* Accessing to R61/R62 registers causes Jtag hang */
 		if (desc->arch_num == ARC_R61 || desc->arch_num == ARC_R62) {
-			LOG_ERROR("It is forbidden to read core registers 61 and 62.");
+			LOG_TARGET_ERROR(target, "It is forbidden to read core registers 61 and 62");
 			return ERROR_FAIL;
 		}
 		CHECK_RETVAL(arc_jtag_read_core_reg_one(&arc->jtag_info, desc->arch_num,
@@ -255,7 +255,7 @@ static int arc_get_register(struct reg *reg)
 
 	reg->dirty = false;
 
-	LOG_DEBUG("Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
+	LOG_TARGET_DEBUG(target, "Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
 			reg->number, desc->name, value);
 
 
@@ -276,12 +276,12 @@ static int arc_set_register(struct reg *reg, uint8_t *buf)
 	/* Accessing to R61/R62 registers causes Jtag hang */
 	if (desc->is_core && (desc->arch_num == ARC_R61 ||
 			desc->arch_num == ARC_R62)) {
-		LOG_ERROR("It is forbidden to write core registers 61 and 62.");
+		LOG_TARGET_ERROR(target, "It is forbidden to write core registers 61 and 62");
 		return ERROR_FAIL;
 	}
 	target_buffer_set_u32(target, reg->value, value);
 
-	LOG_DEBUG("Set register gdb_num=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
+	LOG_TARGET_DEBUG(target, "Set register gdb_num=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
 			reg->number, desc->name, value);
 
 	reg->valid = true;
@@ -355,7 +355,7 @@ static int arc_build_reg_cache(struct target *target)
 	struct reg *reg_list = calloc(num_regs, sizeof(*reg_list));
 
 	if (!cache || !reg_list)  {
-		LOG_ERROR("Not enough memory");
+		LOG_TARGET_ERROR(target, "Not enough memory");
 		goto fail;
 	}
 
@@ -368,14 +368,14 @@ static int arc_build_reg_cache(struct target *target)
 	(*cache_p) = cache;
 
 	if (list_empty(&arc->core_reg_descriptions)) {
-		LOG_ERROR("No core registers were defined");
+		LOG_TARGET_ERROR(target, "No core registers were defined");
 		goto fail;
 	}
 
 	list_for_each_entry(reg_desc, &arc->core_reg_descriptions, list) {
 		CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, i));
 
-		LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
+		LOG_TARGET_DEBUG(target, "reg n=%3li name=%3s group=%s feature=%s", i,
 			reg_list[i].name, reg_list[i].group,
 			reg_list[i].feature->name);
 
@@ -383,27 +383,27 @@ static int arc_build_reg_cache(struct target *target)
 	}
 
 	if (list_empty(&arc->aux_reg_descriptions)) {
-		LOG_ERROR("No aux registers were defined");
+		LOG_TARGET_ERROR(target, "No aux registers were defined");
 		goto fail;
 	}
 
 	list_for_each_entry(reg_desc, &arc->aux_reg_descriptions, list) {
 		 CHECK_RETVAL(arc_init_reg(target, &reg_list[i],  reg_desc, i));
 
-		LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
+		LOG_TARGET_DEBUG(target, "reg n=%3li name=%3s group=%s feature=%s", i,
 			reg_list[i].name, reg_list[i].group,
 			reg_list[i].feature->name);
 
 		/* PC and DEBUG are essential so we search for them. */
 		if (!strcmp("pc", reg_desc->name)) {
 			if (arc->pc_index_in_cache != ULONG_MAX) {
-				LOG_ERROR("Double definition of PC in configuration");
+				LOG_TARGET_ERROR(target, "Double definition of PC in configuration");
 				goto fail;
 			}
 			arc->pc_index_in_cache = i;
 		} else if (!strcmp("debug", reg_desc->name)) {
 			if (arc->debug_index_in_cache != ULONG_MAX) {
-				LOG_ERROR("Double definition of DEBUG in configuration");
+				LOG_TARGET_ERROR(target, "Double definition of DEBUG in configuration");
 				goto fail;
 			}
 			arc->debug_index_in_cache = i;
@@ -413,7 +413,7 @@ static int arc_build_reg_cache(struct target *target)
 
 	if (arc->pc_index_in_cache == ULONG_MAX
 			|| arc->debug_index_in_cache == ULONG_MAX) {
-		LOG_ERROR("`pc' and `debug' registers must be present in target description.");
+		LOG_TARGET_ERROR(target, "`pc' and `debug' registers must be present in target description");
 		goto fail;
 	}
 
@@ -446,7 +446,7 @@ static int arc_build_bcr_reg_cache(struct target *target)
 	unsigned long gdb_regnum = arc->core_and_aux_cache->num_regs;
 
 	if (!cache || !reg_list)  {
-		LOG_ERROR("Unable to allocate memory");
+		LOG_TARGET_ERROR(target, "Unable to allocate memory");
 		goto fail;
 	}
 
@@ -459,7 +459,7 @@ static int arc_build_bcr_reg_cache(struct target *target)
 	(*cache_p) = cache;
 
 	if (list_empty(&arc->bcr_reg_descriptions)) {
-		LOG_ERROR("No BCR registers are defined");
+		LOG_TARGET_ERROR(target, "No BCR registers are defined");
 		goto fail;
 	}
 
@@ -469,7 +469,7 @@ static int arc_build_bcr_reg_cache(struct target *target)
 		 * not real register. */
 		reg_list[i].exist = true;
 
-		LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
+		LOG_TARGET_DEBUG(target, "reg n=%3li name=%3s group=%s feature=%s", i,
 			reg_list[i].name, reg_list[i].group,
 			reg_list[i].feature->name);
 		i += 1;
@@ -501,7 +501,7 @@ static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
 	*reg_list = calloc(*reg_list_size, sizeof(struct reg *));
 
 	if (!*reg_list) {
-		LOG_ERROR("Unable to allocate memory");
+		LOG_TARGET_ERROR(target, "Unable to allocate memory");
 		return ERROR_FAIL;
 	}
 
@@ -521,7 +521,7 @@ static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
 			reg_cache = reg_cache->next;
 		}
 		assert(i == arc->num_regs);
-		LOG_DEBUG("REG_CLASS_ALL: number of regs=%i", *reg_list_size);
+		LOG_TARGET_DEBUG(target, "REG_CLASS_ALL: number of regs=%i", *reg_list_size);
 	} else {
 		unsigned long i = 0;
 		unsigned long gdb_reg_number = 0;
@@ -539,7 +539,7 @@ static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
 			reg_cache = reg_cache->next;
 		}
 		*reg_list_size = i;
-		LOG_DEBUG("REG_CLASS_GENERAL: number of regs=%i", *reg_list_size);
+		LOG_TARGET_DEBUG(target, "REG_CLASS_GENERAL: number of regs=%i", *reg_list_size);
 	}
 
 	return ERROR_OK;
@@ -551,13 +551,13 @@ int arc_reg_get_field(struct target *target, const char *reg_name,
 {
 	struct reg_data_type_struct_field *field;
 
-	LOG_DEBUG("getting register field (reg_name=%s, field_name=%s)", reg_name, field_name);
+	LOG_TARGET_DEBUG(target, "getting register field (reg_name=%s, field_name=%s)", reg_name, field_name);
 
 	/* Get register */
 	struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
 
 	if (!reg) {
-		LOG_ERROR("Requested register `%s' doesn't exist.", reg_name);
+		LOG_TARGET_ERROR(target, "Requested register `%s' doesn't exist", reg_name);
 		return ERROR_ARC_REGISTER_NOT_FOUND;
 	}
 
@@ -597,7 +597,7 @@ int arc_reg_get_field(struct target *target, const char *reg_name,
 static int arc_get_register_value(struct target *target, const char *reg_name,
 		uint32_t *value_ptr)
 {
-	LOG_DEBUG("reg_name=%s", reg_name);
+	LOG_TARGET_DEBUG(target, "reg_name=%s", reg_name);
 
 	struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
 
@@ -615,10 +615,10 @@ static int arc_get_register_value(struct target *target, const char *reg_name,
 static int arc_set_register_value(struct target *target, const char *reg_name,
 		uint32_t value)
 {
-	LOG_DEBUG("reg_name=%s value=0x%08" PRIx32, reg_name, value);
+	LOG_TARGET_DEBUG(target, "reg_name=%s value=0x%08" PRIx32, reg_name, value);
 
 	if (!(target && reg_name)) {
-		LOG_ERROR("Arguments cannot be NULL.");
+		LOG_TARGET_ERROR(target, "Arguments cannot be NULL");
 		return ERROR_FAIL;
 	}
 
@@ -655,7 +655,7 @@ static int arc_configure_dccm(struct target  *target)
 		if (dccm_build_size0 == 0xF)
 			dccm_size <<= dccm_build_size1;
 		arc->dccm_end = arc->dccm_start + dccm_size;
-		LOG_DEBUG("DCCM detected start=0x%" PRIx32 " end=0x%" PRIx32,
+		LOG_TARGET_DEBUG(target, "DCCM detected start=0x%" PRIx32 " end=0x%" PRIx32,
 				arc->dccm_start, arc->dccm_end);
 
 	}
@@ -687,7 +687,7 @@ static int arc_configure_iccm(struct target  *target)
 		/* iccm0 start is located in highest 4 bits of aux_iccm */
 		arc->iccm0_start = aux_iccm & 0xF0000000;
 		arc->iccm0_end = arc->iccm0_start + iccm0_size;
-		LOG_DEBUG("ICCM0 detected start=0x%" PRIx32 " end=0x%" PRIx32,
+		LOG_TARGET_DEBUG(target, "ICCM0 detected start=0x%" PRIx32 " end=0x%" PRIx32,
 				arc->iccm0_start, arc->iccm0_end);
 	}
 
@@ -707,7 +707,7 @@ static int arc_configure_iccm(struct target  *target)
 			iccm1_size <<= iccm_build_size11;
 		arc->iccm1_start = aux_iccm & 0x0F000000;
 		arc->iccm1_end = arc->iccm1_start + iccm1_size;
-		LOG_DEBUG("ICCM1 detected start=0x%" PRIx32 " end=0x%" PRIx32,
+		LOG_TARGET_DEBUG(target, "ICCM1 detected start=0x%" PRIx32 " end=0x%" PRIx32,
 				arc->iccm1_start, arc->iccm1_end);
 	}
 	return ERROR_OK;
@@ -716,7 +716,7 @@ static int arc_configure_iccm(struct target  *target)
 /* Configure some core features, depending on BCRs. */
 static int arc_configure(struct target *target)
 {
-	LOG_DEBUG("Configuring ARC ICCM and DCCM");
+	LOG_TARGET_DEBUG(target, "Configuring ARC ICCM and DCCM");
 
 	/* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */
 	if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true) &&
@@ -770,9 +770,9 @@ static int arc_exit_debug(struct target *target)
 	CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 
 	if (debug_level >= LOG_LVL_DEBUG) {
-		LOG_DEBUG("core stopped (halted) debug-reg: 0x%08" PRIx32, value);
+		LOG_TARGET_DEBUG(target, "core stopped (halted) debug-reg: 0x%08" PRIx32, value);
 		CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
-		LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
+		LOG_TARGET_DEBUG(target, "core STATUS32: 0x%08" PRIx32, value);
 	}
 
 	return ERROR_OK;
@@ -783,19 +783,19 @@ static int arc_halt(struct target *target)
 	uint32_t value, irq_state;
 	struct arc_common *arc = target_to_arc(target);
 
-	LOG_DEBUG("target->state: %s", target_state_name(target));
+	LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target));
 
 	if (target->state == TARGET_HALTED) {
-		LOG_DEBUG("target was already halted");
+		LOG_TARGET_DEBUG(target, "target was already halted");
 		return ERROR_OK;
 	}
 
 	if (target->state == TARGET_UNKNOWN)
-		LOG_WARNING("target was in unknown state when halt was requested");
+		LOG_TARGET_WARNING(target, "target was in unknown state when halt was requested");
 
 	if (target->state == TARGET_RESET) {
 		if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
-			LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
+			LOG_TARGET_ERROR(target, "can't request a halt while in reset if nSRST pulls nTRST");
 			return ERROR_TARGET_FAILURE;
 		} else {
 			target->debug_reason = DBG_REASON_DBGRQ;
@@ -825,9 +825,9 @@ static int arc_halt(struct target *target)
 
 	/* some more debug information */
 	if (debug_level >= LOG_LVL_DEBUG) {
-		LOG_DEBUG("core stopped (halted) DEGUB-REG: 0x%08" PRIx32, value);
+		LOG_TARGET_DEBUG(target, "core stopped (halted) DEGUB-REG: 0x%08" PRIx32, value);
 		CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
-		LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
+		LOG_TARGET_DEBUG(target, "core STATUS32: 0x%08" PRIx32, value);
 	}
 
 	return ERROR_OK;
@@ -846,7 +846,7 @@ static int arc_save_context(struct target *target)
 	struct arc_common *arc = target_to_arc(target);
 	struct reg *reg_list = arc->core_and_aux_cache->reg_list;
 
-	LOG_DEBUG("Saving aux and core registers values");
+	LOG_TARGET_DEBUG(target, "Saving aux and core registers values");
 	assert(reg_list);
 
 	/* It is assumed that there is at least one AUX register in the list, for
@@ -865,7 +865,7 @@ static int arc_save_context(struct target *target)
 	unsigned int aux_cnt = 0;
 
 	if (!core_values || !core_addrs || !aux_values || !aux_addrs)  {
-		LOG_ERROR("Unable to allocate memory");
+		LOG_TARGET_ERROR(target, "Unable to allocate memory");
 		retval = ERROR_FAIL;
 		goto exit;
 	}
@@ -893,7 +893,7 @@ static int arc_save_context(struct target *target)
 	if (core_cnt > 0) {
 		retval = arc_jtag_read_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("Attempt to read core registers failed.");
+			LOG_TARGET_ERROR(target, "Attempt to read core registers failed");
 			retval = ERROR_FAIL;
 			goto exit;
 		}
@@ -901,7 +901,7 @@ static int arc_save_context(struct target *target)
 	if (aux_cnt > 0) {
 		retval = arc_jtag_read_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("Attempt to read aux registers failed.");
+			LOG_TARGET_ERROR(target, "Attempt to read aux registers failed");
 			retval = ERROR_FAIL;
 			goto exit;
 		}
@@ -916,7 +916,7 @@ static int arc_save_context(struct target *target)
 			target_buffer_set_u32(target, reg->value, core_values[core_cnt]);
 			reg->valid = true;
 			reg->dirty = false;
-			LOG_DEBUG("Get core register regnum=%u, name=%s, value=0x%08" PRIx32,
+			LOG_TARGET_DEBUG(target, "Get core register regnum=%u, name=%s, value=0x%08" PRIx32,
 				i, arc_reg->name, core_values[core_cnt]);
 			core_cnt++;
 		}
@@ -931,7 +931,7 @@ static int arc_save_context(struct target *target)
 			target_buffer_set_u32(target, reg->value, aux_values[aux_cnt]);
 			reg->valid = true;
 			reg->dirty = false;
-			LOG_DEBUG("Get aux register regnum=%u, name=%s, value=0x%08" PRIx32,
+			LOG_TARGET_DEBUG(target, "Get aux register regnum=%u, name=%s, value=0x%08" PRIx32,
 				i, arc_reg->name, aux_values[aux_cnt]);
 			aux_cnt++;
 		}
@@ -1009,14 +1009,14 @@ static int arc_examine_debug_reason(struct target *target)
 
 		if (actionpoint) {
 			if (!actionpoint->used)
-				LOG_WARNING("Target halted by an unused actionpoint.");
+				LOG_TARGET_WARNING(target, "Target halted by an unused actionpoint");
 
 			if (actionpoint->type == ARC_AP_BREAKPOINT)
 				target->debug_reason = DBG_REASON_BREAKPOINT;
 			else if (actionpoint->type == ARC_AP_WATCHPOINT)
 				target->debug_reason = DBG_REASON_WATCHPOINT;
 			else
-				LOG_WARNING("Unknown type of actionpoint.");
+				LOG_TARGET_WARNING(target, "Unknown type of actionpoint");
 		}
 	}
 
@@ -1046,7 +1046,7 @@ static int arc_poll(struct target *target)
 	/* check for processor halted */
 	if (status & ARC_JTAG_STAT_RU) {
 		if (target->state != TARGET_RUNNING) {
-			LOG_WARNING("target is still running!");
+			LOG_TARGET_WARNING(target, "target is still running");
 			target->state = TARGET_RUNNING;
 		}
 		return ERROR_OK;
@@ -1057,21 +1057,21 @@ static int arc_poll(struct target *target)
 	if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) {
 		CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
 		if (value & AUX_STATUS32_REG_HALT_BIT) {
-			LOG_DEBUG("ARC core in halt or reset state.");
+			LOG_TARGET_DEBUG(target, "ARC core in halt or reset state");
 			/* Save context if target was not in reset state */
 			if (target->state == TARGET_RUNNING)
 				CHECK_RETVAL(arc_debug_entry(target));
 			target->state = TARGET_HALTED;
 			CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 		} else {
-		LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
+			LOG_TARGET_DEBUG(target, "Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
 						"target is still running");
 		}
 
 	} else if (target->state == TARGET_DEBUG_RUNNING) {
 
 		target->state = TARGET_HALTED;
-		LOG_DEBUG("ARC core is in debug running mode");
+		LOG_TARGET_DEBUG(target, "ARC core is in debug running mode");
 
 		CHECK_RETVAL(arc_debug_entry(target));
 
@@ -1087,7 +1087,7 @@ static int arc_assert_reset(struct target *target)
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
 	bool srst_asserted = false;
 
-	LOG_DEBUG("target->state: %s", target_state_name(target));
+	LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target));
 
 	if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
 		/* allow scripts to override the reset event */
@@ -1101,7 +1101,7 @@ static int arc_assert_reset(struct target *target)
 		if (target->state == TARGET_HALTED && !target->reset_halt) {
 			/* Resume the target and continue from the current
 			 * PC register value. */
-			LOG_DEBUG("Starting CPU execution after reset");
+			LOG_TARGET_DEBUG(target, "Starting CPU execution after reset");
 			CHECK_RETVAL(target_resume(target, 1, 0, 0, 0));
 		}
 		target->state = TARGET_RESET;
@@ -1138,7 +1138,7 @@ static int arc_assert_reset(struct target *target)
 
 static int arc_deassert_reset(struct target *target)
 {
-	LOG_DEBUG("target->state: %s", target_state_name(target));
+	LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target));
 
 	/* deassert reset lines */
 	jtag_add_reset(0, 0);
@@ -1155,7 +1155,7 @@ static int arc_arch_state(struct target *target)
 
 	CHECK_RETVAL(arc_get_register_value(target, "pc", &pc_value));
 
-	LOG_DEBUG("target state: %s;  PC at: 0x%08" PRIx32,
+	LOG_TARGET_DEBUG(target, "target state: %s;  PC at: 0x%08" PRIx32,
 		target_state_name(target),
 		pc_value);
 
@@ -1174,7 +1174,7 @@ static int arc_restore_context(struct target *target)
 	struct arc_common *arc = target_to_arc(target);
 	struct reg *reg_list = arc->core_and_aux_cache->reg_list;
 
-	LOG_DEBUG("Restoring registers values");
+	LOG_TARGET_DEBUG(target, "Restoring registers values");
 	assert(reg_list);
 
 	const uint32_t core_regs_size = arc->num_core_regs  * sizeof(uint32_t);
@@ -1187,7 +1187,7 @@ static int arc_restore_context(struct target *target)
 	unsigned int aux_cnt = 0;
 
 	if (!core_values || !core_addrs || !aux_values || !aux_addrs)  {
-		LOG_ERROR("Unable to allocate memory");
+		LOG_TARGET_ERROR(target, "Unable to allocate memory");
 		retval = ERROR_FAIL;
 		goto exit;
 	}
@@ -1201,7 +1201,7 @@ static int arc_restore_context(struct target *target)
 		struct reg *reg = &(reg_list[i]);
 		struct arc_reg_desc *arc_reg = reg->arch_info;
 		if (reg->valid && reg->exist && reg->dirty) {
-			LOG_DEBUG("Will write regnum=%u", i);
+			LOG_TARGET_DEBUG(target, "Will write regnum=%u", i);
 			core_addrs[core_cnt] = arc_reg->arch_num;
 			core_values[core_cnt] = target_buffer_get_u32(target, reg->value);
 			core_cnt += 1;
@@ -1212,7 +1212,7 @@ static int arc_restore_context(struct target *target)
 		struct reg *reg = &(reg_list[arc->num_core_regs + i]);
 		struct arc_reg_desc *arc_reg = reg->arch_info;
 		if (reg->valid && reg->exist && reg->dirty) {
-			LOG_DEBUG("Will write regnum=%lu", arc->num_core_regs + i);
+			LOG_TARGET_DEBUG(target, "Will write regnum=%lu", arc->num_core_regs + i);
 			aux_addrs[aux_cnt] = arc_reg->arch_num;
 			aux_values[aux_cnt] = target_buffer_get_u32(target, reg->value);
 			aux_cnt += 1;
@@ -1224,7 +1224,7 @@ static int arc_restore_context(struct target *target)
 	if (core_cnt > 0) {
 		retval = arc_jtag_write_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("Attempt to write to core registers failed.");
+			LOG_TARGET_ERROR(target, "Attempt to write to core registers failed");
 			retval = ERROR_FAIL;
 			goto exit;
 		}
@@ -1233,7 +1233,7 @@ static int arc_restore_context(struct target *target)
 	if (aux_cnt > 0) {
 		retval = arc_jtag_write_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("Attempt to write to aux registers failed.");
+			LOG_TARGET_ERROR(target, "Attempt to write to aux registers failed");
 			retval = ERROR_FAIL;
 			goto exit;
 		}
@@ -1260,12 +1260,12 @@ static int arc_enable_interrupts(struct target *target, int enable)
 		/* enable interrupts */
 		value |= SET_CORE_ENABLE_INTERRUPTS;
 		CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
-		LOG_DEBUG("interrupts enabled");
+		LOG_TARGET_DEBUG(target, "interrupts enabled");
 	} else {
 		/* disable interrupts */
 		value &= ~SET_CORE_ENABLE_INTERRUPTS;
 		CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
-		LOG_DEBUG("interrupts disabled");
+		LOG_TARGET_DEBUG(target, "interrupts disabled");
 	}
 
 	return ERROR_OK;
@@ -1279,7 +1279,7 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
 	uint32_t value;
 	struct reg *pc = &arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache];
 
-	LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints:%i,"
+	LOG_TARGET_DEBUG(target, "current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints:%i,"
 		" debug_execution:%i", current, address, handle_breakpoints, debug_execution);
 
 	/* We need to reset ARC cache variables so caches
@@ -1304,7 +1304,7 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
 		target_buffer_set_u32(target, pc->value, address);
 		pc->dirty = true;
 		pc->valid = true;
-		LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address);
+		LOG_TARGET_DEBUG(target, "Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address);
 	}
 
 	if (!current)
@@ -1314,13 +1314,13 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
 
 	CHECK_RETVAL(arc_restore_context(target));
 
-	LOG_DEBUG("Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i",
+	LOG_TARGET_DEBUG(target, "Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i",
 		resume_pc, pc->dirty, pc->valid);
 
 	/* check if GDB tells to set our PC where to continue from */
 	if (pc->valid && resume_pc == target_buffer_get_u32(target, pc->value)) {
 		value = target_buffer_get_u32(target, pc->value);
-		LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32, value);
+		LOG_TARGET_DEBUG(target, "resume Core (when start-core) with PC @:0x%08" PRIx32, value);
 		CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_PC_REG, value));
 	}
 
@@ -1329,7 +1329,7 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
 		/* Single step past breakpoint at current address */
 		struct breakpoint *breakpoint = breakpoint_find(target, resume_pc);
 		if (breakpoint) {
-			LOG_DEBUG("skipping past breakpoint at 0x%08" TARGET_PRIxADDR,
+			LOG_TARGET_DEBUG(target, "skipping past breakpoint at 0x%08" TARGET_PRIxADDR,
 				breakpoint->address);
 			CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint));
 			CHECK_RETVAL(arc_single_step_core(target));
@@ -1350,7 +1350,7 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
 	CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
 	value &= ~SET_CORE_HALT_BIT;        /* clear the HALT bit */
 	CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
-	LOG_DEBUG("Core started to run");
+	LOG_TARGET_DEBUG(target, "Core started to run");
 
 	/* registers are now invalid */
 	register_cache_invalidate(arc->core_and_aux_cache);
@@ -1358,11 +1358,11 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
 	if (!debug_execution) {
 		target->state = TARGET_RUNNING;
 		CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
-		LOG_DEBUG("target resumed at 0x%08" PRIx32, resume_pc);
+		LOG_TARGET_DEBUG(target, "target resumed at 0x%08" PRIx32, resume_pc);
 	} else {
 		target->state = TARGET_DEBUG_RUNNING;
 		CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED));
-		LOG_DEBUG("target debug resumed at 0x%08" PRIx32, resume_pc);
+		LOG_TARGET_DEBUG(target, "target debug resumed at 0x%08" PRIx32, resume_pc);
 	}
 
 	return ERROR_OK;
@@ -1386,7 +1386,7 @@ static void arc_deinit_target(struct target *target)
 {
 	struct arc_common *arc = target_to_arc(target);
 
-	LOG_DEBUG("deinitialization of target");
+	LOG_TARGET_DEBUG(target, "deinitialization of target");
 	if (arc->core_aux_cache_built)
 		arc_free_reg_cache(arc->core_and_aux_cache);
 	if (arc->bcr_cache_built)
@@ -1431,11 +1431,11 @@ static int arc_target_create(struct target *target, Jim_Interp *interp)
 	struct arc_common *arc = calloc(1, sizeof(*arc));
 
 	if (!arc) {
-		LOG_ERROR("Unable to allocate memory");
+		LOG_TARGET_ERROR(target, "Unable to allocate memory");
 		return ERROR_FAIL;
 	}
 
-	LOG_DEBUG("Entering");
+	LOG_TARGET_DEBUG(target, "Entering");
 	CHECK_RETVAL(arc_init_arch_info(target, arc, target->tap));
 
 	return ERROR_OK;
@@ -1452,11 +1452,11 @@ static int arc_write_instruction_u32(struct target *target, uint32_t address,
 {
 	uint8_t value_buf[4];
 	if (!target_was_examined(target)) {
-		LOG_ERROR("Target not examined yet");
+		LOG_TARGET_ERROR(target, "Target not examined yet");
 		return ERROR_FAIL;
 	}
 
-	LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
+	LOG_TARGET_DEBUG(target, "Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
 		instr);
 
 	if (target->endianness == TARGET_LITTLE_ENDIAN)
@@ -1480,7 +1480,7 @@ static int arc_read_instruction_u32(struct target *target, uint32_t address,
 	uint8_t value_buf[4];
 
 	if (!target_was_examined(target)) {
-		LOG_ERROR("Target not examined yet");
+		LOG_TARGET_ERROR(target, "Target not examined yet");
 		return ERROR_FAIL;
 	}
 
@@ -1492,7 +1492,7 @@ static int arc_read_instruction_u32(struct target *target, uint32_t address,
 	else
 		*value = be_to_h_u32(value_buf);
 
-	LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
+	LOG_TARGET_DEBUG(target, "Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
 		*value);
 
 	return ERROR_OK;
@@ -1513,7 +1513,7 @@ static int arc_configure_actionpoint(struct target *target, uint32_t ap_num,
 	if (control_tt != AP_AC_TT_DISABLE) {
 
 		if (arc->actionpoints_num_avail < 1) {
-			LOG_ERROR("No free actionpoints, maximum amount is %u",
+			LOG_TARGET_ERROR(target, "No free actionpoints, maximum amount is %u",
 					arc->actionpoints_num);
 			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 		}
@@ -1547,12 +1547,12 @@ static int arc_set_breakpoint(struct target *target,
 		struct breakpoint *breakpoint)
 {
 	if (breakpoint->is_set) {
-		LOG_WARNING("breakpoint already set");
+		LOG_TARGET_WARNING(target, "breakpoint already set");
 		return ERROR_OK;
 	}
 
 	if (breakpoint->type == BKPT_SOFT) {
-		LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
+		LOG_TARGET_DEBUG(target, "bpid: %" PRIu32, breakpoint->unique_id);
 
 		if (breakpoint->length == 4) {
 			uint32_t verify = 0xffffffff;
@@ -1566,7 +1566,7 @@ static int arc_set_breakpoint(struct target *target,
 			CHECK_RETVAL(arc_read_instruction_u32(target, breakpoint->address, &verify));
 
 			if (verify != ARC_SDBBP_32) {
-				LOG_ERROR("Unable to set 32bit breakpoint at address @0x%" TARGET_PRIxADDR
+				LOG_TARGET_ERROR(target, "Unable to set 32bit breakpoint at address @0x%" TARGET_PRIxADDR
 						" - check that memory is read/writable", breakpoint->address);
 				return ERROR_FAIL;
 			}
@@ -1579,12 +1579,12 @@ static int arc_set_breakpoint(struct target *target,
 
 			CHECK_RETVAL(target_read_u16(target, breakpoint->address, &verify));
 			if (verify != ARC_SDBBP_16) {
-				LOG_ERROR("Unable to set 16bit breakpoint at address @0x%" TARGET_PRIxADDR
+				LOG_TARGET_ERROR(target, "Unable to set 16bit breakpoint at address @0x%" TARGET_PRIxADDR
 						" - check that memory is read/writable", breakpoint->address);
 				return ERROR_FAIL;
 			}
 		} else {
-			LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
+			LOG_TARGET_ERROR(target, "Invalid breakpoint length: target supports only 2 or 4");
 			return ERROR_COMMAND_ARGUMENT_INVALID;
 		}
 
@@ -1600,7 +1600,7 @@ static int arc_set_breakpoint(struct target *target,
 		}
 
 		if (bp_num >= arc->actionpoints_num) {
-			LOG_ERROR("No free actionpoints, maximum amount is %u",
+			LOG_TARGET_ERROR(target, "No free actionpoints, maximum amount is %u",
 					arc->actionpoints_num);
 			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 		}
@@ -1614,12 +1614,12 @@ static int arc_set_breakpoint(struct target *target,
 			ap_list[bp_num].bp_value = breakpoint->address;
 			ap_list[bp_num].type = ARC_AP_BREAKPOINT;
 
-			LOG_DEBUG("bpid: %" PRIu32 ", bp_num %u bp_value 0x%" PRIx32,
+			LOG_TARGET_DEBUG(target, "bpid: %" PRIu32 ", bp_num %u bp_value 0x%" PRIx32,
 					breakpoint->unique_id, bp_num, ap_list[bp_num].bp_value);
 		}
 
 	} else {
-		LOG_DEBUG("ERROR: setting unknown breakpoint type");
+		LOG_TARGET_ERROR(target, "setting unknown breakpoint type");
 		return ERROR_FAIL;
 	}
 
@@ -1632,13 +1632,13 @@ static int arc_unset_breakpoint(struct target *target,
 	int retval = ERROR_OK;
 
 	if (!breakpoint->is_set) {
-		LOG_WARNING("breakpoint not set");
+		LOG_TARGET_WARNING(target, "breakpoint not set");
 		return ERROR_OK;
 	}
 
 	if (breakpoint->type == BKPT_SOFT) {
 		/* restore original instruction (kept in target endianness) */
-		LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
+		LOG_TARGET_DEBUG(target, "bpid: %" PRIu32, breakpoint->unique_id);
 		if (breakpoint->length == 4) {
 			uint32_t current_instr;
 
@@ -1651,7 +1651,7 @@ static int arc_unset_breakpoint(struct target *target,
 				if (retval != ERROR_OK)
 					return retval;
 			} else {
-				LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
+				LOG_TARGET_WARNING(target, "Software breakpoint @0x%" TARGET_PRIxADDR
 					" has been overwritten outside of debugger."
 					"Expected: @0x%x, got: @0x%" PRIx32,
 					breakpoint->address, ARC_SDBBP_32, current_instr);
@@ -1667,24 +1667,24 @@ static int arc_unset_breakpoint(struct target *target,
 				if (retval != ERROR_OK)
 					return retval;
 			} else {
-				LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
+				LOG_TARGET_WARNING(target, "Software breakpoint @0x%" TARGET_PRIxADDR
 					" has been overwritten outside of debugger. "
 					"Expected: 0x%04x, got: 0x%04" PRIx16,
 					breakpoint->address, ARC_SDBBP_16, current_instr);
 			}
 		} else {
-			LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
+			LOG_TARGET_ERROR(target, "Invalid breakpoint length: target supports only 2 or 4");
 			return ERROR_COMMAND_ARGUMENT_INVALID;
 		}
 		breakpoint->is_set = false;
 
-	}	else if (breakpoint->type == BKPT_HARD) {
+	} else if (breakpoint->type == BKPT_HARD) {
 		struct arc_common *arc = target_to_arc(target);
 		struct arc_actionpoint *ap_list = arc->actionpoints_list;
 		unsigned int bp_num = breakpoint->number;
 
 		if (bp_num >= arc->actionpoints_num) {
-			LOG_DEBUG("Invalid actionpoint ID: %u in breakpoint: %" PRIu32,
+			LOG_TARGET_DEBUG(target, "Invalid actionpoint ID: %u in breakpoint: %" PRIu32,
 					  bp_num, breakpoint->unique_id);
 			return ERROR_OK;
 		}
@@ -1697,12 +1697,12 @@ static int arc_unset_breakpoint(struct target *target,
 			ap_list[bp_num].used = 0;
 			ap_list[bp_num].bp_value = 0;
 
-			LOG_DEBUG("bpid: %" PRIu32 " - released actionpoint ID: %u",
+			LOG_TARGET_DEBUG(target, "bpid: %" PRIu32 " - released actionpoint ID: %u",
 					breakpoint->unique_id, bp_num);
 		}
 	} else {
-			LOG_DEBUG("ERROR: unsetting unknown breakpoint type");
-			return ERROR_FAIL;
+		LOG_TARGET_ERROR(target, "unsetting unknown breakpoint type");
+		return ERROR_FAIL;
 	}
 
 	return retval;
@@ -1775,7 +1775,7 @@ static void arc_reset_actionpoints(struct target *target)
 
 int arc_set_actionpoints_num(struct target *target, uint32_t ap_num)
 {
-	LOG_DEBUG("target=%s actionpoints=%" PRIu32, target_name(target), ap_num);
+	LOG_TARGET_DEBUG(target, "actionpoints=%" PRIu32, ap_num);
 	struct arc_common *arc = target_to_arc(target);
 
 	/* Make sure that there are no enabled actionpoints in target. */
@@ -1790,7 +1790,7 @@ int arc_set_actionpoints_num(struct target *target, uint32_t ap_num)
 	arc->actionpoints_list = calloc(ap_num, sizeof(struct arc_actionpoint));
 
 	if (!arc->actionpoints_list) {
-		LOG_ERROR("Unable to allocate memory");
+		LOG_TARGET_ERROR(target, "Unable to allocate memory");
 		return ERROR_FAIL;
 	}
 	return ERROR_OK;
@@ -1813,7 +1813,7 @@ int arc_add_auxreg_actionpoint(struct target *target,
 		ap_num++;
 
 	if (ap_num >= arc->actionpoints_num) {
-		LOG_ERROR("No actionpoint free, maximum amount is %u",
+		LOG_TARGET_ERROR(target, "No actionpoint free, maximum amount is %u",
 				arc->actionpoints_num);
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
@@ -1858,7 +1858,7 @@ int arc_remove_auxreg_actionpoint(struct target *target, uint32_t auxreg_addr)
 			ap_list[ap_num].bp_value = 0;
 		}
 	} else {
-		LOG_ERROR("Register actionpoint not found");
+		LOG_TARGET_ERROR(target, "Register actionpoint not found");
 	}
 	return retval;
 }
@@ -1872,7 +1872,7 @@ static int arc_set_watchpoint(struct target *target,
 	struct arc_actionpoint *ap_list = arc->actionpoints_list;
 
 	if (watchpoint->is_set) {
-		LOG_WARNING("watchpoint already set");
+		LOG_TARGET_WARNING(target, "watchpoint already set");
 		return ERROR_OK;
 	}
 
@@ -1882,13 +1882,13 @@ static int arc_set_watchpoint(struct target *target,
 	}
 
 	if (wp_num >= arc->actionpoints_num) {
-		LOG_ERROR("No free actionpoints, maximum amount is %u",
+		LOG_TARGET_ERROR(target, "No free actionpoints, maximum amount is %u",
 				arc->actionpoints_num);
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
 	if (watchpoint->length != 4) {
-		LOG_ERROR("Only watchpoints of length 4 are supported");
+		LOG_TARGET_ERROR(target, "Only watchpoints of length 4 are supported");
 		return ERROR_TARGET_UNALIGNED_ACCESS;
 	}
 
@@ -1904,7 +1904,7 @@ static int arc_set_watchpoint(struct target *target,
 			enable = AP_AC_TT_READWRITE;
 			break;
 		default:
-			LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
+			LOG_TARGET_ERROR(target, "BUG: watchpoint->rw neither read, write nor access");
 			return ERROR_FAIL;
 	}
 
@@ -1917,7 +1917,7 @@ static int arc_set_watchpoint(struct target *target,
 		ap_list[wp_num].bp_value = watchpoint->address;
 		ap_list[wp_num].type = ARC_AP_WATCHPOINT;
 
-		LOG_DEBUG("wpid: %" PRIu32 ", wp_num %u wp_value 0x%" PRIx32,
+		LOG_TARGET_DEBUG(target, "wpid: %" PRIu32 ", wp_num %u wp_value 0x%" PRIx32,
 				watchpoint->unique_id, wp_num, ap_list[wp_num].bp_value);
 	}
 
@@ -1932,13 +1932,13 @@ static int arc_unset_watchpoint(struct target *target,
 	struct arc_actionpoint *ap_list = arc->actionpoints_list;
 
 	if (!watchpoint->is_set) {
-		LOG_WARNING("watchpoint not set");
+		LOG_TARGET_WARNING(target, "watchpoint not set");
 		return ERROR_OK;
 	}
 
 	unsigned int wp_num = watchpoint->number;
 	if (wp_num >= arc->actionpoints_num) {
-		LOG_DEBUG("Invalid actionpoint ID: %u in watchpoint: %" PRIu32,
+		LOG_TARGET_DEBUG(target, "Invalid actionpoint ID: %u in watchpoint: %" PRIu32,
 				wp_num, watchpoint->unique_id);
 		return ERROR_OK;
 	}
@@ -1951,7 +1951,7 @@ static int arc_unset_watchpoint(struct target *target,
 		ap_list[wp_num].used = 0;
 		ap_list[wp_num].bp_value = 0;
 
-		LOG_DEBUG("wpid: %" PRIu32 " - releasing actionpoint ID: %u",
+		LOG_TARGET_DEBUG(target, "wpid: %" PRIu32 " - releasing actionpoint ID: %u",
 				watchpoint->unique_id, wp_num);
 	}
 
@@ -2009,18 +2009,18 @@ static int arc_hit_watchpoint(struct target *target, struct watchpoint **hit_wat
 
 	if (actionpoint) {
 		if (!actionpoint->used)
-			LOG_WARNING("Target halted by unused actionpoint.");
+			LOG_TARGET_WARNING(target, "Target halted by unused actionpoint");
 
 		/* If this check fails - that is some sort of an error in OpenOCD. */
 		if (actionpoint->type != ARC_AP_WATCHPOINT)
-			LOG_WARNING("Target halted by breakpoint, but is treated as a watchpoint.");
+			LOG_TARGET_WARNING(target, "Target halted by breakpoint, but is treated as a watchpoint");
 
 		for (struct watchpoint *watchpoint = target->watchpoints;
 				watchpoint;
 				watchpoint = watchpoint->next) {
 			if (actionpoint->bp_value == watchpoint->address) {
 				*hit_watchpoint = watchpoint;
-				LOG_DEBUG("Hit watchpoint, wpid: %" PRIu32 ", watchpoint num: %u",
+				LOG_TARGET_DEBUG(target, "Hit watchpoint, wpid: %" PRIu32 ", watchpoint num: %u",
 							watchpoint->unique_id, watchpoint->number);
 				return ERROR_OK;
 			}
@@ -2045,7 +2045,7 @@ static int arc_config_step(struct target *target, int enable_step)
 		value &= ~SET_CORE_AE_BIT; /* clear the AE bit */
 		CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG,
 			value));
-		LOG_DEBUG(" [status32:0x%08" PRIx32 "]", value);
+		LOG_TARGET_DEBUG(target, " [status32:0x%08" PRIx32 "]", value);
 
 		/* Doing read-modify-write, because DEBUG might contain manually set
 		 * bits like UB or ED, which should be preserved.  */
@@ -2054,7 +2054,7 @@ static int arc_config_step(struct target *target, int enable_step)
 		value |= SET_CORE_SINGLE_INSTR_STEP; /* set the IS bit */
 		CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
 			value));
-		LOG_DEBUG("core debug step mode enabled [debug-reg:0x%08" PRIx32 "]", value);
+		LOG_TARGET_DEBUG(target, "core debug step mode enabled [debug-reg:0x%08" PRIx32 "]", value);
 
 	} else {	/* disable core debug step mode */
 		CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
@@ -2062,7 +2062,7 @@ static int arc_config_step(struct target *target, int enable_step)
 		value &= ~SET_CORE_SINGLE_INSTR_STEP; /* clear the IS bit */
 		CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
 			value));
-		LOG_DEBUG("core debug step mode disabled");
+		LOG_TARGET_DEBUG(target, "core debug step mode disabled");
 	}
 
 	return ERROR_OK;
@@ -2104,7 +2104,7 @@ static int arc_step(struct target *target, int current, target_addr_t address,
 		pc->valid = true;
 	}
 
-	LOG_DEBUG("Target steps one instruction from PC=0x%" PRIx32,
+	LOG_TARGET_DEBUG(target, "Target steps one instruction from PC=0x%" PRIx32,
 		buf_get_u32(pc->value, 0, 32));
 
 	/* the front-end may request us not to handle breakpoints */
@@ -2136,7 +2136,7 @@ static int arc_step(struct target *target, int current, target_addr_t address,
 	if (breakpoint)
 		CHECK_RETVAL(arc_set_breakpoint(target, breakpoint));
 
-	LOG_DEBUG("target stepped ");
+	LOG_TARGET_DEBUG(target, "target stepped");
 
 	target->state = TARGET_HALTED;
 
@@ -2159,7 +2159,7 @@ static int arc_icache_invalidate(struct target *target)
 	if (!arc->has_icache || arc->icache_invalidated)
 	    return ERROR_OK;
 
-	LOG_DEBUG("Invalidating I$.");
+	LOG_TARGET_DEBUG(target, "Invalidating I$");
 
 	value = IC_IVIC_INVALIDATE;	/* invalidate I$ */
 	CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_IC_IVIC_REG, value));
@@ -2179,7 +2179,7 @@ static int arc_dcache_invalidate(struct target *target)
 	if (!arc->has_dcache || arc->dcache_invalidated)
 	    return ERROR_OK;
 
-	LOG_DEBUG("Invalidating D$.");
+	LOG_TARGET_DEBUG(target, "Invalidating D$");
 
 	CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &value));
 	dc_ctrl_value = value;
@@ -2208,7 +2208,7 @@ static int arc_l2cache_invalidate(struct target *target)
 	if (!arc->has_l2cache || arc->l2cache_invalidated)
 	    return ERROR_OK;
 
-	LOG_DEBUG("Invalidating L2$.");
+	LOG_TARGET_DEBUG(target, "Invalidating L2$");
 
 	CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
 	slc_ctrl_value = value;
@@ -2221,7 +2221,7 @@ static int arc_l2cache_invalidate(struct target *target)
 
 	/* Wait until invalidate operation ends */
 	do {
-	    LOG_DEBUG("Waiting for invalidation end.");
+	    LOG_TARGET_DEBUG(target, "Waiting for invalidation end");
 	    CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
 	} while (value & L2_CTRL_BS);
 
@@ -2259,7 +2259,7 @@ static int arc_dcache_flush(struct target *target)
 	if (!arc->has_dcache || arc->dcache_flushed)
 	    return ERROR_OK;
 
-	LOG_DEBUG("Flushing D$.");
+	LOG_TARGET_DEBUG(target, "Flushing D$");
 
 	/* Store current value of DC_CTRL */
 	CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &dc_ctrl_value));
@@ -2295,14 +2295,14 @@ static int arc_l2cache_flush(struct target *target)
 	if (!arc->has_l2cache || arc->l2cache_flushed)
 	    return ERROR_OK;
 
-	LOG_DEBUG("Flushing L2$.");
+	LOG_TARGET_DEBUG(target, "Flushing L2$");
 
 	/* Flush L2 cache */
 	CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_FLUSH, L2_FLUSH_FL));
 
 	/* Wait until flush operation ends */
 	do {
-	    LOG_DEBUG("Waiting for flushing end.");
+	    LOG_TARGET_DEBUG(target, "Waiting for flushing end");
 	    CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
 	} while (value & L2_CTRL_BS);
 
diff --git a/src/target/arc_mem.c b/src/target/arc_mem.c
index 3264b663b..3daed1cbb 100644
--- a/src/target/arc_mem.c
+++ b/src/target/arc_mem.c
@@ -35,7 +35,7 @@ static int arc_mem_write_block32(struct target *target, uint32_t addr,
 {
 	struct arc_common *arc = target_to_arc(target);
 
-	LOG_DEBUG("Write 4-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
+	LOG_TARGET_DEBUG(target, "Write 4-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
 			addr, count);
 
 	/* Check arguments */
@@ -66,7 +66,7 @@ static int arc_mem_write_block16(struct target *target, uint32_t addr,
 	uint8_t buffer_te[sizeof(uint32_t)];
 	uint8_t halfword_te[sizeof(uint16_t)];
 
-	LOG_DEBUG("Write 2-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
+	LOG_TARGET_DEBUG(target, "Write 2-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
 			addr, count);
 
 	/* Check arguments */
@@ -124,7 +124,7 @@ static int arc_mem_write_block8(struct target *target, uint32_t addr,
 	uint8_t buffer_te[sizeof(uint32_t)];
 
 
-	LOG_DEBUG("Write 1-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
+	LOG_TARGET_DEBUG(target, "Write 1-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
 			addr, count);
 
 	/* We will read data from memory, so we need to flush the cache. */
@@ -158,7 +158,7 @@ int arc_mem_write(struct target *target, target_addr_t address, uint32_t size,
 	int retval = ERROR_OK;
 	void *tunnel = NULL;
 
-	LOG_DEBUG("address: 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: %" PRIu32,
+	LOG_TARGET_DEBUG(target, "address: 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: %" PRIu32,
 		address, size, count);
 
 	if (target->state != TARGET_HALTED) {
@@ -182,7 +182,7 @@ int arc_mem_write(struct target *target, target_addr_t address, uint32_t size,
 		tunnel = calloc(1, count * size * sizeof(uint8_t));
 
 		if (!tunnel) {
-			LOG_ERROR("Unable to allocate memory");
+			LOG_TARGET_ERROR(target, "Unable to allocate memory");
 			return ERROR_FAIL;
 		}
 
@@ -220,7 +220,7 @@ static int arc_mem_read_block(struct target *target, target_addr_t addr,
 {
 	struct arc_common *arc = target_to_arc(target);
 
-	LOG_DEBUG("Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32
+	LOG_TARGET_DEBUG(target, "Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32
 			", count=%" PRIu32, addr, size, count);
 	assert(!(addr & 3));
 	assert(size == 4);
@@ -243,11 +243,11 @@ int arc_mem_read(struct target *target, target_addr_t address, uint32_t size,
 	uint32_t words_to_read, bytes_to_read;
 
 
-	LOG_DEBUG("Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32
+	LOG_TARGET_DEBUG(target, "Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32
 			", count=%" PRIu32, address, size, count);
 
 	if (target->state != TARGET_HALTED) {
-		LOG_WARNING("target not halted");
+		LOG_TARGET_WARNING(target, "target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
@@ -268,7 +268,7 @@ int arc_mem_read(struct target *target, target_addr_t address, uint32_t size,
 	tunnel_te = calloc(1, bytes_to_read);
 
 	if (!tunnel_he || !tunnel_te) {
-		LOG_ERROR("Unable to allocate memory");
+		LOG_TARGET_ERROR(target, "Unable to allocate memory");
 		free(tunnel_he);
 		free(tunnel_te);
 		return ERROR_FAIL;

commit a75feb0bfd34c4069834fce0089367aa57102f10
Author: Marc Schink <de...@za...>
Date:   Tue Oct 22 18:22:12 2024 +0200

    target/armv7m: Use LOG_TARGET_xxx()
    
    Use LOG_TARGET_xxx() to indicate which target the message belongs to.
    
    Change-Id: Ib1cd37fe6eca2ea42095d2d371116446a936e20a
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8664
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index a403b25a9..49a8a4bba 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -171,7 +171,7 @@ int armv7m_restore_context(struct target *target)
 	struct armv7m_common *armv7m = target_to_armv7m(target);
 	struct reg_cache *cache = armv7m->arm.core_cache;
 
-	LOG_DEBUG(" ");
+	LOG_TARGET_DEBUG(target, " ");
 
 	if (armv7m->pre_restore_context)
 		armv7m->pre_restore_context(target);
@@ -366,9 +366,9 @@ static int armv7m_read_core_reg(struct target *target, struct reg *r,
 			buf_set_u32(r->value + 4, 0, 32, reg_value);
 
 			uint64_t q = buf_get_u64(r->value, 0, 64);
-			LOG_DEBUG("read %s value 0x%016" PRIx64, r->name, q);
+			LOG_TARGET_DEBUG(target, "read %s value 0x%016" PRIx64, r->name, q);
 		} else {
-			LOG_DEBUG("read %s value 0x%08" PRIx32, r->name, reg_value);
+			LOG_TARGET_DEBUG(target, "read %s value 0x%08" PRIx32, r->name, reg_value);
 		}
 	}
 
@@ -436,9 +436,9 @@ static int armv7m_write_core_reg(struct target *target, struct reg *r,
 				goto out_error;
 
 			uint64_t q = buf_get_u64(value, 0, 64);
-			LOG_DEBUG("write %s value 0x%016" PRIx64, r->name, q);
+			LOG_TARGET_DEBUG(target, "write %s value 0x%016" PRIx64, r->name, q);
 		} else {
-			LOG_DEBUG("write %s value 0x%08" PRIx32, r->name, t);
+			LOG_TARGET_DEBUG(target, "write %s value 0x%08" PRIx32, r->name, t);
 		}
 	}
 
@@ -449,7 +449,7 @@ static int armv7m_write_core_reg(struct target *target, struct reg *r,
 
 out_error:
 	r->dirty = true;
-	LOG_ERROR("Error setting register %s", r->name);
+	LOG_TARGET_ERROR(target, "Error setting register %s", r->name);
 	return retval;
 }
 
@@ -520,7 +520,7 @@ int armv7m_start_algorithm(struct target *target,
 	 * at the exit point */
 
 	if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) {
-		LOG_ERROR("current target isn't an ARMV7M target");
+		LOG_TARGET_ERROR(target, "current target isn't an ARMV7M target");
 		return ERROR_TARGET_INVALID;
 	}
 
@@ -563,12 +563,12 @@ int armv7m_start_algorithm(struct target *target,
 /*		uint32_t regvalue; */
 
 		if (!reg) {
-			LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+			LOG_TARGET_ERROR(target, "BUG: register '%s' not found", reg_params[i].reg_name);
 			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 
 		if (reg->size != reg_params[i].size) {
-			LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
+			LOG_TARGET_ERROR(target, "BUG: register '%s' size doesn't match reg_params[i].size",
 				reg_params[i].reg_name);
 			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
@@ -600,10 +600,11 @@ int armv7m_start_algorithm(struct target *target,
 		/* we cannot set ARM_MODE_HANDLER, so use ARM_MODE_THREAD instead */
 		if (armv7m_algorithm_info->core_mode == ARM_MODE_HANDLER) {
 			armv7m_algorithm_info->core_mode = ARM_MODE_THREAD;
-			LOG_INFO("ARM_MODE_HANDLER not currently supported, using ARM_MODE_THREAD instead");
+			LOG_TARGET_INFO(target, "ARM_MODE_HANDLER not currently supported, using ARM_MODE_THREAD instead");
 		}
 
-		LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
+		LOG_TARGET_DEBUG(target, "setting core_mode: 0x%2.2x",
+			armv7m_algorithm_info->core_mode);
 		buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
 			0, 1, armv7m_algorithm_info->core_mode);
 		armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
@@ -633,7 +634,7 @@ int armv7m_wait_algorithm(struct target *target,
 	 * at the exit point */
 
 	if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) {
-		LOG_ERROR("current target isn't an ARMV7M target");
+		LOG_TARGET_ERROR(target, "current target isn't an ARMV7M target");
 		return ERROR_TARGET_INVALID;
 	}
 
@@ -653,7 +654,7 @@ int armv7m_wait_algorithm(struct target *target,
 		/* PC value has been cached in cortex_m_debug_entry() */
 		uint32_t pc = buf_get_u32(armv7m->arm.pc->value, 0, 32);
 		if (pc != exit_point) {
-			LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
+			LOG_TARGET_DEBUG(target, "failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
 					  pc, exit_point);
 			return ERROR_TARGET_ALGO_EXIT;
 		}
@@ -678,12 +679,13 @@ int armv7m_wait_algorithm(struct target *target,
 					false);
 
 			if (!reg) {
-				LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+				LOG_TARGET_ERROR(target, "BUG: register '%s' not found",
+					reg_params[i].reg_name);
 				return ERROR_COMMAND_SYNTAX_ERROR;
 			}
 
 			if (reg->size != reg_params[i].size) {
-				LOG_ERROR(
+				LOG_TARGET_ERROR(target,
 					"BUG: register '%s' size doesn't match reg_params[i].size",
 					reg_params[i].reg_name);
 				return ERROR_COMMAND_SYNTAX_ERROR;
@@ -701,7 +703,7 @@ int armv7m_wait_algorithm(struct target *target,
 		uint32_t regvalue;
 		regvalue = buf_get_u32(reg->value, 0, 32);
 		if (regvalue != armv7m_algorithm_info->context[i]) {
-			LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
+			LOG_TARGET_DEBUG(target, "restoring register %s with value 0x%8.8" PRIx32,
 					  reg->name, armv7m_algorithm_info->context[i]);
 			buf_set_u32(reg->value,
 				0, 32, armv7m_algorithm_info->context[i]);
@@ -712,7 +714,7 @@ int armv7m_wait_algorithm(struct target *target,
 
 	/* restore previous core mode */
 	if (armv7m_algorithm_info->core_mode != armv7m->arm.core_mode) {
-		LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
+		LOG_TARGET_DEBUG(target, "restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 		buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
 			0, 1, armv7m_algorithm_info->core_mode);
 		armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
@@ -738,9 +740,8 @@ int armv7m_arch_state(struct target *target)
 	ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
 	sp = buf_get_u32(arm->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
 
-	LOG_USER("[%s] halted due to %s, current mode: %s %s\n"
+	LOG_TARGET_USER(target, "halted due to %s, current mode: %s %s\n"
 		"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s%s",
-		target_name(target),
 		debug_reason_name(target),
 		arm_mode_name(arm->core_mode),
 		armv7m_exception_string(armv7m->exception_number),
@@ -807,13 +808,13 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
 			feature->name = armv7m_regs[i].feature;
 			reg_list[i].feature = feature;
 		} else
-			LOG_ERROR("unable to allocate feature list");
+			LOG_TARGET_ERROR(target, "unable to allocate feature list");
 
 		reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
 		if (reg_list[i].reg_data_type)
 			reg_list[i].reg_data_type->type = armv7m_regs[i].type;
 		else
-			LOG_ERROR("unable to allocate reg type list");
+			LOG_TARGET_ERROR(target, "unable to allocate reg type list");
 	}
 
 	arm->cpsr = reg_list + ARMV7M_XPSR;
@@ -918,7 +919,7 @@ int armv7m_checksum_memory(struct target *target,
 	if (retval == ERROR_OK)
 		*checksum = buf_get_u32(reg_params[0].value, 0, 32);
 	else
-		LOG_ERROR("error executing cortex_m crc algorithm");
+		LOG_TARGET_ERROR(target, "error executing cortex_m crc algorithm");
 
 	destroy_reg_param(&reg_params[0]);
 	destroy_reg_param(&reg_params[1]);
@@ -1003,7 +1004,7 @@ int armv7m_blank_check_memory(struct target *target,
 	uint32_t erased_word = erased_value | (erased_value << 8)
 			       | (erased_value << 16) | (erased_value << 24);
 
-	LOG_DEBUG("Starting erase check of %d blocks, parameters@"
+	LOG_TARGET_DEBUG(target, "Starting erase check of %d blocks, parameters@"
 		 TARGET_ADDR_FMT, blocks_to_check, erase_check_params->address);
 
 	armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
@@ -1044,7 +1045,8 @@ int armv7m_blank_check_memory(struct target *target,
 		blocks[i].result = result;
 	}
 	if (i && timed_out)
-		LOG_INFO("Slow CPU clock: %d blocks checked, %d remain. Continuing...", i, num_blocks-i);
+		LOG_TARGET_INFO(target, "Slow CPU clock: %d blocks checked, %d remain. Continuing...",
+			i, num_blocks - i);
 
 	retval = i;		/* return number of blocks really checked */
 
@@ -1085,7 +1087,7 @@ int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
 				r->dirty = true;
 				r->valid = true;
 				result = true;
-				LOG_DEBUG("Skipping over BKPT instruction");
+				LOG_TARGET_DEBUG(target, "Skipping over BKPT instruction");
 			}
 		}
 	}

-----------------------------------------------------------------------

Summary of changes:
 src/target/arc.c     | 252 +++++++++++++++++++++++++--------------------------
 src/target/arc_mem.c |  18 ++--
 src/target/armv7m.c  |  52 ++++++-----
 3 files changed, 162 insertions(+), 160 deletions(-)


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      from  4193322315660436983a16bdc5e18e7252e92a55 (commit)

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- Log -----------------------------------------------------------------
commit 78bc6f34d46cb1681143b548dab8c43cca622e43
Author: Marc Schink <de...@za...>
Date:   Tue Oct 22 18:24:11 2024 +0200

    target/esirisc: Use LOG_TARGET_xxx()
    
    Use LOG_TARGET_xxx() for log messages as it is used for other targets.
    
    Change-Id: Ia7e9629d89f2e6cb3f9c156e74ac1a02960f9373
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8663
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/esirisc.c b/src/target/esirisc.c
index 611141439..fc2d20105 100644
--- a/src/target/esirisc.c
+++ b/src/target/esirisc.c
@@ -160,11 +160,11 @@ static int esirisc_disable_interrupts(struct target *target)
 	uint32_t etc;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, &etc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Thread CSR: ETC");
 		return retval;
 	}
 
@@ -172,7 +172,7 @@ static int esirisc_disable_interrupts(struct target *target)
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, etc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Thread CSR: ETC");
 		return retval;
 	}
 
@@ -187,11 +187,11 @@ static int esirisc_enable_interrupts(struct target *target)
 	uint32_t etc;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, &etc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Thread CSR: ETC");
 		return retval;
 	}
 
@@ -199,7 +199,7 @@ static int esirisc_enable_interrupts(struct target *target)
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, etc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Thread CSR: ETC");
 		return retval;
 	}
 
@@ -212,12 +212,12 @@ static int esirisc_save_interrupts(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	int retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC,
 			&esirisc->etc_save);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Thread CSR: ETC");
 		return retval;
 	}
 
@@ -229,12 +229,12 @@ static int esirisc_restore_interrupts(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	int retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC,
 			esirisc->etc_save);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Thread CSR: ETC");
 		return retval;
 	}
 
@@ -247,12 +247,12 @@ static int esirisc_save_hwdc(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	int retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_HWDC,
 			&esirisc->hwdc_save);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Thread CSR: HWDC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Thread CSR: HWDC");
 		return retval;
 	}
 
@@ -265,12 +265,12 @@ static int esirisc_restore_hwdc(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	int retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_HWDC,
 			esirisc->hwdc_save);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: HWDC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: HWDC");
 		return retval;
 	}
 
@@ -281,7 +281,7 @@ static int esirisc_save_context(struct target *target)
 {
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	for (unsigned int i = 0; i < esirisc->reg_cache->num_regs; ++i) {
 		struct reg *reg = esirisc->reg_cache->reg_list + i;
@@ -298,7 +298,7 @@ static int esirisc_restore_context(struct target *target)
 {
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	for (unsigned int i = 0; i < esirisc->reg_cache->num_regs; ++i) {
 		struct reg *reg = esirisc->reg_cache->reg_list + i;
@@ -316,7 +316,7 @@ static int esirisc_flush_caches(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	if (target->state != TARGET_HALTED) {
 		LOG_TARGET_ERROR(target, "not halted");
@@ -325,7 +325,7 @@ static int esirisc_flush_caches(struct target *target)
 
 	int retval = esirisc_jtag_flush_caches(jtag_info);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to flush caches", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to flush caches");
 		return retval;
 	}
 
@@ -337,7 +337,7 @@ static int esirisc_wait_debug_active(struct esirisc_common *esirisc, int ms)
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int64_t t;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(esirisc->target, "-");
 
 	t = timeval_ms();
 	for (;;) {
@@ -359,7 +359,7 @@ static int esirisc_read_memory(struct target *target, target_addr_t address,
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	int num_bits = 8 * size;
 	for (uint32_t i = 0; i < count; ++i) {
@@ -383,12 +383,12 @@ static int esirisc_read_memory(struct target *target, target_addr_t address,
 				break;
 
 			default:
-				LOG_ERROR("%s: unsupported size: %" PRIu32, target_name(target), size);
+				LOG_TARGET_ERROR(target, "unsupported size: %" PRIu32, size);
 				return ERROR_FAIL;
 		}
 
 		if (retval != ERROR_OK) {
-			LOG_ERROR("%s: failed to read address: 0x%" TARGET_PRIxADDR, target_name(target),
+			LOG_TARGET_ERROR(target, "failed to read address: 0x%" TARGET_PRIxADDR,
 					address);
 			return retval;
 		}
@@ -408,7 +408,7 @@ static int esirisc_write_memory(struct target *target, target_addr_t address,
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	int num_bits = 8 * size;
 	for (uint32_t i = 0; i < count; ++i) {
@@ -431,12 +431,12 @@ static int esirisc_write_memory(struct target *target, target_addr_t address,
 				break;
 
 			default:
-				LOG_ERROR("%s: unsupported size: %" PRIu32, target_name(target), size);
+				LOG_TARGET_ERROR(target, "unsupported size: %" PRIu32, size);
 				return ERROR_FAIL;
 		}
 
 		if (retval != ERROR_OK) {
-			LOG_ERROR("%s: failed to write address: 0x%" TARGET_PRIxADDR, target_name(target),
+			LOG_TARGET_ERROR(target, "failed to write address: 0x%" TARGET_PRIxADDR,
 					address);
 			return retval;
 		}
@@ -460,7 +460,7 @@ static int esirisc_next_breakpoint(struct target *target)
 	struct breakpoint **breakpoints_p = esirisc->breakpoints_p;
 	struct breakpoint **breakpoints_e = breakpoints_p + esirisc->num_breakpoints;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	for (int bp_index = 0; breakpoints_p < breakpoints_e; ++breakpoints_p, ++bp_index)
 		if (!*breakpoints_p)
@@ -477,7 +477,7 @@ static int esirisc_add_breakpoint(struct target *target, struct breakpoint *brea
 	uint32_t ibc;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	/*
 	 * The default linker scripts provided by the eSi-RISC toolchain do
@@ -491,7 +491,7 @@ static int esirisc_add_breakpoint(struct target *target, struct breakpoint *brea
 
 	bp_index = esirisc_next_breakpoint(target);
 	if (bp_index < 0) {
-		LOG_ERROR("%s: out of hardware breakpoints", target_name(target));
+		LOG_TARGET_ERROR(target, "out of hardware breakpoints");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
@@ -502,14 +502,14 @@ static int esirisc_add_breakpoint(struct target *target, struct breakpoint *brea
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBA_N + bp_index,
 			breakpoint->address);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: IBA", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: IBA");
 		return retval;
 	}
 
 	/* enable instruction breakpoint */
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, &ibc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Debug CSR: IBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Debug CSR: IBC");
 		return retval;
 	}
 
@@ -517,7 +517,7 @@ static int esirisc_add_breakpoint(struct target *target, struct breakpoint *brea
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, ibc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: IBC");
 		return retval;
 	}
 
@@ -528,7 +528,7 @@ static int esirisc_add_breakpoints(struct target *target)
 {
 	struct breakpoint *breakpoint = target->breakpoints;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	while (breakpoint) {
 		if (!breakpoint->is_set)
@@ -548,12 +548,12 @@ static int esirisc_remove_breakpoint(struct target *target, struct breakpoint *b
 	uint32_t ibc;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	/* disable instruction breakpoint */
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, &ibc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Debug CSR: IBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Debug CSR: IBC");
 		return retval;
 	}
 
@@ -561,7 +561,7 @@ static int esirisc_remove_breakpoint(struct target *target, struct breakpoint *b
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, ibc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: IBC");
 		return retval;
 	}
 
@@ -576,12 +576,12 @@ static int esirisc_remove_breakpoints(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	/* clear instruction breakpoints */
 	int retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, 0);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: IBC");
 		return retval;
 	}
 
@@ -596,7 +596,7 @@ static int esirisc_next_watchpoint(struct target *target)
 	struct watchpoint **watchpoints_p = esirisc->watchpoints_p;
 	struct watchpoint **watchpoints_e = watchpoints_p + esirisc->num_watchpoints;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	for (int wp_index = 0; watchpoints_p < watchpoints_e; ++watchpoints_p, ++wp_index)
 		if (!*watchpoints_p)
@@ -613,11 +613,11 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc
 	uint32_t dbs, dbc;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	wp_index = esirisc_next_watchpoint(target);
 	if (wp_index < 0) {
-		LOG_ERROR("%s: out of hardware watchpoints", target_name(target));
+		LOG_TARGET_ERROR(target, "out of hardware watchpoints");
 		return ERROR_FAIL;
 	}
 
@@ -628,14 +628,14 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBA_N + wp_index,
 			watchpoint->address);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: DBA", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: DBA");
 		return retval;
 	}
 
 	/* specify data breakpoint size */
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBS, &dbs);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Debug CSR: DBS", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Debug CSR: DBS");
 		return retval;
 	}
 
@@ -657,7 +657,7 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc
 			break;
 
 		default:
-			LOG_ERROR("%s: unsupported length: %" PRIu32, target_name(target),
+			LOG_TARGET_ERROR(target, "unsupported length: %" PRIu32,
 					watchpoint->length);
 			return ERROR_FAIL;
 	}
@@ -666,14 +666,14 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBS, dbs);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: DBS", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: DBS");
 		return retval;
 	}
 
 	/* enable data breakpoint */
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, &dbc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Debug CSR: DBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Debug CSR: DBC");
 		return retval;
 	}
 
@@ -692,8 +692,7 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc
 			break;
 
 		default:
-			LOG_ERROR("%s: unsupported rw: %" PRId32, target_name(target),
-					watchpoint->rw);
+			LOG_TARGET_ERROR(target, "unsupported rw: %" PRId32, watchpoint->rw);
 			return ERROR_FAIL;
 	}
 
@@ -701,7 +700,7 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, dbc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: DBC");
 		return retval;
 	}
 
@@ -712,7 +711,7 @@ static int esirisc_add_watchpoints(struct target *target)
 {
 	struct watchpoint *watchpoint = target->watchpoints;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	while (watchpoint) {
 		if (!watchpoint->is_set)
@@ -732,12 +731,12 @@ static int esirisc_remove_watchpoint(struct target *target, struct watchpoint *w
 	uint32_t dbc;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	/* disable data breakpoint */
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, &dbc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Debug CSR: DBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Debug CSR: DBC");
 		return retval;
 	}
 
@@ -745,7 +744,7 @@ static int esirisc_remove_watchpoint(struct target *target, struct watchpoint *w
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, dbc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: DBC");
 		return retval;
 	}
 
@@ -760,12 +759,12 @@ static int esirisc_remove_watchpoints(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	/* clear data breakpoints */
 	int retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, 0);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: DBC");
 		return retval;
 	}
 
@@ -779,14 +778,14 @@ static int esirisc_halt(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	if (target->state == TARGET_HALTED)
 		return ERROR_OK;
 
 	int retval = esirisc_jtag_break(jtag_info);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to halt target", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to halt target");
 		return retval;
 	}
 
@@ -802,11 +801,11 @@ static int esirisc_disable_step(struct target *target)
 	uint32_t dc;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, &dc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Debug CSR: DC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Debug CSR: DC");
 		return retval;
 	}
 
@@ -814,7 +813,7 @@ static int esirisc_disable_step(struct target *target)
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, dc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: DC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: DC");
 		return retval;
 	}
 
@@ -828,11 +827,11 @@ static int esirisc_enable_step(struct target *target)
 	uint32_t dc;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, &dc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Debug CSR: DC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Debug CSR: DC");
 		return retval;
 	}
 
@@ -840,7 +839,7 @@ static int esirisc_enable_step(struct target *target)
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, dc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: DC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: DC");
 		return retval;
 	}
 
@@ -855,7 +854,7 @@ static int esirisc_resume_or_step(struct target *target, int current, target_add
 	struct breakpoint *breakpoint = NULL;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	if (target->state != TARGET_HALTED) {
 		LOG_TARGET_ERROR(target, "not halted");
@@ -901,7 +900,7 @@ static int esirisc_resume_or_step(struct target *target, int current, target_add
 
 	retval = esirisc_jtag_continue(jtag_info);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to resume target", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to resume target");
 		return retval;
 	}
 
@@ -921,7 +920,7 @@ static int esirisc_resume_or_step(struct target *target, int current, target_add
 static int esirisc_resume(struct target *target, int current, target_addr_t address,
 		int handle_breakpoints, int debug_execution)
 {
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	return esirisc_resume_or_step(target, current, address,
 			handle_breakpoints, debug_execution, false);
@@ -930,7 +929,7 @@ static int esirisc_resume(struct target *target, int current, target_addr_t addr
 static int esirisc_step(struct target *target, int current, target_addr_t address,
 		int handle_breakpoints)
 {
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	return esirisc_resume_or_step(target, current, address,
 			handle_breakpoints, 0, true);
@@ -942,20 +941,20 @@ static int esirisc_debug_step(struct target *target)
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	esirisc_disable_interrupts(target);
 	esirisc_enable_step(target);
 
 	retval = esirisc_jtag_continue(jtag_info);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to resume target", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to resume target");
 		return retval;
 	}
 
 	retval = esirisc_wait_debug_active(esirisc, STEP_TIMEOUT);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: step timed out", target_name(target));
+		LOG_TARGET_ERROR(target, "step timed out");
 		return retval;
 	}
 
@@ -971,23 +970,23 @@ static int esirisc_debug_reset(struct target *target)
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	retval = esirisc_jtag_assert_reset(jtag_info);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to assert reset", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to assert reset");
 		return retval;
 	}
 
 	retval = esirisc_jtag_deassert_reset(jtag_info);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to deassert reset", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to deassert reset");
 		return retval;
 	}
 
 	retval = esirisc_wait_debug_active(esirisc, RESET_TIMEOUT);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: reset timed out", target_name(target));
+		LOG_TARGET_ERROR(target, "reset timed out");
 		return retval;
 	}
 
@@ -1000,11 +999,11 @@ static int esirisc_debug_enable(struct target *target)
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	retval = esirisc_jtag_enable_debug(jtag_info);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to enable debug mode", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to enable debug mode");
 		return retval;
 	}
 
@@ -1015,13 +1014,13 @@ static int esirisc_debug_enable(struct target *target)
 	 * targets, which will respond with all ones and appear active.
 	 */
 	if (esirisc_jtag_is_stopped(jtag_info)) {
-		LOG_INFO("%s: debug clock inactive; attempting debug reset", target_name(target));
+		LOG_TARGET_INFO(target, "debug clock inactive; attempting debug reset");
 		retval = esirisc_debug_reset(target);
 		if (retval != ERROR_OK)
 			return retval;
 
 		if (esirisc_jtag_is_stopped(jtag_info)) {
-			LOG_ERROR("%s: target unresponsive; giving up", target_name(target));
+			LOG_TARGET_ERROR(target, "target unresponsive; giving up");
 			return ERROR_FAIL;
 		}
 	}
@@ -1034,7 +1033,7 @@ static int esirisc_debug_entry(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct breakpoint *breakpoint;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	esirisc_save_context(target);
 
@@ -1087,12 +1086,12 @@ static int esirisc_poll(struct target *target)
 
 	retval = esirisc_jtag_enable_debug(jtag_info);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to poll target", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to poll target");
 		return retval;
 	}
 
 	if (esirisc_jtag_is_stopped(jtag_info)) {
-		LOG_ERROR("%s: target has stopped; reset required", target_name(target));
+		LOG_TARGET_ERROR(target, "target has stopped; reset required");
 		target->state = TARGET_UNKNOWN;
 		return ERROR_TARGET_FAILURE;
 	}
@@ -1122,7 +1121,7 @@ static int esirisc_assert_reset(struct target *target)
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	if (jtag_get_reset_config() & RESET_HAS_SRST) {
 		jtag_add_reset(1, 1);
@@ -1134,7 +1133,7 @@ static int esirisc_assert_reset(struct target *target)
 
 		retval = esirisc_jtag_assert_reset(jtag_info);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("%s: failed to assert reset", target_name(target));
+			LOG_TARGET_ERROR(target, "failed to assert reset");
 			return retval;
 		}
 	}
@@ -1153,19 +1152,19 @@ static int esirisc_reset_entry(struct target *target)
 	uint32_t eta, epc;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	/* read exception table address */
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETA, &eta);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Thread CSR: ETA", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Thread CSR: ETA");
 		return retval;
 	}
 
 	/* read reset entry point */
 	retval = esirisc_jtag_read_word(jtag_info, eta + ENTRY_RESET, &epc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read address: 0x%" TARGET_PRIxADDR, target_name(target),
+		LOG_TARGET_ERROR(target, "failed to read address: 0x%" TARGET_PRIxADDR,
 				(target_addr_t)epc);
 		return retval;
 	}
@@ -1173,7 +1172,7 @@ static int esirisc_reset_entry(struct target *target)
 	/* write reset entry point */
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_EPC, epc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Thread CSR: EPC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Thread CSR: EPC");
 		return retval;
 	}
 
@@ -1186,7 +1185,7 @@ static int esirisc_deassert_reset(struct target *target)
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	if (jtag_get_reset_config() & RESET_HAS_SRST) {
 		jtag_add_reset(0, 0);
@@ -1202,14 +1201,14 @@ static int esirisc_deassert_reset(struct target *target)
 	} else {
 		retval = esirisc_jtag_deassert_reset(jtag_info);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("%s: failed to deassert reset", target_name(target));
+			LOG_TARGET_ERROR(target, "failed to deassert reset");
 			return retval;
 		}
 	}
 
 	retval = esirisc_wait_debug_active(esirisc, RESET_TIMEOUT);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: reset timed out", target_name(target));
+		LOG_TARGET_ERROR(target, "reset timed out");
 		return retval;
 	}
 
@@ -1225,7 +1224,7 @@ static int esirisc_deassert_reset(struct target *target)
 	if (!target->reset_halt) {
 		retval = esirisc_jtag_continue(jtag_info);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("%s: failed to resume target", target_name(target));
+			LOG_TARGET_ERROR(target, "failed to resume target");
 			return retval;
 		}
 	}
@@ -1241,7 +1240,7 @@ static int esirisc_arch_state(struct target *target)
 	uint32_t eid = buf_get_u32(esirisc->eid->value, 0, esirisc->eid->size);
 	uint32_t ed = buf_get_u32(esirisc->ed->value, 0, esirisc->ed->size);
 
-	LOG_USER("target halted due to %s, exception: %s\n"
+	LOG_TARGET_USER(target, "target halted due to %s, exception: %s\n"
 			"EPC: 0x%" PRIx32 ", ECAS: 0x%" PRIx32 ", EID: 0x%" PRIx32 ", ED: 0x%" PRIx32,
 			debug_reason_name(target), esirisc_exception_strings[eid], epc, ecas, eid, ed);
 
@@ -1252,7 +1251,7 @@ static const char *esirisc_get_gdb_arch(const struct target *target)
 {
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	/*
 	 * Targets with the UNIFIED_ADDRESS_SPACE option disabled employ a
@@ -1272,7 +1271,7 @@ static int esirisc_get_gdb_reg_list(struct target *target, struct reg **reg_list
 {
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	*reg_list_size = ESIRISC_NUM_REGS;
 
@@ -1302,11 +1301,11 @@ static int esirisc_read_reg(struct reg *reg)
 	struct target *target = esirisc->target;
 	uint32_t data;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	int retval = esirisc_jtag_read_reg(jtag_info, reg->number, &data);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read register: %s", target_name(target), reg->name);
+		LOG_TARGET_ERROR(target, "failed to read register: %s", reg->name);
 		return retval;
 	}
 
@@ -1325,11 +1324,11 @@ static int esirisc_write_reg(struct reg *reg)
 	struct target *target = esirisc->target;
 	uint32_t data = buf_get_u32(reg->value, 0, reg->size);
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	int retval = esirisc_jtag_write_reg(jtag_info, reg->number, data);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write register: %s", target_name(target), reg->name);
+		LOG_TARGET_ERROR(target, "failed to write register: %s", reg->name);
 		return retval;
 	}
 
@@ -1347,11 +1346,11 @@ static int esirisc_read_csr(struct reg *reg)
 	struct target *target = esirisc->target;
 	uint32_t data;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	int retval = esirisc_jtag_read_csr(jtag_info, reg_info->bank, reg_info->csr, &data);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read CSR: %s", target_name(target), reg->name);
+		LOG_TARGET_ERROR(target, "failed to read CSR: %s", reg->name);
 		return retval;
 	}
 
@@ -1370,11 +1369,11 @@ static int esirisc_write_csr(struct reg *reg)
 	struct target *target = esirisc->target;
 	uint32_t data = buf_get_u32(reg->value, 0, reg->size);
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	int retval = esirisc_jtag_write_csr(jtag_info, reg_info->bank, reg_info->csr, data);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write CSR: %s", target_name(target), reg->name);
+		LOG_TARGET_ERROR(target, "failed to write CSR: %s", reg->name);
 		return retval;
 	}
 
@@ -1390,7 +1389,7 @@ static int esirisc_get_reg(struct reg *reg)
 	struct esirisc_common *esirisc = reg_info->esirisc;
 	struct target *target = esirisc->target;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	if (target->state != TARGET_HALTED)
 		return ERROR_TARGET_NOT_HALTED;
@@ -1405,7 +1404,7 @@ static int esirisc_set_reg(struct reg *reg, uint8_t *buf)
 	struct target *target = esirisc->target;
 	uint32_t value = buf_get_u32(buf, 0, reg->size);
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	if (target->state != TARGET_HALTED)
 		return ERROR_TARGET_NOT_HALTED;
@@ -1429,7 +1428,7 @@ static struct reg_cache *esirisc_build_reg_cache(struct target *target)
 	struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 	struct reg *reg_list = calloc(ESIRISC_NUM_REGS, sizeof(struct reg));
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	cache->name = "eSi-RISC registers";
 	cache->next = NULL;
@@ -1519,11 +1518,11 @@ static int esirisc_identify(struct target *target)
 	uint32_t csr;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_ARCH0, &csr);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Configuration CSR: ARCH0", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Configuration CSR: ARCH0");
 		return retval;
 	}
 
@@ -1532,7 +1531,7 @@ static int esirisc_identify(struct target *target)
 
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_MEM, &csr);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Configuration CSR: MEM", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Configuration CSR: MEM");
 		return retval;
 	}
 
@@ -1541,7 +1540,7 @@ static int esirisc_identify(struct target *target)
 
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_IC, &csr);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Configuration CSR: IC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Configuration CSR: IC");
 		return retval;
 	}
 
@@ -1549,7 +1548,7 @@ static int esirisc_identify(struct target *target)
 
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_DC, &csr);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Configuration CSR: DC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Configuration CSR: DC");
 		return retval;
 	}
 
@@ -1557,7 +1556,7 @@ static int esirisc_identify(struct target *target)
 
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_DBG, &csr);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Configuration CSR: DBG", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Configuration CSR: DBG");
 		return retval;
 	}
 
@@ -1566,7 +1565,7 @@ static int esirisc_identify(struct target *target)
 
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_TRACE, &csr);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Configuration CSR: TRACE", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Configuration CSR: TRACE");
 		return retval;
 	}
 
@@ -1584,8 +1583,7 @@ static int esirisc_target_create(struct target *target, Jim_Interp *interp)
 		return ERROR_FAIL;
 
 	if (tap->ir_length != INSTR_LENGTH) {
-		LOG_ERROR("%s: invalid IR length; expected %d", target_name(target),
-				INSTR_LENGTH);
+		LOG_TARGET_ERROR(target, "invalid IR length; expected %d", INSTR_LENGTH);
 		return ERROR_FAIL;
 	}
 
@@ -1629,7 +1627,7 @@ static int esirisc_examine(struct target *target)
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int retval;
 
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");
 
 	if (!target_was_examined(target)) {
 		retval = esirisc_debug_enable(target);
@@ -1649,7 +1647,7 @@ static int esirisc_examine(struct target *target)
 		} else {
 			retval = esirisc_jtag_break(jtag_info);
 			if (retval != ERROR_OK) {
-				LOG_ERROR("%s: failed to halt target", target_name(target));
+				LOG_TARGET_ERROR(target, "failed to halt target");
 				return retval;
 			}
 
@@ -1658,7 +1656,7 @@ static int esirisc_examine(struct target *target)
 
 		retval = esirisc_identify(target);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("%s: failed to identify target", target_name(target));
+			LOG_TARGET_ERROR(target, "failed to identify target");
 			return retval;
 		}
 
@@ -1675,20 +1673,20 @@ static int esirisc_examine(struct target *target)
 		else {
 			retval = esirisc_jtag_continue(jtag_info);
 			if (retval != ERROR_OK) {
-				LOG_ERROR("%s: failed to resume target", target_name(target));
+				LOG_TARGET_ERROR(target, "failed to resume target");
 				return retval;
 			}
 		}
 
 		target_set_examined(target);
 
-		LOG_INFO("%s: %d bit, %d registers, %s%s%s", target_name(target),
+		LOG_TARGET_INFO(target, "%d bit, %d registers, %s%s%s",
 				esirisc->num_bits, esirisc->num_regs,
 				target_endianness(target),
 				esirisc->has_icache ? ", icache" : "",
 				esirisc->has_dcache ? ", dcache" : "");
 
-		LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints%s", target_name(target),
+		LOG_TARGET_INFO(target, "hardware has %d breakpoints, %d watchpoints%s",
 				esirisc->num_breakpoints, esirisc->num_watchpoints,
 				esirisc->has_trace ? ", trace" : "");
 	}
@@ -1707,7 +1705,7 @@ COMMAND_HANDLER(handle_esirisc_cache_arch_command)
 		else if (strcmp(*CMD_ARGV, "von_neumann") == 0)
 			esirisc->cache_arch = ESIRISC_CACHE_VON_NEUMANN;
 		else {
-			LOG_ERROR("invalid cache_arch: %s", *CMD_ARGV);
+			LOG_TARGET_ERROR(target, "invalid cache_arch: %s", *CMD_ARGV);
 			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 	}
@@ -1724,7 +1722,7 @@ COMMAND_HANDLER(handle_esirisc_flush_caches_command)
 	int retval;
 
 	if (!esirisc_has_cache(esirisc)) {
-		LOG_ERROR("target does not support caching");
+		LOG_TARGET_ERROR(target, "target does not support caching");
 		return ERROR_FAIL;
 	}
 
@@ -1770,7 +1768,7 @@ COMMAND_HANDLER(handle_esirisc_hwdc_command)
 				while (CMD_ARGC-- > 0) {
 					int mask = esirisc_find_hwdc_mask(CMD_ARGV[CMD_ARGC]);
 					if (mask < 0) {
-						LOG_ERROR("invalid mask: %s", CMD_ARGV[CMD_ARGC]);
+						LOG_TARGET_ERROR(target, "invalid mask: %s", CMD_ARGV[CMD_ARGC]);
 						return ERROR_COMMAND_SYNTAX_ERROR;
 					}
 					esirisc->hwdc_save |= mask;
diff --git a/src/target/esirisc_trace.c b/src/target/esirisc_trace.c
index a70d9d74b..a1d92d1ca 100644
--- a/src/target/esirisc_trace.c
+++ b/src/target/esirisc_trace.c
@@ -85,7 +85,7 @@ static int esirisc_trace_clear_status(struct target *target)
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_STATUS, ~0);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: Status", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: Status");
 		return retval;
 	}
 
@@ -102,7 +102,7 @@ static int esirisc_trace_get_status(struct target *target, uint32_t *status)
 
 	int retval = esirisc_jtag_read_csr(jtag_info, CSR_TRACE, CSR_TRACE_STATUS, status);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Trace CSR: Status", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Trace CSR: Status");
 		return retval;
 	}
 
@@ -121,7 +121,7 @@ static int esirisc_trace_start(struct target *target)
 
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_TRACE, CSR_TRACE_CONTROL, &control);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Trace CSR: Control", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Trace CSR: Control");
 		return retval;
 	}
 
@@ -129,7 +129,7 @@ static int esirisc_trace_start(struct target *target)
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_CONTROL, control);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: Control", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: Control");
 		return retval;
 	}
 
@@ -148,7 +148,7 @@ static int esirisc_trace_stop(struct target *target)
 
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_TRACE, CSR_TRACE_CONTROL, &control);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Trace CSR: Control", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Trace CSR: Control");
 		return retval;
 	}
 
@@ -156,7 +156,7 @@ static int esirisc_trace_stop(struct target *target)
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_CONTROL, control);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: Control", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: Control");
 		return retval;
 	}
 
@@ -195,7 +195,7 @@ static int esirisc_trace_init(struct target *target)
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_CONTROL, control);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: Control", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: Control");
 		return retval;
 	}
 
@@ -203,14 +203,14 @@ static int esirisc_trace_init(struct target *target)
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_BUFFER_START,
 			trace_info->buffer_start);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: BufferStart", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: BufferStart");
 		return retval;
 	}
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_BUFFER_END,
 			trace_info->buffer_end);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: BufferEnd", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: BufferEnd");
 		return retval;
 	}
 
@@ -221,7 +221,7 @@ static int esirisc_trace_init(struct target *target)
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_BUFFER_CUR,
 			trace_info->buffer_start);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: BufferCurrent", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: BufferCurrent");
 		return retval;
 	}
 
@@ -241,7 +241,7 @@ static int esirisc_trace_init(struct target *target)
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_TRIGGER, trigger);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: Trigger", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: Trigger");
 		return retval;
 	}
 
@@ -249,14 +249,14 @@ static int esirisc_trace_init(struct target *target)
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_START_DATA,
 			trace_info->start_data);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: StartData", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: StartData");
 		return retval;
 	}
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_START_MASK,
 			trace_info->start_mask);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: StartMask", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: StartMask");
 		return retval;
 	}
 
@@ -264,14 +264,14 @@ static int esirisc_trace_init(struct target *target)
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_STOP_DATA,
 			trace_info->stop_data);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: StopData", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: StopData");
 		return retval;
 	}
 
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_STOP_MASK,
 			trace_info->stop_mask);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: StopMask", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: StopMask");
 		return retval;
 	}
 
@@ -279,7 +279,7 @@ static int esirisc_trace_init(struct target *target)
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_DELAY,
 			trace_info->delay_cycles);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: Delay", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: Delay");
 		return retval;
 	}
 
@@ -326,7 +326,7 @@ static int esirisc_trace_read_memory(struct target *target, target_addr_t addres
 
 	retval = target_read_memory(target, address, 1, size, buffer);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read trace data", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read trace data");
 		return retval;
 	}
 
@@ -346,7 +346,7 @@ static int esirisc_trace_read_buffer(struct target *target, uint8_t *buffer)
 
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_TRACE, CSR_TRACE_BUFFER_CUR, &buffer_cur);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Trace CSR: BufferCurrent", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Trace CSR: BufferCurrent");
 		return retval;
 	}
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/esirisc.c       | 242 ++++++++++++++++++++++-----------------------
 src/target/esirisc_trace.c |  36 +++----
 2 files changed, 138 insertions(+), 140 deletions(-)


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Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-820-g419332231

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  4193322315660436983a16bdc5e18e7252e92a55 (commit)
      from  e4ad10e0a1c9ea81279d551076c83c7da932def4 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 4193322315660436983a16bdc5e18e7252e92a55
Author: Marc Schink <de...@za...>
Date:   Tue Oct 22 18:23:14 2024 +0200

    target/mem_ap: Use LOG_TARGET_xxx()
    
    Use LOG_TARGET_xxx() for log messages as it is used for other targets.
    
    Change-Id: I2f937c937a5c09d91dc82b4323be3276ab60b01a
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8662
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/target/mem_ap.c b/src/target/mem_ap.c
index 411402077..5b2bbb1ae 100644
--- a/src/target/mem_ap.c
+++ b/src/target/mem_ap.c
@@ -34,13 +34,13 @@ static int mem_ap_target_create(struct target *target, Jim_Interp *interp)
 		return ERROR_FAIL;
 
 	if (pc->ap_num == DP_APSEL_INVALID) {
-		LOG_ERROR("AP number not specified");
+		LOG_TARGET_ERROR(target, "AP number not specified");
 		return ERROR_FAIL;
 	}
 
 	mem_ap = calloc(1, sizeof(struct mem_ap));
 	if (!mem_ap) {
-		LOG_ERROR("Out of memory");
+		LOG_TARGET_ERROR(target, "Out of memory");
 		return ERROR_FAIL;
 	}
 
@@ -58,7 +58,7 @@ static int mem_ap_target_create(struct target *target, Jim_Interp *interp)
 
 static int mem_ap_init_target(struct command_context *cmd_ctx, struct target *target)
 {
-	LOG_DEBUG("%s", __func__);
+	LOG_TARGET_DEBUG(target, "%s", __func__);
 	target->state = TARGET_UNKNOWN;
 	target->debug_reason = DBG_REASON_UNDEFINED;
 	return ERROR_OK;
@@ -68,7 +68,7 @@ static void mem_ap_deinit_target(struct target *target)
 {
 	struct mem_ap *mem_ap = target->arch_info;
 
-	LOG_DEBUG("%s", __func__);
+	LOG_TARGET_DEBUG(target, "%s", __func__);
 
 	if (mem_ap->ap)
 		dap_put_ap(mem_ap->ap);
@@ -79,7 +79,7 @@ static void mem_ap_deinit_target(struct target *target)
 
 static int mem_ap_arch_state(struct target *target)
 {
-	LOG_DEBUG("%s", __func__);
+	LOG_TARGET_DEBUG(target, "%s", __func__);
 	return ERROR_OK;
 }
 
@@ -95,7 +95,7 @@ static int mem_ap_poll(struct target *target)
 
 static int mem_ap_halt(struct target *target)
 {
-	LOG_DEBUG("%s", __func__);
+	LOG_TARGET_DEBUG(target, "%s", __func__);
 	target->state = TARGET_HALTED;
 	target->debug_reason = DBG_REASON_DBGRQ;
 	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
@@ -105,7 +105,7 @@ static int mem_ap_halt(struct target *target)
 static int mem_ap_resume(struct target *target, int current, target_addr_t address,
 		int handle_breakpoints, int debug_execution)
 {
-	LOG_DEBUG("%s", __func__);
+	LOG_TARGET_DEBUG(target, "%s", __func__);
 	target->state = TARGET_RUNNING;
 	target->debug_reason = DBG_REASON_NOTHALTED;
 	return ERROR_OK;
@@ -114,7 +114,7 @@ static int mem_ap_resume(struct target *target, int current, target_addr_t addre
 static int mem_ap_step(struct target *target, int current, target_addr_t address,
 				int handle_breakpoints)
 {
-	LOG_DEBUG("%s", __func__);
+	LOG_TARGET_DEBUG(target, "%s", __func__);
 	target->state = TARGET_HALTED;
 	target->debug_reason = DBG_REASON_DBGRQ;
 	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
@@ -126,7 +126,7 @@ static int mem_ap_assert_reset(struct target *target)
 	target->state = TARGET_RESET;
 	target->debug_reason = DBG_REASON_UNDEFINED;
 
-	LOG_DEBUG("%s", __func__);
+	LOG_TARGET_DEBUG(target, "%s", __func__);
 	return ERROR_OK;
 }
 
@@ -138,7 +138,7 @@ static int mem_ap_examine(struct target *target)
 		if (!mem_ap->ap) {
 			mem_ap->ap = dap_get_ap(mem_ap->dap, mem_ap->ap_num);
 			if (!mem_ap->ap) {
-				LOG_ERROR("Cannot get AP");
+				LOG_TARGET_ERROR(target, "Cannot get AP");
 				return ERROR_FAIL;
 			}
 		}
@@ -162,7 +162,7 @@ static int mem_ap_deassert_reset(struct target *target)
 		target->debug_reason = DBG_REASON_NOTHALTED;
 	}
 
-	LOG_DEBUG("%s", __func__);
+	LOG_TARGET_DEBUG(target, "%s", __func__);
 	return ERROR_OK;
 }
 
@@ -212,7 +212,7 @@ static int mem_ap_get_gdb_reg_list(struct target *target, struct reg **reg_list[
 {
 	struct mem_ap_alloc_reg_list *mem_ap_alloc = calloc(1, sizeof(struct mem_ap_alloc_reg_list));
 	if (!mem_ap_alloc) {
-		LOG_ERROR("Out of memory");
+		LOG_TARGET_ERROR(target, "Out of memory");
 		return ERROR_FAIL;
 	}
 
@@ -237,7 +237,7 @@ static int mem_ap_read_memory(struct target *target, target_addr_t address,
 {
 	struct mem_ap *mem_ap = target->arch_info;
 
-	LOG_DEBUG("Reading memory at physical address " TARGET_ADDR_FMT
+	LOG_TARGET_DEBUG(target, "Reading memory at physical address " TARGET_ADDR_FMT
 		  "; size %" PRIu32 "; count %" PRIu32, address, size, count);
 
 	if (count == 0 || !buffer)
@@ -252,7 +252,7 @@ static int mem_ap_write_memory(struct target *target, target_addr_t address,
 {
 	struct mem_ap *mem_ap = target->arch_info;
 
-	LOG_DEBUG("Writing memory at physical address " TARGET_ADDR_FMT
+	LOG_TARGET_DEBUG(target, "Writing memory at physical address " TARGET_ADDR_FMT
 		  "; size %" PRIu32 "; count %" PRIu32, address, size, count);
 
 	if (count == 0 || !buffer)

-----------------------------------------------------------------------

Summary of changes:
 src/target/mem_ap.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-819-ge4ad10e0a

[openocd-gerrit <ope...@us...>]

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       via  e4ad10e0a1c9ea81279d551076c83c7da932def4 (commit)
      from  5284a5f3eca63099fc0f3e19e69d1c55a99b214b (commit)

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- Log -----------------------------------------------------------------
commit e4ad10e0a1c9ea81279d551076c83c7da932def4
Author: Marc Schink <de...@za...>
Date:   Tue Oct 22 16:36:15 2024 +0200

    helper/log: Add LOG_TARGET_USER()
    
    Add a target-related log function for user messages as it already
    exists for other log levels.
    
    Change-Id: I9076677d6451b900332583e748bab3f83df56d3b
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8661
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/helper/log.h b/src/helper/log.h
index dc8df6fbb..e2bb131ed 100644
--- a/src/helper/log.h
+++ b/src/helper/log.h
@@ -152,6 +152,9 @@ extern int debug_level;
 #define LOG_TARGET_INFO(target, fmt_str, ...) \
 	LOG_INFO("[%s] " fmt_str, target_name(target), ##__VA_ARGS__)
 
+#define LOG_TARGET_USER(target, fmt_str, ...) \
+	LOG_USER("[%s] " fmt_str, target_name(target), ##__VA_ARGS__)
+
 #define LOG_TARGET_WARNING(target, fmt_str, ...) \
 	LOG_WARNING("[%s] " fmt_str, target_name(target), ##__VA_ARGS__)
 

-----------------------------------------------------------------------

Summary of changes:
 src/helper/log.h | 3 +++
 1 file changed, 3 insertions(+)


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