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From: OpenOCD-Gerrit <ope...@us...> - 2021-07-02 16:11:05
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 3d135a5c70db67ed13cc93eeab0b700f6ef8a412 (commit)
from 12219255c625b048b04d8cfbd7ad59eee4a39442 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 3d135a5c70db67ed13cc93eeab0b700f6ef8a412
Author: Antonio Borneo <bor...@gm...>
Date: Mon Apr 26 23:53:42 2021 +0200
flash: rename CamelCase symbols
Each driver is almost self-contained, with no cross dependency.
Changing symbol names in one drive does not impact the other.
Change-Id: Ic09f844f922a35cf0a9dc23fcd61d035b38308b3
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/6299
Tested-by: jenkins
Reviewed-by: Marc Schink <de...@za...>
diff --git a/src/flash/nand/at91sam9.c b/src/flash/nand/at91sam9.c
index 234dd70c1..534f20ede 100644
--- a/src/flash/nand/at91sam9.c
+++ b/src/flash/nand/at91sam9.c
@@ -25,13 +25,13 @@
#include "imp.h"
#include "arm_io.h"
-#define AT91C_PIOx_SODR (0x30) /**< Offset to PIO SODR. */
-#define AT91C_PIOx_CODR (0x34) /**< Offset to PIO CODR. */
-#define AT91C_PIOx_PDSR (0x3C) /**< Offset to PIO PDSR. */
-#define AT91C_ECCx_CR (0x00) /**< Offset to ECC CR. */
-#define AT91C_ECCx_SR (0x08) /**< Offset to ECC SR. */
-#define AT91C_ECCx_PR (0x0C) /**< Offset to ECC PR. */
-#define AT91C_ECCx_NPR (0x10) /**< Offset to ECC NPR. */
+#define AT91C_PIOX_SODR (0x30) /**< Offset to PIO SODR. */
+#define AT91C_PIOX_CODR (0x34) /**< Offset to PIO CODR. */
+#define AT91C_PIOX_PDSR (0x3C) /**< Offset to PIO PDSR. */
+#define AT91C_ECCX_CR (0x00) /**< Offset to ECC CR. */
+#define AT91C_ECCX_SR (0x08) /**< Offset to ECC SR. */
+#define AT91C_ECCX_PR (0x0C) /**< Offset to ECC PR. */
+#define AT91C_ECCX_NPR (0x10) /**< Offset to ECC NPR. */
/**
* Representation of a pin on an AT91SAM9 chip.
@@ -113,7 +113,7 @@ static int at91sam9_enable(struct nand_device *nand)
struct at91sam9_nand *info = nand->controller_priv;
struct target *target = nand->target;
- return target_write_u32(target, info->ce.pioc + AT91C_PIOx_CODR, 1 << info->ce.num);
+ return target_write_u32(target, info->ce.pioc + AT91C_PIOX_CODR, 1 << info->ce.num);
}
/**
@@ -127,7 +127,7 @@ static int at91sam9_disable(struct nand_device *nand)
struct at91sam9_nand *info = nand->controller_priv;
struct target *target = nand->target;
- return target_write_u32(target, info->ce.pioc + AT91C_PIOx_SODR, 1 << info->ce.num);
+ return target_write_u32(target, info->ce.pioc + AT91C_PIOX_SODR, 1 << info->ce.num);
}
/**
@@ -237,7 +237,7 @@ static int at91sam9_nand_ready(struct nand_device *nand, int timeout)
return 0;
do {
- target_read_u32(target, info->busy.pioc + AT91C_PIOx_PDSR, &status);
+ target_read_u32(target, info->busy.pioc + AT91C_PIOX_PDSR, &status);
if (status & (1 << info->busy.num))
return 1;
@@ -311,7 +311,7 @@ static int at91sam9_ecc_init(struct target *target, struct at91sam9_nand *info)
}
/* reset ECC parity registers */
- return target_write_u32(target, info->ecc + AT91C_ECCx_CR, 1);
+ return target_write_u32(target, info->ecc + AT91C_ECCX_CR, 1);
}
/**
@@ -384,7 +384,7 @@ static int at91sam9_read_page(struct nand_device *nand, uint32_t page,
oob_data = at91sam9_oob_init(nand, oob, &oob_size);
retval = nand_read_data_page(nand, oob_data, oob_size);
if (ERROR_OK == retval && data) {
- target_read_u32(target, info->ecc + AT91C_ECCx_SR, &status);
+ target_read_u32(target, info->ecc + AT91C_ECCX_SR, &status);
if (status & 1) {
LOG_ERROR("Error detected!");
if (status & 4)
@@ -394,7 +394,7 @@ static int at91sam9_read_page(struct nand_device *nand, uint32_t page,
uint32_t parity;
target_read_u32(target,
- info->ecc + AT91C_ECCx_PR,
+ info->ecc + AT91C_ECCX_PR,
&parity);
uint32_t word = (parity & 0x0000FFF0) >> 4;
uint32_t bit = parity & 0x0F;
@@ -462,8 +462,8 @@ static int at91sam9_write_page(struct nand_device *nand, uint32_t page,
if (!oob) {
/* no OOB given, so read in the ECC parity from the ECC controller */
- target_read_u32(target, info->ecc + AT91C_ECCx_PR, &parity);
- target_read_u32(target, info->ecc + AT91C_ECCx_NPR, &nparity);
+ target_read_u32(target, info->ecc + AT91C_ECCX_PR, &parity);
+ target_read_u32(target, info->ecc + AT91C_ECCX_NPR, &nparity);
oob_data[0] = (uint8_t) parity;
oob_data[1] = (uint8_t) (parity >> 8);
diff --git a/src/flash/nand/lpc32xx.c b/src/flash/nand/lpc32xx.c
index f117eadcc..3e2add49b 100644
--- a/src/flash/nand/lpc32xx.c
+++ b/src/flash/nand/lpc32xx.c
@@ -90,7 +90,7 @@ NAND_DEVICE_COMMAND_HANDLER(lpc32xx_nand_device_command)
"1000 and 20000 kHz, was %i",
lpc32xx_info->osc_freq);
- lpc32xx_info->selected_controller = LPC32xx_NO_CONTROLLER;
+ lpc32xx_info->selected_controller = LPC32XX_NO_CONTROLLER;
lpc32xx_info->sw_write_protection = 0;
lpc32xx_info->sw_wp_lower_bound = 0x0;
lpc32xx_info->sw_wp_upper_bound = 0x0;
@@ -222,13 +222,13 @@ static int lpc32xx_init(struct nand_device *nand)
}
/* select MLC controller if none is currently selected */
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_DEBUG("no LPC32xx NAND flash controller selected, "
"using default 'slc'");
- lpc32xx_info->selected_controller = LPC32xx_SLC_CONTROLLER;
+ lpc32xx_info->selected_controller = LPC32XX_SLC_CONTROLLER;
}
- if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
uint32_t mlc_icr_value = 0x0;
float cycle;
int twp, twh, trp, treh, trhz, trbwb, tcea;
@@ -304,7 +304,7 @@ static int lpc32xx_init(struct nand_device *nand)
retval = lpc32xx_reset(nand);
if (ERROR_OK != retval)
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
float cycle;
int r_setup, r_hold, r_width, r_rdy;
int w_setup, w_hold, w_width, w_rdy;
@@ -401,10 +401,10 @@ static int lpc32xx_reset(struct nand_device *nand)
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_CMD = 0xff (reset controller and NAND device) */
retval = target_write_u32(target, 0x200b8000, 0xff);
if (ERROR_OK != retval) {
@@ -417,7 +417,7 @@ static int lpc32xx_reset(struct nand_device *nand)
"after reset");
return ERROR_NAND_OPERATION_TIMEOUT;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
retval = target_write_u32(target, 0x20020010, 0x6);
if (ERROR_OK != retval) {
@@ -447,17 +447,17 @@ static int lpc32xx_command(struct nand_device *nand, uint8_t command)
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_CMD = command */
retval = target_write_u32(target, 0x200b8000, command);
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_CMD = command */
retval = target_write_u32(target, 0x20020008, command);
if (ERROR_OK != retval) {
@@ -481,17 +481,17 @@ static int lpc32xx_address(struct nand_device *nand, uint8_t address)
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_ADDR = address */
retval = target_write_u32(target, 0x200b8004, address);
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_ADDR = address */
retval = target_write_u32(target, 0x20020004, address);
if (ERROR_OK != retval) {
@@ -515,17 +515,17 @@ static int lpc32xx_write_data(struct nand_device *nand, uint16_t data)
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_DATA = data */
retval = target_write_u32(target, 0x200b0000, data);
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_DATA = data */
retval = target_write_u32(target, 0x20020000, data);
if (ERROR_OK != retval) {
@@ -549,10 +549,10 @@ static int lpc32xx_read_data(struct nand_device *nand, void *data)
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* data = MLC_DATA, use sized access */
if (nand->bus_width == 8) {
uint8_t *data8 = data;
@@ -565,7 +565,7 @@ static int lpc32xx_read_data(struct nand_device *nand, void *data)
LOG_ERROR("could not read MLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
uint32_t data32;
/* data = SLC_DATA, must use 32-bit access */
@@ -1233,10 +1233,10 @@ static int lpc32xx_write_page(struct nand_device *nand, uint32_t page,
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
if (!data && oob) {
LOG_ERROR("LPC32xx MLC controller can't write "
"OOB data only");
@@ -1256,7 +1256,7 @@ static int lpc32xx_write_page(struct nand_device *nand, uint32_t page,
retval = lpc32xx_write_page_mlc(nand, page, data, data_size,
oob, oob_size);
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
struct working_area *pworking_area;
if (!data && oob) {
/*
@@ -1584,17 +1584,17 @@ static int lpc32xx_read_page(struct nand_device *nand, uint32_t page,
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
if (data_size > (uint32_t)nand->page_size) {
LOG_ERROR("data size exceeds page size");
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
retval = lpc32xx_read_page_mlc(nand, page, data, data_size,
oob, oob_size);
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
struct working_area *pworking_area;
retval = target_alloc_working_area(target,
@@ -1628,7 +1628,7 @@ static int lpc32xx_controller_ready(struct nand_device *nand, int timeout)
LOG_DEBUG("lpc32xx_controller_ready count start=%d", timeout);
do {
- if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
uint8_t status;
/* Read MLC_ISR, wait for controller to become ready */
@@ -1643,7 +1643,7 @@ static int lpc32xx_controller_ready(struct nand_device *nand, int timeout)
timeout);
return 1;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
uint32_t status;
/* Read SLC_STAT and check READY bit */
@@ -1681,7 +1681,7 @@ static int lpc32xx_nand_ready(struct nand_device *nand, int timeout)
LOG_DEBUG("lpc32xx_nand_ready count start=%d", timeout);
do {
- if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
uint8_t status = 0x0;
/* Read MLC_ISR, wait for NAND flash device to
@@ -1697,7 +1697,7 @@ static int lpc32xx_nand_ready(struct nand_device *nand, int timeout)
timeout);
return 1;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
uint32_t status = 0x0;
/* Read SLC_STAT and check READY bit */
@@ -1770,10 +1770,10 @@ COMMAND_HANDLER(handle_lpc32xx_select_command)
if (CMD_ARGC >= 2) {
if (strcmp(CMD_ARGV[1], "mlc") == 0) {
lpc32xx_info->selected_controller =
- LPC32xx_MLC_CONTROLLER;
+ LPC32XX_MLC_CONTROLLER;
} else if (strcmp(CMD_ARGV[1], "slc") == 0) {
lpc32xx_info->selected_controller =
- LPC32xx_SLC_CONTROLLER;
+ LPC32XX_SLC_CONTROLLER;
} else
return ERROR_COMMAND_SYNTAX_ERROR;
}
diff --git a/src/flash/nand/lpc32xx.h b/src/flash/nand/lpc32xx.h
index 90b20b247..12c8f48e6 100644
--- a/src/flash/nand/lpc32xx.h
+++ b/src/flash/nand/lpc32xx.h
@@ -20,9 +20,9 @@
#define OPENOCD_FLASH_NAND_LPC32XX_H
enum lpc32xx_selected_controller {
- LPC32xx_NO_CONTROLLER,
- LPC32xx_MLC_CONTROLLER,
- LPC32xx_SLC_CONTROLLER,
+ LPC32XX_NO_CONTROLLER,
+ LPC32XX_MLC_CONTROLLER,
+ LPC32XX_SLC_CONTROLLER,
};
struct lpc32xx_nand_controller {
diff --git a/src/flash/nand/s3c24xx_regs.h b/src/flash/nand/s3c24xx_regs.h
index 88bc66567..46bda6bfe 100644
--- a/src/flash/nand/s3c24xx_regs.h
+++ b/src/flash/nand/s3c24xx_regs.h
@@ -61,7 +61,7 @@
#define S3C2410_NFCONF_512BYTE (1 << 14)
#define S3C2410_NFCONF_4STEP (1 << 13)
#define S3C2410_NFCONF_INITECC (1 << 12)
-#define S3C2410_NFCONF_nFCE (1 << 11)
+#define S3C2410_NFCONF_NFCE (1 << 11)
#define S3C2410_NFCONF_TACLS(x) ((x) << 8)
#define S3C2410_NFCONF_TWRPH0(x) ((x) << 4)
#define S3C2410_NFCONF_TWRPH1(x) ((x) << 0)
@@ -83,12 +83,12 @@
#define S3C2440_NFCONT_SPARE_ECCLOCK (1 << 6)
#define S3C2440_NFCONT_MAIN_ECCLOCK (1 << 5)
#define S3C2440_NFCONT_INITECC (1 << 4)
-#define S3C2440_NFCONT_nFCE (1 << 1)
+#define S3C2440_NFCONT_NFCE (1 << 1)
#define S3C2440_NFCONT_ENABLE (1 << 0)
#define S3C2440_NFSTAT_READY (1 << 0)
-#define S3C2440_NFSTAT_nCE (1 << 1)
-#define S3C2440_NFSTAT_RnB_CHANGE (1 << 2)
+#define S3C2440_NFSTAT_NCE (1 << 1)
+#define S3C2440_NFSTAT_RNB_CHANGE (1 << 2)
#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1 << 3)
#define S3C2412_NFCONF_NANDBOOT (1 << 31)
@@ -103,16 +103,16 @@
#define S3C2412_NFCONT_ECC4_DECINT (1 << 12)
#define S3C2412_NFCONT_MAIN_ECC_LOCK (1 << 7)
#define S3C2412_NFCONT_INIT_MAIN_ECC (1 << 5)
-#define S3C2412_NFCONT_nFCE1 (1 << 2)
-#define S3C2412_NFCONT_nFCE0 (1 << 1)
+#define S3C2412_NFCONT_NFCE1 (1 << 2)
+#define S3C2412_NFCONT_NFCE0 (1 << 1)
#define S3C2412_NFSTAT_ECC_ENCDONE (1 << 7)
#define S3C2412_NFSTAT_ECC_DECDONE (1 << 6)
#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1 << 5)
-#define S3C2412_NFSTAT_RnB_CHANGE (1 << 4)
-#define S3C2412_NFSTAT_nFCE1 (1 << 3)
-#define S3C2412_NFSTAT_nFCE0 (1 << 2)
-#define S3C2412_NFSTAT_Res1 (1 << 1)
+#define S3C2412_NFSTAT_RNB_CHANGE (1 << 4)
+#define S3C2412_NFSTAT_NFCE1 (1 << 3)
+#define S3C2412_NFSTAT_NFCE0 (1 << 2)
+#define S3C2412_NFSTAT_RES1 (1 << 1)
#define S3C2412_NFSTAT_READY (1 << 0)
#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)
diff --git a/src/flash/nor/aduc702x.c b/src/flash/nor/aduc702x.c
index b7d2299f7..492b65813 100644
--- a/src/flash/nor/aduc702x.c
+++ b/src/flash/nor/aduc702x.c
@@ -31,15 +31,15 @@ static int aduc702x_build_sector_list(struct flash_bank *bank);
static int aduc702x_check_flash_completion(struct target *target, unsigned int timeout_ms);
static int aduc702x_set_write_enable(struct target *target, int enable);
-#define ADUC702x_FLASH 0xfffff800
-#define ADUC702x_FLASH_FEESTA (0*4)
-#define ADUC702x_FLASH_FEEMOD (1*4)
-#define ADUC702x_FLASH_FEECON (2*4)
-#define ADUC702x_FLASH_FEEDAT (3*4)
-#define ADUC702x_FLASH_FEEADR (4*4)
-#define ADUC702x_FLASH_FEESIGN (5*4)
-#define ADUC702x_FLASH_FEEPRO (6*4)
-#define ADUC702x_FLASH_FEEHIDE (7*4)
+#define ADUC702X_FLASH 0xfffff800
+#define ADUC702X_FLASH_FEESTA (0*4)
+#define ADUC702X_FLASH_FEEMOD (1*4)
+#define ADUC702X_FLASH_FEECON (2*4)
+#define ADUC702X_FLASH_FEEDAT (3*4)
+#define ADUC702X_FLASH_FEEADR (4*4)
+#define ADUC702X_FLASH_FEESIGN (5*4)
+#define ADUC702X_FLASH_FEEPRO (6*4)
+#define ADUC702X_FLASH_FEEHIDE (7*4)
/* flash bank aduc702x 0 0 0 0 <target#>
* The ADC7019-28 devices all have the same flash layout */
@@ -87,9 +87,9 @@ static int aduc702x_erase(struct flash_bank *bank, unsigned int first,
/* mass erase */
if (((first | last) == 0) || ((first == 0) && (last >= bank->num_sectors))) {
LOG_DEBUG("performing mass erase.");
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, 0x3cff);
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, 0xffc3);
- target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x06);
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEDAT, 0x3cff);
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEADR, 0xffc3);
+ target_write_u8(target, ADUC702X_FLASH + ADUC702X_FLASH_FEECON, 0x06);
if (aduc702x_check_flash_completion(target, 3500) != ERROR_OK) {
LOG_ERROR("mass erase failed");
@@ -106,8 +106,8 @@ static int aduc702x_erase(struct flash_bank *bank, unsigned int first,
for (x = 0; x < count; ++x) {
adr = bank->base + ((first + x) * 512);
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, adr);
- target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x05);
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEADR, adr);
+ target_write_u8(target, ADUC702X_FLASH + ADUC702X_FLASH_FEECON, 0x05);
if (aduc702x_check_flash_completion(target, 50) != ERROR_OK) {
LOG_ERROR("failed to erase sector at address 0x%08lX", adr);
@@ -283,7 +283,7 @@ static int aduc702x_write_single(struct flash_bank *bank,
for (x = 0; x < count; x += 2) {
/* FEEADR = address */
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, offset + x);
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEADR, offset + x);
/* set up data */
if ((x + 1) == count) {
@@ -292,10 +292,10 @@ static int aduc702x_write_single(struct flash_bank *bank,
} else
b = buffer[x + 1];
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, buffer[x] | (b << 8));
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEDAT, buffer[x] | (b << 8));
/* do single-write command */
- target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x02);
+ target_write_u8(target, ADUC702X_FLASH + ADUC702X_FLASH_FEECON, 0x02);
if (aduc702x_check_flash_completion(target, 1) != ERROR_OK) {
LOG_ERROR("single write failed for address 0x%08lX",
@@ -345,7 +345,7 @@ static int aduc702x_probe(struct flash_bank *bank)
static int aduc702x_set_write_enable(struct target *target, int enable)
{
/* don't bother to preserve int enable bit here */
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEMOD, enable ? 8 : 0);
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEMOD, enable ? 8 : 0);
return ERROR_OK;
}
@@ -361,7 +361,7 @@ static int aduc702x_check_flash_completion(struct target *target, unsigned int t
int64_t endtime = timeval_ms() + timeout_ms;
while (1) {
- target_read_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEESTA, &v);
+ target_read_u8(target, ADUC702X_FLASH + ADUC702X_FLASH_FEESTA, &v);
if ((v & 4) == 0)
break;
alive_sleep(1);
diff --git a/src/flash/nor/ambiqmicro.c b/src/flash/nor/ambiqmicro.c
index c4c69ce2b..162e1bb78 100644
--- a/src/flash/nor/ambiqmicro.c
+++ b/src/flash/nor/ambiqmicro.c
@@ -123,7 +123,7 @@ static struct {
uint8_t class;
uint8_t partno;
const char *partname;
-} ambiqmicroParts[6] = {
+} ambiqmicro_parts[6] = {
{0xFF, 0x00, "Unknown"},
{0x01, 0x00, "Apollo"},
{0x02, 0x00, "Apollo2"},
@@ -132,7 +132,7 @@ static struct {
{0x05, 0x00, "Apollo"},
};
-static char *ambiqmicroClassname[6] = {
+static char *ambiqmicro_classname[6] = {
"Unknown", "Apollo", "Apollo2", "Unknown", "Unknown", "Apollo"
};
@@ -172,10 +172,10 @@ static int get_ambiqmicro_info(struct flash_bank *bank, struct command_invocatio
}
/* Check class name in range. */
- if (ambiqmicro_info->target_class < sizeof(ambiqmicroClassname))
- classname = ambiqmicroClassname[ambiqmicro_info->target_class];
+ if (ambiqmicro_info->target_class < sizeof(ambiqmicro_classname))
+ classname = ambiqmicro_classname[ambiqmicro_info->target_class];
else
- classname = ambiqmicroClassname[0];
+ classname = ambiqmicro_classname[0];
command_print_sameline(cmd, "\nAmbiq Micro information: Chip is "
"class %d (%s) %s\n",
@@ -195,24 +195,24 @@ static int ambiqmicro_read_part_info(struct flash_bank *bank)
{
struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
struct target *target = bank->target;
- uint32_t PartNum = 0;
+ uint32_t part_num = 0;
int retval;
/*
* Read Part Number.
*/
- retval = target_read_u32(target, 0x40020000, &PartNum);
+ retval = target_read_u32(target, 0x40020000, &part_num);
if (retval != ERROR_OK) {
- LOG_ERROR("status(0x%x):Could not read PartNum.\n", retval);
- /* Set PartNum to default device */
- PartNum = 0;
+ LOG_ERROR("status(0x%x):Could not read part_num.\n", retval);
+ /* Set part_num to default device */
+ part_num = 0;
}
- LOG_DEBUG("Part number: 0x%" PRIx32, PartNum);
+ LOG_DEBUG("Part number: 0x%" PRIx32, part_num);
/*
* Determine device class.
*/
- ambiqmicro_info->target_class = (PartNum & 0xFF000000) >> 24;
+ ambiqmicro_info->target_class = (part_num & 0xFF000000) >> 24;
switch (ambiqmicro_info->target_class) {
case 1: /* 1 - Apollo */
@@ -220,9 +220,9 @@ static int ambiqmicro_read_part_info(struct flash_bank *bank)
bank->base = bank->bank_number * 0x40000;
ambiqmicro_info->pagesize = 2048;
ambiqmicro_info->flshsiz =
- apollo_flash_size[(PartNum & 0x00F00000) >> 20];
+ apollo_flash_size[(part_num & 0x00F00000) >> 20];
ambiqmicro_info->sramsiz =
- apollo_sram_size[(PartNum & 0x000F0000) >> 16];
+ apollo_sram_size[(part_num & 0x000F0000) >> 16];
ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz /
ambiqmicro_info->pagesize;
if (ambiqmicro_info->num_pages > 128) {
@@ -248,12 +248,12 @@ static int ambiqmicro_read_part_info(struct flash_bank *bank)
}
- if (ambiqmicro_info->target_class < ARRAY_SIZE(ambiqmicroParts))
+ if (ambiqmicro_info->target_class < ARRAY_SIZE(ambiqmicro_parts))
ambiqmicro_info->target_name =
- ambiqmicroParts[ambiqmicro_info->target_class].partname;
+ ambiqmicro_parts[ambiqmicro_info->target_class].partname;
else
ambiqmicro_info->target_name =
- ambiqmicroParts[0].partname;
+ ambiqmicro_parts[0].partname;
LOG_DEBUG("num_pages: %" PRIu32 ", pagesize: %" PRIu32 ", flash: %" PRIu32 ", sram: %" PRIu32,
ambiqmicro_info->num_pages,
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index e0c779a33..15ca29628 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -104,10 +104,10 @@
#define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
#define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
-#define offset_EFC_FMR 0
-#define offset_EFC_FCR 4
-#define offset_EFC_FSR 8
-#define offset_EFC_FRR 12
+#define OFFSET_EFC_FMR 0
+#define OFFSET_EFC_FCR 4
+#define OFFSET_EFC_FSR 8
+#define OFFSET_EFC_FRR 12
extern const struct flash_driver at91sam3_flash;
@@ -191,13 +191,13 @@ struct sam3_bank_private {
/* DANGER: THERE ARE DRAGONS HERE.. */
/* NOTE: If you add more 'ghost' pointers */
/* be aware that you must *manually* update */
- /* these pointers in the function sam3_GetDetails() */
+ /* these pointers in the function sam3_get_details() */
/* See the comment "Here there be dragons" */
/* so we can find the chip we belong to */
- struct sam3_chip *pChip;
+ struct sam3_chip *chip;
/* so we can find the original bank pointer */
- struct flash_bank *pBank;
+ struct flash_bank *bank;
unsigned bank_number;
uint32_t controller_address;
uint32_t base_address;
@@ -214,7 +214,7 @@ struct sam3_chip_details {
/* note: If you add pointers here */
/* be careful about them as they */
/* may need to be updated inside */
- /* the function: "sam3_GetDetails() */
+ /* the function: "sam3_get_details() */
/* which copy/overwrites the */
/* 'runtime' copy of this structure */
uint32_t chipid_cidr;
@@ -244,7 +244,7 @@ struct sam3_chip {
struct sam3_reg_list {
uint32_t address; size_t struct_offset; const char *name;
- void (*explain_func)(struct sam3_chip *pInfo);
+ void (*explain_func)(struct sam3_chip *chip);
};
static struct sam3_chip *all_sam3_chips;
@@ -277,7 +277,7 @@ static struct sam3_chip *get_current_sam3(struct command_invocation *cmd)
return NULL;
}
-/* these are used to *initialize* the "pChip->details" structure. */
+/* these are used to *initialize* the "chip->details" structure. */
static const struct sam3_chip_details all_sam3_details[] = {
/* Start at91sam3u* series */
{
@@ -307,8 +307,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
@@ -323,8 +323,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_U,
.controller_address = 0x400e0a00,
@@ -358,8 +358,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
@@ -400,8 +400,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
@@ -449,8 +449,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
@@ -464,8 +464,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_U,
.controller_address = 0x400e0a00,
@@ -499,8 +499,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
@@ -541,8 +541,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
@@ -579,8 +579,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -612,8 +612,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -644,8 +644,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -676,8 +676,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -708,8 +708,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -740,8 +740,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
@@ -755,8 +755,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_SD,
.controller_address = 0x400e0a00,
@@ -780,8 +780,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
@@ -795,8 +795,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_SD,
.controller_address = 0x400e0a00,
@@ -820,8 +820,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
@@ -835,8 +835,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_SD,
.controller_address = 0x400e0a00,
@@ -860,8 +860,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -892,8 +892,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -924,8 +924,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -956,8 +956,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -988,8 +988,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -1020,8 +1020,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -1052,8 +1052,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -1102,8 +1102,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1151,8 +1151,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1200,8 +1200,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1249,8 +1249,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1298,8 +1298,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1347,8 +1347,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1396,8 +1396,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1445,8 +1445,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1494,8 +1494,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1528,8 +1528,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1562,8 +1562,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1596,8 +1596,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1630,8 +1630,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1681,8 +1681,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
@@ -1696,8 +1696,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
@@ -1722,8 +1722,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
@@ -1737,8 +1737,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_256K_AX,
.controller_address = 0x400e0c00,
@@ -1781,8 +1781,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
@@ -1796,8 +1796,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
@@ -1823,8 +1823,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
@@ -1838,8 +1838,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
@@ -1864,8 +1864,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
@@ -1879,8 +1879,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
@@ -1905,8 +1905,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
@@ -1920,8 +1920,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
@@ -1946,8 +1946,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
@@ -1961,8 +1961,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_256K_AX,
.controller_address = 0x400e0c00,
@@ -1987,8 +1987,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
@@ -2002,8 +2002,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_256K_AX,
.controller_address = 0x400e0c00,
@@ -2036,14 +2036,14 @@ static const struct sam3_chip_details all_sam3_details[] = {
/**
* Get the current status of the EEFC and
* the value of some status bits (LOCKE, PROGE).
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param v - result goes here
*/
-static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
+static int efc_get_status(struct sam3_bank_private *private, uint32_t *v)
{
int r;
- r = target_read_u32(pPrivate->pChip->target,
- pPrivate->controller_address + offset_EFC_FSR,
+ r = target_read_u32(private->chip->target,
+ private->controller_address + OFFSET_EFC_FSR,
v);
LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
(unsigned int)(*v),
@@ -2056,15 +2056,15 @@ static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
/**
* Get the result of the last executed command.
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param v - result goes here
*/
-static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
+static int efc_get_result(struct sam3_bank_private *private, uint32_t *v)
{
int r;
uint32_t rv;
- r = target_read_u32(pPrivate->pChip->target,
- pPrivate->controller_address + offset_EFC_FRR,
+ r = target_read_u32(private->chip->target,
+ private->controller_address + OFFSET_EFC_FRR,
&rv);
if (v)
*v = rv;
@@ -2072,7 +2072,7 @@ static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
return r;
}
-static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
+static int efc_start_command(struct sam3_bank_private *private,
unsigned command, unsigned argument)
{
uint32_t n, v;
@@ -2093,16 +2093,16 @@ do_retry:
/* case AT91C_EFC_FCMD_EPA: */
case AT91C_EFC_FCMD_SLB:
case AT91C_EFC_FCMD_CLB:
- n = (pPrivate->size_bytes / pPrivate->page_size);
+ n = (private->size_bytes / private->page_size);
if (argument >= n)
LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
break;
case AT91C_EFC_FCMD_SFB:
case AT91C_EFC_FCMD_CFB:
- if (argument >= pPrivate->pChip->details.n_gpnvms) {
+ if (argument >= private->chip->details.n_gpnvms) {
LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
- pPrivate->pChip->details.n_gpnvms);
+ private->chip->details.n_gpnvms);
}
break;
@@ -2127,7 +2127,7 @@ do_retry:
/* Situation (2) - normal, finished reading unique id */
} else {
/* it should be "ready" */
- EFC_GetStatus(pPrivate, &v);
+ efc_get_status(private, &v);
if (v & 1) {
/* then it is ready */
/* we go on */
@@ -2136,14 +2136,14 @@ do_retry:
/* we have done this before */
/* the controller is not responding. */
LOG_ERROR("flash controller(%d) is not ready! Error",
- pPrivate->bank_number);
+ private->bank_number);
return ERROR_FAIL;
} else {
retry++;
LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
- pPrivate->bank_number);
+ private->bank_number);
/* we do that by issuing the *STOP* command */
- EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
+ efc_start_command(private, AT91C_EFC_FCMD_SPUI, 0);
/* above is recursive, and further recursion is blocked by */
/* if (command == AT91C_EFC_FCMD_SPUI) above */
goto do_retry;
@@ -2153,8 +2153,8 @@ do_retry:
v = (0x5A << 24) | (argument << 8) | command;
LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
- r = target_write_u32(pPrivate->pBank->target,
- pPrivate->controller_address + offset_EFC_FCR, v);
+ r = target_write_u32(private->bank->target,
+ private->controller_address + OFFSET_EFC_FCR, v);
if (r != ERROR_OK)
LOG_DEBUG("Error Write failed");
return r;
@@ -2162,12 +2162,12 @@ do_retry:
/**
* Performs the given command and wait until its completion (or an error).
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param command - Command to perform.
* @param argument - Optional command argument.
* @param status - put command status bits here
*/
-static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
+static int efc_perform_command(struct sam3_bank_private *private,
unsigned command,
unsigned argument,
uint32_t *status)
@@ -2181,14 +2181,14 @@ static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
if (status)
*status = 0;
- r = EFC_StartCommand(pPrivate, command, argument);
+ r = efc_start_command(private, command, argument);
if (r != ERROR_OK)
return r;
ms_end = 500 + timeval_ms();
do {
- r = EFC_GetStatus(pPrivate, &v);
+ r = efc_get_status(private, &v);
if (r != ERROR_OK)
return r;
ms_now = timeval_ms();
@@ -2208,87 +2208,87 @@ static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
/**
* Read the unique ID.
- * @param pPrivate - info about the bank
- * The unique ID is stored in the 'pPrivate' structure.
+ * @param private - info about the bank
+ * The unique ID is stored in the 'private' structure.
*/
-static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
+static int flashd_read_uid(struct sam3_bank_private *private)
{
int r;
uint32_t v;
int x;
/* assume 0 */
- pPrivate->pChip->cfg.unique_id[0] = 0;
- pPrivate->pChip->cfg.unique_id[1] = 0;
- pPrivate->pChip->cfg.unique_id[2] = 0;
- pPrivate->pChip->cfg.unique_id[3] = 0;
+ private->chip->cfg.unique_id[0] = 0;
+ private->chip->cfg.unique_id[1] = 0;
+ private->chip->cfg.unique_id[2] = 0;
+ private->chip->cfg.unique_id[3] = 0;
LOG_DEBUG("Begin");
- r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
+ r = efc_start_command(private, AT91C_EFC_FCMD_STUI, 0);
if (r < 0)
return r;
for (x = 0; x < 4; x++) {
- r = target_read_u32(pPrivate->pChip->target,
- pPrivate->pBank->base + (x * 4),
+ r = target_read_u32(private->chip->target,
+ private->bank->base + (x * 4),
&v);
if (r < 0)
return r;
- pPrivate->pChip->cfg.unique_id[x] = v;
+ private->chip->cfg.unique_id[x] = v;
}
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_SPUI, 0, NULL);
LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
r,
- (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
- (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
- (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
- (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
+ (unsigned int)(private->chip->cfg.unique_id[0]),
+ (unsigned int)(private->chip->cfg.unique_id[1]),
+ (unsigned int)(private->chip->cfg.unique_id[2]),
+ (unsigned int)(private->chip->cfg.unique_id[3]));
return r;
}
/**
* Erases the entire flash.
- * @param pPrivate - the info about the bank.
+ * @param private - the info about the bank.
*/
-static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
+static int flashd_erase_entire_bank(struct sam3_bank_private *private)
{
LOG_DEBUG("Here");
- return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
+ return efc_perform_command(private, AT91C_EFC_FCMD_EA, 0, NULL);
}
/**
* Gets current GPNVM state.
- * @param pPrivate - info about the bank.
+ * @param private - info about the bank.
* @param gpnvm - GPNVM bit index.
* @param puthere - result stored here.
*/
/* ------------------------------------------------------------------------------ */
-static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
+static int flashd_get_gpnvm(struct sam3_bank_private *private, unsigned gpnvm, unsigned *puthere)
{
uint32_t v;
int r;
LOG_DEBUG("Here");
- if (pPrivate->bank_number != 0) {
+ if (private->bank_number != 0) {
LOG_ERROR("GPNVM only works with Bank0");
return ERROR_FAIL;
}
- if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
+ if (gpnvm >= private->chip->details.n_gpnvms) {
LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
- gpnvm, pPrivate->pChip->details.n_gpnvms);
+ gpnvm, private->chip->details.n_gpnvms);
return ERROR_FAIL;
}
/* Get GPNVMs status */
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_GFB, 0, NULL);
if (r != ERROR_OK) {
LOG_ERROR("Failed");
return r;
}
- r = EFC_GetResult(pPrivate, &v);
+ r = efc_get_result(private, &v);
if (puthere) {
/* Check if GPNVM is set */
@@ -2301,59 +2301,59 @@ static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, u
/**
* Clears the selected GPNVM bit.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param gpnvm GPNVM index.
* @returns 0 if successful; otherwise returns an error code.
*/
-static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
+static int flashd_clr_gpnvm(struct sam3_bank_private *private, unsigned gpnvm)
{
int r;
unsigned v;
LOG_DEBUG("Here");
- if (pPrivate->bank_number != 0) {
+ if (private->bank_number != 0) {
LOG_ERROR("GPNVM only works with Bank0");
return ERROR_FAIL;
}
- if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
+ if (gpnvm >= private->chip->details.n_gpnvms) {
LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
- gpnvm, pPrivate->pChip->details.n_gpnvms);
+ gpnvm, private->chip->details.n_gpnvms);
return ERROR_FAIL;
}
- r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
+ r = flashd_get_gpnvm(private, gpnvm, &v);
if (r != ERROR_OK) {
LOG_DEBUG("Failed: %d", r);
return r;
}
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
LOG_DEBUG("End: %d", r);
return r;
}
/**
* Sets the selected GPNVM bit.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param gpnvm GPNVM index.
*/
-static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
+static int flashd_set_gpnvm(struct sam3_bank_private *private, unsigned gpnvm)
{
int r;
unsigned v;
- if (pPrivate->bank_number != 0) {
+ if (private->bank_number != 0) {
LOG_ERROR("GPNVM only works with Bank0");
return ERROR_FAIL;
}
- if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
+ if (gpnvm >= private->chip->details.n_gpnvms) {
LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
- gpnvm, pPrivate->pChip->details.n_gpnvms);
+ gpnvm, private->chip->details.n_gpnvms);
return ERROR_FAIL;
}
- r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
+ r = flashd_get_gpnvm(private, gpnvm, &v);
if (r != ERROR_OK)
return r;
if (v) {
@@ -2361,35 +2361,35 @@ static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
r = ERROR_OK;
} else {
/* set it */
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
}
return r;
}
/**
* Returns a bit field (at most 64) of locked regions within a page.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param v where to store locked bits
*/
-static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
+static int flashd_get_lock_bits(struct sam3_bank_private *private, uint32_t *v)
{
int r;
LOG_DEBUG("Here");
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_GLB, 0, NULL);
if (r == ERROR_OK)
- r = EFC_GetResult(pPrivate, v);
+ r = efc_get_result(private, v);
LOG_DEBUG("End: %d", r);
return r;
}
/**
* Unlocks all the regions in the given address range.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param start_sector first sector to unlock
* @param end_sector last (inclusive) to unlock
*/
-static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
+static int flashd_unlock(struct sam3_bank_private *private,
unsigned start_sector,
unsigned end_sector)
{
@@ -2398,13 +2398,13 @@ static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
uint32_t pg;
uint32_t pages_per_sector;
- pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
+ pages_per_sector = private->sector_size / private->page_size;
/* Unlock all pages */
while (start_sector <= end_sector) {
pg = start_sector * pages_per_sector;
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_CLB, pg, &status);
if (r != ERROR_OK)
return r;
start_sector++;
@@ -2415,11 +2415,11 @@ static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
/**
* Locks regions
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param start_sector - first sector to lock
* @param end_sector - last sector (inclusive) to lock
*/
-static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
+static int flashd_lock(struct sam3_bank_private *private,
unsigned start_sector,
unsigned end_sector)
{
@@ -2428,13 +2428,13 @@ static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
uint32_t pages_per_sector;
int r;
- pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
+ pages_per_sector = private->sector_size / private->page_size;
/* Lock all pages */
while (start_sector <= end_sector) {
pg = start_sector * pages_per_sector;
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_SLB, pg, &status);
if (r != ERROR_OK)
return r;
start_sector++;
@@ -2446,7 +2446,7 @@ static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
/* begin helpful debug code */
/* print the fieldname, the field value, in dec & hex, and return field value */
-static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
+static uint32_t sam3_reg_fieldname(struct sam3_chip *chip,
const char *regname,
uint32_t value,
unsigned shift,
@@ -2598,72 +2598,72 @@ static const char *const _rc_freq[] = {
"4 MHz", "8 MHz", "12 MHz", "reserved"
};
-static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
+static void sam3_explain_ckgr_mor(struct sam3_chip *chip)
{
uint32_t v;
uint32_t rcen;
- v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
+ v = sam3_reg_fieldname(chip, "MOSCXTEN", chip->cfg.CKGR_MOR, 0, 1);
LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
- v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
+ v = sam3_reg_fieldname(chip, "MOSCXTBY", chip->cfg.CKGR_MOR, 1, 1);
LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
- rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
+ rcen = sam3_reg_fieldname(chip, "MOSCRCEN", chip->cfg.CKGR_MOR, 3, 1);
LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
- v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
+ v = sam3_reg_fieldname(chip, "MOSCRCF", chip->cfg.CKGR_MOR, 4, 3);
LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
- pChip->cfg.rc_freq = 0;
+ chip->cfg.rc_freq = 0;
if (rcen) {
switch (v) {
default:
- pChip->cfg.rc_freq = 0;
+ chip->cfg.rc_freq = 0;
break;
case 0:
- pChip->cfg.rc_freq = 4 * 1000 * 1000;
+ chip->cfg.rc_freq = 4 * 1000 * 1000;
break;
case 1:
- pChip->cfg.rc_freq = 8 * 1000 * 1000;
+ chip->cfg.rc_freq = 8 * 1000 * 1000;
break;
...
[truncated message content] |
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-02 16:09:36
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 12219255c625b048b04d8cfbd7ad59eee4a39442 (commit)
from cff0e417da58adef1ceef9a63a99412c2cc87ff3 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 12219255c625b048b04d8cfbd7ad59eee4a39442
Author: Antonio Borneo <bor...@gm...>
Date: Sun Apr 25 16:07:15 2021 +0200
flash/nor/cfi: fix CamelCase symbols in cfi_spansion_pri_ext
The struct cfi_spansion_pri_ext has few symbols in CamelCase.
Change all them accordingly to OpenOCD coding style.
Patch created automatically with the script below:
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
(cat << EOF
VppMin vpp_min
VppMax vpp_max
TopBottom top_bottom
TmpBlkUnprotect tmp_blk_unprotected
SimultaneousOps simultaneous_ops
SiliconRevision silicon_revision
PageMode page_mode
EraseSuspend erase_suspend
BurstMode burst_mode
BlkProtUnprot blk_prot_unprot
BlkProt blk_prot
EOF
) | while read a b; do
sed -i "s/$a/$b/g" src/flash/nor/*cfi*
done
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
Change-Id: I135331539ca9aa84765fdffc51c87a07a46ee77a
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/6298
Tested-by: jenkins
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 666316932..a03179aec 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -561,55 +561,55 @@ static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
- retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &pri_ext->SiliconRevision);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &pri_ext->silicon_revision);
if (retval != ERROR_OK)
return retval;
- retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &pri_ext->EraseSuspend);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &pri_ext->erase_suspend);
if (retval != ERROR_OK)
return retval;
- retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &pri_ext->BlkProt);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &pri_ext->blk_prot);
if (retval != ERROR_OK)
return retval;
- retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &pri_ext->TmpBlkUnprotect);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &pri_ext->tmp_blk_unprotected);
if (retval != ERROR_OK)
return retval;
- retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->BlkProtUnprot);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->blk_prot_unprot);
if (retval != ERROR_OK)
return retval;
- retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10, &pri_ext->SimultaneousOps);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10, &pri_ext->simultaneous_ops);
if (retval != ERROR_OK)
return retval;
- retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11, &pri_ext->BurstMode);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11, &pri_ext->burst_mode);
if (retval != ERROR_OK)
return retval;
- retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12, &pri_ext->PageMode);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12, &pri_ext->page_mode);
if (retval != ERROR_OK)
return retval;
- retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13, &pri_ext->VppMin);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13, &pri_ext->vpp_min);
if (retval != ERROR_OK)
return retval;
- retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14, &pri_ext->VppMax);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14, &pri_ext->vpp_max);
if (retval != ERROR_OK)
return retval;
- retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15, &pri_ext->TopBottom);
+ retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15, &pri_ext->top_bottom);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x",
- pri_ext->SiliconRevision, pri_ext->EraseSuspend, pri_ext->BlkProt);
+ pri_ext->silicon_revision, pri_ext->erase_suspend, pri_ext->blk_prot);
LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, "
- "Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
- pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
+ "Simultaneous Ops: 0x%x", pri_ext->tmp_blk_unprotected,
+ pri_ext->blk_prot_unprot, pri_ext->simultaneous_ops);
- LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
+ LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->burst_mode, pri_ext->page_mode);
LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
- (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
- (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
+ (pri_ext->vpp_min & 0xf0) >> 4, pri_ext->vpp_min & 0x0f,
+ (pri_ext->vpp_max & 0xf0) >> 4, pri_ext->vpp_max & 0x0f);
- LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
+ LOG_DEBUG("WP# protection 0x%x", pri_ext->top_bottom);
return ERROR_OK;
}
@@ -696,20 +696,20 @@ static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
atmel_pri_ext.page_mode);
if (atmel_pri_ext.features & 0x02)
- pri_ext->EraseSuspend = 2;
+ pri_ext->erase_suspend = 2;
/* some chips got it backwards... */
if (cfi_info->device_id == AT49BV6416 ||
cfi_info->device_id == AT49BV6416T) {
if (atmel_pri_ext.bottom_boot)
- pri_ext->TopBottom = 3;
+ pri_ext->top_bottom = 3;
else
- pri_ext->TopBottom = 2;
+ pri_ext->top_bottom = 2;
} else {
if (atmel_pri_ext.bottom_boot)
- pri_ext->TopBottom = 2;
+ pri_ext->top_bottom = 2;
else
- pri_ext->TopBottom = 3;
+ pri_ext->top_bottom = 3;
}
pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
@@ -740,16 +740,16 @@ static int cfi_spansion_info(struct flash_bank *bank, struct command_invocation
pri_ext->major_version, pri_ext->minor_version);
command_print_sameline(cmd, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
- (pri_ext->SiliconRevision) >> 2,
- (pri_ext->SiliconRevision) & 0x03);
+ (pri_ext->silicon_revision) >> 2,
+ (pri_ext->silicon_revision) & 0x03);
command_print_sameline(cmd, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
- pri_ext->EraseSuspend,
- pri_ext->BlkProt);
+ pri_ext->erase_suspend,
+ pri_ext->blk_prot);
command_print_sameline(cmd, "VppMin: %u.%x, VppMax: %u.%x\n",
- (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
- (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
+ (pri_ext->vpp_min & 0xf0) >> 4, pri_ext->vpp_min & 0x0f,
+ (pri_ext->vpp_max & 0xf0) >> 4, pri_ext->vpp_max & 0x0f);
return ERROR_OK;
}
@@ -2480,7 +2480,7 @@ static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, const void *pa
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
(void) param;
- if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3)) {
+ if ((pri_ext->_reversed_geometry) || (pri_ext->top_bottom == 3)) {
LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
for (unsigned int i = 0; i < cfi_info->num_erase_regions / 2; i++) {
diff --git a/src/flash/nor/cfi.h b/src/flash/nor/cfi.h
index 80633f494..f8ca290a5 100644
--- a/src/flash/nor/cfi.h
+++ b/src/flash/nor/cfi.h
@@ -108,17 +108,17 @@ struct cfi_spansion_pri_ext {
uint8_t pri[3];
uint8_t major_version;
uint8_t minor_version;
- uint8_t SiliconRevision; /* bits 1-0: Address Sensitive Unlock */
- uint8_t EraseSuspend;
- uint8_t BlkProt;
- uint8_t TmpBlkUnprotect;
- uint8_t BlkProtUnprot;
- uint8_t SimultaneousOps;
- uint8_t BurstMode;
- uint8_t PageMode;
- uint8_t VppMin;
- uint8_t VppMax;
- uint8_t TopBottom;
+ uint8_t silicon_revision; /* bits 1-0: Address Sensitive Unlock */
+ uint8_t erase_suspend;
+ uint8_t blk_prot;
+ uint8_t tmp_blk_unprotected;
+ uint8_t blk_prot_unprot;
+ uint8_t simultaneous_ops;
+ uint8_t burst_mode;
+ uint8_t page_mode;
+ uint8_t vpp_min;
+ uint8_t vpp_max;
+ uint8_t top_bottom;
int _reversed_geometry;
uint32_t _unlock1;
uint32_t _unlock2;
diff --git a/src/flash/nor/non_cfi.c b/src/flash/nor/non_cfi.c
index a817966c6..1566f3858 100644
--- a/src/flash/nor/non_cfi.c
+++ b/src/flash/nor/non_cfi.c
@@ -536,17 +536,17 @@ void cfi_fixup_non_cfi(struct flash_bank *bank)
pri_ext->major_version = '1';
pri_ext->minor_version = '0';
- pri_ext->SiliconRevision = 0x0;
- pri_ext->EraseSuspend = 0x0;
- pri_ext->BlkProt = 0x0;
- pri_ext->TmpBlkUnprotect = 0x0;
- pri_ext->BlkProtUnprot = 0x0;
- pri_ext->SimultaneousOps = 0x0;
- pri_ext->BurstMode = 0x0;
- pri_ext->PageMode = 0x0;
- pri_ext->VppMin = 0x0;
- pri_ext->VppMax = 0x0;
- pri_ext->TopBottom = 0x0;
+ pri_ext->silicon_revision = 0x0;
+ pri_ext->erase_suspend = 0x0;
+ pri_ext->blk_prot = 0x0;
+ pri_ext->tmp_blk_unprotected = 0x0;
+ pri_ext->blk_prot_unprot = 0x0;
+ pri_ext->simultaneous_ops = 0x0;
+ pri_ext->burst_mode = 0x0;
+ pri_ext->page_mode = 0x0;
+ pri_ext->vpp_min = 0x0;
+ pri_ext->vpp_max = 0x0;
+ pri_ext->top_bottom = 0x0;
pri_ext->_unlock1 = 0x5555;
pri_ext->_unlock2 = 0x2AAA;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/cfi.c | 60 ++++++++++++++++++++++++-------------------------
src/flash/nor/cfi.h | 22 +++++++++---------
src/flash/nor/non_cfi.c | 22 +++++++++---------
3 files changed, 52 insertions(+), 52 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-06-27 13:58:36
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via cff0e417da58adef1ceef9a63a99412c2cc87ff3 (commit)
from 94ba5219ede27d6193ebac15af0468de60c9bfca (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit cff0e417da58adef1ceef9a63a99412c2cc87ff3
Author: Antonio Borneo <bor...@gm...>
Date: Wed Jun 23 16:52:16 2021 +0200
stlink: fix SIGSEGV with libusb v1.0.24-33-g32a2206 (11618)
The stlink driver incorrectly uses a NULL pointer for libusb's
struct libusb_context.
The correct value to be used is local in libusb_helper.c.
Move in the helper file, in a wrapper function, the only call that
requires the above value, and let stlink driver to use this
wrapper.
This issue has not triggered any visible problem until a code
refactoring [1] in libusb has made OpenOCD crashing on Windows and
on MacOS.
Change-Id: Id1818c8af7cf0d4d17dfa1d22aad079da01ef740
Signed-off-by: Antonio Borneo <bor...@gm...>
Fixes: https://sourceforge.net/p/openocd/tickets/308/
Fixes: https://github.com/libusb/libusb/issues/928/
Fixes: 42d8fa899c6a ("stlink_usb: Submit multiple USB URBs at once to improve performance")
Link: [1] https://github.com/libusb/libusb/commit/32a22069428c
Reported-by: Andrzej SierżÄga <as...@gm...>
Co-developed-by: Andrzej SierżÄga <as...@gm...>
Co-developed-by: Xiaofan Chen <xia...@gm...>
Reviewed-on: http://openocd.zylin.com/6331
Tested-by: jenkins
Reviewed-by: Marc Schink <de...@za...>
Reviewed-by: Xiaofan <xia...@gm...>
Reviewed-by: Andrzej SierżÄga <as...@gm...>
Reviewed-by: Oleksij Rempel <li...@re...>
Reviewed-by: Andreas Fritiofson <and...@gm...>
diff --git a/src/jtag/drivers/libusb_helper.c b/src/jtag/drivers/libusb_helper.c
index f0122d534..18fe4bad4 100644
--- a/src/jtag/drivers/libusb_helper.c
+++ b/src/jtag/drivers/libusb_helper.c
@@ -363,3 +363,8 @@ int jtag_libusb_get_pid(struct libusb_device *dev, uint16_t *pid)
return ERROR_FAIL;
}
+
+int jtag_libusb_handle_events_completed(int *completed)
+{
+ return libusb_handle_events_completed(jtag_libusb_context, completed);
+}
diff --git a/src/jtag/drivers/libusb_helper.h b/src/jtag/drivers/libusb_helper.h
index fa7d06e28..3e77865d6 100644
--- a/src/jtag/drivers/libusb_helper.h
+++ b/src/jtag/drivers/libusb_helper.h
@@ -60,5 +60,6 @@ int jtag_libusb_choose_interface(struct libusb_device_handle *devh,
unsigned int *usb_write_ep,
int bclass, int subclass, int protocol, int trans_type);
int jtag_libusb_get_pid(struct libusb_device *dev, uint16_t *pid);
+int jtag_libusb_handle_events_completed(int *completed);
#endif /* OPENOCD_JTAG_DRIVERS_LIBUSB_HELPER_H */
diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c
index c68bbb3ca..7b1932b9f 100644
--- a/src/jtag/drivers/stlink_usb.c
+++ b/src/jtag/drivers/stlink_usb.c
@@ -497,13 +497,8 @@ static void sync_transfer_wait_for_completion(struct libusb_transfer *transfer)
{
int r, *completed = transfer->user_data;
- /* Assuming a single libusb context exists. There no existing interface into this
- * module to pass a libusb context.
- */
- struct libusb_context *ctx = NULL;
-
while (!*completed) {
- r = libusb_handle_events_completed(ctx, completed);
+ r = jtag_libusb_handle_events_completed(completed);
if (r < 0) {
if (r == LIBUSB_ERROR_INTERRUPTED)
continue;
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/libusb_helper.c | 5 +++++
src/jtag/drivers/libusb_helper.h | 1 +
src/jtag/drivers/stlink_usb.c | 7 +------
3 files changed, 7 insertions(+), 6 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-06-27 13:58:04
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- Log -----------------------------------------------------------------
commit 94ba5219ede27d6193ebac15af0468de60c9bfca
Author: Marc Schink <de...@za...>
Date: Mon Jun 21 16:18:38 2021 +0200
flash/nor/stm32l4: Fix stm32l4_probe()
The current implementation fails due to the assert() statements in
get_stm32l4_rev_str() and get_stm32l4_bank_type_str(). Rearrange the
code in order to fix the problem.
Change-Id: If19c648dec8ddd3ef2fb801150114104b34c3bf2
Signed-off-by: Marc Schink <de...@za...>
Fixes: 64c2e03b23 ("flash/nor: improved API of flash_driver.info & fixed buffer overruns")
Reviewed-on: http://openocd.zylin.com/6326
Tested-by: jenkins
Reviewed-by: Jan Matyas <ma...@co...>
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index cd6229548..9598345c6 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -1350,7 +1350,6 @@ static const char *get_stm32l4_bank_type_str(struct flash_bank *bank)
{
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
assert(stm32l4_info->part_info);
- assert(stm32l4_info->probed);
return stm32l4_is_otp(bank) ? "OTP" :
stm32l4_info->dual_bank_mode ? "Flash dual" :
"Flash single";
@@ -1372,8 +1371,6 @@ static int stm32l4_probe(struct flash_bank *bank)
return retval;
const uint32_t device_id = stm32l4_info->idcode & 0xFFF;
- const uint16_t rev_id = stm32l4_info->idcode >> 16;
- const char *rev_str = get_stm32l4_rev_str(bank);
for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
if (device_id == stm32l4_parts[n].id) {
@@ -1388,12 +1385,15 @@ static int stm32l4_probe(struct flash_bank *bank)
}
part_info = stm32l4_info->part_info;
- stm32l4_info->flash_regs = stm32l4_info->part_info->default_flash_regs;
+ const char *rev_str = get_stm32l4_rev_str(bank);
+ const uint16_t rev_id = stm32l4_info->idcode >> 16;
LOG_INFO("device idcode = 0x%08" PRIx32 " (%s - Rev %s : 0x%04x - %s-bank)",
stm32l4_info->idcode, part_info->device_str, rev_str, rev_id,
get_stm32l4_bank_type_str(bank));
+ stm32l4_info->flash_regs = stm32l4_info->part_info->default_flash_regs;
+
/* read flash option register */
retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &options);
if (retval != ERROR_OK)
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32l4x.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-06-26 13:42:57
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
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- Log -----------------------------------------------------------------
commit 0478a93ed52fd8ddc0f68434cb2f05f22cbcad70
Author: Marc Schink <de...@za...>
Date: Tue Jun 15 16:49:37 2021 +0200
target/breakpoints: Remove dead code and cleanup
Change-Id: I8027178b6e771753775514a8641a050c6e63a1d5
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/6321
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c
index c060c7cde..dc8f3c573 100644
--- a/src/target/breakpoints.c
+++ b/src/target/breakpoints.c
@@ -50,11 +50,8 @@ static int breakpoint_add_internal(struct target *target,
struct breakpoint **breakpoint_p = &target->breakpoints;
const char *reason;
int retval;
- int n;
- n = 0;
while (breakpoint) {
- n++;
if (breakpoint->address == address) {
/* FIXME don't assume "same address" means "same
* breakpoint" ... check all the parameters before
@@ -114,11 +111,8 @@ static int context_breakpoint_add_internal(struct target *target,
struct breakpoint *breakpoint = target->breakpoints;
struct breakpoint **breakpoint_p = &target->breakpoints;
int retval;
- int n;
- n = 0;
while (breakpoint) {
- n++;
if (breakpoint->asid == asid) {
/* FIXME don't assume "same address" means "same
* breakpoint" ... check all the parameters before
@@ -167,10 +161,8 @@ static int hybrid_breakpoint_add_internal(struct target *target,
struct breakpoint *breakpoint = target->breakpoints;
struct breakpoint **breakpoint_p = &target->breakpoints;
int retval;
- int n;
- n = 0;
+
while (breakpoint) {
- n++;
if ((breakpoint->asid == asid) && (breakpoint->address == address)) {
/* FIXME don't assume "same address" means "same
* breakpoint" ... check all the parameters before
@@ -238,8 +230,9 @@ int breakpoint_add(struct target *target,
head = head->next;
}
return retval;
- } else
+ } else {
return breakpoint_add_internal(target, address, length, type);
+ }
}
int context_breakpoint_add(struct target *target,
@@ -260,8 +253,9 @@ int context_breakpoint_add(struct target *target,
head = head->next;
}
return retval;
- } else
+ } else {
return context_breakpoint_add_internal(target, asid, length, type);
+ }
}
int hybrid_breakpoint_add(struct target *target,
@@ -301,7 +295,7 @@ static void breakpoint_free(struct target *target, struct breakpoint *breakpoint
breakpoint = breakpoint->next;
}
- if (breakpoint == NULL)
+ if (!breakpoint)
return;
retval = target_remove_breakpoint(target, breakpoint);
@@ -346,20 +340,21 @@ static void breakpoint_remove_all_internal(struct target *target)
void breakpoint_remove(struct target *target, target_addr_t address)
{
- int found = 0;
if (target->smp) {
+ unsigned int num_breakpoints = 0;
struct target_list *head;
struct target *curr;
head = target->head;
while (head != (struct target_list *)NULL) {
curr = head->target;
- found += breakpoint_remove_internal(curr, address);
+ num_breakpoints += breakpoint_remove_internal(curr, address);
head = head->next;
}
- if (found == 0)
+ if (!num_breakpoints)
LOG_ERROR("no breakpoint at address " TARGET_ADDR_FMT " found", address);
- } else
+ } else {
breakpoint_remove_internal(target, address);
+ }
}
void breakpoint_remove_all(struct target *target)
@@ -397,9 +392,9 @@ void breakpoint_clear_target(struct target *target)
breakpoint_clear_target_internal(curr);
head = head->next;
}
- } else
+ } else {
breakpoint_clear_target_internal(target);
-
+ }
}
struct breakpoint *breakpoint_find(struct target *target, target_addr_t address)
@@ -494,7 +489,7 @@ static void watchpoint_free(struct target *target, struct watchpoint *watchpoint
watchpoint = watchpoint->next;
}
- if (watchpoint == NULL)
+ if (!watchpoint)
return;
retval = target_remove_watchpoint(target, watchpoint);
LOG_DEBUG("free WPID: %d --> %d", watchpoint->unique_id, retval);
-----------------------------------------------------------------------
Summary of changes:
src/target/breakpoints.c | 33 ++++++++++++++-------------------
1 file changed, 14 insertions(+), 19 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-06-26 13:42:08
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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commit 2044df3dac715e5bf03a2ebac87048f808d1c7b1
Author: Antonio Borneo <bor...@gm...>
Date: Sat Nov 14 16:38:38 2020 +0100
armv7m: replace flag 'stlink' with 'is_hla_target'
The HLA target is not anymore used by ST-Link only, but required
by Nu-Link and TI-ICDI too.
Rename the flag 'stlink' as 'is_hla_target'.
Change-Id: Id2ee2c0a1e8bf1f1e899f7a560140c34eefeeee5
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/6206
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index f3445e152..f3eb90f24 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -239,8 +239,8 @@ struct armv7m_common {
int fp_feature;
uint32_t demcr;
- /* stlink is a high level adapter, does not support all functions */
- bool stlink;
+ /* hla_target uses a high level adapter that does not support all functions */
+ bool is_hla_target;
struct armv7m_trace_config trace_config;
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index d0256b134..c30556c8a 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2031,9 +2031,9 @@ int cortex_m_examine(struct target *target)
struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
struct armv7m_common *armv7m = target_to_armv7m(target);
- /* stlink shares the examine handler but does not support
+ /* hla_target shares the examine handler but does not support
* all its calls */
- if (!armv7m->stlink) {
+ if (!armv7m->is_hla_target) {
if (cortex_m->apsel == DP_APSEL_INVALID) {
/* Search for the MEM-AP */
retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
@@ -2127,7 +2127,7 @@ int cortex_m_examine(struct target *target)
for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++)
armv7m->arm.core_cache->reg_list[idx].exist = false;
- if (!armv7m->stlink) {
+ if (!armv7m->is_hla_target) {
if (cortex_m->core_info->flags & CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K)
/* Cortex-M3/M4 have 4096 bytes autoincrement range,
* s. ARM IHI 0031C: MEM-AP 7.2.2 */
diff --git a/src/target/hla_target.c b/src/target/hla_target.c
index cd57dd207..7688927fe 100644
--- a/src/target/hla_target.c
+++ b/src/target/hla_target.c
@@ -179,7 +179,7 @@ static int adapter_init_arch_info(struct target *target,
armv7m->store_core_reg_u32 = adapter_store_core_reg_u32;
armv7m->examine_debug_reason = adapter_examine_debug_reason;
- armv7m->stlink = true;
+ armv7m->is_hla_target = true;
target_register_timer_callback(hl_handle_target_request, 1,
TARGET_TIMER_TYPE_PERIODIC, target);
-----------------------------------------------------------------------
Summary of changes:
src/target/armv7m.h | 4 ++--
src/target/cortex_m.c | 6 +++---
src/target/hla_target.c | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-06-26 13:41:37
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 873e5c3976eb82589d5a645266b6ae75cb4c2ecf
Author: Marc Schink <de...@za...>
Date: Thu Jun 17 15:50:47 2021 +0200
target/dsp563xx: Use bool data type for 'hardware_breakpoints_cleared'
Change-Id: Ic18973d3e90d74c211b48627bdaac4cf3357b682
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/6324
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c
index 730573347..5ad52b58d 100644
--- a/src/target/dsp563xx.c
+++ b/src/target/dsp563xx.c
@@ -913,7 +913,7 @@ static int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *
dsp563xx_build_reg_cache(target);
struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
- dsp563xx->hardware_breakpoints_cleared = 0;
+ dsp563xx->hardware_breakpoints_cleared = false;
dsp563xx->hardware_breakpoint[0].used = BPU_NONE;
return ERROR_OK;
@@ -1096,7 +1096,7 @@ static int dsp563xx_poll(struct target *target)
if (err != ERROR_OK)
return err;
- dsp563xx->hardware_breakpoints_cleared = 1;
+ dsp563xx->hardware_breakpoints_cleared = true;
}
return ERROR_OK;
diff --git a/src/target/dsp563xx.h b/src/target/dsp563xx.h
index 18428b854..5c3e1d3c7 100644
--- a/src/target/dsp563xx.h
+++ b/src/target/dsp563xx.h
@@ -52,7 +52,7 @@ struct dsp563xx_common {
struct hardware_breakpoint hardware_breakpoint[1];
/*Were the hardware breakpoints cleared on startup?*/
- int hardware_breakpoints_cleared;
+ bool hardware_breakpoints_cleared;
};
struct dsp563xx_core_reg {
commit 56b72b33cfc7014e001fa9e209b62f4b6c009fb5
Author: Marc Schink <de...@za...>
Date: Thu Jun 17 15:47:11 2021 +0200
target/dsp563xx: Handle return values
This fixes 'dead assignment' bugs identified by the clang static analyzer.
Change-Id: I140ed55f0043e06a533f45f50a36887614585b04
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/6323
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c
index 81ea21e81..730573347 100644
--- a/src/target/dsp563xx.c
+++ b/src/target/dsp563xx.c
@@ -1085,8 +1085,17 @@ static int dsp563xx_poll(struct target *target)
if (!dsp563xx->hardware_breakpoints_cleared) {
err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OBCR, 0);
+ if (err != ERROR_OK)
+ return err;
+
err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OMLR0, 0);
+ if (err != ERROR_OK)
+ return err;
+
err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OMLR1, 0);
+ if (err != ERROR_OK)
+ return err;
+
dsp563xx->hardware_breakpoints_cleared = 1;
}
-----------------------------------------------------------------------
Summary of changes:
src/target/dsp563xx.c | 13 +++++++++++--
src/target/dsp563xx.h | 2 +-
2 files changed, 12 insertions(+), 3 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-06-26 13:41:07
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
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commit fb34fd60ca955fe05c31357052aefad5fa1ef08f
Author: Marek Vasut <mar...@gm...>
Date: Sat Jun 12 20:19:30 2021 +0200
tcl/board: Add Renesas Falcon board
Add board configuration for Renesas Falcon board based on the R8A779A0 V3U SoC.
Change-Id: If8369f2e2b97dfea9ccbee2c9b916ef7094f9b92
Signed-off-by: Marek Vasut <mar...@gm...>
Reviewed-on: http://openocd.zylin.com/6315
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/board/renesas_falcon.cfg b/tcl/board/renesas_falcon.cfg
new file mode 100644
index 000000000..c796f85b5
--- /dev/null
+++ b/tcl/board/renesas_falcon.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Renesas R-Car V3U Falcon Board Config
+
+# The Falcon board comes with either an V3U SOC.
+
+echo "\nFalcon:"
+if { ![info exists SOC] } {
+ set SOC V3U
+}
+source [find target/renesas_rcar_gen3.cfg]
commit 7c8a068a40ab81abf0938c3e091bf4e927a47bcd
Author: Marek Vasut <mar...@gm...>
Date: Sun May 30 17:34:10 2021 +0200
tcl/target: Add support for Renesas R8A779A0 V3U SoC
The V3U SoC is unique in that it now has 8x CA76 and CR52,
while the previous SoCs had CA57/CA53/CR7 . This can still
be handled without too complex modifications to the gen3
configuration file, so add the logic to handle it there.
Change-Id: I7ab33eacc1fd379d369988d3d6690d2e82346c7e
Signed-off-by: Marek Vasut <mar...@gm...>
Reviewed-on: http://openocd.zylin.com/6314
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/renesas_rcar_gen3.cfg b/tcl/target/renesas_rcar_gen3.cfg
index 36e654491..334d25568 100644
--- a/tcl/target/renesas_rcar_gen3.cfg
+++ b/tcl/target/renesas_rcar_gen3.cfg
@@ -7,6 +7,7 @@
# H3: Cortex-A57 x 4, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
# M3W: Cortex-A57 x 2, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
# M3N: Cortex-A57 x 2, Cortex-R7 x 2 (Lock-Step)
+# V3U: Cortex-A76 x 8, Cortex-R52 x2 (Lock-Step)
# V3H: Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
# V3M: Cortex-A53 x 2, Cortex-R7 x 2 (Lock-Step)
# E3: Cortex-A53 x 1, Cortex-R7 x 2 (Lock-Step)
@@ -24,6 +25,12 @@ if { [info exists SOC] } {
set _soc H3
}
+set _num_ca53 0
+set _num_ca57 0
+set _num_ca76 0
+set _num_cr52 0
+set _num_cr7 0
+
# Set configuration for each SOC and the default 'BOOT_CORE'
switch $_soc {
H3 {
@@ -75,6 +82,12 @@ switch $_soc {
set _num_cr7 0
set _boot_core CA53
}
+ V3U {
+ set _CHIPNAME r8a779a0
+ set _num_ca76 8
+ set _num_cr52 1
+ set _boot_core CA76
+ }
default {
error "'$_soc' is invalid!"
}
@@ -96,7 +109,7 @@ if { [info exists DAP_TAPID] } {
set _DAP_TAPID 0x5ba00477
}
-echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca53 CA53(s), $_num_cr7 CR7(s)"
+echo "\t$_soc - $_num_ca76 CA76(s), $_num_ca57 CA57(s), $_num_ca53 CA53(s), $_num_cr52 CR52(s), $_num_cr7 CR7(s)"
echo "\tBoot Core - $_boot_core\n"
set _DAPNAME $_CHIPNAME.dap
@@ -105,10 +118,14 @@ set _DAPNAME $_CHIPNAME.dap
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
+set CA76_DBGBASE {0x81410000 0x81510000 0x81610000 0x81710000 0x81c10000 0x81d10000 0x81e10000 0x81f10000}
+set CA76_CTIBASE {0x81420000 0x81520000 0x81620000 0x81720000 0x81c20000 0x81d20000 0x81e20000 0x81f20000}
set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000}
set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000}
+set CR52_DBGBASE 0x80c10000
+set CR52_CTIBASE 0x80c20000
set CR7_DBGBASE 0x80910000
set CR7_CTIBASE 0x80918000
@@ -137,33 +154,41 @@ proc setup_a5x {core_name dbgbase ctibase num boot} {
}
}
-proc setup_cr7 {dbgbase ctibase boot} {
+proc setup_cr7 {core_name dbgbase ctibase num boot} {
global _CHIPNAME
global _DAPNAME
- set _TARGETNAME $_CHIPNAME.r7
- set _CTINAME $_TARGETNAME.cti
- cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr $ctibase
- set _command "target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \
- -ap-num 1 -dbgbase $dbgbase"
- if { $boot == 1 } {
- set _targets "$_TARGETNAME"
- } else {
- set _command "$_command -defer-examine"
+ for { set _core 0 } { $_core < $num } { incr _core } {
+ set _TARGETNAME $_CHIPNAME.$core_name
+ set _CTINAME $_TARGETNAME.cti
+ cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr $ctibase
+ set _command "target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \
+ -ap-num 1 -dbgbase $dbgbase"
+ if { $boot == 1 } {
+ set _targets "$_TARGETNAME"
+ } else {
+ set _command "$_command -defer-examine"
+ }
+ eval $_command
}
- eval $_command
}
# Organize target list based on the boot core
-if { [string equal $_boot_core CA57] } {
+if { [string equal $_boot_core CA76] } {
+ setup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 1
+ setup_cr7 r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 0
+} elseif { [string equal $_boot_core CA57] } {
setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1
setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
- setup_cr7 $CR7_DBGBASE $CR7_CTIBASE 0
+ setup_cr7 r7 $CR7_DBGBASE $CR7_CTIBASE $_num_cr7 0
} elseif { [string equal $_boot_core CA53] } {
setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1
setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
- setup_cr7 $CR7_DBGBASE $CR7_CTIBASE 0
+ setup_cr7 r7 $CR7_DBGBASE $CR7_CTIBASE $_num_cr7 0
+} elseif { [string equal $_boot_core CR52] } {
+ setup_cr7 r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 1
+ setup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 0
} else {
- setup_cr7 $CR7_DBGBASE $CR7_CTIBASE 1
+ setup_cr7 r7 $CR7_DBGBASE $CR7_CTIBASE $_num_cr7 1
setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
}
commit a38a0afd17d943b8bbc046f5fcfbf150871557a2
Author: Marek Vasut <mar...@gm...>
Date: Sat Jun 12 20:48:51 2021 +0200
tcl/target: Select default boot core on Renesas R-Car Gen2/Gen3
On SMP Renesas R-Car Gen2/Gen3 systems, select the boot core as
the default target using the 'targets' command. This way, the
user can start debugging code running on the boot core without
having to switch to the boot core by explicitly invoking 'targets'
command first, since it is likely the debugged code will run on
the boot core. Note that most of the code is already in place, it
was just not used, so this is more of a fix to make the original
intention work.
Change-Id: I727808adce617c1d9ebd6ffa34f60f5882cdae60
Signed-off-by: Marek Vasut <mar...@gm...>
Reviewed-on: http://openocd.zylin.com/6313
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/renesas_rcar_gen2.cfg b/tcl/target/renesas_rcar_gen2.cfg
index 91baa6c90..e51b37202 100644
--- a/tcl/target/renesas_rcar_gen2.cfg
+++ b/tcl/target/renesas_rcar_gen2.cfg
@@ -87,12 +87,14 @@ dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
set CA15_DBGBASE {0x800B0000 0x800B2000 0x800B4000 0x800B6000}
set CA7_DBGBASE {0x800F0000 0x800F2000 0x800F4000 0x800F6000}
+set _targets ""
set smp_targets ""
proc setup_ca {core_name dbgbase num boot} {
global _CHIPNAME
global _DAPNAME
global smp_targets
+ global _targets
for { set _core 0 } { $_core < $num } { incr _core } {
set _TARGETNAME $_CHIPNAME.$core_name.$_core
set _CTINAME $_TARGETNAME.cti
@@ -123,3 +125,4 @@ if { [string equal $_boot_core CA15] } {
source [find target/renesas_rcar_reset_common.cfg]
eval "target smp $smp_targets"
+targets $_targets
diff --git a/tcl/target/renesas_rcar_gen3.cfg b/tcl/target/renesas_rcar_gen3.cfg
index 5738d371c..36e654491 100644
--- a/tcl/target/renesas_rcar_gen3.cfg
+++ b/tcl/target/renesas_rcar_gen3.cfg
@@ -112,12 +112,14 @@ set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000}
set CR7_DBGBASE 0x80910000
set CR7_CTIBASE 0x80918000
+set _targets ""
set smp_targets ""
proc setup_a5x {core_name dbgbase ctibase num boot} {
global _CHIPNAME
global _DAPNAME
global smp_targets
+ global _targets
for { set _core 0 } { $_core < $num } { incr _core } {
set _TARGETNAME $_CHIPNAME.$core_name.$_core
set _CTINAME $_TARGETNAME.cti
@@ -169,3 +171,4 @@ if { [string equal $_boot_core CA57] } {
source [find target/renesas_rcar_reset_common.cfg]
eval "target smp $smp_targets"
+targets $_targets
-----------------------------------------------------------------------
Summary of changes:
tcl/board/renesas_falcon.cfg | 10 +++++++
tcl/target/renesas_rcar_gen2.cfg | 3 ++
tcl/target/renesas_rcar_gen3.cfg | 60 +++++++++++++++++++++++++++++-----------
3 files changed, 57 insertions(+), 16 deletions(-)
create mode 100644 tcl/board/renesas_falcon.cfg
hooks/post-receive
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|
From: OpenOCD-Gerrit <ope...@us...> - 2021-06-26 13:39:55
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 0ef5144c32ac60ddf3bb005deb3136015e42ae4f (commit)
from af39ee607cd6ce6f3d809bd715892f2df1bf552a (commit)
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- Log -----------------------------------------------------------------
commit 0ef5144c32ac60ddf3bb005deb3136015e42ae4f
Author: Jesse Sheridan <jes...@gm...>
Date: Wed Jun 16 10:38:00 2021 -0700
target/riscv: Implement get_gdb_arch()
Change-Id: I5f4ab5243104df41031950682f688f2448a09b17
Signed-off-by: Jesse Sheridan <jes...@gm...>
Reviewed-on: http://openocd.zylin.com/6322
Tested-by: jenkins
Reviewed-by: Tim Newsome <ti...@si...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 37bc0cc90..4b0bac500 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -1614,6 +1614,18 @@ static int riscv_write_memory(struct target *target, target_addr_t address,
return tt->write_memory(target, address, size, count, buffer);
}
+const char *riscv_get_gdb_arch(struct target *target)
+{
+ switch (riscv_xlen(target)) {
+ case 32:
+ return "riscv:rv32";
+ case 64:
+ return "riscv:rv64";
+ }
+ LOG_ERROR("Unsupported xlen: %d", riscv_xlen(target));
+ return NULL;
+}
+
static int riscv_get_gdb_reg_list_internal(struct target *target,
struct reg **reg_list[], int *reg_list_size,
enum target_register_class reg_class, bool read)
@@ -2848,6 +2860,7 @@ struct target_type riscv_target = {
.mmu = riscv_mmu,
.virt2phys = riscv_virt2phys,
+ .get_gdb_arch = riscv_get_gdb_arch,
.get_gdb_reg_list = riscv_get_gdb_reg_list,
.get_gdb_reg_list_noread = riscv_get_gdb_reg_list_noread,
-----------------------------------------------------------------------
Summary of changes:
src/target/riscv/riscv.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
hooks/post-receive
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2021-06-23 22:51:53
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via af39ee607cd6ce6f3d809bd715892f2df1bf552a (commit)
from 42a0bf3c360c1eae418223f0ab535b4d7accae83 (commit)
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- Log -----------------------------------------------------------------
commit af39ee607cd6ce6f3d809bd715892f2df1bf552a
Author: Rohit Singh <roh...@gm...>
Date: Fri Jan 19 20:54:26 2018 +1100
tcl: Add support for the Digilent Nexys Video board
* https://store.digilentinc.com/nexys-video-artix-7-fpga-trainer-board-for-multimedia-applications/
* https://reference.digilentinc.com/_media/nexys-video:nexys_video_sch.pdf
The Nexys Video board has FTDI FT2232 whose channel B is connected to
Artix-7 FPGA's JTAG pins, and can be supported by OpenOCD's
ftdi interface. Tested to be working fine on real hardware.
Change-Id: I2996166dc8c2b6c08a9390958adfcdec8fc2bd37
Signed-off-by: Rohit Singh <roh...@gm...>
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/4364
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/board/digilent_nexys_video.cfg b/tcl/board/digilent_nexys_video.cfg
new file mode 100644
index 000000000..f171e2403
--- /dev/null
+++ b/tcl/board/digilent_nexys_video.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Digilent Nexys Video with Xilinx Artix-7 FPGA
+# https://reference.digilentinc.com/programmable-logic/nexys-video/start
+
+adapter driver ftdi
+adapter speed 30000
+
+ftdi_device_desc "Digilent USB Device"
+ftdi_vid_pid 0x0403 0x6010
+
+# channel 0 is dedicated for Digilent's DPTI Interface
+# channel 1 is used for JTAG
+ftdi_channel 1
+
+# just TCK TDI TDO TMS, no reset
+ftdi_layout_init 0x0088 0x008b
+reset_config none
+
+# Enable sampling on falling edge for high JTAG speeds.
+ftdi_tdo_sample_edge falling
+
+transport select jtag
+
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
-----------------------------------------------------------------------
Summary of changes:
tcl/board/digilent_nexys_video.cfg | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
create mode 100644 tcl/board/digilent_nexys_video.cfg
hooks/post-receive
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Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-06-18 22:16:31
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 42a0bf3c360c1eae418223f0ab535b4d7accae83 (commit)
from cdb8b00122142c58d9a91e37fbef322f2c9e5d02 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 42a0bf3c360c1eae418223f0ab535b4d7accae83
Author: R. Diez <rdi...@ya...>
Date: Sun May 23 12:18:36 2021 +0200
Doc fix: echo writes to the log, and not to stdout
Fixes bug #202
Change-Id: I855a1b8570af71379891634f405b4cc726917cb2
Signed-off-by: R. Diez <rdi...@ya...>
Reviewed-on: http://openocd.zylin.com/6272
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 7f486a9dd..daf0a6aa1 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -8153,7 +8153,6 @@ file (which is normally the server's standard output).
@deffn {Command} {echo} [-n] message
Logs a message at "user" priority.
-Output @var{message} to stdout.
Option "-n" suppresses trailing newline.
@example
echo "Downloading kernel -- please wait"
diff --git a/src/helper/command.c b/src/helper/command.c
index 4be3abd74..8ea805bd9 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -1222,7 +1222,6 @@ static const struct command_registration command_builtin_handlers[] = {
.handler = jim_echo,
.mode = COMMAND_ANY,
.help = "Logs a message at \"user\" priority. "
- "Output message to stdout. "
"Option \"-n\" suppresses trailing newline",
.usage = "[-n] string",
},
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 1 -
src/helper/command.c | 1 -
2 files changed, 2 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2021-06-18 22:15:54
|
This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
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via 4bb1d8b45ecd768b972efb1e3e9cf6e55336f8fd (commit)
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commit cdb8b00122142c58d9a91e37fbef322f2c9e5d02
Author: Marc Schink <de...@za...>
Date: Sat Jun 5 14:01:10 2021 +0200
doc/openocd: Fix typo
Change-Id: I8cf679190d6911de2dee181879c8895b55466835
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/6296
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 361ceb43f..7f486a9dd 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11181,7 +11181,7 @@ should be passed in to the proc in question.
@section Internal low-level Commands
-By "low-level," we mean commands that a human would typically not
+By "low-level", we mean commands that a human would typically not
invoke directly.
@itemize @bullet
commit da770c4fbb9ea20904caf3fcf4b51d7d064d11a8
Author: Marc Schink <de...@za...>
Date: Fri Jun 4 14:38:17 2021 +0200
Use boolean argument for register_get_by_name()
Change-Id: Ie913630c6ab3b600532d8e375e2fc11ca202cf5e
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/6295
Tested-by: jenkins
Reviewed-by: Jan Matyas <ma...@co...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 6378ea66e..4e1febe04 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1380,7 +1380,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
if (reg_params[i].direction == PARAM_IN)
continue;
- struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
+ struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, false);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -1452,7 +1452,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
struct reg *reg = register_get_by_name(arm->core_cache,
reg_params[i].reg_name,
- 0);
+ false);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
retval = ERROR_COMMAND_SYNTAX_ERROR;
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 11770b5b5..a9a5a381d 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -559,7 +559,7 @@ int armv7m_start_algorithm(struct target *target,
continue;
struct reg *reg =
- register_get_by_name(armv7m->arm.core_cache, reg_params[i].reg_name, 0);
+ register_get_by_name(armv7m->arm.core_cache, reg_params[i].reg_name, false);
/* uint32_t regvalue; */
if (!reg) {
@@ -675,7 +675,7 @@ int armv7m_wait_algorithm(struct target *target,
if (reg_params[i].direction != PARAM_OUT) {
struct reg *reg = register_get_by_name(armv7m->arm.core_cache,
reg_params[i].reg_name,
- 0);
+ false);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c
index 21bed8996..81ea21e81 100644
--- a/src/target/dsp563xx.c
+++ b/src/target/dsp563xx.c
@@ -1402,7 +1402,7 @@ static int dsp563xx_run_algorithm(struct target *target,
struct reg *reg = register_get_by_name(dsp563xx->core_cache,
reg_params[i].reg_name,
- 0);
+ false);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
@@ -1444,7 +1444,7 @@ static int dsp563xx_run_algorithm(struct target *target,
struct reg *reg = register_get_by_name(dsp563xx->core_cache,
reg_params[i].reg_name,
- 0);
+ false);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
continue;
diff --git a/src/target/mips32.c b/src/target/mips32.c
index e1f2b2832..c82536931 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -473,7 +473,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params,
if (reg_params[i].direction == PARAM_IN)
continue;
- struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
+ struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, false);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
@@ -507,7 +507,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params,
for (int i = 0; i < num_reg_params; i++) {
if (reg_params[i].direction != PARAM_OUT) {
- struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
+ struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, false);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
return ERROR_COMMAND_SYNTAX_ERROR;
diff --git a/src/target/nds32.c b/src/target/nds32.c
index cc6e2da44..d524fc288 100644
--- a/src/target/nds32.c
+++ b/src/target/nds32.c
@@ -997,7 +997,7 @@ int nds32_arch_state(struct target *target)
nds32->virtual_hosting ? ", virtual hosting" : "");
/* save pc value to pseudo register pc */
- struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
+ struct reg *reg = register_get_by_name(target->reg_cache, "pc", true);
buf_set_u32(reg->value, 0, 32, value_pc);
return ERROR_OK;
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 50535e266..37bc0cc90 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -1704,7 +1704,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
}
/* Save registers */
- struct reg *reg_pc = register_get_by_name(target->reg_cache, "pc", 1);
+ struct reg *reg_pc = register_get_by_name(target->reg_cache, "pc", true);
if (!reg_pc || reg_pc->type->get(reg_pc) != ERROR_OK)
return ERROR_FAIL;
uint64_t saved_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
@@ -1713,7 +1713,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
uint64_t saved_regs[32];
for (int i = 0; i < num_reg_params; i++) {
LOG_DEBUG("save %s", reg_params[i].reg_name);
- struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, 0);
+ struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
if (!r) {
LOG_ERROR("Couldn't find register named '%s'", reg_params[i].reg_name);
return ERROR_FAIL;
@@ -1747,7 +1747,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
LOG_DEBUG("Disabling Interrupts");
struct reg *reg_mstatus = register_get_by_name(target->reg_cache,
- "mstatus", 1);
+ "mstatus", true);
if (!reg_mstatus) {
LOG_ERROR("Couldn't find mstatus!");
return ERROR_FAIL;
@@ -1828,7 +1828,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
for (int i = 0; i < num_reg_params; i++) {
if (reg_params[i].direction == PARAM_IN ||
reg_params[i].direction == PARAM_IN_OUT) {
- struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, 0);
+ struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
if (r->type->get(r) != ERROR_OK) {
LOG_ERROR("get(%s) failed", r->name);
return ERROR_FAIL;
@@ -1836,7 +1836,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
buf_cpy(r->value, reg_params[i].value, reg_params[i].size);
}
LOG_DEBUG("restore %s", reg_params[i].reg_name);
- struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, 0);
+ struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
buf_set_u64(buf, 0, info->xlen[0], saved_regs[r->number]);
if (r->type->set(r, buf) != ERROR_OK) {
LOG_ERROR("set(%s) failed", r->name);
diff --git a/src/target/stm8.c b/src/target/stm8.c
index 00b524e31..a1653bc57 100644
--- a/src/target/stm8.c
+++ b/src/target/stm8.c
@@ -1876,7 +1876,7 @@ static int stm8_run_algorithm(struct target *target, int num_mem_params,
continue;
struct reg *reg = register_get_by_name(stm8->core_cache,
- reg_params[i].reg_name, 0);
+ reg_params[i].reg_name, false);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
@@ -1910,7 +1910,7 @@ static int stm8_run_algorithm(struct target *target, int num_mem_params,
for (int i = 0; i < num_reg_params; i++) {
if (reg_params[i].direction != PARAM_OUT) {
struct reg *reg = register_get_by_name(stm8->core_cache,
- reg_params[i].reg_name, 0);
+ reg_params[i].reg_name, false);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found",
reg_params[i].reg_name);
diff --git a/src/target/target.c b/src/target/target.c
index 450e231c6..dbc99b41c 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -2342,7 +2342,7 @@ int target_profiling_default(struct target *target, uint32_t *samples,
uint32_t sample_count = 0;
/* hopefully it is safe to cache! We want to stop/restart as quickly as possible. */
- struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
+ struct reg *reg = register_get_by_name(target->reg_cache, "pc", true);
int retval = ERROR_OK;
for (;;) {
@@ -3134,7 +3134,7 @@ COMMAND_HANDLER(handle_reg_command)
}
} else {
/* access a single register by its name */
- reg = register_get_by_name(target->reg_cache, CMD_ARGV[0], 1);
+ reg = register_get_by_name(target->reg_cache, CMD_ARGV[0], true);
if (!reg)
goto not_found;
commit 4bb1d8b45ecd768b972efb1e3e9cf6e55336f8fd
Author: Marc Schink <de...@za...>
Date: Fri Jun 4 14:31:57 2021 +0200
target/register: Minor code cleanup
Change-Id: Ie02a112c0339ae5d3b3763483e493370b487be98
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/6294
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/register.c b/src/target/register.c
index 4ddda6e6b..638747560 100644
--- a/src/target/register.c
+++ b/src/target/register.c
@@ -39,21 +39,20 @@
struct reg *register_get_by_number(struct reg_cache *first,
uint32_t reg_num, bool search_all)
{
- unsigned i;
struct reg_cache *cache = first;
while (cache) {
- for (i = 0; i < cache->num_regs; i++) {
- if (cache->reg_list[i].exist == false)
+ for (unsigned int i = 0; i < cache->num_regs; i++) {
+ if (!cache->reg_list[i].exist)
continue;
if (cache->reg_list[i].number == reg_num)
return &(cache->reg_list[i]);
}
- if (search_all)
- cache = cache->next;
- else
+ if (!search_all)
break;
+
+ cache = cache->next;
}
return NULL;
@@ -62,21 +61,20 @@ struct reg *register_get_by_number(struct reg_cache *first,
struct reg *register_get_by_name(struct reg_cache *first,
const char *name, bool search_all)
{
- unsigned i;
struct reg_cache *cache = first;
while (cache) {
- for (i = 0; i < cache->num_regs; i++) {
- if (cache->reg_list[i].exist == false)
+ for (unsigned int i = 0; i < cache->num_regs; i++) {
+ if (!cache->reg_list[i].exist)
continue;
if (strcmp(cache->reg_list[i].name, name) == 0)
return &(cache->reg_list[i]);
}
- if (search_all)
- cache = cache->next;
- else
+ if (!search_all)
break;
+
+ cache = cache->next;
}
return NULL;
@@ -108,8 +106,8 @@ void register_cache_invalidate(struct reg_cache *cache)
{
struct reg *reg = cache->reg_list;
- for (unsigned n = cache->num_regs; n != 0; n--, reg++) {
- if (reg->exist == false)
+ for (unsigned int n = cache->num_regs; n != 0; n--, reg++) {
+ if (!reg->exist)
continue;
reg->valid = false;
reg->dirty = false;
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 2 +-
src/target/armv4_5.c | 4 ++--
src/target/armv7m.c | 4 ++--
src/target/dsp563xx.c | 4 ++--
src/target/mips32.c | 4 ++--
src/target/nds32.c | 2 +-
src/target/register.c | 26 ++++++++++++--------------
src/target/riscv/riscv.c | 10 +++++-----
src/target/stm8.c | 4 ++--
src/target/target.c | 4 ++--
10 files changed, 31 insertions(+), 33 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2021-06-18 22:14:59
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via f5898bd93ff8b4d36a9aa781541de6f75d24debf (commit)
via 11857607293e1b27b43c307c3f6fba6ebbce90a8 (commit)
from f69adafb3dd252eaf6b269b7993b29d3c78a91c8 (commit)
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- Log -----------------------------------------------------------------
commit f5898bd93ff8b4d36a9aa781541de6f75d24debf
Author: Tarek BOCHKATI <tar...@gm...>
Date: Thu May 13 14:28:24 2021 +0100
flash/stm32fxx.c: do not read CPUID as this info is stored in cortex_m_common
In these drivers we read CPUID to check the Cortex-M PARTNO,
but now the PARTNO is stored in struct cortex_m_common.core_info.
Change-Id: I5bb3b95210ab6e23b8e1252686dd81015740bf68
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/6240
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index 91f2aef86..fbcf83afb 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -29,7 +29,7 @@
#include "imp.h"
#include <helper/binarybuffer.h>
#include <target/algorithm.h>
-#include <target/armv7m.h>
+#include <target/cortex_m.h>
/* stm32x register locations */
@@ -623,34 +623,32 @@ cleanup:
static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
{
- /* This check the device CPUID core register to detect
- * the M0 from the M3 devices. */
-
struct target *target = bank->target;
- uint32_t cpuid, device_id_register = 0;
+ struct cortex_m_common *cortex_m = target_to_cm(target);
+ uint32_t device_id_register = 0;
- /* Get the CPUID from the ARM Core
- * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
- int retval = target_read_u32(target, 0xE000ED00, &cpuid);
- if (retval != ERROR_OK)
- return retval;
+ if (!target_was_examined(target)) {
+ LOG_ERROR("Target not examined yet");
+ return ERROR_FAIL;
+ }
- if (((cpuid >> 4) & 0xFFF) == 0xC20) {
- /* 0xC20 is M0 devices */
+ switch (cortex_m->core_info->partno) {
+ case CORTEX_M0_PARTNO: /* STM32F0x devices */
device_id_register = 0x40015800;
- } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
- /* 0xC23 is M3 devices */
+ break;
+ case CORTEX_M3_PARTNO: /* STM32F1x devices */
device_id_register = 0xE0042000;
- } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
- /* 0xC24 is M4 devices */
+ break;
+ case CORTEX_M4_PARTNO: /* STM32F3x devices */
device_id_register = 0xE0042000;
- } else {
+ break;
+ default:
LOG_ERROR("Cannot identify target as a stm32x");
return ERROR_FAIL;
}
/* read stm32 device id register */
- retval = target_read_u32(target, device_id_register, device_id);
+ int retval = target_read_u32(target, device_id_register, device_id);
if (retval != ERROR_OK)
return retval;
@@ -660,27 +658,30 @@ static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
{
struct target *target = bank->target;
- uint32_t cpuid, flash_size_reg;
+ struct cortex_m_common *cortex_m = target_to_cm(target);
+ uint32_t flash_size_reg;
- int retval = target_read_u32(target, 0xE000ED00, &cpuid);
- if (retval != ERROR_OK)
- return retval;
+ if (!target_was_examined(target)) {
+ LOG_ERROR("Target not examined yet");
+ return ERROR_FAIL;
+ }
- if (((cpuid >> 4) & 0xFFF) == 0xC20) {
- /* 0xC20 is M0 devices */
+ switch (cortex_m->core_info->partno) {
+ case CORTEX_M0_PARTNO: /* STM32F0x devices */
flash_size_reg = 0x1FFFF7CC;
- } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
- /* 0xC23 is M3 devices */
+ break;
+ case CORTEX_M3_PARTNO: /* STM32F1x devices */
flash_size_reg = 0x1FFFF7E0;
- } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
- /* 0xC24 is M4 devices */
+ break;
+ case CORTEX_M4_PARTNO: /* STM32F3x devices */
flash_size_reg = 0x1FFFF7CC;
- } else {
+ break;
+ default:
LOG_ERROR("Cannot identify target as a stm32x");
return ERROR_FAIL;
}
- retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
+ int retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
if (retval != ERROR_OK)
return retval;
diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c
index 44f06f4fd..f718e3b98 100644
--- a/src/flash/nor/stm32f2x.c
+++ b/src/flash/nor/stm32f2x.c
@@ -29,7 +29,7 @@
#include "imp.h"
#include <helper/binarybuffer.h>
#include <target/algorithm.h>
-#include <target/armv7m.h>
+#include <target/cortex_m.h>
/* Regarding performance:
*
@@ -968,25 +968,17 @@ static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
* Only effects Rev A silicon */
struct target *target = bank->target;
- uint32_t cpuid;
+ struct cortex_m_common *cortex_m = target_to_cm(target);
/* read stm32 device id register */
int retval = target_read_u32(target, 0xE0042000, device_id);
if (retval != ERROR_OK)
return retval;
- if ((*device_id & 0xfff) == 0x411) {
- /* read CPUID reg to check core type */
- retval = target_read_u32(target, 0xE000ED00, &cpuid);
- if (retval != ERROR_OK)
- return retval;
-
- /* check for cortex_m4 */
- if (((cpuid >> 4) & 0xFFF) == 0xC24) {
- *device_id &= ~((0xFFFF << 16) | 0xfff);
- *device_id |= (0x1000 << 16) | 0x413;
- LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE");
- }
+ if ((*device_id & 0xfff) == 0x411 && cortex_m->core_info->partno == CORTEX_M4_PARTNO) {
+ *device_id &= ~((0xFFFF << 16) | 0xfff);
+ *device_id |= (0x1000 << 16) | 0x413;
+ LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE");
}
return retval;
}
commit 11857607293e1b27b43c307c3f6fba6ebbce90a8
Author: Tarek BOCHKATI <tar...@gm...>
Date: Tue May 11 14:03:47 2021 +0100
cortex_m: enhance core and arch detection
Rework core detection by adding cortex_m_partno enum to detect all CPUs
using the same method.
Instead of checking the core PARTNO then assign the arch, use the stored
information within cortex_m parts[] with the flags inside which can help
simplifying a bit the cortex_m_examine code.
This change fixes:
- the Cortex-M1 detection as ARMv6-M Core (was managed as ARMv7-M)
- the displayed CPU name for Cortex-M0+ (was displayed Cortex-M0)
Change-Id: I40b6e03f7cf3664c85e297adfc25323196dfe90b
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/6233
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index e442fc3b6..d0256b134 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -52,6 +52,66 @@
* any longer.
*/
+/* Supported Cortex-M Cores */
+static const struct cortex_m_part_info cortex_m_parts[] = {
+ {
+ .partno = CORTEX_M0_PARTNO,
+ .name = "Cortex-M0",
+ .arch = ARM_ARCH_V6M,
+ },
+ {
+ .partno = CORTEX_M0P_PARTNO,
+ .name = "Cortex-M0+",
+ .arch = ARM_ARCH_V6M,
+ },
+ {
+ .partno = CORTEX_M1_PARTNO,
+ .name = "Cortex-M1",
+ .arch = ARM_ARCH_V6M,
+ },
+ {
+ .partno = CORTEX_M3_PARTNO,
+ .name = "Cortex-M3",
+ .arch = ARM_ARCH_V7M,
+ .flags = CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K,
+ },
+ {
+ .partno = CORTEX_M4_PARTNO,
+ .name = "Cortex-M4",
+ .arch = ARM_ARCH_V7M,
+ .flags = CORTEX_M_F_HAS_FPV4 | CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K,
+ },
+ {
+ .partno = CORTEX_M7_PARTNO,
+ .name = "Cortex-M7",
+ .arch = ARM_ARCH_V7M,
+ .flags = CORTEX_M_F_HAS_FPV5,
+ },
+ {
+ .partno = CORTEX_M23_PARTNO,
+ .name = "Cortex-M23",
+ .arch = ARM_ARCH_V8M,
+ },
+ {
+ .partno = CORTEX_M33_PARTNO,
+ .name = "Cortex-M33",
+ .arch = ARM_ARCH_V8M,
+ .flags = CORTEX_M_F_HAS_FPV5,
+ },
+ {
+ .partno = CORTEX_M35P_PARTNO,
+ .name = "Cortex-M35P",
+ .arch = ARM_ARCH_V8M,
+ .flags = CORTEX_M_F_HAS_FPV5,
+ },
+ {
+ .partno = CORTEX_M55_PARTNO,
+ .name = "Cortex-M55",
+ .arch = ARM_ARCH_V8M,
+ .flags = CORTEX_M_F_HAS_FPV5,
+ },
+};
+
/* forward declarations */
static int cortex_m_store_core_reg_u32(struct target *target,
uint32_t num, uint32_t value);
@@ -2001,35 +2061,27 @@ int cortex_m_examine(struct target *target)
if (retval != ERROR_OK)
return retval;
- /* Get CPU Type */
- unsigned int core = (cpuid >> 4) & 0xf;
+ /* Get ARCH and CPU types */
+ const enum cortex_m_partno core_partno = (cpuid & ARM_CPUID_PARTNO_MASK) >> ARM_CPUID_PARTNO_POS;
- /* Check if it is an ARMv8-M core */
- armv7m->arm.arch = ARM_ARCH_V8M;
-
- switch (cpuid & ARM_CPUID_PARTNO_MASK) {
- case CORTEX_M23_PARTNO:
- core = 23;
- break;
- case CORTEX_M33_PARTNO:
- core = 33;
- break;
- case CORTEX_M35P_PARTNO:
- core = 35;
- break;
- case CORTEX_M55_PARTNO:
- core = 55;
- break;
- default:
- armv7m->arm.arch = ARM_ARCH_V7M;
+ for (unsigned int n = 0; n < ARRAY_SIZE(cortex_m_parts); n++) {
+ if (core_partno == cortex_m_parts[n].partno) {
+ cortex_m->core_info = &cortex_m_parts[n];
break;
+ }
+ }
+
+ if (!cortex_m->core_info) {
+ LOG_ERROR("Cortex-M PARTNO 0x%x is unrecognized", core_partno);
+ return ERROR_FAIL;
}
+ armv7m->arm.arch = cortex_m->core_info->arch;
- LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
- core, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
+ LOG_DEBUG("%s r%" PRId8 "p%" PRId8 " processor detected",
+ cortex_m->core_info->name, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
cortex_m->maskints_erratum = false;
- if (core == 7) {
+ if (core_partno == CORTEX_M7_PARTNO) {
uint8_t rev, patch;
rev = (cpuid >> 20) & 0xf;
patch = (cpuid >> 0) & 0xf;
@@ -2040,30 +2092,27 @@ int cortex_m_examine(struct target *target)
}
LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
- if (core == 4) {
+ if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV4) {
target_read_u32(target, MVFR0, &mvfr0);
target_read_u32(target, MVFR1, &mvfr1);
/* test for floating point feature on Cortex-M4 */
if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
- LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", core);
+ LOG_DEBUG("%s floating point feature FPv4_SP found", cortex_m->core_info->name);
armv7m->fp_feature = FPV4_SP;
}
- } else if (core == 7 || core == 33 || core == 35 || core == 55) {
+ } else if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV5) {
target_read_u32(target, MVFR0, &mvfr0);
target_read_u32(target, MVFR1, &mvfr1);
/* test for floating point features on Cortex-M7 */
if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
- LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", core);
+ LOG_DEBUG("%s floating point feature FPv5_SP found", cortex_m->core_info->name);
armv7m->fp_feature = FPV5_SP;
} else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
- LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", core);
+ LOG_DEBUG("%s floating point feature FPv5_DP found", cortex_m->core_info->name);
armv7m->fp_feature = FPV5_DP;
}
- } else if (core == 0) {
- /* Cortex-M0 does not support unaligned memory access */
- armv7m->arm.arch = ARM_ARCH_V6M;
}
/* VECTRESET is supported only on ARMv7-M cores */
@@ -2079,13 +2128,10 @@ int cortex_m_examine(struct target *target)
armv7m->arm.core_cache->reg_list[idx].exist = false;
if (!armv7m->stlink) {
- if (core == 3 || core == 4)
+ if (cortex_m->core_info->flags & CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K)
/* Cortex-M3/M4 have 4096 bytes autoincrement range,
* s. ARM IHI 0031C: MEM-AP 7.2.2 */
armv7m->debug_ap->tar_autoincr_block = (1 << 12);
- else if (core == 7)
- /* Cortex-M7 has only 1024 bytes autoincrement range */
- armv7m->debug_ap->tar_autoincr_block = (1 << 10);
}
/* Enable debug requests */
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 0f221ffff..3ba8a016d 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -42,12 +42,33 @@
#define CPUID 0xE000ED00
-#define ARM_CPUID_PARTNO_MASK 0xFFF0
+#define ARM_CPUID_PARTNO_POS 4
+#define ARM_CPUID_PARTNO_MASK (0xFFF << ARM_CPUID_PARTNO_POS)
+
+enum cortex_m_partno {
+ CORTEX_M0_PARTNO = 0xC20,
+ CORTEX_M1_PARTNO = 0xC21,
+ CORTEX_M3_PARTNO = 0xC23,
+ CORTEX_M4_PARTNO = 0xC24,
+ CORTEX_M7_PARTNO = 0xC27,
+ CORTEX_M0P_PARTNO = 0xC60,
+ CORTEX_M23_PARTNO = 0xD20,
+ CORTEX_M33_PARTNO = 0xD21,
+ CORTEX_M35P_PARTNO = 0xD31,
+ CORTEX_M55_PARTNO = 0xD22,
+};
+
+/* Relevant Cortex-M flags, used in struct cortex_m_part_info.flags */
+#define CORTEX_M_F_HAS_FPV4 BIT(0)
+#define CORTEX_M_F_HAS_FPV5 BIT(1)
+#define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K BIT(2)
-#define CORTEX_M23_PARTNO 0xD200
-#define CORTEX_M33_PARTNO 0xD210
-#define CORTEX_M35P_PARTNO 0xD310
-#define CORTEX_M55_PARTNO 0xD220
+struct cortex_m_part_info {
+ enum cortex_m_partno partno;
+ const char *name;
+ enum arm_arch arch;
+ uint32_t flags;
+};
/* Debug Control Block */
#define DCB_DHCSR 0xE000EDF0
@@ -211,9 +232,9 @@ struct cortex_m_common {
enum cortex_m_soft_reset_config soft_reset_config;
bool vectreset_supported;
-
enum cortex_m_isrmasking_mode isrmasking_mode;
+ const struct cortex_m_part_info *core_info;
struct armv7m_common armv7m;
int apsel;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32f1x.c | 61 +++++++++++++------------
src/flash/nor/stm32f2x.c | 20 +++-----
src/target/cortex_m.c | 116 +++++++++++++++++++++++++++++++++--------------
src/target/cortex_m.h | 33 +++++++++++---
4 files changed, 145 insertions(+), 85 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-06-18 22:13:52
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via f69adafb3dd252eaf6b269b7993b29d3c78a91c8 (commit)
from b19505a34377c2bade1aa129108b0c6aec577512 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit f69adafb3dd252eaf6b269b7993b29d3c78a91c8
Author: Tarek BOCHKATI <tar...@gm...>
Date: Tue May 11 09:28:00 2021 +0100
target/arm: optimize architecture flags
In target/arm.h the struct arm do contain 3 flags to retain architecture
version for some tweaks.
The proposal is to have only one enumerated flag 'arch' for the same purpose.
Change-Id: Ia5d5accfed8158ca21eb54af2fdea8e36f0266ae
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/6229
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nand/arm_io.c b/src/flash/nand/arm_io.c
index e319f9585..705470e77 100644
--- a/src/flash/nand/arm_io.c
+++ b/src/flash/nand/arm_io.c
@@ -173,7 +173,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
buf_set_u32(reg_params[2].value, 0, 32, size);
/* armv4 must exit using a hardware breakpoint */
- if (arm->is_armv4)
+ if (arm->arch == ARM_ARCH_V4)
exit_var = nand->copy_area->address + target_code_size - 4;
/* use alg to write data from work area to NAND chip */
@@ -279,7 +279,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
buf_set_u32(reg_params[2].value, 0, 32, size);
/* armv4 must exit using a hardware breakpoint */
- if (arm->is_armv4)
+ if (arm->arch == ARM_ARCH_V4)
exit_var = nand->copy_area->address + target_code_size - 4;
/* use alg to write data from NAND chip to work area */
diff --git a/src/flash/nor/stm32lx.c b/src/flash/nor/stm32lx.c
index 1ea1b1d0e..5ca424b87 100644
--- a/src/flash/nor/stm32lx.c
+++ b/src/flash/nor/stm32lx.c
@@ -718,7 +718,7 @@ static int stm32lx_read_id_code(struct target *target, uint32_t *id)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
int retval;
- if (armv7m->arm.is_armv6m == true)
+ if (armv7m->arm.arch == ARM_ARCH_V6M)
retval = target_read_u32(target, DBGMCU_IDCODE_L0, id);
else
/* read stm32 device id register */
diff --git a/src/rtos/riot.c b/src/rtos/riot.c
index dcba8381c..9165fe11b 100644
--- a/src/rtos/riot.c
+++ b/src/rtos/riot.c
@@ -416,7 +416,7 @@ static int riot_create(struct target *target)
/* Stacking is different depending on architecture */
struct armv7m_common *armv7m_target = target_to_armv7m(target);
- if (armv7m_target->arm.is_armv6m)
+ if (armv7m_target->arm.arch == ARM_ARCH_V6M)
stacking_info = &rtos_riot_cortex_m0_stacking;
else if (is_armv7m(armv7m_target))
stacking_info = &rtos_riot_cortex_m34_stacking;
diff --git a/src/target/arm.h b/src/target/arm.h
index d97a95edf..f403b8f8a 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -60,6 +60,15 @@ enum arm_core_type {
ARM_CORE_TYPE_M_PROFILE,
};
+/** ARM Architecture specifying the version and the profile */
+enum arm_arch {
+ ARM_ARCH_UNKNOWN,
+ ARM_ARCH_V4,
+ ARM_ARCH_V6M,
+ ARM_ARCH_V7M,
+ ARM_ARCH_V8M,
+};
+
/**
* Represent state of an ARM core.
*
@@ -191,14 +200,8 @@ struct arm {
/** Record the current core state: ARM, Thumb, or otherwise. */
enum arm_state core_state;
- /** Flag reporting unavailability of the BKPT instruction. */
- bool is_armv4;
-
- /** Flag reporting armv6m based core. */
- bool is_armv6m;
-
- /** Flag reporting armv8m based core. */
- bool is_armv8m;
+ /** ARM architecture version */
+ enum arm_arch arch;
/** Floating point or VFP version, 0 if disabled. */
int arm_vfp_version;
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index daa44e46a..bff20a334 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -427,7 +427,7 @@ static int arm720t_target_create(struct target *target, Jim_Interp *interp)
{
struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
- arm720t->arm7_9_common.arm.is_armv4 = true;
+ arm720t->arm7_9_common.arm.arch = ARM_ARCH_V4;
return arm720t_init_arch_info(target, arm720t, target->tap);
}
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 10263f40a..b0348392f 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -686,7 +686,7 @@ static int arm7tdmi_target_create(struct target *target, Jim_Interp *interp)
arm7_9 = calloc(1, sizeof(struct arm7_9_common));
arm7tdmi_init_arch_info(target, arm7_9, target->tap);
- arm7_9->arm.is_armv4 = true;
+ arm7_9->arm.arch = ARM_ARCH_V4;
return ERROR_OK;
}
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 4810c2b16..2a32f1127 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -781,7 +781,7 @@ static int arm9tdmi_target_create(struct target *target, Jim_Interp *interp)
struct arm7_9_common *arm7_9 = calloc(1, sizeof(struct arm7_9_common));
arm9tdmi_init_arch_info(target, arm7_9, target->tap);
- arm7_9->arm.is_armv4 = true;
+ arm7_9->arm.arch = ARM_ARCH_V4;
return ERROR_OK;
}
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 084a6f9b2..6378ea66e 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1347,7 +1347,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
}
/* armv5 and later can terminate with BKPT instruction; less overhead */
- if (!exit_point && arm->is_armv4) {
+ if (!exit_point && arm->arch == ARM_ARCH_V4) {
LOG_ERROR("ARMv4 target needs HW breakpoint location");
return ERROR_FAIL;
}
@@ -1568,7 +1568,7 @@ int arm_checksum_memory(struct target *target,
int timeout = 20000 * (1 + (count / (1024 * 1024)));
/* armv4 must exit using a hardware breakpoint */
- if (arm->is_armv4)
+ if (arm->arch == ARM_ARCH_V4)
exit_var = crc_algorithm->address + sizeof(arm_crc_code_le) - 8;
retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
@@ -1649,7 +1649,7 @@ int arm_blank_check_memory(struct target *target,
buf_set_u32(reg_params[2].value, 0, 32, erased_value);
/* armv4 must exit using a hardware breakpoint */
- if (arm->is_armv4)
+ if (arm->arch == ARM_ARCH_V4)
exit_var = check_algorithm->address + sizeof(check_code_le) - 4;
retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 941fef16a..e442fc3b6 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -504,7 +504,7 @@ static int cortex_m_debug_entry(struct target *target)
/* examine PE security state */
bool secure_state = false;
- if (armv7m->arm.is_armv8m) {
+ if (armv7m->arm.arch == ARM_ARCH_V8M) {
uint32_t dscsr;
retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
@@ -1645,7 +1645,7 @@ static int cortex_m_read_memory(struct target *target, target_addr_t address,
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- if (armv7m->arm.is_armv6m) {
+ if (armv7m->arm.arch == ARM_ARCH_V6M) {
/* armv6m does not handle unaligned memory access */
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
@@ -1659,7 +1659,7 @@ static int cortex_m_write_memory(struct target *target, target_addr_t address,
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- if (armv7m->arm.is_armv6m) {
+ if (armv7m->arm.arch == ARM_ARCH_V6M) {
/* armv6m does not handle unaligned memory access */
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
@@ -2005,7 +2005,7 @@ int cortex_m_examine(struct target *target)
unsigned int core = (cpuid >> 4) & 0xf;
/* Check if it is an ARMv8-M core */
- armv7m->arm.is_armv8m = true;
+ armv7m->arm.arch = ARM_ARCH_V8M;
switch (cpuid & ARM_CPUID_PARTNO_MASK) {
case CORTEX_M23_PARTNO:
@@ -2021,7 +2021,7 @@ int cortex_m_examine(struct target *target)
core = 55;
break;
default:
- armv7m->arm.is_armv8m = false;
+ armv7m->arm.arch = ARM_ARCH_V7M;
break;
}
@@ -2063,18 +2063,18 @@ int cortex_m_examine(struct target *target)
}
} else if (core == 0) {
/* Cortex-M0 does not support unaligned memory access */
- armv7m->arm.is_armv6m = true;
+ armv7m->arm.arch = ARM_ARCH_V6M;
}
/* VECTRESET is supported only on ARMv7-M cores */
- cortex_m->vectreset_supported = !armv7m->arm.is_armv8m && !armv7m->arm.is_armv6m;
+ cortex_m->vectreset_supported = armv7m->arm.arch == ARM_ARCH_V7M;
/* Check for FPU, otherwise mark FPU register as non-existent */
if (armv7m->fp_feature == FP_NONE)
for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++)
armv7m->arm.core_cache->reg_list[idx].exist = false;
- if (!armv7m->arm.is_armv8m)
+ if (armv7m->arm.arch != ARM_ARCH_V8M)
for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++)
armv7m->arm.core_cache->reg_list[idx].exist = false;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nand/arm_io.c | 4 ++--
src/flash/nor/stm32lx.c | 2 +-
src/rtos/riot.c | 2 +-
src/target/arm.h | 19 +++++++++++--------
src/target/arm720t.c | 2 +-
src/target/arm7tdmi.c | 2 +-
src/target/arm9tdmi.c | 2 +-
src/target/armv4_5.c | 6 +++---
src/target/cortex_m.c | 16 ++++++++--------
9 files changed, 29 insertions(+), 26 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-06-18 22:12:52
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b19505a34377c2bade1aa129108b0c6aec577512 (commit)
from 3e8ca67d1f9309d6f7860bdb6e9ad80d60f3ae6e (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit b19505a34377c2bade1aa129108b0c6aec577512
Author: Diego Herranz <die...@di...>
Date: Fri Jun 11 08:58:04 2021 +0100
contrib/itmdump.c: fix implicit declaration warning
atoi used but stdlib.h wasn't included.
Also, include statements reordered alphabetically.
Change-Id: I7fcdbf3fa940a172204ec811399e1a7fdebdc979
Signed-off-by: Diego Herranz <die...@di...>
Reviewed-on: http://openocd.zylin.com/6312
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/contrib/itmdump.c b/contrib/itmdump.c
index 24aa34f32..88099040a 100644
--- a/contrib/itmdump.c
+++ b/contrib/itmdump.c
@@ -39,8 +39,9 @@
#include <errno.h>
#include <libgen.h>
-#include <stdio.h>
#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
#include <string.h>
#include <unistd.h>
-----------------------------------------------------------------------
Summary of changes:
contrib/itmdump.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
hooks/post-receive
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Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2021-06-18 22:12:15
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 3e8ca67d1f9309d6f7860bdb6e9ad80d60f3ae6e (commit)
from cb5d9e0098a62b388fcfc7c89ddb6cda2be77a38 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 3e8ca67d1f9309d6f7860bdb6e9ad80d60f3ae6e
Author: Marc Schink <de...@za...>
Date: Sun Jun 13 10:49:17 2021 +0200
target: Rename 'linked_BRP' to 'linked_brp'
Change-Id: I9dd67ac3e8cd5dd9cdeffce56020b387a8f298fa
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/6316
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index ef00fd131..171c28615 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -1433,7 +1433,7 @@ static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoin
}
breakpoint->set = brp_1 + 1;
- breakpoint->linked_BRP = brp_2;
+ breakpoint->linked_brp = brp_2;
control_CTX = ((CTX_machmode & 0x7) << 20)
| (brp_2 << 16)
| (0 << 14)
@@ -1495,7 +1495,7 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br
if (breakpoint->type == BKPT_HARD) {
if ((breakpoint->address != 0) && (breakpoint->asid != 0)) {
int brp_i = breakpoint->set - 1;
- int brp_j = breakpoint->linked_BRP;
+ int brp_j = breakpoint->linked_brp;
if ((brp_i < 0) || (brp_i >= aarch64->brp_num)) {
LOG_DEBUG("Invalid BRP number in breakpoint");
return ERROR_OK;
@@ -1545,7 +1545,7 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br
if (retval != ERROR_OK)
return retval;
- breakpoint->linked_BRP = 0;
+ breakpoint->linked_brp = 0;
breakpoint->set = 0;
return ERROR_OK;
diff --git a/src/target/breakpoints.h b/src/target/breakpoints.h
index 8c247f7a9..b4a3511d2 100644
--- a/src/target/breakpoints.h
+++ b/src/target/breakpoints.h
@@ -43,7 +43,7 @@ struct breakpoint {
uint8_t *orig_instr;
struct breakpoint *next;
uint32_t unique_id;
- int linked_BRP;
+ int linked_brp;
};
struct watchpoint {
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index ec02d179f..7af0d3d7e 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1444,7 +1444,7 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoi
}
breakpoint->set = brp_1 + 1;
- breakpoint->linked_BRP = brp_2;
+ breakpoint->linked_brp = brp_2;
control_CTX = ((CTX_machmode & 0x7) << 20)
| (brp_2 << 16)
| (0 << 14)
@@ -1500,7 +1500,7 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
if (breakpoint->type == BKPT_HARD) {
if ((breakpoint->address != 0) && (breakpoint->asid != 0)) {
int brp_i = breakpoint->set - 1;
- int brp_j = breakpoint->linked_BRP;
+ int brp_j = breakpoint->linked_brp;
if ((brp_i < 0) || (brp_i >= cortex_a->brp_num)) {
LOG_DEBUG("Invalid BRP number in breakpoint");
return ERROR_OK;
@@ -1539,7 +1539,7 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
brp_list[brp_j].value);
if (retval != ERROR_OK)
return retval;
- breakpoint->linked_BRP = 0;
+ breakpoint->linked_brp = 0;
breakpoint->set = 0;
return ERROR_OK;
diff --git a/src/target/nds32.c b/src/target/nds32.c
index add66b22f..cc6e2da44 100644
--- a/src/target/nds32.c
+++ b/src/target/nds32.c
@@ -1660,7 +1660,7 @@ int nds32_init_arch_info(struct target *target, struct nds32 *nds32)
nds32->syscall_break.orig_instr = NULL;
nds32->syscall_break.next = NULL;
nds32->syscall_break.unique_id = 0x515CAll + target->target_number;
- nds32->syscall_break.linked_BRP = 0;
+ nds32->syscall_break.linked_brp = 0;
nds32_reg_init();
-----------------------------------------------------------------------
Summary of changes:
src/target/aarch64.c | 6 +++---
src/target/breakpoints.h | 2 +-
src/target/cortex_a.c | 6 +++---
src/target/nds32.c | 2 +-
4 files changed, 8 insertions(+), 8 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-06-13 19:00:27
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via cb5d9e0098a62b388fcfc7c89ddb6cda2be77a38 (commit)
from 708284a1accfa01c7a14ea7d7cd588000776d6b7 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit cb5d9e0098a62b388fcfc7c89ddb6cda2be77a38
Author: Tarek BOCHKATI <tar...@gm...>
Date: Sun Feb 14 13:22:03 2021 +0100
armv4_5: do not read/write non-existent registers
Change-Id: I4a0c401a325e57ba5d4d93d83b7e6b71a4d0865e
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/6064
Tested-by: jenkins
Reviewed-by: Marc Schink <de...@za...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 8ba913646..084a6f9b2 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1681,7 +1681,7 @@ static int arm_full_context(struct target *target)
int retval = ERROR_OK;
for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
- if (reg->valid)
+ if (!reg->exist || reg->valid)
continue;
retval = armv4_5_get_core_reg(reg);
}
-----------------------------------------------------------------------
Summary of changes:
src/target/armv4_5.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
hooks/post-receive
--
Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2021-06-13 18:59:48
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 708284a1accfa01c7a14ea7d7cd588000776d6b7 (commit)
via 21e1ebdc8e548f0db5fe5e2f90fb1cfc49cc53b0 (commit)
via 64c2e03b23d9cadc1b919d38e902a079d015ddc6 (commit)
from f2958fc04bd879393fa743860478834e234f05d0 (commit)
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- Log -----------------------------------------------------------------
commit 708284a1accfa01c7a14ea7d7cd588000776d6b7
Author: Tarek BOCHKATI <tar...@gm...>
Date: Sun Feb 14 13:21:36 2021 +0100
arm_dpm: do not read/write non-existent registers
Change-Id: I6a991899bb178ee0c6b41870a45d0a9439d9dc1e
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/6063
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 058f0df09..d1f574856 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -514,7 +514,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
continue;
if (arm->cpsr == cache->reg_list + i)
continue;
- if (!cache->reg_list[i].dirty)
+ if (!cache->reg_list[i].exist || !cache->reg_list[i].dirty)
continue;
r = cache->reg_list[i].arch_info;
@@ -763,7 +763,7 @@ static int arm_dpm_full_context(struct target *target)
for (unsigned i = 0; i < cache->num_regs; i++) {
struct arm_reg *r;
- if (cache->reg_list[i].valid)
+ if (!cache->reg_list[i].exist || cache->reg_list[i].valid)
continue;
r = cache->reg_list[i].arch_info;
commit 21e1ebdc8e548f0db5fe5e2f90fb1cfc49cc53b0
Author: Tarek BOCHKATI <tar...@gm...>
Date: Sun Feb 14 12:39:33 2021 +0100
armv8_dpm: do not read/write non-existent registers
Change-Id: I0f3fffa8cf1746569f6acce0233e9544d3862f51
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/6062
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index 6ef8c33de..b36ef835c 100644
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -782,7 +782,7 @@ int armv8_dpm_read_current_registers(struct arm_dpm *dpm)
struct arm_reg *arm_reg;
r = armv8_reg_current(arm, i);
- if (r->valid)
+ if (!r->exist || r->valid)
continue;
/* Skip reading FP-SIMD registers */
@@ -922,6 +922,9 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
for (unsigned i = 1; i < cache->num_regs; i++) {
struct arm_reg *r;
+ /* skip non-existent */
+ if (!cache->reg_list[i].exist)
+ continue;
/* skip PC and CPSR */
if (i == ARMV8_PC || i == ARMV8_xPSR)
continue;
@@ -1047,7 +1050,7 @@ static int armv8_dpm_full_context(struct target *target)
for (unsigned i = 0; i < cache->num_regs; i++) {
struct arm_reg *r;
- if (cache->reg_list[i].valid)
+ if (!cache->reg_list[i].exist || cache->reg_list[i].valid)
continue;
r = cache->reg_list[i].arch_info;
commit 64c2e03b23d9cadc1b919d38e902a079d015ddc6
Author: Jan Matyas <ma...@co...>
Date: Fri Apr 23 10:47:17 2021 +0200
flash/nor: improved API of flash_driver.info & fixed buffer overruns
1) The API of "info" callback in "struct flash_driver" has been
improved. Fixed buffers for strings
2) Removed the calls to snprintf() from the flash_driver.info
implementations. Many of them were used in an unsafe manner
(buffer overruns were possible).
Change-Id: I42ab8a8018d01f9af43c5ba49f650c3cb5d31dcb
Signed-off-by: Jan Matyas <ma...@co...>
Reviewed-on: http://openocd.zylin.com/6182
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/flash/nor/ambiqmicro.c b/src/flash/nor/ambiqmicro.c
index 1c4dce87d..c4c69ce2b 100644
--- a/src/flash/nor/ambiqmicro.c
+++ b/src/flash/nor/ambiqmicro.c
@@ -161,10 +161,9 @@ FLASH_BANK_COMMAND_HANDLER(ambiqmicro_flash_bank_command)
return ERROR_OK;
}
-static int get_ambiqmicro_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_ambiqmicro_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
- int printed;
char *classname;
if (!ambiqmicro_info->probed) {
@@ -178,16 +177,12 @@ static int get_ambiqmicro_info(struct flash_bank *bank, char *buf, int buf_size)
else
classname = ambiqmicroClassname[0];
- printed = snprintf(buf,
- buf_size,
- "\nAmbiq Micro information: Chip is "
+ command_print_sameline(cmd, "\nAmbiq Micro information: Chip is "
"class %d (%s) %s\n",
ambiqmicro_info->target_class,
classname,
ambiqmicro_info->target_name);
- if ((printed < 0))
- return ERROR_BUF_TOO_SMALL;
return ERROR_OK;
}
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index 9c4afd4af..e0c779a33 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -256,7 +256,7 @@ static struct sam3_chip *get_current_sam3(struct command_invocation *cmd)
t = get_current_target(cmd->ctx);
if (!t) {
- command_print(cmd, "No current target?");
+ command_print_sameline(cmd, "No current target?\n");
return NULL;
}
@@ -264,7 +264,7 @@ static struct sam3_chip *get_current_sam3(struct command_invocation *cmd)
if (!p) {
/* this should not happen */
/* the command is not registered until the chip is created? */
- command_print(cmd, "No SAM3 chips exist?");
+ command_print_sameline(cmd, "No SAM3 chips exist?\n");
return NULL;
}
@@ -273,7 +273,7 @@ static struct sam3_chip *get_current_sam3(struct command_invocation *cmd)
return p;
p = p->next;
}
- command_print(cmd, "Cannot find SAM3 chip?");
+ command_print_sameline(cmd, "Cannot find SAM3 chip?\n");
return NULL;
}
diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c
index d4326e43a..b7ae7f691 100644
--- a/src/flash/nor/at91sam4.c
+++ b/src/flash/nor/at91sam4.c
@@ -235,7 +235,7 @@ static struct sam4_chip *get_current_sam4(struct command_invocation *cmd)
t = get_current_target(cmd->ctx);
if (!t) {
- command_print(cmd, "No current target?");
+ command_print_sameline(cmd, "No current target?\n");
return NULL;
}
@@ -243,7 +243,7 @@ static struct sam4_chip *get_current_sam4(struct command_invocation *cmd)
if (!p) {
/* this should not happen */
/* the command is not registered until the chip is created? */
- command_print(cmd, "No SAM4 chips exist?");
+ command_print_sameline(cmd, "No SAM4 chips exist?\n");
return NULL;
}
@@ -252,7 +252,7 @@ static struct sam4_chip *get_current_sam4(struct command_invocation *cmd)
return p;
p = p->next;
}
- command_print(cmd, "Cannot find SAM4 chip?");
+ command_print_sameline(cmd, "Cannot find SAM4 chip?\n");
return NULL;
}
@@ -2656,19 +2656,16 @@ static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
return ERROR_OK;
}
-static int sam4_info(struct flash_bank *bank, char *buf, int buf_size)
+static int sam4_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct sam4_bank_private *pPrivate;
int k = bank->size / 1024;
pPrivate = get_sam4_bank_private(bank);
- if (pPrivate == NULL) {
- buf[0] = '\0';
+ if (pPrivate == NULL)
return ERROR_FAIL;
- }
- snprintf(buf, buf_size,
- "%s bank %d: %d kB at " TARGET_ADDR_FMT,
+ command_print_sameline(cmd, "%s bank %d: %d kB at " TARGET_ADDR_FMT,
pPrivate->pChip->details.name,
pPrivate->bank_number,
k,
diff --git a/src/flash/nor/at91sam7.c b/src/flash/nor/at91sam7.c
index 3d8fee1af..88f489f60 100644
--- a/src/flash/nor/at91sam7.c
+++ b/src/flash/nor/at91sam7.c
@@ -978,23 +978,17 @@ static int at91sam7_probe(struct flash_bank *bank)
return ERROR_OK;
}
-static int get_at91sam7_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_at91sam7_info(struct flash_bank *bank, struct command_invocation *cmd)
{
- int printed;
struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
if (at91sam7_info->cidr == 0)
return ERROR_FLASH_BANK_NOT_PROBED;
- printed = snprintf(buf, buf_size,
- "\n at91sam7 driver information: Chip is %s\n",
+ command_print_sameline(cmd, "\n at91sam7 driver information: Chip is %s\n",
at91sam7_info->target_name);
- buf += printed;
- buf_size -= printed;
-
- printed = snprintf(buf,
- buf_size,
+ command_print_sameline(cmd,
" Cidr: 0x%8.8" PRIx32 " | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | "
"Flashsize: 0x%8.8" PRIx32 "\n",
at91sam7_info->cidr,
@@ -1003,31 +997,20 @@ static int get_at91sam7_info(struct flash_bank *bank, char *buf, int buf_size)
at91sam7_info->cidr_version,
bank->size);
- buf += printed;
- buf_size -= printed;
-
- printed = snprintf(buf, buf_size,
- " Master clock (estimated): %u KHz | External clock: %u KHz\n",
+ command_print_sameline(cmd,
+ " Master clock (estimated): %u kHz | External clock: %u kHz\n",
(unsigned)(at91sam7_info->mck_freq / 1000),
(unsigned)(at91sam7_info->ext_freq / 1000));
- buf += printed;
- buf_size -= printed;
-
- printed = snprintf(buf,
- buf_size,
+ command_print_sameline(cmd,
" Pagesize: %i bytes | Lockbits(%u): %i 0x%4.4x | Pages in lock region: %i\n",
at91sam7_info->pagesize,
bank->num_sectors,
at91sam7_info->num_lockbits_on,
at91sam7_info->lockbits,
- at91sam7_info->pages_per_sector*at91sam7_info->num_lockbits_on);
-
- buf += printed;
- buf_size -= printed;
+ at91sam7_info->pages_per_sector * at91sam7_info->num_lockbits_on);
- snprintf(buf, buf_size,
- " Securitybit: %i | Nvmbits(%i): %i 0x%1.1x\n",
+ command_print_sameline(cmd, " Securitybit: %i | Nvmbits(%i): %i 0x%1.1x\n",
at91sam7_info->securitybit, at91sam7_info->num_nvmbits,
at91sam7_info->num_nvmbits_on, at91sam7_info->nvmbits);
diff --git a/src/flash/nor/ath79.c b/src/flash/nor/ath79.c
index 9a4595f6d..394b6dda0 100644
--- a/src/flash/nor/ath79.c
+++ b/src/flash/nor/ath79.c
@@ -875,17 +875,16 @@ static int ath79_protect_check(struct flash_bank *bank)
return ERROR_OK;
}
-static int get_ath79_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_ath79_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct ath79_flash_bank *ath79_info = bank->driver_priv;
if (!ath79_info->probed) {
- snprintf(buf, buf_size,
- "\nATH79 flash bank not probed yet\n");
+ command_print_sameline(cmd, "\nATH79 flash bank not probed yet\n");
return ERROR_OK;
}
- snprintf(buf, buf_size, "\nATH79 flash information:\n"
+ command_print_sameline(cmd, "\nATH79 flash information:\n"
" Device \'%s\' (ID 0x%08" PRIx32 ")\n",
ath79_info->dev->name, ath79_info->dev->device_id);
diff --git a/src/flash/nor/atsamv.c b/src/flash/nor/atsamv.c
index 8f1450bf7..f70e5d010 100644
--- a/src/flash/nor/atsamv.c
+++ b/src/flash/nor/atsamv.c
@@ -607,7 +607,7 @@ static int samv_write(struct flash_bank *bank, const uint8_t *buffer,
return ERROR_OK;
}
-static int samv_get_info(struct flash_bank *bank, char *buf, int buf_size)
+static int samv_get_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct samv_flash_bank *samv_info = bank->driver_priv;
if (!samv_info->probed) {
@@ -615,7 +615,7 @@ static int samv_get_info(struct flash_bank *bank, char *buf, int buf_size)
if (ERROR_OK != r)
return r;
}
- snprintf(buf, buf_size, "Cortex-M7 detected with %" PRIu32 " kB flash",
+ command_print_sameline(cmd, "Cortex-M7 detected with %" PRIu32 " kB flash\n",
bank->size / 1024);
return ERROR_OK;
}
diff --git a/src/flash/nor/avrf.c b/src/flash/nor/avrf.c
index dd3d077a0..46621e99f 100644
--- a/src/flash/nor/avrf.c
+++ b/src/flash/nor/avrf.c
@@ -367,7 +367,7 @@ static int avrf_auto_probe(struct flash_bank *bank)
return avrf_probe(bank);
}
-static int avrf_info(struct flash_bank *bank, char *buf, int buf_size)
+static int avrf_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct target *target = bank->target;
struct avr_common *avr = target->arch_info;
@@ -400,12 +400,12 @@ static int avrf_info(struct flash_bank *bank, char *buf, int buf_size)
if (avr_info != NULL) {
/* chip found */
- snprintf(buf, buf_size, "%s - Rev: 0x%" PRIx32 "", avr_info->name,
+ command_print_sameline(cmd, "%s - Rev: 0x%" PRIx32 "", avr_info->name,
EXTRACT_VER(device_id));
return ERROR_OK;
} else {
/* chip not supported */
- snprintf(buf, buf_size, "Cannot identify target as a avr\n");
+ command_print_sameline(cmd, "Cannot identify target as a avr\n");
return ERROR_FLASH_OPERATION_FAILED;
}
}
diff --git a/src/flash/nor/bluenrg-x.c b/src/flash/nor/bluenrg-x.c
index cf968cb8c..f533d54e9 100644
--- a/src/flash/nor/bluenrg-x.c
+++ b/src/flash/nor/bluenrg-x.c
@@ -429,7 +429,7 @@ static int bluenrgx_auto_probe(struct flash_bank *bank)
}
/* This method must return a string displaying information about the bank */
-static int bluenrgx_get_info(struct flash_bank *bank, char *buf, int buf_size)
+static int bluenrgx_get_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct bluenrgx_flash_bank *bluenrgx_info = bank->driver_priv;
int mask_number, cut_number;
@@ -437,8 +437,7 @@ static int bluenrgx_get_info(struct flash_bank *bank, char *buf, int buf_size)
if (!bluenrgx_info->probed) {
int retval = bluenrgx_probe(bank);
if (retval != ERROR_OK) {
- snprintf(buf, buf_size,
- "Unable to find bank information.");
+ command_print_sameline(cmd, "Unable to find bank information.");
return retval;
}
}
@@ -446,8 +445,8 @@ static int bluenrgx_get_info(struct flash_bank *bank, char *buf, int buf_size)
mask_number = (bluenrgx_info->die_id >> 4) & 0xF;
cut_number = bluenrgx_info->die_id & 0xF;
- snprintf(buf, buf_size,
- "%s - Rev: %d.%d", bluenrgx_info->flash_ptr->part_name, mask_number, cut_number);
+ command_print_sameline(cmd, "%s - Rev: %d.%d",
+ bluenrgx_info->flash_ptr->part_name, mask_number, cut_number);
return ERROR_OK;
}
diff --git a/src/flash/nor/cc26xx.c b/src/flash/nor/cc26xx.c
index 5565aeb41..4d58daad8 100644
--- a/src/flash/nor/cc26xx.c
+++ b/src/flash/nor/cc26xx.c
@@ -498,10 +498,9 @@ static int cc26xx_auto_probe(struct flash_bank *bank)
return retval;
}
-static int cc26xx_info(struct flash_bank *bank, char *buf, int buf_size)
+static int cc26xx_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct cc26xx_bank *cc26xx_bank = bank->driver_priv;
- int printed = 0;
const char *device;
switch (cc26xx_bank->device_type) {
@@ -526,13 +525,10 @@ static int cc26xx_info(struct flash_bank *bank, char *buf, int buf_size)
break;
}
- printed = snprintf(buf, buf_size,
+ command_print_sameline(cmd,
"%s device: ICEPick ID 0x%08" PRIx32 ", USER ID 0x%08" PRIx32 "\n",
device, cc26xx_bank->icepick_id, cc26xx_bank->user_id);
- if (printed >= buf_size)
- return ERROR_BUF_TOO_SMALL;
-
return ERROR_OK;
}
diff --git a/src/flash/nor/cc3220sf.c b/src/flash/nor/cc3220sf.c
index 5427bd3a9..1d01ba3be 100644
--- a/src/flash/nor/cc3220sf.c
+++ b/src/flash/nor/cc3220sf.c
@@ -477,15 +477,9 @@ static int cc3220sf_auto_probe(struct flash_bank *bank)
return retval;
}
-static int cc3220sf_info(struct flash_bank *bank, char *buf, int buf_size)
+static int cc3220sf_info(struct flash_bank *bank, struct command_invocation *cmd)
{
- int printed;
-
- printed = snprintf(buf, buf_size, "CC3220SF with 1MB internal flash\n");
-
- if (printed >= buf_size)
- return ERROR_BUF_TOO_SMALL;
-
+ command_print_sameline(cmd, "CC3220SF with 1MB internal flash\n");
return ERROR_OK;
}
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index c9eb38b9b..666316932 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -728,79 +728,57 @@ static int cfi_read_0002_pri_ext(struct flash_bank *bank)
return cfi_read_spansion_pri_ext(bank);
}
-static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
+static int cfi_spansion_info(struct flash_bank *bank, struct command_invocation *cmd)
{
- int printed;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
- printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
- buf += printed;
- buf_size -= printed;
+ command_print_sameline(cmd, "\nSpansion primary algorithm extend information:\n");
- printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
- pri_ext->pri[1], pri_ext->pri[2],
+ command_print_sameline(cmd, "pri: '%c%c%c', version: %c.%c\n",
+ pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2],
pri_ext->major_version, pri_ext->minor_version);
- buf += printed;
- buf_size -= printed;
- printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
+ command_print_sameline(cmd, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
(pri_ext->SiliconRevision) >> 2,
(pri_ext->SiliconRevision) & 0x03);
- buf += printed;
- buf_size -= printed;
- printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
+ command_print_sameline(cmd, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
pri_ext->EraseSuspend,
pri_ext->BlkProt);
- buf += printed;
- buf_size -= printed;
- snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
+ command_print_sameline(cmd, "VppMin: %u.%x, VppMax: %u.%x\n",
(pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
(pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
return ERROR_OK;
}
-static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
+static int cfi_intel_info(struct flash_bank *bank, struct command_invocation *cmd)
{
- int printed;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
- printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
- buf += printed;
- buf_size -= printed;
+ command_print_sameline(cmd, "\nintel primary algorithm extend information:\n");
- printed = snprintf(buf,
- buf_size,
- "pri: '%c%c%c', version: %c.%c\n",
+ command_print_sameline(cmd, "pri: '%c%c%c', version: %c.%c\n",
pri_ext->pri[0],
pri_ext->pri[1],
pri_ext->pri[2],
pri_ext->major_version,
pri_ext->minor_version);
- buf += printed;
- buf_size -= printed;
- printed = snprintf(buf,
- buf_size,
- "feature_support: 0x%" PRIx32 ", "
+ command_print_sameline(cmd, "feature_support: 0x%" PRIx32 ", "
"suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n",
pri_ext->feature_support,
pri_ext->suspend_cmd_support,
pri_ext->blk_status_reg_mask);
- buf += printed;
- buf_size -= printed;
- printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
+ command_print_sameline(cmd, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
(pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
(pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
- buf += printed;
- buf_size -= printed;
- snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, "
+ command_print_sameline(cmd, "protection_fields: %i, prot_reg_addr: 0x%x, "
"factory pre-programmed: %i, user programmable: %i\n",
pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
@@ -2992,45 +2970,36 @@ int cfi_protect_check(struct flash_bank *bank)
return ERROR_OK;
}
-int cfi_get_info(struct flash_bank *bank, char *buf, int buf_size)
+int cfi_get_info(struct flash_bank *bank, struct command_invocation *cmd)
{
- int printed;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
if (cfi_info->qry[0] == 0xff) {
- snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
+ command_print_sameline(cmd, "\ncfi flash bank not probed yet\n");
return ERROR_OK;
}
if (!cfi_info->not_cfi)
- printed = snprintf(buf, buf_size, "\nCFI flash: ");
+ command_print_sameline(cmd, "\nCFI flash: ");
else
- printed = snprintf(buf, buf_size, "\nnon-CFI flash: ");
- buf += printed;
- buf_size -= printed;
+ command_print_sameline(cmd, "\nnon-CFI flash: ");
- printed = snprintf(buf, buf_size, "mfr: 0x%4.4x, id:0x%4.4x\n\n",
+ command_print_sameline(cmd, "mfr: 0x%4.4x, id:0x%4.4x\n",
cfi_info->manufacturer, cfi_info->device_id);
- buf += printed;
- buf_size -= printed;
- printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: "
+ command_print_sameline(cmd, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: "
"0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n",
cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2],
cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
- buf += printed;
- buf_size -= printed;
- printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, "
+ command_print_sameline(cmd, "Vcc min: %x.%x, Vcc max: %x.%x, "
"Vpp min: %u.%x, Vpp max: %u.%x\n",
(cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
(cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
(cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
(cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
- buf += printed;
- buf_size -= printed;
- printed = snprintf(buf, buf_size, "typ. word write timeout: %u us, "
+ command_print_sameline(cmd, "typ. word write timeout: %u us, "
"typ. buf write timeout: %u us, "
"typ. block erase timeout: %u ms, "
"typ. chip erase timeout: %u ms\n",
@@ -3038,12 +3007,8 @@ int cfi_get_info(struct flash_bank *bank, char *buf, int buf_size)
1 << cfi_info->buf_write_timeout_typ,
1 << cfi_info->block_erase_timeout_typ,
1 << cfi_info->chip_erase_timeout_typ);
- buf += printed;
- buf_size -= printed;
- printed = snprintf(buf,
- buf_size,
- "max. word write timeout: %u us, "
+ command_print_sameline(cmd, "max. word write timeout: %u us, "
"max. buf write timeout: %u us, max. "
"block erase timeout: %u ms, max. chip erase timeout: %u ms\n",
(1 <<
@@ -3056,24 +3021,20 @@ int cfi_get_info(struct flash_bank *bank, char *buf, int buf_size)
(1 <<
cfi_info->chip_erase_timeout_max) *
(1 << cfi_info->chip_erase_timeout_typ));
- buf += printed;
- buf_size -= printed;
- printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, "
+ command_print_sameline(cmd, "size: 0x%" PRIx32 ", interface desc: %i, "
"max buffer write size: 0x%x\n",
cfi_info->dev_size,
cfi_info->interface_desc,
1 << cfi_info->max_buf_write_size);
- buf += printed;
- buf_size -= printed;
switch (cfi_info->pri_id) {
case 1:
case 3:
- cfi_intel_info(bank, buf, buf_size);
+ cfi_intel_info(bank, cmd);
break;
case 2:
- cfi_spansion_info(bank, buf, buf_size);
+ cfi_spansion_info(bank, cmd);
break;
default:
LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
diff --git a/src/flash/nor/cfi.h b/src/flash/nor/cfi.h
index eceb9a4b3..80633f494 100644
--- a/src/flash/nor/cfi.h
+++ b/src/flash/nor/cfi.h
@@ -160,7 +160,7 @@ int cfi_protect(struct flash_bank *bank, int set, unsigned int first,
int cfi_probe(struct flash_bank *bank);
int cfi_auto_probe(struct flash_bank *bank);
int cfi_protect_check(struct flash_bank *bank);
-int cfi_get_info(struct flash_bank *bank, char *buf, int buf_size);
+int cfi_get_info(struct flash_bank *bank, struct command_invocation *cmd);
int cfi_flash_bank_cmd(struct flash_bank *bank, unsigned int argc, const char **argv);
uint32_t cfi_flash_address(struct flash_bank *bank, int sector, uint32_t offset);
diff --git a/src/flash/nor/driver.h b/src/flash/nor/driver.h
index e29d4f528..7a5be6517 100644
--- a/src/flash/nor/driver.h
+++ b/src/flash/nor/driver.h
@@ -205,15 +205,14 @@ struct flash_driver {
/**
* Display human-readable information about the flash
- * bank into the given buffer. Drivers must be careful to avoid
- * overflowing the buffer.
+ * bank.
*
* @param bank - the bank to get info about
- * @param char - where to put the text for the human to read
- * @param buf_size - the size of the human buffer.
+ * @param cmd - command invocation instance for which to generate
+ * the textual output
* @returns ERROR_OK if successful; otherwise, an error code.
*/
- int (*info)(struct flash_bank *bank, char *buf, int buf_size);
+ int (*info)(struct flash_bank *bank, struct command_invocation *cmd);
/**
* A more gentle flavor of flash_driver_s::probe, performing
diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 6f2900762..6461e4c72 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -324,23 +324,7 @@ static int efm32x_read_info(struct flash_bank *bank,
return ERROR_OK;
}
-/*
- * Helper to create a human friendly string describing a part
- */
-static int efm32x_decode_info(struct efm32_info *info, char *buf, int buf_size)
-{
- int printed = 0;
- printed = snprintf(buf, buf_size, "%s Gecko, rev %d",
- info->family_data->name, info->prod_rev);
-
- if (printed >= buf_size)
- return ERROR_BUF_TOO_SMALL;
-
- return ERROR_OK;
-}
-
-/* flash bank efm32 <base> <size> 0 0 <target#>
- */
+/* flash bank efm32 <base> <size> 0 0 <target#> */
FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
{
struct efm32x_flash_bank *efm32x_info;
@@ -961,7 +945,6 @@ static int efm32x_probe(struct flash_bank *bank)
struct efm32_info efm32_mcu_info;
int ret;
uint32_t base_address = 0x00000000;
- char buf[256];
efm32x_info->probed = false;
memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
@@ -970,11 +953,8 @@ static int efm32x_probe(struct flash_bank *bank)
if (ERROR_OK != ret)
return ret;
- ret = efm32x_decode_info(&efm32_mcu_info, buf, sizeof(buf));
- if (ERROR_OK != ret)
- return ret;
-
- LOG_INFO("detected part: %s", buf);
+ LOG_INFO("detected part: %s Gecko, rev %d",
+ efm32_mcu_info.family_data->name, efm32_mcu_info.prod_rev);
LOG_INFO("flash size = %dkbytes", efm32_mcu_info.flash_sz_kib);
LOG_INFO("flash page size = %dbytes", efm32_mcu_info.page_size);
@@ -1044,10 +1024,10 @@ static int efm32x_protect_check(struct flash_bank *bank)
return ERROR_OK;
}
-static int get_efm32x_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_efm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct efm32_info info;
- int ret = 0;
+ int ret;
ret = efm32x_read_info(bank, &info);
if (ERROR_OK != ret) {
@@ -1055,7 +1035,8 @@ static int get_efm32x_info(struct flash_bank *bank, char *buf, int buf_size)
return ret;
}
- return efm32x_decode_info(&info, buf, buf_size);
+ command_print_sameline(cmd, "%s Gecko, rev %d", info.family_data->name, info.prod_rev);
+ return ERROR_OK;
}
COMMAND_HANDLER(efm32x_handle_debuglock_command)
diff --git a/src/flash/nor/esirisc_flash.c b/src/flash/nor/esirisc_flash.c
index 24e811704..23fd01e55 100644
--- a/src/flash/nor/esirisc_flash.c
+++ b/src/flash/nor/esirisc_flash.c
@@ -487,11 +487,11 @@ static int esirisc_flash_auto_probe(struct flash_bank *bank)
return esirisc_flash_probe(bank);
}
-static int esirisc_flash_info(struct flash_bank *bank, char *buf, int buf_size)
+static int esirisc_flash_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
- snprintf(buf, buf_size,
+ command_print_sameline(cmd,
"%4s cfg at 0x%" PRIx32 ", clock %" PRIu32 ", wait_states %" PRIu32,
"", /* align with first line */
esirisc_info->cfg,
diff --git a/src/flash/nor/faux.c b/src/flash/nor/faux.c
index d6c6b2dae..ed278b424 100644
--- a/src/flash/nor/faux.c
+++ b/src/flash/nor/faux.c
@@ -92,9 +92,9 @@ static int faux_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t o
return ERROR_OK;
}
-static int faux_info(struct flash_bank *bank, char *buf, int buf_size)
+static int faux_info(struct flash_bank *bank, struct command_invocation *cmd)
{
- snprintf(buf, buf_size, "faux flash driver");
+ command_print_sameline(cmd, "faux flash driver");
return ERROR_OK;
}
diff --git a/src/flash/nor/fespi.c b/src/flash/nor/fespi.c
index 02630ac24..0a14c5092 100644
--- a/src/flash/nor/fespi.c
+++ b/src/flash/nor/fespi.c
@@ -1017,17 +1017,16 @@ static int fespi_protect_check(struct flash_bank *bank)
return ERROR_OK;
}
-static int get_fespi_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_fespi_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct fespi_flash_bank *fespi_info = bank->driver_priv;
if (!(fespi_info->probed)) {
- snprintf(buf, buf_size,
- "\nFESPI flash bank not probed yet\n");
+ command_print_sameline(cmd, "\nFESPI flash bank not probed yet\n");
return ERROR_OK;
}
- snprintf(buf, buf_size, "\nFESPI flash information:\n"
+ command_print_sameline(cmd, "\nFESPI flash information:\n"
" Device \'%s\' (ID 0x%08" PRIx32 ")\n",
fespi_info->dev->name, fespi_info->dev->device_id);
diff --git a/src/flash/nor/fm4.c b/src/flash/nor/fm4.c
index 211a00863..2c51e007f 100644
--- a/src/flash/nor/fm4.c
+++ b/src/flash/nor/fm4.c
@@ -539,7 +539,7 @@ static int fm4_auto_probe(struct flash_bank *bank)
return fm4_probe(bank);
}
-static int fm4_get_info_command(struct flash_bank *bank, char *buf, int buf_size)
+static int fm4_get_info_command(struct flash_bank *bank, struct command_invocation *cmd)
{
struct fm4_flash_bank *fm4_bank = bank->driver_priv;
const char *name;
@@ -586,11 +586,10 @@ static int fm4_get_info_command(struct flash_bank *bank, char *buf, int buf_size
case s6e2cx8:
case s6e2cx9:
case s6e2cxa:
- snprintf(buf, buf_size, "%s MainFlash Macro #%i",
- name, fm4_bank->macro_nr);
+ command_print_sameline(cmd, "%s MainFlash Macro #%i", name, fm4_bank->macro_nr);
break;
default:
- snprintf(buf, buf_size, "%s MainFlash", name);
+ command_print_sameline(cmd, "%s MainFlash", name);
break;
}
diff --git a/src/flash/nor/jtagspi.c b/src/flash/nor/jtagspi.c
index 20362f384..f40efe84f 100644
--- a/src/flash/nor/jtagspi.c
+++ b/src/flash/nor/jtagspi.c
@@ -421,16 +421,16 @@ static int jtagspi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
return ERROR_OK;
}
-static int jtagspi_info(struct flash_bank *bank, char *buf, int buf_size)
+static int jtagspi_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct jtagspi_flash_bank *info = bank->driver_priv;
if (!(info->probed)) {
- snprintf(buf, buf_size, "\nJTAGSPI flash bank not probed yet\n");
+ command_print_sameline(cmd, "\nJTAGSPI flash bank not probed yet\n");
return ERROR_OK;
}
- snprintf(buf, buf_size, "\nSPIFI flash information:\n"
+ command_print_sameline(cmd, "\nSPIFI flash information:\n"
" Device \'%s\' (ID 0x%08" PRIx32 ")\n",
info->dev->name, info->dev->device_id);
diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c
index 1fee6eb2e..45046d607 100644
--- a/src/flash/nor/kinetis.c
+++ b/src/flash/nor/kinetis.c
@@ -2778,7 +2778,7 @@ static int kinetis_auto_probe(struct flash_bank *bank)
return kinetis_probe(bank);
}
-static int kinetis_info(struct flash_bank *bank, char *buf, int buf_size)
+static int kinetis_info(struct flash_bank *bank, struct command_invocation *cmd)
{
const char *bank_class_names[] = {
"(ANY)", "PFlash", "FlexNVM", "FlexRAM"
@@ -2788,7 +2788,7 @@ static int kinetis_info(struct flash_bank *bank, char *buf, int buf_size)
struct kinetis_chip *k_chip = k_bank->k_chip;
uint32_t size_k = bank->size / 1024;
- snprintf(buf, buf_size,
+ command_print_sameline(cmd,
"%s %s: %" PRIu32 "k %s bank %s at " TARGET_ADDR_FMT,
bank->driver->name, k_chip->name,
size_k, bank_class_names[k_bank->flash_class],
diff --git a/src/flash/nor/kinetis_ke.c b/src/flash/nor/kinetis_ke.c
index 5aba7fc64..0d094b5f9 100644
--- a/src/flash/nor/kinetis_ke.c
+++ b/src/flash/nor/kinetis_ke.c
@@ -1171,10 +1171,9 @@ static int kinetis_ke_auto_probe(struct flash_bank *bank)
return kinetis_ke_probe(bank);
}
-static int kinetis_ke_info(struct flash_bank *bank, char *buf, int buf_size)
+static int kinetis_ke_info(struct flash_bank *bank, struct command_invocation *cmd)
{
- (void) snprintf(buf, buf_size,
- "%s driver for flash bank %s at " TARGET_ADDR_FMT,
+ command_print_sameline(cmd, "%s driver for flash bank %s at " TARGET_ADDR_FMT,
bank->driver->name, bank->name, bank->base);
return ERROR_OK;
diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index 3ad62d669..09b5c6aec 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -1552,12 +1552,12 @@ static int lpc2000_erase_check(struct flash_bank *bank)
return lpc2000_iap_blank_check(bank, 0, bank->num_sectors - 1);
}
-static int get_lpc2000_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_lpc2000_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct lpc2000_flash_bank *lpc2000_info = bank->driver_priv;
- snprintf(buf, buf_size, "lpc2000 flash driver variant: %i, clk: %" PRIu32 "kHz", lpc2000_info->variant,
- lpc2000_info->cclk);
+ command_print_sameline(cmd, "lpc2000 flash driver variant: %i, clk: %" PRIu32 "kHz",
+ lpc2000_info->variant, lpc2000_info->cclk);
return ERROR_OK;
}
diff --git a/src/flash/nor/lpcspifi.c b/src/flash/nor/lpcspifi.c
index dd1c63d74..c99ce8d4c 100644
--- a/src/flash/nor/lpcspifi.c
+++ b/src/flash/nor/lpcspifi.c
@@ -926,17 +926,16 @@ static int lpcspifi_protect_check(struct flash_bank *bank)
return ERROR_OK;
}
-static int get_lpcspifi_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_lpcspifi_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
if (!(lpcspifi_info->probed)) {
- snprintf(buf, buf_size,
- "\nSPIFI flash bank not probed yet\n");
+ command_print_sameline(cmd, "\nSPIFI flash bank not probed yet\n");
return ERROR_OK;
}
- snprintf(buf, buf_size, "\nSPIFI flash information:\n"
+ command_print_sameline(cmd, "\nSPIFI flash information:\n"
" Device \'%s\' (ID 0x%08" PRIx32 ")\n",
lpcspifi_info->dev->name, lpcspifi_info->dev->device_id);
diff --git a/src/flash/nor/max32xxx.c b/src/flash/nor/max32xxx.c
index 586a73b1d..33d786889 100644
--- a/src/flash/nor/max32xxx.c
+++ b/src/flash/nor/max32xxx.c
@@ -113,17 +113,14 @@ FLASH_BANK_COMMAND_HANDLER(max32xxx_flash_bank_command)
return ERROR_OK;
}
-static int get_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_info(struct flash_bank *bank, struct command_invocation *cmd)
{
- int printed;
struct max32xxx_flash_bank *info = bank->driver_priv;
if (!info->probed)
return ERROR_FLASH_BANK_NOT_PROBED;
- printed = snprintf(buf, buf_size, "\nMaxim Integrated max32xxx flash driver\n");
- buf += printed;
- buf_size -= printed;
+ command_print_sameline(cmd, "\nMaxim Integrated max32xxx flash driver\n");
return ERROR_OK;
}
diff --git a/src/flash/nor/mdr.c b/src/flash/nor/mdr.c
index 2518c229b..e8484199a 100644
--- a/src/flash/nor/mdr.c
+++ b/src/flash/nor/mdr.c
@@ -597,11 +597,11 @@ static int mdr_auto_probe(struct flash_bank *bank)
return mdr_probe(bank);
}
-static int get_mdr_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_mdr_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct mdr_flash_bank *mdr_info = bank->driver_priv;
- snprintf(buf, buf_size, "MDR32Fx - %s",
- mdr_info->mem_type ? "info memory" : "main memory");
+ command_print_sameline(cmd, "MDR32Fx - %s",
+ mdr_info->mem_type ? "info memory" : "main memory");
return ERROR_OK;
}
diff --git a/src/flash/nor/mrvlqspi.c b/src/flash/nor/mrvlqspi.c
index b98c49dbc..44de98907 100644
--- a/src/flash/nor/mrvlqspi.c
+++ b/src/flash/nor/mrvlqspi.c
@@ -914,17 +914,16 @@ static int mrvlqspi_flash_erase_check(struct flash_bank *bank)
return ERROR_OK;
}
-static int mrvlqspi_get_info(struct flash_bank *bank, char *buf, int buf_size)
+static int mrvlqspi_get_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
if (!(mrvlqspi_info->probed)) {
- snprintf(buf, buf_size,
- "\nQSPI flash bank not probed yet\n");
+ command_print_sameline(cmd, "\nQSPI flash bank not probed yet\n");
return ERROR_OK;
}
- snprintf(buf, buf_size, "\nQSPI flash information:\n"
+ command_print_sameline(cmd, "\nQSPI flash information:\n"
" Device \'%s\' ID 0x%08" PRIx32 "\n",
mrvlqspi_info->dev->name, mrvlqspi_info->dev->device_id);
diff --git a/src/flash/nor/msp432.c b/src/flash/nor/msp432.c
index b6933e1e9..22f7c77a2 100644
--- a/src/flash/nor/msp432.c
+++ b/src/flash/nor/msp432.c
@@ -975,60 +975,50 @@ static int msp432_auto_probe(struct flash_bank *bank)
return retval;
}
-static int msp432_info(struct flash_bank *bank, char *buf, int buf_size)
+static int msp432_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct msp432_bank *msp432_bank = bank->driver_priv;
- int printed = 0;
switch (msp432_bank->device_type) {
case MSP432P401X_DEPR:
if (0xFFFF == msp432_bank->device_id) {
/* Very early pre-production silicon currently deprecated */
- printed = snprintf(buf, buf_size,
- "MSP432P401x pre-production device (deprecated silicon)\n"
+ command_print_sameline(cmd, "MSP432P401x pre-production device (deprecated silicon)\n"
SUPPORT_MESSAGE);
} else {
/* Revision A or B silicon, also deprecated */
- printed = snprintf(buf, buf_size,
- "MSP432P401x Device Rev %c (deprecated silicon)\n"
+ command_print_sameline(cmd, "MSP432P401x Device Rev %c (deprecated silicon)\n"
SUPPORT_MESSAGE, (char)msp432_bank->hardware_rev);
}
break;
case MSP432P401X:
- printed = snprintf(buf, buf_size,
- "MSP432P401x Device Rev %c\n",
+ command_print_sameline(cmd, "MSP432P401x Device Rev %c\n",
(char)msp432_bank->hardware_rev);
break;
case MSP432P411X:
- printed = snprintf(buf, buf_size,
- "MSP432P411x Device Rev %c\n",
+ command_print_sameline(cmd, "MSP432P411x Device Rev %c\n",
(char)msp432_bank->hardware_rev);
break;
case MSP432E401Y:
- printed = snprintf(buf, buf_size, "MSP432E401Y Device\n");
+ command_print_sameline(cmd, "MSP432E401Y Device\n");
break;
case MSP432E411Y:
- printed = snprintf(buf, buf_size, "MSP432E411Y Device\n");
+ command_print_sameline(cmd, "MSP432E411Y Device\n");
break;
case MSP432E4X_GUESS:
- printed = snprintf(buf, buf_size,
+ command_print_sameline(cmd,
"Unrecognized MSP432E4 DID0 and DID1 IDs (%08" PRIX32 ", %08" PRIX32 ")",
msp432_bank->device_id, msp432_bank->hardware_rev);
break;
case MSP432P401X_GUESS:
case MSP432P411X_GUESS:
default:
- printed = snprintf(buf, buf_size,
+ command_print_sameline(cmd,
"Unrecognized MSP432P4 Device ID and Hardware Rev (%04" PRIX32 ", %02" PRIX32 ")",
msp432_bank->device_id, msp432_bank->hardware_rev);
break;
}
- buf_size -= printed;
-
- if (0 > buf_size)
- return ERROR_BUF_TOO_SMALL;
-
return ERROR_OK;
}
diff --git a/src/flash/nor/niietcm4.c b/src/flash/nor/niietcm4.c
index 1831314dd..d48569423 100644
--- a/src/flash/nor/niietcm4.c
+++ b/src/flash/nor/niietcm4.c
@@ -1719,12 +1719,11 @@ static int niietcm4_auto_probe(struct flash_bank *bank)
return niietcm4_probe(bank);
}
-static int get_niietcm4_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_niietcm4_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct niietcm4_flash_bank *niietcm4_info = bank->driver_priv;
- LOG_INFO("\nNIIET Cortex-M4F %s\n%s", niietcm4_info->chip_name, niietcm4_info->chip_brief);
- snprintf(buf, buf_size, " ");
-
+ command_print_sameline(cmd, "\nNIIET Cortex-M4F %s\n%s",
+ niietcm4_info->chip_name, niietcm4_info->chip_brief);
return ERROR_OK;
}
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index 5e17a8c7b..9decbea9d 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -624,35 +624,42 @@ static const char *nrf5_decode_info_package(uint32_t package)
return "xx";
}
-static int nrf5_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_nrf5_chip_type_str(const struct nrf5_info *chip, char *buf, unsigned int buf_size)
{
- struct nrf5_bank *nbank = bank->driver_priv;
- struct nrf5_info *chip = nbank->chip;
int res;
-
if (chip->spec) {
- res = snprintf(buf, buf_size,
- "nRF%s-%s(build code: %s)",
+ res = snprintf(buf, buf_size, "nRF%s-%s(build code: %s)",
chip->spec->part, chip->spec->variant, chip->spec->build_code);
-
} else if (chip->ficr_info_valid) {
char variant[5];
nrf5_info_variant_to_str(chip->ficr_info.variant, variant);
- res = snprintf(buf, buf_size,
- "nRF%" PRIx32 "-%s%.2s(build code: %s)",
+ res = snprintf(buf, buf_size, "nRF%" PRIx32 "-%s%.2s(build code: %s)",
chip->ficr_info.part,
nrf5_decode_info_package(chip->ficr_info.package),
variant, &variant[2]);
-
} else {
- res = snprintf(buf, buf_size, "nRF51xxx (HWID 0x%04" PRIx16 ")",
- chip->hwid);
+ res = snprintf(buf, buf_size, "nRF51xxx (HWID 0x%04" PRIx16 ")", chip->hwid);
}
- if (res <= 0)
+
+ /* safety: */
+ if (res <= 0 || (unsigned int)res >= buf_size) {
+ LOG_ERROR("BUG: buffer problem in %s", __func__);
return ERROR_FAIL;
+ }
+ return ERROR_OK;
+}
- snprintf(buf + res, buf_size - res, " %ukB Flash, %ukB RAM",
- chip->flash_size_kb, chip->ram_size_kb);
+static int nrf5_info(struct flash_bank *bank, struct command_invocation *cmd)
+{
+ struct nrf5_bank *nbank = bank->driver_priv;
+ struct nrf5_info *chip = nbank->chip;
+
+ char chip_type_str[256];
+ if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
+ return ERROR_FAIL;
+
+ command_print_sameline(cmd, "%s %ukB Flash, %ukB RAM",
+ chip_type_str, chip->flash_size_kb, chip->ram_size_kb);
return ERROR_OK;
}
@@ -824,13 +831,15 @@ static int nrf5_probe(struct flash_bank *bank)
chip->flash_size_kb = num_sectors * flash_page_size / 1024;
if (!chip->bank[0].probed && !chip->bank[1].probed) {
- char buf[80];
- nrf5_info(bank, buf, sizeof(buf));
- if (!chip->spec && !chip->ficr_info_valid) {
- LOG_INFO("Unknown device: %s", buf);
- } else {
- LOG_INFO("%s", buf);
- }
+ char chip_type_str[256];
+ if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
+ return ERROR_FAIL;
+ const bool device_is_unknown = (!chip->spec && !chip->ficr_info_valid);
+ LOG_INFO("%s%s %ukB Flash, %ukB RAM",
+ device_is_unknown ? "Unknown device: " : "",
+ chip_type_str,
+ chip->flash_size_kb,
+ chip->ram_size_kb);
}
free(bank->sectors);
diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c
index c42cfb2bb..6844975e2 100644
--- a/src/flash/nor/pic32mx.c
+++ b/src/flash/nor/pic32mx.c
@@ -801,37 +801,35 @@ static int pic32mx_auto_probe(struct flash_bank *bank)
return pic32mx_probe(bank);
}
-static int pic32mx_info(struct flash_bank *bank, char *buf, int buf_size)
+static int pic32mx_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct target *target = bank->target;
struct mips32_common *mips32 = target->arch_info;
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
uint32_t device_id;
- int printed = 0, i;
device_id = ejtag_info->idcode;
if (((device_id >> 1) & 0x7ff) != PIC32MX_MANUF_ID) {
- snprintf(buf, buf_size,
- "Cannot identify target as a PIC32MX family (manufacturer 0x%03x != 0x%03x)\n",
- (unsigned)((device_id >> 1) & 0x7ff),
- PIC32MX_MANUF_ID);
+ command_print_sameline(cmd,
+ "Cannot identify target as a PIC32MX family (manufacturer 0x%03x != 0x%03x)\n",
+ (unsigned)((device_id >> 1) & 0x7ff),
+ PIC32MX_MANUF_ID);
return ERROR_FLASH_OPERATION_FAILED;
}
+ int i;
for (i = 0; pic32mx_devs[i].name != NULL; i++) {
if (pic32mx_devs[i].devid == (device_id & 0x0fffffff)) {
- printed = snprintf(buf, buf_size, "PIC32MX%s", pic32mx_devs[i].name);
+ command_print_sameline(cmd, "PIC32MX%s", pic32mx_devs[i].name);
break;
}
}
if (pic32mx_devs[i].name == NULL)
- printed = snprintf(buf, buf_size, "Unknown");
+ command_print_sameline(cmd, "Unknown");
- buf += printed;
- buf_size -= printed;
- snprintf(buf, buf_size, " Ver: 0x%02x",
+ command_print_sameline(cmd, " Ver: 0x%02x",
(unsigned)((device_id >> 28) & 0xf));
return ERROR_OK;
diff --git a/src/flash/nor/psoc4.c b/src/flash/nor/psoc4.c
index 3ca1f369c..cc2521b0d 100644
--- a/src/flash/nor/psoc4.c
+++ b/src/flash/nor/psoc4.c
@@ -851,7 +851,7 @@ static int psoc4_auto_probe(struct flash_bank *bank)
}
-static int get_psoc4_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_psoc4_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct target *target = bank->target;
struct psoc4_flash_bank *psoc4_info = bank->driver_priv;
@@ -863,35 +863,30 @@ static int get_psoc4_info(struct flash_bank *bank, char *buf, int buf_size)
uint32_t size_in_kb = bank->size / 1024;
if (target->state != TARGET_HALTED) {
- snprintf(buf, buf_size, "%s, flash %" PRIu32 " kb"
+ command_print_sameline(cmd, "%s, flash %" PRIu32 " kb"
" (halt target to see details)", family->name, size_in_kb);
return ERROR_OK;
}
- int retval;
- int printed = 0;
uint32_t silicon_id;
uint16_t family_id;
uint8_t protection;
- retval = psoc4_get_silicon_id(bank, &silicon_id, &family_id, &protection);
+ int retval = psoc4_get_silicon_id(bank, &silicon_id, &family_id, &protection);
if (retval != ERROR_OK)
return retval;
if (family_id != psoc4_info->family_id)
- printed = snprintf(buf, buf_size, "Family id mismatch 0x%02" PRIx16
+ command_print_sameline(cmd, "Family id mismatch 0x%02" PRIx16
"/0x%02" PRIx16 ", silicon id 0x%08" PRIx32,
psoc4_info->family_id, family_id, silicon_id);
else {
- printed = snprintf(buf, buf_size, "%s silicon id 0x%08" PRIx32 "",
+ command_print_sameline(cmd, "%s silicon id 0x%08" PRIx32 "",
family->name, silicon_id);
}
- buf += printed;
- buf_size -= printed;
-
const char *prot_txt = psoc4_decode_chip_protection(protection);
- snprintf(buf, buf_size, ", flash %" PRIu32 " kb %s", size_in_kb, prot_txt);
+ command_print_sameline(cmd, ", flash %" PRIu32 " kb %s", size_in_kb, prot_txt);
return ERROR_OK;
}
diff --git a/src/flash/nor/psoc5lp.c b/src/flash/nor/psoc5lp.c
index c651dea7a..1b268b53d 100644
--- a/src/flash/nor/psoc5lp.c
+++ b/src/flash/nor/psoc5lp.c
@@ -753,14 +753,14 @@ static int psoc5lp_nvl_write(struct flash_bank *bank,
}
static int psoc5lp_nvl_get_info_command(struct flash_bank *bank,
- char *buf, int buf_size)
+ struct command_invocation *cmd)
{
struct psoc5lp_nvl_flash_bank *psoc_nvl_bank = bank->driver_priv;
char part_number[PART_NUMBER_LEN];
psoc5lp_get_part_number(psoc_nvl_bank->device, part_number);
- snprintf(buf, buf_size, "%s", part_number);
+ command_print_sameline(cmd, "%s", part_number);
return ERROR_OK;
}
@@ -934,14 +934,14 @@ static int psoc5lp_eeprom_write(struct flash_bank *bank,
return ERROR_OK;
}
-static int psoc5lp_eeprom_get_info_command(struct flash_bank *bank, char *buf, int buf_size)
+static int psoc5lp_eeprom_get_info_command(struct flash_bank *bank, struct command_invocation *cmd)
{
struct psoc5lp_eeprom_flash_bank *psoc_eeprom_bank = bank->driver_priv;
char part_number[PART_NUMBER_LEN];
psoc5lp_get_part_number(psoc_eeprom_bank->device, part_number);
- snprintf(buf, buf_size, "%s", part_number);
+ command_print_sameline(cmd, "%s", part_number);
return ERROR_OK;
}
@@ -1397,7 +1397,7 @@ static int psoc5lp_protect_check(struct flash_bank *bank)
return ERROR_OK;
}
-static int psoc5lp_get_info_command(struct flash_bank *bank, char *buf, int buf_size)
+static int psoc5lp_get_info_command(struct flash_bank *bank, struct command_invocation *cmd)
{
struct psoc5lp_flash_bank *psoc_bank = bank->driver_priv;
char part_number[PART_NUMBER_LEN];
@@ -1406,7 +1406,7 @@ static int psoc5lp_get_info_command(struct flash_bank *bank, char *buf, int buf_
psoc5lp_get_part_number(psoc_bank->device, part_number);
ecc = psoc_bank->ecc_enabled ? "ECC enabled" : "ECC disabled";
- snprintf(buf, buf_size, "%s %s", part_number, ecc);
+ command_print_sameline(cmd, "%s %s", part_number, ecc);
return ERROR_OK;
}
diff --git a/src/flash/nor/psoc6.c b/src/flash/nor/psoc6.c
index 9c834fde6..c65411bb9 100644
--- a/src/flash/nor/psoc6.c
+++ b/src/flash/nor/psoc6.c
@@ -495,7 +495,7 @@ static const char *protection_to_str(uint8_t protection)
* @param buf_size size of the buffer
* @return ERROR_OK in case of success, ERROR_XXX code otherwise
*************************************************************************************************/
-static int psoc6_get_info(struct flash_bank *bank, char *buf, int buf_size)
+static int psoc6_get_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct psoc6_target_info *psoc6_info = bank->driver_priv;
@@ -506,7 +506,7 @@ static int psoc6_get_info(struct flash_bank *bank, char *buf, int buf_size)
if (hr != ERROR_OK)
return hr;
- snprintf(buf, buf_size,
+ command_print_sameline(cmd,
"PSoC6 Silicon ID: 0x%08" PRIX32 "\n"
"Protection: %s\n"
"Main Flash size: %" PRIu32 " kB\n"
diff --git a/src/flash/nor/sh_qspi.c b/src/flash/nor/sh_qspi.c
index 4ec7ebe65..a1598449c 100644
--- a/src/flash/nor/sh_qspi.c
+++ b/src/flash/nor/sh_qspi.c
@@ -851,17 +851,16 @@ static int sh_qspi_protect_check(struct flash_bank *bank)
return ERROR_OK;
}
-static int sh_qspi_get_info(struct flash_bank *bank, char *buf, int buf_size)
+static int sh_qspi_get_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct sh_qspi_flash_bank *info = bank->driver_priv;
if (!info->probed) {
- snprintf(buf, buf_size,
- "\nSH QSPI flash bank not probed yet\n");
+ command_print_sameline(cmd, "\nSH QSPI flash bank not probed yet\n");
return ERROR_OK;
}
- snprintf(buf, buf_size, "\nSH QSPI flash information:\n"
+ command_print_sameline(cmd, "\nSH QSPI flash information:\n"
" Device \'%s\' (ID 0x%08" PRIx32 ")\n",
info->dev->name, info->dev->device_id);
diff --git a/src/flash/nor/sim3x.c b/src/flash/nor/sim3x.c
index 76280f1ab..b42add96e 100644
--- a/src/flash/nor/sim3x.c
+++ b/src/flash/nor/sim3x.c
@@ -834,53 +834,32 @@ static int sim3x_auto_probe(struct flash_bank *bank)
}
}
-static int sim3x_flash_info(struct flash_bank *bank, char *buf, int buf_size)
+static int sim3x_flash_info(struct flash_bank *bank, struct command_invocation *cmd)
{
- int ret;
- int printed = 0;
struct sim3x_info *sim3x_info;
sim3x_info = bank->driver_priv;
/* Read info about chip */
- ret = sim3x_read_info(bank);
+ int ret = sim3x_read_info(bank);
if (ret != ERROR_OK)
return ret;
/* Part */
if (sim3x_info->part_family && sim3x_info->part_number) {
- printed = snprintf(buf, buf_size, "SiM3%c%d", sim3x_info->part_family, sim3x_info->part_number);
- buf += printed;
- buf_size -= printed;
-
- if (buf_size <= 0)
- return ERROR_BUF_TOO_SMALL;
+ command_print_sameline(cmd, "SiM3%c%d", sim3x_info->part_family, sim3x_info->part_number);
/* Revision */
if (sim3x_info->device_revision && sim3x_info->device_revision <= 'Z' - 'A') {
- printed = snprintf(buf, buf_size, "-%c", sim3x_info->device_revision + 'A');
- buf += printed;
- buf_size -= printed;
-
- if (buf_size <= 0)
- return ERROR_BUF_TOO_SMALL;
+ command_print_sameline(cmd, "-%c", sim3x_info->device_revision + 'A');
/* Package */
- printed = snprintf(buf, buf_size, "-G%s", sim3x_info->device_package);
- buf += printed;
- buf_size -= printed;
-
- if (buf_size <= 0)
- return ERROR_BUF_TOO_SMALL;
+ command_print_sameline(cmd, "-G%s", sim3x_info->device_package);
}
}
/* Print flash size */
- printed = snprintf(buf, buf_size, " flash_size = %dKB", sim3x_info->flash_size_kb);
- buf_size -= printed;
-
- if (buf_size <= 0)
- return ERROR_BUF_TOO_SMALL;
+ command_print_sameline(cmd, " flash_size = %dKB", sim3x_info->flash_size_kb);
return ERROR_OK;
}
diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c
index 55b99de3f..b4c959f05 100644
--- a/src/flash/nor/stellaris.c
+++ b/src/flash/nor/stellaris.c
@@ -479,9 +479,8 @@ FLASH_BANK_COMMAND_HANDLER(stellaris_flash_bank_command)
return ERROR_OK;
}
-static int get_stellaris_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_stellaris_info(struct flash_bank *bank, struct command_invocation *cmd)
{
- int printed;
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
if (stellaris_info->did1 == 0)
@@ -490,41 +489,34 @@ static int get_stellaris_info(struct flash_bank *bank, char *buf, int buf_size)
/* Read main and master clock frequency register */
stellaris_read_clock_info(bank);
- printed = snprintf(buf,
- buf_size,
- "\nTI/LMI Stellaris information: Chip is "
- "class %i (%s) %s rev %c%i\n",
- stellaris_info->target_class,
- StellarisClassname[stellaris_info->target_class],
- stellaris_info->target_name,
- (int)('A' + ((stellaris_info->did0 >> 8) & 0xFF)),
- (int)((stellaris_info->did0) & 0xFF));
- buf += printed;
- buf_size -= printed;
-
- printed = snprintf(buf,
- buf_size,
- "did1: 0x%8.8" PRIx32 ", arch: 0x%4.4" PRIx32
- ", eproc: %s, ramsize: %" PRIu32 "k, flashsize: %" PRIu32 "k\n",
- stellaris_info->did1,
- stellaris_info->did1,
- "ARMv7M",
- stellaris_info->sramsiz,
- (uint32_t)(stellaris_info->num_pages * stellaris_info->pagesize / 1024));
- buf += printed;
- buf_size -= printed;
-
- snprintf(buf,
- buf_size,
- "master clock: %ikHz%s, "
- "rcc is 0x%" PRIx32 ", rcc2 is 0x%" PRIx32 ", "
- "pagesize: %" PRIu32 ", pages: %" PRIu32,
- (int)(stellaris_info->mck_freq / 1000),
- stellaris_info->mck_desc,
- stellaris_info->rcc,
- stellaris_info->rcc2,
- stellaris_info->pagesize,
- stellaris_info->num_pages);
+ command_print_sameline(cmd,
+ "\nTI/LMI Stellaris information: Chip is "
+ "class %i (%s) %s rev %c%i\n",
+ stellaris_info->target_class,
+ StellarisClassname[stellaris_info->target_class],
+ stellaris_info->target_name,
+ (int)('A' + ((stellaris_info->did0 >> 8) & 0xFF)),
+ (int)((stellaris_info->did0) & 0xFF));
+
+ command_print_sameline(cmd,
+ "did1: 0x%8.8" PRIx32 ", arch: 0x%4.4" PRIx32
+ ", eproc: %s, ramsize: %" PRIu32 "k, flashsize: %" PRIu32 "k\n",
+ stellaris_info->did1,
+ stellaris_info->did1,
+ "ARMv7M",
+ stellaris_info->sramsiz,
+ (uint32_t)(stellaris_info->num_pages * stellaris_info->pagesize / 1024));
+
+ command_print_sameline(cmd,
+ "master clock: %ikHz%s, "
+ "rcc is 0x%" PRIx32 ", rcc2 is 0x%" PRIx32 ", "
+ "pagesize: %" PRIu32 ", pages: %" PRIu32,
+ (int)(stellaris_info->mck_freq / 1000),
+ stellaris_info->mck_desc,
+ stellaris_info->rcc,
+ stellaris_info->rcc2,
+ stellaris_info->pagesize,
+ stellaris_info->num_pages);
return ERROR_OK;
}
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index 125f77691..91f2aef86 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -954,11 +954,11 @@ static const char *get_stm32f0_revision(uint16_t rev_id)
return rev_str;
}
-static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
{
uint32_t dbgmcu_idcode;
- /* read stm32 device id register */
+ /* read stm32 device id register */
int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
if (retval != ERROR_OK)
return retval;
@@ -1174,14 +1174,14 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
break;
default:
- snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
+ command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
return ERROR_FAIL;
}
if (rev_str != NULL)
- snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
+ command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
else
- snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
+ command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
return ERROR_OK;
}
diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c
index e3625f322..44f06f4fd 100644
--- a/src/flash/nor/stm32f2x.c
+++ b/src/flash/nor/stm32f2x.c
@@ -1251,7 +1251,7 @@ static int stm32x_auto_probe(struct flash_bank *bank)
return stm32x_probe(bank);
}
-static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
{
uint32_t dbgmcu_idcode;
@@ -1416,14 +1416,14 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
break;
default:
- snprintf(buf, buf_size, "Cannot identify target as a STM32F2/4/7\n");
+ command_print_sameline(cmd, "Cannot identify target as a STM32F2/4/7\n");
return ERROR_FAIL;
}
if (rev_str != NULL)
- snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
+ command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
else
- snprintf(buf, buf_size, "%s - Rev: unknown (0x%04" PRIx16 ")", device_str, rev_id);
+ command_print_sameline(cmd, "%s - Rev: unknown (0x%04" PRIx16 ")", device_str, rev_id);
return ERROR_OK;
}
diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c
index 52e3e0e87..4c503db38 100644
--- a/src/flash/nor/stm32h7x.c
+++ b/src/flash/nor/stm32h7x.c
@@ -916,7 +916,7 @@ static int stm32x_auto_probe(struct flash_bank *bank)
}
/* This method must return a string displaying information about the bank */
-static int stm32x_get_info(struct flash_bank *bank, char *buf, int buf_size)
+static int stm32x_get_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
const struct stm32h7x_part_info *info = stm32x_info->part_info;
@@ -924,7 +924,7 @@ static int stm32x_get_info(struct flash_bank *bank, char *buf, int buf_size)
if (!stm32x_info->probed) {
int retval = stm32x_probe(bank);
if (retval != ERROR_OK) {
- snprintf(buf, buf_size, "Unable to find bank information.");
+ command_print_sameline(cmd, "Unable to find bank information.");
return retval;
}
}
@@ -938,16 +938,16 @@ static int stm32x_get_info(struct flash_bank *bank, char *buf, int buf_size)
rev_str = info->revs[i].str;
if (rev_str != NULL) {
- snprintf(buf, buf_size, "%s - Rev: %s",
+ command_print_sameline(cmd, "%s - Rev: %s",
stm32x_info->part_info->device_str, rev_str);
} else {
- snprintf(buf, buf_size,
+ command_print_sameline(cmd,
"%s - Rev: unknown (0x%04" PRIx16 ")",
stm32x_info->part_info->device_str, rev_id);
}
} else {
- snprintf(buf, buf_size, "Cannot identify target as a STM32H7x");
- return ERROR_FAIL;
+ command_print_sameline(cmd, "Cannot identify target as a STM32H7x");
+ return ERROR_FAIL;
}
return ERROR_OK;
}
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index 7e1fe7cec..cd6229548 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -1332,13 +1332,36 @@ static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
return (retval == ERROR_OK) ? ERROR_FAIL : retval;
}
+static const char *get_stm32l4_rev_str(struct flash_bank *bank)
+{
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
+ assert(part_info);
+
+ const uint16_t rev_id = stm32l4_info->idcode >> 16;
+ for (unsigned int i = 0; i < part_info->num_revs; i++) {
+ if (rev_id == part_info->revs[i].rev)
+ return part_info->revs[i].str;
+ }
+ return "'unknown'";
+}
+
+static const char *get_stm32l4_bank_type_str(struct flash_bank *bank)
+{
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ assert(stm32l4_info->part_info);
+ assert(stm32l4_info->probed);
+ return stm32l4_is_otp(ba...
[truncated message content] |
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-06-13 18:59:09
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via f2958fc04bd879393fa743860478834e234f05d0 (commit)
from 076b4d708e14a830cffee64d39ad0a1940e13e2f (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit f2958fc04bd879393fa743860478834e234f05d0
Author: Tim Newsome <ti...@si...>
Date: Fri May 28 13:38:50 2021 -0700
Add remote bitbang write buffer.
Change 7dd323b26 reduced remote bitbang performance a lot. This change
gets most of that performance back again, by reintroducing a write
buffer.
Performance numbers collected using DebugBreakpoint test from
riscv-tests/debug against a single 64-bit spike (RISC-V simulator)
instance. (Ubuntu 20.04.2, AMD Ryzen 5 3600)
Before Windows support was added: 3.09s
After Windows support was added: 12.67s
After this change: 4.69s
Signed-off-by: Tim Newsome <ti...@si...>
Change-Id: I72ff4912cbbf316a30ef065e5b8f461a555f06cc
Reviewed-on: http://openocd.zylin.com/6283
Tested-by: jenkins
Reviewed-by: Jan Matyas <ma...@co...>
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/remote_bitbang.c b/src/jtag/drivers/remote_bitbang.c
index f7b88303b..57f0c6e07 100644
--- a/src/jtag/drivers/remote_bitbang.c
+++ b/src/jtag/drivers/remote_bitbang.c
@@ -36,17 +36,19 @@ static char *remote_bitbang_host;
static char *remote_bitbang_port;
static int remote_bitbang_fd;
+static uint8_t remote_bitbang_send_buf[512];
+static unsigned int remote_bitbang_send_buf_used;
/* Circular buffer. When start == end, the buffer is empty. */
-static char remote_bitbang_buf[64];
-static unsigned remote_bitbang_start;
-static unsigned remote_bitbang_end;
+static char remote_bitbang_recv_buf[64];
+static unsigned int remote_bitbang_recv_buf_start;
+static unsigned int remote_bitbang_recv_buf_end;
-static int remote_bitbang_buf_full(void)
+static bool remote_bitbang_buf_full(void)
{
- return remote_bitbang_end ==
- ((remote_bitbang_start + sizeof(remote_bitbang_buf) - 1) %
- sizeof(remote_bitbang_buf));
+ return remote_bitbang_recv_buf_end ==
+ ((remote_bitbang_recv_buf_start + sizeof(remote_bitbang_recv_buf) - 1) %
+ sizeof(remote_bitbang_recv_buf));
}
/* Read any incoming data, placing it into the buffer. */
@@ -54,23 +56,23 @@ static int remote_bitbang_fill_buf(void)
{
socket_nonblock(remote_bitbang_fd);
while (!remote_bitbang_buf_full()) {
- unsigned contiguous_available_space;
- if (remote_bitbang_end >= remote_bitbang_start) {
- contiguous_available_space = sizeof(remote_bitbang_buf) -
- remote_bitbang_end;
- if (remote_bitbang_start == 0)
+ unsigned int contiguous_available_space;
+ if (remote_bitbang_recv_buf_end >= remote_bitbang_recv_buf_start) {
+ contiguous_available_space = sizeof(remote_bitbang_recv_buf) -
+ remote_bitbang_recv_buf_end;
+ if (remote_bitbang_recv_buf_start == 0)
contiguous_available_space -= 1;
} else {
- contiguous_available_space = remote_bitbang_start -
- remote_bitbang_end - 1;
+ contiguous_available_space = remote_bitbang_recv_buf_start -
+ remote_bitbang_recv_buf_end - 1;
}
ssize_t count = read_socket(remote_bitbang_fd,
- remote_bitbang_buf + remote_bitbang_end,
+ remote_bitbang_recv_buf + remote_bitbang_recv_buf_end,
contiguous_available_space);
if (count > 0) {
- remote_bitbang_end += count;
- if (remote_bitbang_end == sizeof(remote_bitbang_buf))
- remote_bitbang_end = 0;
+ remote_bitbang_recv_buf_end += count;
+ if (remote_bitbang_recv_buf_end == sizeof(remote_bitbang_recv_buf))
+ remote_bitbang_recv_buf_end = 0;
} else if (count == 0) {
return ERROR_OK;
} else if (count < 0) {
@@ -90,20 +92,43 @@ static int remote_bitbang_fill_buf(void)
return ERROR_OK;
}
-static int remote_bitbang_putc(int c)
+static int remote_bitbang_flush(void)
{
- char buf = c;
- ssize_t count = write_socket(remote_bitbang_fd, &buf, sizeof(buf));
- if (count < 0) {
- log_socket_error("remote_bitbang_putc");
- return ERROR_FAIL;
+ if (remote_bitbang_send_buf_used <= 0)
+ return ERROR_OK;
+
+ unsigned int offset = 0;
+ while (offset < remote_bitbang_send_buf_used) {
+ ssize_t written = write_socket(remote_bitbang_fd, remote_bitbang_send_buf + offset,
+ remote_bitbang_send_buf_used - offset);
+ if (written < 0) {
+ log_socket_error("remote_bitbang_putc");
+ remote_bitbang_send_buf_used = 0;
+ return ERROR_FAIL;
+ }
+ offset += written;
}
+ remote_bitbang_send_buf_used = 0;
+ return ERROR_OK;
+}
+
+typedef enum {
+ NO_FLUSH,
+ FLUSH_SEND_BUF
+} flush_bool_t;
+
+static int remote_bitbang_queue(int c, flush_bool_t flush)
+{
+ remote_bitbang_send_buf[remote_bitbang_send_buf_used++] = c;
+ if (flush == FLUSH_SEND_BUF ||
+ remote_bitbang_send_buf_used >= ARRAY_SIZE(remote_bitbang_send_buf))
+ return remote_bitbang_flush();
return ERROR_OK;
}
static int remote_bitbang_quit(void)
{
- if (remote_bitbang_putc('Q') == ERROR_FAIL)
+ if (remote_bitbang_queue('Q', FLUSH_SEND_BUF) == ERROR_FAIL)
return ERROR_FAIL;
if (close_socket(remote_bitbang_fd) != 0) {
@@ -135,6 +160,9 @@ static bb_value_t char_to_int(int c)
/* Get the next read response. */
static bb_value_t remote_bitbang_rread(void)
{
+ if (remote_bitbang_flush() != ERROR_OK)
+ return ERROR_FAIL;
+
/* Enable blocking access. */
socket_block(remote_bitbang_fd);
char c;
@@ -154,15 +182,19 @@ static int remote_bitbang_sample(void)
if (remote_bitbang_fill_buf() != ERROR_OK)
return ERROR_FAIL;
assert(!remote_bitbang_buf_full());
- return remote_bitbang_putc('R');
+ return remote_bitbang_queue('R', NO_FLUSH);
}
static bb_value_t remote_bitbang_read_sample(void)
{
- if (remote_bitbang_start != remote_bitbang_end) {
- int c = remote_bitbang_buf[remote_bitbang_start];
- remote_bitbang_start =
- (remote_bitbang_start + 1) % sizeof(remote_bitbang_buf);
+ if (remote_bitbang_recv_buf_start == remote_bitbang_recv_buf_end) {
+ if (remote_bitbang_fill_buf() != ERROR_OK)
+ return ERROR_FAIL;
+ }
+ if (remote_bitbang_recv_buf_start != remote_bitbang_recv_buf_end) {
+ int c = remote_bitbang_recv_buf[remote_bitbang_recv_buf_start];
+ remote_bitbang_recv_buf_start =
+ (remote_bitbang_recv_buf_start + 1) % sizeof(remote_bitbang_recv_buf);
return char_to_int(c);
}
return remote_bitbang_rread();
@@ -171,23 +203,25 @@ static bb_value_t remote_bitbang_read_sample(void)
static int remote_bitbang_write(int tck, int tms, int tdi)
{
char c = '0' + ((tck ? 0x4 : 0x0) | (tms ? 0x2 : 0x0) | (tdi ? 0x1 : 0x0));
- return remote_bitbang_putc(c);
+ return remote_bitbang_queue(c, NO_FLUSH);
}
static int remote_bitbang_reset(int trst, int srst)
{
char c = 'r' + ((trst ? 0x2 : 0x0) | (srst ? 0x1 : 0x0));
- return remote_bitbang_putc(c);
+ /* Always flush the send buffer on reset, because the reset call need not be
+ * followed by jtag_execute_queue(). */
+ return remote_bitbang_queue(c, FLUSH_SEND_BUF);
}
static int remote_bitbang_blink(int on)
{
char c = on ? 'B' : 'b';
- return remote_bitbang_putc(c);
+ return remote_bitbang_queue(c, FLUSH_SEND_BUF);
}
static struct bitbang_interface remote_bitbang_bitbang = {
- .buf_size = sizeof(remote_bitbang_buf) - 1,
+ .buf_size = sizeof(remote_bitbang_recv_buf) - 1,
.sample = &remote_bitbang_sample,
.read_sample = &remote_bitbang_read_sample,
.write = &remote_bitbang_write,
@@ -268,8 +302,8 @@ static int remote_bitbang_init(void)
{
bitbang_interface = &remote_bitbang_bitbang;
- remote_bitbang_start = 0;
- remote_bitbang_end = 0;
+ remote_bitbang_recv_buf_start = 0;
+ remote_bitbang_recv_buf_end = 0;
LOG_INFO("Initializing remote_bitbang driver");
if (remote_bitbang_port == NULL)
@@ -326,8 +360,23 @@ static const struct command_registration remote_bitbang_command_handlers[] = {
COMMAND_REGISTRATION_DONE,
};
+static int remote_bitbang_execute_queue(void)
+{
+ /* safety: the send buffer must be empty, no leftover characters from
+ * previous transactions */
+ assert(remote_bitbang_send_buf_used == 0);
+
+ /* process the JTAG command queue */
+ int ret = bitbang_execute_queue();
+ if (ret != ERROR_OK)
+ return ret;
+
+ /* flush not-yet-sent characters, if any */
+ return remote_bitbang_flush();
+}
+
static struct jtag_interface remote_bitbang_interface = {
- .execute_queue = &bitbang_execute_queue,
+ .execute_queue = &remote_bitbang_execute_queue,
};
struct adapter_driver remote_bitbang_adapter_driver = {
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/remote_bitbang.c | 123 ++++++++++++++++++++++++++------------
1 file changed, 86 insertions(+), 37 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-06-13 18:58:22
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 076b4d708e14a830cffee64d39ad0a1940e13e2f (commit)
from bb81ec8bf00f2d8cc0719cef802a367b4dc286e6 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 076b4d708e14a830cffee64d39ad0a1940e13e2f
Author: Marc Schink <de...@za...>
Date: Thu Jun 3 23:11:18 2021 +0200
target/cortex_a: Use bool data type
Change-Id: Ieea3dc05809263aa0eba5125d52fef3fe77e9c5a
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/6289
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 6b76656b9..ec02d179f 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1290,7 +1290,7 @@ static int cortex_a_set_breakpoint(struct target *target,
control = ((matchmode & 0x7) << 20)
| (byte_addr_select << 5)
| (3 << 1) | 1;
- brp_list[brp_i].used = 1;
+ brp_list[brp_i].used = true;
brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
brp_list[brp_i].control = control;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
@@ -1384,7 +1384,7 @@ static int cortex_a_set_context_breakpoint(struct target *target,
control = ((matchmode & 0x7) << 20)
| (byte_addr_select << 5)
| (3 << 1) | 1;
- brp_list[brp_i].used = 1;
+ brp_list[brp_i].used = true;
brp_list[brp_i].value = (breakpoint->asid);
brp_list[brp_i].control = control;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
@@ -1450,7 +1450,7 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoi
| (0 << 14)
| (CTX_byte_addr_select << 5)
| (3 << 1) | 1;
- brp_list[brp_1].used = 1;
+ brp_list[brp_1].used = true;
brp_list[brp_1].value = (breakpoint->asid);
brp_list[brp_1].control = control_CTX;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
@@ -1468,7 +1468,7 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoi
| (brp_1 << 16)
| (IVA_byte_addr_select << 5)
| (3 << 1) | 1;
- brp_list[brp_2].used = 1;
+ brp_list[brp_2].used = true;
brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC);
brp_list[brp_2].control = control_IVA;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
@@ -1507,7 +1507,7 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
}
LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
brp_list[brp_i].control, brp_list[brp_i].value);
- brp_list[brp_i].used = 0;
+ brp_list[brp_i].used = false;
brp_list[brp_i].value = 0;
brp_list[brp_i].control = 0;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
@@ -1526,7 +1526,7 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
}
LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_j,
brp_list[brp_j].control, brp_list[brp_j].value);
- brp_list[brp_j].used = 0;
+ brp_list[brp_j].used = false;
brp_list[brp_j].value = 0;
brp_list[brp_j].control = 0;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
@@ -1551,7 +1551,7 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
}
LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
brp_list[brp_i].control, brp_list[brp_i].value);
- brp_list[brp_i].used = 0;
+ brp_list[brp_i].used = false;
brp_list[brp_i].value = 0;
brp_list[brp_i].control = 0;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
@@ -1753,7 +1753,7 @@ static int cortex_a_set_watchpoint(struct target *target, struct watchpoint *wat
(byte_address_select << 5) |
(load_store_access_control << 3) |
(0x3 << 1) | 1;
- wrp_list[wrp_i].used = 1;
+ wrp_list[wrp_i].used = true;
wrp_list[wrp_i].value = address;
wrp_list[wrp_i].control = control;
@@ -1803,7 +1803,7 @@ static int cortex_a_unset_watchpoint(struct target *target, struct watchpoint *w
}
LOG_DEBUG("wrp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, wrp_i,
wrp_list[wrp_i].control, wrp_list[wrp_i].value);
- wrp_list[wrp_i].used = 0;
+ wrp_list[wrp_i].used = false;
wrp_list[wrp_i].value = 0;
wrp_list[wrp_i].control = 0;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
@@ -3033,7 +3033,7 @@ static int cortex_a_examine_first(struct target *target)
cortex_a->brp_list = calloc(cortex_a->brp_num, sizeof(struct cortex_a_brp));
/* cortex_a->brb_enabled = ????; */
for (i = 0; i < cortex_a->brp_num; i++) {
- cortex_a->brp_list[i].used = 0;
+ cortex_a->brp_list[i].used = false;
if (i < (cortex_a->brp_num-cortex_a->brp_num_context))
cortex_a->brp_list[i].type = BRP_NORMAL;
else
@@ -3051,7 +3051,7 @@ static int cortex_a_examine_first(struct target *target)
free(cortex_a->wrp_list);
cortex_a->wrp_list = calloc(cortex_a->wrp_num, sizeof(struct cortex_a_wrp));
for (i = 0; i < cortex_a->wrp_num; i++) {
- cortex_a->wrp_list[i].used = 0;
+ cortex_a->wrp_list[i].used = false;
cortex_a->wrp_list[i].value = 0;
cortex_a->wrp_list[i].control = 0;
cortex_a->wrp_list[i].WRPn = i;
diff --git a/src/target/cortex_a.h b/src/target/cortex_a.h
index dd135ec97..84e42a706 100644
--- a/src/target/cortex_a.h
+++ b/src/target/cortex_a.h
@@ -64,7 +64,7 @@ enum cortex_a_dacrfixup_mode {
};
struct cortex_a_brp {
- int used;
+ bool used;
int type;
uint32_t value;
uint32_t control;
@@ -72,7 +72,7 @@ struct cortex_a_brp {
};
struct cortex_a_wrp {
- int used;
+ bool used;
uint32_t value;
uint32_t control;
uint8_t WRPn;
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_a.c | 22 +++++++++++-----------
src/target/cortex_a.h | 4 ++--
2 files changed, 13 insertions(+), 13 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-06-04 16:47:41
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via bb81ec8bf00f2d8cc0719cef802a367b4dc286e6 (commit)
from 6a49b1ce2344c8707e322565ff0e5254762353fd (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit bb81ec8bf00f2d8cc0719cef802a367b4dc286e6
Author: Marc Schink <de...@za...>
Date: Sat May 29 12:09:28 2021 +0200
target/startup.tcl: Do not use 'Yoda conditions'
Change-Id: I5e1bbaf032659dda1b365ef4ec6ea4a635d921ce
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/6284
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/startup.tcl b/src/target/startup.tcl
index 54a3942c5..cd98d68e4 100644
--- a/src/target/startup.tcl
+++ b/src/target/startup.tcl
@@ -30,18 +30,17 @@ proc ocd_process_reset_inner { MODE } {
set targets [target names]
# If this target must be halted...
- set halt -1
- if { 0 == [string compare $MODE halt] } {
- set halt 1
- }
- if { 0 == [string compare $MODE init] } {
- set halt 1;
- }
- if { 0 == [string compare $MODE run ] } {
- set halt 0;
- }
- if { $halt < 0 } {
- return -code error "Invalid mode: $MODE, must be one of: halt, init, or run";
+ switch $MODE {
+ halt -
+ init {
+ set halt 1
+ }
+ run {
+ set halt 0
+ }
+ default {
+ return -code error "Invalid mode: $MODE, must be one of: halt, init, or run";
+ }
}
# Target event handlers *might* change which TAPs are enabled
@@ -130,14 +129,14 @@ proc ocd_process_reset_inner { MODE } {
# Did we succeed?
set s [$t curstate]
- if { 0 != [string compare $s "halted" ] } {
+ if { $s != "halted" } {
return -code error [format "TARGET: %s - Not halted" $t]
}
}
}
#Pass 2 - if needed "init"
- if { 0 == [string compare init $MODE] } {
+ if { $MODE == "init" } {
foreach t $targets {
if {[using_jtag] && ![jtag tapisenabled [$t cget -chain-position]]} {
continue
-----------------------------------------------------------------------
Summary of changes:
src/target/startup.tcl | 27 +++++++++++++--------------
1 file changed, 13 insertions(+), 14 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2021-06-04 16:47:09
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 6a49b1ce2344c8707e322565ff0e5254762353fd (commit)
from 358ab3483d2cad0c869585f8a340154690f56569 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 6a49b1ce2344c8707e322565ff0e5254762353fd
Author: R. Diez <rdi...@ya...>
Date: Sun May 23 12:01:48 2021 +0200
Avoid non-standard conditionals with omitted operands.
Fixes bug #257.
Change-Id: I05fc6468306d46399e769098e031e7e588798afc
Signed-off-by: R. Diez <rdi...@ya...>
Reviewed-on: http://openocd.zylin.com/6271
Tested-by: jenkins
Reviewed-by: Xiang W <wx...@12...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nand/lpc3180.c b/src/flash/nand/lpc3180.c
index 97bd7a351..6ce05753e 100644
--- a/src/flash/nand/lpc3180.c
+++ b/src/flash/nand/lpc3180.c
@@ -139,9 +139,9 @@ static int lpc3180_init(struct nand_device *nand)
{
struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
struct target *target = nand->target;
- int bus_width = nand->bus_width ? : 8;
- int address_cycles = nand->address_cycles ? : 3;
- int page_size = nand->page_size ? : 512;
+ int bus_width = nand->bus_width ? nand->bus_width : 8;
+ int address_cycles = nand->address_cycles ? nand->address_cycles : 3;
+ int page_size = nand->page_size ? nand->page_size : 512;
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
diff --git a/src/flash/nand/lpc32xx.c b/src/flash/nand/lpc32xx.c
index 6443beb39..f117eadcc 100644
--- a/src/flash/nand/lpc32xx.c
+++ b/src/flash/nand/lpc32xx.c
@@ -191,9 +191,9 @@ static int lpc32xx_init(struct nand_device *nand)
{
struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
struct target *target = nand->target;
- int bus_width = nand->bus_width ? : 8;
- int address_cycles = nand->address_cycles ? : 3;
- int page_size = nand->page_size ? : 512;
+ int bus_width = nand->bus_width ? nand->bus_width : 8;
+ int address_cycles = nand->address_cycles ? nand->address_cycles : 3;
+ int page_size = nand->page_size ? nand->page_size : 512;
int retval;
if (target->state != TARGET_HALTED) {
diff --git a/src/flash/nand/nuc910.c b/src/flash/nand/nuc910.c
index 1a2dd5968..9546f2ff2 100644
--- a/src/flash/nand/nuc910.c
+++ b/src/flash/nand/nuc910.c
@@ -183,7 +183,7 @@ static int nuc910_nand_init(struct nand_device *nand)
{
struct nuc910_nand_controller *nuc910_nand = nand->controller_priv;
struct target *target = nand->target;
- int bus_width = nand->bus_width ? : 8;
+ int bus_width = nand->bus_width ? nand->bus_width : 8;
int result;
result = validate_target_state(nand);
diff --git a/src/helper/command.c b/src/helper/command.c
index 43c5a0ffb..4be3abd74 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -866,9 +866,9 @@ static COMMAND_HELPER(command_help_show, struct help_entry *c,
stage_msg = " (?mode error?)";
break;
}
- msg = alloc_printf("%s%s", c->help ? : "", stage_msg);
+ msg = alloc_printf("%s%s", c->help ? c->help : "", stage_msg);
} else
- msg = alloc_printf("%s", c->help ? : "");
+ msg = alloc_printf("%s", c->help ? c->help : "");
if (NULL != msg) {
command_help_show_wrap(msg, n + 3, n + 3);
diff --git a/src/jtag/adapter.c b/src/jtag/adapter.c
index 03bb1a9c6..a867d2c3c 100644
--- a/src/jtag/adapter.c
+++ b/src/jtag/adapter.c
@@ -62,7 +62,7 @@ static int jim_adapter_name(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
return JIM_ERR;
}
const char *name = adapter_driver ? adapter_driver->name : NULL;
- Jim_SetResultString(goi.interp, name ? : "undefined", -1);
+ Jim_SetResultString(goi.interp, name ? name : "undefined", -1);
return JIM_OK;
}
diff --git a/src/jtag/core.c b/src/jtag/core.c
index 2166374cc..456faf7a9 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -1455,7 +1455,7 @@ void jtag_tap_init(struct jtag_tap *tap)
unsigned ir_len_bytes;
/* if we're autoprobing, cope with potentially huge ir_length */
- ir_len_bits = tap->ir_length ? : JTAG_IRLEN_MAX;
+ ir_len_bits = tap->ir_length ? tap->ir_length : JTAG_IRLEN_MAX;
ir_len_bytes = DIV_ROUND_UP(ir_len_bits, 8);
tap->expected = calloc(1, ir_len_bytes);
diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c
index 7e3280b20..c68bbb3ca 100644
--- a/src/jtag/drivers/stlink_usb.c
+++ b/src/jtag/drivers/stlink_usb.c
@@ -3904,7 +3904,7 @@ static int stlink_dap_op_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
if (retval != ERROR_OK)
return retval;
- data = data ? : &dummy;
+ data = data ? data : &dummy;
if (stlink_dap_handle->version.flags & STLINK_F_QUIRK_JTAG_DP_READ
&& stlink_dap_handle->st_mode == STLINK_MODE_DEBUG_JTAG) {
/* Quirk required in JTAG. Read RDBUFF to get the data */
@@ -3969,7 +3969,7 @@ static int stlink_dap_op_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
if (retval != ERROR_OK)
return retval;
}
- data = data ? : &dummy;
+ data = data ? data : &dummy;
retval = stlink_read_dap_register(stlink_dap_handle, ap->ap_num, reg,
data);
dap->stlink_flush_ap_write = false;
diff --git a/src/target/target.c b/src/target/target.c
index 63f68ebab..450e231c6 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -5178,7 +5178,7 @@ no_params:
if (goi->argc != 0)
goto no_params;
}
- Jim_SetResultString(goi->interp, target->gdb_port_override ? : "undefined", -1);
+ Jim_SetResultString(goi->interp, target->gdb_port_override ? target->gdb_port_override : "undefined", -1);
/* loop for more */
break;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nand/lpc3180.c | 6 +++---
src/flash/nand/lpc32xx.c | 6 +++---
src/flash/nand/nuc910.c | 2 +-
src/helper/command.c | 4 ++--
src/jtag/adapter.c | 2 +-
src/jtag/core.c | 2 +-
src/jtag/drivers/stlink_usb.c | 4 ++--
src/target/target.c | 2 +-
8 files changed, 14 insertions(+), 14 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-06-04 16:46:35
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 358ab3483d2cad0c869585f8a340154690f56569 (commit)
via 6ae38ef7f7ff6fd51d4536ddf60d905ed6ac158e (commit)
from c4dd883c9a919b0b0a36bc538157820225b85610 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 358ab3483d2cad0c869585f8a340154690f56569
Author: Tim Newsome <ti...@si...>
Date: Thu May 13 16:38:51 2021 -0700
Add target_data_bits().
This is used to compute memory block read alignment, and specifically
allows 64-bit targets to ensure that memory block reads are only
requested on 64-bit boundaries.
Signed-off-by: Tim Newsome <ti...@si...>
Change-Id: Idb1a27b9fc02c46245556bb0f3d6d94b368c4817
Reviewed-on: http://openocd.zylin.com/6249
Reviewed-by: Marc Schink <de...@za...>
Tested-by: jenkins
Reviewed-by: Jan Matyas <ma...@co...>
Reviewed-by: Xiang W <wx...@12...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index fa07fe821..50535e266 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -2813,6 +2813,14 @@ static unsigned riscv_xlen_nonconst(struct target *target)
return riscv_xlen(target);
}
+static unsigned int riscv_data_bits(struct target *target)
+{
+ RISCV_INFO(r);
+ if (r->data_bits)
+ return r->data_bits(target);
+ return riscv_xlen(target);
+}
+
struct target_type riscv_target = {
.name = "riscv",
@@ -2857,6 +2865,7 @@ struct target_type riscv_target = {
.commands = riscv_command_handlers,
.address_bits = riscv_xlen_nonconst,
+ .data_bits = riscv_data_bits
};
/*** RISC-V Interface ***/
diff --git a/src/target/target.c b/src/target/target.c
index 39a07ad6c..63f68ebab 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -1506,6 +1506,13 @@ unsigned target_address_bits(struct target *target)
return 32;
}
+unsigned int target_data_bits(struct target *target)
+{
+ if (target->type->data_bits)
+ return target->type->data_bits(target);
+ return 32;
+}
+
static int target_profiling(struct target *target, uint32_t *samples,
uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
{
@@ -2402,10 +2409,13 @@ static int target_write_buffer_default(struct target *target,
target_addr_t address, uint32_t count, const uint8_t *buffer)
{
uint32_t size;
+ unsigned int data_bytes = target_data_bits(target) / 8;
- /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
+ /* Align up to maximum bytes. The loop condition makes sure the next pass
* will have something to do with the size we leave to it. */
- for (size = 1; size < 4 && count >= size * 2 + (address & size); size *= 2) {
+ for (size = 1;
+ size < data_bytes && count >= size * 2 + (address & size);
+ size *= 2) {
if (address & size) {
int retval = target_write_memory(target, address, size, 1, buffer);
if (retval != ERROR_OK)
@@ -2463,10 +2473,13 @@ int target_read_buffer(struct target *target, target_addr_t address, uint32_t si
static int target_read_buffer_default(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer)
{
uint32_t size;
+ unsigned int data_bytes = target_data_bits(target) / 8;
- /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
+ /* Align up to maximum bytes. The loop condition makes sure the next pass
* will have something to do with the size we leave to it. */
- for (size = 1; size < 4 && count >= size * 2 + (address & size); size *= 2) {
+ for (size = 1;
+ size < data_bytes && count >= size * 2 + (address & size);
+ size *= 2) {
if (address & size) {
int retval = target_read_memory(target, address, size, 1, buffer);
if (retval != ERROR_OK)
diff --git a/src/target/target.h b/src/target/target.h
index d86c63eb0..18a9516f5 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -684,6 +684,13 @@ target_addr_t target_address_max(struct target *target);
*/
unsigned target_address_bits(struct target *target);
+/**
+ * Return the number of data bits this target supports.
+ *
+ * This routine is a wrapper for target->type->data_bits.
+ */
+unsigned int target_data_bits(struct target *target);
+
/** Return the *name* of this targets current state */
const char *target_state_name(struct target *target);
diff --git a/src/target/target_type.h b/src/target/target_type.h
index cc51c0401..cf30cf8cc 100644
--- a/src/target/target_type.h
+++ b/src/target/target_type.h
@@ -295,6 +295,11 @@ struct target_type {
* typically be 32 for 32-bit targets, and 64 for 64-bit targets. If not
* implemented, it's assumed to be 32. */
unsigned (*address_bits)(struct target *target);
+
+ /* Return the number of system bus data bits this target supports. This
+ * will typically be 32 for 32-bit targets, and 64 for 64-bit targets. If
+ * not implemented, it's assumed to be 32. */
+ unsigned int (*data_bits)(struct target *target);
};
#endif /* OPENOCD_TARGET_TARGET_TYPE_H */
commit 6ae38ef7f7ff6fd51d4536ddf60d905ed6ac158e
Author: Adrian Negreanu <adr...@nx...>
Date: Wed May 19 13:33:30 2021 +0300
cmsis_dap: add support for swo commands
Replaced mixed snake_case_CamelCase with snake_case.
Define variables at first-use location.
CMSIS-DAP SWO specification:
https://arm-software.github.io/CMSIS_5/DAP/html/group__DAP__swo__gr.html
Change-Id: Ieba79b16efd445143f964b614673d041aae74f92
Signed-off-by: Adrian Negreanu <adr...@nx...>
Reviewed-on: http://openocd.zylin.com/5820
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c
index c25937531..4062ace23 100644
--- a/src/jtag/drivers/cmsis_dap.c
+++ b/src/jtag/drivers/cmsis_dap.c
@@ -1,4 +1,7 @@
/***************************************************************************
+ * Copyright (C) 2021 by Adrian Negreanu *
+ * gr...@gm... *
+ * *
* Copyright (C) 2018 by Mickaël Thomas *
* mic...@gm... *
* *
@@ -41,6 +44,7 @@
#include <jtag/interface.h>
#include <jtag/commands.h>
#include <jtag/tcl.h>
+#include <target/cortex_m.h>
#include "cmsis_dap.h"
@@ -96,9 +100,12 @@ static bool swd_mode;
#define INFO_ID_CAPS 0xf0 /* byte */
#define INFO_ID_PKT_CNT 0xfe /* byte */
#define INFO_ID_PKT_SZ 0xff /* short */
+#define INFO_ID_SWO_BUF_SZ 0xfd /* word */
-#define INFO_CAPS_SWD 0x01
-#define INFO_CAPS_JTAG 0x02
+#define INFO_CAPS_SWD BIT(0)
+#define INFO_CAPS_JTAG BIT(1)
+#define INFO_CAPS_SWO_UART BIT(2)
+#define INFO_CAPS_SWO_MANCHESTER BIT(3)
/* CMD_LED */
#define LED_ID_CONNECT 0x00
@@ -163,12 +170,44 @@ static bool swd_mode;
#define DAP_OK 0
#define DAP_ERROR 0xFF
+/* CMSIS-DAP SWO Commands */
+#define CMD_DAP_SWO_TRANSPORT 0x17
+#define CMD_DAP_SWO_MODE 0x18
+#define CMD_DAP_SWO_BAUDRATE 0x19
+#define CMD_DAP_SWO_CONTROL 0x1A
+#define CMD_DAP_SWO_STATUS 0x1B
+#define CMD_DAP_SWO_DATA 0x1C
+#define CMD_DAP_SWO_EX_STATUS 0x1E
+
+/* SWO transport mode for reading trace data */
+#define DAP_SWO_TRANSPORT_NONE 0
+#define DAP_SWO_TRANSPORT_DATA 1
+#define DAP_SWO_TRANSPORT_WINUSB 2
+
+/* SWO trace capture mode */
+#define DAP_SWO_MODE_OFF 0
+#define DAP_SWO_MODE_UART 1
+#define DAP_SWO_MODE_MANCHESTER 2
+
+/* SWO trace data capture */
+#define DAP_SWO_CONTROL_STOP 0
+#define DAP_SWO_CONTROL_START 1
+
+/* SWO trace status */
+#define DAP_SWO_STATUS_CAPTURE_INACTIVE 0
+#define DAP_SWO_STATUS_CAPTURE_ACTIVE 1
+#define DAP_SWO_STATUS_CAPTURE_MASK BIT(0)
+#define DAP_SWO_STATUS_STREAM_ERROR_MASK BIT(6)
+#define DAP_SWO_STATUS_BUFFER_OVERRUN_MASK BIT(7)
+
/* CMSIS-DAP Vendor Commands
* None as yet... */
static const char * const info_caps_str[] = {
"SWD Supported",
- "JTAG Supported"
+ "JTAG Supported",
+ "SWO-UART Supported",
+ "SWO-MANCHESTER Supported"
};
struct pending_transfer_result {
@@ -338,9 +377,8 @@ static int cmsis_dap_xfer(struct cmsis_dap *dap, int txlen)
return ERROR_OK;
}
-static int cmsis_dap_cmd_DAP_SWJ_Pins(uint8_t pins, uint8_t mask, uint32_t delay, uint8_t *input)
+static int cmsis_dap_cmd_dap_swj_pins(uint8_t pins, uint8_t mask, uint32_t delay, uint8_t *input)
{
- int retval;
uint8_t *command = cmsis_dap_handle->command;
command[0] = CMD_DAP_SWJ_PINS;
@@ -348,8 +386,7 @@ static int cmsis_dap_cmd_DAP_SWJ_Pins(uint8_t pins, uint8_t mask, uint32_t delay
command[2] = mask;
h_u32_to_le(&command[3], delay);
- retval = cmsis_dap_xfer(cmsis_dap_handle, 7);
-
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 7);
if (retval != ERROR_OK) {
LOG_ERROR("CMSIS-DAP command CMD_DAP_SWJ_PINS failed.");
return ERROR_JTAG_DEVICE_ERROR;
@@ -361,9 +398,8 @@ static int cmsis_dap_cmd_DAP_SWJ_Pins(uint8_t pins, uint8_t mask, uint32_t delay
return ERROR_OK;
}
-static int cmsis_dap_cmd_DAP_SWJ_Clock(uint32_t swj_clock)
+static int cmsis_dap_cmd_dap_swj_clock(uint32_t swj_clock)
{
- int retval;
uint8_t *command = cmsis_dap_handle->command;
/* set clock in Hz */
@@ -372,8 +408,7 @@ static int cmsis_dap_cmd_DAP_SWJ_Clock(uint32_t swj_clock)
command[0] = CMD_DAP_SWJ_CLOCK;
h_u32_to_le(&command[1], swj_clock);
- retval = cmsis_dap_xfer(cmsis_dap_handle, 5);
-
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 5);
if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) {
LOG_ERROR("CMSIS-DAP command CMD_DAP_SWJ_CLOCK failed.");
return ERROR_JTAG_DEVICE_ERROR;
@@ -383,9 +418,8 @@ static int cmsis_dap_cmd_DAP_SWJ_Clock(uint32_t swj_clock)
}
/* clock a sequence of bits out on TMS, to change JTAG states */
-static int cmsis_dap_cmd_DAP_SWJ_Sequence(uint8_t s_len, const uint8_t *sequence)
+static int cmsis_dap_cmd_dap_swj_sequence(uint8_t s_len, const uint8_t *sequence)
{
- int retval;
uint8_t *command = cmsis_dap_handle->command;
#ifdef CMSIS_DAP_JTAG_DEBUG
@@ -400,23 +434,21 @@ static int cmsis_dap_cmd_DAP_SWJ_Sequence(uint8_t s_len, const uint8_t *sequence
command[1] = s_len;
bit_copy(&command[2], 0, sequence, 0, s_len);
- retval = cmsis_dap_xfer(cmsis_dap_handle, 2 + DIV_ROUND_UP(s_len, 8));
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 2 + DIV_ROUND_UP(s_len, 8));
if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK)
return ERROR_FAIL;
return ERROR_OK;
}
-static int cmsis_dap_cmd_DAP_Info(uint8_t info, uint8_t **data)
+static int cmsis_dap_cmd_dap_info(uint8_t info, uint8_t **data)
{
- int retval;
uint8_t *command = cmsis_dap_handle->command;
command[0] = CMD_DAP_INFO;
command[1] = info;
- retval = cmsis_dap_xfer(cmsis_dap_handle, 2);
-
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 2);
if (retval != ERROR_OK) {
LOG_ERROR("CMSIS-DAP command CMD_INFO failed.");
return ERROR_JTAG_DEVICE_ERROR;
@@ -427,17 +459,15 @@ static int cmsis_dap_cmd_DAP_Info(uint8_t info, uint8_t **data)
return ERROR_OK;
}
-static int cmsis_dap_cmd_DAP_LED(uint8_t led, uint8_t state)
+static int cmsis_dap_cmd_dap_led(uint8_t led, uint8_t state)
{
- int retval;
uint8_t *command = cmsis_dap_handle->command;
command[0] = CMD_DAP_LED;
command[1] = led;
command[2] = state;
- retval = cmsis_dap_xfer(cmsis_dap_handle, 3);
-
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 3);
if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) {
LOG_ERROR("CMSIS-DAP command CMD_LED failed.");
return ERROR_JTAG_DEVICE_ERROR;
@@ -446,16 +476,14 @@ static int cmsis_dap_cmd_DAP_LED(uint8_t led, uint8_t state)
return ERROR_OK;
}
-static int cmsis_dap_cmd_DAP_Connect(uint8_t mode)
+static int cmsis_dap_cmd_dap_connect(uint8_t mode)
{
- int retval;
uint8_t *command = cmsis_dap_handle->command;
command[0] = CMD_DAP_CONNECT;
command[1] = mode;
- retval = cmsis_dap_xfer(cmsis_dap_handle, 2);
-
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 2);
if (retval != ERROR_OK) {
LOG_ERROR("CMSIS-DAP command CMD_CONNECT failed.");
return ERROR_JTAG_DEVICE_ERROR;
@@ -469,15 +497,13 @@ static int cmsis_dap_cmd_DAP_Connect(uint8_t mode)
return ERROR_OK;
}
-static int cmsis_dap_cmd_DAP_Disconnect(void)
+static int cmsis_dap_cmd_dap_disconnect(void)
{
- int retval;
uint8_t *command = cmsis_dap_handle->command;
command[0] = CMD_DAP_DISCONNECT;
- retval = cmsis_dap_xfer(cmsis_dap_handle, 1);
-
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 1);
if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) {
LOG_ERROR("CMSIS-DAP command CMD_DISCONNECT failed.");
return ERROR_JTAG_DEVICE_ERROR;
@@ -486,9 +512,8 @@ static int cmsis_dap_cmd_DAP_Disconnect(void)
return ERROR_OK;
}
-static int cmsis_dap_cmd_DAP_TFER_Configure(uint8_t idle, uint16_t retry_count, uint16_t match_retry)
+static int cmsis_dap_cmd_dap_tfer_configure(uint8_t idle, uint16_t retry_count, uint16_t match_retry)
{
- int retval;
uint8_t *command = cmsis_dap_handle->command;
command[0] = CMD_DAP_TFER_CONFIGURE;
@@ -496,8 +521,7 @@ static int cmsis_dap_cmd_DAP_TFER_Configure(uint8_t idle, uint16_t retry_count,
h_u16_to_le(&command[2], retry_count);
h_u16_to_le(&command[4], match_retry);
- retval = cmsis_dap_xfer(cmsis_dap_handle, 6);
-
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 6);
if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) {
LOG_ERROR("CMSIS-DAP command CMD_TFER_Configure failed.");
return ERROR_JTAG_DEVICE_ERROR;
@@ -506,16 +530,14 @@ static int cmsis_dap_cmd_DAP_TFER_Configure(uint8_t idle, uint16_t retry_count,
return ERROR_OK;
}
-static int cmsis_dap_cmd_DAP_SWD_Configure(uint8_t cfg)
+static int cmsis_dap_cmd_dap_swd_configure(uint8_t cfg)
{
- int retval;
uint8_t *command = cmsis_dap_handle->command;
command[0] = CMD_DAP_SWD_CONFIGURE;
command[1] = cfg;
- retval = cmsis_dap_xfer(cmsis_dap_handle, 2);
-
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 2);
if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) {
LOG_ERROR("CMSIS-DAP command CMD_SWD_Configure failed.");
return ERROR_JTAG_DEVICE_ERROR;
@@ -525,16 +547,14 @@ static int cmsis_dap_cmd_DAP_SWD_Configure(uint8_t cfg)
}
#if 0
-static int cmsis_dap_cmd_DAP_Delay(uint16_t delay_us)
+static int cmsis_dap_cmd_dap_delay(uint16_t delay_us)
{
- int retval;
uint8_t *command = cmsis_dap_handle->command;
command[0] = CMD_DAP_DELAY;
h_u16_to_le(&command[1], delay_us);
- retval = cmsis_dap_xfer(cmsis_dap_handle, 3);
-
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 3);
if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) {
LOG_ERROR("CMSIS-DAP command CMD_Delay failed.");
return ERROR_JTAG_DEVICE_ERROR;
@@ -546,7 +566,6 @@ static int cmsis_dap_cmd_DAP_Delay(uint16_t delay_us)
static int cmsis_dap_metacmd_targetsel(uint32_t instance_id)
{
- int retval;
uint8_t *command = cmsis_dap_handle->command;
const uint32_t SEQ_RD = 0x80, SEQ_WR = 0x00;
@@ -574,12 +593,171 @@ static int cmsis_dap_metacmd_targetsel(uint32_t instance_id)
idx += 4;
command[idx++] = parity_u32(instance_id);
- retval = cmsis_dap_xfer(cmsis_dap_handle, idx);
-
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, idx);
if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) {
LOG_ERROR("CMSIS-DAP command SWD_Sequence failed.");
return ERROR_JTAG_DEVICE_ERROR;
}
+
+ return ERROR_OK;
+}
+
+/**
+ * Sets the SWO transport mode.
+ * @param[in] transport The transport mode. Can be None, SWO_Data or
+ * WinUSB (requires CMSIS-DAP v2).
+ */
+static int cmsis_dap_cmd_dap_swo_transport(uint8_t transport)
+{
+ uint8_t *command = cmsis_dap_handle->command;
+
+ command[0] = CMD_DAP_SWO_TRANSPORT;
+ command[1] = transport;
+
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 2);
+ if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) {
+ LOG_ERROR("CMSIS-DAP: command CMD_SWO_Transport(%d) failed.", transport);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ return ERROR_OK;
+}
+
+/**
+ * Sets the SWO trace capture mode.
+ * @param[in] mode Trace capture mode. Can be UART or MANCHESTER.
+ */
+static int cmsis_dap_cmd_dap_swo_mode(uint8_t mode)
+{
+ uint8_t *command = cmsis_dap_handle->command;
+
+ command[0] = CMD_DAP_SWO_MODE;
+ command[1] = mode;
+
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 2);
+ if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) {
+ LOG_ERROR("CMSIS-DAP: command CMD_SWO_Mode(%d) failed.", mode);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ return ERROR_OK;
+}
+
+/**
+ * Sets the baudrate for capturing SWO trace data.
+ * Can be called iteratively to determine supported baudrates.
+ * @param[in] in_baudrate Requested baudrate.
+ * @param[out] dev_baudrate Actual baudrate or 0 (baudrate not configured).
+ * When requested baudrate is not achievable the
+ * closest configured baudrate can be returned or
+ * 0 which indicates that baudrate was not configured.
+ */
+static int cmsis_dap_cmd_dap_swo_baudrate(
+ uint32_t in_baudrate,
+ uint32_t *dev_baudrate)
+{
+ uint8_t *command = cmsis_dap_handle->command;
+
+ command[0] = CMD_DAP_SWO_BAUDRATE;
+ h_u32_to_le(&command[1], in_baudrate);
+
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 4);
+ uint32_t rvbr = le_to_h_u32(&cmsis_dap_handle->response[1]);
+ if (retval != ERROR_OK || rvbr == 0) {
+ LOG_ERROR("CMSIS-DAP: command CMD_SWO_Baudrate(%u) -> %u failed.", in_baudrate, rvbr);
+ if (dev_baudrate)
+ *dev_baudrate = 0;
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ if (dev_baudrate)
+ *dev_baudrate = rvbr;
+
+ return ERROR_OK;
+}
+
+/**
+ * Controls the SWO trace data capture.
+ * @param[in] control Start or stop a trace. Starting capture automatically
+ * flushes any existing trace data in buffers which has
+ * not yet been read.
+ */
+static int cmsis_dap_cmd_dap_swo_control(uint8_t control)
+{
+ uint8_t *command = cmsis_dap_handle->command;
+
+ command[0] = CMD_DAP_SWO_CONTROL;
+ command[1] = control;
+
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 2);
+ if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) {
+ LOG_ERROR("CMSIS-DAP: command CMD_SWO_Control(%d) failed.", control);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ return ERROR_OK;
+}
+
+/**
+ * Reads the SWO trace status.
+ * @param[out] trace_status The trace's status.
+ * Bit0: Trace Capture (1 - active, 0 - inactive).
+ * Bit6: Trace Stream Error.
+ * Bit7: Trace Buffer Overrun.
+ * @param[out] trace_count Number of bytes in Trace Buffer (not yet read).
+ */
+static int cmsis_dap_cmd_dap_swo_status(
+ uint8_t *trace_status,
+ size_t *trace_count)
+{
+ uint8_t *command = cmsis_dap_handle->command;
+
+ command[0] = CMD_DAP_SWO_STATUS;
+
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 1);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("CMSIS-DAP: command CMD_SWO_Status failed.");
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ if (trace_status)
+ *trace_status = cmsis_dap_handle->response[1];
+ if (trace_count)
+ *trace_count = le_to_h_u32(&cmsis_dap_handle->response[2]);
+
+ return ERROR_OK;
+}
+
+/**
+ * Reads the captured SWO trace data from Trace Buffer.
+ * @param[in] max_trace_count Maximum number of Trace Data bytes to read.
+ * @param[out] trace_status The trace's status.
+ * @param[out] trace_count Number of Trace Data bytes read.
+ * @param[out] data Trace Data bytes read.
+ */
+static int cmsis_dap_cmd_dap_swo_data(
+ size_t max_trace_count,
+ uint8_t *trace_status,
+ size_t *trace_count,
+ uint8_t *data)
+{
+ uint8_t *command = cmsis_dap_handle->command;
+
+ command[0] = CMD_DAP_SWO_DATA;
+ h_u16_to_le(&command[1], max_trace_count);
+
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 3);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("CMSIS-DAP: command CMD_SWO_Data failed.");
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ *trace_status = cmsis_dap_handle->response[1];
+ *trace_count = le_to_h_u16(&cmsis_dap_handle->response[2]);
+
+ if (*trace_count > 0)
+ memcpy(data, &cmsis_dap_handle->response[4], *trace_count);
+
return ERROR_OK;
}
@@ -620,8 +798,8 @@ static void cmsis_dap_swd_write_from_queue(struct cmsis_dap *dap)
* able to automatically retry anything (because ARM
* has forgotten to implement sticky error flags
* clearing). See also comments regarding
- * cmsis_dap_cmd_DAP_TFER_Configure() and
- * cmsis_dap_cmd_DAP_SWD_Configure() in
+ * cmsis_dap_cmd_dap_tfer_configure() and
+ * cmsis_dap_cmd_dap_swd_configure() in
* cmsis_dap_init().
*/
if (!(cmd & SWD_CMD_RnW) &&
@@ -640,7 +818,6 @@ static void cmsis_dap_swd_write_from_queue(struct cmsis_dap *dap)
}
int retval = dap->backend->write(dap, idx, USB_TIMEOUT);
-
if (retval < 0) {
queued_retval = retval;
goto skip;
@@ -805,7 +982,7 @@ static int cmsis_dap_get_serial_info(void)
{
uint8_t *data;
- int retval = cmsis_dap_cmd_DAP_Info(INFO_ID_SERNUM, &data);
+ int retval = cmsis_dap_cmd_dap_info(INFO_ID_SERNUM, &data);
if (retval != ERROR_OK)
return retval;
@@ -820,7 +997,7 @@ static int cmsis_dap_get_version_info(void)
uint8_t *data;
/* INFO_ID_FW_VER - string */
- int retval = cmsis_dap_cmd_DAP_Info(INFO_ID_FW_VER, &data);
+ int retval = cmsis_dap_cmd_dap_info(INFO_ID_FW_VER, &data);
if (retval != ERROR_OK)
return retval;
@@ -835,7 +1012,7 @@ static int cmsis_dap_get_caps_info(void)
uint8_t *data;
/* INFO_ID_CAPS - byte */
- int retval = cmsis_dap_cmd_DAP_Info(INFO_ID_CAPS, &data);
+ int retval = cmsis_dap_cmd_dap_info(INFO_ID_CAPS, &data);
if (retval != ERROR_OK)
return retval;
@@ -848,16 +1025,39 @@ static int cmsis_dap_get_caps_info(void)
LOG_INFO("CMSIS-DAP: %s", info_caps_str[0]);
if (caps & INFO_CAPS_JTAG)
LOG_INFO("CMSIS-DAP: %s", info_caps_str[1]);
+ if (caps & INFO_CAPS_SWO_UART)
+ LOG_INFO("CMSIS-DAP: %s", info_caps_str[2]);
+ if (caps & INFO_CAPS_SWO_MANCHESTER)
+ LOG_INFO("CMSIS-DAP: %s", info_caps_str[3]);
}
return ERROR_OK;
}
+static int cmsis_dap_get_swo_buf_sz(uint32_t *swo_buf_sz)
+{
+ uint8_t *data;
+
+ /* INFO_ID_SWO_BUF_SZ - word */
+ int retval = cmsis_dap_cmd_dap_info(INFO_ID_SWO_BUF_SZ, &data);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (data[0] != 4)
+ return ERROR_FAIL;
+
+ *swo_buf_sz = le_to_h_u32(&data[1]);
+
+ LOG_INFO("CMSIS-DAP: SWO Trace Buffer Size = %u bytes", *swo_buf_sz);
+
+ return ERROR_OK;
+}
+
static int cmsis_dap_get_status(void)
{
uint8_t d;
- int retval = cmsis_dap_cmd_DAP_SWJ_Pins(0, 0, 0, &d);
+ int retval = cmsis_dap_cmd_dap_swj_pins(0, 0, 0, &d);
if (retval == ERROR_OK) {
LOG_INFO("SWCLK/TCK = %d SWDIO/TMS = %d TDI = %d TDO = %d nTRST = %d nRESET = %d",
@@ -884,11 +1084,11 @@ static int cmsis_dap_swd_switch_seq(enum swd_special_seq seq)
* Reconnecting would break connecting under reset. */
/* First disconnect before connecting, Atmel EDBG needs it for SAMD/R/L/C */
- cmsis_dap_cmd_DAP_Disconnect();
+ cmsis_dap_cmd_dap_disconnect();
/* When we are reconnecting, DAP_Connect needs to be rerun, at
* least on Keil ULINK-ME */
- retval = cmsis_dap_cmd_DAP_Connect(CONNECT_SWD);
+ retval = cmsis_dap_cmd_dap_connect(CONNECT_SWD);
if (retval != ERROR_OK)
return retval;
}
@@ -929,25 +1129,23 @@ static int cmsis_dap_swd_switch_seq(enum swd_special_seq seq)
return ERROR_FAIL;
}
- retval = cmsis_dap_cmd_DAP_SWJ_Sequence(s_len, s);
+ retval = cmsis_dap_cmd_dap_swj_sequence(s_len, s);
if (retval != ERROR_OK)
return retval;
/* Atmel EDBG needs renew clock setting after SWJ_Sequence
* otherwise default frequency is used */
- return cmsis_dap_cmd_DAP_SWJ_Clock(jtag_get_speed_khz());
+ return cmsis_dap_cmd_dap_swj_clock(jtag_get_speed_khz());
}
static int cmsis_dap_swd_open(void)
{
- int retval;
-
if (!(cmsis_dap_handle->caps & INFO_CAPS_SWD)) {
LOG_ERROR("CMSIS-DAP: SWD not supported");
return ERROR_JTAG_DEVICE_ERROR;
}
- retval = cmsis_dap_cmd_DAP_Connect(CONNECT_SWD);
+ int retval = cmsis_dap_cmd_dap_connect(CONNECT_SWD);
if (retval != ERROR_OK)
return retval;
@@ -959,10 +1157,9 @@ static int cmsis_dap_swd_open(void)
static int cmsis_dap_init(void)
{
- int retval;
uint8_t *data;
- retval = cmsis_dap_open();
+ int retval = cmsis_dap_open();
if (retval != ERROR_OK)
return retval;
@@ -991,7 +1188,7 @@ static int cmsis_dap_init(void)
return ERROR_JTAG_DEVICE_ERROR;
}
- retval = cmsis_dap_cmd_DAP_Connect(CONNECT_JTAG);
+ retval = cmsis_dap_cmd_dap_connect(CONNECT_JTAG);
if (retval != ERROR_OK)
return retval;
@@ -1004,7 +1201,7 @@ static int cmsis_dap_init(void)
pending_queue_len = 12;
/* INFO_ID_PKT_SZ - short */
- retval = cmsis_dap_cmd_DAP_Info(INFO_ID_PKT_SZ, &data);
+ retval = cmsis_dap_cmd_dap_info(INFO_ID_PKT_SZ, &data);
if (retval != ERROR_OK)
goto init_err;
@@ -1027,7 +1224,7 @@ static int cmsis_dap_init(void)
}
/* INFO_ID_PKT_CNT - byte */
- retval = cmsis_dap_cmd_DAP_Info(INFO_ID_PKT_CNT, &data);
+ retval = cmsis_dap_cmd_dap_info(INFO_ID_PKT_CNT, &data);
if (retval != ERROR_OK)
goto init_err;
@@ -1055,36 +1252,36 @@ static int cmsis_dap_init(void)
/* Now try to connect to the target
* TODO: This is all SWD only @ present */
- retval = cmsis_dap_cmd_DAP_SWJ_Clock(jtag_get_speed_khz());
+ retval = cmsis_dap_cmd_dap_swj_clock(jtag_get_speed_khz());
if (retval != ERROR_OK)
goto init_err;
/* Ask CMSIS-DAP to automatically retry on receiving WAIT for
* up to 64 times. This must be changed to 0 if sticky
* overrun detection is enabled. */
- retval = cmsis_dap_cmd_DAP_TFER_Configure(0, 64, 0);
+ retval = cmsis_dap_cmd_dap_tfer_configure(0, 64, 0);
if (retval != ERROR_OK)
goto init_err;
if (swd_mode) {
/* Data Phase (bit 2) must be set to 1 if sticky overrun
* detection is enabled */
- retval = cmsis_dap_cmd_DAP_SWD_Configure(0); /* 1 TRN, no Data Phase */
+ retval = cmsis_dap_cmd_dap_swd_configure(0); /* 1 TRN, no Data Phase */
if (retval != ERROR_OK)
goto init_err;
}
/* Both LEDs on */
/* Intentionally not checked for error, debugging will work
* without LEDs */
- (void)cmsis_dap_cmd_DAP_LED(LED_ID_CONNECT, LED_ON);
- (void)cmsis_dap_cmd_DAP_LED(LED_ID_RUN, LED_ON);
+ (void)cmsis_dap_cmd_dap_led(LED_ID_CONNECT, LED_ON);
+ (void)cmsis_dap_cmd_dap_led(LED_ID_RUN, LED_ON);
/* support connecting with srst asserted */
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
if (jtag_reset_config & RESET_SRST_NO_GATING) {
- retval = cmsis_dap_cmd_DAP_SWJ_Pins(0, SWJ_PIN_SRST, 0, NULL);
+ retval = cmsis_dap_cmd_dap_swj_pins(0, SWJ_PIN_SRST, 0, NULL);
if (retval != ERROR_OK)
goto init_err;
LOG_INFO("Connecting under reset");
@@ -1106,10 +1303,11 @@ static int cmsis_dap_swd_init(void)
static int cmsis_dap_quit(void)
{
- cmsis_dap_cmd_DAP_Disconnect();
+ cmsis_dap_cmd_dap_disconnect();
+
/* Both LEDs off */
- cmsis_dap_cmd_DAP_LED(LED_ID_RUN, LED_OFF);
- cmsis_dap_cmd_DAP_LED(LED_ID_CONNECT, LED_OFF);
+ cmsis_dap_cmd_dap_led(LED_ID_RUN, LED_OFF);
+ cmsis_dap_cmd_dap_led(LED_ID_CONNECT, LED_OFF);
cmsis_dap_close(cmsis_dap_handle);
@@ -1127,7 +1325,7 @@ static int cmsis_dap_reset(int trst, int srst)
if (!trst)
output_pins |= SWJ_PIN_TRST;
- int retval = cmsis_dap_cmd_DAP_SWJ_Pins(output_pins,
+ int retval = cmsis_dap_cmd_dap_swj_pins(output_pins,
SWJ_PIN_TRST | SWJ_PIN_SRST, 0, NULL);
if (retval != ERROR_OK)
LOG_ERROR("CMSIS-DAP: Interface reset failed");
@@ -1137,7 +1335,7 @@ static int cmsis_dap_reset(int trst, int srst)
static void cmsis_dap_execute_sleep(struct jtag_command *cmd)
{
#if 0
- int retval = cmsis_dap_cmd_DAP_Delay(cmd->cmd.sleep->us);
+ int retval = cmsis_dap_cmd_dap_delay(cmd->cmd.sleep->us);
if (retval != ERROR_OK)
#endif
jtag_sleep(cmd->cmd.sleep->us);
@@ -1148,10 +1346,11 @@ static int cmsis_dap_execute_tlr_reset(struct jtag_command *cmd)
{
LOG_INFO("cmsis-dap JTAG TLR_RESET");
uint8_t seq = 0xff;
- int ret = cmsis_dap_cmd_DAP_SWJ_Sequence(8, &seq);
- if (ret == ERROR_OK)
+
+ int retval = cmsis_dap_cmd_dap_swj_sequence(8, &seq);
+ if (retval == ERROR_OK)
tap_set_state(TAP_RESET);
- return ret;
+ return retval;
}
/* Set new end state */
@@ -1369,11 +1568,8 @@ static void cmsis_dap_add_tms_sequence(const uint8_t *sequence, int s_len)
/* Move to the end state by queuing a sequence to clock into TMS */
static void cmsis_dap_state_move(void)
{
- uint8_t tms_scan;
- uint8_t tms_scan_bits;
-
- tms_scan = tap_get_tms_path(tap_get_state(), tap_get_end_state());
- tms_scan_bits = tap_get_tms_path_len(tap_get_state(), tap_get_end_state());
+ uint8_t tms_scan = tap_get_tms_path(tap_get_state(), tap_get_end_state());
+ uint8_t tms_scan_bits = tap_get_tms_path_len(tap_get_state(), tap_get_end_state());
LOG_DEBUG_IO("state move from %s to %s: %d clocks, %02X on tms",
tap_state_name(tap_get_state()), tap_state_name(tap_get_end_state()),
@@ -1488,11 +1684,10 @@ static void cmsis_dap_execute_scan(struct jtag_command *cmd)
static void cmsis_dap_pathmove(int num_states, tap_state_t *path)
{
- int i;
uint8_t tms0 = 0x00;
uint8_t tms1 = 0xff;
- for (i = 0; i < num_states; i++) {
+ for (int i = 0; i < num_states; i++) {
if (path[i] == tap_state_transition(tap_get_state(), false))
cmsis_dap_add_tms_sequence(&tms0, 1);
else if (path[i] == tap_state_transition(tap_get_state(), true))
@@ -1520,12 +1715,10 @@ static void cmsis_dap_execute_pathmove(struct jtag_command *cmd)
static void cmsis_dap_stableclocks(int num_cycles)
{
- int i;
-
uint8_t tms = tap_get_state() == TAP_RESET;
/* TODO: Perform optimizations? */
/* Execute num_cycles. */
- for (i = 0; i < num_cycles; i++)
+ for (int i = 0; i < num_cycles; i++)
cmsis_dap_add_tms_sequence(&tms, 1);
}
@@ -1565,7 +1758,7 @@ static void cmsis_dap_execute_stableclocks(struct jtag_command *cmd)
static void cmsis_dap_execute_tms(struct jtag_command *cmd)
{
LOG_DEBUG_IO("TMS: %d bits", cmd->cmd.tms->num_bits);
- cmsis_dap_cmd_DAP_SWJ_Sequence(cmd->cmd.tms->num_bits, cmd->cmd.tms->bits);
+ cmsis_dap_cmd_dap_swj_sequence(cmd->cmd.tms->num_bits, cmd->cmd.tms->bits);
}
/* TODO: Is there need to call cmsis_dap_flush() for the JTAG_PATHMOVE,
@@ -1623,7 +1816,7 @@ static int cmsis_dap_speed(int speed)
return ERROR_JTAG_NOT_IMPLEMENTED;
}
- return cmsis_dap_cmd_DAP_SWJ_Clock(speed);
+ return cmsis_dap_cmd_dap_swj_clock(speed);
}
static int cmsis_dap_speed_div(int speed, int *khz)
@@ -1638,6 +1831,157 @@ static int cmsis_dap_khz(int khz, int *jtag_speed)
return ERROR_OK;
}
+static bool calculate_swo_prescaler(unsigned int traceclkin_freq,
+ uint32_t trace_freq, uint16_t *prescaler)
+{
+ unsigned int presc = (traceclkin_freq + trace_freq / 2) / trace_freq;
+ if (presc == 0 || presc > TPIU_ACPR_MAX_SWOSCALER + 1)
+ return false;
+
+ /* Probe's UART speed must be within 3% of the TPIU's SWO baud rate. */
+ unsigned int max_deviation = (traceclkin_freq * 3) / 100;
+ if (presc * trace_freq < traceclkin_freq - max_deviation ||
+ presc * trace_freq > traceclkin_freq + max_deviation)
+ return false;
+
+ *prescaler = presc;
+
+ return true;
+}
+
+/**
+ * @see adapter_driver::config_trace
+ */
+static int cmsis_dap_config_trace(
+ bool trace_enabled,
+ enum tpiu_pin_protocol pin_protocol,
+ uint32_t port_size,
+ unsigned int *swo_freq,
+ unsigned int traceclkin_hz,
+ uint16_t *swo_prescaler)
+{
+ int retval;
+
+ if (!trace_enabled) {
+ if (cmsis_dap_handle->trace_enabled) {
+ retval = cmsis_dap_cmd_dap_swo_control(DAP_SWO_CONTROL_STOP);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to disable the SWO-trace.");
+ return retval;
+ }
+ }
+ cmsis_dap_handle->trace_enabled = false;
+ LOG_INFO("SWO-trace disabled.");
+ return ERROR_OK;
+ }
+
+ if (!(cmsis_dap_handle->caps & INFO_CAPS_SWO_UART) &&
+ !(cmsis_dap_handle->caps & INFO_CAPS_SWO_MANCHESTER)) {
+ LOG_ERROR("SWO-trace is not supported by the device.");
+ return ERROR_FAIL;
+ }
+
+ uint8_t swo_mode;
+ if (pin_protocol == TPIU_PIN_PROTOCOL_ASYNC_UART &&
+ (cmsis_dap_handle->caps & INFO_CAPS_SWO_UART)) {
+ swo_mode = DAP_SWO_MODE_UART;
+ } else if (pin_protocol == TPIU_PIN_PROTOCOL_ASYNC_MANCHESTER &&
+ (cmsis_dap_handle->caps & INFO_CAPS_SWO_MANCHESTER)) {
+ swo_mode = DAP_SWO_MODE_MANCHESTER;
+ } else {
+ LOG_ERROR("Selected pin protocol is not supported.");
+ return ERROR_FAIL;
+ }
+
+ if (*swo_freq == 0) {
+ LOG_INFO("SWO-trace frequency autodetection not implemented.");
+ return ERROR_FAIL;
+ }
+
+ retval = cmsis_dap_cmd_dap_swo_control(DAP_SWO_CONTROL_STOP);
+ if (retval != ERROR_OK)
+ return retval;
+
+ cmsis_dap_handle->trace_enabled = false;
+
+ retval = cmsis_dap_get_swo_buf_sz(&cmsis_dap_handle->swo_buf_sz);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = cmsis_dap_cmd_dap_swo_transport(DAP_SWO_TRANSPORT_DATA);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = cmsis_dap_cmd_dap_swo_mode(swo_mode);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = cmsis_dap_cmd_dap_swo_baudrate(*swo_freq, swo_freq);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (!calculate_swo_prescaler(traceclkin_hz, *swo_freq,
+ swo_prescaler)) {
+ LOG_ERROR("SWO frequency is not suitable. Please choose a "
+ "different frequency or use auto-detection.");
+ return ERROR_FAIL;
+ }
+
+ LOG_INFO("SWO frequency: %u Hz.", *swo_freq);
+ LOG_INFO("SWO prescaler: %u.", *swo_prescaler);
+
+ retval = cmsis_dap_cmd_dap_swo_control(DAP_SWO_CONTROL_START);
+ if (retval != ERROR_OK)
+ return retval;
+
+ cmsis_dap_handle->trace_enabled = true;
+
+ return ERROR_OK;
+}
+
+/**
+ * @see adapter_driver::poll_trace
+ */
+static int cmsis_dap_poll_trace(uint8_t *buf, size_t *size)
+{
+ uint8_t trace_status;
+ size_t trace_count;
+
+ if (!cmsis_dap_handle->trace_enabled) {
+ *size = 0;
+ return ERROR_OK;
+ }
+
+ int retval = cmsis_dap_cmd_dap_swo_status(&trace_status, &trace_count);
+ if (retval != ERROR_OK)
+ return retval;
+ if ((trace_status & DAP_SWO_STATUS_CAPTURE_MASK) != DAP_SWO_STATUS_CAPTURE_ACTIVE)
+ return ERROR_FAIL;
+
+ *size = trace_count < *size ? trace_count : *size;
+ size_t read_so_far = 0;
+ do {
+ size_t rb = 0;
+ uint32_t packet_size = cmsis_dap_handle->packet_size - 4 /*data-reply*/;
+ uint32_t remaining = *size - read_so_far;
+ if (remaining < packet_size)
+ packet_size = remaining;
+ retval = cmsis_dap_cmd_dap_swo_data(
+ packet_size,
+ &trace_status,
+ &rb,
+ &buf[read_so_far]);
+ if (retval != ERROR_OK)
+ return retval;
+ if ((trace_status & DAP_SWO_STATUS_CAPTURE_MASK) != DAP_SWO_STATUS_CAPTURE_ACTIVE)
+ return ERROR_FAIL;
+
+ read_so_far += rb;
+ } while (read_so_far < *size);
+
+ return ERROR_OK;
+}
+
COMMAND_HANDLER(cmsis_dap_handle_info_command)
{
if (cmsis_dap_get_version_info() == ERROR_OK)
@@ -1648,14 +1992,12 @@ COMMAND_HANDLER(cmsis_dap_handle_info_command)
COMMAND_HANDLER(cmsis_dap_handle_cmd_command)
{
- int retval;
- unsigned i;
uint8_t *command = cmsis_dap_handle->command;
- for (i = 0; i < CMD_ARGC; i++)
+ for (unsigned i = 0; i < CMD_ARGC; i++)
command[i] = strtoul(CMD_ARGV[i], NULL, 16);
- retval = cmsis_dap_xfer(cmsis_dap_handle, CMD_ARGC);
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, CMD_ARGC);
if (retval != ERROR_OK) {
LOG_ERROR("CMSIS-DAP command failed.");
@@ -1817,6 +2159,8 @@ struct adapter_driver cmsis_dap_adapter_driver = {
.speed = cmsis_dap_speed,
.khz = cmsis_dap_khz,
.speed_div = cmsis_dap_speed_div,
+ .config_trace = cmsis_dap_config_trace,
+ .poll_trace = cmsis_dap_poll_trace,
.jtag_ops = &cmsis_dap_interface,
.swd_ops = &cmsis_dap_swd_driver,
diff --git a/src/jtag/drivers/cmsis_dap.h b/src/jtag/drivers/cmsis_dap.h
index c9f24c896..634a62c8f 100644
--- a/src/jtag/drivers/cmsis_dap.h
+++ b/src/jtag/drivers/cmsis_dap.h
@@ -18,6 +18,8 @@ struct cmsis_dap {
uint8_t *response;
uint8_t caps;
uint8_t mode;
+ uint32_t swo_buf_sz;
+ bool trace_enabled;
};
struct cmsis_dap_backend {
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/cmsis_dap.c | 532 +++++++++++++++++++++++++++++++++++--------
src/jtag/drivers/cmsis_dap.h | 2 +
src/target/riscv/riscv.c | 9 +
src/target/target.c | 21 +-
src/target/target.h | 7 +
src/target/target_type.h | 5 +
6 files changed, 478 insertions(+), 98 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-06-04 16:45:56
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via c4dd883c9a919b0b0a36bc538157820225b85610 (commit)
from a9fb73a5b0b5bd3ac7b0e14a18b457009fe173f0 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit c4dd883c9a919b0b0a36bc538157820225b85610
Author: Marc Schink <de...@za...>
Date: Mon May 17 12:53:16 2021 +0200
target: Use 'bool' for 'reset_halt'
Change-Id: I974a6360ea7467067511541ac212f2e9d3de7895
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/6262
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/target.c b/src/target/target.c
index 1547b29e7..39a07ad6c 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -5375,7 +5375,7 @@ static int jim_target_reset(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
target_reset_examined(target);
/* determine if we should halt or not. */
- target->reset_halt = !!a;
+ target->reset_halt = (a != 0);
/* When this happens - all workareas are invalid. */
target_free_all_working_areas_restore(target, 0);
diff --git a/src/target/target.h b/src/target/target.h
index 046bd99ae..d86c63eb0 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -157,7 +157,7 @@ struct target {
struct target_event_action *event_action;
- int reset_halt; /* attempt resetting the CPU into the halted mode? */
+ bool reset_halt; /* attempt resetting the CPU into the halted mode? */
target_addr_t working_area; /* working area (initialised RAM). Evaluated
* upon first allocation from virtual/physical address. */
bool working_area_virt_spec; /* virtual address specified? */
-----------------------------------------------------------------------
Summary of changes:
src/target/target.c | 2 +-
src/target/target.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-06-04 16:45:22
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a9fb73a5b0b5bd3ac7b0e14a18b457009fe173f0 (commit)
from 11598cb1be82dcca7995b2b7823a13435079da4f (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit a9fb73a5b0b5bd3ac7b0e14a18b457009fe173f0
Author: Marc Schink <de...@za...>
Date: Tue Nov 3 14:09:37 2020 +0100
drivers/jlink: Remove trailing dots
This makes the messages consistent with most of the rest of
the OpenOCD output.
Change-Id: I915a01187e7fc317e02483ac0bbd39ec077d6321
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/6274
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/jlink.c b/src/jtag/drivers/jlink.c
index 8c1a8116d..6781e14ff 100644
--- a/src/jtag/drivers/jlink.c
+++ b/src/jtag/drivers/jlink.c
@@ -282,7 +282,7 @@ static int jlink_execute_command(struct jtag_command *cmd)
jlink_execute_sleep(cmd);
break;
default:
- LOG_ERROR("BUG: Unknown JTAG command type encountered.");
+ LOG_ERROR("BUG: Unknown JTAG command type encountered");
return ERROR_JTAG_QUEUE_FAILED;
}
@@ -316,7 +316,7 @@ static int jlink_speed(int speed)
ret = jaylink_get_speeds(devh, &tmp);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_get_speeds() failed: %s.",
+ LOG_ERROR("jaylink_get_speeds() failed: %s",
jaylink_strerror(ret));
return ERROR_JTAG_DEVICE_ERROR;
}
@@ -329,13 +329,13 @@ static int jlink_speed(int speed)
if (!speed) {
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_ADAPTIVE_CLOCKING)) {
- LOG_ERROR("Adaptive clocking is not supported by the device.");
+ LOG_ERROR("Adaptive clocking is not supported by the device");
return ERROR_JTAG_NOT_IMPLEMENTED;
}
speed = JAYLINK_SPEED_ADAPTIVE_CLOCKING;
} else if (speed > max_speed) {
- LOG_INFO("Reduced speed from %d kHz to %d kHz (maximum).", speed,
+ LOG_INFO("Reduced speed from %d kHz to %d kHz (maximum)", speed,
max_speed);
speed = max_speed;
}
@@ -343,7 +343,7 @@ static int jlink_speed(int speed)
ret = jaylink_set_speed(devh, speed);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_set_speed() failed: %s.",
+ LOG_ERROR("jaylink_set_speed() failed: %s",
jaylink_strerror(ret));
return ERROR_JTAG_DEVICE_ERROR;
}
@@ -372,7 +372,7 @@ static bool read_device_config(struct device_config *cfg)
ret = jaylink_read_raw_config(devh, (uint8_t *)cfg);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_read_raw_config() failed: %s.",
+ LOG_ERROR("jaylink_read_raw_config() failed: %s",
jaylink_strerror(ret));
return false;
}
@@ -393,7 +393,7 @@ static int select_interface(void)
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_SELECT_TIF)) {
if (iface != JAYLINK_TIF_JTAG) {
- LOG_ERROR("Device supports JTAG transport only.");
+ LOG_ERROR("Device supports JTAG transport only");
return ERROR_JTAG_INIT_FAILED;
}
@@ -403,20 +403,20 @@ static int select_interface(void)
ret = jaylink_get_available_interfaces(devh, &interfaces);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_get_available_interfaces() failed: %s.",
+ LOG_ERROR("jaylink_get_available_interfaces() failed: %s",
jaylink_strerror(ret));
return ERROR_JTAG_INIT_FAILED;
}
if (!(interfaces & (1 << iface))) {
- LOG_ERROR("Selected transport is not supported by the device.");
+ LOG_ERROR("Selected transport is not supported by the device");
return ERROR_JTAG_INIT_FAILED;
}
ret = jaylink_select_interface(devh, iface, NULL);
if (ret < 0) {
- LOG_ERROR("jaylink_select_interface() failed: %s.",
+ LOG_ERROR("jaylink_select_interface() failed: %s",
jaylink_strerror(ret));
return ERROR_JTAG_INIT_FAILED;
}
@@ -437,7 +437,7 @@ static int jlink_register(void)
ret = jaylink_register(devh, &conn, connlist, &count);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_register() failed: %s.", jaylink_strerror(ret));
+ LOG_ERROR("jaylink_register() failed: %s", jaylink_strerror(ret));
return ERROR_FAIL;
}
@@ -452,7 +452,7 @@ static int jlink_register(void)
if (!handle_found) {
LOG_ERROR("Registration failed: maximum number of connections on the "
- "device reached.");
+ "device reached");
return ERROR_FAIL;
}
@@ -475,13 +475,13 @@ static bool adjust_swd_buffer_size(void)
ret = jaylink_get_free_memory(devh, &tmp);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_get_free_memory() failed: %s.",
+ LOG_ERROR("jaylink_get_free_memory() failed: %s",
jaylink_strerror(ret));
return false;
}
if (tmp < 143) {
- LOG_ERROR("Not enough free device internal memory: %" PRIu32 " bytes.", tmp);
+ LOG_ERROR("Not enough free device internal memory: %" PRIu32 " bytes", tmp);
return false;
}
@@ -489,7 +489,7 @@ static bool adjust_swd_buffer_size(void)
if (tmp != swd_buffer_size) {
swd_buffer_size = tmp;
- LOG_DEBUG("Adjusted SWD transaction buffer size to %u bytes.",
+ LOG_DEBUG("Adjusted SWD transaction buffer size to %u bytes",
swd_buffer_size);
}
@@ -542,7 +542,7 @@ static bool jlink_usb_location_equal(struct jaylink_device *dev)
if (retval == JAYLINK_ERR_NOT_SUPPORTED) {
return false;
} else if (retval != JAYLINK_OK) {
- LOG_WARNING("jaylink_device_get_usb_bus_ports() failed: %s.",
+ LOG_WARNING("jaylink_device_get_usb_bus_ports() failed: %s",
jaylink_strerror(retval));
return false;
}
@@ -558,7 +558,7 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device)
{
int ret = jaylink_discovery_scan(jayctx, ifaces);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_discovery_scan() failed: %s.", jaylink_strerror(ret));
+ LOG_ERROR("jaylink_discovery_scan() failed: %s", jaylink_strerror(ret));
jaylink_exit(jayctx);
return ERROR_JTAG_INIT_FAILED;
}
@@ -568,7 +568,7 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device)
ret = jaylink_get_devices(jayctx, &devs, &num_devices);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_get_devices() failed: %s.", jaylink_strerror(ret));
+ LOG_ERROR("jaylink_get_devices() failed: %s", jaylink_strerror(ret));
jaylink_exit(jayctx);
return ERROR_JTAG_INIT_FAILED;
}
@@ -576,7 +576,7 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device)
use_usb_location = (jtag_usb_get_location() != NULL);
if (!use_serial_number && !use_usb_address && !use_usb_location && num_devices > 1) {
- LOG_ERROR("Multiple devices found, specify the desired device.");
+ LOG_ERROR("Multiple devices found, specify the desired device");
jaylink_free_devices(devs, true);
jaylink_exit(jayctx);
return ERROR_JTAG_INIT_FAILED;
@@ -594,7 +594,7 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device)
if (ret == JAYLINK_ERR_NOT_AVAILABLE) {
continue;
} else if (ret != JAYLINK_OK) {
- LOG_WARNING("jaylink_device_get_serial_number() failed: %s.",
+ LOG_WARNING("jaylink_device_get_serial_number() failed: %s",
jaylink_strerror(ret));
continue;
}
@@ -610,7 +610,7 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device)
if (ret == JAYLINK_ERR_NOT_SUPPORTED) {
continue;
} else if (ret != JAYLINK_OK) {
- LOG_WARNING("jaylink_device_get_usb_address() failed: %s.",
+ LOG_WARNING("jaylink_device_get_usb_address() failed: %s",
jaylink_strerror(ret));
continue;
}
@@ -629,7 +629,7 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device)
break;
}
- LOG_ERROR("Failed to open device: %s.", jaylink_strerror(ret));
+ LOG_ERROR("Failed to open device: %s", jaylink_strerror(ret));
}
jaylink_free_devices(devs, true);
@@ -645,25 +645,25 @@ static int jlink_init(void)
struct jaylink_hardware_status hwstatus;
size_t length;
- LOG_DEBUG("Using libjaylink %s (compiled with %s).",
+ LOG_DEBUG("Using libjaylink %s (compiled with %s)",
jaylink_version_package_get_string(), JAYLINK_VERSION_PACKAGE_STRING);
if (!jaylink_library_has_cap(JAYLINK_CAP_HIF_USB) && use_usb_address) {
- LOG_ERROR("J-Link driver does not support USB devices.");
+ LOG_ERROR("J-Link driver does not support USB devices");
return ERROR_JTAG_INIT_FAILED;
}
ret = jaylink_init(&jayctx);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_init() failed: %s.", jaylink_strerror(ret));
+ LOG_ERROR("jaylink_init() failed: %s", jaylink_strerror(ret));
return ERROR_JTAG_INIT_FAILED;
}
ret = jaylink_log_set_callback(jayctx, &jaylink_log_handler, NULL);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_log_set_callback() failed: %s.",
+ LOG_ERROR("jaylink_log_set_callback() failed: %s",
jaylink_strerror(ret));
jaylink_exit(jayctx);
return ERROR_JTAG_INIT_FAILED;
@@ -681,7 +681,7 @@ static int jlink_init(void)
}
if (!found_device) {
- LOG_ERROR("No J-Link device found.");
+ LOG_ERROR("No J-Link device found");
jaylink_exit(jayctx);
return ERROR_JTAG_INIT_FAILED;
}
@@ -694,7 +694,7 @@ static int jlink_init(void)
ret = jaylink_get_firmware_version(devh, &firmware_version, &length);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_get_firmware_version() failed: %s.",
+ LOG_ERROR("jaylink_get_firmware_version() failed: %s",
jaylink_strerror(ret));
jaylink_close(devh);
jaylink_exit(jayctx);
@@ -703,14 +703,14 @@ static int jlink_init(void)
LOG_INFO("%s", firmware_version);
free(firmware_version);
} else {
- LOG_WARNING("Device responds empty firmware version string.");
+ LOG_WARNING("Device responds empty firmware version string");
}
memset(caps, 0, JAYLINK_DEV_EXT_CAPS_SIZE);
ret = jaylink_get_caps(devh, caps);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_get_caps() failed: %s.", jaylink_strerror(ret));
+ LOG_ERROR("jaylink_get_caps() failed: %s", jaylink_strerror(ret));
jaylink_close(devh);
jaylink_exit(jayctx);
return ERROR_JTAG_INIT_FAILED;
@@ -720,7 +720,7 @@ static int jlink_init(void)
ret = jaylink_get_extended_caps(devh, caps);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_get_extended_caps() failed: %s.",
+ LOG_ERROR("jaylink_get_extended_caps() failed: %s",
jaylink_strerror(ret));
jaylink_close(devh);
jaylink_exit(jayctx);
@@ -734,7 +734,7 @@ static int jlink_init(void)
ret = jaylink_get_hardware_version(devh, &hwver);
if (ret != JAYLINK_OK) {
- LOG_ERROR("Failed to retrieve hardware version: %s.",
+ LOG_ERROR("Failed to retrieve hardware version: %s",
jaylink_strerror(ret));
jaylink_close(devh);
jaylink_exit(jayctx);
@@ -763,7 +763,7 @@ static int jlink_init(void)
if (jaylink_has_cap(caps, JAYLINK_DEV_CAP_READ_CONFIG)) {
if (!read_device_config(&config)) {
- LOG_ERROR("Failed to read device configuration data.");
+ LOG_ERROR("Failed to read device configuration data");
jaylink_close(devh);
jaylink_exit(jayctx);
return ERROR_JTAG_INIT_FAILED;
@@ -775,7 +775,7 @@ static int jlink_init(void)
ret = jaylink_get_hardware_status(devh, &hwstatus);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_get_hardware_status() failed: %s.",
+ LOG_ERROR("jaylink_get_hardware_status() failed: %s",
jaylink_strerror(ret));
jaylink_close(devh);
jaylink_exit(jayctx);
@@ -837,14 +837,14 @@ static int jlink_quit(void)
ret = jaylink_swo_stop(devh);
if (ret != JAYLINK_OK)
- LOG_ERROR("jaylink_swo_stop() failed: %s.", jaylink_strerror(ret));
+ LOG_ERROR("jaylink_swo_stop() failed: %s", jaylink_strerror(ret));
}
if (jaylink_has_cap(caps, JAYLINK_DEV_CAP_REGISTER)) {
ret = jaylink_unregister(devh, &conn, connlist, &count);
if (ret != JAYLINK_OK)
- LOG_ERROR("jaylink_unregister() failed: %s.",
+ LOG_ERROR("jaylink_unregister() failed: %s",
jaylink_strerror(ret));
}
@@ -892,7 +892,7 @@ static void jlink_path_move(int num_states, tap_state_t *path)
else if (path[i] == tap_state_transition(tap_get_state(), true))
jlink_clock_data(NULL, 0, &tms, 0, NULL, 0, 1);
else {
- LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition.",
+ LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition",
tap_state_name(tap_get_state()), tap_state_name(path[i]));
exit(-1);
}
@@ -935,7 +935,7 @@ static void jlink_runtest(int num_cycles)
static void jlink_reset(int trst, int srst)
{
- LOG_DEBUG("TRST: %i, SRST: %i.", trst, srst);
+ LOG_DEBUG("TRST: %i, SRST: %i", trst, srst);
/* Signals are active low. */
if (srst == 0)
@@ -963,17 +963,17 @@ COMMAND_HANDLER(jlink_usb_command)
int tmp;
if (CMD_ARGC != 1) {
- command_print(CMD, "Need exactly one argument for jlink usb.");
+ command_print(CMD, "Need exactly one argument for jlink usb");
return ERROR_COMMAND_SYNTAX_ERROR;
}
if (sscanf(CMD_ARGV[0], "%i", &tmp) != 1) {
- command_print(CMD, "Invalid USB address: %s.", CMD_ARGV[0]);
+ command_print(CMD, "Invalid USB address: %s", CMD_ARGV[0]);
return ERROR_FAIL;
}
if (tmp < JAYLINK_USB_ADDRESS_0 || tmp > JAYLINK_USB_ADDRESS_3) {
- command_print(CMD, "Invalid USB address: %s.", CMD_ARGV[0]);
+ command_print(CMD, "Invalid USB address: %s", CMD_ARGV[0]);
return ERROR_FAIL;
}
@@ -990,17 +990,17 @@ COMMAND_HANDLER(jlink_serial_command)
int ret;
if (CMD_ARGC != 1) {
- command_print(CMD, "Need exactly one argument for jlink serial.");
+ command_print(CMD, "Need exactly one argument for jlink serial");
return ERROR_COMMAND_SYNTAX_ERROR;
}
ret = jaylink_parse_serial_number(CMD_ARGV[0], &serial_number);
if (ret == JAYLINK_ERR) {
- command_print(CMD, "Invalid serial number: %s.", CMD_ARGV[0]);
+ command_print(CMD, "Invalid serial number: %s", CMD_ARGV[0]);
return ERROR_FAIL;
} else if (ret != JAYLINK_OK) {
- command_print(CMD, "jaylink_parse_serial_number() failed: %s.",
+ command_print(CMD, "jaylink_parse_serial_number() failed: %s",
jaylink_strerror(ret));
return ERROR_FAIL;
}
@@ -1019,7 +1019,7 @@ COMMAND_HANDLER(jlink_handle_hwstatus_command)
ret = jaylink_get_hardware_status(devh, &status);
if (ret != JAYLINK_OK) {
- command_print(CMD, "jaylink_get_hardware_status() failed: %s.",
+ command_print(CMD, "jaylink_get_hardware_status() failed: %s",
jaylink_strerror(ret));
return ERROR_FAIL;
}
@@ -1032,7 +1032,7 @@ COMMAND_HANDLER(jlink_handle_hwstatus_command)
status.tres, status.trst);
if (status.target_voltage < 1500)
- command_print(CMD, "Target voltage too low. Check target power.");
+ command_print(CMD, "Target voltage too low. Check target power");
return ERROR_OK;
}
@@ -1044,19 +1044,19 @@ COMMAND_HANDLER(jlink_handle_free_memory_command)
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_GET_FREE_MEMORY)) {
command_print(CMD, "Retrieval of free memory is not supported by "
- "the device.");
+ "the device");
return ERROR_OK;
}
ret = jaylink_get_free_memory(devh, &tmp);
if (ret != JAYLINK_OK) {
- command_print(CMD, "jaylink_get_free_memory() failed: %s.",
+ command_print(CMD, "jaylink_get_free_memory() failed: %s",
jaylink_strerror(ret));
return ERROR_FAIL;
}
- command_print(CMD, "Device has %" PRIu32 " bytes of free memory.", tmp);
+ command_print(CMD, "Device has %" PRIu32 " bytes of free memory", tmp);
return ERROR_OK;
}
@@ -1081,7 +1081,7 @@ COMMAND_HANDLER(jlink_handle_jlink_jtag_command)
command_print(CMD, "JTAG command version: %i", version);
} else if (CMD_ARGC == 1) {
if (sscanf(CMD_ARGV[0], "%i", &tmp) != 1) {
- command_print(CMD, "Invalid argument: %s.", CMD_ARGV[0]);
+ command_print(CMD, "Invalid argument: %s", CMD_ARGV[0]);
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -1093,11 +1093,11 @@ COMMAND_HANDLER(jlink_handle_jlink_jtag_command)
jtag_command_version = JAYLINK_JTAG_VERSION_3;
break;
default:
- command_print(CMD, "Invalid argument: %s.", CMD_ARGV[0]);
+ command_print(CMD, "Invalid argument: %s", CMD_ARGV[0]);
return ERROR_COMMAND_SYNTAX_ERROR;
}
} else {
- command_print(CMD, "Need exactly one argument for jlink jtag.");
+ command_print(CMD, "Need exactly one argument for jlink jtag");
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -1110,14 +1110,13 @@ COMMAND_HANDLER(jlink_handle_target_power_command)
int enable;
if (CMD_ARGC != 1) {
- command_print(CMD, "Need exactly one argument for jlink "
- "targetpower.");
+ command_print(CMD, "Need exactly one argument for jlink targetpower");
return ERROR_COMMAND_SYNTAX_ERROR;
}
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_SET_TARGET_POWER)) {
command_print(CMD, "Target power supply is not supported by the "
- "device.");
+ "device");
return ERROR_OK;
}
@@ -1126,14 +1125,14 @@ COMMAND_HANDLER(jlink_handle_target_power_command)
} else if (!strcmp(CMD_ARGV[0], "off")) {
enable = false;
} else {
- command_print(CMD, "Invalid argument: %s.", CMD_ARGV[0]);
+ command_print(CMD, "Invalid argument: %s", CMD_ARGV[0]);
return ERROR_FAIL;
}
ret = jaylink_set_target_power(devh, enable);
if (ret != JAYLINK_OK) {
- command_print(CMD, "jaylink_set_target_power() failed: %s.",
+ command_print(CMD, "jaylink_set_target_power() failed: %s",
jaylink_strerror(ret));
return ERROR_FAIL;
}
@@ -1240,7 +1239,7 @@ static int poll_trace(uint8_t *buf, size_t *size)
ret = jaylink_swo_read(devh, buf, &length);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_swo_read() failed: %s.", jaylink_strerror(ret));
+ LOG_ERROR("jaylink_swo_read() failed: %s", jaylink_strerror(ret));
return ERROR_FAIL;
}
@@ -1260,7 +1259,7 @@ static uint32_t calculate_trace_buffer_size(void)
ret = jaylink_get_free_memory(devh, &tmp);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_get_free_memory() failed: %s.",
+ LOG_ERROR("jaylink_get_free_memory() failed: %s",
jaylink_strerror(ret));
return ERROR_FAIL;
}
@@ -1334,14 +1333,14 @@ static int config_trace(bool enabled, enum tpiu_pin_protocol pin_protocol,
if (!enabled)
return ERROR_OK;
- LOG_ERROR("Trace capturing is not supported by the device.");
+ LOG_ERROR("Trace capturing is not supported by the device");
return ERROR_FAIL;
}
ret = jaylink_swo_stop(devh);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_swo_stop() failed: %s.", jaylink_strerror(ret));
+ LOG_ERROR("jaylink_swo_stop() failed: %s", jaylink_strerror(ret));
return ERROR_FAIL;
}
@@ -1357,21 +1356,21 @@ static int config_trace(bool enabled, enum tpiu_pin_protocol pin_protocol,
}
if (pin_protocol != TPIU_PIN_PROTOCOL_ASYNC_UART) {
- LOG_ERROR("Selected pin protocol is not supported.");
+ LOG_ERROR("Selected pin protocol is not supported");
return ERROR_FAIL;
}
buffer_size = calculate_trace_buffer_size();
if (!buffer_size) {
- LOG_ERROR("Not enough free device memory to start trace capturing.");
+ LOG_ERROR("Not enough free device memory to start trace capturing");
return ERROR_FAIL;
}
ret = jaylink_swo_get_speeds(devh, JAYLINK_SWO_MODE_UART, &speed);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_swo_get_speeds() failed: %s.",
+ LOG_ERROR("jaylink_swo_get_speeds() failed: %s",
jaylink_strerror(ret));
return ERROR_FAIL;
}
@@ -1382,49 +1381,49 @@ static int config_trace(bool enabled, enum tpiu_pin_protocol pin_protocol,
max_freq = speed.freq / speed.min_div;
if (*trace_freq > max_freq) {
- LOG_INFO("Given SWO frequency too high, using %" PRIu32 " Hz instead.",
+ LOG_INFO("Given SWO frequency too high, using %" PRIu32 " Hz instead",
max_freq);
*trace_freq = max_freq;
} else if (*trace_freq < min_freq) {
- LOG_INFO("Given SWO frequency too low, using %" PRIu32 " Hz instead.",
+ LOG_INFO("Given SWO frequency too low, using %" PRIu32 " Hz instead",
min_freq);
*trace_freq = min_freq;
} else if (*trace_freq != speed.freq / divider) {
*trace_freq = speed.freq / divider;
LOG_INFO("Given SWO frequency is not supported by the device, "
- "using %u Hz instead.", *trace_freq);
+ "using %u Hz instead", *trace_freq);
}
if (!calculate_swo_prescaler(traceclkin_freq, *trace_freq,
prescaler)) {
LOG_ERROR("SWO frequency is not suitable. Please choose a "
- "different frequency or use auto-detection.");
+ "different frequency or use auto-detection");
return ERROR_FAIL;
}
} else {
- LOG_INFO("Trying to auto-detect SWO frequency.");
+ LOG_INFO("Trying to auto-detect SWO frequency");
if (!detect_swo_freq_and_prescaler(speed, traceclkin_freq, trace_freq,
prescaler)) {
LOG_ERROR("Maximum permitted frequency deviation of %.02f %% "
- "could not be achieved.", SWO_MAX_FREQ_DEV);
- LOG_ERROR("Auto-detection of SWO frequency failed.");
+ "could not be achieved", SWO_MAX_FREQ_DEV);
+ LOG_ERROR("Auto-detection of SWO frequency failed");
return ERROR_FAIL;
}
- LOG_INFO("Using SWO frequency of %u Hz.", *trace_freq);
+ LOG_INFO("Using SWO frequency of %u Hz", *trace_freq);
}
ret = jaylink_swo_start(devh, JAYLINK_SWO_MODE_UART, *trace_freq,
buffer_size);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_start_swo() failed: %s.", jaylink_strerror(ret));
+ LOG_ERROR("jaylink_start_swo() failed: %s", jaylink_strerror(ret));
return ERROR_FAIL;
}
- LOG_DEBUG("Using %" PRIu32 " bytes device memory for trace capturing.",
+ LOG_DEBUG("Using %" PRIu32 " bytes device memory for trace capturing",
buffer_size);
/*
@@ -1443,7 +1442,7 @@ COMMAND_HANDLER(jlink_handle_config_usb_address_command)
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_READ_CONFIG)) {
command_print(CMD, "Reading configuration is not supported by the "
- "device.");
+ "device");
return ERROR_OK;
}
@@ -1451,19 +1450,18 @@ COMMAND_HANDLER(jlink_handle_config_usb_address_command)
show_config_usb_address(CMD);
} else if (CMD_ARGC == 1) {
if (sscanf(CMD_ARGV[0], "%" SCNd8, &tmp) != 1) {
- command_print(CMD, "Invalid USB address: %s.", CMD_ARGV[0]);
+ command_print(CMD, "Invalid USB address: %s", CMD_ARGV[0]);
return ERROR_FAIL;
}
if (tmp > JAYLINK_USB_ADDRESS_3) {
- command_print(CMD, "Invalid USB address: %u.", tmp);
+ command_print(CMD, "Invalid USB address: %u", tmp);
return ERROR_FAIL;
}
tmp_config.usb_address = tmp;
} else {
- command_print(CMD, "Need exactly one argument for jlink config "
- "usb.");
+ command_print(CMD, "Need exactly one argument for jlink config usb");
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -1476,13 +1474,13 @@ COMMAND_HANDLER(jlink_handle_config_target_power_command)
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_READ_CONFIG)) {
command_print(CMD, "Reading configuration is not supported by the "
- "device.");
+ "device");
return ERROR_OK;
}
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_SET_TARGET_POWER)) {
command_print(CMD, "Target power supply is not supported by the "
- "device.");
+ "device");
return ERROR_OK;
}
@@ -1494,14 +1492,14 @@ COMMAND_HANDLER(jlink_handle_config_target_power_command)
} else if (!strcmp(CMD_ARGV[0], "off")) {
enable = false;
} else {
- command_print(CMD, "Invalid argument: %s.", CMD_ARGV[0]);
+ command_print(CMD, "Invalid argument: %s", CMD_ARGV[0]);
return ERROR_FAIL;
}
tmp_config.target_power = enable;
} else {
command_print(CMD, "Need exactly one argument for jlink config "
- "targetpower.");
+ "targetpower");
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -1517,13 +1515,13 @@ COMMAND_HANDLER(jlink_handle_config_mac_address_command)
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_READ_CONFIG)) {
command_print(CMD, "Reading configuration is not supported by the "
- "device.");
+ "device");
return ERROR_OK;
}
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_ETHERNET)) {
command_print(CMD, "Ethernet connectivity is not supported by the "
- "device.");
+ "device");
return ERROR_OK;
}
@@ -1534,7 +1532,7 @@ COMMAND_HANDLER(jlink_handle_config_mac_address_command)
if ((strlen(str) != 17) || (str[2] != ':' || str[5] != ':' ||
str[8] != ':' || str[11] != ':' || str[14] != ':')) {
- command_print(CMD, "Invalid MAC address format.");
+ command_print(CMD, "Invalid MAC address format");
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -1544,19 +1542,18 @@ COMMAND_HANDLER(jlink_handle_config_mac_address_command)
}
if (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) {
- command_print(CMD, "Invalid MAC address: zero address.");
+ command_print(CMD, "Invalid MAC address: zero address");
return ERROR_COMMAND_SYNTAX_ERROR;
}
if (!(0x01 & addr[0])) {
- command_print(CMD, "Invalid MAC address: multicast address.");
+ command_print(CMD, "Invalid MAC address: multicast address");
return ERROR_COMMAND_SYNTAX_ERROR;
}
memcpy(tmp_config.mac_address, addr, sizeof(addr));
} else {
- command_print(CMD, "Need exactly one argument for jlink config "
- " mac.");
+ command_print(CMD, "Need exactly one argument for jlink config mac");
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -1605,13 +1602,13 @@ COMMAND_HANDLER(jlink_handle_config_ip_address_command)
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_READ_CONFIG)) {
command_print(CMD, "Reading configuration is not supported by the "
- "device.");
+ "device");
return ERROR_OK;
}
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_ETHERNET)) {
command_print(CMD, "Ethernet connectivity is not supported by the "
- "device.");
+ "device");
return ERROR_OK;
}
@@ -1662,44 +1659,44 @@ COMMAND_HANDLER(jlink_handle_config_write_command)
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_READ_CONFIG)) {
command_print(CMD, "Reading configuration is not supported by the "
- "device.");
+ "device");
return ERROR_OK;
}
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_WRITE_CONFIG)) {
command_print(CMD, "Writing configuration is not supported by the "
- "device.");
+ "device");
return ERROR_OK;
}
if (!memcmp(&config, &tmp_config, sizeof(struct device_config))) {
command_print(CMD, "Operation not performed due to no changes in "
- "the configuration.");
+ "the configuration");
return ERROR_OK;
}
ret = jaylink_write_raw_config(devh, (const uint8_t *)&tmp_config);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_write_raw_config() failed: %s.",
+ LOG_ERROR("jaylink_write_raw_config() failed: %s",
jaylink_strerror(ret));
return ERROR_FAIL;
}
if (!read_device_config(&config)) {
- LOG_ERROR("Failed to read device configuration for verification.");
+ LOG_ERROR("Failed to read device configuration for verification");
return ERROR_FAIL;
}
if (memcmp(&config, &tmp_config, sizeof(struct device_config))) {
LOG_ERROR("Verification of device configuration failed. Please check "
- "your device.");
+ "your device");
return ERROR_FAIL;
}
memcpy(&tmp_config, &config, sizeof(struct device_config));
command_print(CMD, "The new device configuration applies after power "
- "cycling the J-Link device.");
+ "cycling the J-Link device");
return ERROR_OK;
}
@@ -1707,7 +1704,7 @@ COMMAND_HANDLER(jlink_handle_config_write_command)
COMMAND_HANDLER(jlink_handle_config_command)
{
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_READ_CONFIG)) {
- command_print(CMD, "Device doesn't support reading configuration.");
+ command_print(CMD, "Device doesn't support reading configuration");
return ERROR_OK;
}
@@ -1730,7 +1727,7 @@ COMMAND_HANDLER(jlink_handle_emucom_write_command)
return ERROR_COMMAND_SYNTAX_ERROR;
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_EMUCOM)) {
- LOG_ERROR("Device does not support EMUCOM.");
+ LOG_ERROR("Device does not support EMUCOM");
return ERROR_FAIL;
}
@@ -1739,21 +1736,21 @@ COMMAND_HANDLER(jlink_handle_emucom_write_command)
tmp = strlen(CMD_ARGV[1]);
if (tmp % 2 != 0) {
- LOG_ERROR("Data must be encoded as hexadecimal pairs.");
+ LOG_ERROR("Data must be encoded as hexadecimal pairs");
return ERROR_COMMAND_ARGUMENT_INVALID;
}
buf = malloc(tmp / 2);
if (!buf) {
- LOG_ERROR("Failed to allocate buffer.");
+ LOG_ERROR("Failed to allocate buffer");
return ERROR_FAIL;
}
dummy = unhexify(buf, CMD_ARGV[1], tmp / 2);
if (dummy != (tmp / 2)) {
- LOG_ERROR("Data must be encoded as hexadecimal pairs.");
+ LOG_ERROR("Data must be encoded as hexadecimal pairs");
free(buf);
return ERROR_COMMAND_ARGUMENT_INVALID;
}
@@ -1764,15 +1761,15 @@ COMMAND_HANDLER(jlink_handle_emucom_write_command)
free(buf);
if (ret == JAYLINK_ERR_DEV_NOT_SUPPORTED) {
- LOG_ERROR("Channel not supported by the device.");
+ LOG_ERROR("Channel not supported by the device");
return ERROR_FAIL;
} else if (ret != JAYLINK_OK) {
- LOG_ERROR("Failed to write to channel: %s.", jaylink_strerror(ret));
+ LOG_ERROR("Failed to write to channel: %s", jaylink_strerror(ret));
return ERROR_FAIL;
}
if (length != (tmp / 2))
- LOG_WARNING("Only %" PRIu32 " bytes written to the channel.", length);
+ LOG_WARNING("Only %" PRIu32 " bytes written to the channel", length);
return ERROR_OK;
}
@@ -1789,7 +1786,7 @@ COMMAND_HANDLER(jlink_handle_emucom_read_command)
return ERROR_COMMAND_SYNTAX_ERROR;
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_EMUCOM)) {
- LOG_ERROR("Device does not support EMUCOM.");
+ LOG_ERROR("Device does not support EMUCOM");
return ERROR_FAIL;
}
@@ -1799,23 +1796,23 @@ COMMAND_HANDLER(jlink_handle_emucom_read_command)
buf = malloc(length * 3 + 1);
if (!buf) {
- LOG_ERROR("Failed to allocate buffer.");
+ LOG_ERROR("Failed to allocate buffer");
return ERROR_FAIL;
}
ret = jaylink_emucom_read(devh, channel, buf, &length);
if (ret == JAYLINK_ERR_DEV_NOT_SUPPORTED) {
- LOG_ERROR("Channel is not supported by the device.");
+ LOG_ERROR("Channel is not supported by the device");
free(buf);
return ERROR_FAIL;
} else if (ret == JAYLINK_ERR_DEV_NOT_AVAILABLE) {
LOG_ERROR("Channel is not available for the requested amount of data. "
- "%" PRIu32 " bytes are available.", length);
+ "%" PRIu32 " bytes are available", length);
free(buf);
return ERROR_FAIL;
} else if (ret != JAYLINK_OK) {
- LOG_ERROR("Failed to read from channel: %s.", jaylink_strerror(ret));
+ LOG_ERROR("Failed to read from channel: %s", jaylink_strerror(ret));
free(buf);
return ERROR_FAIL;
}
@@ -1823,7 +1820,7 @@ COMMAND_HANDLER(jlink_handle_emucom_read_command)
tmp = hexify((char *)buf + length, buf, length, 2 * length + 1);
if (tmp != 2 * length) {
- LOG_ERROR("Failed to convert data into hexadecimal string.");
+ LOG_ERROR("Failed to convert data into hexadecimal string");
free(buf);
return ERROR_FAIL;
}
@@ -2081,7 +2078,7 @@ static int jlink_flush(void)
tap_length, jtag_command_version);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_jtag_io() failed: %s.", jaylink_strerror(ret));
+ LOG_ERROR("jaylink_jtag_io() failed: %s", jaylink_strerror(ret));
jlink_tap_init();
return ERROR_JTAG_QUEUE_FAILED;
}
@@ -2092,7 +2089,7 @@ static int jlink_flush(void)
buf_set_buf(tdo_buffer, p->first, p->buffer,
p->buffer_offset, p->length);
- LOG_DEBUG_IO("Pending scan result, length = %d.", p->length);
+ LOG_DEBUG_IO("Pending scan result, length = %d", p->length);
}
jlink_tap_init();
@@ -2157,7 +2154,7 @@ static int jlink_swd_switch_seq(enum swd_special_seq seq)
s_len = swd_seq_swd_to_jtag_len;
break;
default:
- LOG_ERROR("Sequence %d not supported.", seq);
+ LOG_ERROR("Sequence %d not supported", seq);
return ERROR_FAIL;
}
@@ -2171,10 +2168,10 @@ static int jlink_swd_run_queue(void)
int i;
int ret;
- LOG_DEBUG("Executing %d queued transactions.", pending_scan_results_length);
+ LOG_DEBUG("Executing %d queued transactions", pending_scan_results_length);
if (queued_retval != ERROR_OK) {
- LOG_DEBUG("Skipping due to previous errors: %d.", queued_retval);
+ LOG_DEBUG("Skipping due to previous errors: %d", queued_retval);
goto skip;
}
@@ -2187,7 +2184,7 @@ static int jlink_swd_run_queue(void)
ret = jaylink_swd_io(devh, tms_buffer, tdi_buffer, tdo_buffer, tap_length);
if (ret != JAYLINK_OK) {
- LOG_ERROR("jaylink_swd_io() failed: %s.", jaylink_strerror(ret));
+ LOG_ERROR("jaylink_swd_io() failed: %s", jaylink_strerror(ret));
goto skip;
}
@@ -2204,7 +2201,7 @@ static int jlink_swd_run_queue(void)
int parity = buf_get_u32(tdo_buffer, 3 + 32 + pending_scan_results_buffer[i].first, 1);
if (parity != parity_u32(data)) {
- LOG_ERROR("SWD: Read data parity mismatch.");
+ LOG_ERROR("SWD: Read data parity mismatch");
queued_retval = ERROR_FAIL;
goto skip;
}
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/jlink.c | 237 +++++++++++++++++++++++------------------------
1 file changed, 117 insertions(+), 120 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
