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From: OpenOCD-Gerrit <ope...@us...> - 2021-07-31 09:10:25
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via db16b3dc5b061c152f2478a5b9b7b3a3b0908911 (commit) via beff3de2ce7e275bf8c0051641dfc1acb0ecee9a (commit) via d94e1ffef0c352af1a291819907f398f060a462e (commit) from dbb10a57d128073cece9ccfc7edc7bb45b220406 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit db16b3dc5b061c152f2478a5b9b7b3a3b0908911 Author: Tim Newsome <ti...@si...> Date: Fri Jul 9 12:58:07 2021 -0700 Call poll at a fixed interval. The existing implementation blocks in select() for a fixed amount of time. This change tracks when the next event (likely poll()) wants to be run, and uses a shorter timeout in select() if necessary. Also track all these timeouts using milliseconds as returned by timeval_ms() instead of `struct timeval` to simplify the code. This feature is helpful if poll() wants to do something like sample PCs or memory values for basically the entire time that otherwise OpenOCD would be hung in select(). See https://github.com/riscv/riscv-openocd/pull/541 for an example of that. The RISC-V code using this change will be upstreamed some day, too. Signed-off-by: Tim Newsome <ti...@si...> Change-Id: I67104a7cf69ed07c8399c14aa55963fc5116a67d Reviewed-on: http://openocd.zylin.com/6363 Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/src/server/server.c b/src/server/server.c index 6f0b23caa..64acd3689 100644 --- a/src/server/server.c +++ b/src/server/server.c @@ -437,6 +437,8 @@ int server_loop(struct command_context *command_context) /* used in accept() */ int retval; + int64_t next_event = timeval_ms() + polling_period; + #ifndef _WIN32 if (signal(SIGPIPE, SIG_IGN) == SIG_ERR) LOG_ERROR("couldn't set SIGPIPE to SIG_IGN"); @@ -478,7 +480,12 @@ int server_loop(struct command_context *command_context) retval = socket_select(fd_max + 1, &read_fds, NULL, NULL, &tv); } else { /* Every 100ms, can be changed with "poll_period" command */ - tv.tv_usec = polling_period * 1000; + int timeout_ms = next_event - timeval_ms(); + if (timeout_ms < 0) + timeout_ms = 0; + else if (timeout_ms > polling_period) + timeout_ms = polling_period; + tv.tv_usec = timeout_ms * 1000; /* Only while we're sleeping we'll let others run */ openocd_sleep_prelude(); kept_alive(); @@ -511,7 +518,8 @@ int server_loop(struct command_context *command_context) if (retval == 0) { /* We only execute these callbacks when there was nothing to do or we timed *out */ - target_call_timer_callbacks(); + target_call_timer_callbacks_now(); + next_event = target_timer_next_event(); process_jim_events(command_context); FD_ZERO(&read_fds); /* eCos leaves read_fds unchanged in this case! */ diff --git a/src/target/target.c b/src/target/target.c index cf1873c5e..a67712009 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -154,9 +154,10 @@ static struct target_type *target_types[] = { struct target *all_targets; static struct target_event_callback *target_event_callbacks; static struct target_timer_callback *target_timer_callbacks; +static int64_t target_timer_next_event_value; static LIST_HEAD(target_reset_callback_list); static LIST_HEAD(target_trace_callback_list); -static const int polling_interval = 100; +static const int polling_interval = TARGET_DEFAULT_POLLING_INTERVAL; static const struct jim_nvp nvp_assert[] = { { .name = "assert", NVP_ASSERT }, @@ -1733,8 +1734,8 @@ int target_register_timer_callback(int (*callback)(void *priv), (*callbacks_p)->time_ms = time_ms; (*callbacks_p)->removed = false; - gettimeofday(&(*callbacks_p)->when, NULL); - timeval_add_time(&(*callbacks_p)->when, 0, time_ms * 1000); + (*callbacks_p)->when = timeval_ms() + time_ms; + target_timer_next_event_value = MIN(target_timer_next_event_value, (*callbacks_p)->when); (*callbacks_p)->priv = priv; (*callbacks_p)->next = NULL; @@ -1868,15 +1869,14 @@ int target_call_trace_callbacks(struct target *target, size_t len, uint8_t *data } static int target_timer_callback_periodic_restart( - struct target_timer_callback *cb, struct timeval *now) + struct target_timer_callback *cb, int64_t *now) { - cb->when = *now; - timeval_add_time(&cb->when, 0, cb->time_ms * 1000L); + cb->when = *now + cb->time_ms; return ERROR_OK; } static int target_call_timer_callback(struct target_timer_callback *cb, - struct timeval *now) + int64_t *now) { cb->callback(cb->priv); @@ -1898,8 +1898,12 @@ static int target_call_timer_callbacks_check_time(int checktime) keep_alive(); - struct timeval now; - gettimeofday(&now, NULL); + int64_t now = timeval_ms(); + + /* Initialize to a default value that's a ways into the future. + * The loop below will make it closer to now if there are + * callbacks that want to be called sooner. */ + target_timer_next_event_value = now + 1000; /* Store an address of the place containing a pointer to the * next item; initially, that's a standalone "root of the @@ -1915,11 +1919,14 @@ static int target_call_timer_callbacks_check_time(int checktime) bool call_it = (*callback)->callback && ((!checktime && (*callback)->type == TARGET_TIMER_TYPE_PERIODIC) || - timeval_compare(&now, &(*callback)->when) >= 0); + now >= (*callback)->when); if (call_it) target_call_timer_callback(*callback, &now); + if (!(*callback)->removed && (*callback)->when < target_timer_next_event_value) + target_timer_next_event_value = (*callback)->when; + callback = &(*callback)->next; } @@ -1927,17 +1934,22 @@ static int target_call_timer_callbacks_check_time(int checktime) return ERROR_OK; } -int target_call_timer_callbacks(void) +int target_call_timer_callbacks() { return target_call_timer_callbacks_check_time(1); } /* invoke periodic callbacks immediately */ -int target_call_timer_callbacks_now(void) +int target_call_timer_callbacks_now() { return target_call_timer_callbacks_check_time(0); } +int64_t target_timer_next_event(void) +{ + return target_timer_next_event_value; +} + /* Prints the working area layout for debug purposes */ static void print_wa_layout(struct target *target) { diff --git a/src/target/target.h b/src/target/target.h index 18a9516f5..1e19434e4 100644 --- a/src/target/target.h +++ b/src/target/target.h @@ -333,7 +333,7 @@ struct target_timer_callback { unsigned int time_ms; enum target_timer_type type; bool removed; - struct timeval when; + int64_t when; /* output of timeval_ms() */ void *priv; struct target_timer_callback *next; }; @@ -407,6 +407,11 @@ int target_call_timer_callbacks(void); * a synchronous command completes. */ int target_call_timer_callbacks_now(void); +/** + * Returns when the next registered event will take place. Callers can use this + * to go to sleep until that time occurs. + */ +int64_t target_timer_next_event(void); struct target *get_target_by_num(int num); struct target *get_current_target(struct command_context *cmd_ctx); @@ -790,4 +795,6 @@ int target_profiling_default(struct target *target, uint32_t *samples, uint32_t extern bool get_target_reset_nag(void); +#define TARGET_DEFAULT_POLLING_INTERVAL 100 + #endif /* OPENOCD_TARGET_TARGET_H */ commit beff3de2ce7e275bf8c0051641dfc1acb0ecee9a Author: PoroCYon <por...@ti...> Date: Wed Jul 21 04:17:08 2021 +0200 drivers/cmsis-dap: update for newest protocol version The capabilities INFO command can now return two bytes, without this patch, the capabilities would simply not be read and left as 0 (i.e. no capabilities). cf. https://arm-software.github.io/CMSIS_5/DAP/html/group__DAP__Info.html ; https://github.com/ARM-software/CMSIS_5/blob/116866fd74756c88096e37cbd0066fadad583cad/CMSIS/DAP/Firmware/Source/DAP.c#L100-L111 Change-Id: Ibd894971edf1c120cae08089e5515ce5e9972323 Signed-off-by: PoroCYon <por...@ti...> Reviewed-on: http://openocd.zylin.com/6373 Tested-by: jenkins Reviewed-by: Andrzej SierżÄga <as...@gm...> Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c index be8881d9b..06d5c6962 100644 --- a/src/jtag/drivers/cmsis_dap.c +++ b/src/jtag/drivers/cmsis_dap.c @@ -102,10 +102,16 @@ static bool swd_mode; #define INFO_ID_PKT_SZ 0xff /* short */ #define INFO_ID_SWO_BUF_SZ 0xfd /* word */ -#define INFO_CAPS_SWD BIT(0) -#define INFO_CAPS_JTAG BIT(1) -#define INFO_CAPS_SWO_UART BIT(2) -#define INFO_CAPS_SWO_MANCHESTER BIT(3) +#define INFO_CAPS_SWD BIT(0) +#define INFO_CAPS_JTAG BIT(1) +#define INFO_CAPS_SWO_UART BIT(2) +#define INFO_CAPS_SWO_MANCHESTER BIT(3) +#define INFO_CAPS_ATOMIC_CMDS BIT(4) +#define INFO_CAPS_TEST_DOMAIN_TIMER BIT(5) +#define INFO_CAPS_SWO_STREAMING_TRACE BIT(6) +#define INFO_CAPS_UART_PORT BIT(7) +#define INFO_CAPS_USB_COM_PORT BIT(8) +#define INFO_CAPS__NUM_CAPS 9 /* CMD_LED */ #define LED_ID_CONNECT 0x00 @@ -203,11 +209,16 @@ static bool swd_mode; /* CMSIS-DAP Vendor Commands * None as yet... */ -static const char * const info_caps_str[] = { - "SWD Supported", - "JTAG Supported", - "SWO-UART Supported", - "SWO-MANCHESTER Supported" +static const char * const info_caps_str[INFO_CAPS__NUM_CAPS] = { + "SWD supported", + "JTAG supported", + "SWO-UART supported", + "SWO-MANCHESTER supported", + "Atomic commands supported", + "Test domain timer supported", + "SWO streaming trace supported", + "UART communication port supported", + "UART via USB COM port supported", }; struct pending_transfer_result { @@ -1016,19 +1027,17 @@ static int cmsis_dap_get_caps_info(void) if (retval != ERROR_OK) return retval; - if (data[0] == 1) { - uint8_t caps = data[1]; + if (data[0] == 1 || data[0] == 2) { + uint16_t caps = data[1]; + if (data[0] == 2) + caps |= (uint16_t)data[2] << 8; cmsis_dap_handle->caps = caps; - if (caps & INFO_CAPS_SWD) - LOG_INFO("CMSIS-DAP: %s", info_caps_str[0]); - if (caps & INFO_CAPS_JTAG) - LOG_INFO("CMSIS-DAP: %s", info_caps_str[1]); - if (caps & INFO_CAPS_SWO_UART) - LOG_INFO("CMSIS-DAP: %s", info_caps_str[2]); - if (caps & INFO_CAPS_SWO_MANCHESTER) - LOG_INFO("CMSIS-DAP: %s", info_caps_str[3]); + for (int i = 0; i < INFO_CAPS__NUM_CAPS; ++i) { + if (caps & BIT(i)) + LOG_INFO("CMSIS-DAP: %s", info_caps_str[i]); + } } return ERROR_OK; diff --git a/src/jtag/drivers/cmsis_dap.h b/src/jtag/drivers/cmsis_dap.h index 634a62c8f..f6d9df21b 100644 --- a/src/jtag/drivers/cmsis_dap.h +++ b/src/jtag/drivers/cmsis_dap.h @@ -16,7 +16,7 @@ struct cmsis_dap { uint16_t packet_buffer_size; uint8_t *command; uint8_t *response; - uint8_t caps; + uint16_t caps; uint8_t mode; uint32_t swo_buf_sz; bool trace_enabled; commit d94e1ffef0c352af1a291819907f398f060a462e Author: Matthew Mets <ma...@bl...> Date: Thu Jul 22 01:25:15 2021 +0200 doc/openocd.texi: Add documentation for bcm2835 interface This adds documentation for the bcm2835 interface configuration parameters to the user manual. Documentation format is based on the FTDI interface section, and was taken from the descriptions in the driver source code. Change-Id: I77b09b8bd44d8e8fe9cc5fb9de3c3a30550d943c Signed-off-by: Matthew Mets <ma...@bl...> Reviewed-on: http://openocd.zylin.com/6376 Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/doc/openocd.texi b/doc/openocd.texi index 8f372a1a2..3aee034a4 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -3197,6 +3197,73 @@ configuration on exit. See @file{interface/raspberrypi-native.cfg} for a sample config and pinout. +@deffn {Config Command} {bcm2835gpio_jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo} +Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order). +Must be specified to enable JTAG transport. These pins can also be specified +individually. +@end deffn + +@deffn {Config Command} {bcm2835gpio_tck_num} @var{tck} +Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be +specified using the configuration command bcm2835gpio_jtag_nums. +@end deffn + +@deffn {Config Command} {bcm2835gpio_tms_num} @var{tms} +Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be +specified using the configuration command bcm2835gpio_jtag_nums. +@end deffn + +@deffn {Config Command} {bcm2835gpio_tdo_num} @var{tdo} +Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be +specified using the configuration command bcm2835gpio_jtag_nums. +@end deffn + +@deffn {Config Command} {bcm2835gpio_tdi_num} @var{tdi} +Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be +specified using the configuration command bcm2835gpio_jtag_nums. +@end deffn + +@deffn {Config Command} {bcm2835gpio_swd_nums} @var{swclk} @var{swdio} +Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be +specified to enable SWD transport. These pins can also be specified individually. +@end deffn + +@deffn {Config Command} {bcm2835gpio_swclk_num} @var{swclk} +Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be +specified using the configuration command bcm2835gpio_swd_nums. +@end deffn + +@deffn {Config Command} {bcm2835gpio_swdio_num} @var{swdio} +Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be +specified using the configuration command bcm2835gpio_swd_nums. +@end deffn + +@deffn {Config Command} {bcm2835gpio_swdio_dir_num} @var{swdio} @var{dir} +Set SWDIO direction control pin GPIO number. If specified, this pin can be used +to control the direction of an external buffer on the SWDIO pin (set=output +mode, clear=input mode). If not specified, this feature is disabled. +@end deffn + +@deffn {Config Command} {bcm2835gpio_srst_num} @var{srst} +Set SRST GPIO number. Must be specified to enable SRST. +@end deffn + +@deffn {Config Command} {bcm2835gpio_trst_num} @var{trst} +Set TRST GPIO number. Must be specified to enable TRST. +@end deffn + +@deffn {Config Command} {bcm2835gpio_speed_coeffs} @var{speed_coeff} @var{speed_offset} +Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified, +speed_coeff defaults to 113714, and speed_offset defaults to 28. +@end deffn + +@deffn {Config Command} {bcm2835gpio_peripheral_base} @var{base} +Set the peripheral base register address to access GPIOs. For the RPi1, use +0x20000000. For RPi2 and RPi3, use 0x3F000000. For RPi4, use 0xFE000000. A full +list can be found in the +@uref{https://www.raspberrypi.org/documentation/hardware/raspberrypi/peripheral_addresses.md, official guide}. +@end deffn + @end deffn @deffn {Interface Driver} {imx_gpio} ----------------------------------------------------------------------- Summary of changes: doc/openocd.texi | 67 ++++++++++++++++++++++++++++++++++++++++++++ src/jtag/drivers/cmsis_dap.c | 47 ++++++++++++++++++------------- src/jtag/drivers/cmsis_dap.h | 2 +- src/server/server.c | 12 ++++++-- src/target/target.c | 36 ++++++++++++++++-------- src/target/target.h | 9 +++++- 6 files changed, 138 insertions(+), 35 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-31 09:09:09
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via dbb10a57d128073cece9ccfc7edc7bb45b220406 (commit) via 44d7cc31dac89d270541bca1c6b7e34d803cbaaf (commit) from c8f92ee73b7c1d2bb67bb7f8653a8ea1be873665 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit dbb10a57d128073cece9ccfc7edc7bb45b220406 Author: Matthew Mets <ma...@bl...> Date: Tue Jul 20 01:48:47 2021 +0200 interface/jtag_hat: Add interface configuration for the JTAG HAT This adds support for the Blinkinlabs JTAG Hat, a Raspberry Pi expansion board that provides JTAG and SWD connections via level- shifting buffers. Change-Id: I228bf6a18890b7c3d6679bbc63bfe39f726d8323 Signed-off-by: Matthew Mets <ma...@bl...> Reviewed-on: http://openocd.zylin.com/6372 Reviewed-by: Antonio Borneo <bor...@gm...> Tested-by: jenkins diff --git a/tcl/interface/jtag_hat_rpi2.cfg b/tcl/interface/jtag_hat_rpi2.cfg new file mode 100644 index 000000000..495ff0f04 --- /dev/null +++ b/tcl/interface/jtag_hat_rpi2.cfg @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Blinkinlabs JTAG_Hat +# +# https://github.com/blinkinlabs/jtag_hat +# + +adapter driver bcm2835gpio + +bcm2835gpio_peripheral_base 0x3F000000 + +# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET +# These depend on system clock, calibrated for stock 700MHz +# bcm2835gpio_speed SPEED_COEFF SPEED_OFFSET +bcm2835gpio_speed_coeffs 146203 36 + +# Each of the JTAG lines need a gpio number set: tck tms tdi tdo +# Header pin numbers: 23 22 19 21 +bcm2835gpio_jtag_nums 11 25 10 9 + +# Each of the SWD lines need a gpio number set: swclk swdio +# Header pin numbers: 23 22 +bcm2835gpio_swd_nums 11 25 + +# Direction pin for SWDIO level shifting buffer +bcm2835gpio_swdio_dir_num 6 + +# If you define trst or srst, use appropriate reset_config +# Header pin numbers: TRST - 26, SRST - 18 + +bcm2835gpio_trst_num 7 +#reset_config trst_only + +bcm2835gpio_srst_num 24 +#reset_config srst_only + +# or if you have both connected +#reset_config trst_and_srst commit 44d7cc31dac89d270541bca1c6b7e34d803cbaaf Author: Matthew Mets <ma...@bl...> Date: Tue Jul 20 01:28:05 2021 +0200 drivers/bcm2835: Add support for SWDIO direction control pin Adds a new, optional configuration "bcm2835gpio_swdio_dir_num" to the BCM2835 driver, to control the direction of an external buffer driver IC in SWD mode. For example, this is needed to use a level- shifting buffer, such as the SN74LVC2T45 used on the JTAG Hat Change-Id: If5c146f310ecf8ceae85443b3670936467d2786d Signed-off-by: Matthew Mets <ma...@bl...> Reviewed-on: http://openocd.zylin.com/6371 Reviewed-by: Antonio Borneo <bor...@gm...> Tested-by: jenkins diff --git a/src/jtag/drivers/bcm2835gpio.c b/src/jtag/drivers/bcm2835gpio.c index 40cb5aa0b..6db4340e8 100644 --- a/src/jtag/drivers/bcm2835gpio.c +++ b/src/jtag/drivers/bcm2835gpio.c @@ -86,6 +86,8 @@ static int swclk_gpio = -1; static int swclk_gpio_mode; static int swdio_gpio = -1; static int swdio_gpio_mode; +static int swdio_dir_gpio = -1; +static int swdio_dir_gpio_mode; /* Transition delay coefficients */ static int speed_coeff = 113714; @@ -149,10 +151,20 @@ static int bcm2835gpio_reset(int trst, int srst) static void bcm2835_swdio_drive(bool is_output) { - if (is_output) - OUT_GPIO(swdio_gpio); - else - INP_GPIO(swdio_gpio); + if (swdio_dir_gpio > 0) { + if (is_output) { + GPIO_SET = 1 << swdio_dir_gpio; + OUT_GPIO(swdio_gpio); + } else { + INP_GPIO(swdio_gpio); + GPIO_CLR = 1 << swdio_dir_gpio; + } + } else { + if (is_output) + OUT_GPIO(swdio_gpio); + else + INP_GPIO(swdio_gpio); + } } static int bcm2835_swdio_read(void) @@ -295,6 +307,15 @@ COMMAND_HANDLER(bcm2835gpio_handle_swd_gpionum_swdio) return ERROR_OK; } +COMMAND_HANDLER(bcm2835gpio_handle_swd_dir_gpionum_swdio) +{ + if (CMD_ARGC == 1) + COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swdio_dir_gpio); + + command_print(CMD, "BCM2835 num: swdio_dir = %d", swdio_dir_gpio); + return ERROR_OK; +} + COMMAND_HANDLER(bcm2835gpio_handle_speed_coeffs) { if (CMD_ARGC == 2) { @@ -374,6 +395,13 @@ static const struct command_registration bcm2835gpio_command_handlers[] = { .help = "gpio number for swdio.", .usage = "[swdio]", }, + { + .name = "bcm2835gpio_swdio_dir_num", + .handler = &bcm2835gpio_handle_swd_dir_gpionum_swdio, + .mode = COMMAND_CONFIG, + .help = "gpio number for swdio direction control pin (set=output mode, clear=input mode)", + .usage = "[swdio_dir]", + }, { .name = "bcm2835gpio_srst_num", .handler = &bcm2835gpio_handle_jtag_gpionum_srst, @@ -541,6 +569,12 @@ static int bcm2835gpio_init(void) OUT_GPIO(srst_gpio); } + if (swdio_dir_gpio != -1) { + swdio_dir_gpio_mode = MODE_GPIO(swdio_dir_gpio); + GPIO_SET = 1 << swdio_dir_gpio; + OUT_GPIO(swdio_dir_gpio); + } + LOG_DEBUG("saved pinmux settings: tck %d tms %d tdi %d " "tdo %d trst %d srst %d", tck_gpio_mode, tms_gpio_mode, tdi_gpio_mode, tdo_gpio_mode, trst_gpio_mode, srst_gpio_mode); @@ -567,5 +601,8 @@ static int bcm2835gpio_quit(void) if (srst_gpio != -1) SET_MODE_GPIO(srst_gpio, srst_gpio_mode); + if (swdio_dir_gpio != -1) + SET_MODE_GPIO(swdio_dir_gpio, swdio_dir_gpio_mode); + return ERROR_OK; } ----------------------------------------------------------------------- Summary of changes: src/jtag/drivers/bcm2835gpio.c | 45 ++++++++++++++++++++-- .../{raspberrypi2-native.cfg => jtag_hat_rpi2.cfg} | 24 ++++++------ 2 files changed, 53 insertions(+), 16 deletions(-) copy tcl/interface/{raspberrypi2-native.cfg => jtag_hat_rpi2.cfg} (56%) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-31 09:07:49
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via c8f92ee73b7c1d2bb67bb7f8653a8ea1be873665 (commit) from d9f99f6e26e6809b617d9ba36530ad4c32e912e1 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit c8f92ee73b7c1d2bb67bb7f8653a8ea1be873665 Author: Antonio Borneo <bor...@gm...> Date: Sat Jul 24 12:37:09 2021 +0200 jtag/aice: fix build with clang on MacOS Commit fceb29d03ff9 ("jtag/aice: use macros in place of const variables") replaces some 'static const uint8_t' with macros. This breaks the build on MacOS because the macro values are of 'int' type that doesn't match with the printf format 'PRIx8'. error: format specifies type 'unsigned char' but the argument has type 'int' [-Werror,-Wformat] Replace the printf format 'PRIx8' with 'x'. While there, remove a useless cast to uint32_t and fix the printf format too. Change-Id: Ib87298a61637b75a2813f209e5209d39ab2745f8 Signed-off-by: Antonio Borneo <bor...@gm...> Fixes: fceb29d03ff9 ("jtag/aice: use macros in place of const variables") Reviewed-on: http://openocd.zylin.com/6380 Tested-by: jenkins diff --git a/src/jtag/aice/aice_usb.c b/src/jtag/aice/aice_usb.c index 8a8b83088..a943bb8b0 100644 --- a/src/jtag/aice/aice_usb.c +++ b/src/jtag/aice/aice_usb.c @@ -583,7 +583,7 @@ static int aice_scan_chain(uint32_t *id_codes, uint8_t *num_of_ids) if (cmd_ack_code != AICE_CMD_SCAN_CHAIN) { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_SCAN_CHAIN, cmd_ack_code); return ERROR_FAIL; } @@ -638,8 +638,8 @@ int aice_read_ctrl(uint32_t address, uint32_t *data) LOG_DEBUG("READ_CTRL response, data: 0x%" PRIx32, *data); if (cmd_ack_code != AICE_CMD_READ_CTRL) { - LOG_ERROR("aice command error (command=0x%" PRIx32 ", response=0x%" PRIx8 ")", - (uint32_t)AICE_CMD_READ_CTRL, cmd_ack_code); + LOG_ERROR("aice command error (command=0x%x, response=0x%" PRIx8 ")", + AICE_CMD_READ_CTRL, cmd_ack_code); return ERROR_FAIL; } @@ -676,7 +676,7 @@ int aice_write_ctrl(uint32_t address, uint32_t data) LOG_DEBUG("WRITE_CTRL response"); if (cmd_ack_code != AICE_CMD_WRITE_CTRL) { - LOG_ERROR("aice command error (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command error (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_WRITE_CTRL, cmd_ack_code); return ERROR_FAIL; } @@ -718,7 +718,7 @@ static int aice_read_dtr(uint8_t target_id, uint32_t *data) } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_T_READ_DTR, cmd_ack_code); return ERROR_FAIL; } @@ -768,7 +768,7 @@ static int aice_read_dtr_to_buffer(uint8_t target_id, uint32_t buffer_idx) break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_READ_DTR_TO_BUFFER, cmd_ack_code); return ERROR_FAIL; @@ -820,7 +820,7 @@ static int aice_write_dtr(uint8_t target_id, uint32_t data) break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_T_WRITE_DTR, cmd_ack_code); return ERROR_FAIL; @@ -871,7 +871,7 @@ static int aice_write_dtr_from_buffer(uint8_t target_id, uint32_t buffer_idx) break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_WRITE_DTR_FROM_BUFFER, cmd_ack_code); return ERROR_FAIL; @@ -921,7 +921,7 @@ static int aice_read_misc(uint8_t target_id, uint32_t address, uint32_t *data) break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_T_READ_MISC, cmd_ack_code); return ERROR_FAIL; } @@ -976,7 +976,7 @@ static int aice_write_misc(uint8_t target_id, uint32_t address, uint32_t data) break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_T_WRITE_MISC, cmd_ack_code); return ERROR_FAIL; @@ -1026,7 +1026,7 @@ static int aice_read_edmsr(uint8_t target_id, uint32_t address, uint32_t *data) break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_T_READ_EDMSR, cmd_ack_code); return ERROR_FAIL; @@ -1082,7 +1082,7 @@ static int aice_write_edmsr(uint8_t target_id, uint32_t address, uint32_t data) break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_T_WRITE_EDMSR, cmd_ack_code); return ERROR_FAIL; @@ -1165,8 +1165,7 @@ static int aice_write_dim(uint8_t target_id, uint32_t *word, uint8_t num_of_word break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 - ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_T_WRITE_DIM, cmd_ack_code); return ERROR_FAIL; @@ -1220,7 +1219,7 @@ static int aice_do_execute(uint8_t target_id) break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_T_EXECUTE, cmd_ack_code); return ERROR_FAIL; @@ -1273,7 +1272,7 @@ static int aice_write_mem_b(uint8_t target_id, uint32_t address, uint32_t data) break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_T_WRITE_MEM_B, cmd_ack_code); return ERROR_FAIL; @@ -1328,7 +1327,7 @@ static int aice_write_mem_h(uint8_t target_id, uint32_t address, uint32_t data) break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_T_WRITE_MEM_H, cmd_ack_code); return ERROR_FAIL; @@ -1383,7 +1382,7 @@ static int aice_write_mem(uint8_t target_id, uint32_t address, uint32_t data) break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_T_WRITE_MEM, cmd_ack_code); return ERROR_FAIL; @@ -1434,7 +1433,7 @@ static int aice_fastread_mem(uint8_t target_id, uint8_t *word, uint32_t num_of_w break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_T_FASTREAD_MEM, cmd_ack_code); return ERROR_FAIL; @@ -1490,7 +1489,7 @@ static int aice_fastwrite_mem(uint8_t target_id, const uint8_t *word, uint32_t n break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_T_FASTWRITE_MEM, cmd_ack_code); return ERROR_FAIL; @@ -1540,7 +1539,7 @@ static int aice_read_mem_b(uint8_t target_id, uint32_t address, uint32_t *data) break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_T_READ_MEM_B, cmd_ack_code); return ERROR_FAIL; @@ -1590,7 +1589,7 @@ static int aice_read_mem_h(uint8_t target_id, uint32_t address, uint32_t *data) break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_T_READ_MEM_H, cmd_ack_code); return ERROR_FAIL; @@ -1641,7 +1640,7 @@ static int aice_read_mem(uint8_t target_id, uint32_t address, uint32_t *data) break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_T_READ_MEM, cmd_ack_code); return ERROR_FAIL; @@ -1686,7 +1685,7 @@ static int aice_batch_buffer_read(uint8_t buf_index, uint32_t *word, uint32_t nu break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_BATCH_BUFFER_READ, cmd_ack_code); return ERROR_FAIL; @@ -1738,7 +1737,7 @@ int aice_batch_buffer_write(uint8_t buf_index, const uint8_t *word, uint32_t num break; } else { if (retry_times > aice_max_retry_times) { - LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")", + LOG_ERROR("aice command timeout (command=0x%x, response=0x%" PRIx8 ")", AICE_CMD_BATCH_BUFFER_WRITE, cmd_ack_code); return ERROR_FAIL; ----------------------------------------------------------------------- Summary of changes: src/jtag/aice/aice_usb.c | 49 ++++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 25 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-30 11:17:10
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via d9f99f6e26e6809b617d9ba36530ad4c32e912e1 (commit) from ae6de2f93d960c7d35e8d4c86d9c17dda17c561e (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit d9f99f6e26e6809b617d9ba36530ad4c32e912e1 Author: Paul Fertser <fer...@gm...> Date: Sun Jun 6 12:09:37 2021 +0300 doc: move the official channel to Libera.Chat Due to Freenode takeover it's likely that most of our users are going to seek support on Libera in the nearest future. Change-Id: I98db95bab51f4ef2ac854bf521468d22b2794e56 Signed-off-by: Paul Fertser <fer...@gm...> Reviewed-on: http://openocd.zylin.com/6297 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tar...@gm...> Reviewed-by: Antonio Borneo <bor...@gm...> Reviewed-by: Marc Schink <de...@za...> diff --git a/doc/openocd.texi b/doc/openocd.texi index b49550511..8f372a1a2 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -202,7 +202,7 @@ communication between users: @section OpenOCD IRC Support can also be found on irc: -@uref{irc://irc.freenode.net/openocd} +@uref{irc://irc.libera.chat/openocd} @node Developers @chapter OpenOCD Developer Resources ----------------------------------------------------------------------- Summary of changes: doc/openocd.texi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-24 09:40:17
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via ae6de2f93d960c7d35e8d4c86d9c17dda17c561e (commit) via e2ef1c9090ad01e78aa537418ca3f543e4c1282b (commit) from c0c7d6fe8b04f521a7262303083ef5eb6ebaf4e5 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit ae6de2f93d960c7d35e8d4c86d9c17dda17c561e Author: Florian Fainelli <f.f...@gm...> Date: Tue Jul 6 11:21:54 2021 -0700 arm_adi_v5: Added Cortex-A76 identifiers Add identifiers of the Cortex-A76 ROM and debug unit. Change-Id: Ieef0d990189d3c0502e8d530874dc9cbca4417d8 Signed-off-by: Florian Fainelli <f.f...@gm...> Reviewed-on: http://openocd.zylin.com/6358 Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 16fe69a8d..c421fe6a3 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -1138,6 +1138,7 @@ static const struct { { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", }, { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", }, { ARM_ID, 0x4e0, "Cortex-A35 ROM", "(v7 Memory Map ROM Table)", }, + { ARM_ID, 0x4e4, "Cortex-A76 ROM", "(ROM Table)", }, { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", }, { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", }, { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", }, @@ -1194,6 +1195,7 @@ static const struct { { ARM_ID, 0xd04, "Cortex-A35 Debug", "(Debug Unit)", }, { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", }, { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", }, + { ARM_ID, 0xd0b, "Cortex-A76 Debug", "(Debug Unit)", }, { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" }, { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" }, { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" }, commit e2ef1c9090ad01e78aa537418ca3f543e4c1282b Author: Florian Fainelli <f.f...@gm...> Date: Fri Jul 9 11:04:27 2021 -0700 arm_adi_v5: Provide Brahma-B53 identifiers The Broadcom Brahma-B53 CPUs contains a number of custom ROM table entries for its PMU, Debug unit, and a couple of ROM tables. Change-Id: I1f21f07ed296579c374f24e781325789bf4ebf51 Signed-off-by: Florian Fainelli <f.f...@gm...> Reviewed-on: http://openocd.zylin.com/6368 Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index dc6f63d46..16fe69a8d 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -1201,6 +1201,10 @@ static const struct { { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" }, { 0x0E5, 0x000, "SHARC+/Blackfin+", "", }, { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", }, + { 0x1bf, 0x100, "Brahma-B53 Debug", "(Debug Unit)", }, + { 0x1bf, 0x9d3, "Brahma-B53 PMU", "(Performance Monitor Unit)", }, + { 0x1bf, 0x4a1, "Brahma-B53 ROM", "(ROM Table)", }, + { 0x1bf, 0x721, "Brahma-B53 ROM", "(ROM Table)", }, { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", }, { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", }, { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", }, ----------------------------------------------------------------------- Summary of changes: src/target/arm_adi_v5.c | 6 ++++++ 1 file changed, 6 insertions(+) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-24 09:39:40
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via c0c7d6fe8b04f521a7262303083ef5eb6ebaf4e5 (commit) via 54e699b2601036e384a124657aa1fbdd9ff2dc87 (commit) via 0a1f904707fa3c170032dd9dba8f2ef9207ff9b2 (commit) via 391782318723915bd259eadf9469251c13c8fa9c (commit) via 08ee7bb982b16742f52cfdc6c649d82ffa2eb177 (commit) from b159f5cdedd70fff9309722e927be670845f4df5 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit c0c7d6fe8b04f521a7262303083ef5eb6ebaf4e5 Author: Antonio Borneo <bor...@gm...> Date: Sat Jul 3 17:18:53 2021 +0200 openocd: fix Yoda conditions with checkpatch The new checkpatch can automatically fix the code, but this feature is still error prone and not complete. Patch generated automatically through the new checkpatch with flags "--types CONSTANT_COMPARISON --fix-inplace". Some Yoda condition is detected by checkpatch but not fixed; it will be fixed manually in a following commit. Change-Id: Ifaaa1159e63dbd1db6aa3c017125df9874fa9703 Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6355 Tested-by: jenkins diff --git a/src/flash/nand/fileio.c b/src/flash/nand/fileio.c index 49db112e2..b9c7f79f7 100644 --- a/src/flash/nand/fileio.c +++ b/src/flash/nand/fileio.c @@ -119,7 +119,7 @@ COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state, nand_fileio_init(state); unsigned minargs = need_size ? 4 : 3; - if (CMD_ARGC < minargs) + if (minargs > CMD_ARGC) return ERROR_COMMAND_SYNTAX_ERROR; struct nand_device *nand; @@ -141,7 +141,7 @@ COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state, } } - if (CMD_ARGC > minargs) { + if (minargs < CMD_ARGC) { for (unsigned i = minargs; i < CMD_ARGC; i++) { if (!strcmp(CMD_ARGV[i], "oob_raw")) state->oob_format |= NAND_OOB_RAW; diff --git a/src/flash/nor/avrf.c b/src/flash/nor/avrf.c index 4fa4e0d45..a5a2cbd5b 100644 --- a/src/flash/nor/avrf.c +++ b/src/flash/nor/avrf.c @@ -134,7 +134,7 @@ static int avr_jtagprg_chiperase(struct avr_common *avr) &poll_value, 0x3380, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN); - if (ERROR_OK != mcu_execute_queue()) + if (mcu_execute_queue() != ERROR_OK) return ERROR_FAIL; LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value); } while (!(poll_value & 0x0200)); @@ -195,7 +195,7 @@ static int avr_jtagprg_writeflashpage(struct avr_common *avr, &poll_value, 0x3700, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN); - if (ERROR_OK != mcu_execute_queue()) + if (mcu_execute_queue() != ERROR_OK) return ERROR_FAIL; LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value); } while (!(poll_value & 0x0200)); @@ -266,7 +266,7 @@ static int avrf_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t o LOG_DEBUG("offset is 0x%08" PRIx32 "", offset); LOG_DEBUG("count is %" PRIu32 "", count); - if (ERROR_OK != avr_jtagprg_enterprogmode(avr)) + if (avr_jtagprg_enterprogmode(avr) != ERROR_OK) return ERROR_FAIL; if (bank->size > 0x20000) @@ -315,7 +315,7 @@ static int avrf_probe(struct flash_bank *bank) avrf_info->probed = false; avr_jtag_read_jtagid(avr, &device_id); - if (ERROR_OK != mcu_execute_queue()) + if (mcu_execute_queue() != ERROR_OK) return ERROR_FAIL; LOG_INFO("device id = 0x%08" PRIx32 "", device_id); @@ -380,7 +380,7 @@ static int avrf_info(struct flash_bank *bank, struct command_invocation *cmd) } avr_jtag_read_jtagid(avr, &device_id); - if (ERROR_OK != mcu_execute_queue()) + if (mcu_execute_queue() != ERROR_OK) return ERROR_FAIL; LOG_INFO("device id = 0x%08" PRIx32 "", device_id); @@ -420,9 +420,9 @@ static int avrf_mass_erase(struct flash_bank *bank) return ERROR_TARGET_NOT_HALTED; } - if ((ERROR_OK != avr_jtagprg_enterprogmode(avr)) - || (ERROR_OK != avr_jtagprg_chiperase(avr)) - || (ERROR_OK != avr_jtagprg_leaveprogmode(avr))) + if ((avr_jtagprg_enterprogmode(avr) != ERROR_OK) + || (avr_jtagprg_chiperase(avr) != ERROR_OK) + || (avr_jtagprg_leaveprogmode(avr) != ERROR_OK)) return ERROR_FAIL; return ERROR_OK; diff --git a/src/flash/nor/cc26xx.c b/src/flash/nor/cc26xx.c index 0895798d3..f6b563279 100644 --- a/src/flash/nor/cc26xx.c +++ b/src/flash/nor/cc26xx.c @@ -148,7 +148,7 @@ static int cc26xx_init(struct flash_bank *bank) return retval; /* Confirm the defined working address is the area we need to use */ - if (CC26XX_ALGO_BASE_ADDRESS != cc26xx_bank->working_area->address) + if (cc26xx_bank->working_area->address != CC26XX_ALGO_BASE_ADDRESS) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; /* Write flash helper algorithm into target memory */ @@ -211,7 +211,7 @@ static int cc26xx_mass_erase(struct flash_bank *bank) int retval; - if (TARGET_HALTED != target->state) { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -275,7 +275,7 @@ static int cc26xx_erase(struct flash_bank *bank, unsigned int first, uint32_t length; int retval; - if (TARGET_HALTED != target->state) { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -327,7 +327,7 @@ static int cc26xx_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t index; int retval; - if (TARGET_HALTED != target->state) { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } diff --git a/src/flash/nor/cc3220sf.c b/src/flash/nor/cc3220sf.c index 522b21a8c..b29653841 100644 --- a/src/flash/nor/cc3220sf.c +++ b/src/flash/nor/cc3220sf.c @@ -42,7 +42,7 @@ static int cc3220sf_mass_erase(struct flash_bank *bank) int retval = ERROR_OK; - if (TARGET_HALTED != target->state) { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -118,7 +118,7 @@ static int cc3220sf_erase(struct flash_bank *bank, unsigned int first, int retval = ERROR_OK; - if (TARGET_HALTED != target->state) { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -192,7 +192,7 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, int retval = ERROR_OK; - if (TARGET_HALTED != target->state) { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -295,7 +295,7 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, /* Check that the head value was written to flash */ result = buf_get_u32(reg_params[2].value, 0, 32); - if (0 != result) { + if (result != 0) { retval = ERROR_FAIL; LOG_ERROR("cc3220sf: Flash operation failed"); } @@ -359,7 +359,7 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, /* Check that all words were written to flash */ result = buf_get_u32(reg_params[2].value, 0, 32); - if (0 != result) { + if (result != 0) { retval = ERROR_FAIL; LOG_ERROR("cc3220sf: Flash operation failed"); break; @@ -369,7 +369,7 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, } /* Do one word write for any final bytes less than a full word */ - if ((retval == ERROR_OK) && (0 != tail_count)) { + if ((retval == ERROR_OK) && (tail_count != 0)) { uint8_t tail[4]; /* Set starting byte offset for data to write */ @@ -409,7 +409,7 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, /* Check that the tail was written to flash */ result = buf_get_u32(reg_params[2].value, 0, 32); - if (0 != result) { + if (result != 0) { retval = ERROR_FAIL; LOG_ERROR("cc3220sf: Flash operation failed"); } diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c index c8ce90866..ab0186d7d 100644 --- a/src/flash/nor/efm32.c +++ b/src/flash/nor/efm32.c @@ -386,7 +386,7 @@ static int efm32x_wait_status(struct flash_bank *bank, int timeout, LOG_DEBUG("status: 0x%" PRIx32 "", status); - if (((status & wait_mask) == 0) && (0 == wait_for_set)) + if (((status & wait_mask) == 0) && (wait_for_set == 0)) break; else if (((status & wait_mask) != 0) && wait_for_set) break; @@ -457,7 +457,7 @@ static int efm32x_erase(struct flash_bank *bank, unsigned int first, struct target *target = bank->target; int ret = 0; - if (TARGET_HALTED != target->state) { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -958,7 +958,7 @@ static int efm32x_probe(struct flash_bank *bank) LOG_INFO("flash size = %dkbytes", efm32_mcu_info.flash_sz_kib); LOG_INFO("flash page size = %dbytes", efm32_mcu_info.page_size); - assert(0 != efm32_mcu_info.page_size); + assert(efm32_mcu_info.page_size != 0); int num_pages = efm32_mcu_info.flash_sz_kib * 1024 / efm32_mcu_info.page_size; diff --git a/src/flash/nor/fespi.c b/src/flash/nor/fespi.c index 99ec67d30..150e91a1c 100644 --- a/src/flash/nor/fespi.c +++ b/src/flash/nor/fespi.c @@ -538,7 +538,7 @@ static unsigned as_compile(struct algorithm_steps *as, uint8_t *target, break; } case STEP_WRITE_REG: - if (4 > bytes_left) { + if (bytes_left < 4) { finish_early = true; break; } @@ -546,7 +546,7 @@ static unsigned as_compile(struct algorithm_steps *as, uint8_t *target, offset += 3; break; case STEP_SET_DIR: - if (3 > bytes_left) { + if (bytes_left < 3) { finish_early = true; break; } @@ -555,7 +555,7 @@ static unsigned as_compile(struct algorithm_steps *as, uint8_t *target, break; case STEP_TXWM_WAIT: case STEP_WIP_WAIT: - if (2 > bytes_left) { + if (bytes_left < 2) { finish_early = true; break; } diff --git a/src/flash/nor/msp432.c b/src/flash/nor/msp432.c index 23d4982f4..667349f28 100644 --- a/src/flash/nor/msp432.c +++ b/src/flash/nor/msp432.c @@ -209,7 +209,7 @@ static int msp432_wait_return_code(struct target *target) int retval = ERROR_OK; start_ms = timeval_ms(); - while ((0 == return_code) || (return_code == FLASH_BUSY)) { + while ((return_code == 0) || (return_code == FLASH_BUSY)) { retval = target_read_u32(target, ALGO_RETURN_CODE_ADDR, &return_code); if (retval != ERROR_OK) return retval; @@ -322,11 +322,11 @@ static int msp432_init(struct flash_bank *bank) "msp432: Unrecognized MSP432P4 Device ID and Hardware " "Rev (%04" PRIX32 ", %02" PRIX32 ")", msp432_bank->device_id, msp432_bank->hardware_rev); - } else if (MSP432P401X_DEPR == msp432_bank->device_type) { + } else if (msp432_bank->device_type == MSP432P401X_DEPR) { LOG_WARNING( "msp432: MSP432P401x pre-production device (deprecated " "silicon)\n" SUPPORT_MESSAGE); - } else if (MSP432E4X_GUESS == msp432_bank->device_type) { + } else if (msp432_bank->device_type == MSP432E4X_GUESS) { /* Explicit device type check failed. Report this. */ LOG_WARNING( "msp432: Unrecognized MSP432E4 DID0 and DID1 values " @@ -343,7 +343,7 @@ static int msp432_init(struct flash_bank *bank) return retval; /* Confirm the defined working address is the area we need to use */ - if (ALGO_BASE_ADDR != msp432_bank->working_area->address) + if (msp432_bank->working_area->address != ALGO_BASE_ADDR) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; /* Write flash helper algorithm into target memory */ @@ -432,7 +432,7 @@ static int msp432_mass_erase(struct flash_bank *bank, bool all) int retval; - if (TARGET_HALTED != target->state) { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -501,7 +501,7 @@ COMMAND_HANDLER(msp432_mass_erase_command) msp432_bank = bank->driver_priv; - if (MSP432E4 == msp432_bank->family_type) { + if (msp432_bank->family_type == MSP432E4) { /* MSP432E4 does not have main vs info regions, ignore "all" */ all = false; } @@ -510,7 +510,7 @@ COMMAND_HANDLER(msp432_mass_erase_command) if (retval != ERROR_OK) return retval; - if (MSP432E4 == msp432_bank->family_type) { + if (msp432_bank->family_type == MSP432E4) { /* MSP432E4 does not have main vs info regions */ LOG_INFO("msp432: Mass erase of flash is complete"); } else { @@ -537,7 +537,7 @@ COMMAND_HANDLER(msp432_bsl_command) msp432_bank = bank->driver_priv; - if (MSP432E4 == msp432_bank->family_type) { + if (msp432_bank->family_type == MSP432E4) { LOG_WARNING("msp432: MSP432E4 does not have a BSL region"); return ERROR_OK; } @@ -602,7 +602,7 @@ static int msp432_erase(struct flash_bank *bank, unsigned int first, int retval; - if (TARGET_HALTED != target->state) { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -680,7 +680,7 @@ static int msp432_write(struct flash_bank *bank, const uint8_t *buffer, int retval; - if (TARGET_HALTED != target->state) { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -829,7 +829,7 @@ static int msp432_probe(struct flash_bank *bank) if (retval != ERROR_OK) return retval; - if (0 == size) { + if (size == 0) { /* This is likely an MSP432E4 */ msp432_bank->family_type = MSP432E4; @@ -864,7 +864,7 @@ static int msp432_probe(struct flash_bank *bank) msp432_bank->device_type = msp432_device_type(msp432_bank->family_type, msp432_bank->device_id, msp432_bank->hardware_rev); - if (MSP432P4 == msp432_bank->family_type) { + if (msp432_bank->family_type == MSP432P4) { /* Set up MSP432P4 specific flash parameters */ if (is_main) { retval = target_read_u32(target, P4_FLASH_MAIN_SIZE_REG, &size); @@ -981,7 +981,7 @@ static int msp432_info(struct flash_bank *bank, struct command_invocation *cmd) switch (msp432_bank->device_type) { case MSP432P401X_DEPR: - if (0xFFFF == msp432_bank->device_id) { + if (msp432_bank->device_id == 0xFFFF) { /* Very early pre-production silicon currently deprecated */ command_print_sameline(cmd, "MSP432P401x pre-production device (deprecated silicon)\n" SUPPORT_MESSAGE); diff --git a/src/flash/nor/tms470.c b/src/flash/nor/tms470.c index 50783148b..37f093396 100644 --- a/src/flash/nor/tms470.c +++ b/src/flash/nor/tms470.c @@ -437,7 +437,7 @@ static int tms470_try_flash_keys(struct target *target, const uint32_t *key_set) target_write_u32(target, 0xFFE89C0C, key_set[i]); } - if (ERROR_OK == tms470_check_flash_unlocked(target)) { + if (tms470_check_flash_unlocked(target) == ERROR_OK) { /* * There seems to be a side-effect of reading the FMPKEY * register in that it re-enables the protection. So we diff --git a/src/helper/binarybuffer.c b/src/helper/binarybuffer.c index 49e347b6e..e2dfa87b6 100644 --- a/src/helper/binarybuffer.c +++ b/src/helper/binarybuffer.c @@ -222,7 +222,7 @@ static void str_radix_guess(const char **_str, unsigned *_str_len, unsigned *_radix) { unsigned radix = *_radix; - if (0 != radix) + if (radix != 0) return; const char *str = *_str; unsigned str_len = *_str_len; diff --git a/src/helper/jim-nvp.c b/src/helper/jim-nvp.c index 580b07915..e21bc680d 100644 --- a/src/helper/jim-nvp.c +++ b/src/helper/jim-nvp.c @@ -66,7 +66,7 @@ int jim_get_nvp(Jim_Interp *interp, struct jim_nvp *jim_nvp_name2value_simple(const struct jim_nvp *p, const char *name) { while (p->name) { - if (0 == strcmp(name, p->name)) + if (strcmp(name, p->name) == 0) break; p++; } @@ -76,7 +76,7 @@ struct jim_nvp *jim_nvp_name2value_simple(const struct jim_nvp *p, const char *n struct jim_nvp *jim_nvp_name2value_nocase_simple(const struct jim_nvp *p, const char *name) { while (p->name) { - if (0 == strcasecmp(name, p->name)) + if (strcasecmp(name, p->name) == 0) break; p++; } diff --git a/src/helper/replacements.c b/src/helper/replacements.c index 86ddd8075..81b1976d0 100644 --- a/src/helper/replacements.c +++ b/src/helper/replacements.c @@ -233,7 +233,7 @@ int win_select(int max_fd, fd_set *rfds, fd_set *wfds, fd_set *efds, struct time if (retcode < 0) retcode = 0; for (i = 0; i < n_handles; i++) { - if (WAIT_OBJECT_0 == WaitForSingleObject(handles[i], 0)) { + if (WaitForSingleObject(handles[i], 0) == WAIT_OBJECT_0) { if (SAFE_FD_ISSET(handle_slot_to_fd[i], rfds)) { DWORD bytes; intptr_t handle = (intptr_t) _get_osfhandle( diff --git a/src/helper/time_support.c b/src/helper/time_support.c index 05eaf0a9d..861889ec6 100644 --- a/src/helper/time_support.c +++ b/src/helper/time_support.c @@ -86,7 +86,7 @@ int duration_measure(struct duration *duration) { struct timeval end; int retval = gettimeofday(&end, NULL); - if (0 == retval) + if (retval == 0) timeval_subtract(&duration->elapsed, &end, &duration->start); return retval; } diff --git a/src/jtag/aice/aice_interface.c b/src/jtag/aice/aice_interface.c index 86e9d16c1..c7556c018 100644 --- a/src/jtag/aice/aice_interface.c +++ b/src/jtag/aice/aice_interface.c @@ -121,7 +121,7 @@ int aice_init_targets(void) */ static int aice_init(void) { - if (ERROR_OK != aice_port->api->open(¶m)) { + if (aice_port->api->open(¶m) != ERROR_OK) { LOG_ERROR("Cannot find AICE Interface! Please check " "connection and permissions."); return ERROR_JTAG_INIT_FAILED; @@ -217,7 +217,7 @@ static int aice_khz(int khz, int *jtag_speed) int i; for (i = 0 ; i < AICE_KHZ_TO_SPEED_MAP_SIZE ; i++) { if (khz == aice_khz_to_speed_map[i]) { - if (8 <= i) + if (i >= 8) *jtag_speed = i | AICE_TCK_CONTROL_TCK3048; else *jtag_speed = i; diff --git a/src/jtag/aice/aice_usb.c b/src/jtag/aice/aice_usb.c index 53d283846..8a8b83088 100644 --- a/src/jtag/aice/aice_usb.c +++ b/src/jtag/aice/aice_usb.c @@ -1835,9 +1835,9 @@ static int aice_check_dbger(uint32_t coreid, uint32_t expect_status) aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &value_dbger); if ((value_dbger & expect_status) == expect_status) { - if (ERROR_OK != check_suppressed_exception(coreid, value_dbger)) + if (check_suppressed_exception(coreid, value_dbger) != ERROR_OK) return ERROR_FAIL; - if (ERROR_OK != check_privilege(coreid, value_dbger)) + if (check_privilege(coreid, value_dbger) != ERROR_OK) return ERROR_FAIL; return ERROR_OK; } @@ -1895,18 +1895,18 @@ static int aice_read_reg(uint32_t coreid, uint32_t num, uint32_t *val) uint32_t instructions[4]; /** execute instructions in DIM */ - if (NDS32_REG_TYPE_GPR == nds32_reg_type(num)) { /* general registers */ + if (nds32_reg_type(num) == NDS32_REG_TYPE_GPR) { /* general registers */ instructions[0] = MTSR_DTR(num); instructions[1] = DSB; instructions[2] = NOP; instructions[3] = BEQ_MINUS_12; - } else if (NDS32_REG_TYPE_SPR == nds32_reg_type(num)) { /* user special registers */ + } else if (nds32_reg_type(num) == NDS32_REG_TYPE_SPR) { /* user special registers */ instructions[0] = MFUSR_G0(0, nds32_reg_sr_index(num)); instructions[1] = MTSR_DTR(0); instructions[2] = DSB; instructions[3] = BEQ_MINUS_12; - } else if (NDS32_REG_TYPE_AUMR == nds32_reg_type(num)) { /* audio registers */ - if ((CB_CTL <= num) && (num <= CBE3)) { + } else if (nds32_reg_type(num) == NDS32_REG_TYPE_AUMR) { /* audio registers */ + if ((num >= CB_CTL) && (num <= CBE3)) { instructions[0] = AMFAR2(0, nds32_reg_sr_index(num)); instructions[1] = MTSR_DTR(0); instructions[2] = DSB; @@ -1917,7 +1917,7 @@ static int aice_read_reg(uint32_t coreid, uint32_t num, uint32_t *val) instructions[2] = DSB; instructions[3] = BEQ_MINUS_12; } - } else if (NDS32_REG_TYPE_FPU == nds32_reg_type(num)) { /* fpu registers */ + } else if (nds32_reg_type(num) == NDS32_REG_TYPE_FPU) { /* fpu registers */ if (num == FPCSR) { instructions[0] = FMFCSR; instructions[1] = MTSR_DTR(0); @@ -1983,7 +1983,7 @@ static int aice_usb_read_reg(uint32_t coreid, uint32_t num, uint32_t *val) } else if ((core_info[coreid].target_dtr_valid == true) && (num == DR43)) { *val = core_info[coreid].target_dtr_backup; } else { - if (ERROR_OK != aice_read_reg(coreid, num, val)) + if (aice_read_reg(coreid, num, val) != ERROR_OK) *val = 0xBBADBEEF; } @@ -2004,18 +2004,18 @@ static int aice_write_reg(uint32_t coreid, uint32_t num, uint32_t val) return ERROR_FAIL; } - if (NDS32_REG_TYPE_GPR == nds32_reg_type(num)) { /* general registers */ + if (nds32_reg_type(num) == NDS32_REG_TYPE_GPR) { /* general registers */ instructions[0] = MFSR_DTR(num); instructions[1] = DSB; instructions[2] = NOP; instructions[3] = BEQ_MINUS_12; - } else if (NDS32_REG_TYPE_SPR == nds32_reg_type(num)) { /* user special registers */ + } else if (nds32_reg_type(num) == NDS32_REG_TYPE_SPR) { /* user special registers */ instructions[0] = MFSR_DTR(0); instructions[1] = MTUSR_G0(0, nds32_reg_sr_index(num)); instructions[2] = DSB; instructions[3] = BEQ_MINUS_12; - } else if (NDS32_REG_TYPE_AUMR == nds32_reg_type(num)) { /* audio registers */ - if ((CB_CTL <= num) && (num <= CBE3)) { + } else if (nds32_reg_type(num) == NDS32_REG_TYPE_AUMR) { /* audio registers */ + if ((num >= CB_CTL) && (num <= CBE3)) { instructions[0] = MFSR_DTR(0); instructions[1] = AMTAR2(0, nds32_reg_sr_index(num)); instructions[2] = DSB; @@ -2026,7 +2026,7 @@ static int aice_write_reg(uint32_t coreid, uint32_t num, uint32_t val) instructions[2] = DSB; instructions[3] = BEQ_MINUS_12; } - } else if (NDS32_REG_TYPE_FPU == nds32_reg_type(num)) { /* fpu registers */ + } else if (nds32_reg_type(num) == NDS32_REG_TYPE_FPU) { /* fpu registers */ if (num == FPCSR) { instructions[0] = MFSR_DTR(0); instructions[1] = FMTCSR; @@ -2146,7 +2146,7 @@ static int aice_usb_read_reg_64(uint32_t coreid, uint32_t num, uint64_t *val) uint32_t value; uint32_t high_value; - if (ERROR_OK != aice_read_reg(coreid, num, &value)) + if (aice_read_reg(coreid, num, &value) != ERROR_OK) value = 0xBBADBEEF; aice_read_reg(coreid, R1, &high_value); @@ -2503,10 +2503,10 @@ static int aice_restore_tmp_registers(uint32_t coreid) static int aice_open_device(struct aice_port_param_s *param) { - if (ERROR_OK != aice_usb_open(param)) + if (aice_usb_open(param) != ERROR_OK) return ERROR_FAIL; - if (ERROR_FAIL == aice_get_version_info()) { + if (aice_get_version_info() == ERROR_FAIL) { LOG_ERROR("Cannot get AICE version!"); return ERROR_FAIL; } @@ -2514,7 +2514,7 @@ static int aice_open_device(struct aice_port_param_s *param) LOG_INFO("AICE initialization started"); /* attempt to reset Andes EDM */ - if (ERROR_FAIL == aice_reset_box()) { + if (aice_reset_box() == ERROR_FAIL) { LOG_ERROR("Cannot initial AICE box!"); return ERROR_FAIL; } @@ -2526,7 +2526,7 @@ static int aice_usb_set_jtag_clock(uint32_t a_clock) { jtag_clock = a_clock; - if (ERROR_OK != aice_usb_set_clock(a_clock)) { + if (aice_usb_set_clock(a_clock) != ERROR_OK) { LOG_ERROR("Cannot set AICE JTAG clock!"); return ERROR_FAIL; } @@ -2705,7 +2705,7 @@ static int aice_usb_state(uint32_t coreid, enum aice_target_state_s *state) /* Clear CRST */ aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_CRST); } else if ((dbger_value & NDS_DBGER_DEX) == NDS_DBGER_DEX) { - if (AICE_TARGET_RUNNING == core_info[coreid].core_state) { + if (core_info[coreid].core_state == AICE_TARGET_RUNNING) { /* enter debug mode, init EDM registers */ /* backup EDM registers */ aice_backup_edm_registers(coreid); @@ -2713,7 +2713,7 @@ static int aice_usb_state(uint32_t coreid, enum aice_target_state_s *state) aice_init_edm_registers(coreid, true); aice_backup_tmp_registers(coreid); core_info[coreid].core_state = AICE_TARGET_HALTED; - } else if (AICE_TARGET_UNKNOWN == core_info[coreid].core_state) { + } else if (core_info[coreid].core_state == AICE_TARGET_UNKNOWN) { /* debug 'debug mode', use force debug to halt core */ aice_usb_halt(coreid); } @@ -2889,7 +2889,7 @@ static int aice_usb_assert_srst(uint32_t coreid, enum aice_srst_type_s srst) if (srst == AICE_SRST) result = aice_issue_srst(coreid); else { - if (1 == total_num_of_core) + if (total_num_of_core == 1) result = aice_issue_reset_hold(coreid); else result = aice_issue_reset_hold_multi(); @@ -2972,7 +2972,7 @@ static int aice_usb_step(uint32_t coreid) aice_write_reg(coreid, ir0_reg_num, ir0_value); } - if (ERROR_FAIL == aice_usb_run(coreid)) + if (aice_usb_run(coreid) == ERROR_FAIL) return ERROR_FAIL; int i = 0; @@ -3092,7 +3092,7 @@ static int aice_usb_read_memory_unit(uint32_t coreid, uint32_t addr, uint32_t si ", size: %" PRIu32 ", count: %" PRIu32 "", addr, size, count); - if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel) + if (core_info[coreid].access_channel == NDS_MEMORY_ACC_CPU) aice_usb_set_address_dim(coreid, addr); uint32_t value; @@ -3101,7 +3101,7 @@ static int aice_usb_read_memory_unit(uint32_t coreid, uint32_t addr, uint32_t si switch (size) { case 1: - if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel) + if (core_info[coreid].access_channel == NDS_MEMORY_ACC_BUS) read_mem_func = aice_usb_read_mem_b_bus; else read_mem_func = aice_usb_read_mem_b_dim; @@ -3113,7 +3113,7 @@ static int aice_usb_read_memory_unit(uint32_t coreid, uint32_t addr, uint32_t si } break; case 2: - if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel) + if (core_info[coreid].access_channel == NDS_MEMORY_ACC_BUS) read_mem_func = aice_usb_read_mem_h_bus; else read_mem_func = aice_usb_read_mem_h_dim; @@ -3127,7 +3127,7 @@ static int aice_usb_read_memory_unit(uint32_t coreid, uint32_t addr, uint32_t si } break; case 4: - if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel) + if (core_info[coreid].access_channel == NDS_MEMORY_ACC_BUS) read_mem_func = aice_usb_read_mem_w_bus; else read_mem_func = aice_usb_read_mem_w_dim; @@ -3211,7 +3211,7 @@ static int aice_usb_write_memory_unit(uint32_t coreid, uint32_t addr, uint32_t s ", size: %" PRIu32 ", count: %" PRIu32 "", addr, size, count); - if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel) + if (core_info[coreid].access_channel == NDS_MEMORY_ACC_CPU) aice_usb_set_address_dim(coreid, addr); size_t i; @@ -3219,7 +3219,7 @@ static int aice_usb_write_memory_unit(uint32_t coreid, uint32_t addr, uint32_t s switch (size) { case 1: - if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel) + if (core_info[coreid].access_channel == NDS_MEMORY_ACC_BUS) write_mem_func = aice_usb_write_mem_b_bus; else write_mem_func = aice_usb_write_mem_b_dim; @@ -3231,7 +3231,7 @@ static int aice_usb_write_memory_unit(uint32_t coreid, uint32_t addr, uint32_t s } break; case 2: - if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel) + if (core_info[coreid].access_channel == NDS_MEMORY_ACC_BUS) write_mem_func = aice_usb_write_mem_h_bus; else write_mem_func = aice_usb_write_mem_h_dim; @@ -3246,7 +3246,7 @@ static int aice_usb_write_memory_unit(uint32_t coreid, uint32_t addr, uint32_t s } break; case 4: - if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel) + if (core_info[coreid].access_channel == NDS_MEMORY_ACC_BUS) write_mem_func = aice_usb_write_mem_w_bus; else write_mem_func = aice_usb_write_mem_w_dim; @@ -3322,10 +3322,10 @@ static int aice_usb_bulk_read_mem(uint32_t coreid, uint32_t addr, int retval; - if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel) + if (core_info[coreid].access_channel == NDS_MEMORY_ACC_CPU) aice_usb_set_address_dim(coreid, addr); - if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel) + if (core_info[coreid].access_channel == NDS_MEMORY_ACC_CPU) retval = aice_usb_read_memory_unit(coreid, addr, 4, length / 4, buffer); else retval = aice_bulk_read_mem(coreid, addr, length / 4, buffer); @@ -3340,10 +3340,10 @@ static int aice_usb_bulk_write_mem(uint32_t coreid, uint32_t addr, int retval; - if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel) + if (core_info[coreid].access_channel == NDS_MEMORY_ACC_CPU) aice_usb_set_address_dim(coreid, addr); - if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel) + if (core_info[coreid].access_channel == NDS_MEMORY_ACC_CPU) retval = aice_usb_write_memory_unit(coreid, addr, 4, length / 4, buffer); else retval = aice_bulk_write_mem(coreid, addr, length / 4, buffer); @@ -3353,7 +3353,7 @@ static int aice_usb_bulk_write_mem(uint32_t coreid, uint32_t addr, static int aice_usb_read_debug_reg(uint32_t coreid, uint32_t addr, uint32_t *val) { - if (AICE_TARGET_HALTED == core_info[coreid].core_state) { + if (core_info[coreid].core_state == AICE_TARGET_HALTED) { if (addr == NDS_EDM_SR_EDMSW) { *val = core_info[coreid].edmsw_backup; } else if (addr == NDS_EDM_SR_EDM_DTR) { @@ -3373,7 +3373,7 @@ static int aice_usb_read_debug_reg(uint32_t coreid, uint32_t addr, uint32_t *val static int aice_usb_write_debug_reg(uint32_t coreid, uint32_t addr, const uint32_t val) { - if (AICE_TARGET_HALTED == core_info[coreid].core_state) { + if (core_info[coreid].core_state == AICE_TARGET_HALTED) { if (addr == NDS_EDM_SR_EDM_DTR) { core_info[coreid].host_dtr_backup = val; core_info[coreid].edmsw_backup |= 0x2; @@ -3402,7 +3402,7 @@ static int aice_usb_memory_mode(uint32_t coreid, enum nds_memory_select mem_sele core_info[coreid].memory_select = mem_select; - if (NDS_MEMORY_SELECT_AUTO != core_info[coreid].memory_select) + if (core_info[coreid].memory_select != NDS_MEMORY_SELECT_AUTO) aice_write_misc(coreid, NDS_EDM_MISC_ACC_CTL, core_info[coreid].memory_select - 1); else @@ -3454,13 +3454,13 @@ static int aice_usb_read_tlb(uint32_t coreid, target_addr_t virtual_address, aice_read_reg(coreid, MR4, &value_mr4); access_page_size = value_mr4 & 0xF; - if (0 == access_page_size) { /* 4K page */ + if (access_page_size == 0) { /* 4K page */ virtual_offset = virtual_address & 0x00000FFF; physical_page_number = value_mr3 & 0xFFFFF000; - } else if (1 == access_page_size) { /* 8K page */ + } else if (access_page_size == 1) { /* 8K page */ virtual_offset = virtual_address & 0x00001FFF; physical_page_number = value_mr3 & 0xFFFFE000; - } else if (5 == access_page_size) { /* 1M page */ + } else if (access_page_size == 5) { /* 1M page */ virtual_offset = virtual_address & 0x000FFFFF; physical_page_number = value_mr3 & 0xFFF00000; } else { @@ -3546,10 +3546,10 @@ static int aice_usb_dcache_inval_all(uint32_t coreid) cache_index = (way_index << (dcache->log2_set + dcache->log2_line_size)) | (set_index << dcache->log2_line_size); - if (ERROR_OK != aice_write_dtr(coreid, cache_index)) + if (aice_write_dtr(coreid, cache_index) != ERROR_OK) return ERROR_FAIL; - if (ERROR_OK != aice_execute_dim(coreid, instructions, 4)) + if (aice_execute_dim(coreid, instructions, 4) != ERROR_OK) return ERROR_FAIL; } } @@ -3594,10 +3594,10 @@ static int aice_usb_dcache_wb_all(uint32_t coreid) cache_index = (way_index << (dcache->log2_set + dcache->log2_line_size)) | (set_index << dcache->log2_line_size); - if (ERROR_OK != aice_write_dtr(coreid, cache_index)) + if (aice_write_dtr(coreid, cache_index) != ERROR_OK) return ERROR_FAIL; - if (ERROR_OK != aice_execute_dim(coreid, instructions, 4)) + if (aice_execute_dim(coreid, instructions, 4) != ERROR_OK) return ERROR_FAIL; } } @@ -3642,10 +3642,10 @@ static int aice_usb_icache_inval_all(uint32_t coreid) cache_index = (way_index << (icache->log2_set + icache->log2_line_size)) | (set_index << icache->log2_line_size); - if (ERROR_OK != aice_write_dtr(coreid, cache_index)) + if (aice_write_dtr(coreid, cache_index) != ERROR_OK) return ERROR_FAIL; - if (ERROR_OK != aice_execute_dim(coreid, instructions, 4)) + if (aice_execute_dim(coreid, instructions, 4) != ERROR_OK) return ERROR_FAIL; } } @@ -3896,13 +3896,13 @@ static int fill_profiling_batch_commands(uint32_t coreid, uint32_t reg_no) aice_read_dtr_to_buffer(coreid, AICE_BATCH_DATA_BUFFER_0); /* get samples */ - if (NDS32_REG_TYPE_GPR == nds32_reg_type(reg_no)) { + if (nds32_reg_type(reg_no) == NDS32_REG_TYPE_GPR) { /* general registers */ dim_instructions[0] = MTSR_DTR(reg_no); dim_instructions[1] = DSB; dim_instructions[2] = NOP; dim_instructions[3] = BEQ_MINUS_12; - } else if (NDS32_REG_TYPE_SPR == nds32_reg_type(reg_no)) { + } else if (nds32_reg_type(reg_no) == NDS32_REG_TYPE_SPR) { /* user special registers */ dim_instructions[0] = MFUSR_G0(0, nds32_reg_sr_index(reg_no)); dim_instructions[1] = MTSR_DTR(0); diff --git a/src/jtag/core.c b/src/jtag/core.c index 14062383f..13366e01b 100644 --- a/src/jtag/core.c +++ b/src/jtag/core.c @@ -243,7 +243,7 @@ struct jtag_tap *jtag_tap_by_string(const char *s) struct jtag_tap *t = jtag_all_taps(); while (t) { - if (0 == strcmp(t->dotted_name, s)) + if (strcmp(t->dotted_name, s) == 0) return t; t = t->next_tap; } @@ -1197,7 +1197,7 @@ static bool jtag_examine_chain_match_tap(const struct jtag_tap *tap) return true; /* treat "-expected-id 0" as a "don't-warn" wildcard */ - if (0 == tap->expected_ids[ii]) + if (tap->expected_ids[ii] == 0) return true; } diff --git a/src/jtag/drivers/buspirate.c b/src/jtag/drivers/buspirate.c index 642ad12f4..0864c60b3 100644 --- a/src/jtag/drivers/buspirate.c +++ b/src/jtag/drivers/buspirate.c @@ -800,7 +800,7 @@ static void buspirate_tap_append(int tms, int tdi) int bit_index = tap_chain_index % 8; uint8_t bit = 1 << bit_index; - if (0 == bit_index) { + if (bit_index == 0) { /* Let's say that the TAP shift operation wants to shift 9 bits, so we will be sending to the Bus Pirate a bit count of 9 but still full 16 bits (2 bytes) of shift data. @@ -1178,13 +1178,13 @@ static int buspirate_serial_setspeed(int fd, char speed, cc_t timeout) /* set the serial port parameters */ fcntl(fd, F_SETFL, 0); - if (0 != tcgetattr(fd, &t_opt)) + if (tcgetattr(fd, &t_opt) != 0) return -1; - if (0 != cfsetispeed(&t_opt, baud)) + if (cfsetispeed(&t_opt, baud) != 0) return -1; - if (0 != cfsetospeed(&t_opt, baud)) + if (cfsetospeed(&t_opt, baud) != 0) return -1; t_opt.c_cflag |= (CLOCAL | CREAD); @@ -1206,7 +1206,7 @@ static int buspirate_serial_setspeed(int fd, char speed, cc_t timeout) /* Note that, in the past, TCSANOW was used below instead of TCSADRAIN, and CMD_UART_SPEED did not work properly then, at least with the Bus Pirate v3.5 (USB). */ - if (0 != tcsetattr(fd, TCSADRAIN, &t_opt)) { + if (tcsetattr(fd, TCSADRAIN, &t_opt) != 0) { /* According to the Linux documentation, this is actually not enough to detect errors, you need to call tcgetattr() and check that all changes have been performed successfully. */ diff --git a/src/jtag/drivers/cmsis_dap_usb_hid.c b/src/jtag/drivers/cmsis_dap_usb_hid.c index ff0ac7837..5bb8ee8b1 100644 --- a/src/jtag/drivers/cmsis_dap_usb_hid.c +++ b/src/jtag/drivers/cmsis_dap_usb_hid.c @@ -73,7 +73,7 @@ static int cmsis_dap_hid_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t p while (cur_dev) { bool found = false; - if (0 == vids[0]) { + if (vids[0] == 0) { if (!cur_dev->product_string) { LOG_DEBUG("Cannot read product string of device 0x%x:0x%x", cur_dev->vendor_id, cur_dev->product_id); diff --git a/src/jtag/drivers/versaloon/usbtoxxx/usbtoxxx.c b/src/jtag/drivers/versaloon/usbtoxxx/usbtoxxx.c index fecd32c32..f701bb052 100644 --- a/src/jtag/drivers/versaloon/usbtoxxx/usbtoxxx.c +++ b/src/jtag/drivers/versaloon/usbtoxxx/usbtoxxx.c @@ -126,12 +126,12 @@ RESULT usbtoxxx_execute_command(void) return ERROR_FAIL; } - if (ERROR_OK != usbtoxxx_validate_current_command_type()) { + if (usbtoxxx_validate_current_command_type() != ERROR_OK) { LOG_BUG(ERRMSG_FAILURE_OPERATION, "validate previous commands"); versaloon_free_want_pos(); return ERRCODE_FAILURE_OPERATION; } - if (3 == usbtoxxx_buffer_index) { + if (usbtoxxx_buffer_index == 3) { versaloon_free_want_pos(); return ERROR_OK; } @@ -139,7 +139,7 @@ RESULT usbtoxxx_execute_command(void) versaloon_buf[0] = USB_TO_ALL; SET_LE_U16(&versaloon_buf[1], usbtoxxx_buffer_index); - if (ERROR_OK != versaloon_send_command(usbtoxxx_buffer_index, &inlen)) { + if (versaloon_send_command(usbtoxxx_buffer_index, &inlen) != ERROR_OK) { versaloon_free_want_pos(); return ERROR_FAIL; } @@ -148,7 +148,7 @@ RESULT usbtoxxx_execute_command(void) usbtoxxx_buffer_index = 0; for (i = 0; i < versaloon_pending_idx; i++) { /* check result */ - if ((0 == i) || !((versaloon_pending[i].collect) + if ((i == 0) || !((versaloon_pending[i].collect) && (versaloon_pending[i - 1].collect) && (versaloon_pending[i].cmd == versaloon_pending[i - 1].cmd))) { @@ -159,7 +159,7 @@ RESULT usbtoxxx_execute_command(void) "current dongle"); result = ERROR_FAIL; break; - } else if (USB_TO_XXX_OK != versaloon_buf[usbtoxxx_buffer_index]) { + } else if (versaloon_buf[usbtoxxx_buffer_index] != USB_TO_XXX_OK) { LOG_ERROR("%s command 0x%02x failed with 0x%02x", usbtoxxx_get_type_name(versaloon_pending[i].type), versaloon_pending[i].cmd, @@ -245,8 +245,8 @@ RESULT usbtoxxx_init(void) { versaloon_pending_idx = 0; - if ((ERROR_OK != usbtoinfo_get_abilities(usbtoxxx_abilities)) || - (ERROR_OK != usbtoxxx_execute_command())) + if ((usbtoinfo_get_abilities(usbtoxxx_abilities) != ERROR_OK) || + (usbtoxxx_execute_command() != ERROR_OK)) return ERROR_FAIL; LOG_INFO("USB_TO_XXX abilities: 0x%08X:0x%08X:0x%08X", GET_LE_U32(&usbtoxxx_abilities[0]), @@ -283,7 +283,7 @@ static RESULT usbtoxxx_ensure_buffer_size(uint16_t cmdlen) memset(&context_tmp, 0, sizeof(context_tmp)); if (poll_nesting) { - if (0 == poll_context.type_pre) { + if (poll_context.type_pre == 0) { LOG_BUG("USB_TO_POLL toooooo long"); return ERROR_OK; } @@ -329,18 +329,18 @@ RESULT usbtoxxx_add_command(uint8_t type, uint8_t cmd, uint8_t *cmdbuf, /* 3 more bytes by usbtoxxx_validate_current_command_type */ /* 3 more bytes when ((0 == collect_index) || (collect_cmd != cmd)) */ - if (ERROR_OK != usbtoxxx_ensure_buffer_size(cmdlen + 6)) + if (usbtoxxx_ensure_buffer_size(cmdlen + 6) != ERROR_OK) return ERROR_FAIL; if ((type_pre != type) || (!usbtoxxx_buffer)) { - if (ERROR_OK != usbtoxxx_validate_current_command_type()) { + if (usbtoxxx_validate_current_command_type() != ERROR_OK) { LOG_BUG(ERRMSG_FAILURE_OPERATION, "validate previous commands"); return ERRCODE_FAILURE_OPERATION; } type_pre = type; } - if ((0 == collect_index) || (collect_cmd != cmd)) { + if ((collect_index == 0) || (collect_cmd != cmd)) { usbtoxxx_buffer[usbtoxxx_current_cmd_index++] = cmd; if (collect) { @@ -368,10 +368,10 @@ RESULT usbtoxxx_add_command(uint8_t type, uint8_t cmd, uint8_t *cmdbuf, RESULT usbtoinfo_get_abilities(uint8_t abilities[USB_TO_XXX_ABILITIES_LEN]) { - if (ERROR_OK != usbtoxxx_ensure_buffer_size(3)) + if (usbtoxxx_ensure_buffer_size(3) != ERROR_OK) return ERROR_FAIL; - if (ERROR_OK != usbtoxxx_validate_current_command_type()) { + if (usbtoxxx_validate_current_command_type() != ERROR_OK) { LOG_BUG(ERRMSG_FAILURE_OPERATION, "validate previous commands"); return ERRCODE_FAILURE_OPERATION; } @@ -383,12 +383,12 @@ RESULT usbtoinfo_get_abilities(uint8_t abilities[USB_TO_XXX_ABILITIES_LEN]) RESULT usbtopoll_start(uint16_t retry_cnt, uint16_t interval_us) { - if (ERROR_OK != usbtoxxx_ensure_buffer_size(3 + 5)) + if (usbtoxxx_ensure_buffer_size(3 + 5) != ERROR_OK) return ERROR_FAIL; if (!poll_nesting) usbtoxxx_save_context(&poll_context); - if (ERROR_OK != usbtoxxx_validate_current_command_type()) { + if (usbtoxxx_validate_current_command_type() != ERROR_OK) { LOG_BUG(ERRMSG_FAILURE_OPERATION, "validate previous commands"); return ERRCODE_FAILURE_OPERATION; } @@ -410,10 +410,10 @@ RESULT usbtopoll_end(void) LOG_BUG(ERRMSG_FAILURE_OPERATION, "check poll nesting"); return ERRCODE_FAILURE_OPERATION; } - if (ERROR_OK != usbtoxxx_ensure_buffer_size(3 + 1)) + if (usbtoxxx_ensure_buffer_size(3 + 1) != ERROR_OK) return ERROR_FAIL; - if (ERROR_OK != usbtoxxx_validate_current_command_type()) { + if (usbtoxxx_validate_current_command_type() != ERROR_OK) { LOG_BUG(ERRMSG_FAILURE_OPERATION, "validate previous commands"); return ERRCODE_FAILURE_OPERATION; } @@ -439,10 +439,10 @@ RESULT usbtopoll_checkok(uint8_t equ, uint16_t offset, uint8_t size, LOG_BUG(ERRMSG_FAILURE_OPERATION, "check poll nesting"); return ERRCODE_FAILURE_OPERATION; } - if (ERROR_OK != usbtoxxx_ensure_buffer_size(3 + 4 + 2 * size)) + if (usbtoxxx_ensure_buffer_size(3 + 4 + 2 * size) != ERROR_OK) return ERROR_FAIL; - if (ERROR_OK != usbtoxxx_validate_current_command_type()) { + if (usbtoxxx_validate_current_command_type() != ERROR_OK) { LOG_BUG(ERRMSG_FAILURE_OPERATION, "validate previous commands"); return ERRCODE_FAILURE_OPERATION; } @@ -475,10 +475,10 @@ RESULT usbtopoll_checkfail(uint8_t equ, uint16_t offset, uint8_t size, LOG_BUG(ERRMSG_FAILURE_OPERATION, "check poll nesting"); return ERRCODE_FAILURE_OPERATION; } - if (ERROR_OK != usbtoxxx_ensure_buffer_size(3 + 4 + 2 * size)) + if (usbtoxxx_ensure_buffer_size(3 + 4 + 2 * size) != ERROR_OK) return ERROR_FAIL; - if (ERROR_OK != usbtoxxx_validate_current_command_type()) { + if (usbtoxxx_validate_current_command_type() != ERROR_OK) { LOG_BUG(ERRMSG_FAILURE_OPERATION, "validate previous commands"); return ERRCODE_FAILURE_OPERATION; } @@ -504,10 +504,10 @@ RESULT usbtopoll_verifybuff(uint16_t offset, uint16_t size, uint8_t *buff) LOG_BUG(ERRMSG_FAILURE_OPERATION, "check poll nesting"); return ERRCODE_FAILURE_OPERATION; } - if (ERROR_OK != usbtoxxx_ensure_buffer_size(3 + 5 + size)) + if (usbtoxxx_ensure_buffer_size(3 + 5 + size) != ERROR_OK) return ERROR_FAIL; - if (ERROR_OK != usbtoxxx_validate_current_command_type()) { + if (usbtoxxx_validate_current_command_type() != ERROR_OK) { LOG_BUG(ERRMSG_FAILURE_OPERATION, "validate previous commands"); return ERRCODE_FAILURE_OPERATION; } @@ -527,10 +527,10 @@ RESULT usbtopoll_verifybuff(uint16_t offset, uint16_t size, uint8_t *buff) RESULT usbtodelay_delay(uint16_t dly) { - if (ERROR_OK != usbtoxxx_ensure_buffer_size(3 + 2)) + if (usbtoxxx_ensure_buffer_size(3 + 2) != ERROR_OK) return ERROR_FAIL; - if (ERROR_OK != usbtoxxx_validate_current_command_type()) { + if (usbtoxxx_validate_current_command_type() != ERROR_OK) { LOG_BUG(ERRMSG_FAILURE_OPERATION, "validate previous commands"); return ERRCODE_FAILURE_OPERATION; } diff --git a/src/jtag/drivers/versaloon/versaloon.c b/src/jtag/drivers/versaloon/versaloon.c index 199c89818..b17c1d49b 100644 --- a/src/jtag/drivers/versaloon/versaloon.c +++ b/src/jtag/drivers/versaloon/versaloon.c @@ -203,7 +203,7 @@ RESULT versaloon_send_command(uint16_t out_len, uint16_t *inlen) LOG_BUG(ERRMSG_INVALID_BUFFER, TO_STR(versaloon_buf)); return ERRCODE_INVALID_BUFFER; } - if ((0 == out_len) || (out_len > versaloon_interface.usb_setting.buf_size)) { + if ((out_len == 0) || (out_len > versaloon_interface.usb_setting.buf_size)) { LOG_BUG(ERRMSG_INVALID_PARAMETER, __func__); return ERRCODE_INVALID_PARAMETER; } @@ -222,7 +222,7 @@ RESULT versaloon_send_command(uint16_t out_len, uint16_t *inlen) versaloon_interface.usb_setting.ep_in, versaloon_buf, versaloon_interface.usb_setting.buf_size, &transferred, versaloon_usb_to); - if (0 == ret) { + if (ret == 0) { *inlen = (uint16_t)transferred; return ERROR_OK; } else { @@ -254,7 +254,7 @@ static RESULT versaloon_init(void) versaloon_usb_to = 100; for (retry = 0; retry < VERSALOON_RETRY_CNT; retry++) { versaloon_buf[0] = VERSALOON_GET_INFO; - if ((ERROR_OK == versaloon_send_command(1, &ret)) && (ret >= 3)) + if ((versaloon_send_command(1, &ret) == ERROR_OK) && (ret >= 3)) break; } versaloon_usb_to = timeout_tmp; @@ -285,7 +285,7 @@ static RESULT versaloon_init(void) LOG_ERROR(ERRMSG_NOT_ENOUGH_MEMORY); return ERRCODE_NOT_ENOUGH_MEMORY; } - if (ERROR_OK != usbtoxxx_init()) { + if (usbtoxxx_init() != ERROR_OK) { LOG_ERROR(ERRMSG_FAILURE_OPERATION, "initialize usbtoxxx"); return ERROR_FAIL; } @@ -337,7 +337,7 @@ static RESULT versaloon_get_target_voltage(uint16_t *voltage) versaloon_buf[0] = VERSALOON_GET_TVCC; - if ((ERROR_OK != versaloon_send_command(1, &inlen)) || (inlen != 2)) { + if ((versaloon_send_command(1, &inlen) != ERROR_OK) || (inlen != 2)) { LOG_ERROR(ERRMSG_FAILURE_OPERATION, "communicate with versaloon"); return ERRCODE_FAILURE_OPERATION; } else { diff --git a/src/jtag/drivers/vsllink.c b/src/jtag/drivers/vsllink.c index d298a9407..57a7c666f 100644 --- a/src/jtag/drivers/vsllink.c +++ b/src/jtag/drivers/vsllink.c @@ -287,7 +287,7 @@ static int vsllink_interface_init(void) libusb_init(&vsllink_handle->libusb_ctx); - if (ERROR_OK != vsllink_usb_open(vsllink_handle)) { + if (vsllink_usb_open(vsllink_handle) != ERROR_OK) { LOG_ERROR("Can't find USB JTAG Interface!" "Please check connection and permissions."); return ERROR_JTAG_INIT_FAILED; @@ -297,7 +297,7 @@ static int vsllink_interface_init(void) versaloon_interface.usb_setting.pid); versaloon_usb_device_handle = vsllink_handle->usb_device_handle; - if (ERROR_OK != versaloon_interface.init()) + if (versaloon_interface.init() != ERROR_OK) return ERROR_FAIL; if (versaloon_interface.usb_setting.buf_size < 32) { versaloon_interface.fini(); @@ -344,7 +344,7 @@ static int vsllink_init(void) GPIO_TRST, GPIO_SRST, GPIO_SRST); } - if (ERROR_OK != versaloon_interface.adaptors.peripheral_commit()) + if (versaloon_interface.adaptors.peripheral_commit() != ERROR_OK) return ERROR_FAIL; vsllink_reset(0, 0); diff --git a/src/jtag/drivers/xds110.c b/src/jtag/drivers/xds110.c index f62051422..243577d7c 100644 --- a/src/jtag/drivers/xds110.c +++ b/src/jtag/drivers/xds110.c @@ -341,7 +341,7 @@ static bool usb_connect(void) /* Initialize libusb context */ result = libusb_init(&ctx); - if (0 == result) { + if (result == 0) { /* Get list of USB devices attached to system */ count = libusb_get_device_list(ctx, &list); if (count <= 0) { @@ -350,7 +350,7 @@ static bool usb_connect(void) } } - if (0 == result) { + if (result == 0) { /* Scan through list of devices for any XDS110s */ for (i = 0; i < count; i++) { /* Check for device vid/pid match */ @@ -365,13 +365,13 @@ static bool usb_connect(void) } if (match) { result = libusb_open(list[i], &dev); - if (0 == result) { + if (result == 0) { const int max_data = 256; unsigned char data[max_data + 1]; *data = '\0'; /* May be the requested device if serial number matches */ - if (0 == xds110.serial[0]) { + if (xds110.serial[0] == 0) { /* No serial number given; match first XDS110 found */ found = true; break; @@ -430,7 +430,7 @@ static bool usb_connect(void) } /* On an error, clean up what we can */ - if (0 != result) { + if (result != 0) { if (dev) { /* Release the debug and data interface on the XDS110 */ (void)libusb_release_interface(dev, xds110.interface); @@ -443,12 +443,12 @@ static bool usb_connect(void) } /* Log the results */ - if (0 == result) + if (result == 0) LOG_INFO("XDS110: connected"); else LOG_ERROR("XDS110: failed to connect"); - return (0 == result) ? true : false; + return (result == 0) ? true : false; } static void usb_disconnect(void) @@ -476,13 +476,13 @@ static bool usb_read(unsigned char *buffer, int size, int *bytes_read, return false; /* Force a non-zero timeout to prevent blocking */ - if (0 == timeout) + if (timeout == 0) timeout = DEFAULT_TIMEOUT; result = libusb_bulk_transfer(xds110.dev, xds110.endpoint_in, buffer, size, bytes_read, timeout); - return (0 == result) ? true : false; + return (result == 0) ? true : false; } static bool usb_write(unsigned char *buffer, int size, int *written) @@ -671,7 +671,7 @@ static bool xds_execute(uint32_t out_length, uint32_t in_length, if (!success) error = SC_ERR_XDS110_FAIL; - if (0 != error) + if (error != 0) success = false; return success; @@ -1280,7 +1280,7 @@ static int xds110_swd_run_queue(void) uint32_t value; bool success = true; - if (0 == xds110.txn_request_size) + if (xds110.txn_request_size == 0) return ERROR_OK; /* Terminate request queue */ @@ -1316,7 +1316,7 @@ static int xds110_swd_run_queue(void) /* Transfer results into caller's buffers */ for (result = 0; result < xds110.txn_result_count; result++) - if (0 != xds110.txn_dap_results[result]) + if (xds110.txn_dap_results[result] != 0) *xds110.txn_dap_results[result] = dap_results[result]; xds110.txn_request_size = 0; @@ -1395,7 +1395,7 @@ static void xds110_show_info(void) (((firmware >> 12) & 0xf) * 10) + ((firmware >> 8) & 0xf), (((firmware >> 4) & 0xf) * 10) + ((firmware >> 0) & 0xf)); LOG_INFO("XDS110: hardware version = 0x%04x", xds110.hardware); - if (0 != xds110.serial[0]) + if (xds110.serial[0] != 0) LOG_INFO("XDS110: serial number = %s", xds110.serial); if (xds110.is_swd_mode) { LOG_INFO("XDS110: connected to target via SWD"); @@ -1470,12 +1470,12 @@ static int xds110_init(void) if (success) { /* Set supply voltage for stand-alone probes */ - if (XDS110_STAND_ALONE_ID == xds110.hardware) { + if (xds110.hardware == XDS110_STAND_ALONE_ID) { success = xds_set_supply(xds110.voltage); /* Allow time for target device to power up */ /* (CC32xx takes up to 1300 ms before debug is enabled) */ alive_sleep(1500); - } else if (0 != xds110.voltage) { + } else if (xds110.voltage != 0) { /* Voltage supply not a feature of embedded probes */ LOG_WARNING( "XDS110: ignoring supply voltage, not supported on this probe"); @@ -1557,7 +1557,7 @@ static void xds110_flush(void) uint8_t data_in[MAX_DATA_BLOCK]; uint8_t *data_pntr; - if (0 == xds110.txn_request_size) + if (xds110.txn_request_size == 0) return; /* Terminate request queue */ diff --git a/src/rtos/embKernel.c b/src/rtos/embKernel.c index 85c8d1905..d70ae37d9 100644 --- a/src/rtos/embKernel.c +++ b/src/rtos/embKernel.c @@ -121,7 +121,7 @@ static int embkernel_create(struct target *target) { size_t i = 0; while ((i < ARRAY_SIZE(embkernel_params_list)) && - (0 != strcmp(embkernel_params_list[i].target_name, target->type->name))) + (strcmp(embkernel_params_list[i].target_name, target->type->name) != 0)) i++; if (i >= ARRAY_SIZE(embkernel_params_list)) { diff --git a/src/rtos/mqx.c b/src/rtos/mqx.c index 777d23ce3..754470e3c 100644 --- a/src/rtos/mqx.c +++ b/src/rtos/mqx.c @@ -260,7 +260,7 @@ static int mqx_create( { /* check target name against supported architectures */ for (unsigned int i = 0; i < ARRAY_SIZE(mqx_params_list); i++) { - if (0 == strcmp(mqx_params_list[i].target_name, target->type->name)) { + if (strcmp(mqx_params_list[i].target_name, target->type->name) == 0) { target->rtos->rtos_specific_params = (void *)&mqx_params_list[i]; /* LOG_DEBUG("MQX RTOS - valid architecture: %s", target->type->name); */ return 0; @@ -291,7 +291,7 @@ static int mqx_update_threads( /* clear old data */ rtos_free_threadlist(rtos); /* check scheduler */ - if (ERROR_OK != mqx_is_scheduler_running(rtos)) + if (mqx_is_scheduler_running(rtos) != ERROR_OK) return ERROR_FAIL; /* get kernel_data symbol */ if (mqx_get_symbol(rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_addr) != ERROR_OK) @@ -438,7 +438,7 @@ static int mqx_get_thread_reg_list( LOG_ERROR("MQX RTOS - invalid threadid: 0x%X", (int)thread_id); return ERROR_FAIL; } - if (ERROR_OK != mqx_is_scheduler_running(rtos)) + if (mqx_is_scheduler_running(rtos) != ERROR_OK) return ERROR_FAIL; /* get kernel_data symbol */ if (mqx_get_symbol(rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_addr) != ERROR_OK) diff --git a/src/rtos/riot.c b/src/rtos/riot.c index 6652db651..fb5d1b29d 100644 --- a/src/rtos/riot.c +++ b/src/rtos/riot.c @@ -401,7 +401,7 @@ static int riot_create(struct target *target) /* lookup if target is supported by RIOT */ while ((i < RIOT_NUM_PARAMS) && - (0 != strcmp(riot_params_list[i].target_name, target->type->name))) { + (strcmp(riot_params_list[i].target_name, target->type->name) != 0)) { i++; } if (i >= RIOT_NUM_PARAMS) { diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c index 2b6215430..c9c4efd41 100644 --- a/src/rtos/rtos.c +++ b/src/rtos/rtos.c @@ -152,7 +152,7 @@ int rtos_create(struct jim_getopt_info *goi, struct target *target) } for (x = 0; rtos_types[x]; x++) - if (0 == strcmp(cp, rtos_types[x]->name)) + if (strcmp(cp, rtos_types[x]->name) == 0) return os_alloc_create(target, rtos_types[x]); Jim_SetResultFormatted(goi->interp, "Unknown RTOS type %s, try one of: ", cp); diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c index 3a39f8a25..015baa1d8 100644 --- a/src/server/gdb_server.c +++ b/src/server/gdb_server.c @@ -1212,7 +1212,7 @@ static int gdb_get_registers_packet(struct connection *connection, LOG_DEBUG("-"); #endif - if ((target->rtos) && (ERROR_OK == rtos_get_gdb_reg_list(connection))) + if ((target->rtos) && (rtos_get_gdb_reg_list(connection) == ERROR_OK)) return ERROR_OK; retval = target_get_gdb_reg_list(target, ®_list, ®_list_size, @@ -1342,7 +1342,7 @@ static int gdb_get_register_packet(struct connection *connection, LOG_DEBUG("-"); #endif - if ((target->rtos) && (ERROR_OK == rtos_get_gdb_reg(connection, reg_num))) + if ((target->rtos) && (rtos_get_gdb_reg(connection, reg_num) == ERROR_OK)) return ERROR_OK; retval = target_get_gdb_reg_list_noread(target, ®_list, ®_list_size, @@ -1399,7 +1399,7 @@ static int gdb_set_register_packet(struct connection *connection, gdb_target_to_reg(target, separator + 1, chars, bin_buf); if ((target->rtos) && - (ERROR_OK == rtos_set_reg(connection, reg_num, bin_buf))) { + (rtos_set_reg(connection, reg_num, bin_buf) == ERROR_OK)) { free(bin_buf); gdb_put_packet(connection, "OK", 2); return ERROR_OK; diff --git a/src/svf/svf.c b/src/svf/svf.c index c93d530d2..3021dcb66 100644 --- a/src/svf/svf.c +++ b/src/svf/svf.c @@ -460,25 +460,25 @@ COMMAND_HANDLER(handle_svf_command) } /* HDR %d TDI (0) */ - if (ERROR_OK != svf_set_padding(&svf_para.hdr_para, header_dr_len, 0)) { + if (svf_set_padding(&svf_para.hdr_para, header_dr_len, 0) != ERROR_OK) { LOG_ERROR("failed to set data header"); return ERROR_FAIL; } /* HIR %d TDI (0xFF) */ - if (ERROR_OK != svf_set_padding(&svf_para.hir_para, header_ir_len, 0xFF)) { + if (svf_set_padding(&svf_para.hir_para, header_ir_len, 0xFF) != ERROR_OK) { LOG_ERROR("failed to set instruction header"); return ERROR_FAIL; } /* TDR %d TDI (0) */ - if (ERROR_OK != svf_set_padding(&svf_para.tdr_para, trailer_dr_len, 0)) { + if (svf_set_padding(&svf_para.tdr_para, trailer_dr_len, 0) != ERROR_OK) { LOG_ERROR("failed to set data trailer"); return ERROR_FAIL; } /* TIR %d TDI (0xFF) */ - if (ERROR_OK != svf_set_padding(&svf_para.tir_para, trailer_ir_len, 0xFF)) { + if (svf_set_padding(&svf_para.tir_para, trailer_ir_len, 0xFF) != ERROR_OK) { LOG_ERROR("failed to set instruction trailer"); return ERROR_FAIL; } @@ -492,7 +492,7 @@ COMMAND_HANDLER(handle_svf_command) } rewind(svf_fd); } - while (ERROR_OK == svf_read_command_from_file(svf_fd)) { + while (svf_read_command_from_file(svf_fd) == ERROR_OK) { /* Log Output */ if (svf_quiet) { if (svf_progress_enabled) { @@ -510,7 +510,7 @@ COMMAND_HANDLER(handle_svf_command) LOG_USER_N("%s", svf_read_line); } /* Run Command */ - if (ERROR_OK != svf_run_command(CMD_CTX, svf_command_buffer)) { + if (svf_run_command(CMD_CTX, svf_command_buffer) != ERROR_OK) { LOG_ERROR("fail to run command at line %d", svf_line_number); ret = ERROR_FAIL; break; @@ -518,9 +518,9 @@ COMMAND_HANDLER(handle_svf_command) command_num++; } - if ((!svf_nil) && (ERROR_OK != jtag_execute_queue())) + if ((!svf_nil) && (jtag_execute_queue() != ERROR_OK)) ret = ERROR_FAIL; - else if (ERROR_OK != svf_check_tdo()) + else if (svf_check_tdo() != ERROR_OK) ret = ERROR_FAIL; /* print time */ @@ -790,7 +790,7 @@ static int svf_copy_hexstring_to_binary(char *str, uint8_t **bin, int orig_bit_l int i, str_len = strlen(str), str_hbyte_len = (bit_len + 3) >> 2; uint8_t ch = 0; - if (ERROR_OK != svf_adjust_array_length(bin, orig_bit_len, bit_len)) { + if (svf_adjust_array_length(bin, orig_bit_len, bit_len) != ERROR_OK) { LOG_ERROR("fail to adjust length of array"); return ERROR_FAIL; } @@ -893,9 +893,9 @@ static int svf_add_check_para(uint8_t enabled, int buffer_offset, int bit_len) static int svf_execute_tap(void) { - if ((!svf_nil) && (ERROR_OK != jtag_execute_queue())) + if ((!svf_nil) && (jtag_execute_queue() != ERROR_OK)) return ERROR_FAIL; - else if (ERROR_OK != svf_check_tdo()) + else if (svf_check_tdo() != ERROR_OK) return ERROR_FAIL; svf_buffer_index = 0; @@ -923,7 +923,7 @@ static int svf_run_command(struct command_context *cmd_ctx, char *cmd_str) /* flag padding commands skipped due to -tap command */ int padding_command_skipped = 0; - if (ERROR_OK != svf_parse_cmd_string(cmd_str, strlen(cmd_str), argus, &num_of_argu)) + if (svf_parse_cmd_string(cmd_str, strlen(cmd_str), argus, &num_of_argu) != ERROR_OK) return ERROR_FAIL; /* NOTE: we're a bit loose here, because we ignore case in @@ -963,7 +963,7 @@ static int svf_run_command(struct command_context *cmd_ctx, char *cmd_str) LOG_ERROR("invalid parameter of %s", argus[0]); return ERROR_FAIL; } - if (1 == num_of_argu) { + if (num_of_argu == 1) { /* TODO: set jtag speed to full speed */ svf_para.frequency = 0; } else { @@ -971,7 +971,7 @@ static int svf_run_command(struct command_context *cmd_ctx, char *cmd_str) LOG_ERROR("HZ not found in FREQUENCY command"); return ERROR_FAIL; } - if (ERROR_OK != svf_execute_tap()) + if (svf_execute_tap() != ERROR_OK) return ERROR_FAIL; svf_para.frequency = atof(argus[1]); /* TODO: set jtag speed to */ @@ -1434,7 +1434,7 @@ xxr_common: return ERROR_FAIL; } /* OpenOCD refuses paths containing TAP_RESET */ - if (TAP_RESET == path[i]) { + if (path[i] == TAP_RESET) { /* FIXME last state MUST be stable! */ if (i > 0) { if (!svf_nil) @@ -1487,7 +1487,7 @@ xxr_common: return ERROR_FAIL; } if (svf_para.trst_mode != TRST_ABSENT) { - if (ERROR_OK != svf_execute_tap()) + if (svf_execute_tap() != ERROR_OK) return ERROR_FAIL; i_tmp = svf_find_string_in_array(argus[1], (char **)svf_trst_mode_name, @@ -1530,7 +1530,7 @@ xxr_common: if ((svf_buffer_index > 0) && (((command != STATE) && (command != RUNTEST)) || ((command == STATE) && (num_of_argu == 2)))) { - if (ERROR_OK != svf_execute_tap()) + if (svf_execute_tap() != ERROR_OK) return ERROR_FAIL; /* output debug info */ diff --git a/src/target/armv8.c b/src/target/armv8.c index 43a365938..749ea8729 100644 --- a/src/target/armv8.c +++ b/src/target/armv8.c @@ -1062,7 +1062,7 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command) return ERROR_OK; } - while (CMD_ARGC > argp) { + while (argp < CMD_ARGC) { n = jim_nvp_name2value_simple(nvp_ecatch_modes, CMD_ARGV[argp]); if (!n->name) { LOG_ERROR("Unknown option: %s", CMD_ARGV[argp]); diff --git a/src/target/lakemont.c b/src/target/lakemont.c index c30ac3b74..576956e31 100644 --- a/src/target/lakemont.c +++ b/src/target/lakemont.c @@ -611,7 +611,7 @@ static int read_all_core_hw_regs(struct targe... [truncated message content] |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-24 09:38:33
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via b159f5cdedd70fff9309722e927be670845f4df5 (commit) from 20b29b7767097f999fe2eb4f7fb6c2917e9f66a6 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit b159f5cdedd70fff9309722e927be670845f4df5 Author: Antonio Borneo <bor...@gm...> Date: Tue Apr 27 18:46:43 2021 +0200 target: rename CamelCase symbols No major cross dependencies, mostly changes internal to each file/function. Change-Id: I7cc87458a341bae29a4f772b0af5d97b4bfc2da3 Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6343 Tested-by: jenkins Reviewed-by: Marc Schink <de...@za...> diff --git a/src/target/avr32_ap7k.c b/src/target/avr32_ap7k.c index b0c08752d..4cf0276d6 100644 --- a/src/target/avr32_ap7k.c +++ b/src/target/avr32_ap7k.c @@ -526,7 +526,7 @@ static int avr32_ap7k_target_create(struct target *target, Jim_Interp *interp) struct avr32_ap7k_common *ap7k = calloc(1, sizeof(struct avr32_ap7k_common)); - ap7k->common_magic = AP7k_COMMON_MAGIC; + ap7k->common_magic = AP7K_COMMON_MAGIC; target->arch_info = ap7k; return ERROR_OK; diff --git a/src/target/avr32_ap7k.h b/src/target/avr32_ap7k.h index 3f27534a3..65b856ef1 100644 --- a/src/target/avr32_ap7k.h +++ b/src/target/avr32_ap7k.h @@ -20,7 +20,7 @@ struct target; -#define AP7k_COMMON_MAGIC 0x4150374b +#define AP7K_COMMON_MAGIC 0x4150374b struct avr32_ap7k_common { int common_magic; struct avr32_jtag jtag; diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c index 5ad52b58d..0d80ed367 100644 --- a/src/target/dsp563xx.c +++ b/src/target/dsp563xx.c @@ -96,10 +96,10 @@ /* * OBCR Register bit definitions */ -#define OBCR_b0_and_b1 ((0x0) << 10) -#define OBCR_b0_or_b1 ((0x1) << 10) -#define OBCR_b1_after_b0 ((0x2) << 10) -#define OBCR_b0_after_b1 ((0x3) << 10) +#define OBCR_B0_AND_B1 ((0x0) << 10) +#define OBCR_B0_OR_B1 ((0x1) << 10) +#define OBCR_B1_AFTER_B0 ((0x2) << 10) +#define OBCR_B0_AFTER_B1 ((0x3) << 10) #define OBCR_BP_DISABLED (0x0) #define OBCR_BP_MEM_P (0x1) @@ -1885,17 +1885,17 @@ static int dsp563xx_remove_watchpoint(struct target *target, struct watchpoint * return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } -static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t address, uint32_t memType, +static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t address, uint32_t mem_type, enum watchpoint_rw rw, enum watchpoint_condition cond) { int err = ERROR_OK; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); - bool wasRunning = false; + bool was_running = false; /* Only set breakpoint when halted */ if (target->state != TARGET_HALTED) { dsp563xx_halt(target); - wasRunning = true; + was_running = true; } if (dsp563xx->hardware_breakpoint[0].used) { @@ -1905,8 +1905,8 @@ static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t addres uint32_t obcr_value = 0; if (err == ERROR_OK) { - obcr_value |= OBCR_b0_or_b1; - switch (memType) { + obcr_value |= OBCR_B0_OR_B1; + switch (mem_type) { case MEM_X: obcr_value |= OBCR_BP_MEM_X; break; @@ -1917,7 +1917,7 @@ static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t addres obcr_value |= OBCR_BP_MEM_P; break; default: - LOG_ERROR("Unknown memType parameter (%" PRIu32 ")", memType); + LOG_ERROR("Unknown mem_type parameter (%" PRIu32 ")", mem_type); err = ERROR_TARGET_INVALID; } } @@ -1981,7 +1981,7 @@ static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t addres if (err == ERROR_OK) dsp563xx->hardware_breakpoint[0].used = BPU_WATCHPOINT; - if (err == ERROR_OK && wasRunning) { + if (err == ERROR_OK && was_running) { /* Resume from current PC */ err = dsp563xx_resume(target, 1, 0x0, 0, 0); } diff --git a/src/target/dsp5680xx.c b/src/target/dsp5680xx.c index 62844ea3b..71bf6f184 100644 --- a/src/target/dsp5680xx.c +++ b/src/target/dsp5680xx.c @@ -501,7 +501,7 @@ static int core_move_value_to_pc(struct target *target, uint32_t value) return retval; } -static int eonce_load_TX_RX_to_r0(struct target *target) +static int eonce_load_tx_rx_to_r0(struct target *target) { int retval; @@ -512,7 +512,7 @@ static int eonce_load_TX_RX_to_r0(struct target *target) return retval; } -static int core_load_TX_RX_high_addr_to_r0(struct target *target) +static int core_load_tx_rx_high_addr_to_r0(struct target *target) { int retval = 0; @@ -855,7 +855,7 @@ static int eonce_pc_store(struct target *target) err_check_propagate(retval); retval = core_move_r4_to_y(target); err_check_propagate(retval); - retval = eonce_load_TX_RX_to_r0(target); + retval = eonce_load_tx_rx_to_r0(target); err_check_propagate(retval); retval = core_move_y0_at_r0(target); err_check_propagate(retval); @@ -1110,7 +1110,7 @@ static int dsp5680xx_read_16_single(struct target *t, uint32_t a, else retval = core_move_at_r0_to_y0(target); err_check_propagate(retval); - retval = eonce_load_TX_RX_to_r0(target); + retval = eonce_load_tx_rx_to_r0(target); err_check_propagate(retval); retval = core_move_y0_at_r0(target); err_check_propagate(retval); @@ -1147,7 +1147,7 @@ static int dsp5680xx_read_32_single(struct target *t, uint32_t a, err_check_propagate(retval); } /* Get lower part of data to TX/RX */ - retval = eonce_load_TX_RX_to_r0(target); + retval = eonce_load_tx_rx_to_r0(target); err_check_propagate(retval); retval = core_move_y0_at_r0_inc(target); /* This also load TX/RX high to r0 */ err_check_propagate(retval); @@ -1543,7 +1543,7 @@ static int perl_crc(const uint8_t *buff8, uint32_t word_count) * * @return */ -static int dsp5680xx_f_SIM_reset(struct target *target) +static int dsp5680xx_f_sim_reset(struct target *target) { int retval = ERROR_OK; @@ -1575,7 +1575,7 @@ static int dsp5680xx_soft_reset_halt(struct target *target) retval = dsp5680xx_halt(target); err_check_propagate(retval); - retval = dsp5680xx_f_SIM_reset(target); + retval = dsp5680xx_f_sim_reset(target); err_check_propagate(retval); return retval; } @@ -1617,7 +1617,7 @@ static int dsp5680xx_f_ex(struct target *target, uint16_t c, uint32_t address, u uint32_t command = c; int retval; - retval = core_load_TX_RX_high_addr_to_r0(target); + retval = core_load_tx_rx_high_addr_to_r0(target); err_check_propagate(retval); retval = core_move_long_to_r2(target, HFM_BASE_ADDR); err_check_propagate(retval); @@ -1727,7 +1727,7 @@ static int set_fm_ck_div(struct target *target) retval = core_move_long_to_r2(target, HFM_BASE_ADDR); err_check_propagate(retval); - retval = core_load_TX_RX_high_addr_to_r0(target); + retval = core_load_tx_rx_high_addr_to_r0(target); err_check_propagate(retval); /* read HFM_CLKD */ retval = core_move_at_r2_to_y0(target); @@ -1882,7 +1882,7 @@ int dsp5680xx_f_erase(struct target *target, int first, int last) * Reset SIM * */ - retval = dsp5680xx_f_SIM_reset(target); + retval = dsp5680xx_f_sim_reset(target); err_check_propagate(retval); /* * Set hfmdiv @@ -2014,7 +2014,7 @@ int dsp5680xx_f_wr(struct target *t, const uint8_t *b, uint32_t a, uint32_t coun retval = core_move_long_to_r3(target, address); /* Destination address to r3 */ err_check_propagate(retval); - core_load_TX_RX_high_addr_to_r0(target); /* TX/RX reg address to r0 */ + core_load_tx_rx_high_addr_to_r0(target); /* TX/RX reg address to r0 */ err_check_propagate(retval); retval = core_move_long_to_r2(target, HFM_BASE_ADDR); /* FM base address to r2 */ err_check_propagate(retval); diff --git a/src/target/dsp5680xx.h b/src/target/dsp5680xx.h index 72557cea2..b969417f8 100644 --- a/src/target/dsp5680xx.h +++ b/src/target/dsp5680xx.h @@ -238,7 +238,7 @@ * ---------------------------------------------------------------- */ #define MC568013_SIM_BASE_ADDR 0xF140 -#define MC56803x_2x_SIM_BASE_ADDR 0xF100 +#define MC56803X_2X_SIM_BASE_ADDR 0xF100 #define SIM_CMD_RESET 0x10 /** diff --git a/src/target/esirisc.c b/src/target/esirisc.c index c928445cc..9476b0fb4 100644 --- a/src/target/esirisc.c +++ b/src/target/esirisc.c @@ -56,38 +56,38 @@ static const char * const esirisc_exception_strings[] = { [EID_SYSTEM_CALL] = "SystemCall", [EID_MEMORY_MANAGEMENT] = "MemoryManagement", [EID_UNRECOVERABLE] = "Unrecoverable", - [EID_INTERRUPTn+0] = "Interrupt0", - [EID_INTERRUPTn+1] = "Interrupt1", - [EID_INTERRUPTn+2] = "Interrupt2", - [EID_INTERRUPTn+3] = "Interrupt3", - [EID_INTERRUPTn+4] = "Interrupt4", - [EID_INTERRUPTn+5] = "Interrupt5", - [EID_INTERRUPTn+6] = "Interrupt6", - [EID_INTERRUPTn+7] = "Interrupt7", - [EID_INTERRUPTn+8] = "Interrupt8", - [EID_INTERRUPTn+9] = "Interrupt9", - [EID_INTERRUPTn+10] = "Interrupt10", - [EID_INTERRUPTn+11] = "Interrupt11", - [EID_INTERRUPTn+12] = "Interrupt12", - [EID_INTERRUPTn+13] = "Interrupt13", - [EID_INTERRUPTn+14] = "Interrupt14", - [EID_INTERRUPTn+15] = "Interrupt15", - [EID_INTERRUPTn+16] = "Interrupt16", - [EID_INTERRUPTn+17] = "Interrupt17", - [EID_INTERRUPTn+18] = "Interrupt18", - [EID_INTERRUPTn+19] = "Interrupt19", - [EID_INTERRUPTn+20] = "Interrupt20", - [EID_INTERRUPTn+21] = "Interrupt21", - [EID_INTERRUPTn+22] = "Interrupt22", - [EID_INTERRUPTn+23] = "Interrupt23", - [EID_INTERRUPTn+24] = "Interrupt24", - [EID_INTERRUPTn+25] = "Interrupt25", - [EID_INTERRUPTn+26] = "Interrupt26", - [EID_INTERRUPTn+27] = "Interrupt27", - [EID_INTERRUPTn+28] = "Interrupt28", - [EID_INTERRUPTn+29] = "Interrupt29", - [EID_INTERRUPTn+30] = "Interrupt30", - [EID_INTERRUPTn+31] = "Interrupt31", + [EID_INTERRUPT_N+0] = "Interrupt0", + [EID_INTERRUPT_N+1] = "Interrupt1", + [EID_INTERRUPT_N+2] = "Interrupt2", + [EID_INTERRUPT_N+3] = "Interrupt3", + [EID_INTERRUPT_N+4] = "Interrupt4", + [EID_INTERRUPT_N+5] = "Interrupt5", + [EID_INTERRUPT_N+6] = "Interrupt6", + [EID_INTERRUPT_N+7] = "Interrupt7", + [EID_INTERRUPT_N+8] = "Interrupt8", + [EID_INTERRUPT_N+9] = "Interrupt9", + [EID_INTERRUPT_N+10] = "Interrupt10", + [EID_INTERRUPT_N+11] = "Interrupt11", + [EID_INTERRUPT_N+12] = "Interrupt12", + [EID_INTERRUPT_N+13] = "Interrupt13", + [EID_INTERRUPT_N+14] = "Interrupt14", + [EID_INTERRUPT_N+15] = "Interrupt15", + [EID_INTERRUPT_N+16] = "Interrupt16", + [EID_INTERRUPT_N+17] = "Interrupt17", + [EID_INTERRUPT_N+18] = "Interrupt18", + [EID_INTERRUPT_N+19] = "Interrupt19", + [EID_INTERRUPT_N+20] = "Interrupt20", + [EID_INTERRUPT_N+21] = "Interrupt21", + [EID_INTERRUPT_N+22] = "Interrupt22", + [EID_INTERRUPT_N+23] = "Interrupt23", + [EID_INTERRUPT_N+24] = "Interrupt24", + [EID_INTERRUPT_N+25] = "Interrupt25", + [EID_INTERRUPT_N+26] = "Interrupt26", + [EID_INTERRUPT_N+27] = "Interrupt27", + [EID_INTERRUPT_N+28] = "Interrupt28", + [EID_INTERRUPT_N+29] = "Interrupt29", + [EID_INTERRUPT_N+30] = "Interrupt30", + [EID_INTERRUPT_N+31] = "Interrupt31", }; /* @@ -508,7 +508,7 @@ static int esirisc_add_breakpoint(struct target *target, struct breakpoint *brea esirisc->breakpoints_p[bp_index] = breakpoint; /* specify instruction breakpoint address */ - retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBAn + bp_index, + retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBA_N + bp_index, breakpoint->address); if (retval != ERROR_OK) { LOG_ERROR("%s: failed to write Debug CSR: IBA", target_name(target)); @@ -634,7 +634,7 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc esirisc->watchpoints_p[wp_index] = watchpoint; /* specify data breakpoint address */ - retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBAn + wp_index, + retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBA_N + wp_index, watchpoint->address); if (retval != ERROR_OK) { LOG_ERROR("%s: failed to write Debug CSR: DBA", target_name(target)); diff --git a/src/target/esirisc.h b/src/target/esirisc.h index 57deba616..ad14223ad 100644 --- a/src/target/esirisc.h +++ b/src/target/esirisc.h @@ -47,7 +47,7 @@ #define EID_SYSTEM_CALL 0x0b #define EID_MEMORY_MANAGEMENT 0x0c #define EID_UNRECOVERABLE 0x0d -#define EID_INTERRUPTn 0x20 +#define EID_INTERRUPT_N 0x20 /* Exception Entry Points */ #define ENTRY_RESET 0x00 @@ -58,7 +58,7 @@ #define ENTRY_SYSCALL 0x05 #define ENTRY_DEBUG 0x06 #define ENTRY_NMI 0x07 -#define ENTRY_INTERRUPTn 0x08 +#define ENTRY_INTERRUPT_N 0x08 /* Hardware Debug Control */ #define HWDC_R (1<<4) /* Reset & Hardware Failure */ diff --git a/src/target/esirisc_regs.h b/src/target/esirisc_regs.h index a946a2ecc..6ccda500b 100644 --- a/src/target/esirisc_regs.h +++ b/src/target/esirisc_regs.h @@ -148,8 +148,8 @@ enum esirisc_reg_num { #define CSR_DEBUG_HWDC 0x03 /* Hardware Debug Control */ #define CSR_DEBUG_DBS 0x04 /* Data Breakpoint Size */ #define CSR_DEBUG_DBR 0x05 /* Data Breakpoint Range */ -#define CSR_DEBUG_IBAn 0x08 /* Instruction Breakpoint Address [0..7] */ -#define CSR_DEBUG_DBAn 0x10 /* Data Breakpoint Address [0..7] */ +#define CSR_DEBUG_IBA_N 0x08 /* Instruction Breakpoint Address [0..7] */ +#define CSR_DEBUG_DBA_N 0x10 /* Data Breakpoint Address [0..7] */ /* Configuration CSRs */ #define CSR_CONFIG_ARCH0 0x00 /* Architectural Configuration 0 */ @@ -160,12 +160,12 @@ enum esirisc_reg_num { #define CSR_CONFIG_IC 0x05 /* Instruction Cache Configuration */ #define CSR_CONFIG_DC 0x06 /* Data Cache Configuration */ #define CSR_CONFIG_INT 0x07 /* Interrupt Configuration */ -#define CSR_CONFIG_ISAn 0x08 /* Instruction Set Configuration [0..6] */ +#define CSR_CONFIG_ISA_N 0x08 /* Instruction Set Configuration [0..6] */ #define CSR_CONFIG_DBG 0x0f /* Debug Configuration */ #define CSR_CONFIG_MID 0x10 /* Manufacturer ID */ #define CSR_CONFIG_REV 0x11 /* Revision Number */ #define CSR_CONFIG_MPID 0x12 /* Multiprocessor ID */ -#define CSR_CONFIG_FREQn 0x13 /* Frequency [0..2] */ +#define CSR_CONFIG_FREQ_N 0x13 /* Frequency [0..2] */ #define CSR_CONFIG_TRACE 0x16 /* Trace Configuration */ /* Trace CSRs */ diff --git a/src/target/image.c b/src/target/image.c index 8f72329bd..df07ea3ef 100644 --- a/src/target/image.c +++ b/src/target/image.c @@ -123,7 +123,7 @@ static int identify_image_type(struct image *image, const char *type_string, con } static int image_ihex_buffer_complete_inner(struct image *image, - char *lpszLine, + char *lpsz_line, struct imagesection *section) { struct image_ihex *ihex = image->type_private; @@ -152,7 +152,7 @@ static int image_ihex_buffer_complete_inner(struct image *image, section[image->num_sections].size = 0x0; section[image->num_sections].flags = 0; - while (fileio_fgets(fileio, 1023, lpszLine) == ERROR_OK) { + while (fileio_fgets(fileio, 1023, lpsz_line) == ERROR_OK) { uint32_t count; uint32_t address; uint32_t record_type; @@ -161,10 +161,10 @@ static int image_ihex_buffer_complete_inner(struct image *image, size_t bytes_read = 0; /* skip comments and blank lines */ - if ((lpszLine[0] == '#') || (strlen(lpszLine + strspn(lpszLine, "\n\t\r ")) == 0)) + if ((lpsz_line[0] == '#') || (strlen(lpsz_line + strspn(lpsz_line, "\n\t\r ")) == 0)) continue; - if (sscanf(&lpszLine[bytes_read], ":%2" SCNx32 "%4" SCNx32 "%2" SCNx32, &count, + if (sscanf(&lpsz_line[bytes_read], ":%2" SCNx32 "%4" SCNx32 "%2" SCNx32, &count, &address, &record_type) != 3) return ERROR_IMAGE_FORMAT_ERROR; bytes_read += 9; @@ -199,7 +199,7 @@ static int image_ihex_buffer_complete_inner(struct image *image, while (count-- > 0) { unsigned value; - sscanf(&lpszLine[bytes_read], "%2x", &value); + sscanf(&lpsz_line[bytes_read], "%2x", &value); ihex->buffer[cooked_bytes] = (uint8_t)value; cal_checksum += (uint8_t)ihex->buffer[cooked_bytes]; bytes_read += 2; @@ -225,7 +225,7 @@ static int image_ihex_buffer_complete_inner(struct image *image, } else if (record_type == 2) { /* Linear Address Record */ uint16_t upper_address; - sscanf(&lpszLine[bytes_read], "%4hx", &upper_address); + sscanf(&lpsz_line[bytes_read], "%4hx", &upper_address); cal_checksum += (uint8_t)(upper_address >> 8); cal_checksum += (uint8_t)upper_address; bytes_read += 4; @@ -257,14 +257,14 @@ static int image_ihex_buffer_complete_inner(struct image *image, /* "Start Segment Address Record" will not be supported * but we must consume it, and do not create an error. */ while (count-- > 0) { - sscanf(&lpszLine[bytes_read], "%2" SCNx32, &dummy); + sscanf(&lpsz_line[bytes_read], "%2" SCNx32, &dummy); cal_checksum += (uint8_t)dummy; bytes_read += 2; } } else if (record_type == 4) { /* Extended Linear Address Record */ uint16_t upper_address; - sscanf(&lpszLine[bytes_read], "%4hx", &upper_address); + sscanf(&lpsz_line[bytes_read], "%4hx", &upper_address); cal_checksum += (uint8_t)(upper_address >> 8); cal_checksum += (uint8_t)upper_address; bytes_read += 4; @@ -293,7 +293,7 @@ static int image_ihex_buffer_complete_inner(struct image *image, } else if (record_type == 5) { /* Start Linear Address Record */ uint32_t start_address; - sscanf(&lpszLine[bytes_read], "%8" SCNx32, &start_address); + sscanf(&lpsz_line[bytes_read], "%8" SCNx32, &start_address); cal_checksum += (uint8_t)(start_address >> 24); cal_checksum += (uint8_t)(start_address >> 16); cal_checksum += (uint8_t)(start_address >> 8); @@ -307,7 +307,7 @@ static int image_ihex_buffer_complete_inner(struct image *image, return ERROR_IMAGE_FORMAT_ERROR; } - sscanf(&lpszLine[bytes_read], "%2" SCNx32, &checksum); + sscanf(&lpsz_line[bytes_read], "%2" SCNx32, &checksum); if ((uint8_t)checksum != (uint8_t)(~cal_checksum + 1)) { /* checksum failed */ @@ -317,7 +317,7 @@ static int image_ihex_buffer_complete_inner(struct image *image, if (end_rec) { end_rec = false; - LOG_WARNING("continuing after end-of-file record: %.40s", lpszLine); + LOG_WARNING("continuing after end-of-file record: %.40s", lpsz_line); } } } @@ -336,23 +336,23 @@ static int image_ihex_buffer_complete_inner(struct image *image, */ static int image_ihex_buffer_complete(struct image *image) { - char *lpszLine = malloc(1023); - if (lpszLine == NULL) { + char *lpsz_line = malloc(1023); + if (lpsz_line == NULL) { LOG_ERROR("Out of memory"); return ERROR_FAIL; } struct imagesection *section = malloc(sizeof(struct imagesection) * IMAGE_MAX_SECTIONS); if (section == NULL) { - free(lpszLine); + free(lpsz_line); LOG_ERROR("Out of memory"); return ERROR_FAIL; } int retval; - retval = image_ihex_buffer_complete_inner(image, lpszLine, section); + retval = image_ihex_buffer_complete_inner(image, lpsz_line, section); free(section); - free(lpszLine); + free(lpsz_line); return retval; } @@ -755,7 +755,7 @@ static int image_elf_read_section(struct image *image, } static int image_mot_buffer_complete_inner(struct image *image, - char *lpszLine, + char *lpsz_line, struct imagesection *section) { struct image_mot *mot = image->type_private; @@ -784,7 +784,7 @@ static int image_mot_buffer_complete_inner(struct image *image, section[image->num_sections].size = 0x0; section[image->num_sections].flags = 0; - while (fileio_fgets(fileio, 1023, lpszLine) == ERROR_OK) { + while (fileio_fgets(fileio, 1023, lpsz_line) == ERROR_OK) { uint32_t count; uint32_t address; uint32_t record_type; @@ -793,11 +793,11 @@ static int image_mot_buffer_complete_inner(struct image *image, uint32_t bytes_read = 0; /* skip comments and blank lines */ - if ((lpszLine[0] == '#') || (strlen(lpszLine + strspn(lpszLine, "\n\t\r ")) == 0)) + if ((lpsz_line[0] == '#') || (strlen(lpsz_line + strspn(lpsz_line, "\n\t\r ")) == 0)) continue; /* get record type and record length */ - if (sscanf(&lpszLine[bytes_read], "S%1" SCNx32 "%2" SCNx32, &record_type, + if (sscanf(&lpsz_line[bytes_read], "S%1" SCNx32 "%2" SCNx32, &record_type, &count) != 2) return ERROR_IMAGE_FORMAT_ERROR; @@ -809,18 +809,18 @@ static int image_mot_buffer_complete_inner(struct image *image, if (record_type == 0) { /* S0 - starting record (optional) */ - int iValue; + int value; while (count-- > 0) { - sscanf(&lpszLine[bytes_read], "%2x", &iValue); - cal_checksum += (uint8_t)iValue; + sscanf(&lpsz_line[bytes_read], "%2x", &value); + cal_checksum += (uint8_t)value; bytes_read += 2; } } else if (record_type >= 1 && record_type <= 3) { switch (record_type) { case 1: /* S1 - 16 bit address data record */ - sscanf(&lpszLine[bytes_read], "%4" SCNx32, &address); + sscanf(&lpsz_line[bytes_read], "%4" SCNx32, &address); cal_checksum += (uint8_t)(address >> 8); cal_checksum += (uint8_t)address; bytes_read += 4; @@ -829,7 +829,7 @@ static int image_mot_buffer_complete_inner(struct image *image, case 2: /* S2 - 24 bit address data record */ - sscanf(&lpszLine[bytes_read], "%6" SCNx32, &address); + sscanf(&lpsz_line[bytes_read], "%6" SCNx32, &address); cal_checksum += (uint8_t)(address >> 16); cal_checksum += (uint8_t)(address >> 8); cal_checksum += (uint8_t)address; @@ -839,7 +839,7 @@ static int image_mot_buffer_complete_inner(struct image *image, case 3: /* S3 - 32 bit address data record */ - sscanf(&lpszLine[bytes_read], "%8" SCNx32, &address); + sscanf(&lpsz_line[bytes_read], "%8" SCNx32, &address); cal_checksum += (uint8_t)(address >> 24); cal_checksum += (uint8_t)(address >> 16); cal_checksum += (uint8_t)(address >> 8); @@ -868,7 +868,7 @@ static int image_mot_buffer_complete_inner(struct image *image, while (count-- > 0) { unsigned value; - sscanf(&lpszLine[bytes_read], "%2x", &value); + sscanf(&lpsz_line[bytes_read], "%2x", &value); mot->buffer[cooked_bytes] = (uint8_t)value; cal_checksum += (uint8_t)mot->buffer[cooked_bytes]; bytes_read += 2; @@ -881,7 +881,7 @@ static int image_mot_buffer_complete_inner(struct image *image, uint32_t dummy; while (count-- > 0) { - sscanf(&lpszLine[bytes_read], "%2" SCNx32, &dummy); + sscanf(&lpsz_line[bytes_read], "%2" SCNx32, &dummy); cal_checksum += (uint8_t)dummy; bytes_read += 2; } @@ -906,7 +906,7 @@ static int image_mot_buffer_complete_inner(struct image *image, } /* account for checksum, will always be 0xFF */ - sscanf(&lpszLine[bytes_read], "%2" SCNx32, &checksum); + sscanf(&lpsz_line[bytes_read], "%2" SCNx32, &checksum); cal_checksum += (uint8_t)checksum; if (cal_checksum != 0xFF) { @@ -917,7 +917,7 @@ static int image_mot_buffer_complete_inner(struct image *image, if (end_rec) { end_rec = false; - LOG_WARNING("continuing after end-of-file record: %.40s", lpszLine); + LOG_WARNING("continuing after end-of-file record: %.40s", lpsz_line); } } } @@ -936,23 +936,23 @@ static int image_mot_buffer_complete_inner(struct image *image, */ static int image_mot_buffer_complete(struct image *image) { - char *lpszLine = malloc(1023); - if (lpszLine == NULL) { + char *lpsz_line = malloc(1023); + if (lpsz_line == NULL) { LOG_ERROR("Out of memory"); return ERROR_FAIL; } struct imagesection *section = malloc(sizeof(struct imagesection) * IMAGE_MAX_SECTIONS); if (section == NULL) { - free(lpszLine); + free(lpsz_line); LOG_ERROR("Out of memory"); return ERROR_FAIL; } int retval; - retval = image_mot_buffer_complete_inner(image, lpszLine, section); + retval = image_mot_buffer_complete_inner(image, lpsz_line, section); free(section); - free(lpszLine); + free(lpsz_line); return retval; } diff --git a/src/target/target.c b/src/target/target.c index 7dbcadba6..4d2c6465d 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -2884,57 +2884,57 @@ COMMAND_HANDLER(handle_targets_command) /* every 300ms we check for reset & powerdropout and issue a "reset halt" if so. */ -static int powerDropout; -static int srstAsserted; +static int power_dropout; +static int srst_asserted; -static int runPowerRestore; -static int runPowerDropout; -static int runSrstAsserted; -static int runSrstDeasserted; +static int run_power_restore; +static int run_power_dropout; +static int run_srst_asserted; +static int run_srst_deasserted; static int sense_handler(void) { - static int prevSrstAsserted; - static int prevPowerdropout; + static int prev_srst_asserted; + static int prev_power_dropout; - int retval = jtag_power_dropout(&powerDropout); + int retval = jtag_power_dropout(&power_dropout); if (retval != ERROR_OK) return retval; - int powerRestored; - powerRestored = prevPowerdropout && !powerDropout; - if (powerRestored) - runPowerRestore = 1; + int power_restored; + power_restored = prev_power_dropout && !power_dropout; + if (power_restored) + run_power_restore = 1; int64_t current = timeval_ms(); - static int64_t lastPower; - bool waitMore = lastPower + 2000 > current; - if (powerDropout && !waitMore) { - runPowerDropout = 1; - lastPower = current; + static int64_t last_power; + bool wait_more = last_power + 2000 > current; + if (power_dropout && !wait_more) { + run_power_dropout = 1; + last_power = current; } - retval = jtag_srst_asserted(&srstAsserted); + retval = jtag_srst_asserted(&srst_asserted); if (retval != ERROR_OK) return retval; - int srstDeasserted; - srstDeasserted = prevSrstAsserted && !srstAsserted; + int srst_deasserted; + srst_deasserted = prev_srst_asserted && !srst_asserted; - static int64_t lastSrst; - waitMore = lastSrst + 2000 > current; - if (srstDeasserted && !waitMore) { - runSrstDeasserted = 1; - lastSrst = current; + static int64_t last_srst; + wait_more = last_srst + 2000 > current; + if (srst_deasserted && !wait_more) { + run_srst_deasserted = 1; + last_srst = current; } - if (!prevSrstAsserted && srstAsserted) - runSrstAsserted = 1; + if (!prev_srst_asserted && srst_asserted) + run_srst_asserted = 1; - prevSrstAsserted = srstAsserted; - prevPowerdropout = powerDropout; + prev_srst_asserted = srst_asserted; + prev_power_dropout = power_dropout; - if (srstDeasserted || powerRestored) { + if (srst_deasserted || power_restored) { /* Other than logging the event we can't do anything here. * Issuing a reset is a particularly bad idea as we might * be inside a reset already. @@ -2965,21 +2965,21 @@ static int handle_target(void *priv) * clearing the flags after running these events. */ int did_something = 0; - if (runSrstAsserted) { + if (run_srst_asserted) { LOG_INFO("srst asserted detected, running srst_asserted proc."); Jim_Eval(interp, "srst_asserted"); did_something = 1; } - if (runSrstDeasserted) { + if (run_srst_deasserted) { Jim_Eval(interp, "srst_deasserted"); did_something = 1; } - if (runPowerDropout) { + if (run_power_dropout) { LOG_INFO("Power dropout detected, running power_dropout proc."); Jim_Eval(interp, "power_dropout"); did_something = 1; } - if (runPowerRestore) { + if (run_power_restore) { Jim_Eval(interp, "power_restore"); did_something = 1; } @@ -2991,10 +2991,10 @@ static int handle_target(void *priv) /* clear action flags */ - runSrstAsserted = 0; - runSrstDeasserted = 0; - runPowerRestore = 0; - runPowerDropout = 0; + run_srst_asserted = 0; + run_srst_deasserted = 0; + run_power_restore = 0; + run_power_dropout = 0; recursive = 0; } @@ -3020,7 +3020,7 @@ static int handle_target(void *priv) target->backoff.count = 0; /* only poll target if we've got power and srst isn't asserted */ - if (!powerDropout && !srstAsserted) { + if (!power_dropout && !srst_asserted) { /* polling may fail silently until the target has been examined */ retval = target_poll(target); if (retval != ERROR_OK) { @@ -3596,7 +3596,7 @@ COMMAND_HANDLER(handle_mw_command) return target_fill_mem(target, address, fn, wordsize, value, count); } -static COMMAND_HELPER(parse_load_image_command_CMD_ARGV, struct image *image, +static COMMAND_HELPER(parse_load_image_command, struct image *image, target_addr_t *min_address, target_addr_t *max_address) { if (CMD_ARGC < 1 || CMD_ARGC > 5) @@ -3637,7 +3637,7 @@ COMMAND_HANDLER(handle_load_image_command) target_addr_t max_address = -1; struct image image; - int retval = CALL_COMMAND_HANDLER(parse_load_image_command_CMD_ARGV, + int retval = CALL_COMMAND_HANDLER(parse_load_image_command, &image, &min_address, &max_address); if (retval != ERROR_OK) return retval; @@ -4166,44 +4166,44 @@ COMMAND_HANDLER(handle_virt2phys_command) return retval; } -static void writeData(FILE *f, const void *data, size_t len) +static void write_data(FILE *f, const void *data, size_t len) { size_t written = fwrite(data, 1, len, f); if (written != len) LOG_ERROR("failed to write %zu bytes: %s", len, strerror(errno)); } -static void writeLong(FILE *f, int l, struct target *target) +static void write_long(FILE *f, int l, struct target *target) { uint8_t val[4]; target_buffer_set_u32(target, val, l); - writeData(f, val, 4); + write_data(f, val, 4); } -static void writeString(FILE *f, char *s) +static void write_string(FILE *f, char *s) { - writeData(f, s, strlen(s)); + write_data(f, s, strlen(s)); } typedef unsigned char UNIT[2]; /* unit of profiling */ /* Dump a gmon.out histogram file. */ -static void write_gmon(uint32_t *samples, uint32_t sampleNum, const char *filename, bool with_range, +static void write_gmon(uint32_t *samples, uint32_t sample_num, const char *filename, bool with_range, uint32_t start_address, uint32_t end_address, struct target *target, uint32_t duration_ms) { uint32_t i; FILE *f = fopen(filename, "w"); if (f == NULL) return; - writeString(f, "gmon"); - writeLong(f, 0x00000001, target); /* Version */ - writeLong(f, 0, target); /* padding */ - writeLong(f, 0, target); /* padding */ - writeLong(f, 0, target); /* padding */ + write_string(f, "gmon"); + write_long(f, 0x00000001, target); /* Version */ + write_long(f, 0, target); /* padding */ + write_long(f, 0, target); /* padding */ + write_long(f, 0, target); /* padding */ uint8_t zero = 0; /* GMON_TAG_TIME_HIST */ - writeData(f, &zero, 1); + write_data(f, &zero, 1); /* figure out bucket size */ uint32_t min; @@ -4214,7 +4214,7 @@ static void write_gmon(uint32_t *samples, uint32_t sampleNum, const char *filena } else { min = samples[0]; max = samples[0]; - for (i = 0; i < sampleNum; i++) { + for (i = 0; i < sample_num; i++) { if (min > samples[i]) min = samples[i]; if (max < samples[i]) @@ -4226,50 +4226,50 @@ static void write_gmon(uint32_t *samples, uint32_t sampleNum, const char *filena max++; } - int addressSpace = max - min; - assert(addressSpace >= 2); + int address_space = max - min; + assert(address_space >= 2); /* FIXME: What is the reasonable number of buckets? * The profiling result will be more accurate if there are enough buckets. */ - static const uint32_t maxBuckets = 128 * 1024; /* maximum buckets. */ - uint32_t numBuckets = addressSpace / sizeof(UNIT); - if (numBuckets > maxBuckets) - numBuckets = maxBuckets; - int *buckets = malloc(sizeof(int) * numBuckets); + static const uint32_t max_buckets = 128 * 1024; /* maximum buckets. */ + uint32_t num_buckets = address_space / sizeof(UNIT); + if (num_buckets > max_buckets) + num_buckets = max_buckets; + int *buckets = malloc(sizeof(int) * num_buckets); if (buckets == NULL) { fclose(f); return; } - memset(buckets, 0, sizeof(int) * numBuckets); - for (i = 0; i < sampleNum; i++) { + memset(buckets, 0, sizeof(int) * num_buckets); + for (i = 0; i < sample_num; i++) { uint32_t address = samples[i]; if ((address < min) || (max <= address)) continue; long long a = address - min; - long long b = numBuckets; - long long c = addressSpace; + long long b = num_buckets; + long long c = address_space; int index_t = (a * b) / c; /* danger!!!! int32 overflows */ buckets[index_t]++; } /* append binary memory gmon.out &profile_hist_hdr ((char*)&profile_hist_hdr + sizeof(struct gmon_hist_hdr)) */ - writeLong(f, min, target); /* low_pc */ - writeLong(f, max, target); /* high_pc */ - writeLong(f, numBuckets, target); /* # of buckets */ - float sample_rate = sampleNum / (duration_ms / 1000.0); - writeLong(f, sample_rate, target); - writeString(f, "seconds"); + write_long(f, min, target); /* low_pc */ + write_long(f, max, target); /* high_pc */ + write_long(f, num_buckets, target); /* # of buckets */ + float sample_rate = sample_num / (duration_ms / 1000.0); + write_long(f, sample_rate, target); + write_string(f, "seconds"); for (i = 0; i < (15-strlen("seconds")); i++) - writeData(f, &zero, 1); - writeString(f, "s"); + write_data(f, &zero, 1); + write_string(f, "s"); /*append binary memory gmon.out profile_hist_data (profile_hist_data + profile_hist_hdr.hist_size) */ - char *data = malloc(2 * numBuckets); + char *data = malloc(2 * num_buckets); if (data != NULL) { - for (i = 0; i < numBuckets; i++) { + for (i = 0; i < num_buckets; i++) { int val; val = buckets[i]; if (val > 65535) @@ -4278,7 +4278,7 @@ static void write_gmon(uint32_t *samples, uint32_t sampleNum, const char *filena data[i * 2 + 1] = (val >> 8) & 0xff; } free(buckets); - writeData(f, data, numBuckets * 2); + write_data(f, data, num_buckets * 2); free(data); } else free(buckets); @@ -4375,26 +4375,26 @@ COMMAND_HANDLER(handle_profile_command) static int new_u64_array_element(Jim_Interp *interp, const char *varname, int idx, uint64_t val) { char *namebuf; - Jim_Obj *nameObjPtr, *valObjPtr; + Jim_Obj *obj_name, *obj_val; int result; namebuf = alloc_printf("%s(%d)", varname, idx); if (!namebuf) return JIM_ERR; - nameObjPtr = Jim_NewStringObj(interp, namebuf, -1); + obj_name = Jim_NewStringObj(interp, namebuf, -1); jim_wide wide_val = val; - valObjPtr = Jim_NewWideObj(interp, wide_val); - if (!nameObjPtr || !valObjPtr) { + obj_val = Jim_NewWideObj(interp, wide_val); + if (!obj_name || !obj_val) { free(namebuf); return JIM_ERR; } - Jim_IncrRefCount(nameObjPtr); - Jim_IncrRefCount(valObjPtr); - result = Jim_SetVariable(interp, nameObjPtr, valObjPtr); - Jim_DecrRefCount(interp, nameObjPtr); - Jim_DecrRefCount(interp, valObjPtr); + Jim_IncrRefCount(obj_name); + Jim_IncrRefCount(obj_val); + result = Jim_SetVariable(interp, obj_name, obj_val); + Jim_DecrRefCount(interp, obj_name); + Jim_DecrRefCount(interp, obj_val); free(namebuf); /* printf("%s(%d) <= 0%08x\n", varname, idx, val); */ return result; @@ -4579,21 +4579,21 @@ static int get_u64_array_element(Jim_Interp *interp, const char *varname, size_t if (!namebuf) return JIM_ERR; - Jim_Obj *nameObjPtr = Jim_NewStringObj(interp, namebuf, -1); - if (!nameObjPtr) { + Jim_Obj *obj_name = Jim_NewStringObj(interp, namebuf, -1); + if (!obj_name) { free(namebuf); return JIM_ERR; } - Jim_IncrRefCount(nameObjPtr); - Jim_Obj *valObjPtr = Jim_GetVariable(interp, nameObjPtr, JIM_ERRMSG); - Jim_DecrRefCount(interp, nameObjPtr); + Jim_IncrRefCount(obj_name); + Jim_Obj *obj_val = Jim_GetVariable(interp, obj_name, JIM_ERRMSG); + Jim_DecrRefCount(interp, obj_name); free(namebuf); - if (valObjPtr == NULL) + if (obj_val == NULL) return JIM_ERR; jim_wide wide_val; - int result = Jim_GetWide(interp, valObjPtr, &wide_val); + int result = Jim_GetWide(interp, obj_val, &wide_val); *val = wide_val; return result; } @@ -5456,11 +5456,11 @@ static int jim_target_wait_state(Jim_Interp *interp, int argc, Jim_Obj *const *a e = target_wait_state(target, n->value, a); if (e != ERROR_OK) { - Jim_Obj *eObj = Jim_NewIntObj(interp, e); + Jim_Obj *obj = Jim_NewIntObj(interp, e); Jim_SetResultFormatted(goi.interp, "target: %s wait %s fails (%#s) %s", target_name(target), n->name, - eObj, target_strerror_safe(e)); + obj, target_strerror_safe(e)); return JIM_ERR; } return JIM_OK; @@ -6069,7 +6069,7 @@ static const struct command_registration target_subcommand_handlers[] = { COMMAND_REGISTRATION_DONE }; -struct FastLoad { +struct fast_load { target_addr_t address; uint8_t *data; int length; @@ -6077,7 +6077,7 @@ struct FastLoad { }; static int fastload_num; -static struct FastLoad *fastload; +static struct fast_load *fastload; static void free_fastload(void) { @@ -6099,7 +6099,7 @@ COMMAND_HANDLER(handle_fast_load_image_command) struct image image; - int retval = CALL_COMMAND_HANDLER(parse_load_image_command_CMD_ARGV, + int retval = CALL_COMMAND_HANDLER(parse_load_image_command, &image, &min_address, &max_address); if (retval != ERROR_OK) return retval; @@ -6114,13 +6114,13 @@ COMMAND_HANDLER(handle_fast_load_image_command) image_size = 0x0; retval = ERROR_OK; fastload_num = image.num_sections; - fastload = malloc(sizeof(struct FastLoad)*image.num_sections); + fastload = malloc(sizeof(struct fast_load)*image.num_sections); if (fastload == NULL) { command_print(CMD, "out of memory"); image_close(&image); return ERROR_FAIL; } - memset(fastload, 0, sizeof(struct FastLoad)*image.num_sections); + memset(fastload, 0, sizeof(struct fast_load)*image.num_sections); for (unsigned int i = 0; i < image.num_sections; i++) { buffer = malloc(image.sections[i].size); if (buffer == NULL) { diff --git a/src/target/x86_32_common.c b/src/target/x86_32_common.c index d0b0e37e3..b7dff2361 100644 --- a/src/target/x86_32_common.c +++ b/src/target/x86_32_common.c @@ -472,10 +472,10 @@ int calcaddr_physfromlin(struct target *t, target_addr_t addr, target_addr_t *ph } uint32_t cr4 = buf_get_u32(x86_32->cache->reg_list[CR4].value, 0, 32); - bool isPAE = cr4 & 0x00000020; /* PAE - Physical Address Extension */ + bool is_pae = cr4 & 0x00000020; /* PAE - Physical Address Extension */ uint32_t cr3 = buf_get_u32(x86_32->cache->reg_list[CR3].value, 0, 32); - if (isPAE) { + if (is_pae) { uint32_t pdpt_base = cr3 & 0xFFFFF000; /* lower 12 bits of CR3 must always be 0 */ uint32_t pdpt_index = (addr & 0xC0000000) >> 30; /* A[31:30] index to PDPT */ uint32_t pdpt_addr = pdpt_base + (8 * pdpt_index); ----------------------------------------------------------------------- Summary of changes: src/target/avr32_ap7k.c | 2 +- src/target/avr32_ap7k.h | 2 +- src/target/dsp563xx.c | 22 ++--- src/target/dsp5680xx.c | 22 ++--- src/target/dsp5680xx.h | 2 +- src/target/esirisc.c | 68 +++++++-------- src/target/esirisc.h | 4 +- src/target/esirisc_regs.h | 8 +- src/target/image.c | 70 ++++++++-------- src/target/target.c | 200 ++++++++++++++++++++++----------------------- src/target/x86_32_common.c | 4 +- 11 files changed, 202 insertions(+), 202 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-20 13:57:10
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 20b29b7767097f999fe2eb4f7fb6c2917e9f66a6 (commit) via 28c24a5c41c47a66e9310912f88148814f730a25 (commit) from bba48b057cdc4f26721e06a5310652dcf0e55873 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 20b29b7767097f999fe2eb4f7fb6c2917e9f66a6 Author: Antonio Borneo <bor...@gm...> Date: Sat Jul 3 18:18:57 2021 +0200 openocd: manually fix Yoda conditions Fix the remaining Yoda conditions, detected by checkpatch but not fixed automatically. While there, apply minor style changes. Change-Id: I6e1978b89c4d56a20aceaeb2b52968eb6384432a Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6356 Tested-by: jenkins Reviewed-by: Oleksij Rempel <li...@re...> Reviewed-by: Xiang W <wx...@12...> diff --git a/src/flash/nand/at91sam9.c b/src/flash/nand/at91sam9.c index 4341935fe..c8886d17a 100644 --- a/src/flash/nand/at91sam9.c +++ b/src/flash/nand/at91sam9.c @@ -383,7 +383,7 @@ static int at91sam9_read_page(struct nand_device *nand, uint32_t page, oob_data = at91sam9_oob_init(nand, oob, &oob_size); retval = nand_read_data_page(nand, oob_data, oob_size); - if (ERROR_OK == retval && data) { + if (retval == ERROR_OK && data) { target_read_u32(target, info->ecc + AT91C_ECCX_SR, &status); if (status & 1) { LOG_ERROR("Error detected!"); diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c index 15ca29628..4a7c1cdab 100644 --- a/src/flash/nor/at91sam3.c +++ b/src/flash/nor/at91sam3.c @@ -3626,7 +3626,7 @@ COMMAND_HANDLER(sam3_handle_gpnvm_command) who = -1; break; case 2: - if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all"))) + if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) who = -1; else { uint32_t v32; @@ -3636,7 +3636,7 @@ COMMAND_HANDLER(sam3_handle_gpnvm_command) break; } - if (0 == strcmp("show", CMD_ARGV[0])) { + if (strcmp("show", CMD_ARGV[0]) == 0) { if (who == -1) { showall: r = ERROR_OK; @@ -3664,10 +3664,10 @@ showall: return ERROR_COMMAND_SYNTAX_ERROR; } - if (0 == strcmp("set", CMD_ARGV[0])) + if (strcmp("set", CMD_ARGV[0]) == 0) r = flashd_set_gpnvm(&(chip->details.bank[0]), who); - else if ((0 == strcmp("clr", CMD_ARGV[0])) || - (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */ + else if ((strcmp("clr", CMD_ARGV[0]) == 0) || + (strcmp("clear", CMD_ARGV[0]) == 0)) /* quietly accept both */ r = flashd_clr_gpnvm(&(chip->details.bank[0]), who); else { command_print(CMD, "Unknown command: %s", CMD_ARGV[0]); diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c index b45cf071d..958ec5ec0 100644 --- a/src/flash/nor/at91sam4.c +++ b/src/flash/nor/at91sam4.c @@ -3173,7 +3173,7 @@ COMMAND_HANDLER(sam4_handle_gpnvm_command) who = -1; break; case 2: - if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all"))) + if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) who = -1; else { uint32_t v32; @@ -3183,7 +3183,7 @@ COMMAND_HANDLER(sam4_handle_gpnvm_command) break; } - if (0 == strcmp("show", CMD_ARGV[0])) { + if (strcmp("show", CMD_ARGV[0]) == 0) { if (who == -1) { showall: r = ERROR_OK; @@ -3211,10 +3211,10 @@ showall: return ERROR_COMMAND_SYNTAX_ERROR; } - if (0 == strcmp("set", CMD_ARGV[0])) + if (strcmp("set", CMD_ARGV[0]) == 0) r = flashd_set_gpnvm(&(chip->details.bank[0]), who); - else if ((0 == strcmp("clr", CMD_ARGV[0])) || - (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */ + else if ((strcmp("clr", CMD_ARGV[0]) == 0) || + (strcmp("clear", CMD_ARGV[0]) == 0)) /* quietly accept both */ r = flashd_clr_gpnvm(&(chip->details.bank[0]), who); else { command_print(CMD, "Unknown command: %s", CMD_ARGV[0]); diff --git a/src/flash/nor/max32xxx.c b/src/flash/nor/max32xxx.c index a1bb668eb..1327da6e1 100644 --- a/src/flash/nor/max32xxx.c +++ b/src/flash/nor/max32xxx.c @@ -801,7 +801,7 @@ COMMAND_HANDLER(max32xxx_handle_protection_set_command) info = bank->driver_priv; /* Convert the range to the page numbers */ - if (1 != sscanf(CMD_ARGV[1], "0x%"SCNx32, &addr)) { + if (sscanf(CMD_ARGV[1], "0x%"SCNx32, &addr) != 1) { LOG_WARNING("Error parsing address"); command_print(CMD, "max32xxx protection_set <bank> <addr> <size>"); return ERROR_FAIL; @@ -809,7 +809,7 @@ COMMAND_HANDLER(max32xxx_handle_protection_set_command) /* Mask off the top portion on the address */ addr = (addr & 0x0FFFFFFF); - if (1 != sscanf(CMD_ARGV[2], "0x%"SCNx32, &len)) { + if (sscanf(CMD_ARGV[2], "0x%"SCNx32, &len) != 1) { LOG_WARNING("Error parsing length"); command_print(CMD, "max32xxx protection_set <bank> <addr> <size>"); return ERROR_FAIL; @@ -857,7 +857,7 @@ COMMAND_HANDLER(max32xxx_handle_protection_clr_command) info = bank->driver_priv; /* Convert the range to the page numbers */ - if (1 != sscanf(CMD_ARGV[1], "0x%"SCNx32, &addr)) { + if (sscanf(CMD_ARGV[1], "0x%"SCNx32, &addr) != 1) { LOG_WARNING("Error parsing address"); command_print(CMD, "max32xxx protection_clr <bank> <addr> <size>"); return ERROR_FAIL; @@ -865,7 +865,7 @@ COMMAND_HANDLER(max32xxx_handle_protection_clr_command) /* Mask off the top portion on the address */ addr = (addr & 0x0FFFFFFF); - if (1 != sscanf(CMD_ARGV[2], "0x%"SCNx32, &len)) { + if (sscanf(CMD_ARGV[2], "0x%"SCNx32, &len) != 1) { LOG_WARNING("Error parsing length"); command_print(CMD, "max32xxx protection_clr <bank> <addr> <size>"); return ERROR_FAIL; diff --git a/src/flash/nor/msp432.c b/src/flash/nor/msp432.c index b418bf152..81c94b6db 100644 --- a/src/flash/nor/msp432.c +++ b/src/flash/nor/msp432.c @@ -315,8 +315,8 @@ static int msp432_init(struct flash_bank *bank) } /* Issue warnings if this is a device we may not be able to flash */ - if (MSP432P401X_GUESS == msp432_bank->device_type || - MSP432P411X_GUESS == msp432_bank->device_type) { + if (msp432_bank->device_type == MSP432P401X_GUESS || + msp432_bank->device_type == MSP432P411X_GUESS) { /* Explicit device type check failed. Report this. */ LOG_WARNING( "msp432: Unrecognized MSP432P4 Device ID and Hardware " @@ -489,9 +489,9 @@ COMMAND_HANDLER(msp432_mass_erase_command) all = false; } else if (2 == CMD_ARGC) { /* Check argument for how much to erase */ - if (0 == strcmp(CMD_ARGV[1], "main")) + if (strcmp(CMD_ARGV[1], "main") == 0) all = false; - else if (0 == strcmp(CMD_ARGV[1], "all")) + else if (strcmp(CMD_ARGV[1], "all") == 0) all = true; else return ERROR_COMMAND_SYNTAX_ERROR; @@ -543,9 +543,9 @@ COMMAND_HANDLER(msp432_bsl_command) } if (2 == CMD_ARGC) { - if (0 == strcmp(CMD_ARGV[1], "lock")) + if (strcmp(CMD_ARGV[1], "lock") == 0) msp432_bank->unlock_bsl = false; - else if (0 == strcmp(CMD_ARGV[1], "unlock")) + else if (strcmp(CMD_ARGV[1], "unlock") == 0) msp432_bank->unlock_bsl = true; else return ERROR_COMMAND_SYNTAX_ERROR; @@ -597,8 +597,8 @@ static int msp432_erase(struct flash_bank *bank, unsigned int first, struct msp432_bank *msp432_bank = bank->driver_priv; struct msp432_algo_params algo_params; - bool is_main = FLASH_BASE == bank->base; - bool is_info = P4_FLASH_INFO_BASE == bank->base; + bool is_main = bank->base == FLASH_BASE; + bool is_info = bank->base == P4_FLASH_INFO_BASE; int retval; @@ -676,7 +676,7 @@ static int msp432_write(struct flash_bank *bank, const uint8_t *buffer, long long start_ms; long long elapsed_ms; - bool is_info = P4_FLASH_INFO_BASE == bank->base; + bool is_info = bank->base == P4_FLASH_INFO_BASE; int retval; @@ -812,8 +812,8 @@ static int msp432_probe(struct flash_bank *bank) uint32_t size; unsigned int num_sectors; - bool is_main = FLASH_BASE == bank->base; - bool is_info = P4_FLASH_INFO_BASE == bank->base; + bool is_main = bank->base == FLASH_BASE; + bool is_info = bank->base == P4_FLASH_INFO_BASE; int retval; @@ -960,8 +960,8 @@ static int msp432_auto_probe(struct flash_bank *bank) { struct msp432_bank *msp432_bank = bank->driver_priv; - bool is_main = FLASH_BASE == bank->base; - bool is_info = P4_FLASH_INFO_BASE == bank->base; + bool is_main = bank->base == FLASH_BASE; + bool is_info = bank->base == P4_FLASH_INFO_BASE; int retval = ERROR_OK; @@ -1030,7 +1030,7 @@ static int msp432_protect_check(struct flash_bank *bank) static void msp432_flash_free_driver_priv(struct flash_bank *bank) { - bool is_main = FLASH_BASE == bank->base; + bool is_main = bank->base == FLASH_BASE; /* A single private struct is shared between main and info banks */ /* Only free it on the call for main bank */ diff --git a/src/flash/nor/tms470.c b/src/flash/nor/tms470.c index f1eba9cd3..50783148b 100644 --- a/src/flash/nor/tms470.c +++ b/src/flash/nor/tms470.c @@ -296,9 +296,9 @@ COMMAND_HANDLER(tms470_handle_flash_keyset_command) int i; for (i = 0; i < 4; i++) { - int start = (0 == strncmp(CMD_ARGV[i], "0x", 2)) ? 2 : 0; + int start = (strncmp(CMD_ARGV[i], "0x", 2) == 0) ? 2 : 0; - if (1 != sscanf(&CMD_ARGV[i][start], "%" SCNx32 "", &flash_keys[i])) { + if (sscanf(&CMD_ARGV[i][start], "%" SCNx32 "", &flash_keys[i]) != 1) { command_print(CMD, "could not process flash key %s", CMD_ARGV[i]); LOG_ERROR("could not process flash key %s", CMD_ARGV[i]); diff --git a/src/helper/fileio.c b/src/helper/fileio.c index 5138fa180..d544b8544 100644 --- a/src/helper/fileio.c +++ b/src/helper/fileio.c @@ -198,7 +198,7 @@ int fileio_read_u32(struct fileio *fileio, uint32_t *data) retval = fileio_local_read(fileio, sizeof(uint32_t), buf, &size_read); - if (ERROR_OK == retval && sizeof(uint32_t) != size_read) + if (retval == ERROR_OK && sizeof(uint32_t) != size_read) retval = -EIO; if (retval == ERROR_OK) *data = be_to_h_u32(buf); @@ -252,7 +252,7 @@ int fileio_write_u32(struct fileio *fileio, uint32_t data) retval = fileio_write(fileio, 4, buf, &size_written); - if (ERROR_OK == retval && size_written != sizeof(uint32_t)) + if (retval == ERROR_OK && size_written != sizeof(uint32_t)) retval = -EIO; return retval; diff --git a/src/helper/log.c b/src/helper/log.c index 785a8bded..b39cb9136 100644 --- a/src/helper/log.c +++ b/src/helper/log.c @@ -290,7 +290,7 @@ void log_init(void) if (NULL != debug_env) { int value; int retval = parse_int(debug_env, &value); - if (ERROR_OK == retval && + if (retval == ERROR_OK && debug_level >= LOG_LVL_SILENT && debug_level <= LOG_LVL_DEBUG_IO) debug_level = value; diff --git a/src/jtag/aice/aice_usb.c b/src/jtag/aice/aice_usb.c index 1c90b476c..f0bb6ccae 100644 --- a/src/jtag/aice/aice_usb.c +++ b/src/jtag/aice/aice_usb.c @@ -1929,12 +1929,12 @@ static int aice_read_reg(uint32_t coreid, uint32_t num, uint32_t *val) instructions[2] = DSB; instructions[3] = BEQ_MINUS_12; } else { - if (FS0 <= num && num <= FS31) { /* single precision */ + if (num >= FS0 && num <= FS31) { /* single precision */ instructions[0] = FMFSR(0, nds32_reg_sr_index(num)); instructions[1] = MTSR_DTR(0); instructions[2] = DSB; instructions[3] = BEQ_MINUS_12; - } else if (FD0 <= num && num <= FD31) { /* double precision */ + } else if (num >= FD0 && num <= FD31) { /* double precision */ instructions[0] = FMFDR(0, nds32_reg_sr_index(num)); instructions[1] = MTSR_DTR(0); instructions[2] = DSB; @@ -2035,12 +2035,12 @@ static int aice_write_reg(uint32_t coreid, uint32_t num, uint32_t val) } else if (num == FPCFG) { /* FPCFG is readonly */ } else { - if (FS0 <= num && num <= FS31) { /* single precision */ + if (num >= FS0 && num <= FS31) { /* single precision */ instructions[0] = MFSR_DTR(0); instructions[1] = FMTSR(0, nds32_reg_sr_index(num)); instructions[2] = DSB; instructions[3] = BEQ_MINUS_12; - } else if (FD0 <= num && num <= FD31) { /* double precision */ + } else if (num >= FD0 && num <= FD31) { /* double precision */ instructions[0] = MFSR_DTR(0); instructions[1] = FMTDR(0, nds32_reg_sr_index(num)); instructions[2] = DSB; diff --git a/src/jtag/drivers/versaloon/versaloon.c b/src/jtag/drivers/versaloon/versaloon.c index b8602ddeb..c6e390c93 100644 --- a/src/jtag/drivers/versaloon/versaloon.c +++ b/src/jtag/drivers/versaloon/versaloon.c @@ -212,7 +212,7 @@ RESULT versaloon_send_command(uint16_t out_len, uint16_t *inlen) ret = libusb_bulk_transfer(versaloon_usb_device_handle, versaloon_interface.usb_setting.ep_out, versaloon_buf, out_len, &transferred, versaloon_usb_to); - if (0 != ret || transferred != out_len) { + if (ret != 0 || transferred != out_len) { LOG_ERROR(ERRMSG_FAILURE_OPERATION, "send usb data"); return ERRCODE_FAILURE_OPERATION; } diff --git a/src/jtag/drivers/xds110.c b/src/jtag/drivers/xds110.c index 7b560df9d..1a17f70cc 100644 --- a/src/jtag/drivers/xds110.c +++ b/src/jtag/drivers/xds110.c @@ -379,8 +379,8 @@ static bool usb_connect(void) /* Get the device's serial number string */ result = libusb_get_string_descriptor_ascii(dev, desc.iSerialNumber, data, max_data); - if (0 < result && - 0 == strcmp((char *)data, (char *)xds110.serial)) { + if (result > 0 && + strcmp((char *)data, (char *)xds110.serial) == 0) { found = true; break; } @@ -497,7 +497,7 @@ static bool usb_write(unsigned char *buffer, int size, int *written) result = libusb_bulk_transfer(xds110.dev, xds110.endpoint_out, buffer, size, &bytes_written, 0); - while (LIBUSB_ERROR_PIPE == result && retries < 3) { + while (result == LIBUSB_ERROR_PIPE && retries < 3) { /* Try clearing the pipe stall and retry transfer */ libusb_clear_halt(xds110.dev, xds110.endpoint_out); result = libusb_bulk_transfer(xds110.dev, xds110.endpoint_out, buffer, @@ -508,7 +508,7 @@ static bool usb_write(unsigned char *buffer, int size, int *written) if (NULL != written) *written = bytes_written; - return (0 == result && size == bytes_written) ? true : false; + return (result == 0 && size == bytes_written) ? true : false; } static bool usb_get_response(uint32_t *total_bytes_read, uint32_t timeout) @@ -1021,7 +1021,7 @@ static bool xds_set_supply(uint32_t voltage) xds110.write_payload[0] = XDS_SET_SUPPLY; xds110_set_u32(volts_pntr, voltage); - *source_pntr = (uint8_t)(0 != voltage ? 1 : 0); + *source_pntr = (uint8_t)(voltage != 0 ? 1 : 0); success = xds_execute(XDS_OUT_LEN + 5, XDS_IN_LEN, DEFAULT_ATTEMPTS, DEFAULT_TIMEOUT); diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c index 79eea5460..2355babf0 100644 --- a/src/jtag/tcl.c +++ b/src/jtag/tcl.c @@ -133,7 +133,7 @@ static int jim_command_drscan(Jim_Interp *interp, int argc, Jim_Obj * const *arg /* get arg as a string. */ cp = Jim_GetString(args[i], NULL); /* is it the magic? */ - if (0 == strcmp("-endstate", cp)) { + if (strcmp("-endstate", cp) == 0) { /* is the statename valid? */ cp = Jim_GetString(args[i + 1], NULL); diff --git a/src/rtos/mqx.c b/src/rtos/mqx.c index 377bca96c..9f59c6d7c 100644 --- a/src/rtos/mqx.c +++ b/src/rtos/mqx.c @@ -199,28 +199,22 @@ static int mqx_is_scheduler_running( uint32_t capability_value = 0; /* get '_mqx_kernel_data' symbol */ - if (ERROR_OK != mqx_get_symbol( - rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_symbol - )) { + if (mqx_get_symbol(rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_symbol) != ERROR_OK) return ERROR_FAIL; - } + /* get '_mqx_kernel_data' */ - if (ERROR_OK != mqx_get_member( - rtos, kernel_data_symbol, 0, 4, - "_mqx_kernel_data", &kernel_data_addr - )) { + if (mqx_get_member(rtos, kernel_data_symbol, 0, 4, + "_mqx_kernel_data", &kernel_data_addr) != ERROR_OK) return ERROR_FAIL; - } + /* return if '_mqx_kernel_data' is NULL or default 0xFFFFFFFF */ - if (0 == kernel_data_addr || (uint32_t)(-1) == kernel_data_addr) + if (kernel_data_addr == 0 || kernel_data_addr == (uint32_t)(-1)) return ERROR_FAIL; /* get kernel_data->ADDRESSING_CAPABILITY */ - if (ERROR_OK != mqx_get_member( - rtos, kernel_data_addr, MQX_KERNEL_OFFSET_CAPABILITY, 4, - "kernel_data->ADDRESSING_CAPABILITY", (void *)&capability_value - )) { + if (mqx_get_member(rtos, kernel_data_addr, MQX_KERNEL_OFFSET_CAPABILITY, 4, + "kernel_data->ADDRESSING_CAPABILITY", (void *)&capability_value) != ERROR_OK) return ERROR_FAIL; - } + /* check first member, the '_mqx_kernel_data->ADDRESSING_CAPABILITY'. it suppose to be set to value 8 */ if (capability_value != 8) { @@ -228,12 +222,10 @@ static int mqx_is_scheduler_running( return ERROR_FAIL; } /* get active ptr */ - if (ERROR_OK != mqx_get_member( - rtos, kernel_data_addr, MQX_KERNEL_OFFSET_ACTIVE_TASK, 4, - "kernel_data->ACTIVE_PTR", (void *)&active_td_addr - )) { + if (mqx_get_member(rtos, kernel_data_addr, MQX_KERNEL_OFFSET_ACTIVE_TASK, 4, + "kernel_data->ACTIVE_PTR", (void *)&active_td_addr) != ERROR_OK) return ERROR_FAIL; - } + /* active task is system task, scheduler has not not run yet */ system_td_addr = kernel_data_addr + MQX_KERNEL_OFFSET_SYSTEM_TASK; if (active_td_addr == system_td_addr) { @@ -302,33 +294,25 @@ static int mqx_update_threads( if (ERROR_OK != mqx_is_scheduler_running(rtos)) return ERROR_FAIL; /* get kernel_data symbol */ - if (ERROR_OK != mqx_get_symbol( - rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_addr - )) { + if (mqx_get_symbol(rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_addr) != ERROR_OK) return ERROR_FAIL; - } + /* read kernel_data */ - if (ERROR_OK != mqx_get_member( - rtos, kernel_data_addr, 0, 4, "_mqx_kernel_data", &kernel_data_addr - )) { + if (mqx_get_member(rtos, kernel_data_addr, 0, 4, + "_mqx_kernel_data", &kernel_data_addr) != ERROR_OK) return ERROR_FAIL; - } + /* get task queue address */ task_queue_addr = kernel_data_addr + MQX_KERNEL_OFFSET_TDLIST; /* get task queue size */ - if (ERROR_OK != mqx_get_member( - rtos, task_queue_addr, MQX_QUEUE_OFFSET_SIZE, 2, - "kernel_data->TD_LIST.SIZE", &task_queue_size - )) { + if (mqx_get_member(rtos, task_queue_addr, MQX_QUEUE_OFFSET_SIZE, 2, + "kernel_data->TD_LIST.SIZE", &task_queue_size) != ERROR_OK) return ERROR_FAIL; - } + /* get active ptr */ - if (ERROR_OK != mqx_get_member( - rtos, kernel_data_addr, MQX_KERNEL_OFFSET_ACTIVE_TASK, 4, - "kernel_data->ACTIVE_PTR", (void *)&active_td_addr - )) { + if (mqx_get_member(rtos, kernel_data_addr, MQX_KERNEL_OFFSET_ACTIVE_TASK, 4, + "kernel_data->ACTIVE_PTR", (void *)&active_td_addr) != ERROR_OK) return ERROR_FAIL; - } /* setup threads info */ rtos->thread_count = task_queue_size; @@ -355,60 +339,46 @@ static int mqx_update_threads( char *state_name = "Unknown"; /* set current taskpool address */ - if (ERROR_OK != mqx_get_member( - rtos, taskpool_addr, MQX_TASK_OFFSET_NEXT, 4, - "td_struct_ptr->NEXT", &taskpool_addr - )) { + if (mqx_get_member(rtos, taskpool_addr, MQX_TASK_OFFSET_NEXT, 4, + "td_struct_ptr->NEXT", &taskpool_addr) != ERROR_OK) return ERROR_FAIL; - } + /* get task address from taskpool */ task_addr = taskpool_addr - MQX_TASK_OFFSET_TDLIST; /* get address of 'td_struct_ptr->TEMPLATE_LIST_PTR' */ - if (ERROR_OK != mqx_get_member( - rtos, task_addr, MQX_TASK_OFFSET_TEMPLATE, 4, - "td_struct_ptr->TEMPLATE_LIST_PTR", &task_template - )) { + if (mqx_get_member(rtos, task_addr, MQX_TASK_OFFSET_TEMPLATE, 4, + "td_struct_ptr->TEMPLATE_LIST_PTR", &task_template) != ERROR_OK) return ERROR_FAIL; - } + /* get address of 'td_struct_ptr->TEMPLATE_LIST_PTR->NAME' */ - if (ERROR_OK != mqx_get_member( - rtos, task_template, MQX_TASK_TEMPLATE_OFFSET_NAME, 4, - "td_struct_ptr->TEMPLATE_LIST_PTR->NAME", &task_name_addr - )) { + if (mqx_get_member(rtos, task_template, MQX_TASK_TEMPLATE_OFFSET_NAME, 4, + "td_struct_ptr->TEMPLATE_LIST_PTR->NAME", &task_name_addr) != ERROR_OK) return ERROR_FAIL; - } + /* get value of 'td_struct->TEMPLATE_LIST_PTR->NAME' */ - if (ERROR_OK != mqx_get_member( - rtos, task_name_addr, 0, MQX_THREAD_NAME_LENGTH, - "*td_struct_ptr->TEMPLATE_LIST_PTR->NAME", task_name - )) { + if (mqx_get_member(rtos, task_name_addr, 0, MQX_THREAD_NAME_LENGTH, + "*td_struct_ptr->TEMPLATE_LIST_PTR->NAME", task_name) != ERROR_OK) return ERROR_FAIL; - } + /* always terminate last character by force, otherwise openocd might fail if task_name has corrupted data */ task_name[MQX_THREAD_NAME_LENGTH] = '\0'; /* get value of 'td_struct_ptr->TASK_ID' */ - if (ERROR_OK != mqx_get_member( - rtos, task_addr, MQX_TASK_OFFSET_ID, 4, - "td_struct_ptr->TASK_ID", &task_id - )) { + if (mqx_get_member(rtos, task_addr, MQX_TASK_OFFSET_ID, 4, + "td_struct_ptr->TASK_ID", &task_id) != ERROR_OK) return ERROR_FAIL; - } + /* get task errno */ - if (ERROR_OK != mqx_get_member( - rtos, task_addr, MQX_TASK_OFFSET_ERROR_CODE, 4, - "td_struct_ptr->TASK_ERROR_CODE", &task_errno - )) { + if (mqx_get_member(rtos, task_addr, MQX_TASK_OFFSET_ERROR_CODE, 4, + "td_struct_ptr->TASK_ERROR_CODE", &task_errno) != ERROR_OK) return ERROR_FAIL; - } + /* get value of 'td_struct_ptr->STATE' */ - if (ERROR_OK != mqx_get_member( - rtos, task_addr, MQX_TASK_OFFSET_STATE, 4, - "td_struct_ptr->STATE", &task_state - )) { + if (mqx_get_member(rtos, task_addr, MQX_TASK_OFFSET_STATE, 4, + "td_struct_ptr->STATE", &task_state) != ERROR_OK) return ERROR_FAIL; - } + task_state &= MQX_TASK_STATE_MASK; /* and search for defined state */ for (state_index = 0; state_index < ARRAY_SIZE(mqx_states); state_index++) { @@ -471,26 +441,21 @@ static int mqx_get_thread_reg_list( if (ERROR_OK != mqx_is_scheduler_running(rtos)) return ERROR_FAIL; /* get kernel_data symbol */ - if (ERROR_OK != mqx_get_symbol( - rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_addr - )) { + if (mqx_get_symbol(rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_addr) != ERROR_OK) return ERROR_FAIL; - } + /* read kernel_data */ - if (ERROR_OK != mqx_get_member( - rtos, kernel_data_addr, 0, 4, "_mqx_kernel_data", &kernel_data_addr - )) { + if (mqx_get_member(rtos, kernel_data_addr, 0, 4, + "_mqx_kernel_data", &kernel_data_addr) != ERROR_OK) return ERROR_FAIL; - } + /* get task queue address */ task_queue_addr = kernel_data_addr + MQX_KERNEL_OFFSET_TDLIST; /* get task queue size */ - if (ERROR_OK != mqx_get_member( - rtos, task_queue_addr, MQX_QUEUE_OFFSET_SIZE, 2, - "kernel_data->TD_LIST.SIZE", &task_queue_size - )) { + if (mqx_get_member(rtos, task_queue_addr, MQX_QUEUE_OFFSET_SIZE, 2, + "kernel_data->TD_LIST.SIZE", &task_queue_size) != ERROR_OK) return ERROR_FAIL; - } + /* search for taskid */ for ( uint32_t i = 0, taskpool_addr = task_queue_addr; @@ -501,21 +466,17 @@ static int mqx_get_thread_reg_list( uint32_t task_id = 0; /* set current taskpool address */ tmp_address = taskpool_addr; - if (ERROR_OK != mqx_get_member( - rtos, tmp_address, MQX_TASK_OFFSET_NEXT, 4, - "td_struct_ptr->NEXT", &taskpool_addr - )) { + if (mqx_get_member(rtos, tmp_address, MQX_TASK_OFFSET_NEXT, 4, + "td_struct_ptr->NEXT", &taskpool_addr) != ERROR_OK) return ERROR_FAIL; - } + /* get task address from taskpool */ task_addr = taskpool_addr - MQX_TASK_OFFSET_TDLIST; /* get value of td_struct->TASK_ID */ - if (ERROR_OK != mqx_get_member( - rtos, task_addr, MQX_TASK_OFFSET_ID, 4, - "td_struct_ptr->TASK_ID", &task_id - )) { + if (mqx_get_member(rtos, task_addr, MQX_TASK_OFFSET_ID, 4, + "td_struct_ptr->TASK_ID", &task_id) != ERROR_OK) return ERROR_FAIL; - } + /* found taskid, break */ if (task_id == thread_id) { my_task_addr = task_addr; @@ -527,11 +488,10 @@ static int mqx_get_thread_reg_list( return ERROR_FAIL; } /* get task stack head address */ - if (ERROR_OK != mqx_get_member( - rtos, my_task_addr, MQX_TASK_OFFSET_STACK, 4, "task->STACK_PTR", &stack_ptr - )) { + if (mqx_get_member(rtos, my_task_addr, MQX_TASK_OFFSET_STACK, 4, + "task->STACK_PTR", &stack_ptr) != ERROR_OK) return ERROR_FAIL; - } + return rtos_generic_stack_read( rtos->target, ((struct mqx_params *)rtos->rtos_specific_params)->stacking_info, stack_ptr, reg_list, num_regs ); diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c index 8e3febc06..7d96825b9 100644 --- a/src/rtos/rtos.c +++ b/src/rtos/rtos.c @@ -140,7 +140,7 @@ int rtos_create(struct jim_getopt_info *goi, struct target *target) if (e != JIM_OK) return e; - if (0 == strcmp(cp, "auto")) { + if (strcmp(cp, "auto") == 0) { /* Auto detect tries to look up all symbols for each RTOS, * and runs the RTOS driver's _detect() function when GDB * finds all symbols for any RTOS. See rtos_qsymbol(). */ diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c index 9de7048f4..1e5b5e252 100644 --- a/src/target/arm_semihosting.c +++ b/src/target/arm_semihosting.c @@ -367,7 +367,7 @@ int arm_semihosting(struct target *target, int *retval) } /* Check for ARM operation numbers. */ - if (0 <= semihosting->op && semihosting->op <= 0x31) { + if (semihosting->op >= 0 && semihosting->op <= 0x31) { *retval = semihosting_common(target); if (*retval != ERROR_OK) { LOG_ERROR("Failed semihosting operation (0x%02X)", semihosting->op); diff --git a/src/target/nds32.c b/src/target/nds32.c index 184f2fecc..4b1d1177c 100644 --- a/src/target/nds32.c +++ b/src/target/nds32.c @@ -422,7 +422,7 @@ static struct reg_cache *nds32_build_reg_cache(struct target *target, reg_list[i].reg_data_type = calloc(sizeof(struct reg_data_type), 1); - if (FD0 <= reg_arch_info[i].num && reg_arch_info[i].num <= FD31) { + if (reg_arch_info[i].num >= FD0 && reg_arch_info[i].num <= FD31) { reg_list[i].value = reg_arch_info[i].value; reg_list[i].type = &nds32_reg_access_type_64; @@ -456,20 +456,20 @@ static struct reg_cache *nds32_build_reg_cache(struct target *target, } } - if (R16 <= reg_arch_info[i].num && reg_arch_info[i].num <= R25) + if (reg_arch_info[i].num >= R16 && reg_arch_info[i].num <= R25) reg_list[i].caller_save = true; else reg_list[i].caller_save = false; reg_list[i].feature = malloc(sizeof(struct reg_feature)); - if (R0 <= reg_arch_info[i].num && reg_arch_info[i].num <= IFC_LP) + if (reg_arch_info[i].num >= R0 && reg_arch_info[i].num <= IFC_LP) reg_list[i].feature->name = "org.gnu.gdb.nds32.core"; - else if (CR0 <= reg_arch_info[i].num && reg_arch_info[i].num <= SECUR0) + else if (reg_arch_info[i].num >= CR0 && reg_arch_info[i].num <= SECUR0) reg_list[i].feature->name = "org.gnu.gdb.nds32.system"; - else if (D0L24 <= reg_arch_info[i].num && reg_arch_info[i].num <= CBE3) + else if (reg_arch_info[i].num >= D0L24 && reg_arch_info[i].num <= CBE3) reg_list[i].feature->name = "org.gnu.gdb.nds32.audio"; - else if (FPCSR <= reg_arch_info[i].num && reg_arch_info[i].num <= FD31) + else if (reg_arch_info[i].num >= FPCSR && reg_arch_info[i].num <= FD31) reg_list[i].feature->name = "org.gnu.gdb.nds32.fpu"; cache->num_regs++; @@ -1545,7 +1545,7 @@ int nds32_restore_context(struct target *target) i, buf_get_u32(reg->value, 0, 32)); reg_arch_info = reg->arch_info; - if (FD0 <= reg_arch_info->num && reg_arch_info->num <= FD31) { + if (reg_arch_info->num >= FD0 && reg_arch_info->num <= FD31) { uint64_t val = buf_get_u64(reg_arch_info->value, 0, 64); aice_write_reg_64(aice, reg_arch_info->num, val); } else { @@ -1735,8 +1735,7 @@ int nds32_cache_sync(struct target *target, target_addr_t address, uint32_t leng * be physical address. L1I_VA_INVALIDATE uses PSW.IT to decide * address translation or not. */ target_addr_t physical_addr; - if (ERROR_FAIL == target->type->virt2phys(target, cur_address, - &physical_addr)) + if (target->type->virt2phys(target, cur_address, &physical_addr) == ERROR_FAIL) return ERROR_FAIL; /* I$ invalidate */ @@ -1926,8 +1925,7 @@ int nds32_examine_debug_reason(struct nds32 *nds32) if (ERROR_OK != nds32_read_opcode(nds32, value_pc, &opcode)) return ERROR_FAIL; - if (ERROR_OK != nds32_evaluate_opcode(nds32, opcode, value_pc, - &instruction)) + if (nds32_evaluate_opcode(nds32, opcode, value_pc, &instruction) != ERROR_OK) return ERROR_FAIL; /* hit 'break 0x7FFF' */ @@ -1966,8 +1964,7 @@ int nds32_examine_debug_reason(struct nds32 *nds32) case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_IMPRECISE: case NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE: case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE: - if (ERROR_OK != nds32->get_watched_address(nds32, - &(nds32->watched_address), reason)) + if (nds32->get_watched_address(nds32, &(nds32->watched_address), reason) != ERROR_OK) return ERROR_FAIL; target->debug_reason = DBG_REASON_WATCHPOINT; diff --git a/src/target/nds32_cmd.c b/src/target/nds32_cmd.c index 3931707be..af1f8b18a 100644 --- a/src/target/nds32_cmd.c +++ b/src/target/nds32_cmd.c @@ -577,8 +577,7 @@ COMMAND_HANDLER(handle_nds32_decode_command) while (i < insn_count) { if (ERROR_OK != nds32_read_opcode(nds32, read_addr, &opcode)) return ERROR_FAIL; - if (ERROR_OK != nds32_evaluate_opcode(nds32, opcode, - read_addr, &instruction)) + if (nds32_evaluate_opcode(nds32, opcode, read_addr, &instruction) != ERROR_OK) return ERROR_FAIL; command_print(CMD, "%s", instruction.text); diff --git a/src/target/nds32_disassembler.c b/src/target/nds32_disassembler.c index 0cfd197d2..0bf74e178 100644 --- a/src/target/nds32_disassembler.c +++ b/src/target/nds32_disassembler.c @@ -2849,7 +2849,7 @@ static uint32_t field_mask[9] = { static uint8_t nds32_extract_field_8u(uint16_t opcode, uint32_t start, uint32_t length) { - if (0 < length && length < 9) + if (length > 0 && length < 9) return (opcode >> start) & field_mask[length]; return 0; diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index b70c259dc..b93e5494a 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -4653,10 +4653,10 @@ int riscv013_test_compliance(struct target *target) for (unsigned int i = 1; i < 32; i = i << 1) { riscv_reg_t testval = i | ((i + 1ULL) << 32); riscv_reg_t testval_read; - COMPLIANCE_TEST(ERROR_OK == register_write_direct(target, GDB_REGNO_ZERO + i, testval), + COMPLIANCE_TEST(register_write_direct(target, GDB_REGNO_ZERO + i, testval) == ERROR_OK, "GPR Writes should be supported."); COMPLIANCE_MUST_PASS(write_abstract_arg(target, 0, 0xDEADBEEFDEADBEEF, 64)); - COMPLIANCE_TEST(ERROR_OK == register_read_direct(target, &testval_read, GDB_REGNO_ZERO + i), + COMPLIANCE_TEST(register_read_direct(target, &testval_read, GDB_REGNO_ZERO + i) == ERROR_OK, "GPR Reads should be supported."); if (riscv_xlen(target) > 32) { /* Dummy comment to satisfy linter, since removing the branches here doesn't actually compile. */ @@ -4680,7 +4680,7 @@ int riscv013_test_compliance(struct target *target) if (info->progbufsize >= 3) { testvar = 0; - COMPLIANCE_TEST(ERROR_OK == register_write_direct(target, GDB_REGNO_S0, 0), + COMPLIANCE_TEST(register_write_direct(target, GDB_REGNO_S0, 0) == ERROR_OK, "Need to be able to write S0 to test ABSTRACTAUTO"); struct riscv_program program; COMPLIANCE_MUST_PASS(riscv_program_init(&program, target)); @@ -4721,7 +4721,7 @@ int riscv013_test_compliance(struct target *target) } COMPLIANCE_WRITE(target, DM_ABSTRACTAUTO, 0); - COMPLIANCE_TEST(ERROR_OK == register_read_direct(target, &value, GDB_REGNO_S0), + COMPLIANCE_TEST(register_read_direct(target, &value, GDB_REGNO_S0) == ERROR_OK, "Need to be able to read S0 to test ABSTRACTAUTO"); COMPLIANCE_TEST(testvar == value, @@ -4797,8 +4797,8 @@ int riscv013_test_compliance(struct target *target) /* Pulse reset. */ target->reset_halt = true; COMPLIANCE_MUST_PASS(riscv_set_current_hartid(target, 0)); - COMPLIANCE_TEST(ERROR_OK == assert_reset(target), "Must be able to assert NDMRESET"); - COMPLIANCE_TEST(ERROR_OK == deassert_reset(target), "Must be able to deassert NDMRESET"); + COMPLIANCE_TEST(assert_reset(target) == ERROR_OK, "Must be able to assert NDMRESET"); + COMPLIANCE_TEST(deassert_reset(target) == ERROR_OK, "Must be able to deassert NDMRESET"); /* Verify that most stuff is not affected by ndmreset. */ COMPLIANCE_READ(target, &testvar_read, DM_ABSTRACTCS); diff --git a/src/target/riscv/riscv_semihosting.c b/src/target/riscv/riscv_semihosting.c index c0e81eae4..90b8ddb4f 100644 --- a/src/target/riscv/riscv_semihosting.c +++ b/src/target/riscv/riscv_semihosting.c @@ -137,7 +137,7 @@ semihosting_result_t riscv_semihosting(struct target *target, int *retval) semihosting->word_size_bytes = riscv_xlen(target) / 8; /* Check for ARM operation numbers. */ - if (0 <= semihosting->op && semihosting->op <= 0x31) { + if (semihosting->op >= 0 && semihosting->op <= 0x31) { *retval = semihosting_common(target); if (*retval != ERROR_OK) { LOG_ERROR("Failed semihosting operation (0x%02X)", semihosting->op); commit 28c24a5c41c47a66e9310912f88148814f730a25 Author: Antonio Borneo <bor...@gm...> Date: Sat Jul 3 16:47:35 2021 +0200 openocd: fix simple cases of Yoda condition There are ~900 Yoda conditions to be aligned to the coding style. For recurrent Yoda conditions it's preferable using a trivial script in order to minimize the review effort. E.g. comparison of uppercase macro/enum with lowercase variable: - ...(ERROR_OK == retval)... + ...(retval == ERROR_OK)... Patch generated automatically with the command: sed -i \ 's/(\([A-Z][A-Z0-9_]*\) \([=!]=\) \([a-z][a-z0-9_]*\))/(\3 \2 \1)/g' \ $(find src/ -type f) While there, remove the braces {} around a single statement block to prevent warning from checkpatch. Change-Id: If585b0a4b4578879c87b2dd74d9e0025e275ec6b Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6354 Tested-by: jenkins Reviewed-by: Xiang W <wx...@12...> diff --git a/src/flash/common.c b/src/flash/common.c index 3e2551192..e8e795a4e 100644 --- a/src/flash/common.c +++ b/src/flash/common.c @@ -32,7 +32,7 @@ unsigned get_flash_name_index(const char *name) unsigned requested; int retval = parse_uint(name_index + 1, &requested); /* detect parsing error by forcing past end of bank list */ - return (ERROR_OK == retval) ? requested : ~0U; + return (retval == ERROR_OK) ? requested : ~0U; } bool flash_driver_name_matches(const char *name, const char *expected) diff --git a/src/flash/nand/at91sam9.c b/src/flash/nand/at91sam9.c index 534f20ede..4341935fe 100644 --- a/src/flash/nand/at91sam9.c +++ b/src/flash/nand/at91sam9.c @@ -368,16 +368,16 @@ static int at91sam9_read_page(struct nand_device *nand, uint32_t page, uint32_t status; retval = at91sam9_ecc_init(target, info); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = nand_page_command(nand, page, NAND_CMD_READ0, !data); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (data) { retval = nand_read_data_page(nand, data, data_size); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; } @@ -443,16 +443,16 @@ static int at91sam9_write_page(struct nand_device *nand, uint32_t page, uint32_t parity, nparity; retval = at91sam9_ecc_init(target, info); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (data) { retval = nand_write_data_page(nand, data, data_size); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Unable to write data to NAND device"); return retval; } @@ -476,7 +476,7 @@ static int at91sam9_write_page(struct nand_device *nand, uint32_t page, if (!oob) free(oob_data); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Unable to write OOB data to NAND"); return retval; } diff --git a/src/flash/nand/core.c b/src/flash/nand/core.c index baef5d59c..8e2af2338 100644 --- a/src/flash/nand/core.c +++ b/src/flash/nand/core.c @@ -750,7 +750,7 @@ int nand_page_command(struct nand_device *nand, uint32_t page, nand->controller->address(nand, (page >> 16) & 0xff); /* large page devices need a start command if reading */ - if (NAND_CMD_READ0 == cmd) + if (cmd == NAND_CMD_READ0) nand->controller->command(nand, NAND_CMD_READSTART); } @@ -772,7 +772,7 @@ int nand_read_data_page(struct nand_device *nand, uint8_t *data, uint32_t size) if (nand->controller->read_block_data != NULL) retval = (nand->controller->read_block_data)(nand, data, size); - if (ERROR_NAND_NO_BUFFER == retval) { + if (retval == ERROR_NAND_NO_BUFFER) { uint32_t i; int incr = (nand->device->options & NAND_BUSWIDTH_16) ? 2 : 1; @@ -793,7 +793,7 @@ int nand_read_page_raw(struct nand_device *nand, uint32_t page, int retval; retval = nand_page_command(nand, page, NAND_CMD_READ0, !data); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (data) @@ -812,7 +812,7 @@ int nand_write_data_page(struct nand_device *nand, uint8_t *data, uint32_t size) if (nand->controller->write_block_data != NULL) retval = (nand->controller->write_block_data)(nand, data, size); - if (ERROR_NAND_NO_BUFFER == retval) { + if (retval == ERROR_NAND_NO_BUFFER) { bool is16bit = nand->device->options & NAND_BUSWIDTH_16; uint32_t incr = is16bit ? 2 : 1; uint16_t write_data; @@ -825,7 +825,7 @@ int nand_write_data_page(struct nand_device *nand, uint8_t *data, uint32_t size) write_data = *data; retval = nand->controller->write_data(nand, write_data); - if (ERROR_OK != retval) + if (retval != ERROR_OK) break; data += incr; @@ -849,7 +849,7 @@ int nand_write_finish(struct nand_device *nand) return ERROR_NAND_OPERATION_TIMEOUT; retval = nand_read_status(nand, &status); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("couldn't read status"); return ERROR_NAND_OPERATION_FAILED; } @@ -870,12 +870,12 @@ int nand_write_page_raw(struct nand_device *nand, uint32_t page, int retval; retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (data) { retval = nand_write_data_page(nand, data, data_size); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Unable to write data to NAND device"); return retval; } @@ -883,7 +883,7 @@ int nand_write_page_raw(struct nand_device *nand, uint32_t page, if (oob) { retval = nand_write_data_page(nand, oob, oob_size); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Unable to write OOB data to NAND device"); return retval; } diff --git a/src/flash/nand/driver.c b/src/flash/nand/driver.c index f7665603f..b525f3d0a 100644 --- a/src/flash/nand/driver.c +++ b/src/flash/nand/driver.c @@ -75,7 +75,7 @@ int nand_driver_walk(nand_driver_walker_t f, void *x) { for (unsigned i = 0; nand_flash_controllers[i]; i++) { int retval = (*f)(nand_flash_controllers[i], x); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; } return ERROR_OK; diff --git a/src/flash/nand/fileio.c b/src/flash/nand/fileio.c index fee401292..5504841b5 100644 --- a/src/flash/nand/fileio.c +++ b/src/flash/nand/fileio.c @@ -67,8 +67,8 @@ int nand_fileio_start(struct command_invocation *cmd, if (NULL != filename) { int retval = fileio_open(&state->fileio, filename, filemode, FILEIO_BINARY); - if (ERROR_OK != retval) { - const char *msg = (FILEIO_READ == filemode) ? "read" : "write"; + if (retval != ERROR_OK) { + const char *msg = (filemode == FILEIO_READ) ? "read" : "write"; command_print(cmd, "failed to open '%s' for %s access", filename, msg); return retval; @@ -124,7 +124,7 @@ COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state, struct nand_device *nand; int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (NULL == nand->device) { @@ -159,7 +159,7 @@ COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state, } retval = nand_fileio_start(CMD, nand, CMD_ARGV[1], filemode, state); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (!need_size) { diff --git a/src/flash/nand/lpc3180.c b/src/flash/nand/lpc3180.c index 6ce05753e..bda7b87c3 100644 --- a/src/flash/nand/lpc3180.c +++ b/src/flash/nand/lpc3180.c @@ -589,7 +589,7 @@ static int lpc3180_write_page(struct nand_device *nand, oob_size); } retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* allocate a working area */ @@ -970,7 +970,7 @@ static int lpc3180_read_page(struct nand_device *nand, /* read always the data and also oob areas*/ retval = nand_page_command(nand, page, NAND_CMD_READ0, 0); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* allocate a working area */ diff --git a/src/flash/nand/lpc32xx.c b/src/flash/nand/lpc32xx.c index 3e2add49b..49890c2ab 100644 --- a/src/flash/nand/lpc32xx.c +++ b/src/flash/nand/lpc32xx.c @@ -141,7 +141,7 @@ static float lpc32xx_cycle_time(struct nand_device *nand) /* determine current SYSCLK (13'MHz or main oscillator) */ retval = target_read_u32(target, 0x40004050, &sysclk_ctrl); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read SYSCLK_CTRL"); return ERROR_NAND_OPERATION_FAILED; } @@ -153,7 +153,7 @@ static float lpc32xx_cycle_time(struct nand_device *nand) /* determine selected HCLK source */ retval = target_read_u32(target, 0x40004044, &pwr_ctrl); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read HCLK_CTRL"); return ERROR_NAND_OPERATION_FAILED; } @@ -162,14 +162,14 @@ static float lpc32xx_cycle_time(struct nand_device *nand) hclk = sysclk; else { retval = target_read_u32(target, 0x40004058, &hclkpll_ctrl); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read HCLKPLL_CTRL"); return ERROR_NAND_OPERATION_FAILED; } hclk_pll = lpc32xx_pll(sysclk, hclkpll_ctrl); retval = target_read_u32(target, 0x40004040, &hclkdiv_ctrl); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read CLKDIV_CTRL"); return ERROR_NAND_OPERATION_FAILED; } @@ -235,21 +235,21 @@ static int lpc32xx_init(struct nand_device *nand) /* FLASHCLK_CTRL = 0x22 (enable clk for MLC) */ retval = target_write_u32(target, 0x400040c8, 0x22); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set FLASHCLK_CTRL"); return ERROR_NAND_OPERATION_FAILED; } /* MLC_CEH = 0x0 (Force nCE assert) */ retval = target_write_u32(target, 0x200b804c, 0x0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_CEH"); return ERROR_NAND_OPERATION_FAILED; } /* MLC_LOCK = 0xa25e (unlock protected registers) */ retval = target_write_u32(target, 0x200b8044, 0xa25e); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_LOCK"); return ERROR_NAND_OPERATION_FAILED; } @@ -264,7 +264,7 @@ static int lpc32xx_init(struct nand_device *nand) if (bus_width == 16) mlc_icr_value |= 0x1; retval = target_write_u32(target, 0x200b8030, mlc_icr_value); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ICR"); return ERROR_NAND_OPERATION_FAILED; } @@ -282,7 +282,7 @@ static int lpc32xx_init(struct nand_device *nand) /* MLC_LOCK = 0xa25e (unlock protected registers) */ retval = target_write_u32(target, 0x200b8044, 0xa25e); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_LOCK"); return ERROR_NAND_OPERATION_FAILED; } @@ -296,13 +296,13 @@ static int lpc32xx_init(struct nand_device *nand) | ((trhz & 0x7) << 16) | ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24)); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_TIME_REG"); return ERROR_NAND_OPERATION_FAILED; } retval = lpc32xx_reset(nand); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return ERROR_NAND_OPERATION_FAILED; } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) { float cycle; @@ -311,7 +311,7 @@ static int lpc32xx_init(struct nand_device *nand) /* FLASHCLK_CTRL = 0x05 (enable clk for SLC) */ retval = target_write_u32(target, 0x400040c8, 0x05); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set FLASHCLK_CTRL"); return ERROR_NAND_OPERATION_FAILED; } @@ -320,7 +320,7 @@ static int lpc32xx_init(struct nand_device *nand) * so reset calling is here at the beginning */ retval = lpc32xx_reset(nand); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return ERROR_NAND_OPERATION_FAILED; /* SLC_CFG = @@ -333,14 +333,14 @@ static int lpc32xx_init(struct nand_device *nand) */ retval = target_write_u32(target, 0x20020014, 0x3e | ((bus_width == 16) ? 1 : 0)); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set SLC_CFG"); return ERROR_NAND_OPERATION_FAILED; } /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */ retval = target_write_u32(target, 0x20020020, 0x03); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set SLC_IEN"); return ERROR_NAND_OPERATION_FAILED; } @@ -349,14 +349,14 @@ static int lpc32xx_init(struct nand_device *nand) /* DMACLK_CTRL = 0x01 (enable clock for DMA controller) */ retval = target_write_u32(target, 0x400040e8, 0x01); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set DMACLK_CTRL"); return ERROR_NAND_OPERATION_FAILED; } /* DMACConfig = DMA enabled*/ retval = target_write_u32(target, 0x31000030, 0x01); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set DMACConfig"); return ERROR_NAND_OPERATION_FAILED; } @@ -380,7 +380,7 @@ static int lpc32xx_init(struct nand_device *nand) | ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28)); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set SLC_TAC"); return ERROR_NAND_OPERATION_FAILED; } @@ -407,7 +407,7 @@ static int lpc32xx_reset(struct nand_device *nand) } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) { /* MLC_CMD = 0xff (reset controller and NAND device) */ retval = target_write_u32(target, 0x200b8000, 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_CMD"); return ERROR_NAND_OPERATION_FAILED; } @@ -420,7 +420,7 @@ static int lpc32xx_reset(struct nand_device *nand) } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) { /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */ retval = target_write_u32(target, 0x20020010, 0x6); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set SLC_CTRL"); return ERROR_NAND_OPERATION_FAILED; } @@ -453,14 +453,14 @@ static int lpc32xx_command(struct nand_device *nand, uint8_t command) } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) { /* MLC_CMD = command */ retval = target_write_u32(target, 0x200b8000, command); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_CMD"); return ERROR_NAND_OPERATION_FAILED; } } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) { /* SLC_CMD = command */ retval = target_write_u32(target, 0x20020008, command); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set SLC_CMD"); return ERROR_NAND_OPERATION_FAILED; } @@ -487,14 +487,14 @@ static int lpc32xx_address(struct nand_device *nand, uint8_t address) } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) { /* MLC_ADDR = address */ retval = target_write_u32(target, 0x200b8004, address); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) { /* SLC_ADDR = address */ retval = target_write_u32(target, 0x20020004, address); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set SLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } @@ -521,14 +521,14 @@ static int lpc32xx_write_data(struct nand_device *nand, uint16_t data) } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) { /* MLC_DATA = data */ retval = target_write_u32(target, 0x200b0000, data); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_DATA"); return ERROR_NAND_OPERATION_FAILED; } } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) { /* SLC_DATA = data */ retval = target_write_u32(target, 0x20020000, data); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set SLC_DATA"); return ERROR_NAND_OPERATION_FAILED; } @@ -561,7 +561,7 @@ static int lpc32xx_read_data(struct nand_device *nand, void *data) LOG_ERROR("BUG: bus_width neither 8 nor 16 bit"); return ERROR_NAND_OPERATION_FAILED; } - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read MLC_DATA"); return ERROR_NAND_OPERATION_FAILED; } @@ -570,7 +570,7 @@ static int lpc32xx_read_data(struct nand_device *nand, void *data) /* data = SLC_DATA, must use 32-bit access */ retval = target_read_u32(target, 0x20020000, &data32); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read SLC_DATA"); return ERROR_NAND_OPERATION_FAILED; } @@ -600,7 +600,7 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page, /* MLC_CMD = sequential input */ retval = target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_CMD"); return ERROR_NAND_OPERATION_FAILED; } @@ -608,20 +608,20 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page, if (nand->page_size == 512) { /* MLC_ADDR = 0x0 (one column cycle) */ retval = target_write_u32(target, 0x200b8004, 0x0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } /* MLC_ADDR = row */ retval = target_write_u32(target, 0x200b8004, page & 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } retval = target_write_u32(target, 0x200b8004, (page >> 8) & 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } @@ -629,7 +629,7 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page, if (nand->address_cycles == 4) { retval = target_write_u32(target, 0x200b8004, (page >> 16) & 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } @@ -637,25 +637,25 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page, } else { /* MLC_ADDR = 0x0 (two column cycles) */ retval = target_write_u32(target, 0x200b8004, 0x0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } retval = target_write_u32(target, 0x200b8004, 0x0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } /* MLC_ADDR = row */ retval = target_write_u32(target, 0x200b8004, page & 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } retval = target_write_u32(target, 0x200b8004, (page >> 8) & 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } @@ -687,27 +687,27 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page, /* write MLC_ECC_ENC_REG to start encode cycle */ retval = target_write_u32(target, 0x200b8008, 0x0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ECC_ENC_REG"); return ERROR_NAND_OPERATION_FAILED; } retval = target_write_memory(target, 0x200a8000, 4, 128, page_buffer); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_BUF (data)"); return ERROR_NAND_OPERATION_FAILED; } retval = target_write_memory(target, 0x200a8000, 1, 6, oob_buffer); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_BUF (oob)"); return ERROR_NAND_OPERATION_FAILED; } /* write MLC_ECC_AUTO_ENC_REG to start auto encode */ retval = target_write_u32(target, 0x200b8010, 0x0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ECC_AUTO_ENC_REG"); return ERROR_NAND_OPERATION_FAILED; } @@ -721,7 +721,7 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page, /* MLC_CMD = auto program command */ retval = target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_CMD"); return ERROR_NAND_OPERATION_FAILED; } @@ -901,14 +901,14 @@ static int lpc32xx_start_slc_dma(struct nand_device *nand, uint32_t count, /* DMACIntTCClear = ch0 */ retval = target_write_u32(target, 0x31000008, 1); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not set DMACIntTCClear"); return retval; } /* DMACIntErrClear = ch0 */ retval = target_write_u32(target, 0x31000010, 1); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not set DMACIntErrClear"); return retval; } @@ -926,28 +926,28 @@ static int lpc32xx_start_slc_dma(struct nand_device *nand, uint32_t count, retval = target_write_u32(target, 0x31000110, 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not set DMACC0Config"); return retval; } /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */ retval = target_write_u32(target, 0x20020010, 0x3); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not set SLC_CTRL"); return retval; } /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/ retval = target_write_u32(target, 0x20020028, 2); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not set SLC_ICR"); return retval; } /* SLC_TC */ retval = target_write_u32(target, 0x20020030, count); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("lpc32xx_start_slc_dma: Could not set SLC_TC"); return retval; } @@ -974,13 +974,13 @@ static int lpc32xx_dma_ready(struct nand_device *nand, int timeout) /* Read DMACRawIntTCStat */ retval = target_read_u32(target, 0x31000014, &tc_stat); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not read DMACRawIntTCStat"); return 0; } /* Read DMACRawIntErrStat */ retval = target_read_u32(target, 0x31000018, &err_stat); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not read DMACRawIntErrStat"); return 0; } @@ -1065,13 +1065,13 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, retval = target_write_memory(target, target_mem_base, 4, nll * sizeof(struct dmac_ll) / 4, (uint8_t *)dmalist); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not write DMA descriptors to IRAM"); return retval; } retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("NAND_CMD_SEQIN failed"); return retval; } @@ -1085,7 +1085,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, WIDTH = bus_width */ retval = target_write_u32(target, 0x20020014, 0x3c); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not set SLC_CFG"); return retval; } @@ -1097,7 +1097,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, retval = target_write_memory(target, target_mem_base + DATA_OFFS, 4, nand->page_size/4, fdata); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not write data to IRAM"); return retval; } @@ -1106,7 +1106,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, retval = target_write_memory(target, 0x31000100, 4, sizeof(struct dmac_ll) / 4, (uint8_t *)dmalist); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not write DMA descriptor to DMAC"); return retval; } @@ -1115,7 +1115,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, int tot_size = nand->page_size; tot_size += tot_size == 2048 ? 64 : 16; retval = lpc32xx_start_slc_dma(nand, tot_size, 0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("DMA failed"); return retval; } @@ -1139,7 +1139,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, static uint32_t hw_ecc[8]; retval = target_read_memory(target, target_mem_base + ECC_OFFS, 4, ecc_count, (uint8_t *)hw_ecc); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Reading hw generated ECC from IRAM failed"); return retval; } @@ -1154,7 +1154,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, } retval = target_write_memory(target, target_mem_base + SPARE_OFFS, 4, foob_size / 4, foob); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Writing OOB to IRAM failed"); return retval; } @@ -1163,7 +1163,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, retval = target_write_memory(target, 0x31000100, 4, sizeof(struct dmac_ll) / 4, (uint8_t *)(&dmalist[nll-1])); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not write OOB DMA descriptor to DMAC"); return retval; } @@ -1173,7 +1173,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, /* DMACIntTCClear = ch0 */ retval = target_write_u32(target, 0x31000008, 1); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not set DMACIntTCClear"); return retval; } @@ -1190,7 +1190,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, retval = target_write_u32(target, 0x31000110, 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not set DMACC0Config"); return retval; } @@ -1203,7 +1203,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, } else { /* Start xfer of data from iram to flash using DMA */ retval = lpc32xx_start_slc_dma(nand, foob_size, 1); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("DMA OOB failed"); return retval; } @@ -1211,7 +... [truncated message content] |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-20 13:56:10
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via bba48b057cdc4f26721e06a5310652dcf0e55873 (commit) via 71aba329a3713b5011661bb929d4c5d69b75daae (commit) from 45d5ec2adeefe369d6a9999fcbcad546bf167241 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit bba48b057cdc4f26721e06a5310652dcf0e55873 Author: Antonio Borneo <bor...@gm...> Date: Sun Jun 6 23:59:39 2021 +0200 flash/nor: convert enum in uppercase Change-Id: I7b31be25a651069b63c6dea6cb5e7994184390b1 Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6349 Tested-by: jenkins Reviewed-by: Xiang W <wx...@12...> diff --git a/src/flash/nor/fm3.c b/src/flash/nor/fm3.c index 15a08f701..c5eab5124 100644 --- a/src/flash/nor/fm3.c +++ b/src/flash/nor/fm3.c @@ -33,29 +33,29 @@ #define FLASH_DQ5 0x20 /* Time limit exceeding flag bit (TLOV) position */ enum fm3_variant { - mb9bfxx1, /* Flash Type '1' */ - mb9bfxx2, - mb9bfxx3, - mb9bfxx4, - mb9bfxx5, - mb9bfxx6, - mb9bfxx7, - mb9bfxx8, - - mb9afxx1, /* Flash Type '2' */ - mb9afxx2, - mb9afxx3, - mb9afxx4, - mb9afxx5, - mb9afxx6, - mb9afxx7, - mb9afxx8, + MB9BFXX1, /* Flash Type '1' */ + MB9BFXX2, + MB9BFXX3, + MB9BFXX4, + MB9BFXX5, + MB9BFXX6, + MB9BFXX7, + MB9BFXX8, + + MB9AFXX1, /* Flash Type '2' */ + MB9AFXX2, + MB9AFXX3, + MB9AFXX4, + MB9AFXX5, + MB9AFXX6, + MB9AFXX7, + MB9AFXX8, }; enum fm3_flash_type { - fm3_no_flash_type = 0, - fm3_flash_type1 = 1, - fm3_flash_type2 = 2 + FM3_NO_FLASH_TYPE = 0, + FM3_FLASH_TYPE1 = 1, + FM3_FLASH_TYPE2 = 2 }; struct fm3_flash_bank { @@ -76,53 +76,53 @@ FLASH_BANK_COMMAND_HANDLER(fm3_flash_bank_command) /* Flash type '1' */ if (strcmp(CMD_ARGV[5], "mb9bfxx1.cpu") == 0) { - fm3_info->variant = mb9bfxx1; - fm3_info->flashtype = fm3_flash_type1; + fm3_info->variant = MB9BFXX1; + fm3_info->flashtype = FM3_FLASH_TYPE1; } else if (strcmp(CMD_ARGV[5], "mb9bfxx2.cpu") == 0) { - fm3_info->variant = mb9bfxx2; - fm3_info->flashtype = fm3_flash_type1; + fm3_info->variant = MB9BFXX2; + fm3_info->flashtype = FM3_FLASH_TYPE1; } else if (strcmp(CMD_ARGV[5], "mb9bfxx3.cpu") == 0) { - fm3_info->variant = mb9bfxx3; - fm3_info->flashtype = fm3_flash_type1; + fm3_info->variant = MB9BFXX3; + fm3_info->flashtype = FM3_FLASH_TYPE1; } else if (strcmp(CMD_ARGV[5], "mb9bfxx4.cpu") == 0) { - fm3_info->variant = mb9bfxx4; - fm3_info->flashtype = fm3_flash_type1; + fm3_info->variant = MB9BFXX4; + fm3_info->flashtype = FM3_FLASH_TYPE1; } else if (strcmp(CMD_ARGV[5], "mb9bfxx5.cpu") == 0) { - fm3_info->variant = mb9bfxx5; - fm3_info->flashtype = fm3_flash_type1; + fm3_info->variant = MB9BFXX5; + fm3_info->flashtype = FM3_FLASH_TYPE1; } else if (strcmp(CMD_ARGV[5], "mb9bfxx6.cpu") == 0) { - fm3_info->variant = mb9bfxx6; - fm3_info->flashtype = fm3_flash_type1; + fm3_info->variant = MB9BFXX6; + fm3_info->flashtype = FM3_FLASH_TYPE1; } else if (strcmp(CMD_ARGV[5], "mb9bfxx7.cpu") == 0) { - fm3_info->variant = mb9bfxx7; - fm3_info->flashtype = fm3_flash_type1; + fm3_info->variant = MB9BFXX7; + fm3_info->flashtype = FM3_FLASH_TYPE1; } else if (strcmp(CMD_ARGV[5], "mb9bfxx8.cpu") == 0) { - fm3_info->variant = mb9bfxx8; - fm3_info->flashtype = fm3_flash_type1; + fm3_info->variant = MB9BFXX8; + fm3_info->flashtype = FM3_FLASH_TYPE1; } else if (strcmp(CMD_ARGV[5], "mb9afxx1.cpu") == 0) { /* Flash type '2' */ - fm3_info->variant = mb9afxx1; - fm3_info->flashtype = fm3_flash_type2; + fm3_info->variant = MB9AFXX1; + fm3_info->flashtype = FM3_FLASH_TYPE2; } else if (strcmp(CMD_ARGV[5], "mb9afxx2.cpu") == 0) { - fm3_info->variant = mb9afxx2; - fm3_info->flashtype = fm3_flash_type2; + fm3_info->variant = MB9AFXX2; + fm3_info->flashtype = FM3_FLASH_TYPE2; } else if (strcmp(CMD_ARGV[5], "mb9afxx3.cpu") == 0) { - fm3_info->variant = mb9afxx3; - fm3_info->flashtype = fm3_flash_type2; + fm3_info->variant = MB9AFXX3; + fm3_info->flashtype = FM3_FLASH_TYPE2; } else if (strcmp(CMD_ARGV[5], "mb9afxx4.cpu") == 0) { - fm3_info->variant = mb9afxx4; - fm3_info->flashtype = fm3_flash_type2; + fm3_info->variant = MB9AFXX4; + fm3_info->flashtype = FM3_FLASH_TYPE2; } else if (strcmp(CMD_ARGV[5], "mb9afxx5.cpu") == 0) { - fm3_info->variant = mb9afxx5; - fm3_info->flashtype = fm3_flash_type2; + fm3_info->variant = MB9AFXX5; + fm3_info->flashtype = FM3_FLASH_TYPE2; } else if (strcmp(CMD_ARGV[5], "mb9afxx6.cpu") == 0) { - fm3_info->variant = mb9afxx6; - fm3_info->flashtype = fm3_flash_type2; + fm3_info->variant = MB9AFXX6; + fm3_info->flashtype = FM3_FLASH_TYPE2; } else if (strcmp(CMD_ARGV[5], "mb9afxx7.cpu") == 0) { - fm3_info->variant = mb9afxx7; - fm3_info->flashtype = fm3_flash_type2; + fm3_info->variant = MB9AFXX7; + fm3_info->flashtype = FM3_FLASH_TYPE2; } else if (strcmp(CMD_ARGV[5], "mb9afxx8.cpu") == 0) { - fm3_info->variant = mb9afxx8; - fm3_info->flashtype = fm3_flash_type2; + fm3_info->variant = MB9AFXX8; + fm3_info->flashtype = FM3_FLASH_TYPE2; } /* unknown Flash type */ @@ -219,10 +219,10 @@ static int fm3_erase(struct flash_bank *bank, unsigned int first, u32_flash_type = (uint32_t) fm3_info->flashtype; - if (u32_flash_type == fm3_flash_type1) { + if (u32_flash_type == FM3_FLASH_TYPE1) { u32_flash_seq_address1 = 0x00001550; u32_flash_seq_address2 = 0x00000AA8; - } else if (u32_flash_type == fm3_flash_type2) { + } else if (u32_flash_type == FM3_FLASH_TYPE2) { u32_flash_seq_address1 = 0x00000AA8; u32_flash_seq_address2 = 0x00000554; } else { @@ -368,10 +368,10 @@ static int fm3_write_block(struct flash_bank *bank, const uint8_t *buffer, u32_flash_type = (uint32_t) fm3_info->flashtype; - if (u32_flash_type == fm3_flash_type1) { + if (u32_flash_type == FM3_FLASH_TYPE1) { u32_flash_seq_address1 = 0x00001550; u32_flash_seq_address2 = 0x00000AA8; - } else if (u32_flash_type == fm3_flash_type2) { + } else if (u32_flash_type == FM3_FLASH_TYPE2) { u32_flash_seq_address1 = 0x00000AA8; u32_flash_seq_address2 = 0x00000554; } else { @@ -673,8 +673,8 @@ static int fm3_probe(struct flash_bank *bank) bank->sectors[1].is_erased = -1; bank->sectors[1].is_protected = -1; - if ((fm3_info->variant == mb9bfxx1) - || (fm3_info->variant == mb9afxx1)) { + if ((fm3_info->variant == MB9BFXX1) + || (fm3_info->variant == MB9AFXX1)) { num_pages = 3; bank->size = 64 * 1024; /* bytes */ bank->num_sectors = num_pages; @@ -685,18 +685,18 @@ static int fm3_probe(struct flash_bank *bank) bank->sectors[2].is_protected = -1; } - if ((fm3_info->variant == mb9bfxx2) - || (fm3_info->variant == mb9bfxx4) - || (fm3_info->variant == mb9bfxx5) - || (fm3_info->variant == mb9bfxx6) - || (fm3_info->variant == mb9bfxx7) - || (fm3_info->variant == mb9bfxx8) - || (fm3_info->variant == mb9afxx2) - || (fm3_info->variant == mb9afxx4) - || (fm3_info->variant == mb9afxx5) - || (fm3_info->variant == mb9afxx6) - || (fm3_info->variant == mb9afxx7) - || (fm3_info->variant == mb9afxx8)) { + if ((fm3_info->variant == MB9BFXX2) + || (fm3_info->variant == MB9BFXX4) + || (fm3_info->variant == MB9BFXX5) + || (fm3_info->variant == MB9BFXX6) + || (fm3_info->variant == MB9BFXX7) + || (fm3_info->variant == MB9BFXX8) + || (fm3_info->variant == MB9AFXX2) + || (fm3_info->variant == MB9AFXX4) + || (fm3_info->variant == MB9AFXX5) + || (fm3_info->variant == MB9AFXX6) + || (fm3_info->variant == MB9AFXX7) + || (fm3_info->variant == MB9AFXX8)) { num_pages = 3; bank->size = 128 * 1024; /* bytes */ bank->num_sectors = num_pages; @@ -707,16 +707,16 @@ static int fm3_probe(struct flash_bank *bank) bank->sectors[2].is_protected = -1; } - if ((fm3_info->variant == mb9bfxx4) - || (fm3_info->variant == mb9bfxx5) - || (fm3_info->variant == mb9bfxx6) - || (fm3_info->variant == mb9bfxx7) - || (fm3_info->variant == mb9bfxx8) - || (fm3_info->variant == mb9afxx4) - || (fm3_info->variant == mb9afxx5) - || (fm3_info->variant == mb9afxx6) - || (fm3_info->variant == mb9afxx7) - || (fm3_info->variant == mb9afxx8)) { + if ((fm3_info->variant == MB9BFXX4) + || (fm3_info->variant == MB9BFXX5) + || (fm3_info->variant == MB9BFXX6) + || (fm3_info->variant == MB9BFXX7) + || (fm3_info->variant == MB9BFXX8) + || (fm3_info->variant == MB9AFXX4) + || (fm3_info->variant == MB9AFXX5) + || (fm3_info->variant == MB9AFXX6) + || (fm3_info->variant == MB9AFXX7) + || (fm3_info->variant == MB9AFXX8)) { num_pages = 4; bank->size = 256 * 1024; /* bytes */ bank->num_sectors = num_pages; @@ -727,14 +727,14 @@ static int fm3_probe(struct flash_bank *bank) bank->sectors[3].is_protected = -1; } - if ((fm3_info->variant == mb9bfxx5) - || (fm3_info->variant == mb9bfxx6) - || (fm3_info->variant == mb9bfxx7) - || (fm3_info->variant == mb9bfxx8) - || (fm3_info->variant == mb9afxx5) - || (fm3_info->variant == mb9afxx6) - || (fm3_info->variant == mb9afxx7) - || (fm3_info->variant == mb9afxx8)) { + if ((fm3_info->variant == MB9BFXX5) + || (fm3_info->variant == MB9BFXX6) + || (fm3_info->variant == MB9BFXX7) + || (fm3_info->variant == MB9BFXX8) + || (fm3_info->variant == MB9AFXX5) + || (fm3_info->variant == MB9AFXX6) + || (fm3_info->variant == MB9AFXX7) + || (fm3_info->variant == MB9AFXX8)) { num_pages = 5; bank->size = 384 * 1024; /* bytes */ bank->num_sectors = num_pages; @@ -745,12 +745,12 @@ static int fm3_probe(struct flash_bank *bank) bank->sectors[4].is_protected = -1; } - if ((fm3_info->variant == mb9bfxx6) - || (fm3_info->variant == mb9bfxx7) - || (fm3_info->variant == mb9bfxx8) - || (fm3_info->variant == mb9afxx6) - || (fm3_info->variant == mb9afxx7) - || (fm3_info->variant == mb9afxx8)) { + if ((fm3_info->variant == MB9BFXX6) + || (fm3_info->variant == MB9BFXX7) + || (fm3_info->variant == MB9BFXX8) + || (fm3_info->variant == MB9AFXX6) + || (fm3_info->variant == MB9AFXX7) + || (fm3_info->variant == MB9AFXX8)) { num_pages = 6; bank->size = 512 * 1024; /* bytes */ bank->num_sectors = num_pages; @@ -761,10 +761,10 @@ static int fm3_probe(struct flash_bank *bank) bank->sectors[5].is_protected = -1; } - if ((fm3_info->variant == mb9bfxx7) - || (fm3_info->variant == mb9bfxx8) - || (fm3_info->variant == mb9afxx7) - || (fm3_info->variant == mb9afxx8)) { + if ((fm3_info->variant == MB9BFXX7) + || (fm3_info->variant == MB9BFXX8) + || (fm3_info->variant == MB9AFXX7) + || (fm3_info->variant == MB9AFXX8)) { num_pages = 8; bank->size = 768 * 1024; /* bytes */ bank->num_sectors = num_pages; @@ -780,8 +780,8 @@ static int fm3_probe(struct flash_bank *bank) bank->sectors[7].is_protected = -1; } - if ((fm3_info->variant == mb9bfxx8) - || (fm3_info->variant == mb9afxx8)) { + if ((fm3_info->variant == MB9BFXX8) + || (fm3_info->variant == MB9AFXX8)) { num_pages = 10; bank->size = 1024 * 1024; /* bytes */ bank->num_sectors = num_pages; @@ -827,11 +827,11 @@ static int fm3_chip_erase(struct flash_bank *bank) u32_flash_type = (uint32_t) fm3_info2->flashtype; - if (u32_flash_type == fm3_flash_type1) { + if (u32_flash_type == FM3_FLASH_TYPE1) { LOG_INFO("*** Erasing mb9bfxxx type"); u32_flash_seq_address1 = 0x00001550; u32_flash_seq_address2 = 0x00000AA8; - } else if (u32_flash_type == fm3_flash_type2) { + } else if (u32_flash_type == FM3_FLASH_TYPE2) { LOG_INFO("*** Erasing mb9afxxx type"); u32_flash_seq_address1 = 0x00000AA8; u32_flash_seq_address2 = 0x00000554; diff --git a/src/flash/nor/fm4.c b/src/flash/nor/fm4.c index 2c51e007f..592ccb603 100644 --- a/src/flash/nor/fm4.c +++ b/src/flash/nor/fm4.c @@ -28,17 +28,17 @@ #define WDG_LCK (WDG_BASE + 0xC00) enum fm4_variant { - mb9bfx64, - mb9bfx65, - mb9bfx66, - mb9bfx67, - mb9bfx68, + MB9BFX64, + MB9BFX65, + MB9BFX66, + MB9BFX67, + MB9BFX68, - s6e2cx8, - s6e2cx9, - s6e2cxa, + S6E2CX8, + S6E2CX9, + S6E2CXA, - s6e2dx, + S6E2DX, }; struct fm4_flash_bank { @@ -350,19 +350,19 @@ static int mb9bf_probe(struct flash_bank *bank) uint32_t flash_addr = bank->base; switch (fm4_bank->variant) { - case mb9bfx64: + case MB9BFX64: bank->num_sectors = 8; break; - case mb9bfx65: + case MB9BFX65: bank->num_sectors = 10; break; - case mb9bfx66: + case MB9BFX66: bank->num_sectors = 12; break; - case mb9bfx67: + case MB9BFX67: bank->num_sectors = 16; break; - case mb9bfx68: + case MB9BFX68: bank->num_sectors = 20; break; default: @@ -421,13 +421,13 @@ static int s6e2cc_probe(struct flash_bank *bank) } switch (fm4_bank->variant) { - case s6e2cx8: + case S6E2CX8: num_sectors = (fm4_bank->macro_nr == 0) ? 20 : 0; break; - case s6e2cx9: + case S6E2CX9: num_sectors = (fm4_bank->macro_nr == 0) ? 20 : 12; break; - case s6e2cxa: + case S6E2CXA: num_sectors = 20; break; default: @@ -503,19 +503,19 @@ static int fm4_probe(struct flash_bank *bank) } switch (fm4_bank->variant) { - case mb9bfx64: - case mb9bfx65: - case mb9bfx66: - case mb9bfx67: - case mb9bfx68: + case MB9BFX64: + case MB9BFX65: + case MB9BFX66: + case MB9BFX67: + case MB9BFX68: retval = mb9bf_probe(bank); break; - case s6e2cx8: - case s6e2cx9: - case s6e2cxa: + case S6E2CX8: + case S6E2CX9: + case S6E2CXA: retval = s6e2cc_probe(bank); break; - case s6e2dx: + case S6E2DX: retval = s6e2dh_probe(bank); break; default: @@ -550,31 +550,31 @@ static int fm4_get_info_command(struct flash_bank *bank, struct command_invocati } switch (fm4_bank->variant) { - case mb9bfx64: + case MB9BFX64: name = "MB9BFx64"; break; - case mb9bfx65: + case MB9BFX65: name = "MB9BFx65"; break; - case mb9bfx66: + case MB9BFX66: name = "MB9BFx66"; break; - case mb9bfx67: + case MB9BFX67: name = "MB9BFx67"; break; - case mb9bfx68: + case MB9BFX68: name = "MB9BFx68"; break; - case s6e2cx8: + case S6E2CX8: name = "S6E2Cx8"; break; - case s6e2cx9: + case S6E2CX9: name = "S6E2Cx9"; break; - case s6e2cxa: + case S6E2CXA: name = "S6E2CxA"; break; - case s6e2dx: + case S6E2DX: name = "S6E2Dx"; break; default: @@ -583,9 +583,9 @@ static int fm4_get_info_command(struct flash_bank *bank, struct command_invocati } switch (fm4_bank->variant) { - case s6e2cx8: - case s6e2cx9: - case s6e2cxa: + case S6E2CX8: + case S6E2CX9: + case S6E2CXA: command_print_sameline(cmd, "%s MainFlash Macro #%i", name, fm4_bank->macro_nr); break; default: @@ -617,15 +617,15 @@ static int mb9bf_bank_setup(struct flash_bank *bank, const char *variant) struct fm4_flash_bank *fm4_bank = bank->driver_priv; if (fm4_name_match(variant, "MB9BFx64")) { - fm4_bank->variant = mb9bfx64; + fm4_bank->variant = MB9BFX64; } else if (fm4_name_match(variant, "MB9BFx65")) { - fm4_bank->variant = mb9bfx65; + fm4_bank->variant = MB9BFX65; } else if (fm4_name_match(variant, "MB9BFx66")) { - fm4_bank->variant = mb9bfx66; + fm4_bank->variant = MB9BFX66; } else if (fm4_name_match(variant, "MB9BFx67")) { - fm4_bank->variant = mb9bfx67; + fm4_bank->variant = MB9BFX67; } else if (fm4_name_match(variant, "MB9BFx68")) { - fm4_bank->variant = mb9bfx68; + fm4_bank->variant = MB9BFX68; } else { LOG_WARNING("MB9BF variant %s not recognized.", variant); return ERROR_FLASH_OPER_UNSUPPORTED; @@ -639,11 +639,11 @@ static int s6e2cc_bank_setup(struct flash_bank *bank, const char *variant) struct fm4_flash_bank *fm4_bank = bank->driver_priv; if (fm4_name_match(variant, "S6E2Cx8")) { - fm4_bank->variant = s6e2cx8; + fm4_bank->variant = S6E2CX8; } else if (fm4_name_match(variant, "S6E2Cx9")) { - fm4_bank->variant = s6e2cx9; + fm4_bank->variant = S6E2CX9; } else if (fm4_name_match(variant, "S6E2CxA")) { - fm4_bank->variant = s6e2cxa; + fm4_bank->variant = S6E2CXA; } else { LOG_WARNING("S6E2CC variant %s not recognized.", variant); return ERROR_FLASH_OPER_UNSUPPORTED; @@ -677,7 +677,7 @@ FLASH_BANK_COMMAND_HANDLER(fm4_flash_bank_command) else if (fm4_name_match(variant, "S6E2Cx")) ret = s6e2cc_bank_setup(bank, variant); else if (fm4_name_match(variant, "S6E2Dx")) { - fm4_bank->variant = s6e2dx; + fm4_bank->variant = S6E2DX; ret = ERROR_OK; } else { LOG_WARNING("Family %s not recognized.", variant); diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c index 28dc5c3b3..754957e54 100644 --- a/src/flash/nor/lpc2000.c +++ b/src/flash/nor/lpc2000.c @@ -284,15 +284,15 @@ #define LPC11XX_REG_SECTORS 24 typedef enum { - lpc2000_v1, - lpc2000_v2, - lpc1700, - lpc4300, - lpc800, - lpc1100, - lpc1500, - lpc54100, - lpc_auto, + LPC2000_V1, + LPC2000_V2, + LPC1700, + LPC4300, + LPC800, + LPC1100, + LPC1500, + LPC54100, + LPC_AUTO, } lpc2000_variant; struct lpc2000_flash_bank { @@ -342,7 +342,7 @@ static int lpc2000_build_sector_list(struct flash_bank *bank) /* default to a 4096 write buffer */ lpc2000_info->cmd51_max_buffer = 4096; - if (lpc2000_info->variant == lpc2000_v1) { + if (lpc2000_info->variant == LPC2000_V1) { lpc2000_info->cmd51_dst_boundary = 512; lpc2000_info->checksum_vector = 5; lpc2000_info->iap_max_stack = 128; @@ -387,7 +387,7 @@ static int lpc2000_build_sector_list(struct flash_bank *bank) LOG_ERROR("BUG: unknown bank->size encountered"); exit(-1); } - } else if (lpc2000_info->variant == lpc2000_v2) { + } else if (lpc2000_info->variant == LPC2000_V2) { lpc2000_info->cmd51_dst_boundary = 256; lpc2000_info->checksum_vector = 5; lpc2000_info->iap_max_stack = 128; @@ -453,7 +453,7 @@ static int lpc2000_build_sector_list(struct flash_bank *bank) bank->sectors[i].is_protected = 1; } } - } else if (lpc2000_info->variant == lpc1700) { + } else if (lpc2000_info->variant == LPC1700) { lpc2000_info->cmd51_dst_boundary = 256; lpc2000_info->checksum_vector = 7; lpc2000_info->iap_max_stack = 128; @@ -502,7 +502,7 @@ static int lpc2000_build_sector_list(struct flash_bank *bank) bank->sectors[i].is_erased = -1; bank->sectors[i].is_protected = 1; } - } else if (lpc2000_info->variant == lpc4300) { + } else if (lpc2000_info->variant == LPC4300) { lpc2000_info->cmd51_dst_boundary = 512; lpc2000_info->checksum_vector = 7; lpc2000_info->iap_max_stack = 208; @@ -533,7 +533,7 @@ static int lpc2000_build_sector_list(struct flash_bank *bank) bank->sectors[i].is_protected = 1; } - } else if (lpc2000_info->variant == lpc800) { + } else if (lpc2000_info->variant == LPC800) { lpc2000_info->cmd51_dst_boundary = 64; lpc2000_info->checksum_vector = 7; lpc2000_info->iap_max_stack = 208; /* 148byte for LPC81x,208byte for LPC82x. */ @@ -577,7 +577,7 @@ static int lpc2000_build_sector_list(struct flash_bank *bank) bank->sectors[i].is_protected = 1; } - } else if (lpc2000_info->variant == lpc1100) { + } else if (lpc2000_info->variant == LPC1100) { lpc2000_info->cmd51_dst_boundary = 256; lpc2000_info->checksum_vector = 7; lpc2000_info->iap_max_stack = 128; @@ -607,7 +607,7 @@ static int lpc2000_build_sector_list(struct flash_bank *bank) bank->sectors[i].is_protected = 1; } - } else if (lpc2000_info->variant == lpc1500) { + } else if (lpc2000_info->variant == LPC1500) { lpc2000_info->cmd51_dst_boundary = 256; lpc2000_info->checksum_vector = 7; lpc2000_info->iap_max_stack = 128; @@ -638,7 +638,7 @@ static int lpc2000_build_sector_list(struct flash_bank *bank) bank->sectors[i].is_protected = 1; } - } else if (lpc2000_info->variant == lpc54100) { + } else if (lpc2000_info->variant == LPC54100) { lpc2000_info->cmd51_dst_boundary = 256; lpc2000_info->checksum_vector = 7; lpc2000_info->iap_max_stack = 128; @@ -697,18 +697,18 @@ static int lpc2000_iap_working_area_init(struct flash_bank *bank, struct working /* write IAP code to working area */ switch (lpc2000_info->variant) { - case lpc800: - case lpc1100: - case lpc1500: - case lpc1700: - case lpc4300: - case lpc54100: - case lpc_auto: + case LPC800: + case LPC1100: + case LPC1500: + case LPC1700: + case LPC4300: + case LPC54100: + case LPC_AUTO: target_buffer_set_u32(target, jump_gate, ARMV4_5_T_BX(12)); target_buffer_set_u32(target, jump_gate + 4, ARMV5_T_BKPT(0)); break; - case lpc2000_v1: - case lpc2000_v2: + case LPC2000_V1: + case LPC2000_V2: target_buffer_set_u32(target, jump_gate, ARMV4_5_BX(12)); target_buffer_set_u32(target, jump_gate + 4, ARMV4_5_B(0xfffffe, 0)); break; @@ -740,28 +740,28 @@ static int lpc2000_iap_call(struct flash_bank *bank, struct working_area *iap_wo uint32_t iap_entry_point = 0; /* to make compiler happier */ switch (lpc2000_info->variant) { - case lpc800: - case lpc1100: - case lpc1700: - case lpc_auto: + case LPC800: + case LPC1100: + case LPC1700: + case LPC_AUTO: armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; armv7m_info.core_mode = ARM_MODE_THREAD; iap_entry_point = 0x1fff1ff1; break; - case lpc1500: - case lpc54100: + case LPC1500: + case LPC54100: armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; armv7m_info.core_mode = ARM_MODE_THREAD; iap_entry_point = 0x03000205; break; - case lpc2000_v1: - case lpc2000_v2: + case LPC2000_V1: + case LPC2000_V2: arm_algo.common_magic = ARM_COMMON_MAGIC; arm_algo.core_mode = ARM_MODE_SVC; arm_algo.core_state = ARM_STATE_ARM; iap_entry_point = 0x7ffffff1; break; - case lpc4300: + case LPC4300: armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; armv7m_info.core_mode = ARM_MODE_THREAD; /* read out IAP entry point from ROM driver table at 0x10400100 */ @@ -802,13 +802,13 @@ static int lpc2000_iap_call(struct flash_bank *bank, struct working_area *iap_wo buf_set_u32(reg_params[2].value, 0, 32, iap_entry_point); switch (lpc2000_info->variant) { - case lpc800: - case lpc1100: - case lpc1500: - case lpc1700: - case lpc4300: - case lpc54100: - case lpc_auto: + case LPC800: + case LPC1100: + case LPC1500: + case LPC1700: + case LPC4300: + case LPC54100: + case LPC_AUTO: /* IAP stack */ init_reg_param(®_params[3], "sp", 32, PARAM_OUT); buf_set_u32(reg_params[3].value, 0, 32, @@ -822,8 +822,8 @@ static int lpc2000_iap_call(struct flash_bank *bank, struct working_area *iap_wo target_run_algorithm(target, 2, mem_params, 5, reg_params, iap_working_area->address, 0, 10000, &armv7m_info); break; - case lpc2000_v1: - case lpc2000_v2: + case LPC2000_V1: + case LPC2000_V2: /* IAP stack */ init_reg_param(®_params[3], "sp_svc", 32, PARAM_OUT); buf_set_u32(reg_params[3].value, 0, 32, @@ -879,7 +879,7 @@ static int lpc2000_iap_blank_check(struct flash_bank *bank, unsigned int first, return retval; struct lpc2000_flash_bank *lpc2000_info = bank->driver_priv; - if (lpc2000_info->variant == lpc4300) + if (lpc2000_info->variant == LPC4300) param_table[2] = lpc2000_info->lpc4300_bank; for (unsigned int i = first; i <= last && retval == ERROR_OK; i++) { @@ -929,23 +929,23 @@ FLASH_BANK_COMMAND_HANDLER(lpc2000_flash_bank_command) bank->driver_priv = lpc2000_info; if (strcmp(CMD_ARGV[6], "lpc2000_v1") == 0) { - lpc2000_info->variant = lpc2000_v1; + lpc2000_info->variant = LPC2000_V1; } else if (strcmp(CMD_ARGV[6], "lpc2000_v2") == 0) { - lpc2000_info->variant = lpc2000_v2; + lpc2000_info->variant = LPC2000_V2; } else if (strcmp(CMD_ARGV[6], "lpc1700") == 0 || strcmp(CMD_ARGV[6], "lpc4000") == 0) { - lpc2000_info->variant = lpc1700; + lpc2000_info->variant = LPC1700; } else if (strcmp(CMD_ARGV[6], "lpc1800") == 0 || strcmp(CMD_ARGV[6], "lpc4300") == 0) { - lpc2000_info->variant = lpc4300; + lpc2000_info->variant = LPC4300; } else if (strcmp(CMD_ARGV[6], "lpc800") == 0) { - lpc2000_info->variant = lpc800; + lpc2000_info->variant = LPC800; } else if (strcmp(CMD_ARGV[6], "lpc1100") == 0) { - lpc2000_info->variant = lpc1100; + lpc2000_info->variant = LPC1100; } else if (strcmp(CMD_ARGV[6], "lpc1500") == 0) { - lpc2000_info->variant = lpc1500; + lpc2000_info->variant = LPC1500; } else if (strcmp(CMD_ARGV[6], "lpc54100") == 0) { - lpc2000_info->variant = lpc54100; + lpc2000_info->variant = LPC54100; } else if (strcmp(CMD_ARGV[6], "auto") == 0) { - lpc2000_info->variant = lpc_auto; + lpc2000_info->variant = LPC_AUTO; } else { LOG_ERROR("unknown LPC2000 variant: %s", CMD_ARGV[6]); free(lpc2000_info); @@ -993,7 +993,7 @@ static int lpc2000_erase(struct flash_bank *bank, unsigned int first, param_table[0] = first; param_table[1] = last; - if (lpc2000_info->variant == lpc4300) + if (lpc2000_info->variant == LPC4300) param_table[2] = lpc2000_info->lpc4300_bank; else param_table[2] = lpc2000_info->cclk; @@ -1006,7 +1006,7 @@ static int lpc2000_erase(struct flash_bank *bank, unsigned int first, if (retval != ERROR_OK) return retval; - if (lpc2000_info->variant == lpc4300) + if (lpc2000_info->variant == LPC4300) /* Init IAP Anyway */ lpc2000_iap_call(bank, iap_working_area, 49, param_table, result_table); @@ -1030,7 +1030,7 @@ static int lpc2000_erase(struct flash_bank *bank, unsigned int first, if (retval == ERROR_OK) { /* Erase sectors */ param_table[2] = lpc2000_info->cclk; - if (lpc2000_info->variant == lpc4300) + if (lpc2000_info->variant == LPC4300) param_table[3] = lpc2000_info->lpc4300_bank; status_code = lpc2000_iap_call(bank, iap_working_area, 52, param_table, result_table); @@ -1134,7 +1134,7 @@ static int lpc2000_write(struct flash_bank *bank, const uint8_t *buffer, uint32_ uint32_t param_table[5] = {0}; uint32_t result_table[4]; - if (lpc2000_info->variant == lpc4300) + if (lpc2000_info->variant == LPC4300) /* Init IAP Anyway */ lpc2000_iap_call(bank, iap_working_area, 49, param_table, result_table); @@ -1149,7 +1149,7 @@ static int lpc2000_write(struct flash_bank *bank, const uint8_t *buffer, uint32_ param_table[0] = first_sector; param_table[1] = last_sector; - if (lpc2000_info->variant == lpc4300) + if (lpc2000_info->variant == LPC4300) param_table[2] = lpc2000_info->lpc4300_bank; else param_table[2] = lpc2000_info->cclk; @@ -1280,7 +1280,7 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank) switch (part_id) { case LPC1110_1: case LPC1110_2: - lpc2000_info->variant = lpc1100; + lpc2000_info->variant = LPC1100; bank->size = 4 * 1024; break; @@ -1296,7 +1296,7 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank) case LPC11E11_101: case LPC1311: case LPC1311_1: - lpc2000_info->variant = lpc1100; + lpc2000_info->variant = LPC1100; bank->size = 8 * 1024; break; @@ -1316,7 +1316,7 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank) case LPC11U12_201_1: case LPC11U12_201_2: case LPC1342: - lpc2000_info->variant = lpc1100; + lpc2000_info->variant = LPC1100; bank->size = 16 * 1024; break; @@ -1331,7 +1331,7 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank) case LPC11U13_201_1: case LPC11U13_201_2: case LPC11U23_301: - lpc2000_info->variant = lpc1100; + lpc2000_info->variant = LPC1100; bank->size = 24 * 1024; break; @@ -1359,18 +1359,18 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank) case LPC1343: case LPC1343_1: case LPC1345: - lpc2000_info->variant = lpc1100; + lpc2000_info->variant = LPC1100; bank->size = 32 * 1024; break; case LPC1751_1: case LPC1751_2: - lpc2000_info->variant = lpc1700; + lpc2000_info->variant = LPC1700; bank->size = 32 * 1024; break; case LPC11U34_311: - lpc2000_info->variant = lpc1100; + lpc2000_info->variant = LPC1100; bank->size = 40 * 1024; break; @@ -1378,12 +1378,12 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank) case LPC11U34_421: case LPC1316: case LPC1346: - lpc2000_info->variant = lpc1100; + lpc2000_info->variant = LPC1100; bank->size = 48 * 1024; break; case LPC1114_333_1: - lpc2000_info->variant = lpc1100; + lpc2000_info->variant = LPC1100; bank->size = 56 * 1024; break; @@ -1394,19 +1394,19 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank) case LPC11U66: case LPC1317: case LPC1347: - lpc2000_info->variant = lpc1100; + lpc2000_info->variant = LPC1100; bank->size = 64 * 1024; break; case LPC1752: case LPC4072: - lpc2000_info->variant = lpc1700; + lpc2000_info->variant = LPC1700; bank->size = 64 * 1024; break; case LPC11E36_501: case LPC11U36_401: - lpc2000_info->variant = lpc1100; + lpc2000_info->variant = LPC1100; bank->size = 96 * 1024; break; @@ -1419,7 +1419,7 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank) case LPC11E68: case LPC11U67_1: case LPC11U67_2: - lpc2000_info->variant = lpc1100; + lpc2000_info->variant = LPC1100; bank->size = 128 * 1024; break; @@ -1427,13 +1427,13 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank) case LPC1764: case LPC1774: case LPC4074: - lpc2000_info->variant = lpc1700; + lpc2000_info->variant = LPC1700; bank->size = 128 * 1024; break; case LPC11U68_1: case LPC11U68_2: - lpc2000_info->variant = lpc1100; + lpc2000_info->variant = LPC1100; bank->size = 256 * 1024; break; @@ -1445,7 +1445,7 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank) case LPC1785: case LPC1786: case LPC4076: - lpc2000_info->variant = lpc1700; + lpc2000_info->variant = LPC1700; bank->size = 256 * 1024; break; @@ -1460,17 +1460,17 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank) case LPC1788: case LPC4078: case LPC4088: - lpc2000_info->variant = lpc1700; + lpc2000_info->variant = LPC1700; bank->size = 512 * 1024; break; case LPC810_021: - lpc2000_info->variant = lpc800; + lpc2000_info->variant = LPC800; bank->size = 4 * 1024; break; case LPC811_001: - lpc2000_info->variant = lpc800; + lpc2000_info->variant = LPC800; bank->size = 8 * 1024; break; @@ -1480,13 +1480,13 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank) case LPC812_101_3: case LPC822_101: case LPC822_101_1: - lpc2000_info->variant = lpc800; + lpc2000_info->variant = LPC800; bank->size = 16 * 1024; break; case LPC824_201: case LPC824_201_1: - lpc2000_info->variant = lpc800; + lpc2000_info->variant = LPC800; bank->size = 32 * 1024; break; @@ -1494,7 +1494,7 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank) case NHS3100: case NHS3152: case NHS3153: - lpc2000_info->variant = lpc800; + lpc2000_info->variant = LPC800; bank->size = 30 * 1024; break; @@ -1505,7 +1505,7 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank) case LPC845_301_1: case LPC845_301_2: case LPC845_301_3: - lpc2000_info->variant = lpc800; + lpc2000_info->variant = LPC800; bank->size = 64 * 1024; break; @@ -1524,11 +1524,11 @@ static int lpc2000_probe(struct flash_bank *bank) struct lpc2000_flash_bank *lpc2000_info = bank->driver_priv; if (!lpc2000_info->probed) { - if (lpc2000_info->variant == lpc_auto) { + if (lpc2000_info->variant == LPC_AUTO) { status = lpc2000_auto_probe_flash(bank); if (status != ERROR_OK) return status; - } else if (lpc2000_info->variant == lpc1100 || lpc2000_info->variant == lpc1700) { + } else if (lpc2000_info->variant == LPC1100 || lpc2000_info->variant == LPC1700) { status = get_lpc2000_part_id(bank, &part_id); if (status == LPC2000_CMD_SUCCESS) LOG_INFO("If auto-detection fails for this part, please email " commit 71aba329a3713b5011661bb929d4c5d69b75daae Author: Antonio Borneo <bor...@gm...> Date: Sun Jun 6 18:29:04 2021 +0200 target/nds32: use lowercase for C variables Convert to lowercase the name of arrays. Convert to macro two uppercase const variables. Change-Id: Ic6f5cad38722dfdf78d662ff4893e94482ab423d Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6348 Tested-by: jenkins Reviewed-by: Marc Schink <de...@za...> Reviewed-by: Xiang W <wx...@12...> diff --git a/src/target/nds32.c b/src/target/nds32.c index 39d2c0067..372f82d0c 100644 --- a/src/target/nds32.c +++ b/src/target/nds32.c @@ -27,9 +27,6 @@ #include "nds32_tlb.h" #include "nds32_disassembler.h" -const int NDS32_BREAK_16 = 0x00EA; /* 0xEA00 */ -const int NDS32_BREAK_32 = 0x0A000064; /* 0x6400000A */ - struct nds32_edm_operation nds32_edm_ops[NDS32_EDM_OPERATION_MAX_NUM]; uint32_t nds32_edm_ops_num; @@ -47,7 +44,7 @@ const char *nds32_debug_type_name[11] = { "LOAD STORE GLOBAL STOP", }; -static const int NDS32_LM_SIZE_TABLE[16] = { +static const int nds32_lm_size_table[16] = { 4 * 1024, 8 * 1024, 16 * 1024, @@ -61,7 +58,7 @@ static const int NDS32_LM_SIZE_TABLE[16] = { 2 * 1024, }; -static const int NDS32_LINE_SIZE_TABLE[6] = { +static const int nds32_line_size_table[6] = { 0, 8, 16, @@ -1622,11 +1619,11 @@ int nds32_config(struct nds32 *nds32) uint32_t size_index; nds32_get_mapped_reg(nds32, MR6, &value_mr6); size_index = (value_mr6 >> 1) & 0xF; - nds32->memory.ilm_size = NDS32_LM_SIZE_TABLE[size_index]; + nds32->memory.ilm_size = nds32_lm_size_table[size_index]; nds32_get_mapped_reg(nds32, MR7, &value_mr7); size_index = (value_mr7 >> 1) & 0xF; - nds32->memory.dlm_size = NDS32_LM_SIZE_TABLE[size_index]; + nds32->memory.dlm_size = nds32_lm_size_table[size_index]; return ERROR_OK; } @@ -1697,8 +1694,8 @@ int nds32_cache_sync(struct target *target, target_addr_t address, uint32_t leng struct nds32 *nds32 = target_to_nds32(target); struct nds32_cache *dcache = &(nds32->memory.dcache); struct nds32_cache *icache = &(nds32->memory.icache); - uint32_t dcache_line_size = NDS32_LINE_SIZE_TABLE[dcache->line_size]; - uint32_t icache_line_size = NDS32_LINE_SIZE_TABLE[icache->line_size]; + uint32_t dcache_line_size = nds32_line_size_table[dcache->line_size]; + uint32_t icache_line_size = nds32_line_size_table[icache->line_size]; uint32_t cur_address; int result; uint32_t start_line, end_line; diff --git a/src/target/nds32_cmd.c b/src/target/nds32_cmd.c index f7647c385..3931707be 100644 --- a/src/target/nds32_cmd.c +++ b/src/target/nds32_cmd.c @@ -28,12 +28,12 @@ extern struct nds32_edm_operation nds32_edm_ops[NDS32_EDM_OPERATION_MAX_NUM]; extern uint32_t nds32_edm_ops_num; -static const char *const NDS_MEMORY_ACCESS_NAME[] = { +static const char *const nds_memory_access_name[] = { "BUS", "CPU", }; -static const char *const NDS_MEMORY_SELECT_NAME[] = { +static const char *const nds_memory_select_name[] = { "AUTO", "MEM", "ILM", @@ -84,13 +84,13 @@ COMMAND_HANDLER(handle_nds32_memory_access_command) memory->access_channel = NDS_MEMORY_ACC_CPU; LOG_DEBUG("memory access channel is changed to %s", - NDS_MEMORY_ACCESS_NAME[memory->access_channel]); + nds_memory_access_name[memory->access_channel]); aice_memory_access(aice, memory->access_channel); } else { command_print(CMD, "%s: memory access channel: %s", target_name(target), - NDS_MEMORY_ACCESS_NAME[memory->access_channel]); + nds_memory_access_name[memory->access_channel]); } return ERROR_OK; @@ -147,7 +147,7 @@ COMMAND_HANDLER(handle_nds32_memory_mode_command) command_print(CMD, "%s: memory mode: %s", target_name(target), - NDS_MEMORY_SELECT_NAME[nds32->memory.mode]); + nds_memory_select_name[nds32->memory.mode]); return ERROR_OK; } diff --git a/src/target/nds32_insn.h b/src/target/nds32_insn.h index eb6664517..4e0b2d53b 100644 --- a/src/target/nds32_insn.h +++ b/src/target/nds32_insn.h @@ -72,7 +72,7 @@ #define FMTDR(a, b) (0x6A000049 | ((a) << 20) | ((b) << 15)) /* break instructions */ -extern const int NDS32_BREAK_16; -extern const int NDS32_BREAK_32; +#define NDS32_BREAK_16 (0x00EA) +#define NDS32_BREAK_32 (0x0A000064) #endif /* OPENOCD_TARGET_NDS32_INSN_H */ ----------------------------------------------------------------------- Summary of changes: src/flash/nor/fm3.c | 204 ++++++++++++++++++++++++------------------------ src/flash/nor/fm4.c | 94 +++++++++++----------- src/flash/nor/lpc2000.c | 168 +++++++++++++++++++-------------------- src/target/nds32.c | 15 ++-- src/target/nds32_cmd.c | 10 +-- src/target/nds32_insn.h | 4 +- 6 files changed, 246 insertions(+), 249 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-20 13:55:01
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 45d5ec2adeefe369d6a9999fcbcad546bf167241 (commit) via e4c0f45a5f01b202b916deb950485c67c4a6fb10 (commit) via fceb29d03ff9b2829be2cadd64d09d264c568349 (commit) from b08e27323a0e0f6daa9bacd026876c103bf1133f (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 45d5ec2adeefe369d6a9999fcbcad546bf167241 Author: Antonio Borneo <bor...@gm...> Date: Thu Apr 29 00:31:29 2021 +0200 flash: use lowercase for C variables Change-Id: I1c3cb5d1c8c0d73adb3c7320a1b8e3940183cd17 Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6347 Tested-by: jenkins Reviewed-by: Marc Schink <de...@za...> Reviewed-by: Xiang W <wx...@12...> diff --git a/src/flash/nand/mxc.c b/src/flash/nand/mxc.c index 90027070f..1fe7d30d2 100644 --- a/src/flash/nand/mxc.c +++ b/src/flash/nand/mxc.c @@ -207,9 +207,9 @@ static int mxc_init(struct nand_device *nand) int validate_target_result; uint16_t buffsize_register_content; uint32_t sreg_content; - uint32_t SREG = MX2_FMCR; - uint32_t SEL_16BIT = MX2_FMCR_NF_16BIT_SEL; - uint32_t SEL_FMS = MX2_FMCR_NF_FMS; + uint32_t sreg = MX2_FMCR; + uint32_t sel_16bit = MX2_FMCR_NF_16BIT_SEL; + uint32_t sel_fms = MX2_FMCR_NF_FMS; int retval; uint16_t nand_status_content; /* @@ -226,27 +226,27 @@ static int mxc_init(struct nand_device *nand) mxc_nf_info->flags.one_kb_sram = 0; if (mxc_nf_info->mxc_version == MXC_VERSION_MX31) { - SREG = MX3_PCSR; - SEL_16BIT = MX3_PCSR_NF_16BIT_SEL; - SEL_FMS = MX3_PCSR_NF_FMS; + sreg = MX3_PCSR; + sel_16bit = MX3_PCSR_NF_16BIT_SEL; + sel_fms = MX3_PCSR_NF_FMS; } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX25) { - SREG = MX25_RCSR; - SEL_16BIT = MX25_RCSR_NF_16BIT_SEL; - SEL_FMS = MX25_RCSR_NF_FMS; + sreg = MX25_RCSR; + sel_16bit = MX25_RCSR_NF_16BIT_SEL; + sel_fms = MX25_RCSR_NF_FMS; } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX35) { - SREG = MX35_RCSR; - SEL_16BIT = MX35_RCSR_NF_16BIT_SEL; - SEL_FMS = MX35_RCSR_NF_FMS; + sreg = MX35_RCSR; + sel_16bit = MX35_RCSR_NF_16BIT_SEL; + sel_fms = MX35_RCSR_NF_FMS; } - target_read_u32(target, SREG, &sreg_content); + target_read_u32(target, sreg, &sreg_content); if (!nand->bus_width) { /* bus_width not yet defined. Read it from MXC_FMCR */ - nand->bus_width = (sreg_content & SEL_16BIT) ? 16 : 8; + nand->bus_width = (sreg_content & sel_16bit) ? 16 : 8; } else { /* bus_width forced in soft. Sync it to MXC_FMCR */ - sreg_content |= ((nand->bus_width == 16) ? SEL_16BIT : 0x00000000); - target_write_u32(target, SREG, sreg_content); + sreg_content |= ((nand->bus_width == 16) ? sel_16bit : 0x00000000); + target_write_u32(target, sreg, sreg_content); } if (nand->bus_width == 16) LOG_DEBUG("MXC_NF : bus is 16-bit width"); @@ -254,10 +254,10 @@ static int mxc_init(struct nand_device *nand) LOG_DEBUG("MXC_NF : bus is 8-bit width"); if (!nand->page_size) - nand->page_size = (sreg_content & SEL_FMS) ? 2048 : 512; + nand->page_size = (sreg_content & sel_fms) ? 2048 : 512; else { - sreg_content |= ((nand->page_size == 2048) ? SEL_FMS : 0x00000000); - target_write_u32(target, SREG, sreg_content); + sreg_content |= ((nand->page_size == 2048) ? sel_fms : 0x00000000); + target_write_u32(target, sreg, sreg_content); } if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) { LOG_ERROR("NAND controller have only 1 kb SRAM, so " @@ -649,18 +649,18 @@ static int mxc_read_page(struct nand_device *nand, uint32_t page, } if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) { - uint32_t SPARE_BUFFER3; + uint32_t spare_buffer3; /* BI-swap - work-around of mxc NFC for NAND device with page == 2k */ target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1); if (nfc_is_v1()) - SPARE_BUFFER3 = MXC_NF_V1_SPARE_BUFFER3 + 4; + spare_buffer3 = MXC_NF_V1_SPARE_BUFFER3 + 4; else - SPARE_BUFFER3 = MXC_NF_V2_SPARE_BUFFER3; - target_read_u16(target, SPARE_BUFFER3, &swap2); + spare_buffer3 = MXC_NF_V2_SPARE_BUFFER3; + target_read_u16(target, spare_buffer3, &swap2); new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8); swap2 = (swap1 << 8) | (swap2 & 0xFF); target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1); - target_write_u16(target, SPARE_BUFFER3, swap2); + target_write_u16(target, spare_buffer3, swap2); } if (data) diff --git a/src/flash/nor/at91sam7.c b/src/flash/nor/at91sam7.c index 88f489f60..d3eadc786 100644 --- a/src/flash/nor/at91sam7.c +++ b/src/flash/nor/at91sam7.c @@ -104,11 +104,11 @@ static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode); static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout); static int at91sam7_flash_command(struct flash_bank *bank, uint8_t cmd, uint16_t pagen); -static const uint32_t MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 }; -static const uint32_t MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 }; -static const uint32_t MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 }; +static const uint32_t mc_fmr[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 }; +static const uint32_t mc_fcr[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 }; +static const uint32_t mc_fsr[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 }; -static const char *EPROC[8] = { +static const char *eproc[8] = { "Unknown", "ARM946-E", "ARM7TDMI", "Unknown", "ARM920T", "ARM926EJ-S", "Unknown", "Unknown" }; @@ -179,7 +179,7 @@ static long SRAMSIZ[16] = { static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number) { uint32_t fsr; - target_read_u32(target, MC_FSR[bank_number], &fsr); + target_read_u32(target, mc_fsr[bank_number], &fsr); return fsr; } @@ -290,7 +290,7 @@ static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode) LOG_DEBUG("fmcn[%i]: %i", bank->bank_number, (int)(fmcn)); fmr = fmcn << 16 | fws << 8; - target_write_u32(target, MC_FMR[bank->bank_number], fmr); + target_write_u32(target, mc_fmr[bank->bank_number], fmr); } at91sam7_info->flashmode = mode; @@ -329,7 +329,7 @@ static int at91sam7_flash_command(struct flash_bank *bank, uint8_t cmd, uint16_t struct target *target = bank->target; fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd; - target_write_u32(target, MC_FCR[bank->bank_number], fcr); + target_write_u32(target, mc_fcr[bank->bank_number], fcr); LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u", fcr, bank->bank_number + 1, @@ -993,7 +993,7 @@ static int get_at91sam7_info(struct flash_bank *bank, struct command_invocation "Flashsize: 0x%8.8" PRIx32 "\n", at91sam7_info->cidr, at91sam7_info->cidr_arch, - EPROC[at91sam7_info->cidr_eproc], + eproc[at91sam7_info->cidr_eproc], at91sam7_info->cidr_version, bank->size); diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c index 9598345c6..aa4171e0c 100644 --- a/src/flash/nor/stm32l4x.c +++ b/src/flash/nor/stm32l4x.c @@ -1320,10 +1320,10 @@ static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id) int retval; /* try reading possible IDCODE registers, in the following order */ - uint32_t DBGMCU_IDCODE[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5}; + uint32_t dbgmcu_idcode[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5}; - for (unsigned int i = 0; i < ARRAY_SIZE(DBGMCU_IDCODE); i++) { - retval = target_read_u32(bank->target, DBGMCU_IDCODE[i], id); + for (unsigned int i = 0; i < ARRAY_SIZE(dbgmcu_idcode); i++) { + retval = target_read_u32(bank->target, dbgmcu_idcode[i], id); if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff)) return ERROR_OK; } diff --git a/src/flash/nor/tms470.c b/src/flash/nor/tms470.c index 8284938f9..f1eba9cd3 100644 --- a/src/flash/nor/tms470.c +++ b/src/flash/nor/tms470.c @@ -39,7 +39,7 @@ struct tms470_flash_bank { }; -static const struct flash_sector TMS470R1A256_SECTORS[] = { +static const struct flash_sector tms470r1a256_sectors[] = { {0x00000000, 0x00002000, -1, -1}, {0x00002000, 0x00002000, -1, -1}, {0x00004000, 0x00002000, -1, -1}, @@ -57,9 +57,9 @@ static const struct flash_sector TMS470R1A256_SECTORS[] = { }; #define TMS470R1A256_NUM_SECTORS \ - ARRAY_SIZE(TMS470R1A256_SECTORS) + ARRAY_SIZE(tms470r1a256_sectors) -static const struct flash_sector TMS470R1A288_BANK0_SECTORS[] = { +static const struct flash_sector tms470r1a288_bank0_sectors[] = { {0x00000000, 0x00002000, -1, -1}, {0x00002000, 0x00002000, -1, -1}, {0x00004000, 0x00002000, -1, -1}, @@ -67,9 +67,9 @@ static const struct flash_sector TMS470R1A288_BANK0_SECTORS[] = { }; #define TMS470R1A288_BANK0_NUM_SECTORS \ - ARRAY_SIZE(TMS470R1A288_BANK0_SECTORS) + ARRAY_SIZE(tms470r1a288_bank0_sectors) -static const struct flash_sector TMS470R1A288_BANK1_SECTORS[] = { +static const struct flash_sector tms470r1a288_bank1_sectors[] = { {0x00040000, 0x00010000, -1, -1}, {0x00050000, 0x00010000, -1, -1}, {0x00060000, 0x00010000, -1, -1}, @@ -77,9 +77,9 @@ static const struct flash_sector TMS470R1A288_BANK1_SECTORS[] = { }; #define TMS470R1A288_BANK1_NUM_SECTORS \ - ARRAY_SIZE(TMS470R1A288_BANK1_SECTORS) + ARRAY_SIZE(tms470r1a288_bank1_sectors) -static const struct flash_sector TMS470R1A384_BANK0_SECTORS[] = { +static const struct flash_sector tms470r1a384_bank0_sectors[] = { {0x00000000, 0x00002000, -1, -1}, {0x00002000, 0x00002000, -1, -1}, {0x00004000, 0x00004000, -1, -1}, @@ -93,9 +93,9 @@ static const struct flash_sector TMS470R1A384_BANK0_SECTORS[] = { }; #define TMS470R1A384_BANK0_NUM_SECTORS \ - ARRAY_SIZE(TMS470R1A384_BANK0_SECTORS) + ARRAY_SIZE(tms470r1a384_bank0_sectors) -static const struct flash_sector TMS470R1A384_BANK1_SECTORS[] = { +static const struct flash_sector tms470r1a384_bank1_sectors[] = { {0x00020000, 0x00008000, -1, -1}, {0x00028000, 0x00008000, -1, -1}, {0x00030000, 0x00008000, -1, -1}, @@ -103,9 +103,9 @@ static const struct flash_sector TMS470R1A384_BANK1_SECTORS[] = { }; #define TMS470R1A384_BANK1_NUM_SECTORS \ - ARRAY_SIZE(TMS470R1A384_BANK1_SECTORS) + ARRAY_SIZE(tms470r1a384_bank1_sectors) -static const struct flash_sector TMS470R1A384_BANK2_SECTORS[] = { +static const struct flash_sector tms470r1a384_bank2_sectors[] = { {0x00040000, 0x00008000, -1, -1}, {0x00048000, 0x00008000, -1, -1}, {0x00050000, 0x00008000, -1, -1}, @@ -113,7 +113,7 @@ static const struct flash_sector TMS470R1A384_BANK2_SECTORS[] = { }; #define TMS470R1A384_BANK2_NUM_SECTORS \ - ARRAY_SIZE(TMS470R1A384_BANK2_SECTORS) + ARRAY_SIZE(tms470r1a384_bank2_sectors) /* ---------------------------------------------------------------------- */ @@ -173,10 +173,10 @@ static int tms470_read_part_info(struct flash_bank *bank) bank->base = 0x00000000; bank->size = 256 * 1024; bank->num_sectors = TMS470R1A256_NUM_SECTORS; - bank->sectors = malloc(sizeof(TMS470R1A256_SECTORS)); + bank->sectors = malloc(sizeof(tms470r1a256_sectors)); if (!bank->sectors) return ERROR_FLASH_OPERATION_FAILED; - (void)memcpy(bank->sectors, TMS470R1A256_SECTORS, sizeof(TMS470R1A256_SECTORS)); + (void)memcpy(bank->sectors, tms470r1a256_sectors, sizeof(tms470r1a256_sectors)); break; case 0x2b: @@ -187,21 +187,21 @@ static int tms470_read_part_info(struct flash_bank *bank) bank->base = 0x00000000; bank->size = 32 * 1024; bank->num_sectors = TMS470R1A288_BANK0_NUM_SECTORS; - bank->sectors = malloc(sizeof(TMS470R1A288_BANK0_SECTORS)); + bank->sectors = malloc(sizeof(tms470r1a288_bank0_sectors)); if (!bank->sectors) return ERROR_FLASH_OPERATION_FAILED; - (void)memcpy(bank->sectors, TMS470R1A288_BANK0_SECTORS, - sizeof(TMS470R1A288_BANK0_SECTORS)); + (void)memcpy(bank->sectors, tms470r1a288_bank0_sectors, + sizeof(tms470r1a288_bank0_sectors)); } else if ((bank->base >= 0x00040000) && (bank->base < 0x00080000)) { tms470_info->ordinal = 1; bank->base = 0x00040000; bank->size = 256 * 1024; bank->num_sectors = TMS470R1A288_BANK1_NUM_SECTORS; - bank->sectors = malloc(sizeof(TMS470R1A288_BANK1_SECTORS)); + bank->sectors = malloc(sizeof(tms470r1a288_bank1_sectors)); if (!bank->sectors) return ERROR_FLASH_OPERATION_FAILED; - (void)memcpy(bank->sectors, TMS470R1A288_BANK1_SECTORS, - sizeof(TMS470R1A288_BANK1_SECTORS)); + (void)memcpy(bank->sectors, tms470r1a288_bank1_sectors, + sizeof(tms470r1a288_bank1_sectors)); } else { LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".", part_name, bank->base); @@ -217,31 +217,31 @@ static int tms470_read_part_info(struct flash_bank *bank) bank->base = 0x00000000; bank->size = 128 * 1024; bank->num_sectors = TMS470R1A384_BANK0_NUM_SECTORS; - bank->sectors = malloc(sizeof(TMS470R1A384_BANK0_SECTORS)); + bank->sectors = malloc(sizeof(tms470r1a384_bank0_sectors)); if (!bank->sectors) return ERROR_FLASH_OPERATION_FAILED; - (void)memcpy(bank->sectors, TMS470R1A384_BANK0_SECTORS, - sizeof(TMS470R1A384_BANK0_SECTORS)); + (void)memcpy(bank->sectors, tms470r1a384_bank0_sectors, + sizeof(tms470r1a384_bank0_sectors)); } else if ((bank->base >= 0x00020000) && (bank->base < 0x00040000)) { tms470_info->ordinal = 1; bank->base = 0x00020000; bank->size = 128 * 1024; bank->num_sectors = TMS470R1A384_BANK1_NUM_SECTORS; - bank->sectors = malloc(sizeof(TMS470R1A384_BANK1_SECTORS)); + bank->sectors = malloc(sizeof(tms470r1a384_bank1_sectors)); if (!bank->sectors) return ERROR_FLASH_OPERATION_FAILED; - (void)memcpy(bank->sectors, TMS470R1A384_BANK1_SECTORS, - sizeof(TMS470R1A384_BANK1_SECTORS)); + (void)memcpy(bank->sectors, tms470r1a384_bank1_sectors, + sizeof(tms470r1a384_bank1_sectors)); } else if ((bank->base >= 0x00040000) && (bank->base < 0x00060000)) { tms470_info->ordinal = 2; bank->base = 0x00040000; bank->size = 128 * 1024; bank->num_sectors = TMS470R1A384_BANK2_NUM_SECTORS; - bank->sectors = malloc(sizeof(TMS470R1A384_BANK2_SECTORS)); + bank->sectors = malloc(sizeof(tms470r1a384_bank2_sectors)); if (!bank->sectors) return ERROR_FLASH_OPERATION_FAILED; - (void)memcpy(bank->sectors, TMS470R1A384_BANK2_SECTORS, - sizeof(TMS470R1A384_BANK2_SECTORS)); + (void)memcpy(bank->sectors, tms470r1a384_bank2_sectors, + sizeof(tms470r1a384_bank2_sectors)); } else { LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".", part_name, bank->base); @@ -325,37 +325,37 @@ COMMAND_HANDLER(tms470_handle_flash_keyset_command) return ERROR_OK; } -static const uint32_t FLASH_KEYS_ALL_ONES[] = { 0xFFFFFFFF, 0xFFFFFFFF, +static const uint32_t flash_keys_all_ones[] = { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,}; -static const uint32_t FLASH_KEYS_ALL_ZEROS[] = { 0x00000000, 0x00000000, +static const uint32_t flash_keys_all_zeros[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,}; -static const uint32_t FLASH_KEYS_MIX1[] = { 0xf0fff0ff, 0xf0fff0ff, +static const uint32_t flash_keys_mix1[] = { 0xf0fff0ff, 0xf0fff0ff, 0xf0fff0ff, 0xf0fff0ff}; -static const uint32_t FLASH_KEYS_MIX2[] = { 0x0000ffff, 0x0000ffff, +static const uint32_t flash_keys_mix2[] = { 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff}; /* ---------------------------------------------------------------------- */ -static int oscMHz = 12; +static int osc_mhz = 12; COMMAND_HANDLER(tms470_handle_osc_megahertz_command) { if (CMD_ARGC > 1) return ERROR_COMMAND_SYNTAX_ERROR; else if (CMD_ARGC == 1) - sscanf(CMD_ARGV[0], "%d", &oscMHz); + sscanf(CMD_ARGV[0], "%d", &osc_mhz); - if (oscMHz <= 0) { + if (osc_mhz <= 0) { LOG_ERROR("osc_megahertz must be positive and non-zero!"); command_print(CMD, "osc_megahertz must be positive and non-zero!"); - oscMHz = 12; + osc_mhz = 12; return ERROR_COMMAND_SYNTAX_ERROR; } - command_print(CMD, "osc_megahertz=%d", oscMHz); + command_print(CMD, "osc_megahertz=%d", osc_mhz); return ERROR_OK; } @@ -474,16 +474,16 @@ static int tms470_unlock_flash(struct flash_bank *bank) if (keys_set) { key_set_count = 5; p_key_sets[0] = flash_keys; - p_key_sets[1] = FLASH_KEYS_ALL_ONES; - p_key_sets[2] = FLASH_KEYS_ALL_ZEROS; - p_key_sets[3] = FLASH_KEYS_MIX1; - p_key_sets[4] = FLASH_KEYS_MIX2; + p_key_sets[1] = flash_keys_all_ones; + p_key_sets[2] = flash_keys_all_zeros; + p_key_sets[3] = flash_keys_mix1; + p_key_sets[4] = flash_keys_mix2; } else { key_set_count = 4; - p_key_sets[0] = FLASH_KEYS_ALL_ONES; - p_key_sets[1] = FLASH_KEYS_ALL_ZEROS; - p_key_sets[2] = FLASH_KEYS_MIX1; - p_key_sets[3] = FLASH_KEYS_MIX2; + p_key_sets[0] = flash_keys_all_ones; + p_key_sets[1] = flash_keys_all_zeros; + p_key_sets[2] = flash_keys_mix1; + p_key_sets[3] = flash_keys_mix2; } for (i = 0; i < key_set_count; i++) { @@ -573,7 +573,7 @@ static int tms470_flash_initialize_internal_state_machine(struct flash_bank *ban * the plldis global. */ target_read_u32(target, 0xFFFFFFDC, &glbctrl); - sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * oscMHz / (1 + (glbctrl & 7)); + sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * osc_mhz / (1 + (glbctrl & 7)); delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5; target_write_u32(target, 0xFFE8A018, (delay << 4) | (delay << 8)); LOG_DEBUG("set fmpsetup = 0x%04" PRIx32 "", (delay << 4) | (delay << 8)); diff --git a/src/flash/nor/xcf.c b/src/flash/nor/xcf.c index 33f79f510..1220a1ef2 100644 --- a/src/flash/nor/xcf.c +++ b/src/flash/nor/xcf.c @@ -68,25 +68,25 @@ struct xcf_status { * GLOBAL VARIABLES ****************************************************************************** */ -static const uint8_t CMD_BYPASS[2] = {0xFF, 0xFF}; - -static const uint8_t CMD_ISC_ADDRESS_SHIFT[2] = {0xEB, 0x00}; -static const uint8_t CMD_ISC_DATA_SHIFT[2] = {0xED, 0x00}; -static const uint8_t CMD_ISC_DISABLE[2] = {0xF0, 0x00}; -static const uint8_t CMD_ISC_ENABLE[2] = {0xE8, 0x00}; -static const uint8_t CMD_ISC_ERASE[2] = {0xEC, 0x00}; -static const uint8_t CMD_ISC_PROGRAM[2] = {0xEA, 0x00}; - -static const uint8_t CMD_XSC_BLANK_CHECK[2] = {0x0D, 0x00}; -static const uint8_t CMD_XSC_CONFIG[2] = {0xEE, 0x00}; -static const uint8_t CMD_XSC_DATA_BTC[2] = {0xF2, 0x00}; -static const uint8_t CMD_XSC_DATA_CCB[2] = {0x0C, 0x00}; -static const uint8_t CMD_XSC_DATA_DONE[2] = {0x09, 0x00}; -static const uint8_t CMD_XSC_DATA_SUCR[2] = {0x0E, 0x00}; -static const uint8_t CMD_XSC_DATA_WRPT[2] = {0xF7, 0x00}; -static const uint8_t CMD_XSC_OP_STATUS[2] = {0xE3, 0x00}; -static const uint8_t CMD_XSC_READ[2] = {0xEF, 0x00}; -static const uint8_t CMD_XSC_UNLOCK[2] = {0x55, 0xAA}; +static const uint8_t cmd_bypass[2] = {0xFF, 0xFF}; + +static const uint8_t cmd_isc_address_shift[2] = {0xEB, 0x00}; +static const uint8_t cmd_isc_data_shift[2] = {0xED, 0x00}; +static const uint8_t cmd_isc_disable[2] = {0xF0, 0x00}; +static const uint8_t cmd_isc_enable[2] = {0xE8, 0x00}; +static const uint8_t cmd_isc_erase[2] = {0xEC, 0x00}; +static const uint8_t cmd_isc_program[2] = {0xEA, 0x00}; + +static const uint8_t cmd_xsc_blank_check[2] = {0x0D, 0x00}; +static const uint8_t cmd_xsc_config[2] = {0xEE, 0x00}; +static const uint8_t cmd_xsc_data_btc[2] = {0xF2, 0x00}; +static const uint8_t cmd_xsc_data_ccb[2] = {0x0C, 0x00}; +static const uint8_t cmd_xsc_data_done[2] = {0x09, 0x00}; +static const uint8_t cmd_xsc_data_sucr[2] = {0x0E, 0x00}; +static const uint8_t cmd_xsc_data_wrpt[2] = {0xF7, 0x00}; +static const uint8_t cmd_xsc_op_status[2] = {0xE3, 0x00}; +static const uint8_t cmd_xsc_read[2] = {0xEF, 0x00}; +static const uint8_t cmd_xsc_unlock[2] = {0x55, 0xAA}; /* ****************************************************************************** @@ -135,7 +135,7 @@ static struct xcf_status read_status(struct flash_bank *bank) scan.check_mask = NULL; scan.check_value = NULL; scan.num_bits = 16; - scan.out_value = CMD_BYPASS; + scan.out_value = cmd_bypass; scan.in_value = irdata; jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE); @@ -162,7 +162,7 @@ static int isc_enter(struct flash_bank *bank) scan.check_mask = NULL; scan.check_value = NULL; scan.num_bits = 16; - scan.out_value = CMD_ISC_ENABLE; + scan.out_value = cmd_isc_enable; scan.in_value = NULL; jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE); @@ -191,7 +191,7 @@ static int isc_leave(struct flash_bank *bank) scan.check_mask = NULL; scan.check_value = NULL; scan.num_bits = 16; - scan.out_value = CMD_ISC_DISABLE; + scan.out_value = cmd_isc_disable; scan.in_value = NULL; jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE); @@ -252,7 +252,7 @@ static int isc_wait_erase_program(struct flash_bank *bank, int64_t timeout_ms) int64_t dt; do { - isc_read_register(bank, CMD_XSC_OP_STATUS, &isc_default, 8); + isc_read_register(bank, cmd_xsc_op_status, &isc_default, 8); if (((isc_default >> 2) & 1) == 1) return ERROR_OK; dt = timeval_ms() - t0; @@ -307,7 +307,7 @@ static int isc_program_register(struct flash_bank *bank, const uint8_t *cmd, jtag_add_dr_scan(bank->target->tap, 1, &scan, TAP_IRSHIFT); scan.num_bits = 16; - scan.out_value = CMD_ISC_PROGRAM; + scan.out_value = cmd_isc_program; scan.in_value = NULL; jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE); @@ -322,7 +322,7 @@ static int isc_clear_protect(struct flash_bank *bank, unsigned int first, { uint8_t select_block[3] = {0x0, 0x0, 0x0}; select_block[0] = fill_select_block(first, last); - return isc_set_register(bank, CMD_XSC_UNLOCK, select_block, 24, 0); + return isc_set_register(bank, cmd_xsc_unlock, select_block, 24, 0); } static int isc_set_protect(struct flash_bank *bank, unsigned int first, @@ -332,7 +332,7 @@ static int isc_set_protect(struct flash_bank *bank, unsigned int first, for (unsigned int i = first; i <= last; i++) wrpt[0] &= ~(1 << i); - return isc_program_register(bank, CMD_XSC_DATA_WRPT, wrpt, 16, 0); + return isc_program_register(bank, cmd_xsc_data_wrpt, wrpt, 16, 0); } static int isc_erase_sectors(struct flash_bank *bank, unsigned int first, @@ -341,19 +341,19 @@ static int isc_erase_sectors(struct flash_bank *bank, unsigned int first, uint8_t select_block[3] = {0, 0, 0}; select_block[0] = fill_select_block(first, last); int64_t timeout = SECTOR_ERASE_TIMEOUT_MS * (last - first + 1); - return isc_set_register(bank, CMD_ISC_ERASE, select_block, 24, timeout); + return isc_set_register(bank, cmd_isc_erase, select_block, 24, timeout); } static int isc_adr_shift(struct flash_bank *bank, int adr) { uint8_t adr_buf[3]; h_u24_to_le(adr_buf, adr); - return isc_set_register(bank, CMD_ISC_ADDRESS_SHIFT, adr_buf, 24, 0); + return isc_set_register(bank, cmd_isc_address_shift, adr_buf, 24, 0); } static int isc_program_data_page(struct flash_bank *bank, const uint8_t *page_buf) { - return isc_program_register(bank, CMD_ISC_DATA_SHIFT, page_buf, 8 * XCF_PAGE_SIZE, 100); + return isc_program_register(bank, cmd_isc_data_shift, page_buf, 8 * XCF_PAGE_SIZE, 100); } static void isc_data_read_out(struct flash_bank *bank, uint8_t *buffer, uint32_t count) @@ -366,7 +366,7 @@ static void isc_data_read_out(struct flash_bank *bank, uint8_t *buffer, uint32_t scan.check_mask = NULL; scan.check_value = NULL; scan.num_bits = 16; - scan.out_value = CMD_XSC_READ; + scan.out_value = cmd_xsc_read; scan.in_value = NULL; jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE); @@ -382,7 +382,7 @@ static int isc_set_data_done(struct flash_bank *bank, int sector) { uint8_t done = 0xFF; done &= ~(1 << sector); - return isc_program_register(bank, CMD_XSC_DATA_DONE, &done, 8, 100); + return isc_program_register(bank, cmd_xsc_data_done, &done, 8, 100); } static void flip_u8(uint8_t *out, const uint8_t *in, int len) @@ -508,7 +508,7 @@ EXIT: static uint16_t isc_read_ccb(struct flash_bank *bank) { uint8_t ccb[2]; - isc_read_register(bank, CMD_XSC_DATA_CCB, ccb, 16); + isc_read_register(bank, cmd_xsc_data_ccb, ccb, 16); return le_to_h_u16(ccb); } @@ -526,13 +526,13 @@ static int isc_program_ccb(struct flash_bank *bank, uint16_t ccb) { uint8_t buf[2]; h_u16_to_le(buf, ccb); - return isc_program_register(bank, CMD_XSC_DATA_CCB, buf, 16, 100); + return isc_program_register(bank, cmd_xsc_data_ccb, buf, 16, 100); } static int isc_program_singe_revision_sucr(struct flash_bank *bank) { uint8_t sucr[2] = {0xFC, 0xFF}; - return isc_program_register(bank, CMD_XSC_DATA_SUCR, sucr, 16, 100); + return isc_program_register(bank, cmd_xsc_data_sucr, sucr, 16, 100); } static int isc_program_single_revision_btc(struct flash_bank *bank) @@ -543,7 +543,7 @@ static int isc_program_single_revision_btc(struct flash_bank *bank) btc |= ((bank->num_sectors - 1) << 2); btc &= ~(1 << 4); h_u32_to_le(buf, btc); - return isc_program_register(bank, CMD_XSC_DATA_BTC, buf, 32, 100); + return isc_program_register(bank, cmd_xsc_data_btc, buf, 32, 100); } static int fpga_configure(struct flash_bank *bank) @@ -553,7 +553,7 @@ static int fpga_configure(struct flash_bank *bank) scan.check_mask = NULL; scan.check_value = NULL; scan.num_bits = 16; - scan.out_value = CMD_XSC_CONFIG; + scan.out_value = cmd_xsc_config; scan.in_value = NULL; jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE); jtag_execute_queue(); @@ -663,7 +663,7 @@ static int xcf_protect_check(struct flash_bank *bank) uint8_t wrpt[2]; isc_enter(bank); - isc_read_register(bank, CMD_XSC_DATA_WRPT, wrpt, 16); + isc_read_register(bank, cmd_xsc_data_wrpt, wrpt, 16); isc_leave(bank); for (unsigned int i = 0; i < bank->num_sectors; i++) @@ -684,7 +684,7 @@ static int xcf_erase_check(struct flash_bank *bank) scan.check_mask = NULL; scan.check_value = NULL; scan.num_bits = 16; - scan.out_value = CMD_XSC_BLANK_CHECK; + scan.out_value = cmd_xsc_blank_check; scan.in_value = NULL; jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE); jtag_execute_queue(); commit e4c0f45a5f01b202b916deb950485c67c4a6fb10 Author: Antonio Borneo <bor...@gm...> Date: Sun Jun 6 18:17:01 2021 +0200 drivers/buspirate: use macros in place of const variables Uppercase symbols are normally used for macro or enum's values. Convert the uppercase const variables to macros. Change-Id: I749544c2e5deba65583824a7c2a6023e697714df Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6346 Tested-by: jenkins Reviewed-by: Marc Schink <de...@za...> diff --git a/src/jtag/drivers/buspirate.c b/src/jtag/drivers/buspirate.c index 616832ea7..59819513b 100644 --- a/src/jtag/drivers/buspirate.c +++ b/src/jtag/drivers/buspirate.c @@ -58,6 +58,8 @@ static void buspirate_stableclocks(int num_cycles); #define CMD_RAW_SPEED 0x60 #define CMD_RAW_MODE 0x80 +#define CMD_TAP_SHIFT_HEADER_LEN 3 + /* raw-wire mode configuration */ #define CMD_RAW_CONFIG_HIZ 0x00 #define CMD_RAW_CONFIG_3V3 0x08 @@ -71,6 +73,9 @@ static void buspirate_stableclocks(int num_cycles); #define B1000000 0010010 #endif +#define SHORT_TIMEOUT 1 /* Must be at least 1. */ +#define NORMAL_TIMEOUT 10 + enum { MODE_HIZ = 0, MODE_JTAG = 1, /* push-pull outputs */ @@ -107,9 +112,6 @@ static bool swd_mode; static int queued_retval; static char swd_features; -static const cc_t SHORT_TIMEOUT = 1; /* Must be at least 1. */ -static const cc_t NORMAL_TIMEOUT = 10; - static int buspirate_fd = -1; static int buspirate_pinmode = MODE_JTAG_OD; static int buspirate_baudrate = SERIAL_NORMAL; @@ -708,8 +710,6 @@ static void buspirate_tap_init(void) static int buspirate_tap_execute(void) { - static const int CMD_TAP_SHIFT_HEADER_LEN = 3; - uint8_t tmp[4096]; uint8_t *in_buf; int i; commit fceb29d03ff9b2829be2cadd64d09d264c568349 Author: Antonio Borneo <bor...@gm...> Date: Sun Jun 6 18:14:03 2021 +0200 jtag/aice: use macros in place of const variables Uppercase symbols are normally used for macro or enum's values. Convert the uppercase const variables to macros. Change-Id: I4ba47ce2d3183b50730c5a9a265f274c7b802519 Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6345 Tested-by: jenkins Reviewed-by: Marc Schink <de...@za...> Reviewed-by: Xiang W <wx...@12...> diff --git a/src/jtag/aice/aice_usb.c b/src/jtag/aice/aice_usb.c index 3a0e48522..751fd135c 100644 --- a/src/jtag/aice/aice_usb.c +++ b/src/jtag/aice/aice_usb.c @@ -53,29 +53,29 @@ static enum aice_target_endian data_endian; #define AICE_FORMAT_DTHMB (4) /* Constants for AICE command */ -static const uint8_t AICE_CMD_SCAN_CHAIN = 0x00; -static const uint8_t AICE_CMD_T_READ_MISC = 0x20; -static const uint8_t AICE_CMD_T_READ_EDMSR = 0x21; -static const uint8_t AICE_CMD_T_READ_DTR = 0x22; -static const uint8_t AICE_CMD_T_READ_MEM_B = 0x24; -static const uint8_t AICE_CMD_T_READ_MEM_H = 0x25; -static const uint8_t AICE_CMD_T_READ_MEM = 0x26; -static const uint8_t AICE_CMD_T_FASTREAD_MEM = 0x27; -static const uint8_t AICE_CMD_T_WRITE_MISC = 0x28; -static const uint8_t AICE_CMD_T_WRITE_EDMSR = 0x29; -static const uint8_t AICE_CMD_T_WRITE_DTR = 0x2A; -static const uint8_t AICE_CMD_T_WRITE_DIM = 0x2B; -static const uint8_t AICE_CMD_T_WRITE_MEM_B = 0x2C; -static const uint8_t AICE_CMD_T_WRITE_MEM_H = 0x2D; -static const uint8_t AICE_CMD_T_WRITE_MEM = 0x2E; -static const uint8_t AICE_CMD_T_FASTWRITE_MEM = 0x2F; -static const uint8_t AICE_CMD_T_EXECUTE = 0x3E; -static const uint8_t AICE_CMD_READ_CTRL = 0x50; -static const uint8_t AICE_CMD_WRITE_CTRL = 0x51; -static const uint8_t AICE_CMD_BATCH_BUFFER_READ = 0x60; -static const uint8_t AICE_CMD_READ_DTR_TO_BUFFER = 0x61; -static const uint8_t AICE_CMD_BATCH_BUFFER_WRITE = 0x68; -static const uint8_t AICE_CMD_WRITE_DTR_FROM_BUFFER = 0x69; +#define AICE_CMD_SCAN_CHAIN 0x00 +#define AICE_CMD_T_READ_MISC 0x20 +#define AICE_CMD_T_READ_EDMSR 0x21 +#define AICE_CMD_T_READ_DTR 0x22 +#define AICE_CMD_T_READ_MEM_B 0x24 +#define AICE_CMD_T_READ_MEM_H 0x25 +#define AICE_CMD_T_READ_MEM 0x26 +#define AICE_CMD_T_FASTREAD_MEM 0x27 +#define AICE_CMD_T_WRITE_MISC 0x28 +#define AICE_CMD_T_WRITE_EDMSR 0x29 +#define AICE_CMD_T_WRITE_DTR 0x2A +#define AICE_CMD_T_WRITE_DIM 0x2B +#define AICE_CMD_T_WRITE_MEM_B 0x2C +#define AICE_CMD_T_WRITE_MEM_H 0x2D +#define AICE_CMD_T_WRITE_MEM 0x2E +#define AICE_CMD_T_FASTWRITE_MEM 0x2F +#define AICE_CMD_T_EXECUTE 0x3E +#define AICE_CMD_READ_CTRL 0x50 +#define AICE_CMD_WRITE_CTRL 0x51 +#define AICE_CMD_BATCH_BUFFER_READ 0x60 +#define AICE_CMD_READ_DTR_TO_BUFFER 0x61 +#define AICE_CMD_BATCH_BUFFER_WRITE 0x68 +#define AICE_CMD_WRITE_DTR_FROM_BUFFER 0x69 /***************************************************************************/ /* AICE commands' pack/unpack functions */ ----------------------------------------------------------------------- Summary of changes: src/flash/nand/mxc.c | 48 +++++++++++----------- src/flash/nor/at91sam7.c | 16 ++++---- src/flash/nor/stm32l4x.c | 6 +-- src/flash/nor/tms470.c | 94 ++++++++++++++++++++++---------------------- src/flash/nor/xcf.c | 76 +++++++++++++++++------------------ src/jtag/aice/aice_usb.c | 46 +++++++++++----------- src/jtag/drivers/buspirate.c | 10 ++--- 7 files changed, 148 insertions(+), 148 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-20 13:54:12
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via b08e27323a0e0f6daa9bacd026876c103bf1133f (commit) via 43750e8d5329003c1757672a2887910824b08ad9 (commit) via cbaccc5c3eff817faf59693f653b3a2da063c818 (commit) via 12d6f6d80431a7660cbf88838efae66fbf583413 (commit) from c0ea4295df22c8f9b7d17472171f77639e19b61d (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit b08e27323a0e0f6daa9bacd026876c103bf1133f Author: Antonio Borneo <bor...@gm...> Date: Sun Jun 6 17:41:09 2021 +0200 svf: rename CamelCase label Change-Id: I41871bbbead9810f9a66b2e440a7b26094d6cd0c Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6344 Tested-by: jenkins Reviewed-by: Marc Schink <de...@za...> Reviewed-by: Xiang W <wx...@12...> diff --git a/src/svf/svf.c b/src/svf/svf.c index f35c61314..482dcdc0d 100644 --- a/src/svf/svf.c +++ b/src/svf/svf.c @@ -989,35 +989,35 @@ static int svf_run_command(struct command_context *cmd_ctx, char *cmd_str) break; } xxr_para_tmp = &svf_para.hdr_para; - goto XXR_common; + goto xxr_common; case HIR: if (svf_tap_is_specified) { padding_command_skipped = 1; break; } xxr_para_tmp = &svf_para.hir_para; - goto XXR_common; + goto xxr_common; case TDR: if (svf_tap_is_specified) { padding_command_skipped = 1; break; } xxr_para_tmp = &svf_para.tdr_para; - goto XXR_common; + goto xxr_common; case TIR: if (svf_tap_is_specified) { padding_command_skipped = 1; break; } xxr_para_tmp = &svf_para.tir_para; - goto XXR_common; + goto xxr_common; case SDR: xxr_para_tmp = &svf_para.sdr_para; - goto XXR_common; + goto xxr_common; case SIR: xxr_para_tmp = &svf_para.sir_para; - goto XXR_common; -XXR_common: + goto xxr_common; +xxr_common: /* XXR length [TDI (tdi)] [TDO (tdo)][MASK (mask)] [SMASK (smask)] */ if ((num_of_argu > 10) || (num_of_argu % 2)) { LOG_ERROR("invalid parameter of %s", argus[0]); commit 43750e8d5329003c1757672a2887910824b08ad9 Author: Antonio Borneo <bor...@gm...> Date: Sun Jun 6 17:48:48 2021 +0200 target/nds32: rename CamelCase symbols Change-Id: I4619eb47cd051f52e60a3fdbc49aaf71e13a81e2 Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6342 Tested-by: jenkins Reviewed-by: Marc Schink <de...@za...> Reviewed-by: Xiang W <wx...@12...> diff --git a/src/target/nds32.c b/src/target/nds32.c index d524fc288..39d2c0067 100644 --- a/src/target/nds32.c +++ b/src/target/nds32.c @@ -1134,7 +1134,7 @@ static void nds32_init_config(struct nds32 *nds32) misc_config->div_instruction = (value_cr4 >> 5) & 0x1; misc_config->mac_instruction = (value_cr4 >> 6) & 0x1; misc_config->audio_isa = (value_cr4 >> 7) & 0x3; - misc_config->L2_cache = (value_cr4 >> 9) & 0x1; + misc_config->l2_cache = (value_cr4 >> 9) & 0x1; misc_config->reduce_register = (value_cr4 >> 10) & 0x1; misc_config->addr_24 = (value_cr4 >> 11) & 0x1; misc_config->interruption_level = (value_cr4 >> 12) & 0x1; diff --git a/src/target/nds32.h b/src/target/nds32.h index 3670fd289..e9b9ee194 100644 --- a/src/target/nds32.h +++ b/src/target/nds32.h @@ -217,7 +217,7 @@ struct nds32_misc_config { bool div_instruction; bool mac_instruction; int audio_isa; - bool L2_cache; + bool l2_cache; bool reduce_register; bool addr_24; bool interruption_level; diff --git a/src/target/nds32_tlb.c b/src/target/nds32_tlb.c index 93a924109..81734e0c1 100644 --- a/src/target/nds32_tlb.c +++ b/src/target/nds32_tlb.c @@ -44,34 +44,34 @@ int nds32_walk_page_table(struct nds32 *nds32, const target_addr_t virtual_addre struct target *target = nds32->target; uint32_t value_mr1; uint32_t load_address; - uint32_t L1_page_table_entry; - uint32_t L2_page_table_entry; + uint32_t l1_page_table_entry; + uint32_t l2_page_table_entry; uint32_t page_size_index = nds32->mmu_config.default_min_page_size; struct page_table_walker_info_s *page_table_info_p = &(page_table_info[page_size_index]); /* Read L1 Physical Page Table */ nds32_get_mapped_reg(nds32, MR1, &value_mr1); - load_address = (value_mr1 & page_table_info_p->L1_base_mask) | - ((virtual_address & page_table_info_p->L1_offset_mask) >> - page_table_info_p->L1_offset_shift); + load_address = (value_mr1 & page_table_info_p->l1_base_mask) | + ((virtual_address & page_table_info_p->l1_offset_mask) >> + page_table_info_p->l1_offset_shift); /* load_address is physical address */ - nds32_read_buffer(target, load_address, 4, (uint8_t *)&L1_page_table_entry); + nds32_read_buffer(target, load_address, 4, (uint8_t *)&l1_page_table_entry); /* Read L2 Physical Page Table */ - if (L1_page_table_entry & 0x1) /* L1_PTE not present */ + if (l1_page_table_entry & 0x1) /* L1_PTE not present */ return ERROR_FAIL; - load_address = (L1_page_table_entry & page_table_info_p->L2_base_mask) | - ((virtual_address & page_table_info_p->L2_offset_mask) >> - page_table_info_p->L2_offset_shift); + load_address = (l1_page_table_entry & page_table_info_p->l2_base_mask) | + ((virtual_address & page_table_info_p->l2_offset_mask) >> + page_table_info_p->l2_offset_shift); /* load_address is physical address */ - nds32_read_buffer(target, load_address, 4, (uint8_t *)&L2_page_table_entry); + nds32_read_buffer(target, load_address, 4, (uint8_t *)&l2_page_table_entry); - if ((L2_page_table_entry & 0x1) != 0x1) /* L2_PTE not valid */ + if ((l2_page_table_entry & 0x1) != 0x1) /* L2_PTE not valid */ return ERROR_FAIL; - *physical_address = (L2_page_table_entry & page_table_info_p->ppn_mask) | + *physical_address = (l2_page_table_entry & page_table_info_p->ppn_mask) | (virtual_address & page_table_info_p->va_offset_mask); return ERROR_OK; diff --git a/src/target/nds32_tlb.h b/src/target/nds32_tlb.h index 62512c111..c22ed7335 100644 --- a/src/target/nds32_tlb.h +++ b/src/target/nds32_tlb.h @@ -29,13 +29,13 @@ enum { struct page_table_walker_info_s { - uint32_t L1_offset_mask; - uint32_t L1_offset_shift; - uint32_t L2_offset_mask; - uint32_t L2_offset_shift; + uint32_t l1_offset_mask; + uint32_t l1_offset_shift; + uint32_t l2_offset_mask; + uint32_t l2_offset_shift; uint32_t va_offset_mask; - uint32_t L1_base_mask; - uint32_t L2_base_mask; + uint32_t l1_base_mask; + uint32_t l2_base_mask; uint32_t ppn_mask; }; commit cbaccc5c3eff817faf59693f653b3a2da063c818 Author: Antonio Borneo <bor...@gm...> Date: Tue Apr 27 18:50:34 2021 +0200 target/mips: rename CamelCase symbols No major cross dependencies, mostly changes internal to each file/function. Change-Id: Iec58f7fe1d65f621ae0c841b5e25ef222885792b Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6341 Tested-by: jenkins Reviewed-by: Marc Schink <de...@za...> Reviewed-by: Xiang W <wx...@12...> diff --git a/src/target/mips32.h b/src/target/mips32.h index f107b57d5..5ca3b7e05 100644 --- a/src/target/mips32.h +++ b/src/target/mips32.h @@ -248,7 +248,7 @@ struct mips32_algorithm { /*MICRO MIPS INSTRUCTIONS, see doc MD00582 */ #define POOL32A 0X00u -#define POOL32AXf 0x3Cu +#define POOL32AXF 0x3Cu #define POOL32B 0x08u #define POOL32I 0x10u #define MMIPS32_OP_ADDI 0x04u @@ -300,24 +300,24 @@ struct mips32_algorithm { #define MMIPS32_CACHE(op, off, base) MIPS32_R_INST(POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off) #define MMIPS32_J(tar) MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1)))) -#define MMIPS32_JR(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_JALR, POOL32AXf) +#define MMIPS32_JR(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_JALR, POOL32AXF) #define MMIPS32_LB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off) #define MMIPS32_LBU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off) #define MMIPS32_LHU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off) #define MMIPS32_LUI(reg, val) MIPS32_I_INST(POOL32I, MMIPS32_OP_LUI, reg, val) #define MMIPS32_LW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off) -#define MMIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MFC0, POOL32AXf) -#define MMIPS32_MFLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, POOL32AXf) -#define MMIPS32_MFHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, POOL32AXf) -#define MMIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MTC0, POOL32AXf) -#define MMIPS32_MTLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, POOL32AXf) -#define MMIPS32_MTHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, POOL32AXf) +#define MMIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MFC0, POOL32AXF) +#define MMIPS32_MFLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, POOL32AXF) +#define MMIPS32_MFHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, POOL32AXF) +#define MMIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MTC0, POOL32AXF) +#define MMIPS32_MTLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, POOL32AXF) +#define MMIPS32_MTHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, POOL32AXF) #define MMIPS32_MOVN(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN) #define MMIPS32_NOP 0 #define MMIPS32_ORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val) -#define MMIPS32_RDHWR(tar, dst) MIPS32_R_INST(POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, POOL32AXf) +#define MMIPS32_RDHWR(tar, dst) MIPS32_R_INST(POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, POOL32AXF) #define MMIPS32_SB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off) #define MMIPS32_SH(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off) #define MMIPS32_SW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off) @@ -327,7 +327,7 @@ struct mips32_algorithm { #define MMIPS32_SYNCI(off, base) MIPS32_I_INST(POOL32I, MMIPS32_OP_SYNCI, base, off) #define MMIPS32_SLL(dst, src, sa) MIPS32_R_INST(POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL) #define MMIPS32_SLTI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val) -#define MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1ADu, POOL32AXf) */ +#define MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1ADu, POOL32AXF) */ #define MMIPS32_XOR(reg, val1, val2) MIPS32_R_INST(POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR) #define MMIPS32_XORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val) @@ -336,8 +336,8 @@ struct mips32_algorithm { /* ejtag specific instructions */ -#define MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x38D, POOL32AXf) */ -#define MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1BD, POOL32AXf) */ +#define MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x38D, POOL32AXF) */ +#define MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1BD, POOL32AXF) */ #define MMIPS16_SDBBP 0x46C0u /* POOL16C instr */ /* instruction code with isa selection */ diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c index d4c019fbe..09af855e5 100644 --- a/src/target/mips_ejtag.c +++ b/src/target/mips_ejtag.c @@ -296,8 +296,8 @@ static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info) ejtag_info->ejtag_dbm_offs = EJTAG_V20_DBM_OFFS; ejtag_info->ejtag_dbv_offs = EJTAG_V20_DBV_OFFS; - ejtag_info->ejtag_iba_step_size = EJTAG_V20_IBAn_STEP; - ejtag_info->ejtag_dba_step_size = EJTAG_V20_DBAn_STEP; + ejtag_info->ejtag_iba_step_size = EJTAG_V20_IBAN_STEP; + ejtag_info->ejtag_dba_step_size = EJTAG_V20_DBAN_STEP; } else { ejtag_info->ejtag_ibs_addr = EJTAG_V25_IBS; ejtag_info->ejtag_iba0_addr = EJTAG_V25_IBA0; @@ -312,8 +312,8 @@ static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info) ejtag_info->ejtag_dbc_offs = EJTAG_V25_DBC_OFFS; ejtag_info->ejtag_dbv_offs = EJTAG_V25_DBV_OFFS; - ejtag_info->ejtag_iba_step_size = EJTAG_V25_IBAn_STEP; - ejtag_info->ejtag_dba_step_size = EJTAG_V25_DBAn_STEP; + ejtag_info->ejtag_iba_step_size = EJTAG_V25_IBAN_STEP; + ejtag_info->ejtag_dba_step_size = EJTAG_V25_DBAN_STEP; } } diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h index ace3d281e..e50101b0f 100644 --- a/src/target/mips_ejtag.h +++ b/src/target/mips_ejtag.h @@ -147,33 +147,33 @@ #define EJTAG_V20_IBA0 0xFF300100 #define EJTAG_V20_IBC_OFFS 0x4 /* IBC Offset */ #define EJTAG_V20_IBM_OFFS 0x8 -#define EJTAG_V20_IBAn_STEP 0x10 /* Offset for next channel */ +#define EJTAG_V20_IBAN_STEP 0x10 /* Offset for next channel */ #define EJTAG_V20_DBS 0xFF300008 #define EJTAG_V20_DBA0 0xFF300200 #define EJTAG_V20_DBC_OFFS 0x4 #define EJTAG_V20_DBM_OFFS 0x8 #define EJTAG_V20_DBV_OFFS 0xc -#define EJTAG_V20_DBAn_STEP 0x10 +#define EJTAG_V20_DBAN_STEP 0x10 #define EJTAG_V25_IBS 0xFF301000 #define EJTAG_V25_IBA0 0xFF301100 #define EJTAG_V25_IBM_OFFS 0x8 #define EJTAG_V25_IBASID_OFFS 0x10 #define EJTAG_V25_IBC_OFFS 0x18 -#define EJTAG_V25_IBAn_STEP 0x100 +#define EJTAG_V25_IBAN_STEP 0x100 #define EJTAG_V25_DBS 0xFF302000 #define EJTAG_V25_DBA0 0xFF302100 #define EJTAG_V25_DBM_OFFS 0x8 #define EJTAG_V25_DBASID_OFFS 0x10 #define EJTAG_V25_DBC_OFFS 0x18 #define EJTAG_V25_DBV_OFFS 0x20 -#define EJTAG_V25_DBAn_STEP 0x100 +#define EJTAG_V25_DBAN_STEP 0x100 -#define EJTAG_DBCn_NOSB (1 << 13) -#define EJTAG_DBCn_NOLB (1 << 12) -#define EJTAG_DBCn_BLM_MASK 0xff -#define EJTAG_DBCn_BLM_SHIFT 4 -#define EJTAG_DBCn_BE (1 << 0) +#define EJTAG_DBCN_NOSB (1 << 13) +#define EJTAG_DBCN_NOLB (1 << 12) +#define EJTAG_DBCN_BLM_MASK 0xff +#define EJTAG_DBCN_BLM_SHIFT 4 +#define EJTAG_DBCN_BE (1 << 0) #define EJTAG_VERSION_20 0 #define EJTAG_VERSION_25 1 diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 52b4b3217..249412a42 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -880,8 +880,8 @@ static int mips_m4k_set_watchpoint(struct target *target, * and exclude both load and store accesses from watchpoint * condition evaluation */ - int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE | - (0xff << EJTAG_DBCn_BLM_SHIFT); + int enable = EJTAG_DBCN_NOSB | EJTAG_DBCN_NOLB | EJTAG_DBCN_BE | + (0xff << EJTAG_DBCN_BLM_SHIFT); if (watchpoint->set) { LOG_WARNING("watchpoint already set"); @@ -907,13 +907,13 @@ static int mips_m4k_set_watchpoint(struct target *target, switch (watchpoint->rw) { case WPT_READ: - enable &= ~EJTAG_DBCn_NOLB; + enable &= ~EJTAG_DBCN_NOLB; break; case WPT_WRITE: - enable &= ~EJTAG_DBCn_NOSB; + enable &= ~EJTAG_DBCN_NOSB; break; case WPT_ACCESS: - enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB); + enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB); break; default: LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); diff --git a/src/target/mips_mips64.c b/src/target/mips_mips64.c index 0fc089726..9ba46b753 100644 --- a/src/target/mips_mips64.c +++ b/src/target/mips_mips64.c @@ -410,8 +410,8 @@ static int mips_mips64_set_watchpoint(struct target *target, * and exclude both load and store accesses from watchpoint * condition evaluation */ - int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE - | (0xff << EJTAG_DBCn_BLM_SHIFT); + int enable = EJTAG_DBCN_NOSB | EJTAG_DBCN_NOLB | EJTAG_DBCN_BE + | (0xff << EJTAG_DBCN_BLM_SHIFT); if (watchpoint->set) { LOG_WARNING("watchpoint already set"); @@ -438,13 +438,13 @@ static int mips_mips64_set_watchpoint(struct target *target, switch (watchpoint->rw) { case WPT_READ: - enable &= ~EJTAG_DBCn_NOLB; + enable &= ~EJTAG_DBCN_NOLB; break; case WPT_WRITE: - enable &= ~EJTAG_DBCn_NOSB; + enable &= ~EJTAG_DBCN_NOSB; break; case WPT_ACCESS: - enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB); + enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB); break; default: LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); commit 12d6f6d80431a7660cbf88838efae66fbf583413 Author: Antonio Borneo <bor...@gm...> Date: Wed Apr 28 00:25:03 2021 +0200 target/arm: opcodes: rename CamelCase symbols and uppercase variables No major cross dependencies, mostly changes internal to each file/function. Change-Id: I1325560ef0350517d86d4927cb17ceaae81b75d2 Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6340 Tested-by: jenkins Reviewed-by: Oleksij Rempel <li...@re...> Reviewed-by: Xiang W <wx...@12...> diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index 9b8c09e45..661859379 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -123,36 +123,36 @@ static int evaluate_pld(uint32_t opcode, { /* PLD */ if ((opcode & 0x0d30f000) == 0x0510f000) { - uint8_t Rn; - uint8_t U; + uint8_t rn; + uint8_t u; unsigned offset; instruction->type = ARM_PLD; - Rn = (opcode & 0xf0000) >> 16; - U = (opcode & 0x00800000) >> 23; - if (Rn == 0xf) { + rn = (opcode & 0xf0000) >> 16; + u = (opcode & 0x00800000) >> 23; + if (rn == 0xf) { /* literal */ offset = opcode & 0x0fff; snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD %s%d", - address, opcode, U ? "" : "-", offset); + address, opcode, u ? "" : "-", offset); } else { - uint8_t I, R; + uint8_t i, r; - I = (opcode & 0x02000000) >> 25; - R = (opcode & 0x00400000) >> 22; + i = (opcode & 0x02000000) >> 25; + r = (opcode & 0x00400000) >> 22; - if (I) { + if (i) { /* register PLD{W} [<Rn>,+/-<Rm>{, <shift>}] */ offset = (opcode & 0x0F80) >> 7; - uint8_t Rm; - Rm = opcode & 0xf; + uint8_t rm; + rm = opcode & 0xf; if (offset == 0) { /* No shift */ snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD%s [r%d, %sr%d]", - address, opcode, R ? "" : "W", Rn, U ? "" : "-", Rm); + address, opcode, r ? "" : "W", rn, u ? "" : "-", rm); } else { uint8_t shift; @@ -162,22 +162,22 @@ static int evaluate_pld(uint32_t opcode, /* LSL */ snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD%s [r%d, %sr%d, LSL #0x%x)", - address, opcode, R ? "" : "W", Rn, U ? "" : "-", Rm, offset); + address, opcode, r ? "" : "W", rn, u ? "" : "-", rm, offset); } else if (shift == 0x1) { /* LSR */ snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD%s [r%d, %sr%d, LSR #0x%x)", - address, opcode, R ? "" : "W", Rn, U ? "" : "-", Rm, offset); + address, opcode, r ? "" : "W", rn, u ? "" : "-", rm, offset); } else if (shift == 0x2) { /* ASR */ snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD%s [r%d, %sr%d, ASR #0x%x)", - address, opcode, R ? "" : "W", Rn, U ? "" : "-", Rm, offset); + address, opcode, r ? "" : "W", rn, u ? "" : "-", rm, offset); } else if (shift == 0x3) { /* ROR */ snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD%s [r%d, %sr%d, ROR #0x%x)", - address, opcode, R ? "" : "W", Rn, U ? "" : "-", Rm, offset); + address, opcode, r ? "" : "W", rn, u ? "" : "-", rm, offset); } } } else { @@ -186,11 +186,11 @@ static int evaluate_pld(uint32_t opcode, if (offset == 0) { snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD%s [r%d]", - address, opcode, R ? "" : "W", Rn); + address, opcode, r ? "" : "W", rn); } else { snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD%s [r%d, #%s%d]", - address, opcode, R ? "" : "W", Rn, U ? "" : "-", offset); + address, opcode, r ? "" : "W", rn, u ? "" : "-", offset); } } } @@ -349,13 +349,13 @@ static int evaluate_blx_imm(uint32_t opcode, static int evaluate_b_bl(uint32_t opcode, uint32_t address, struct arm_instruction *instruction) { - uint8_t L; + uint8_t l; uint32_t immediate; int offset; uint32_t target_address; immediate = opcode & 0x00ffffff; - L = (opcode & 0x01000000) >> 24; + l = (opcode & 0x01000000) >> 24; /* sign extend 24-bit immediate */ if (immediate & 0x00800000) @@ -368,7 +368,7 @@ static int evaluate_b_bl(uint32_t opcode, target_address = address + 8 + offset; - if (L) + if (l) instruction->type = ARM_BL; else instruction->type = ARM_B; @@ -378,7 +378,7 @@ static int evaluate_b_bl(uint32_t opcode, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tB%s%s 0x%8.8" PRIx32, address, opcode, - (L) ? "L" : "", + (l) ? "L" : "", COND(opcode), target_address); @@ -397,13 +397,13 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, /* MCRR or MRRC */ if (((opcode & 0x0ff00000) == 0x0c400000) || ((opcode & 0x0ff00000) == 0x0c500000)) { - uint8_t cp_opcode, Rd, Rn, CRm; + uint8_t cp_opcode, rd, rn, crm; char *mnemonic; cp_opcode = (opcode & 0xf0) >> 4; - Rd = (opcode & 0xf000) >> 12; - Rn = (opcode & 0xf0000) >> 16; - CRm = (opcode & 0xf); + rd = (opcode & 0xf000) >> 12; + rn = (opcode & 0xf0000) >> 16; + crm = (opcode & 0xf); /* MCRR */ if ((opcode & 0x0ff00000) == 0x0c400000) { @@ -424,15 +424,15 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, address, opcode, mnemonic, ((opcode & 0xf0000000) == 0xf0000000) ? "2" : COND(opcode), - COND(opcode), cp_num, cp_opcode, Rd, Rn, CRm); + COND(opcode), cp_num, cp_opcode, rd, rn, crm); } else {/* LDC or STC */ - uint8_t CRd, Rn, offset; - uint8_t U; + uint8_t crd, rn, offset; + uint8_t u; char *mnemonic; char addressing_mode[32]; - CRd = (opcode & 0xf000) >> 12; - Rn = (opcode & 0xf0000) >> 16; + crd = (opcode & 0xf000) >> 12; + rn = (opcode & 0xf0000) >> 16; offset = (opcode & 0xff) << 2; /* load/store */ @@ -444,21 +444,21 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, mnemonic = "STC"; } - U = (opcode & 0x00800000) >> 23; + u = (opcode & 0x00800000) >> 23; /* addressing modes */ if ((opcode & 0x01200000) == 0x01000000)/* offset */ snprintf(addressing_mode, 32, "[r%i, #%s%d]", - Rn, U ? "" : "-", offset); + rn, u ? "" : "-", offset); else if ((opcode & 0x01200000) == 0x01200000) /* pre-indexed */ snprintf(addressing_mode, 32, "[r%i, #%s%d]!", - Rn, U ? "" : "-", offset); + rn, u ? "" : "-", offset); else if ((opcode & 0x01200000) == 0x00200000) /* post-indexed */ snprintf(addressing_mode, 32, "[r%i], #%s%d", - Rn, U ? "" : "-", offset); + rn, u ? "" : "-", offset); else if ((opcode & 0x01200000) == 0x00000000) /* unindexed */ snprintf(addressing_mode, 32, "[r%i], {%d}", - Rn, offset >> 2); + rn, offset >> 2); snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 @@ -467,7 +467,7 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, ((opcode & 0xf0000000) == 0xf0000000) ? "2" : COND(opcode), (opcode & (1 << 22)) ? "L" : "", - cp_num, CRd, addressing_mode); + cp_num, crd, addressing_mode); } return ERROR_OK; @@ -481,13 +481,13 @@ static int evaluate_cdp_mcr_mrc(uint32_t opcode, { const char *cond; char *mnemonic; - uint8_t cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2; + uint8_t cp_num, opcode_1, crd_rd, crn, crm, opcode_2; cond = ((opcode & 0xf0000000) == 0xf0000000) ? "2" : COND(opcode); cp_num = (opcode & 0xf00) >> 8; - CRd_Rd = (opcode & 0xf000) >> 12; - CRn = (opcode & 0xf0000) >> 16; - CRm = (opcode & 0xf); + crd_rd = (opcode & 0xf000) >> 12; + crn = (opcode & 0xf0000) >> 16; + crm = (opcode & 0xf); opcode_2 = (opcode & 0xe0) >> 5; /* CDP or MRC/MCR */ @@ -511,9 +511,9 @@ static int evaluate_cdp_mcr_mrc(uint32_t opcode, cond, cp_num, opcode_1, - CRd_Rd, - CRn, - CRm, + crd_rd, + crn, + crm, opcode_2); } else {/* bit 4 not set -> CDP */ instruction->type = ARM_CDP; @@ -530,9 +530,9 @@ static int evaluate_cdp_mcr_mrc(uint32_t opcode, cond, cp_num, opcode_1, - CRd_Rd, - CRn, - CRm, + crd_rd, + crn, + crm, opcode_2); } @@ -543,60 +543,60 @@ static int evaluate_cdp_mcr_mrc(uint32_t opcode, static int evaluate_load_store(uint32_t opcode, uint32_t address, struct arm_instruction *instruction) { - uint8_t I, P, U, B, W, L; - uint8_t Rn, Rd; + uint8_t i, p, u, b, w, l; + uint8_t rn, rd; char *operation;/* "LDR" or "STR" */ char *suffix; /* "", "B", "T", "BT" */ char offset[32]; /* examine flags */ - I = (opcode & 0x02000000) >> 25; - P = (opcode & 0x01000000) >> 24; - U = (opcode & 0x00800000) >> 23; - B = (opcode & 0x00400000) >> 22; - W = (opcode & 0x00200000) >> 21; - L = (opcode & 0x00100000) >> 20; + i = (opcode & 0x02000000) >> 25; + p = (opcode & 0x01000000) >> 24; + u = (opcode & 0x00800000) >> 23; + b = (opcode & 0x00400000) >> 22; + w = (opcode & 0x00200000) >> 21; + l = (opcode & 0x00100000) >> 20; /* target register */ - Rd = (opcode & 0xf000) >> 12; + rd = (opcode & 0xf000) >> 12; /* base register */ - Rn = (opcode & 0xf0000) >> 16; + rn = (opcode & 0xf0000) >> 16; - instruction->info.load_store.Rd = Rd; - instruction->info.load_store.Rn = Rn; - instruction->info.load_store.U = U; + instruction->info.load_store.rd = rd; + instruction->info.load_store.rn = rn; + instruction->info.load_store.u = u; /* determine operation */ - if (L) + if (l) operation = "LDR"; else operation = "STR"; /* determine instruction type and suffix */ - if (B) { - if ((P == 0) && (W == 1)) { - if (L) + if (b) { + if ((p == 0) && (w == 1)) { + if (l) instruction->type = ARM_LDRBT; else instruction->type = ARM_STRBT; suffix = "BT"; } else { - if (L) + if (l) instruction->type = ARM_LDRB; else instruction->type = ARM_STRB; suffix = "B"; } } else { - if ((P == 0) && (W == 1)) { - if (L) + if ((p == 0) && (w == 1)) { + if (l) instruction->type = ARM_LDRT; else instruction->type = ARM_STRT; suffix = "T"; } else { - if (L) + if (l) instruction->type = ARM_LDR; else instruction->type = ARM_STR; @@ -604,10 +604,10 @@ static int evaluate_load_store(uint32_t opcode, } } - if (!I) { /* #+-<offset_12> */ + if (!i) { /* #+-<offset_12> */ uint32_t offset_12 = (opcode & 0xfff); if (offset_12) - snprintf(offset, 32, ", #%s0x%" PRIx32 "", (U) ? "" : "-", offset_12); + snprintf(offset, 32, ", #%s0x%" PRIx32 "", (u) ? "" : "-", offset_12); else snprintf(offset, 32, "%s", ""); @@ -615,11 +615,11 @@ static int evaluate_load_store(uint32_t opcode, instruction->info.load_store.offset.offset = offset_12; } else {/* either +-<Rm> or +-<Rm>, <shift>, #<shift_imm> */ uint8_t shift_imm, shift; - uint8_t Rm; + uint8_t rm; shift_imm = (opcode & 0xf80) >> 7; shift = (opcode & 0x60) >> 5; - Rm = (opcode & 0xf); + rm = (opcode & 0xf); /* LSR encodes a shift by 32 bit as 0x0 */ if ((shift == 0x1) && (shift_imm == 0x0)) @@ -634,35 +634,35 @@ static int evaluate_load_store(uint32_t opcode, shift = 0x4; instruction->info.load_store.offset_mode = 1; - instruction->info.load_store.offset.reg.Rm = Rm; + instruction->info.load_store.offset.reg.rm = rm; instruction->info.load_store.offset.reg.shift = shift; instruction->info.load_store.offset.reg.shift_imm = shift_imm; if ((shift_imm == 0x0) && (shift == 0x0)) /* +-<Rm> */ - snprintf(offset, 32, ", %sr%i", (U) ? "" : "-", Rm); + snprintf(offset, 32, ", %sr%i", (u) ? "" : "-", rm); else { /* +-<Rm>, <Shift>, #<shift_imm> */ switch (shift) { case 0x0: /* LSL */ - snprintf(offset, 32, ", %sr%i, LSL #0x%x", (U) ? "" : "-", Rm, shift_imm); + snprintf(offset, 32, ", %sr%i, LSL #0x%x", (u) ? "" : "-", rm, shift_imm); break; case 0x1: /* LSR */ - snprintf(offset, 32, ", %sr%i, LSR #0x%x", (U) ? "" : "-", Rm, shift_imm); + snprintf(offset, 32, ", %sr%i, LSR #0x%x", (u) ? "" : "-", rm, shift_imm); break; case 0x2: /* ASR */ - snprintf(offset, 32, ", %sr%i, ASR #0x%x", (U) ? "" : "-", Rm, shift_imm); + snprintf(offset, 32, ", %sr%i, ASR #0x%x", (u) ? "" : "-", rm, shift_imm); break; case 0x3: /* ROR */ - snprintf(offset, 32, ", %sr%i, ROR #0x%x", (U) ? "" : "-", Rm, shift_imm); + snprintf(offset, 32, ", %sr%i, ROR #0x%x", (u) ? "" : "-", rm, shift_imm); break; case 0x4: /* RRX */ - snprintf(offset, 32, ", %sr%i, RRX", (U) ? "" : "-", Rm); + snprintf(offset, 32, ", %sr%i, RRX", (u) ? "" : "-", rm); break; } } } - if (P == 1) { - if (W == 0) { /* offset */ + if (p == 1) { + if (w == 0) { /* offset */ snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i%s]", @@ -671,8 +671,8 @@ static int evaluate_load_store(uint32_t opcode, operation, COND(opcode), suffix, - Rd, - Rn, + rd, + rn, offset); instruction->info.load_store.index_mode = 0; @@ -685,8 +685,8 @@ static int evaluate_load_store(uint32_t opcode, operation, COND(opcode), suffix, - Rd, - Rn, + rd, + rn, offset); instruction->info.load_store.index_mode = 1; @@ -700,8 +700,8 @@ static int evaluate_load_store(uint32_t opcode, operation, COND(opcode), suffix, - Rd, - Rn, + rd, + rn, offset); instruction->info.load_store.index_mode = 2; @@ -1029,35 +1029,35 @@ undef: static int evaluate_misc_load_store(uint32_t opcode, uint32_t address, struct arm_instruction *instruction) { - uint8_t P, U, I, W, L, S, H; - uint8_t Rn, Rd; + uint8_t p, u, i, w, l, s, h; + uint8_t rn, rd; char *operation;/* "LDR" or "STR" */ char *suffix; /* "H", "SB", "SH", "D" */ char offset[32]; /* examine flags */ - P = (opcode & 0x01000000) >> 24; - U = (opcode & 0x00800000) >> 23; - I = (opcode & 0x00400000) >> 22; - W = (opcode & 0x00200000) >> 21; - L = (opcode & 0x00100000) >> 20; - S = (opcode & 0x00000040) >> 6; - H = (opcode & 0x00000020) >> 5; + p = (opcode & 0x01000000) >> 24; + u = (opcode & 0x00800000) >> 23; + i = (opcode & 0x00400000) >> 22; + w = (opcode & 0x00200000) >> 21; + l = (opcode & 0x00100000) >> 20; + s = (opcode & 0x00000040) >> 6; + h = (opcode & 0x00000020) >> 5; /* target register */ - Rd = (opcode & 0xf000) >> 12; + rd = (opcode & 0xf000) >> 12; /* base register */ - Rn = (opcode & 0xf0000) >> 16; + rn = (opcode & 0xf0000) >> 16; - instruction->info.load_store.Rd = Rd; - instruction->info.load_store.Rn = Rn; - instruction->info.load_store.U = U; + instruction->info.load_store.rd = rd; + instruction->info.load_store.rn = rn; + instruction->info.load_store.u = u; /* determine instruction type and suffix */ - if (S) {/* signed */ - if (L) {/* load */ - if (H) { + if (s) {/* signed */ + if (l) {/* load */ + if (h) { operation = "LDR"; instruction->type = ARM_LDRSH; suffix = "SH"; @@ -1069,7 +1069,7 @@ static int evaluate_misc_load_store(uint32_t opcode, } else {/* there are no signed stores, so this is used to encode double-register *load/stores */ suffix = "D"; - if (H) { + if (h) { operation = "STR"; instruction->type = ARM_STRD; } else { @@ -1079,7 +1079,7 @@ static int evaluate_misc_load_store(uint32_t opcode, } } else {/* unsigned */ suffix = "H"; - if (L) {/* load */ + if (l) {/* load */ operation = "LDR"; instruction->type = ARM_LDRH; } else {/* store */ @@ -1088,25 +1088,25 @@ static int evaluate_misc_load_store(uint32_t opcode, } } - if (I) {/* Immediate offset/index (#+-<offset_8>)*/ + if (i) {/* Immediate offset/index (#+-<offset_8>)*/ uint32_t offset_8 = ((opcode & 0xf00) >> 4) | (opcode & 0xf); - snprintf(offset, 32, "#%s0x%" PRIx32 "", (U) ? "" : "-", offset_8); + snprintf(offset, 32, "#%s0x%" PRIx32 "", (u) ? "" : "-", offset_8); instruction->info.load_store.offset_mode = 0; instruction->info.load_store.offset.offset = offset_8; } else {/* Register offset/index (+-<Rm>) */ - uint8_t Rm; - Rm = (opcode & 0xf); - snprintf(offset, 32, "%sr%i", (U) ? "" : "-", Rm); + uint8_t rm; + rm = (opcode & 0xf); + snprintf(offset, 32, "%sr%i", (u) ? "" : "-", rm); instruction->info.load_store.offset_mode = 1; - instruction->info.load_store.offset.reg.Rm = Rm; + instruction->info.load_store.offset.reg.rm = rm; instruction->info.load_store.offset.reg.shift = 0x0; instruction->info.load_store.offset.reg.shift_imm = 0x0; } - if (P == 1) { - if (W == 0) { /* offset */ + if (p == 1) { + if (w == 0) { /* offset */ snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i, %s]", @@ -1115,8 +1115,8 @@ static int evaluate_misc_load_store(uint32_t opcode, operation, COND(opcode), suffix, - Rd, - Rn, + rd, + rn, offset); instruction->info.load_store.index_mode = 0; @@ -1129,8 +1129,8 @@ static int evaluate_misc_load_store(uint32_t opcode, operation, COND(opcode), suffix, - Rd, - Rn, + rd, + rn, offset); instruction->info.load_store.index_mode = 1; @@ -1144,8 +1144,8 @@ static int evaluate_misc_load_store(uint32_t opcode, operation, COND(opcode), suffix, - Rd, - Rn, + rd, + rn, offset); instruction->info.load_store.index_mode = 2; @@ -1158,7 +1158,7 @@ static int evaluate_misc_load_store(uint32_t opcode, static int evaluate_ldm_stm(uint32_t opcode, uint32_t address, struct arm_instruction *instruction) { - uint8_t P, U, S, W, L, Rn; + uint8_t p, u, s, w, l, rn; uint32_t register_list; char *addressing_mode; char *mnemonic; @@ -1167,20 +1167,20 @@ static int evaluate_ldm_stm(uint32_t opcode, int i; int first_reg = 1; - P = (opcode & 0x01000000) >> 24; - U = (opcode & 0x00800000) >> 23; - S = (opcode & 0x00400000) >> 22; - W = (opcode & 0x00200000) >> 21; - L = (opcode & 0x00100000) >> 20; + p = (opcode & 0x01000000) >> 24; + u = (opcode & 0x00800000) >> 23; + s = (opcode & 0x00400000) >> 22; + w = (opcode & 0x00200000) >> 21; + l = (opcode & 0x00100000) >> 20; register_list = (opcode & 0xffff); - Rn = (opcode & 0xf0000) >> 16; + rn = (opcode & 0xf0000) >> 16; - instruction->info.load_store_multiple.Rn = Rn; + instruction->info.load_store_multiple.rn = rn; instruction->info.load_store_multiple.register_list = register_list; - instruction->info.load_store_multiple.S = S; - instruction->info.load_store_multiple.W = W; + instruction->info.load_store_multiple.s = s; + instruction->info.load_store_multiple.w = w; - if (L) { + if (l) { instruction->type = ARM_LDM; mnemonic = "LDM"; } else { @@ -1188,8 +1188,8 @@ static int evaluate_ldm_stm(uint32_t opcode, mnemonic = "STM"; } - if (P) { - if (U) { + if (p) { + if (u) { instruction->info.load_store_multiple.addressing_mode = 1; addressing_mode = "IB"; } else { @@ -1197,7 +1197,7 @@ static int evaluate_ldm_stm(uint32_t opcode, addressing_mode = "DB"; } } else { - if (U) { + if (u) { instruction->info.load_store_multiple.addressing_mode = 0; /* "IA" is the default in UAL syntax */ addressing_mode = ""; @@ -1229,7 +1229,7 @@ static int evaluate_ldm_stm(uint32_t opcode, "\t%s%s%s r%i%s, {%s}%s", address, opcode, mnemonic, addressing_mode, COND(opcode), - Rn, (W) ? "!" : "", reg_list, (S) ? "^" : ""); + rn, (w) ? "!" : "", reg_list, (s) ? "^" : ""); return ERROR_OK; } @@ -1242,12 +1242,12 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode, if ((opcode & 0x000000f0) == 0x00000090) { /* Multiply (accumulate) */ if ((opcode & 0x0f800000) == 0x00000000) { - uint8_t Rm, Rs, Rn, Rd, S; - Rm = opcode & 0xf; - Rs = (opcode & 0xf00) >> 8; - Rn = (opcode & 0xf000) >> 12; - Rd = (opcode & 0xf0000) >> 16; - S = (opcode & 0x00100000) >> 20; + uint8_t rm, rs, rn, rd, s; + rm = opcode & 0xf; + rs = (opcode & 0xf00) >> 8; + rn = (opcode & 0xf000) >> 12; + rd = (opcode & 0xf0000) >> 16; + s = (opcode & 0x00100000) >> 20; /* examine A bit (accumulate) */ if (opcode & 0x00200000) { @@ -1258,11 +1258,11 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode, address, opcode, COND(opcode), - (S) ? "S" : "", - Rd, - Rm, - Rs, - Rn); + (s) ? "S" : "", + rd, + rm, + rs, + rn); } else { instruction->type = ARM_MUL; snprintf(instruction->text, @@ -1271,10 +1271,10 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode, address, opcode, COND(opcode), - (S) ? "S" : "", - Rd, - Rm, - Rs); + (s) ? "S" : "", + rd, + rm, + rs); } return ERROR_OK; @@ -1283,12 +1283,12 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode, /* Multiply (accumulate) long */ if ((opcode & 0x0f800000) == 0x00800000) { char *mnemonic = NULL; - uint8_t Rm, Rs, RdHi, RdLow, S; - Rm = opcode & 0xf; - Rs = (opcode & 0xf00) >> 8; - RdHi = (opcode & 0xf000) >> 12; - RdLow = (opcode & 0xf0000) >> 16; - S = (opcode & 0x00100000) >> 20; + uint8_t rm, rs, rd_hi, rd_low, s; + rm = opcode & 0xf; + rs = (opcode & 0xf00) >> 8; + rd_hi = (opcode & 0xf000) >> 12; + rd_low = (opcode & 0xf0000) >> 16; + s = (opcode & 0x00100000) >> 20; switch ((opcode & 0x00600000) >> 21) { case 0x0: @@ -1316,21 +1316,21 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode, opcode, mnemonic, COND(opcode), - (S) ? "S" : "", - RdLow, - RdHi, - Rm, - Rs); + (s) ? "S" : "", + rd_low, + rd_hi, + rm, + rs); return ERROR_OK; } /* Swap/swap byte */ if ((opcode & 0x0f800000) == 0x01000000) { - uint8_t Rm, Rd, Rn; - Rm = opcode & 0xf; - Rd = (opcode & 0xf000) >> 12; - Rn = (opcode & 0xf0000) >> 16; + uint8_t rm, rd, rn; + rm = opcode & 0xf; + rd = (opcode & 0xf000) >> 12; + rn = (opcode & 0xf0000) >> 16; /* examine B flag */ instruction->type = (opcode & 0x00400000) ? ARM_SWPB : ARM_SWP; @@ -1342,9 +1342,9 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode, opcode, (opcode & 0x00400000) ? "SWPB" : "SWP", COND(opcode), - Rd, - Rm, - Rn); + rd, + rm, + rn); return ERROR_OK; } @@ -1356,8 +1356,8 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode, static int evaluate_mrs_msr(uint32_t opcode, uint32_t address, struct arm_instruction *instruction) { - int R = (opcode & 0x00400000) >> 22; - char *PSR = (R) ? "SPSR" : "CPSR"; + int r = (opcode & 0x00400000) >> 22; + char *PSR = (r) ? "SPSR" : "CPSR"; /* Move register to status register (MSR) */ if (opcode & 0x00200000) { @@ -1382,7 +1382,7 @@ static int evaluate_mrs_msr(uint32_t opcode, ror(immediate, (rotate * 2)) ); } else {/* register variant */ - uint8_t Rm = opcode & 0xf; + uint8_t rm = opcode & 0xf; snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMSR%s %s_%s%s%s%s, r%i", @@ -1394,15 +1394,15 @@ static int evaluate_mrs_msr(uint32_t opcode, (opcode & 0x20000) ? "x" : "", (opcode & 0x40000) ? "s" : "", (opcode & 0x80000) ? "f" : "", - Rm + rm ); } } else {/* Move status register to register (MRS) */ - uint8_t Rd; + uint8_t rd; instruction->type = ARM_MRS; - Rd = (opcode & 0x0000f000) >> 12; + rd = (opcode & 0x0000f000) >> 12; snprintf(instruction->text, 128, @@ -1410,7 +1410,7 @@ static int evaluate_mrs_msr(uint32_t opcode, address, opcode, COND(opcode), - Rd, + rd, PSR); } @@ -1427,37 +1427,37 @@ static int evaluate_misc_instr(uint32_t opcode, /* BX */ if ((opcode & 0x006000f0) == 0x00200010) { - uint8_t Rm; + uint8_t rm; instruction->type = ARM_BX; - Rm = opcode & 0xf; + rm = opcode & 0xf; snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBX%s r%i", - address, opcode, COND(opcode), Rm); + address, opcode, COND(opcode), rm); - instruction->info.b_bl_bx_blx.reg_operand = Rm; + instruction->info.b_bl_bx_blx.reg_operand = rm; instruction->info.b_bl_bx_blx.target_address = -1; } /* BXJ - "Jazelle" support (ARMv5-J) */ if ((opcode & 0x006000f0) == 0x00200020) { - uint8_t Rm; + uint8_t rm; instruction->type = ARM_BX; - Rm = opcode & 0xf; + rm = opcode & 0xf; snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBXJ%s r%i", - address, opcode, COND(opcode), Rm); + address, opcode, COND(opcode), rm); - instruction->info.b_bl_bx_blx.reg_operand = Rm; + instruction->info.b_bl_bx_blx.reg_operand = rm; instruction->info.b_bl_bx_blx.target_address = -1; } /* CLZ */ if ((opcode & 0x006000f0) == 0x00600010) { - uint8_t Rm, Rd; + uint8_t rm, rd; instruction->type = ARM_CLZ; - Rm = opcode & 0xf; - Rd = (opcode & 0xf000) >> 12; + rm = opcode & 0xf; + rd = (opcode & 0xf000) >> 12; snprintf(instruction->text, 128, @@ -1465,30 +1465,30 @@ static int evaluate_misc_instr(uint32_t opcode, address, opcode, COND(opcode), - Rd, - Rm); + rd, + rm); } /* BLX(2) */ if ((opcode & 0x006000f0) == 0x00200030) { - uint8_t Rm; + uint8_t rm; instruction->type = ARM_BLX; - Rm = opcode & 0xf; + rm = opcode & 0xf; snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX%s r%i", - address, opcode, COND(opcode), Rm); + address, opcode, COND(opcode), rm); - instruction->info.b_bl_bx_blx.reg_operand = Rm; + instruction->info.b_bl_bx_blx.reg_operand = rm; instruction->info.b_bl_bx_blx.target_address = -1; } /* Enhanced DSP add/subtracts */ if ((opcode & 0x0000000f0) == 0x00000050) { - uint8_t Rm, Rd, Rn; + uint8_t rm, rd, rn; char *mnemonic = NULL; - Rm = opcode & 0xf; - Rd = (opcode & 0xf000) >> 12; - Rn = (opcode & 0xf0000) >> 16; + rm = opcode & 0xf; + rd = (opcode & 0xf000) >> 12; + rn = (opcode & 0xf0000) >> 16; switch ((opcode & 0x00600000) >> 21) { case 0x0: @@ -1516,9 +1516,9 @@ static int evaluate_misc_instr(uint32_t opcode, opcode, mnemonic, COND(opcode), - Rd, - Rm, - Rn); + rd, + rm, + rn); } /* exception return */ @@ -1571,12 +1571,12 @@ static int evaluate_misc_instr(uint32_t opcode, /* SMLA < x><y> */ if ((opcode & 0x00600000) == 0x00000000) { - uint8_t Rd, Rm, Rs, Rn; - instruction->type = ARM_SMLAxy; - Rd = (opcode & 0xf0000) >> 16; - Rm = (opcode & 0xf); - Rs = (opcode & 0xf00) >> 8; - Rn = (opcode & 0xf000) >> 12; + uint8_t rd, rm, rs, rn; + instruction->type = ARM_SMLAXY; + rd = (opcode & 0xf0000) >> 16; + rm = (opcode & 0xf); + rs = (opcode & 0xf00) >> 8; + rn = (opcode & 0xf000) >> 12; snprintf(instruction->text, 128, @@ -1586,20 +1586,20 @@ static int evaluate_misc_instr(uint32_t opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode), - Rd, - Rm, - Rs, - Rn); + rd, + rm, + rs, + rn); } /* SMLAL < x><y> */ if ((opcode & 0x00600000) == 0x00400000) { - uint8_t RdLow, RdHi, Rm, Rs; - instruction->type = ARM_SMLAxy; - RdHi = (opcode & 0xf0000) >> 16; - RdLow = (opcode & 0xf000) >> 12; - Rm = (opcode & 0xf); - Rs = (opcode & 0xf00) >> 8; + uint8_t rd_low, rd_hi, rm, rs; + instruction->type = ARM_SMLAXY; + rd_hi = (opcode & 0xf0000) >> 16; + rd_low = (opcode & 0xf000) >> 12; + rm = (opcode & 0xf); + rs = (opcode & 0xf00) >> 8; snprintf(instruction->text, 128, @@ -1609,20 +1609,20 @@ static int evaluate_misc_instr(uint32_t opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode), - RdLow, - RdHi, - Rm, - Rs); + rd_low, + rd_hi, + rm, + rs); } /* SMLAW < y> */ if (((opcode & 0x00600000) == 0x00200000) && (x == 0)) { - uint8_t Rd, Rm, Rs, Rn; - instruction->type = ARM_SMLAWy; - Rd = (opcode & 0xf0000) >> 16; - Rm = (opcode & 0xf); - Rs = (opcode & 0xf00) >> 8; - Rn = (opcode & 0xf000) >> 12; + uint8_t rd, rm, rs, rn; + instruction->type = ARM_SMLAWY; + rd = (opcode & 0xf0000) >> 16; + rm = (opcode & 0xf); + rs = (opcode & 0xf00) >> 8; + rn = (opcode & 0xf000) >> 12; snprintf(instruction->text, 128, @@ -1631,19 +1631,19 @@ static int evaluate_misc_instr(uint32_t opcode, opcode, (y) ? "T" : "B", COND(opcode), - Rd, - Rm, - Rs, - Rn); + rd, + rm, + rs, + rn); } /* SMUL < x><y> */ if ((opcode & 0x00600000) == 0x00600000) { - uint8_t Rd, Rm, Rs; - instruction->type = ARM_SMULxy; - Rd = (opcode & 0xf0000) >> 16; - Rm = (opcode & 0xf); - Rs = (opcode & 0xf00) >> 8; + uint8_t rd, rm, rs; + instruction->type = ARM_SMULXY; + rd = (opcode & 0xf0000) >> 16; + rm = (opcode & 0xf); + rs = (opcode & 0xf00) >> 8; snprintf(instruction->text, 128, @@ -1653,18 +1653,18 @@ static int evaluate_misc_instr(uint32_t opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode), - Rd, - Rm, - Rs); + rd, + rm, + rs); } /* SMULW < y> */ if (((opcode & 0x00600000) == 0x00200000) && (x == 1)) { - uint8_t Rd, Rm, Rs; - instruction->type = ARM_SMULWy; - Rd = (opcode & 0xf0000) >> 16; - Rm = (opcode & 0xf); - Rs = (opcode & 0xf00) >> 8; + uint8_t rd, rm, rs; + instruction->type = ARM_SMULWY; + rd = (opcode & 0xf0000) >> 16; + rm = (opcode & 0xf); + rs = (opcode & 0xf00) >> 8; snprintf(instruction->text, 128, @@ -1673,9 +1673,9 @@ static int evaluate_misc_instr(uint32_t opcode, opcode, (y) ? "T" : "B", COND(opcode), - Rd, - Rm, - Rs); + rd, + rm, + rs); } } @@ -1686,24 +1686,24 @@ static int evaluate_mov_imm(uint32_t opcode, uint32_t address, struct arm_instruction *instruction) { uint16_t immediate; - uint8_t Rd; - bool T; + uint8_t rd; + bool t; - Rd = (opcode & 0xf000) >> 12; - T = opcode & 0x00400000; + rd = (opcode & 0xf000) >> 12; + t = opcode & 0x00400000; immediate = (opcode & 0xf0000) >> 4 | (opcode & 0xfff); instruction->type = ARM_MOV; - instruction->info.data_proc.Rd = Rd; + instruction->info.data_proc.rd = rd; snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMOV%s%s r%i, #0x%" PRIx16, address, opcode, - T ? "T" : "W", + t ? "T" : "W", COND(opcode), - Rd, + rd, immediate); return ERROR_OK; @@ -1712,20 +1712,20 @@ static int evaluate_mov_imm(uint32_t opcode, static int evaluate_data_proc(uint32_t opcode, uint32_t address, struct arm_instruction *instruction) { - uint8_t I, op, S, Rn, Rd; + uint8_t i, op, s, rn, rd; char *mnemonic = NULL; char shifter_operand[32]; - I = (opcode & 0x02000000) >> 25; + i = (opcode & 0x02000000) >> 25; op = (opcode & 0x01e00000) >> 21; - S = (opcode & 0x00100000) >> 20; + s = (opcode & 0x00100000) >> 20; - Rd = (opcode & 0xf000) >> 12; - Rn = (opcode & 0xf0000) >> 16; + rd = (opcode & 0xf000) >> 12; + rn = (opcode & 0xf0000) >> 16; - instruction->info.data_proc.Rd = Rd; - instruction->info.data_proc.Rn = Rn; - instruction->info.data_proc.S = S; + instruction->info.data_proc.rd = rd; + instruction->info.data_proc.rn = rn; + instruction->info.data_proc.s = s; switch (op) { case 0x0: @@ -1794,7 +1794,7 @@ static int evaluate_data_proc(uint32_t opcode, break; } - if (I) {/* immediate shifter operand (#<immediate>)*/ + if (i) {/* immediate shifter operand (#<immediate>)*/ uint8_t immed_8 = opcode & 0xff; uint8_t rotate_imm = (opcode & 0xf00) >> 8; uint32_t immediate; @@ -1806,9 +1806,9 @@ static int evaluate_data_proc(uint32_t opcode, instruction->info.data_proc.variant = 0; instruction->info.data_proc.shifter_operand.immediate.immediate = immediate; } else {/* register-based shifter operand */ - uint8_t shift, Rm; + uint8_t shift, rm; shift = (opcode & 0x60) >> 5; - Rm = (opcode & 0xf); + rm = (opcode & 0xf); if ((opcode & 0x10) != 0x10) { /* Immediate shifts ("<Rm>" or "<Rm>, <shift> *#<shift_immediate>") */ @@ -1816,7 +1816,7 @@ static int evaluate_data_proc(uint32_t opcode, shift_imm = (opcode & 0xf80) >> 7; instruction->info.data_proc.variant = 1; - instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm; + instruction->info.data_proc.shifter_operand.immediate_shift.rm = rm; instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = shift_imm; instruction->info.data_proc.shifter_operand.immediate_shift.shift = shift; @@ -1834,51 +1834,51 @@ static int evaluate_data_proc(uint32_t opcode, shift = 0x4; if ((shift_imm == 0x0) && (shift == 0x0)) - snprintf(shifter_operand, 32, "r%i", Rm); + snprintf(shifter_operand, 32, "r%i", rm); else { if (shift == 0x0) /* LSL */ snprintf(shifter_operand, 32, "r%i, LSL #0x%x", - Rm, + rm, shift_imm); else if (shift == 0x1) /* LSR */ snprintf(shifter_operand, 32, "r%i, LSR #0x%x", - Rm, + rm, shift_imm); else if (shift == 0x2) /* ASR */ snprintf(shifter_operand, 32, "r%i, ASR #0x%x", - Rm, + rm, shift_imm); else if (shift == 0x3) /* ROR */ snprintf(shifter_operand, 32, "r%i, ROR #0x%x", - Rm, + rm, shift_imm); else if (shift == 0x4) /* RRX */ - snprintf(shifter_operand, 32, "r%i, RRX", Rm); + snprintf(shifter_operand, 32, "r%i, RRX", rm); } } else {/* Register shifts ("<Rm>, <shift> <Rs>") */ - uint8_t Rs = (opcode & 0xf00) >> 8; + uint8_t rs = (opcode & 0xf00) >> 8; instruction->info.data_proc.variant = 2; - instruction->info.data_proc.shifter_operand.register_shift.Rm = Rm; - instruction->info.data_proc.shifter_operand.register_shift.Rs = Rs; + instruction->info.data_proc.shifter_operand.register_shift.rm = rm; + instruction->info.data_proc.shifter_operand.register_shift.rs = rs; instruction->info.data_proc.shifter_operand.register_shift.shift = shift; if (shift == 0x0) /* LSL */ - snprintf(shifter_operand, 32, "r%i, LSL r%i", Rm, Rs); + snprintf(shifter_operand, 32, "r%i, LSL r%i", rm, rs); else if (shift == 0x1) /* LSR */ - snprintf(shifter_operand, 32, "r%i, LSR r%i", Rm, Rs); + snprintf(shifter_operand, 32, "r%i, LSR r%i", rm, rs); else if (shift == 0x2) /* ASR */ - snprintf(shifter_operand, 32, "r%i, ASR r%i", Rm, Rs); + snprintf(shifter_operand, 32, "r%i, ASR r%i", rm, rs); else if (shift == 0x3) /* ROR */ - snprintf(shifter_operand, 32, "r%i, ROR r%i", Rm, Rs); + snprintf(shifter_operand, 32, "r%i, ROR r%i", rm, rs); } } @@ -1891,9 +1891,9 @@ static int evaluate_data_proc(uint32_t opcode, opcode, mnemonic, COND(opcode), - (S) ? "S" : "", - Rd, - Rn, + (s) ? "S" : "", + rd, + rn, shifter_operand); } else if ((op == 0xd) || (op == 0xf)) { /* <opcode1>{<cond>}{S} <Rd>, *<shifter_operand> */ @@ -1911,13 +1911,13 @@ static int evaluate_data_proc(uint32_t opcode, opcode, mnemonic, COND(opcode), - (S) ? "S" : "", - Rd, + (s) ? "S" : "", + rd, shifter_operand); } else {/* <opcode2>{<cond>} <Rn>, <shifter_operand> */ snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, %s", address, opcode, mnemonic, COND(opcode), - Rn, shifter_operand); + rn, shifter_operand); } return ERROR_OK; @@ -2123,9 +2123,9 @@ static int evaluate_b_bl_blx_thumb(uint16_t opcode, static int evaluate_add_sub_thumb(uint16_t opcode, uint32_t address, struct arm_instruction *instruction) { - uint8_t Rd = (opcode >> 0) & 0x7; - uint8_t Rn = (opcode >> 3) & 0x7; - uint8_t Rm_imm = (opcode >> 6) & 0x7; + uint8_t rd = (opcode >> 0) & 0x7; + uint8_t rn = (opcode >> 3) & 0x7; + uint8_t rm_imm = (opcode >> 6) & 0x7; uint32_t opc = opcode & (1 << 9); uint32_t reg_imm = opcode & (1 << 10); char *mnemonic; @@ -2139,22 +2139,22 @@ static int evaluate_add_sub_thumb(uint16_t opcode, mnemonic = "ADDS"; } - instruction->info.data_proc.Rd = Rd; - instruction->info.data_proc.Rn = Rn; - instruction->info.data_proc.S = 1; + instruction->info.data_proc.rd = rd; + instruction->info.data_proc.rn = rn; + instruction->info.data_proc.s = 1; if (reg_imm) { instruction->info.data_proc.variant = 0;/*immediate*/ - instruction->info.data_proc.shifter_operand.immediate.immediate = Rm_imm; + instruction->info.data_proc.shifter_operand.immediate.immediate = rm_imm; snprintf(instruction->text, 128, "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, #%d", - address, opcode, mnemonic, Rd, Rn, Rm_imm); + address, opcode, mnemonic, rd, rn, rm_imm); } else { instruction->info.data_proc.variant = 1;/*immediate shift*/ - instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm_imm; + instruction->info.data_proc.shifter_operand.immediate_shift.rm = rm_imm; snprintf(instruction->text, 128, "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, r%i", - address, opcode, mnemonic, Rd, Rn, Rm_imm); + address, opcode, mnemonic, rd, rn, rm_imm); } return ERROR_OK; @@ -2163,8 +2163,8 @@ static int evaluate_add_sub_thumb(uint16_t opcode, static int evaluate_shift_imm_thumb(uint16_t opcode, uint32_t address, struct arm_instruction *instruction) { - uint8_t Rd = (opcode >> 0) & 0x7; - uint8_t Rm = (opcode >> 3) & 0x7; + uint8_t rd = (opcode >> 0) & 0x7; + uint8_t rm = (opcode >> 3) & 0x7; uint8_t imm = (opcode >> 6) & 0x1f; uint8_t opc = (opcode >> 11) & 0x3; char *mnemonic = NULL; @@ -2190,17 +2190,17 @@ static int evaluate_shift_imm_thumb(uint16_t opcode, if ((imm == 0) && (opc != 0)) imm = 32; - instruction->info.data_proc.Rd = Rd; - instruction->info.data_proc.Rn = -1; - instruction->info.data_proc.S = 1; + instruction->info.data_proc.rd = rd; + instruction->info.data_proc.rn = -1; + instruction->info.data_proc.s = 1; instruction->info.data_proc.variant = 1;/*immediate_shift*/ - instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm; + instruction->info.data_proc.shifter_operand.immediate_shift.rm = rm; instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = imm; snprintf(instruction->text, 128, "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, #%#2.2x", - address, opcode, mnemonic, Rd, Rm, imm); + address, opcode, mnemonic, rd, rm, imm); return ERROR_OK; } @@ -2209,13 +2209,13 @@ static int evaluate_data_proc_imm_thumb(uint16_t opcode, uint32_t address, struct arm_instruction *instruction) { uint8_t imm = opcode & 0xff; - uint8_t Rd = (opcode >> 8) & 0x7; + uint8_t rd = (opcode >> 8) & 0x7; uint32_t opc = (opcode >> 11) & 0x3; char *mnemonic = NULL; - instruction->info.data_proc.Rd = Rd; - instruction->info.data_proc.Rn = Rd; - instruction->info.data_proc.S = 1; + instruction->info.data_proc.rd = rd; + instruction->info.data_proc.rn = rd; + instruction->info.data_proc.s = 1; instruction->info.data_proc.variant = 0;/*immediate*/ instruction->info.data_proc.shifter_operand.immediate.immediate = imm; @@ -2223,12 +2223,12 @@ static int evaluate_data_proc_imm_thumb(uint16_t opcode, case 0: instruction->type = ARM_MOV; mnemonic = "MOVS"; - instruction->info.data_proc.Rn = -1; + instruction->info.data_proc.rn = -1; break; case 1: instruction->type = ARM_CMP; mnemonic = "CMP"; - instruction->info.data_proc.Rd = -1; + instruction->info.data_proc.rd = -1; break; case 2: instruction->type = ARM_ADD; @@ -2242,7 +2242,7 @@ static int evaluate_data_proc_imm_thumb(uint16_t opcode, snprintf(instruction->text, 128, "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, #%#2.2x", - address, opcode, mnemonic, Rd, imm); + address, opcode, mnemonic, rd, imm); return ERROR_OK; } @@ -2250,27 +2250,27 @@ static int evaluate_data_proc_imm_thumb(uint16_t opcode, static int evaluate_data_proc_thumb(uint16_t opcode, uint32_t address, struct arm_instruction *instruction) { - uint8_t high_reg, op, Rm, Rd, H1, H2; + uint8_t high_reg, op, rm, rd, h1, h2; char *mnemonic = NULL; bool nop = false; high_reg = (opcode & 0x0400) >> 10; op = (opcode & 0x03C0) >> 6; - Rd = (opcode & 0x0007); - Rm = (opcode & 0x0038) >> 3; - H1 = (opcode & 0x0080) >> 7; - H2 = (opcode & 0x0040) >> 6; + rd = (opcode & 0x0007); + rm = (opcode & 0x0038) >> 3; + h1 = (opcode & 0x0080) >> 7; + h2 = (opcode & 0x0040) >> 6; - instruction->info.data_proc.Rd = Rd; - instruction->info.data_proc.Rn = Rd; - instruction->info.data_proc.S = (!high_reg || (instruction->type == ARM_CMP)); + instruction->info.data_proc.rd = rd; + instruction->info.data_proc.rn = rd; + instruction->info.data_proc.s = (!high_reg || (instruction->type == ARM_CMP)); instruction->info.data_proc.variant = 1 /*immediate shift*/; - instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm; + instruction->info.data_proc.shifter_operand.immediate_shift.rm = rm; if (high_reg) { - Rd |= H1 << 3; - Rm |= H2 << 3; + rd |= h1 << 3; + rm |= h2 << 3; op >>= 2; switch (op) { @@ -2285,24 +2285,24 @@ static int evaluate_data_proc_thumb(uint16_t opcode, case 0x2: instruction->type = ARM_MOV; mnemonic = "MOV"; - if (Rd == Rm) + if (rd == rm) nop = true; break; case 0x3: if ((opcode & 0x7) == 0x0) { - instruction->info.b_bl_bx_blx.reg_operand = Rm; - if (H1) { + instruction->info.b_bl_bx_blx.reg_operand = rm; + if (h1) { instruction->type = ARM_BLX; snprintf(instruction->text, 128, "0x%8.8" PRIx32 " 0x%4.4x \tBLX\tr%i", - address, opcode, Rm); + address, opcode, rm); } else { instruction->type = ARM_BX; snprintf(instruction->text, 128, "0x%8.8" PRIx32 " 0x%4.4x \tBX\tr%i", - address, opcode, Rm); + address, opcode, rm); } } else { instruction->type = ARM_UNDEFINED_INSTRUCTION; @@ -2329,24 +2329,24 @@ static int evaluate_data_proc_thumb(uint16_t opcode, mnemonic = "LSLS"; instruction->info.data_proc.variant = 2 /*register shift*/; instruction->info.data_proc.shifter_operand.register_shift.shift = 0; - instruction->info.data_proc.shifter_operand.register_shift.Rm = Rd; - instruction->info.data_proc.shifter_operand.register_shift.Rs = Rm; + instruction->info.data_proc.shifter_operand.register_shift.rm = rd; + instruction->info.data_proc.shifter_operand.register_shift.rs = rm; break; case 0x3: instruction->type = ARM_MOV; mnemonic = "LSRS"; instruction->info.data_proc.variant = 2 /*register shift*/; instruction->info.data_proc.shifter_operand.register_shift.shift = 1; - instruction->info.data_proc.shifter_operand.register_shift.Rm = Rd; - instruction->info.data_proc.shifter_operand.register_shift.Rs = Rm; + instruction->info.data_proc.shifter_operand.register_shift.rm = rd; + instruction->info.data_proc.shifter_operand.register_shift.rs = rm; break; case 0x4: instruction->type = ARM_MOV; mnemonic = "ASRS"; instruction->info.data_proc.variant = 2 /*register shift*/; instruction->info.data_proc.shifter_operand.register_shift.shift = 2; - instruction->info.data_proc.shifter_operand.register_shift.Rm = Rd; - instruction->info.data_proc.shifter_operand.register_shift.Rs = Rm; + instruction->info.data_proc.shifter_operand.register_shift.rm = rd; + instru... [truncated message content] |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-20 13:53:31
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This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via c0ea4295df22c8f9b7d17472171f77639e19b61d (commit) via 67cb50e26a685835c0863b35f579fb723973d6bd (commit) from 7c38f24529cd765fc16a317874c46a9b428bb4b7 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit c0ea4295df22c8f9b7d17472171f77639e19b61d Author: Antonio Borneo <bor...@gm...> Date: Sun Jun 6 17:20:30 2021 +0200 target/cortex_m: rename CamelCase symbol Change-Id: I67d803e15ba9fd08f2b31361fb3604275e483605 Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6339 Tested-by: jenkins Reviewed-by: Marc Schink <de...@za...> Reviewed-by: Xiang W <wx...@12...> diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c index 7b1932b9f..5d7ab6af3 100644 --- a/src/jtag/drivers/stlink_usb.c +++ b/src/jtag/drivers/stlink_usb.c @@ -2286,7 +2286,7 @@ static int stlink_usb_write_reg(void *handle, unsigned int regsel, uint32_t val) if (res != ERROR_OK) return res; - return stlink_usb_write_debug_reg(h, DCB_DCRSR, DCRSR_WnR | (regsel & 0x7f)); + return stlink_usb_write_debug_reg(h, DCB_DCRSR, DCRSR_WNR | (regsel & 0x7f)); /* FIXME: poll DHCSR.S_REGRDY after write DCRSR */ } diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index c30556c8a..bd68fe868 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -169,7 +169,7 @@ static int cortex_m_store_core_reg_u32(struct target *target, if (retval != ERROR_OK) return retval; - retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regsel | DCRSR_WnR); + retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regsel | DCRSR_WNR); if (retval != ERROR_OK) return retval; diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h index 453305483..16fc8ab70 100644 --- a/src/target/cortex_m.h +++ b/src/target/cortex_m.h @@ -77,7 +77,7 @@ struct cortex_m_part_info { #define DCB_DEMCR 0xE000EDFC #define DCB_DSCSR 0xE000EE08 -#define DCRSR_WnR BIT(16) +#define DCRSR_WNR BIT(16) #define DWT_CTRL 0xE0001000 #define DWT_CYCCNT 0xE0001004 commit 67cb50e26a685835c0863b35f579fb723973d6bd Author: Antonio Borneo <bor...@gm...> Date: Tue Apr 27 15:58:26 2021 +0200 target/arm: rename CamelCase symbols No major cross dependencies, mostly changes internal to each file/function. Change-Id: I3f0879f0f33c6badc36a0dc60229323978a7e280 Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6338 Tested-by: jenkins Reviewed-by: Oleksij Rempel <li...@re...> Reviewed-by: Xiang W <wx...@12...> diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 7853ca3ff..87c6bceb7 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -1259,18 +1259,18 @@ static int aarch64_set_breakpoint(struct target *target, bpt_value = brp_list[brp_i].value; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn, + + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn, (uint32_t)(bpt_value & 0xFFFFFFFF)); if (retval != ERROR_OK) return retval; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn, + + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn, (uint32_t)(bpt_value >> 32)); if (retval != ERROR_OK) return retval; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn, + + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn, brp_list[brp_i].control); if (retval != ERROR_OK) return retval; @@ -1377,12 +1377,12 @@ static int aarch64_set_context_breakpoint(struct target *target, brp_list[brp_i].value = (breakpoint->asid); brp_list[brp_i].control = control; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn, + + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn, brp_list[brp_i].value); if (retval != ERROR_OK) return retval; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn, + + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn, brp_list[brp_i].control); if (retval != ERROR_OK) return retval; @@ -1398,11 +1398,11 @@ static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoin int retval = ERROR_FAIL; int brp_1 = 0; /* holds the contextID pair */ int brp_2 = 0; /* holds the IVA pair */ - uint32_t control_CTX, control_IVA; - uint8_t CTX_byte_addr_select = 0x0F; - uint8_t IVA_byte_addr_select = 0x0F; - uint8_t CTX_machmode = 0x03; - uint8_t IVA_machmode = 0x01; + uint32_t control_ctx, control_iva; + uint8_t ctx_byte_addr_select = 0x0F; + uint8_t iva_byte_addr_select = 0x0F; + uint8_t ctx_machmode = 0x03; + uint8_t iva_machmode = 0x01; struct aarch64_common *aarch64 = target_to_aarch64(target); struct armv8_common *armv8 = &aarch64->armv8_common; struct aarch64_brp *brp_list = aarch64->brp_list; @@ -1434,45 +1434,45 @@ static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoin breakpoint->set = brp_1 + 1; breakpoint->linked_brp = brp_2; - control_CTX = ((CTX_machmode & 0x7) << 20) + control_ctx = ((ctx_machmode & 0x7) << 20) | (brp_2 << 16) | (0 << 14) - | (CTX_byte_addr_select << 5) + | (ctx_byte_addr_select << 5) | (3 << 1) | 1; brp_list[brp_1].used = 1; brp_list[brp_1].value = (breakpoint->asid); - brp_list[brp_1].control = control_CTX; + brp_list[brp_1].control = control_ctx; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_1].BRPn, + + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_1].brpn, brp_list[brp_1].value); if (retval != ERROR_OK) return retval; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_1].BRPn, + + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_1].brpn, brp_list[brp_1].control); if (retval != ERROR_OK) return retval; - control_IVA = ((IVA_machmode & 0x7) << 20) + control_iva = ((iva_machmode & 0x7) << 20) | (brp_1 << 16) | (1 << 13) - | (IVA_byte_addr_select << 5) + | (iva_byte_addr_select << 5) | (3 << 1) | 1; brp_list[brp_2].used = 1; brp_list[brp_2].value = breakpoint->address & 0xFFFFFFFFFFFFFFFC; - brp_list[brp_2].control = control_IVA; + brp_list[brp_2].control = control_iva; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_2].BRPn, + + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_2].brpn, brp_list[brp_2].value & 0xFFFFFFFF); if (retval != ERROR_OK) return retval; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_2].BRPn, + + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_2].brpn, brp_list[brp_2].value >> 32); if (retval != ERROR_OK) return retval; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_2].BRPn, + + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_2].brpn, brp_list[brp_2].control); if (retval != ERROR_OK) return retval; @@ -1506,17 +1506,17 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br brp_list[brp_i].value = 0; brp_list[brp_i].control = 0; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn, + + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn, brp_list[brp_i].control); if (retval != ERROR_OK) return retval; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn, + + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn, (uint32_t)brp_list[brp_i].value); if (retval != ERROR_OK) return retval; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn, + + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn, (uint32_t)brp_list[brp_i].value); if (retval != ERROR_OK) return retval; @@ -1530,17 +1530,17 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br brp_list[brp_j].value = 0; brp_list[brp_j].control = 0; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_j].BRPn, + + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_j].brpn, brp_list[brp_j].control); if (retval != ERROR_OK) return retval; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_j].BRPn, + + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_j].brpn, (uint32_t)brp_list[brp_j].value); if (retval != ERROR_OK) return retval; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_j].BRPn, + + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_j].brpn, (uint32_t)brp_list[brp_j].value); if (retval != ERROR_OK) return retval; @@ -1561,18 +1561,18 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br brp_list[brp_i].value = 0; brp_list[brp_i].control = 0; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn, + + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn, brp_list[brp_i].control); if (retval != ERROR_OK) return retval; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn, + + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn, brp_list[brp_i].value); if (retval != ERROR_OK) return retval; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn, + + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn, (uint32_t)brp_list[brp_i].value); if (retval != ERROR_OK) return retval; @@ -1735,18 +1735,18 @@ static int aarch64_set_watchpoint(struct target *target, wp_list[wp_i].control = control; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].BRPn, + + CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].brpn, (uint32_t)(wp_list[wp_i].value & 0xFFFFFFFF)); if (retval != ERROR_OK) return retval; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].BRPn, + + CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].brpn, (uint32_t)(wp_list[wp_i].value >> 32)); if (retval != ERROR_OK) return retval; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].BRPn, + + CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].brpn, control); if (retval != ERROR_OK) return retval; @@ -1791,18 +1791,18 @@ static int aarch64_unset_watchpoint(struct target *target, wp_list[wp_i].value = 0; wp_list[wp_i].control = 0; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].BRPn, + + CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].brpn, wp_list[wp_i].control); if (retval != ERROR_OK) return retval; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].BRPn, + + CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].brpn, wp_list[wp_i].value); if (retval != ERROR_OK) return retval; retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base - + CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].BRPn, + + CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].brpn, (uint32_t)wp_list[wp_i].value); if (retval != ERROR_OK) return retval; @@ -2656,7 +2656,7 @@ static int aarch64_examine_first(struct target *target) aarch64->brp_list[i].type = BRP_CONTEXT; aarch64->brp_list[i].value = 0; aarch64->brp_list[i].control = 0; - aarch64->brp_list[i].BRPn = i; + aarch64->brp_list[i].brpn = i; } /* Setup Watchpoint Register Pairs */ @@ -2668,7 +2668,7 @@ static int aarch64_examine_first(struct target *target) aarch64->wp_list[i].type = BRP_NORMAL; aarch64->wp_list[i].value = 0; aarch64->wp_list[i].control = 0; - aarch64->wp_list[i].BRPn = i; + aarch64->wp_list[i].brpn = i; } LOG_DEBUG("Configured %i hw breakpoints, %i watchpoints", @@ -3005,8 +3005,8 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv) int cpnum; uint32_t op1; uint32_t op2; - uint32_t CRn; - uint32_t CRm; + uint32_t crn; + uint32_t crm; uint32_t value; long l; @@ -3043,7 +3043,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv) "CRn", (int) l); return JIM_ERR; } - CRn = l; + crn = l; retval = Jim_GetLong(interp, argv[4], &l); if (retval != JIM_OK) @@ -3053,7 +3053,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv) "CRm", (int) l); return JIM_ERR; } - CRm = l; + crm = l; retval = Jim_GetLong(interp, argv[5], &l); if (retval != JIM_OK) @@ -3074,14 +3074,14 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv) value = l; /* NOTE: parameters reordered! */ - /* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */ - retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value); + /* ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2) */ + retval = arm->mcr(target, cpnum, op1, op2, crn, crm, value); if (retval != ERROR_OK) return JIM_ERR; } else { /* NOTE: parameters reordered! */ - /* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */ - retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value); + /* ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2) */ + retval = arm->mrc(target, cpnum, op1, op2, crn, crm, &value); if (retval != ERROR_OK) return JIM_ERR; diff --git a/src/target/aarch64.h b/src/target/aarch64.h index 7c0ddf868..b57361f88 100644 --- a/src/target/aarch64.h +++ b/src/target/aarch64.h @@ -46,7 +46,7 @@ struct aarch64_brp { int type; target_addr_t value; uint32_t control; - uint8_t BRPn; + uint8_t brpn; }; struct aarch64_common { diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c index 239253d20..29bc04f6d 100644 --- a/src/target/adi_v5_jtag.c +++ b/src/target/adi_v5_jtag.c @@ -128,7 +128,7 @@ struct dap_cmd { struct list_head lh; uint8_t instr; uint8_t reg_addr; - uint8_t RnW; + uint8_t rnw; uint8_t *invalue; uint8_t ack; uint32_t memaccess_tck; @@ -153,7 +153,7 @@ static void log_dap_cmd(const char *header, struct dap_cmd *el) LOG_DEBUG("%s: %2s %6s %5s 0x%08x 0x%08x %2s", header, el->instr == JTAG_DP_APACC ? "AP" : "DP", dap_reg_name(el->instr, el->reg_addr), - el->RnW == DPAP_READ ? "READ" : "WRITE", + el->rnw == DPAP_READ ? "READ" : "WRITE", buf_get_u32(el->outvalue_buf, 0, 32), buf_get_u32(el->invalue, 0, 32), el->ack == JTAG_ACK_OK_FAULT ? "OK" : @@ -170,7 +170,7 @@ static int jtag_limit_queue_size(struct adiv5_dap *dap) } static struct dap_cmd *dap_cmd_new(struct adiv5_dap *dap, uint8_t instr, - uint8_t reg_addr, uint8_t RnW, + uint8_t reg_addr, uint8_t rnw, uint8_t *outvalue, uint8_t *invalue, uint32_t memaccess_tck) { @@ -193,7 +193,7 @@ static struct dap_cmd *dap_cmd_new(struct adiv5_dap *dap, uint8_t instr, INIT_LIST_HEAD(&cmd->lh); cmd->instr = instr; cmd->reg_addr = reg_addr; - cmd->RnW = RnW; + cmd->rnw = rnw; if (outvalue != NULL) memcpy(cmd->outvalue_buf, outvalue, 4); cmd->invalue = (invalue != NULL) ? invalue : cmd->invalue_buf; @@ -253,7 +253,7 @@ static int adi_jtag_dp_scan_cmd(struct adiv5_dap *dap, struct dap_cmd *cmd, uint * For APACC access with any sticky error flag set, this is discarded. */ cmd->fields[0].num_bits = 3; - buf_set_u32(&cmd->out_addr_buf, 0, 3, ((cmd->reg_addr >> 1) & 0x6) | (cmd->RnW & 0x1)); + buf_set_u32(&cmd->out_addr_buf, 0, 3, ((cmd->reg_addr >> 1) & 0x6) | (cmd->rnw & 0x1)); cmd->fields[0].out_value = &cmd->out_addr_buf; cmd->fields[0].in_value = (ack != NULL) ? ack : &cmd->ack; @@ -299,7 +299,7 @@ static int adi_jtag_dp_scan_cmd_sync(struct adiv5_dap *dap, struct dap_cmd *cmd, * conversions are performed. See section 4.4.3 of the ADIv5 spec, which * discusses operations which access these registers. * - * Note that only one scan is performed. If RnW is set, a separate scan + * Note that only one scan is performed. If rnw is set, a separate scan * will be needed to collect the data which was read; the "invalue" collects * the posted result of a preceding operation, not the current one. * @@ -307,7 +307,7 @@ static int adi_jtag_dp_scan_cmd_sync(struct adiv5_dap *dap, struct dap_cmd *cmd, * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access) * @param reg_addr two significant bits; A[3:2]; for APACC access, the * SELECT register has more addressing bits. - * @param RnW false iff outvalue will be written to the DP or AP + * @param rnw false iff outvalue will be written to the DP or AP * @param outvalue points to a 32-bit (little-endian) integer * @param invalue NULL, or points to a 32-bit (little-endian) integer * @param ack points to where the three bit JTAG_ACK_* code will be stored @@ -315,14 +315,14 @@ static int adi_jtag_dp_scan_cmd_sync(struct adiv5_dap *dap, struct dap_cmd *cmd, */ static int adi_jtag_dp_scan(struct adiv5_dap *dap, - uint8_t instr, uint8_t reg_addr, uint8_t RnW, + uint8_t instr, uint8_t reg_addr, uint8_t rnw, uint8_t *outvalue, uint8_t *invalue, uint32_t memaccess_tck, uint8_t *ack) { struct dap_cmd *cmd; int retval; - cmd = dap_cmd_new(dap, instr, reg_addr, RnW, outvalue, invalue, memaccess_tck); + cmd = dap_cmd_new(dap, instr, reg_addr, rnw, outvalue, invalue, memaccess_tck); if (cmd != NULL) cmd->dp_select = dap->select; else @@ -342,7 +342,7 @@ static int adi_jtag_dp_scan(struct adiv5_dap *dap, * must be different). */ static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap, - uint8_t instr, uint8_t reg_addr, uint8_t RnW, + uint8_t instr, uint8_t reg_addr, uint8_t rnw, uint32_t outvalue, uint32_t *invalue, uint32_t memaccess_tck, uint8_t *ack) { @@ -351,7 +351,7 @@ static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap, buf_set_u32(out_value_buf, 0, 32, outvalue); - retval = adi_jtag_dp_scan(dap, instr, reg_addr, RnW, + retval = adi_jtag_dp_scan(dap, instr, reg_addr, rnw, out_value_buf, (uint8_t *)invalue, memaccess_tck, ack); if (retval != ERROR_OK) return retval; @@ -377,21 +377,21 @@ static int adi_jtag_finish_read(struct adiv5_dap *dap) } static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap, - uint8_t instr, uint8_t reg_addr, uint8_t RnW, + uint8_t instr, uint8_t reg_addr, uint8_t rnw, uint32_t outvalue, uint32_t *invalue, uint32_t memaccess_tck) { int retval; /* Issue the read or write */ retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr, - RnW, outvalue, NULL, memaccess_tck, NULL); + rnw, outvalue, NULL, memaccess_tck, NULL); if (retval != ERROR_OK) return retval; /* For reads, collect posted value; RDBUFF has no other effect. * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK". */ - if ((RnW == DPAP_READ) && (invalue != NULL)) { + if ((rnw == DPAP_READ) && (invalue != NULL)) { retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, 0, NULL); if (retval != ERROR_OK) @@ -435,7 +435,7 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap) */ if (found_wait && el != list_first_entry(&dap->cmd_journal, struct dap_cmd, lh)) { prev = list_entry(el->lh.prev, struct dap_cmd, lh); - if (prev->RnW == DPAP_READ) { + if (prev->rnw == DPAP_READ) { log_dap_cmd("PND", prev); /* search for the next OK transaction, it contains * the result of the previous READ */ diff --git a/src/target/arm.h b/src/target/arm.h index f403b8f8a..2f3573415 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -231,13 +231,13 @@ struct arm { /** Read coprocessor register. */ int (*mrc)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, + uint32_t crn, uint32_t crm, uint32_t *value); /** Write coprocessor register. */ int (*mcr)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, + uint32_t crn, uint32_t crm, uint32_t value); void *arch_info; diff --git a/src/target/arm11.c b/src/target/arm11.c index ff125d0ea..81409cbe8 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -51,14 +51,14 @@ static int arm11_step(struct target *target, int current, */ static int arm11_check_init(struct arm11_common *arm11) { - CHECK_RETVAL(arm11_read_DSCR(arm11)); + CHECK_RETVAL(arm11_read_dscr(arm11)); if (!(arm11->dscr & DSCR_HALT_DBG_MODE)) { LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr); LOG_DEBUG("Bringing target into debug mode"); arm11->dscr |= DSCR_HALT_DBG_MODE; - CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr)); + CHECK_RETVAL(arm11_write_dscr(arm11, arm11->dscr)); /* add further reset initialization here */ @@ -104,9 +104,9 @@ static int arm11_debug_entry(struct arm11_common *arm11) /* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */ arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL); if (arm11->is_wdtr_saved) { - arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); + arm11_add_debug_scan_n(arm11, 0x05, ARM11_TAP_DEFAULT); - arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); struct scan_field chain5_fields[3]; @@ -126,7 +126,7 @@ static int arm11_debug_entry(struct arm11_common *arm11) * but not to issue ITRs(?). The ARMv7 arch spec says it's required * for executing instructions via ITR. */ - CHECK_RETVAL(arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr)); + CHECK_RETVAL(arm11_write_dscr(arm11, DSCR_ITR_EN | arm11->dscr)); /* From the spec: @@ -143,14 +143,14 @@ static int arm11_debug_entry(struct arm11_common *arm11) /* mcr 15, 0, r0, cr7, cr10, {4} */ arm11_run_instr_no_data1(arm11, 0xee070f9a); - uint32_t dscr = arm11_read_DSCR(arm11); + uint32_t dscr = arm11_read_dscr(arm11); LOG_DEBUG("DRAIN, DSCR %08x", dscr); if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT) { arm11_run_instr_no_data1(arm11, 0xe320f000); - dscr = arm11_read_DSCR(arm11); + dscr = arm11_read_dscr(arm11); LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr); @@ -242,7 +242,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp) /* spec says clear wDTR and rDTR; we assume they are clear as otherwise our programming would be sloppy */ { - CHECK_RETVAL(arm11_read_DSCR(arm11)); + CHECK_RETVAL(arm11_read_dscr(arm11)); if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL)) { /* @@ -285,23 +285,23 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp) register_cache_invalidate(arm11->arm.core_cache); /* restore DSCR */ - CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr)); + CHECK_RETVAL(arm11_write_dscr(arm11, arm11->dscr)); /* maybe restore rDTR */ if (arm11->is_rdtr_saved) { - arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); + arm11_add_debug_scan_n(arm11, 0x05, ARM11_TAP_DEFAULT); - arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); struct scan_field chain5_fields[3]; - uint8_t Ready = 0; /* ignored */ - uint8_t Valid = 0; /* ignored */ + uint8_t ready = 0; /* ignored */ + uint8_t valid = 0; /* ignored */ arm11_setup_field(arm11, 32, &arm11->saved_rdtr, NULL, chain5_fields + 0); - arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1); - arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2); + arm11_setup_field(arm11, 1, &ready, NULL, chain5_fields + 1); + arm11_setup_field(arm11, 1, &valid, NULL, chain5_fields + 2); arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE( chain5_fields), chain5_fields, TAP_DRPAUSE); @@ -376,14 +376,14 @@ static int arm11_halt(struct target *target) return ERROR_OK; } - arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE); + arm11_add_ir(arm11, ARM11_HALT, TAP_IDLE); CHECK_RETVAL(jtag_execute_queue()); int i = 0; while (1) { - CHECK_RETVAL(arm11_read_DSCR(arm11)); + CHECK_RETVAL(arm11_read_dscr(arm11)); if (arm11->dscr & DSCR_CORE_HALTED) break; @@ -519,13 +519,13 @@ static int arm11_resume(struct target *target, int current, /* activate all watchpoints and breakpoints */ CHECK_RETVAL(arm11_leave_debug_state(arm11, true)); - arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE); + arm11_add_ir(arm11, ARM11_RESTART, TAP_IDLE); CHECK_RETVAL(jtag_execute_queue()); int i = 0; while (1) { - CHECK_RETVAL(arm11_read_DSCR(arm11)); + CHECK_RETVAL(arm11_read_dscr(arm11)); LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr); @@ -661,7 +661,7 @@ static int arm11_step(struct target *target, int current, CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints)); - arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE); + arm11_add_ir(arm11, ARM11_RESTART, TAP_IDLE); CHECK_RETVAL(jtag_execute_queue()); @@ -672,7 +672,7 @@ static int arm11_step(struct target *target, int current, const uint32_t mask = DSCR_CORE_RESTARTED | DSCR_CORE_HALTED; - CHECK_RETVAL(arm11_read_DSCR(arm11)); + CHECK_RETVAL(arm11_read_dscr(arm11)); LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr); if ((arm11->dscr & mask) == mask) @@ -1151,7 +1151,7 @@ static int arm11_examine(struct target *target) /* check IDCODE */ - arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT); struct scan_field idcode_field; @@ -1161,9 +1161,9 @@ static int arm11_examine(struct target *target) /* check DIDR */ - arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT); + arm11_add_debug_scan_n(arm11, 0x00, ARM11_TAP_DEFAULT); - arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); struct scan_field chain0_fields[2]; diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 823ce5cc1..0200647c1 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -132,7 +132,7 @@ static const char *arm11_ir_to_string(uint8_t ir) * * \remarks This adds to the JTAG command queue but does \em not execute it. */ -void arm11_add_IR(struct arm11_common *arm11, uint8_t instr, tap_state_t state) +void arm11_add_ir(struct arm11_common *arm11, uint8_t instr, tap_state_t state) { struct jtag_tap *tap = arm11->arm.target->tap; @@ -153,7 +153,7 @@ void arm11_add_IR(struct arm11_common *arm11, uint8_t instr, tap_state_t state) } /** Verify data shifted out from Scan Chain Register (SCREG). */ -static void arm11_in_handler_SCAN_N(uint8_t *in_value) +static void arm11_in_handler_scan_n(uint8_t *in_value) { /* Don't expect JTAG layer to modify bits we didn't ask it to read */ uint8_t v = *in_value & 0x1F; @@ -186,12 +186,12 @@ static void arm11_in_handler_SCAN_N(uint8_t *in_value) * call will end in Pause-DR. The second call, due to the IR * caching, will not go through Capture-DR when shifting in the * new scan chain number. As a result the verification in - * arm11_in_handler_SCAN_N() must fail. + * arm11_in_handler_scan_n() must fail. * * \remarks This adds to the JTAG command queue but does \em not execute it. */ -int arm11_add_debug_SCAN_N(struct arm11_common *arm11, +int arm11_add_debug_scan_n(struct arm11_common *arm11, uint8_t chain, tap_state_t state) { /* Don't needlessly switch the scan chain. @@ -211,7 +211,7 @@ int arm11_add_debug_SCAN_N(struct arm11_common *arm11, #endif JTAG_DEBUG("SCREG <= %d", chain); - arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT); struct scan_field field; @@ -225,7 +225,7 @@ int arm11_add_debug_SCAN_N(struct arm11_common *arm11, jtag_execute_queue_noclear(); - arm11_in_handler_SCAN_N(tmp); + arm11_in_handler_scan_n(tmp); arm11->jtag_info.cur_scan_chain = chain; @@ -250,7 +250,7 @@ int arm11_add_debug_SCAN_N(struct arm11_common *arm11, * is properly set up. Depending on the instruction, you may also need * to ensure that the rDTR is ready before that Run-Test/Idle state. */ -static void arm11_add_debug_INST(struct arm11_common *arm11, +static void arm11_add_debug_inst(struct arm11_common *arm11, uint32_t inst, uint8_t *flag, tap_state_t state) { JTAG_DEBUG("INST <= 0x%08x", (unsigned) inst); @@ -273,15 +273,15 @@ static void arm11_add_debug_INST(struct arm11_common *arm11, * command queue. It does not require the ARM11 debug TAP to be * in any particular state. */ -int arm11_read_DSCR(struct arm11_common *arm11) +int arm11_read_dscr(struct arm11_common *arm11) { int retval; - retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); + retval = arm11_add_debug_scan_n(arm11, 0x01, ARM11_TAP_DEFAULT); if (retval != ERROR_OK) return retval; - arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); uint32_t dscr; struct scan_field chain1_field; @@ -311,14 +311,14 @@ int arm11_read_DSCR(struct arm11_common *arm11) * * \remarks This is a stand-alone function that executes the JTAG command queue. */ -int arm11_write_DSCR(struct arm11_common *arm11, uint32_t dscr) +int arm11_write_dscr(struct arm11_common *arm11, uint32_t dscr) { int retval; - retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); + retval = arm11_add_debug_scan_n(arm11, 0x01, ARM11_TAP_DEFAULT); if (retval != ERROR_OK) return retval; - arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); struct scan_field chain1_field; @@ -353,7 +353,7 @@ int arm11_write_DSCR(struct arm11_common *arm11, uint32_t dscr) */ int arm11_run_instr_data_prepare(struct arm11_common *arm11) { - return arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); + return arm11_add_debug_scan_n(arm11, 0x05, ARM11_TAP_DEFAULT); } /** Cleanup after ITR/DTR operations @@ -372,7 +372,7 @@ int arm11_run_instr_data_prepare(struct arm11_common *arm11) */ int arm11_run_instr_data_finish(struct arm11_common *arm11) { - return arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT); + return arm11_add_debug_scan_n(arm11, 0x00, ARM11_TAP_DEFAULT); } /** @@ -392,16 +392,16 @@ static int arm11_run_instr_no_data(struct arm11_common *arm11, uint32_t *opcode, size_t count) { - arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); while (count--) { - arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE); + arm11_add_debug_inst(arm11, *opcode++, NULL, TAP_IDLE); int i = 0; while (1) { uint8_t flag; - arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE); + arm11_add_debug_inst(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE); CHECK_RETVAL(jtag_execute_queue()); @@ -463,33 +463,33 @@ int arm11_run_instr_data_to_core(struct arm11_common *arm11, uint32_t *data, size_t count) { - arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); - arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE); + arm11_add_debug_inst(arm11, opcode, NULL, TAP_DRPAUSE); - arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); struct scan_field chain5_fields[3]; - uint32_t Data; - uint8_t Ready; - uint8_t nRetry; + uint32_t _data; + uint8_t ready; + uint8_t n_retry; - arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0); - arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1); - arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2); + arm11_setup_field(arm11, 32, &_data, NULL, chain5_fields + 0); + arm11_setup_field(arm11, 1, NULL, &ready, chain5_fields + 1); + arm11_setup_field(arm11, 1, NULL, &n_retry, chain5_fields + 2); while (count--) { int i = 0; do { - Data = *data; + _data = *data; arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE( chain5_fields), chain5_fields, TAP_IDLE); CHECK_RETVAL(jtag_execute_queue()); - JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry); + JTAG_DEBUG("DTR ready %d n_retry %d", ready, n_retry); int64_t then = 0; @@ -504,24 +504,24 @@ int arm11_run_instr_data_to_core(struct arm11_common *arm11, } i++; - } while (!Ready); + } while (!ready); data++; } - arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); int i = 0; do { - Data = 0; + _data = 0; arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE( chain5_fields), chain5_fields, TAP_DRPAUSE); CHECK_RETVAL(jtag_execute_queue()); - JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", - (unsigned) Data, Ready, nRetry); + JTAG_DEBUG("DTR _data %08x ready %d n_retry %d", + (unsigned) _data, ready, n_retry); int64_t then = 0; @@ -535,7 +535,7 @@ int arm11_run_instr_data_to_core(struct arm11_common *arm11, } i++; - } while (!Ready); + } while (!ready); return ERROR_OK; } @@ -557,7 +557,7 @@ int arm11_run_instr_data_to_core(struct arm11_common *arm11, * https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html * https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html */ -static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = { +static const tap_state_t arm11_move_drpause_idle_drpause_with_delay[] = { TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT }; @@ -581,26 +581,26 @@ static int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap, chain5_fields[2].out_value = NULL; chain5_fields[2].in_value = NULL; - uint8_t *Readies; - unsigned readiesNum = count; - unsigned bytes = sizeof(*Readies)*readiesNum; + uint8_t *readies; + unsigned readies_num = count; + unsigned bytes = sizeof(*readies)*readies_num; - Readies = malloc(bytes); - if (Readies == NULL) { + readies = malloc(bytes); + if (readies == NULL) { LOG_ERROR("Out of memory allocating %u bytes", bytes); return ERROR_FAIL; } - uint8_t *ReadyPos = Readies; + uint8_t *ready_pos = readies; while (count--) { chain5_fields[0].out_value = (uint8_t *)(data++); - chain5_fields[1].in_value = ReadyPos++; + chain5_fields[1].in_value = ready_pos++; if (count > 0) { jtag_add_dr_scan(tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); - jtag_add_pathmove(ARRAY_SIZE(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay), - arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay); + jtag_add_pathmove(ARRAY_SIZE(arm11_move_drpause_idle_drpause_with_delay), + arm11_move_drpause_idle_drpause_with_delay); } else jtag_add_dr_scan(tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_IDLE); } @@ -609,18 +609,18 @@ static int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap, if (retval == ERROR_OK) { unsigned error_count = 0; - for (size_t i = 0; i < readiesNum; i++) { - if (Readies[i] != 1) + for (size_t i = 0; i < readies_num; i++) { + if (readies[i] != 1) error_count++; } if (error_count > 0) { LOG_ERROR("%u words out of %u not transferred", - error_count, readiesNum); + error_count, readies_num); retval = ERROR_FAIL; } } - free(Readies); + free(readies); return retval; } @@ -649,11 +649,11 @@ int arm11_run_instr_data_to_core_noack(struct arm11_common *arm11, uint32_t *data, size_t count) { - arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); - arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE); + arm11_add_debug_inst(arm11, opcode, NULL, TAP_DRPAUSE); - arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); int retval = arm11_run_instr_data_to_core_noack_inner(arm11->arm.target->tap, opcode, @@ -663,7 +663,7 @@ int arm11_run_instr_data_to_core_noack(struct arm11_common *arm11, if (retval != ERROR_OK) return retval; - arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); struct scan_field chain5_fields[3]; @@ -740,21 +740,21 @@ int arm11_run_instr_data_from_core(struct arm11_common *arm11, uint32_t *data, size_t count) { - arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); - arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE); + arm11_add_debug_inst(arm11, opcode, NULL, TAP_IDLE); - arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); struct scan_field chain5_fields[3]; - uint32_t Data; - uint8_t Ready; - uint8_t nRetry; + uint32_t _data; + uint8_t ready; + uint8_t n_retry; - arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0); - arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1); - arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2); + arm11_setup_field(arm11, 32, NULL, &_data, chain5_fields + 0); + arm11_setup_field(arm11, 1, NULL, &ready, chain5_fields + 1); + arm11_setup_field(arm11, 1, NULL, &n_retry, chain5_fields + 2); while (count--) { int i = 0; @@ -765,8 +765,8 @@ int arm11_run_instr_data_from_core(struct arm11_common *arm11, CHECK_RETVAL(jtag_execute_queue()); - JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", - (unsigned) Data, Ready, nRetry); + JTAG_DEBUG("DTR _data %08x ready %d n_retry %d", + (unsigned) _data, ready, n_retry); int64_t then = 0; @@ -781,9 +781,9 @@ int arm11_run_instr_data_from_core(struct arm11_common *arm11, } i++; - } while (!Ready); + } while (!ready); - *data++ = Data; + *data++ = _data; } return ERROR_OK; @@ -856,51 +856,51 @@ int arm11_sc7_run(struct arm11_common *arm11, struct arm11_sc7_action *actions, { int retval; - retval = arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT); + retval = arm11_add_debug_scan_n(arm11, 0x07, ARM11_TAP_DEFAULT); if (retval != ERROR_OK) return retval; - arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); + arm11_add_ir(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); struct scan_field chain7_fields[3]; - uint8_t nRW; - uint32_t DataOut; - uint8_t AddressOut; - uint8_t Ready; - uint32_t DataIn; - uint8_t AddressIn; + uint8_t n_rw; + uint32_t data_out; + uint8_t address_out; + uint8_t ready; + uint32_t data_in; + uint8_t address_in; - arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0); - arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1); - arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2); + arm11_setup_field(arm11, 1, &n_rw, &ready, chain7_fields + 0); + arm11_setup_field(arm11, 32, &data_out, &data_in, chain7_fields + 1); + arm11_setup_field(arm11, 7, &address_out, &address_in, chain7_fields + 2); for (size_t i = 0; i < count + 1; i++) { if (i < count) { - nRW = actions[i].write ? 1 : 0; - DataOut = actions[i].value; - AddressOut = actions[i].address; + n_rw = actions[i].write ? 1 : 0; + data_out = actions[i].value; + address_out = actions[i].address; } else { - nRW = 1; - DataOut = 0; - AddressOut = 0; + n_rw = 1; + data_out = 0; + address_out = 0; } /* Timeout here so we don't get stuck. */ int i_n = 0; while (1) { JTAG_DEBUG("SC7 <= c%-3d Data %08x %s", - (unsigned) AddressOut, - (unsigned) DataOut, - nRW ? "write" : "read"); + (unsigned) address_out, + (unsigned) data_out, + n_rw ? "write" : "read"); arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain7_fields), chain7_fields, TAP_DRPAUSE); CHECK_RETVAL(jtag_execute_queue()); - /* 'nRW' is 'Ready' on read out */ - if (Ready) + /* 'n_rw' is 'ready' on read out */ + if (ready) break; int64_t then = 0; @@ -918,17 +918,17 @@ int arm11_sc7_run(struct arm11_common *arm11, struct arm11_sc7_action *actions, i_n++; } - if (!nRW) - JTAG_DEBUG("SC7 => Data %08x", (unsigned) DataIn); + if (!n_rw) + JTAG_DEBUG("SC7 => Data %08x", (unsigned) data_in); if (i > 0) { - if (actions[i - 1].address != AddressIn) + if (actions[i - 1].address != address_in) LOG_WARNING("Scan chain 7 shifted out unexpected address"); if (!actions[i - 1].write) - actions[i - 1].value = DataIn; + actions[i - 1].value = data_in; else { - if (actions[i - 1].value != DataIn) + if (actions[i - 1].value != data_in) LOG_WARNING("Scan chain 7 shifted out unexpected data"); } } diff --git a/src/target/arm11_dbgtap.h b/src/target/arm11_dbgtap.h index be0248411..c6b20a895 100644 --- a/src/target/arm11_dbgtap.h +++ b/src/target/arm11_dbgtap.h @@ -27,12 +27,12 @@ void arm11_setup_field(struct arm11_common *arm11, int num_bits, void *in_data, void *out_data, struct scan_field *field); -void arm11_add_IR(struct arm11_common *arm11, +void arm11_add_ir(struct arm11_common *arm11, uint8_t instr, tap_state_t state); -int arm11_add_debug_SCAN_N(struct arm11_common *arm11, +int arm11_add_debug_scan_n(struct arm11_common *arm11, uint8_t chain, tap_state_t state); -int arm11_read_DSCR(struct arm11_common *arm11); -int arm11_write_DSCR(struct arm11_common *arm11, uint32_t dscr); +int arm11_read_dscr(struct arm11_common *arm11); +int arm11_write_dscr(struct arm11_common *arm11, uint32_t dscr); int arm11_run_instr_data_prepare(struct arm11_common *arm11); int arm11_run_instr_data_finish(struct arm11_common *arm11); diff --git a/src/target/arm720t.c b/src/target/arm720t.c index bff20a334..db75011cb 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -389,11 +389,11 @@ static void arm720t_deinit_target(struct target *target) /* FIXME remove forward decls */ static int arm720t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, + uint32_t crn, uint32_t crm, uint32_t *value); static int arm720t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, + uint32_t crn, uint32_t crm, uint32_t value); static int arm720t_init_arch_info(struct target *target, @@ -433,7 +433,7 @@ static int arm720t_target_create(struct target *target, Jim_Interp *interp) static int arm720t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, + uint32_t crn, uint32_t crm, uint32_t *value) { if (cpnum != 15) { @@ -443,14 +443,14 @@ static int arm720t_mrc(struct target *target, int cpnum, /* read "to" r0 */ return arm720t_read_cp15(target, - ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2), + ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2), value); } static int arm720t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, + uint32_t crn, uint32_t crm, uint32_t value) { if (cpnum != 15) { @@ -460,7 +460,7 @@ static int arm720t_mcr(struct target *target, int cpnum, /* write "from" r0 */ return arm720t_write_cp15(target, - ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2), + ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2), value); } diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 797f61c93..36ca5b930 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -141,13 +141,13 @@ static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); } else if (arm7_9->sw_breakpoints_added == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE); } else { LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1"); @@ -210,13 +210,13 @@ static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *break embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); } else if (breakpoint->set == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE); } else { LOG_ERROR("BUG: no hardware comparator available"); @@ -484,9 +484,9 @@ static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watch embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], - 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); + 0xff & ~EICE_W_CTRL_NOPC & ~rw_mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], - EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); + EICE_W_CTRL_ENABLE | EICE_W_CTRL_NOPC | (watchpoint->rw & 1)); retval = jtag_execute_queue(); if (retval != ERROR_OK) @@ -503,9 +503,9 @@ static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watch embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], - 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); + 0xff & ~EICE_W_CTRL_NOPC & ~rw_mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], - EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); + EICE_W_CTRL_ENABLE | EICE_W_CTRL_NOPC | (watchpoint->rw & 1)); retval = jtag_execute_queue(); if (retval != ERROR_OK) @@ -933,7 +933,7 @@ int arm7_9_assert_reset(struct target *target) embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff); } } @@ -1212,7 +1212,7 @@ int arm7_9_halt(struct target *target) embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], - ~EICE_W_CTRL_nOPC & 0xff); + ~EICE_W_CTRL_NOPC & 0xff); } target->debug_reason = DBG_REASON_DBGRQ; @@ -1873,14 +1873,14 @@ void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc) embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], - ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff); + ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_NOPC) & 0xff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], - ~EICE_W_CTRL_nOPC & 0xff); + ~EICE_W_CTRL_NOPC & 0xff); } else { embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff); @@ -1892,7 +1892,7 @@ void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc) embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], - ~EICE_W_CTRL_nOPC & 0xff); + ~EICE_W_CTRL_NOPC & 0xff); } } diff --git a/src/target/arm920t.c b/src/target/arm920t.c index a45dc6420..c8842da03 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -799,11 +799,11 @@ int arm920t_soft_reset_halt(struct target *target) /* FIXME remove forward decls */ static int arm920t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, + uint32_t crn, uint32_t crm, uint32_t *value); static int arm920t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, + uint32_t crn, uint32_t crm, uint32_t value); static int arm920t_init_arch_info(struct target *target, @@ -873,7 +873,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) uint32_t cp15_ctrl, cp15_ctrl_saved; uint32_t regs[16]; uint32_t *regs_p[16]; - uint32_t C15_C_D_Ind, C15_C_I_Ind; + uint32_t c15_c_d_ind, c15_c_i_ind; int i; FILE *output; int segment, index_t; @@ -933,7 +933,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) /* read current victim */ arm920t_read_cp15_physical(target, - CP15PHYS_DCACHE_IDX, &C15_C_D_Ind); + CP15PHYS_DCACHE_IDX, &c15_c_d_ind); /* clear interpret mode */ cp15c15 &= ~0x1; @@ -992,7 +992,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) } /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */ - regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26); + regs[0] = 0x0 | (segment << 5) | (c15_c_d_ind << 26); arm9tdmi_write_core_regs(target, 0x1, regs); /* set interpret mode */ @@ -1034,7 +1034,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) /* read current victim */ arm920t_read_cp15_physical(target, CP15PHYS_ICACHE_IDX, - &C15_C_I_Ind); + &c15_c_i_ind); /* clear interpret mode */ cp15c15 &= ~0x1; @@ -1092,7 +1092,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) } /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */ - regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26); + regs[0] = 0x0 | (segment << 5) | (c15_c_d_ind << 26); arm9tdmi_write_core_regs(target, 0x1, regs); /* set interpret mode */ @@ -1156,7 +1156,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) uint32_t *regs_p[16]; int i; FILE *output; - uint32_t Dlockdown, Ilockdown; + uint32_t d_lockdown, i_lockdown; struct arm920t_tlb_entry d_tlb[64], i_tlb[64]; int victim; struct reg *r; @@ -1213,13 +1213,13 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) retval = jtag_execute_queue(); if (retval != ERROR_OK) return retval; - Dlockdown = regs[1]; + d_lockdown = regs[1]; for (victim = 0; victim < 64; victim += 8) { /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] * base remains unchanged, victim goes through entries 0 to 63 */ - regs[1] = (Dlockdown & 0xfc000000) | (victim << 20); + regs[1] = (d_lockdown & 0xfc000000) | (victim << 20); arm9tdmi_write_core_regs(target, 0x2, regs); /* set interpret mode */ @@ -1256,7 +1256,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] * base remains unchanged, victim goes through entries 0 to 63 */ - regs[1] = (Dlockdown & 0xfc000000) | (victim << 20); + regs[1] = (d_lockdown & 0xfc000000) | (victim << 20); arm9tdmi_write_core_regs(target, 0x2, regs); /* set interpret mode */ @@ -1292,7 +1292,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) } /* restore D TLB lockdown */ - regs[1] = Dlockdown; + regs[1] = d_lockdown; arm9tdmi_write_core_regs(target, 0x2, regs); /* Write D TLB lockdown */ @@ -1319,13 +1319,13 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) retval = jtag_execute_queue(); if (retval != ERROR_OK) return retval; - Ilockdown = regs[1]; + i_lockdown = regs[1]; for (victim = 0; victim < 64; victim += 8) { /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] * base remains unchanged, victim goes through entries 0 to 63 */ - regs[1] = (Ilockdown & 0xfc000000) | (victim << 20); + regs[1] = (i_lockdown & 0xfc000000) | (victim << 20); arm9tdmi_write_core_regs(target, 0x2, regs); /* set interpret mode */ @@ -1362,7 +1362,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] * base remains unchanged, victim goes through entries 0 to 63 */ - regs[1] = (Dlockdown & 0xfc000000) | (victim << 20); + regs[1] = (d_lockdown & 0xfc000000) | (victim << 20); arm9tdmi_write_core_regs(target, 0x2, regs); /* set interpret mode */ @@ -1398,7 +1398,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) } /* restore I TLB lockdown */ - regs[1] = Ilockdown; + regs[1] = i_lockdown; arm9tdmi_write_core_regs(target, 0x2, regs); /* Write I TLB lockdown */ @@ -1528,7 +1528,7 @@ COMMAND_HANDLER(arm920t_handle_cache_info_command) static int arm920t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, + uint32_t crn, uint32_t crm, uint32_t *value) { if (cpnum != 15) { @@ -1538,13 +1538,13 @@ static int arm920t_mrc(struct target *target, int cpnum, /* read "to" r0 */ return arm920t_read_cp15_interpreted(target, - ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2), + ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2), 0, value); } static int arm920t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, + uint32_t crn, uint32_t crm, uint32_t value) { if (cpnum != 15) { @@ -1554,7 +1554,7 @@ static int arm920t_mcr(struct target *target, int cpnum, /* write "from" r0 */ return arm920t_write_cp15_interpreted(target, - ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2), + ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2), 0, value); } diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 21fd6897e..ea0927be6 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -46,15 +46,15 @@ #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -#define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0)) +#define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, crn, crm) ((opcode_1 << 11) | (opcode_2 << 8) | (crn << 4) | (crm << 0)) static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, uint32_t *value) + uint32_t crn, uint32_t crm, uint32_t *value) { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm_jtag *jtag_info = &arm7_9->jtag_info; - uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); + uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, crn, crm); struct scan_field fields[4]; uint8_t address_buf[2] = {0, 0}; uint8_t nr_w_buf = 0; @@ -123,22 +123,22 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2 } static int arm926ejs_mrc(struct target *target, int cpnum, uint32_t op1, - uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) + uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value) { if (cpnum != 15) { LOG_ERROR("Only cp15 is supported"); return ERROR_FAIL; } - return arm926ejs_cp15_read(target, op1, op2, CRn, CRm, value); + return arm926ejs_cp15_read(target, op1, op2, crn, crm, value); } static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, uint32_t value) + uint32_t crn, uint32_t crm, uint32_t value) { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm_jtag *jtag_info = &arm7_9->jtag_info; - uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); + uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, crn, crm); struct scan_field fields[4]; uint8_t value_buf[4]; uint8_t address_buf[2] = {0, 0}; @@ -206,13 +206,13 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op } static int arm926ejs_mcr(struct target *target, int cpnum, uint32_t op1, - uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) + uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value) { if (cpnum != 15) { LOG_ERROR("Only cp15 is supported"); return ERROR_FAIL; } - return arm926ejs_cp15_write(target, op1, op2, CRn, CRm, value); + return arm926ejs_cp15_write(target, op1, op2, crn, crm, value); } static int arm926ejs_examine_debug_reason(struct target *target) diff --git a/src/target/arm926ejs.h b/src/target/arm926ejs.h index d4fd0cb6e..0cd523af9 100644 --- a/src/target/arm926ejs.h +++ b/src/target/arm926ejs.h @@ -29,9 +29,9 @@ struct arm926ejs_common { uint32_t common_magic; struct armv4_5_mmu_common armv4_5_mmu; int (*read_cp15)(struct target *target, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, uint32_t *value); + uint32_t crn, uint32_t crm, uint32_t *value); int (*write_cp15)(struct target *target, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, uint32_t value); + uint32_t crn, uint32_t crm, uint32_t value); uint32_t cp15_control_reg; uint32_t d_fsr; uint32_t i_fsr; diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index d1f574856..276e90d89 100644 --... [truncated message content] |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-20 13:52:06
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 7c38f24529cd765fc16a317874c46a9b428bb4b7 (commit) via 1d4b252bb16ef823d8e98bd70fc323099033898b (commit) from 65c9653cc768f77a5e8cf2af73e0f40d614bdec2 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 7c38f24529cd765fc16a317874c46a9b428bb4b7 Author: Marc Schink <de...@za...> Date: Wed Jun 23 20:54:49 2021 +0200 tcl: Adapt config files to new ftdi command syntax The patch was created automatically using the following script: %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- (cat << EOF ftdi_device_desc ftdi device_desc ftdi_serial ftdi serial ftdi_channel ftdi channel ftdi_layout_init ftdi layout_init ftdi_layout_signal ftdi layout_signal ftdi_set_signal ftdi set_signal ftdi_get_signal ftdi get_signal ftdi_vid_pid ftdi vid_pid ftdi_tdo_sample_edge ftdi tdo_sample_edge EOF ) | while read a b; do sed -i "s/$a/$b/g" $(find tcl -type f -name "*.cfg" ) done %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- Change-Id: Iff781f37bb5511b7e15cbe6dcdf6d28e89fb174f Signed-off-by: Marc Schink <de...@za...> Reviewed-on: http://openocd.zylin.com/6333 Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/tcl/board/digilent_analog_discovery.cfg b/tcl/board/digilent_analog_discovery.cfg index 954e54008..64cdacfa8 100644 --- a/tcl/board/digilent_analog_discovery.cfg +++ b/tcl/board/digilent_analog_discovery.cfg @@ -8,10 +8,10 @@ # adapter driver ftdi -ftdi_device_desc "Digilent USB Device" -ftdi_vid_pid 0x0403 0x6014 +ftdi device_desc "Digilent USB Device" +ftdi vid_pid 0x0403 0x6014 -ftdi_layout_init 0x8008 0x800b +ftdi layout_init 0x8008 0x800b adapter speed 25000 diff --git a/tcl/board/digilent_nexys_video.cfg b/tcl/board/digilent_nexys_video.cfg index f171e2403..b60ec912f 100644 --- a/tcl/board/digilent_nexys_video.cfg +++ b/tcl/board/digilent_nexys_video.cfg @@ -6,19 +6,19 @@ adapter driver ftdi adapter speed 30000 -ftdi_device_desc "Digilent USB Device" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Digilent USB Device" +ftdi vid_pid 0x0403 0x6010 # channel 0 is dedicated for Digilent's DPTI Interface # channel 1 is used for JTAG -ftdi_channel 1 +ftdi channel 1 # just TCK TDI TDO TMS, no reset -ftdi_layout_init 0x0088 0x008b +ftdi layout_init 0x0088 0x008b reset_config none # Enable sampling on falling edge for high JTAG speeds. -ftdi_tdo_sample_edge falling +ftdi tdo_sample_edge falling transport select jtag diff --git a/tcl/board/dp_busblaster_v3.cfg b/tcl/board/dp_busblaster_v3.cfg index a9974d9bc..b94b43a0b 100644 --- a/tcl/board/dp_busblaster_v3.cfg +++ b/tcl/board/dp_busblaster_v3.cfg @@ -8,6 +8,6 @@ # source [find interface/ftdi/dp_busblaster.cfg] -ftdi_channel 1 +ftdi channel 1 jtag newtap xc2c32a tap -expected-id 0x06e1c093 -irlen 8 diff --git a/tcl/board/dp_busblaster_v4.cfg b/tcl/board/dp_busblaster_v4.cfg index 7b3bee8fc..2c2f0e9d1 100644 --- a/tcl/board/dp_busblaster_v4.cfg +++ b/tcl/board/dp_busblaster_v4.cfg @@ -14,6 +14,6 @@ # source [find interface/ftdi/dp_busblaster.cfg] -ftdi_channel 1 +ftdi channel 1 jtag newtap xc2c64a tap -expected-id 0x06e5c093 -irlen 8 diff --git a/tcl/board/gumstix-aerocore.cfg b/tcl/board/gumstix-aerocore.cfg index f0103ed45..565df4cf8 100644 --- a/tcl/board/gumstix-aerocore.cfg +++ b/tcl/board/gumstix-aerocore.cfg @@ -1,10 +1,10 @@ # JTAG for the STM32F4x chip used on the Gumstix AeroCore is available on # the first interface of a Quad FTDI chip. nTRST is bit 4. adapter driver ftdi -ftdi_vid_pid 0x0403 0x6011 +ftdi vid_pid 0x0403 0x6011 -ftdi_layout_init 0x0000 0x001b -ftdi_layout_signal nTRST -data 0x0010 +ftdi layout_init 0x0000 0x001b +ftdi layout_signal nTRST -data 0x0010 source [find target/stm32f4x.cfg] reset_config trst_only diff --git a/tcl/board/kasli.cfg b/tcl/board/kasli.cfg index d492249ba..7cfdcf20e 100644 --- a/tcl/board/kasli.cfg +++ b/tcl/board/kasli.cfg @@ -1,8 +1,8 @@ adapter driver ftdi -ftdi_device_desc "Quad RS232-HS" -ftdi_vid_pid 0x0403 0x6011 -ftdi_channel 0 -ftdi_layout_init 0x0008 0x000b +ftdi device_desc "Quad RS232-HS" +ftdi vid_pid 0x0403 0x6011 +ftdi channel 0 +ftdi layout_init 0x0008 0x000b # adapter usb location 1:8 reset_config none diff --git a/tcl/board/kindle2.cfg b/tcl/board/kindle2.cfg index a39f15c67..71dca741c 100644 --- a/tcl/board/kindle2.cfg +++ b/tcl/board/kindle2.cfg @@ -37,7 +37,7 @@ jtag_ntrst_delay 30 arm11 memwrite burst disable adapter speed 1000 -ftdi_tdo_sample_edge falling +ftdi tdo_sample_edge falling proc kindle2_init {} { imx3x_reset diff --git a/tcl/board/nds32_corvettef1.cfg b/tcl/board/nds32_corvettef1.cfg index cec172342..7300ce04a 100644 --- a/tcl/board/nds32_corvettef1.cfg +++ b/tcl/board/nds32_corvettef1.cfg @@ -7,12 +7,12 @@ adapter speed 10000 adapter driver ftdi -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0c08 0x0f1b -ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 -ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 reset_config srst_only source [find target/nds32v5.cfg] diff --git a/tcl/board/numato_mimas_a7.cfg b/tcl/board/numato_mimas_a7.cfg index d4012bada..12df8913d 100644 --- a/tcl/board/numato_mimas_a7.cfg +++ b/tcl/board/numato_mimas_a7.cfg @@ -8,13 +8,13 @@ # Therefore, prefer external power supply. adapter driver ftdi -ftdi_device_desc "Mimas Artix 7 FPGA Module" -ftdi_vid_pid 0x2a19 0x1009 +ftdi device_desc "Mimas Artix 7 FPGA Module" +ftdi vid_pid 0x2a19 0x1009 # channel 0 is for custom purpose by users (like uart, fifo etc) # channel 1 is reserved for JTAG (by-default) or SPI (possible via changing solder jumpers) -ftdi_channel 1 -ftdi_tdo_sample_edge falling +ftdi channel 1 +ftdi tdo_sample_edge falling # FTDI Pin Layout @@ -28,7 +28,7 @@ ftdi_tdo_sample_edge falling # OE_N is JTAG buffer output enable signal (active-low) # PROG_B is not used, so left as input to FTDI. # -ftdi_layout_init 0x0008 0x004b +ftdi layout_init 0x0008 0x004b reset_config none adapter speed 30000 diff --git a/tcl/board/quark_d2000_refboard.cfg b/tcl/board/quark_d2000_refboard.cfg index 8b8314a0e..a89895d89 100644 --- a/tcl/board/quark_d2000_refboard.cfg +++ b/tcl/board/quark_d2000_refboard.cfg @@ -2,11 +2,11 @@ # the board has an onboard FTDI FT232H chip adapter driver ftdi -ftdi_vid_pid 0x0403 0x6014 -ftdi_channel 0 +ftdi vid_pid 0x0403 0x6014 +ftdi channel 0 -ftdi_layout_init 0x0000 0x030b -ftdi_layout_signal nTRST -data 0x0100 -noe 0x0100 +ftdi layout_init 0x0000 0x030b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0100 source [find target/quark_d20xx.cfg] diff --git a/tcl/board/sayma_amc.cfg b/tcl/board/sayma_amc.cfg index 64c085428..0bd76ba01 100644 --- a/tcl/board/sayma_amc.cfg +++ b/tcl/board/sayma_amc.cfg @@ -11,19 +11,19 @@ # which features an Artix 7 FPGA. adapter driver ftdi -ftdi_device_desc "Quad RS232-HS" -ftdi_vid_pid 0x0403 0x6011 -ftdi_channel 0 +ftdi device_desc "Quad RS232-HS" +ftdi vid_pid 0x0403 0x6011 +ftdi channel 0 # Use this to distinguish multiple boards by topology #adapter usb location 5:1 # sampling on falling edge generally seems to work and accelerates things but # is not fully tested -#ftdi_tdo_sample_edge falling +#ftdi tdo_sample_edge falling # EN_USB_JTAG on ADBUS7: out, high # USB_nTRST on ADBUS4: out, high, but R46 is DNP -ftdi_layout_init 0x0098 0x008b -#ftdi_layout_signal EN_USB -data 0x0080 -#ftdi_layout_signal nTRST -data 0x0010 +ftdi layout_init 0x0098 0x008b +#ftdi layout_signal EN_USB -data 0x0080 +#ftdi layout_signal nTRST -data 0x0010 reset_config none adapter speed 5000 diff --git a/tcl/board/sifive-e31arty.cfg b/tcl/board/sifive-e31arty.cfg index b7a255ea2..8e701f156 100644 --- a/tcl/board/sifive-e31arty.cfg +++ b/tcl/board/sifive-e31arty.cfg @@ -14,8 +14,8 @@ $_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work- flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 init if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z + ftdi set_signal nSRST 0 + ftdi set_signal nSRST z } halt flash protect 0 64 last off diff --git a/tcl/board/sifive-e51arty.cfg b/tcl/board/sifive-e51arty.cfg index 20ad57551..a543987bb 100644 --- a/tcl/board/sifive-e51arty.cfg +++ b/tcl/board/sifive-e51arty.cfg @@ -14,8 +14,8 @@ $_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work- flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 init if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z + ftdi set_signal nSRST 0 + ftdi set_signal nSRST z } halt flash protect 0 64 last off diff --git a/tcl/board/sifive-hifive1.cfg b/tcl/board/sifive-hifive1.cfg index 196f540bb..c47485bf2 100644 --- a/tcl/board/sifive-hifive1.cfg +++ b/tcl/board/sifive-hifive1.cfg @@ -1,15 +1,15 @@ adapter speed 10000 adapter driver ftdi -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0008 0x001b -ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 +ftdi layout_init 0x0008 0x001b +ftdi layout_signal nSRST -oe 0x0020 -data 0x0020 #Reset Stretcher logic on FE310 is ~1 second long #This doesn't apply if you use -# ftdi_set_signal, but still good to document +# ftdi set_signal, but still good to document #adapter srst delay 1500 set _CHIPNAME riscv @@ -23,8 +23,8 @@ flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME init #reset -- This type of reset is not implemented yet if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z + ftdi set_signal nSRST 0 + ftdi set_signal nSRST z #Wait for the reset stretcher #It will work without this, but #will incur lots of delays for later commands. diff --git a/tcl/board/ti_tmdx570ls20susb.cfg b/tcl/board/ti_tmdx570ls20susb.cfg index 87cab2690..e71136cfe 100644 --- a/tcl/board/ti_tmdx570ls20susb.cfg +++ b/tcl/board/ti_tmdx570ls20susb.cfg @@ -12,5 +12,5 @@ reset_config trst_only # xds100v2 config says add this to the end init -ftdi_set_signal PWR_RST 1 +ftdi set_signal PWR_RST 1 jtag arp_init diff --git a/tcl/interface/ftdi/100ask-openjtag.cfg b/tcl/interface/ftdi/100ask-openjtag.cfg index 3cbd37e06..a12df97af 100644 --- a/tcl/interface/ftdi/100ask-openjtag.cfg +++ b/tcl/interface/ftdi/100ask-openjtag.cfg @@ -8,9 +8,9 @@ # adapter driver ftdi -ftdi_device_desc "USB<=>JTAG&RS232" -ftdi_vid_pid 0x1457 0x5118 +ftdi device_desc "USB<=>JTAG&RS232" +ftdi vid_pid 0x1457 0x5118 -ftdi_layout_init 0x0f08 0x0f1b -ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 -ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_init 0x0f08 0x0f1b +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 diff --git a/tcl/interface/ftdi/axm0432.cfg b/tcl/interface/ftdi/axm0432.cfg index 6cc1752e2..84b77a69a 100644 --- a/tcl/interface/ftdi/axm0432.cfg +++ b/tcl/interface/ftdi/axm0432.cfg @@ -10,9 +10,9 @@ echo "Please report your experience with this file to openocd-devel mailing list echo "so it could be marked as working or fixed." adapter driver ftdi -ftdi_device_desc "Symphony SoundBite" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Symphony SoundBite" +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0c08 0x0c2b -ftdi_layout_signal nTRST -data 0x0800 -ftdi_layout_signal nSRST -data 0x0400 +ftdi layout_init 0x0c08 0x0c2b +ftdi layout_signal nTRST -data 0x0800 +ftdi layout_signal nSRST -data 0x0400 diff --git a/tcl/interface/ftdi/c232hm.cfg b/tcl/interface/ftdi/c232hm.cfg index 27cf76674..25fcae1b0 100644 --- a/tcl/interface/ftdi/c232hm.cfg +++ b/tcl/interface/ftdi/c232hm.cfg @@ -14,18 +14,18 @@ # http://www.ftdichip.com/Support/Documents/AppNotes/AN_129_FTDI_Hi_Speed_USB_To_JTAG_Example.pdf adapter driver ftdi -#ftdi_device_desc "C232HM-DDHSL-0" -#ftdi_device_desc "C232HM-EDHSL-0" +#ftdi device_desc "C232HM-DDHSL-0" +#ftdi device_desc "C232HM-EDHSL-0" # Common PID for FT232H -ftdi_vid_pid 0x0403 0x6014 +ftdi vid_pid 0x0403 0x6014 # Layout # High data byte 0x40 configures red LED on ACBUS6 initially high (unlit, since active-low) # Low data byte 0x08 configures TMS on ACBUS3 initially high (asserted); TCK, TDI low # High direction byte 0x40 configures red LED on ACBUS6 as high (output) # Low direction byte 0x0b configures TDO on ACBUS2 as low (input) -ftdi_layout_init 0x4008 0x400b +ftdi layout_init 0x4008 0x400b # ---A*BUS-------CCCCCCCC|DDDDDDDD # --------\______76543210|76543210 @@ -35,12 +35,12 @@ ftdi_layout_init 0x4008 0x400b #GPIOL2 0x0040 = 00000000|01000000 = ADBUS6 #GPIOL3 0x0080 = 00000000|10000000 = ADBUS7 # -ndata treats the LED as active-low for expected behavior (toggle when transferring) -ftdi_layout_signal LED -ndata 0x4000 +ftdi layout_signal LED -ndata 0x4000 # Available for aliasing as desired -ftdi_layout_signal GPIOL0 -data 0x0010 -oe 0x0010 -ftdi_layout_signal GPIOL1 -data 0x0020 -oe 0x0020 -ftdi_layout_signal GPIOL2 -data 0x0040 -oe 0x0040 -ftdi_layout_signal GPIOL3 -data 0x0080 -oe 0x0080 +ftdi layout_signal GPIOL0 -data 0x0010 -oe 0x0010 +ftdi layout_signal GPIOL1 -data 0x0020 -oe 0x0020 +ftdi layout_signal GPIOL2 -data 0x0040 -oe 0x0040 +ftdi layout_signal GPIOL3 -data 0x0080 -oe 0x0080 # C232HM FT232H JTAG/Other # Num Color Name Func diff --git a/tcl/interface/ftdi/calao-usb-a9260-c01.cfg b/tcl/interface/ftdi/calao-usb-a9260-c01.cfg index a23ddbfb5..41e597391 100644 --- a/tcl/interface/ftdi/calao-usb-a9260-c01.cfg +++ b/tcl/interface/ftdi/calao-usb-a9260-c01.cfg @@ -11,12 +11,12 @@ echo "experience with this file to openocd-devel mailing list, so it could be ma echo "as working or fixed." adapter driver ftdi -ftdi_device_desc "USB-A9260" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "USB-A9260" +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0c08 0x0f1b -ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 -ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 script interface/calao-usb-a9260.cfg script target/at91sam9260minimal.cfg diff --git a/tcl/interface/ftdi/calao-usb-a9260-c02.cfg b/tcl/interface/ftdi/calao-usb-a9260-c02.cfg index 67427c5c0..001aef59c 100644 --- a/tcl/interface/ftdi/calao-usb-a9260-c02.cfg +++ b/tcl/interface/ftdi/calao-usb-a9260-c02.cfg @@ -11,12 +11,12 @@ echo "experience with this file to openocd-devel mailing list, so it could be ma echo "as working or fixed." adapter driver ftdi -ftdi_device_desc "USB-A9260" -ftdi_vid_pid 0x0403 0x6001 +ftdi device_desc "USB-A9260" +ftdi vid_pid 0x0403 0x6001 -ftdi_layout_init 0x0c08 0x0f1b -ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 -ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 script interface/calao-usb-a9260.cfg script target/at91sam9260minimal.cfg diff --git a/tcl/interface/ftdi/cortino.cfg b/tcl/interface/ftdi/cortino.cfg index 2bc516cc6..c0eae3105 100644 --- a/tcl/interface/ftdi/cortino.cfg +++ b/tcl/interface/ftdi/cortino.cfg @@ -5,9 +5,9 @@ # adapter driver ftdi -ftdi_device_desc "Cortino" -ftdi_vid_pid 0x0640 0x0032 +ftdi device_desc "Cortino" +ftdi vid_pid 0x0640 0x0032 -ftdi_layout_init 0x0108 0x010b -ftdi_layout_signal nTRST -data 0x0100 -ftdi_layout_signal nSRST -data 0x0200 -oe 0x0200 +ftdi layout_init 0x0108 0x010b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0200 -oe 0x0200 diff --git a/tcl/interface/ftdi/digilent-hs1.cfg b/tcl/interface/ftdi/digilent-hs1.cfg index dfba3393a..55391b9d3 100644 --- a/tcl/interface/ftdi/digilent-hs1.cfg +++ b/tcl/interface/ftdi/digilent-hs1.cfg @@ -2,10 +2,10 @@ # (the later being the OEM on-board version) adapter driver ftdi -ftdi_device_desc "Digilent Adept USB Device" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Digilent Adept USB Device" +ftdi vid_pid 0x0403 0x6010 # channel 1 does not have any functionality -ftdi_channel 0 +ftdi channel 0 # just TCK TDI TDO TMS, no reset -ftdi_layout_init 0x0088 0x008b +ftdi layout_init 0x0088 0x008b reset_config none diff --git a/tcl/interface/ftdi/digilent-hs2.cfg b/tcl/interface/ftdi/digilent-hs2.cfg index ae6ba01bb..269eca0f3 100644 --- a/tcl/interface/ftdi/digilent-hs2.cfg +++ b/tcl/interface/ftdi/digilent-hs2.cfg @@ -1,10 +1,10 @@ # this supports JTAG-HS2 (and apparently Nexys4 as well) adapter driver ftdi -ftdi_device_desc "Digilent Adept USB Device" -ftdi_vid_pid 0x0403 0x6014 +ftdi device_desc "Digilent Adept USB Device" +ftdi vid_pid 0x0403 0x6014 -ftdi_channel 0 -ftdi_layout_init 0x00e8 0x60eb +ftdi channel 0 +ftdi layout_init 0x00e8 0x60eb reset_config none diff --git a/tcl/interface/ftdi/digilent_jtag_hs3.cfg b/tcl/interface/ftdi/digilent_jtag_hs3.cfg index 7160bed8e..ca2807f80 100644 --- a/tcl/interface/ftdi/digilent_jtag_hs3.cfg +++ b/tcl/interface/ftdi/digilent_jtag_hs3.cfg @@ -3,11 +3,11 @@ # adapter driver ftdi -ftdi_vid_pid 0x0403 0x6014 -ftdi_device_desc "Digilent USB Device" +ftdi vid_pid 0x0403 0x6014 +ftdi device_desc "Digilent USB Device" # From Digilent support: # The SRST pin is [...] 0x20 and 0x10 is the /OE (active low output enable) -ftdi_layout_init 0x2088 0x308b -ftdi_layout_signal nSRST -data 0x2000 -noe 0x1000 +ftdi layout_init 0x2088 0x308b +ftdi layout_signal nSRST -data 0x2000 -noe 0x1000 diff --git a/tcl/interface/ftdi/digilent_jtag_smt2.cfg b/tcl/interface/ftdi/digilent_jtag_smt2.cfg index 55f278bdc..f4ba27bef 100644 --- a/tcl/interface/ftdi/digilent_jtag_smt2.cfg +++ b/tcl/interface/ftdi/digilent_jtag_smt2.cfg @@ -8,10 +8,10 @@ # adapter driver ftdi -ftdi_vid_pid 0x0403 0x6014 +ftdi vid_pid 0x0403 0x6014 -ftdi_layout_init 0x20e8 0x3feb -ftdi_layout_signal nSRST -data 0x2000 -ftdi_layout_signal GPIO2 -data 0x2000 -ftdi_layout_signal GPIO1 -data 0x0200 -ftdi_layout_signal GPIO0 -data 0x0100 +ftdi layout_init 0x20e8 0x3feb +ftdi layout_signal nSRST -data 0x2000 +ftdi layout_signal GPIO2 -data 0x2000 +ftdi layout_signal GPIO1 -data 0x0200 +ftdi layout_signal GPIO0 -data 0x0100 diff --git a/tcl/interface/ftdi/digilent_jtag_smt2_nc.cfg b/tcl/interface/ftdi/digilent_jtag_smt2_nc.cfg index bc783a46c..a143cd772 100644 --- a/tcl/interface/ftdi/digilent_jtag_smt2_nc.cfg +++ b/tcl/interface/ftdi/digilent_jtag_smt2_nc.cfg @@ -8,11 +8,11 @@ # https://www.xilinx.com/products/boards-and-kits/kcu105.html#documentation # # Note that the digilent_jtag_smt2 layout does not work and hangs while -# the ftdi_device_desc from digilent_hs2 is wrong. +# the ftdi device_desc from digilent_hs2 is wrong. adapter driver ftdi -ftdi_device_desc "Digilent USB Device" -ftdi_vid_pid 0x0403 0x6014 -ftdi_channel 0 -ftdi_layout_init 0x00e8 0x60eb +ftdi device_desc "Digilent USB Device" +ftdi vid_pid 0x0403 0x6014 +ftdi channel 0 +ftdi layout_init 0x00e8 0x60eb reset_config none diff --git a/tcl/interface/ftdi/dlp-usb1232h.cfg b/tcl/interface/ftdi/dlp-usb1232h.cfg index 9ddc2c80a..e9651dd99 100644 --- a/tcl/interface/ftdi/dlp-usb1232h.cfg +++ b/tcl/interface/ftdi/dlp-usb1232h.cfg @@ -13,9 +13,9 @@ echo "in ft2232.c. Please report your experience with this file to openocd-devel echo "mailing list, so it could be marked as working or fixed." adapter driver ftdi -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0008 0x000b -ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010 -ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040 +ftdi layout_init 0x0008 0x000b +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nSRST -data 0x0040 -oe 0x0040 diff --git a/tcl/interface/ftdi/dp_busblaster.cfg b/tcl/interface/ftdi/dp_busblaster.cfg index 86ab4d840..420f788d2 100644 --- a/tcl/interface/ftdi/dp_busblaster.cfg +++ b/tcl/interface/ftdi/dp_busblaster.cfg @@ -12,9 +12,9 @@ echo "Info : If you need SWD support, flash KT-Link buffer from https://github.c and use dp_busblaster_kt-link.cfg instead" adapter driver ftdi -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0c08 0x0f1b -ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 -ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/tcl/interface/ftdi/dp_busblaster_kt-link.cfg b/tcl/interface/ftdi/dp_busblaster_kt-link.cfg index d49a4c98f..4924d2619 100644 --- a/tcl/interface/ftdi/dp_busblaster_kt-link.cfg +++ b/tcl/interface/ftdi/dp_busblaster_kt-link.cfg @@ -10,12 +10,12 @@ # adapter driver ftdi -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x8c28 0xff3b -ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 -ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 -ftdi_layout_signal LED -ndata 0x8000 -ftdi_layout_signal SWD_EN -ndata 0x0020 -oe 0x2000 -ftdi_layout_signal SWDIO_OE -ndata 0x1000 +ftdi layout_init 0x8c28 0xff3b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_signal LED -ndata 0x8000 +ftdi layout_signal SWD_EN -ndata 0x0020 -oe 0x2000 +ftdi layout_signal SWDIO_OE -ndata 0x1000 diff --git a/tcl/interface/ftdi/flossjtag-noeeprom.cfg b/tcl/interface/ftdi/flossjtag-noeeprom.cfg index 42ed18ec3..7083e6388 100644 --- a/tcl/interface/ftdi/flossjtag-noeeprom.cfg +++ b/tcl/interface/ftdi/flossjtag-noeeprom.cfg @@ -18,9 +18,9 @@ echo "Please report your experience with this file to openocd-devel mailing list echo "so it could be marked as working or fixed." adapter driver ftdi -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0008 0x000b -ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010 -ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040 +ftdi layout_init 0x0008 0x000b +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nSRST -data 0x0040 -oe 0x0040 diff --git a/tcl/interface/ftdi/flossjtag.cfg b/tcl/interface/ftdi/flossjtag.cfg index c4ad81dcc..2e3cfca48 100644 --- a/tcl/interface/ftdi/flossjtag.cfg +++ b/tcl/interface/ftdi/flossjtag.cfg @@ -18,12 +18,12 @@ echo "Please report your experience with this file to openocd-devel mailing list echo "so it could be marked as working or fixed." adapter driver ftdi -ftdi_vid_pid 0x0403 0x6010 -ftdi_device_desc "FLOSS-JTAG" -#ftdi_serial "FJ000001" +ftdi vid_pid 0x0403 0x6010 +ftdi device_desc "FLOSS-JTAG" +#ftdi serial "FJ000001" -ftdi_layout_init 0x0008 0x180b -ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010 -ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040 -ftdi_layout_signal LED -data 0x0800 -ftdi_layout_signal LED2 -data 0x1000 +ftdi layout_init 0x0008 0x180b +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nSRST -data 0x0040 -oe 0x0040 +ftdi layout_signal LED -data 0x0800 +ftdi layout_signal LED2 -data 0x1000 diff --git a/tcl/interface/ftdi/flyswatter.cfg b/tcl/interface/ftdi/flyswatter.cfg index 0b849ad53..bfa015b2c 100644 --- a/tcl/interface/ftdi/flyswatter.cfg +++ b/tcl/interface/ftdi/flyswatter.cfg @@ -5,10 +5,10 @@ # adapter driver ftdi -ftdi_device_desc "Flyswatter" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Flyswatter" +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0818 0x0cfb -ftdi_layout_signal nTRST -data 0x0010 -ftdi_layout_signal nSRST -oe 0x0020 -ftdi_layout_signal LED -data 0x0c00 +ftdi layout_init 0x0818 0x0cfb +ftdi layout_signal nTRST -data 0x0010 +ftdi layout_signal nSRST -oe 0x0020 +ftdi layout_signal LED -data 0x0c00 diff --git a/tcl/interface/ftdi/flyswatter2.cfg b/tcl/interface/ftdi/flyswatter2.cfg index 4f4a1f819..0b4a8ef9f 100644 --- a/tcl/interface/ftdi/flyswatter2.cfg +++ b/tcl/interface/ftdi/flyswatter2.cfg @@ -5,10 +5,10 @@ # adapter driver ftdi -ftdi_device_desc "Flyswatter2" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Flyswatter2" +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0538 0x057b -ftdi_layout_signal LED -ndata 0x0400 -ftdi_layout_signal nTRST -data 0x0010 -ftdi_layout_signal nSRST -data 0x0020 -noe 0x0100 +ftdi layout_init 0x0538 0x057b +ftdi layout_signal LED -ndata 0x0400 +ftdi layout_signal nTRST -data 0x0010 +ftdi layout_signal nSRST -data 0x0020 -noe 0x0100 diff --git a/tcl/interface/ftdi/ft232h-module-swd.cfg b/tcl/interface/ftdi/ft232h-module-swd.cfg index 98a8c844f..7fa428359 100644 --- a/tcl/interface/ftdi/ft232h-module-swd.cfg +++ b/tcl/interface/ftdi/ft232h-module-swd.cfg @@ -8,27 +8,27 @@ adapter driver ftdi -ftdi_vid_pid 0x0403 0x6014 +ftdi vid_pid 0x0403 0x6014 # data MSB..LSB direction (1:out) MSB..LSB # 0000'0000'0011'0000 0000'0000'0011'1011 -ftdi_layout_init 0x0030 0x003b +ftdi layout_init 0x0030 0x003b # 0xfff8 0xfffb # Those signal are only required on some platforms or may required to be # enabled explicitly (e.g. nrf5x chips). -ftdi_layout_signal nSRST -data 0x0010 -oe 0x0010 -ftdi_layout_signal nTRST -data 0x0020 -oe 0x0020 +ftdi layout_signal nSRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nTRST -data 0x0020 -oe 0x0020 # swd enable -ftdi_layout_signal SWD_EN -data 0 +ftdi layout_signal SWD_EN -data 0 # tri-state (configure as input) TDO/TIO when reading -ftdi_layout_signal SWDIO_OE -data 0 +ftdi layout_signal SWDIO_OE -data 0 transport select swd # re-configure TDO as tri-state -#ftdi_layout_signal TDO -data 0x0002 -oe 0x0002 -#ftdi_layout_signal TDI -data 0x0004 +#ftdi layout_signal TDO -data 0x0002 -oe 0x0002 +#ftdi layout_signal TDI -data 0x0004 # Adafruit FT232H JTAG SWD # Name Pin Name Func Func diff --git a/tcl/interface/ftdi/gw16042.cfg b/tcl/interface/ftdi/gw16042.cfg index 1288f77b1..ef3182938 100644 --- a/tcl/interface/ftdi/gw16042.cfg +++ b/tcl/interface/ftdi/gw16042.cfg @@ -18,9 +18,9 @@ # adapter driver ftdi -ftdi_device_desc "USB-JTAG" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "USB-JTAG" +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0058 0x007b -ftdi_layout_signal nTRST -data 0x0010 -ftdi_layout_signal nSRST -oe 0x0020 +ftdi layout_init 0x0058 0x007b +ftdi layout_signal nTRST -data 0x0010 +ftdi layout_signal nSRST -oe 0x0020 diff --git a/tcl/interface/ftdi/hie-jtag.cfg b/tcl/interface/ftdi/hie-jtag.cfg index 39af87d89..6694df048 100644 --- a/tcl/interface/ftdi/hie-jtag.cfg +++ b/tcl/interface/ftdi/hie-jtag.cfg @@ -6,15 +6,15 @@ # adapter driver ftdi -ftdi_channel 0 -ftdi_vid_pid 0x0403 0x6014 -ftdi_device_desc "HIE JTAG Debugger" +ftdi channel 0 +ftdi vid_pid 0x0403 0x6014 +ftdi device_desc "HIE JTAG Debugger" -ftdi_layout_init 0x0c08 0x4f1b +ftdi layout_init 0x0c08 0x4f1b # define both Reset signals -ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 -ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 # Toggle USB LED -ftdi_layout_signal LED -ndata 0x4000 +ftdi layout_signal LED -ndata 0x4000 diff --git a/tcl/interface/ftdi/hilscher_nxhx10_etm.cfg b/tcl/interface/ftdi/hilscher_nxhx10_etm.cfg index 3802f6d2c..d55f636de 100644 --- a/tcl/interface/ftdi/hilscher_nxhx10_etm.cfg +++ b/tcl/interface/ftdi/hilscher_nxhx10_etm.cfg @@ -10,9 +10,9 @@ echo "Please report your experience with this file to openocd-devel mailing list echo "so it could be marked as working or fixed." adapter driver ftdi -ftdi_device_desc "NXHX 10-ETM" -ftdi_vid_pid 0x0640 0x0028 +ftdi device_desc "NXHX 10-ETM" +ftdi vid_pid 0x0640 0x0028 -ftdi_layout_init 0x0308 0x030b -ftdi_layout_signal nTRST -data 0x0100 -ftdi_layout_signal nSRST -data 0x0200 +ftdi layout_init 0x0308 0x030b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0200 diff --git a/tcl/interface/ftdi/hilscher_nxhx500_etm.cfg b/tcl/interface/ftdi/hilscher_nxhx500_etm.cfg index f2e64b4f5..8c7981561 100644 --- a/tcl/interface/ftdi/hilscher_nxhx500_etm.cfg +++ b/tcl/interface/ftdi/hilscher_nxhx500_etm.cfg @@ -10,9 +10,9 @@ echo "Please report your experience with this file to openocd-devel mailing list echo "so it could be marked as working or fixed." adapter driver ftdi -ftdi_device_desc "NXHX 500-ETM" -ftdi_vid_pid 0x0640 0x0028 +ftdi device_desc "NXHX 500-ETM" +ftdi vid_pid 0x0640 0x0028 -ftdi_layout_init 0x0308 0x030b -ftdi_layout_signal nTRST -data 0x0100 -ftdi_layout_signal nSRST -data 0x0200 +ftdi layout_init 0x0308 0x030b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0200 diff --git a/tcl/interface/ftdi/hilscher_nxhx500_re.cfg b/tcl/interface/ftdi/hilscher_nxhx500_re.cfg index 38f3c690e..9aa2cd516 100644 --- a/tcl/interface/ftdi/hilscher_nxhx500_re.cfg +++ b/tcl/interface/ftdi/hilscher_nxhx500_re.cfg @@ -10,9 +10,9 @@ echo "Please report your experience with this file to openocd-devel mailing list echo "so it could be marked as working or fixed." adapter driver ftdi -ftdi_device_desc "NXHX 500-RE" -ftdi_vid_pid 0x0640 0x0028 +ftdi device_desc "NXHX 500-RE" +ftdi vid_pid 0x0640 0x0028 -ftdi_layout_init 0x0308 0x030b -ftdi_layout_signal nTRST -data 0x0100 -ftdi_layout_signal nSRST -data 0x0200 +ftdi layout_init 0x0308 0x030b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0200 diff --git a/tcl/interface/ftdi/hilscher_nxhx50_etm.cfg b/tcl/interface/ftdi/hilscher_nxhx50_etm.cfg index bff081f18..a64d0e8a4 100644 --- a/tcl/interface/ftdi/hilscher_nxhx50_etm.cfg +++ b/tcl/interface/ftdi/hilscher_nxhx50_etm.cfg @@ -10,9 +10,9 @@ echo "Please report your experience with this file to openocd-devel mailing list echo "so it could be marked as working or fixed." adapter driver ftdi -ftdi_device_desc "NXHX 50-ETM" -ftdi_vid_pid 0x0640 0x0028 +ftdi device_desc "NXHX 50-ETM" +ftdi vid_pid 0x0640 0x0028 -ftdi_layout_init 0x0308 0x030b -ftdi_layout_signal nTRST -data 0x0100 -ftdi_layout_signal nSRST -data 0x0200 +ftdi layout_init 0x0308 0x030b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0200 diff --git a/tcl/interface/ftdi/hilscher_nxhx50_re.cfg b/tcl/interface/ftdi/hilscher_nxhx50_re.cfg index f9fbd015a..277883675 100644 --- a/tcl/interface/ftdi/hilscher_nxhx50_re.cfg +++ b/tcl/interface/ftdi/hilscher_nxhx50_re.cfg @@ -10,9 +10,9 @@ echo "Please report your experience with this file to openocd-devel mailing list echo "so it could be marked as working or fixed." adapter driver ftdi -ftdi_device_desc "NXHX50-RE" -ftdi_vid_pid 0x0640 0x0028 +ftdi device_desc "NXHX50-RE" +ftdi vid_pid 0x0640 0x0028 -ftdi_layout_init 0x0308 0x030b -ftdi_layout_signal nTRST -data 0x0100 -ftdi_layout_signal nSRST -data 0x0200 +ftdi layout_init 0x0308 0x030b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0200 diff --git a/tcl/interface/ftdi/hitex_lpc1768stick.cfg b/tcl/interface/ftdi/hitex_lpc1768stick.cfg index 9fe80f126..87affe84a 100644 --- a/tcl/interface/ftdi/hitex_lpc1768stick.cfg +++ b/tcl/interface/ftdi/hitex_lpc1768stick.cfg @@ -6,9 +6,9 @@ adapter driver ftdi -ftdi_device_desc "LPC1768-Stick" -ftdi_vid_pid 0x0640 0x0026 +ftdi device_desc "LPC1768-Stick" +ftdi vid_pid 0x0640 0x0026 -ftdi_layout_init 0x0388 0x038b -ftdi_layout_signal nTRST -data 0x0100 -ftdi_layout_signal nSRST -data 0x0080 -noe 0x200 +ftdi layout_init 0x0388 0x038b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0080 -noe 0x200 diff --git a/tcl/interface/ftdi/hitex_str9-comstick.cfg b/tcl/interface/ftdi/hitex_str9-comstick.cfg index 2b3dc3690..6490d65f4 100644 --- a/tcl/interface/ftdi/hitex_str9-comstick.cfg +++ b/tcl/interface/ftdi/hitex_str9-comstick.cfg @@ -5,9 +5,9 @@ # adapter driver ftdi -ftdi_device_desc "STR9-comStick" -ftdi_vid_pid 0x0640 0x002c +ftdi device_desc "STR9-comStick" +ftdi vid_pid 0x0640 0x002c -ftdi_layout_init 0x0108 0x010b -ftdi_layout_signal nTRST -data 0x0100 -ftdi_layout_signal nSRST -data 0x0200 -oe 0x0200 +ftdi layout_init 0x0108 0x010b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0200 -oe 0x0200 diff --git a/tcl/interface/ftdi/icebear.cfg b/tcl/interface/ftdi/icebear.cfg index 04c27319e..76b2102a5 100644 --- a/tcl/interface/ftdi/icebear.cfg +++ b/tcl/interface/ftdi/icebear.cfg @@ -10,9 +10,9 @@ echo "Please report your experience with this file to openocd-devel mailing list echo "so it could be marked as working or fixed." adapter driver ftdi -ftdi_device_desc "ICEbear JTAG adapter" -ftdi_vid_pid 0x0403 0xc140 +ftdi device_desc "ICEbear JTAG adapter" +ftdi vid_pid 0x0403 0xc140 -ftdi_layout_init 0x0028 0x002b -ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010 -ftdi_layout_signal nSRST -data 0x0020 +ftdi layout_init 0x0028 0x002b +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nSRST -data 0x0020 diff --git a/tcl/interface/ftdi/imx8mp-evk.cfg b/tcl/interface/ftdi/imx8mp-evk.cfg index 4e04e8cd7..64f3f3db0 100644 --- a/tcl/interface/ftdi/imx8mp-evk.cfg +++ b/tcl/interface/ftdi/imx8mp-evk.cfg @@ -11,18 +11,18 @@ # adapter driver ftdi -ftdi_vid_pid 0x0403 0x6011 -ftdi_channel 0 +ftdi vid_pid 0x0403 0x6011 +ftdi channel 0 -ftdi_layout_init 0x00f8 0x000b +ftdi layout_init 0x00f8 0x000b -ftdi_layout_signal RESET_B -data 0x0010 -oe 0x0010 +ftdi layout_signal RESET_B -data 0x0010 -oe 0x0010 # Called SYS_nRST in schematics -ftdi_layout_signal nSRST -data 0x0020 -oe 0x0020 -ftdi_layout_signal IO_nRST -data 0x0040 -oe 0x0040 -ftdi_layout_signal ONOFF_B -data 0x0080 -oe 0x0080 +ftdi layout_signal nSRST -data 0x0020 -oe 0x0020 +ftdi layout_signal IO_nRST -data 0x0040 -oe 0x0040 +ftdi layout_signal ONOFF_B -data 0x0080 -oe 0x0080 -ftdi_layout_signal GPIO1 -data 0x0100 -oe 0x0100 -ftdi_layout_signal GPIO2 -data 0x0200 -oe 0x0200 -ftdi_layout_signal GPIO3 -data 0x0400 -oe 0x0400 -ftdi_layout_signal GPIO4 -data 0x0800 -oe 0x0800 +ftdi layout_signal GPIO1 -data 0x0100 -oe 0x0100 +ftdi layout_signal GPIO2 -data 0x0200 -oe 0x0200 +ftdi layout_signal GPIO3 -data 0x0400 -oe 0x0400 +ftdi layout_signal GPIO4 -data 0x0800 -oe 0x0800 diff --git a/tcl/interface/ftdi/incircuit-icprog.cfg b/tcl/interface/ftdi/incircuit-icprog.cfg index e0bd5ef59..a20095446 100644 --- a/tcl/interface/ftdi/incircuit-icprog.cfg +++ b/tcl/interface/ftdi/incircuit-icprog.cfg @@ -7,8 +7,8 @@ # adapter driver ftdi -ftdi_vid_pid 0x0403 0x6010 +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0508 0x0f1b -ftdi_layout_signal nSRST -noe 0x0400 -data 0x0800 -ftdi_layout_signal nTRST -noe 0x0100 -data 0x0200 +ftdi layout_init 0x0508 0x0f1b +ftdi layout_signal nSRST -noe 0x0400 -data 0x0800 +ftdi layout_signal nTRST -noe 0x0100 -data 0x0200 diff --git a/tcl/interface/ftdi/iotlab-usb.cfg b/tcl/interface/ftdi/iotlab-usb.cfg index caa0596fd..92ffa840b 100644 --- a/tcl/interface/ftdi/iotlab-usb.cfg +++ b/tcl/interface/ftdi/iotlab-usb.cfg @@ -4,8 +4,8 @@ # adapter driver ftdi -ftdi_vid_pid 0x0403 0x6010 +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0008 0x000b -ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010 -ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040 +ftdi layout_init 0x0008 0x000b +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nSRST -data 0x0040 -oe 0x0040 diff --git a/tcl/interface/ftdi/isodebug.cfg b/tcl/interface/ftdi/isodebug.cfg index ead28644c..018998963 100644 --- a/tcl/interface/ftdi/isodebug.cfg +++ b/tcl/interface/ftdi/isodebug.cfg @@ -2,26 +2,26 @@ # 5 kV isolated JTAG/SWD + UART adapter by Unjo AB adapter driver ftdi -ftdi_vid_pid 0x22b7 0x150d +ftdi vid_pid 0x22b7 0x150d -ftdi_layout_init 0x0ff8 0xfffb +ftdi layout_init 0x0ff8 0xfffb -ftdi_layout_signal LED -ndata 0x0100 -ftdi_layout_signal nTRST -data 0x0200 -ftdi_layout_signal nSRST -noe 0x0400 -ftdi_layout_signal SWDIO_OE -data 0x0008 +ftdi layout_signal LED -ndata 0x0100 +ftdi layout_signal nTRST -data 0x0200 +ftdi layout_signal nSRST -noe 0x0400 +ftdi layout_signal SWDIO_OE -data 0x0008 # Mode signals, either of these needs to be high to drive the JTAG/SWD pins. # The power-on state is low for both signals but the init setting above sets # JTAG_EN high. -ftdi_layout_signal SWD_EN -data 0x1000 -ftdi_layout_signal JTAG_EN -data 0x0800 +ftdi layout_signal SWD_EN -data 0x1000 +ftdi layout_signal JTAG_EN -data 0x0800 # In SWD mode, the JTAG_EN signal doubles as SWO_EN_N which switches the # second FTDI channel UART RxD to the SWO pin instead of the separate RxD # pin. Note that the default init state has this pin high so when OpenOCD # starts in SWD mode, SWO is by default disabled. To enable SWO tracing, -# issue the command 'ftdi_set_signal SWO_EN 1' where tracing is configured. +# issue the command 'ftdi set_signal SWO_EN 1' where tracing is configured. # To switch back to using the separate UART, SWO_EN needs to be disabled # before exiting OpenOCD, or the adapter replugged. -ftdi_layout_signal SWO_EN -nalias JTAG_EN +ftdi layout_signal SWO_EN -nalias JTAG_EN diff --git a/tcl/interface/ftdi/jtag-lock-pick_tiny_2.cfg b/tcl/interface/ftdi/jtag-lock-pick_tiny_2.cfg index 82eeaa7b5..3eefecf83 100644 --- a/tcl/interface/ftdi/jtag-lock-pick_tiny_2.cfg +++ b/tcl/interface/ftdi/jtag-lock-pick_tiny_2.cfg @@ -5,12 +5,12 @@ # adapter driver ftdi -ftdi_device_desc "JTAG-lock-pick Tiny 2" -ftdi_vid_pid 0x0403 0x8220 +ftdi device_desc "JTAG-lock-pick Tiny 2" +ftdi vid_pid 0x0403 0x8220 -ftdi_layout_init 0x8c28 0xff3b -ftdi_layout_signal SWD_EN -ndata 0x0020 -oe 0x2000 -ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 -ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 -ftdi_layout_signal SWDIO_OE -ndata 0x1000 -ftdi_layout_signal LED -ndata 0x8000 +ftdi layout_init 0x8c28 0xff3b +ftdi layout_signal SWD_EN -ndata 0x0020 -oe 0x2000 +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_signal SWDIO_OE -ndata 0x1000 +ftdi layout_signal LED -ndata 0x8000 diff --git a/tcl/interface/ftdi/jtagkey.cfg b/tcl/interface/ftdi/jtagkey.cfg index 06463ab91..511244b3f 100644 --- a/tcl/interface/ftdi/jtagkey.cfg +++ b/tcl/interface/ftdi/jtagkey.cfg @@ -5,9 +5,9 @@ # adapter driver ftdi -ftdi_device_desc "Amontec JTAGkey" -ftdi_vid_pid 0x0403 0xcff8 +ftdi device_desc "Amontec JTAGkey" +ftdi vid_pid 0x0403 0xcff8 -ftdi_layout_init 0x0c08 0x0f1b -ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 -ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/tcl/interface/ftdi/jtagkey2.cfg b/tcl/interface/ftdi/jtagkey2.cfg index ba151d3b5..aa33a7528 100644 --- a/tcl/interface/ftdi/jtagkey2.cfg +++ b/tcl/interface/ftdi/jtagkey2.cfg @@ -5,9 +5,9 @@ # adapter driver ftdi -ftdi_device_desc "Amontec JTAGkey-2" -ftdi_vid_pid 0x0403 0xcff8 +ftdi device_desc "Amontec JTAGkey-2" +ftdi vid_pid 0x0403 0xcff8 -ftdi_layout_init 0x0c08 0x0f1b -ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 -ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/tcl/interface/ftdi/jtagkey2p.cfg b/tcl/interface/ftdi/jtagkey2p.cfg index acb5047e9..dbfca66c4 100644 --- a/tcl/interface/ftdi/jtagkey2p.cfg +++ b/tcl/interface/ftdi/jtagkey2p.cfg @@ -5,9 +5,9 @@ # adapter driver ftdi -ftdi_device_desc "Amontec JTAGkey-2P" -ftdi_vid_pid 0x0403 0xcff8 +ftdi device_desc "Amontec JTAGkey-2P" +ftdi vid_pid 0x0403 0xcff8 -ftdi_layout_init 0x0c08 0x0f1b -ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 -ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/tcl/interface/ftdi/kt-link.cfg b/tcl/interface/ftdi/kt-link.cfg index 5fc5db9d0..112ecf154 100644 --- a/tcl/interface/ftdi/kt-link.cfg +++ b/tcl/interface/ftdi/kt-link.cfg @@ -5,12 +5,12 @@ # adapter driver ftdi -ftdi_device_desc "KT-LINK" -ftdi_vid_pid 0x0403 0xbbe2 +ftdi device_desc "KT-LINK" +ftdi vid_pid 0x0403 0xbbe2 -ftdi_layout_init 0x8c28 0xff3b -ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 -ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 -ftdi_layout_signal LED -data 0x8000 -ftdi_layout_signal SWD_EN -ndata 0x0020 -oe 0x2000 -ftdi_layout_signal SWDIO_OE -ndata 0x1000 +ftdi layout_init 0x8c28 0xff3b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_signal LED -data 0x8000 +ftdi layout_signal SWD_EN -ndata 0x0020 -oe 0x2000 +ftdi layout_signal SWDIO_OE -ndata 0x1000 diff --git a/tcl/interface/ftdi/lisa-l.cfg b/tcl/interface/ftdi/lisa-l.cfg index 4e52f7b7e..3da64a00e 100644 --- a/tcl/interface/ftdi/lisa-l.cfg +++ b/tcl/interface/ftdi/lisa-l.cfg @@ -10,11 +10,11 @@ echo "in ft2232.c. Please report your experience with this file to openocd-devel echo "mailing list, so it could be marked as working or fixed." adapter driver ftdi -ftdi_device_desc "Lisa/L" -ftdi_vid_pid 0x0403 0x6010 -ftdi_channel 1 +ftdi device_desc "Lisa/L" +ftdi vid_pid 0x0403 0x6010 +ftdi channel 1 -ftdi_layout_init 0x0008 0x180b -ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010 -ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040 -ftdi_layout_signal LED -data 0x1800 +ftdi layout_init 0x0008 0x180b +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nSRST -data 0x0040 -oe 0x0040 +ftdi layout_signal LED -data 0x1800 diff --git a/tcl/interface/ftdi/luminary-icdi.cfg b/tcl/interface/ftdi/luminary-icdi.cfg index 8bc783e92..08676a348 100644 --- a/tcl/interface/ftdi/luminary-icdi.cfg +++ b/tcl/interface/ftdi/luminary-icdi.cfg @@ -16,10 +16,10 @@ # adapter driver ftdi -ftdi_device_desc "Luminary Micro ICDI Board" -ftdi_vid_pid 0x0403 0xbcda +ftdi device_desc "Luminary Micro ICDI Board" +ftdi vid_pid 0x0403 0xbcda -ftdi_layout_init 0x00a8 0x00eb -ftdi_layout_signal nSRST -noe 0x0020 -ftdi_layout_signal SWD_EN -ndata 0x0080 -ftdi_layout_signal SWDIO_OE -data 0x0008 +ftdi layout_init 0x00a8 0x00eb +ftdi layout_signal nSRST -noe 0x0020 +ftdi layout_signal SWD_EN -ndata 0x0080 +ftdi layout_signal SWDIO_OE -data 0x0008 diff --git a/tcl/interface/ftdi/luminary-lm3s811.cfg b/tcl/interface/ftdi/luminary-lm3s811.cfg index aac915e34..90f454ef0 100644 --- a/tcl/interface/ftdi/luminary-lm3s811.cfg +++ b/tcl/interface/ftdi/luminary-lm3s811.cfg @@ -12,10 +12,10 @@ # adapter driver ftdi -ftdi_device_desc "LM3S811 Evaluation Board" -ftdi_vid_pid 0x0403 0xbcd9 +ftdi device_desc "LM3S811 Evaluation Board" +ftdi vid_pid 0x0403 0xbcd9 -ftdi_layout_init 0x0088 0x008b -ftdi_layout_signal nSRST -data 0x0020 -oe 0x0020 -ftdi_layout_signal SWD_EN -ndata 0x0080 -ftdi_layout_signal SWDIO_OE -data 0x0008 +ftdi layout_init 0x0088 0x008b +ftdi layout_signal nSRST -data 0x0020 -oe 0x0020 +ftdi layout_signal SWD_EN -ndata 0x0080 +ftdi layout_signal SWDIO_OE -data 0x0008 diff --git a/tcl/interface/ftdi/luminary.cfg b/tcl/interface/ftdi/luminary.cfg index 5e34f8cea..3258b214c 100644 --- a/tcl/interface/ftdi/luminary.cfg +++ b/tcl/interface/ftdi/luminary.cfg @@ -25,10 +25,10 @@ # adapter driver ftdi -ftdi_device_desc "Stellaris Evaluation Board" -ftdi_vid_pid 0x0403 0xbcd9 +ftdi device_desc "Stellaris Evaluation Board" +ftdi vid_pid 0x0403 0xbcd9 -ftdi_layout_init 0x00a8 0x00eb -ftdi_layout_signal nSRST -noe 0x0020 -ftdi_layout_signal SWD_EN -ndata 0x0080 -ftdi_layout_signal SWDIO_OE -data 0x0008 +ftdi layout_init 0x00a8 0x00eb +ftdi layout_signal nSRST -noe 0x0020 +ftdi layout_signal SWD_EN -ndata 0x0080 +ftdi layout_signal SWDIO_OE -data 0x0008 diff --git a/tcl/interface/ftdi/m53evk.cfg b/tcl/interface/ftdi/m53evk.cfg index 6597f2d30..2b7c43445 100644 --- a/tcl/interface/ftdi/m53evk.cfg +++ b/tcl/interface/ftdi/m53evk.cfg @@ -5,10 +5,10 @@ # adapter driver ftdi -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 -ftdi_channel 0 -ftdi_layout_init 0x0008 0x000b -ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010 -ftdi_layout_signal nSRST -data 0x0020 -oe 0x0020 +ftdi channel 0 +ftdi layout_init 0x0008 0x000b +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nSRST -data 0x0020 -oe 0x0020 diff --git a/tcl/interface/ftdi/mbftdi.cfg b/tcl/interface/ftdi/mbftdi.cfg index c0ff86574..a34390ba7 100644 --- a/tcl/interface/ftdi/mbftdi.cfg +++ b/tcl/interface/ftdi/mbftdi.cfg @@ -10,7 +10,7 @@ # adapter driver ftdi -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0008 0x000b +ftdi layout_init 0x0008 0x000b diff --git a/tcl/interface/ftdi/minimodule-swd.cfg b/tcl/interface/ftdi/minimodule-swd.cfg index 4bc331edb..15b007afb 100644 --- a/tcl/interface/ftdi/minimodule-swd.cfg +++ b/tcl/interface/ftdi/minimodule-swd.cfg @@ -38,17 +38,17 @@ adapter driver ftdi #Select your module type and channel -#ftdi_device_desc "FT2232H MiniModule" -ftdi_vid_pid 0x0403 0x6010 -#ftdi_channel 1 +#ftdi device_desc "FT2232H MiniModule" +ftdi vid_pid 0x0403 0x6010 +#ftdi channel 1 -#ftdi_device_desc "FT4232H MiniModule" -#ftdi_vid_pid 0x0403 0x6011 -#ftdi_channel 1 +#ftdi device_desc "FT4232H MiniModule" +#ftdi vid_pid 0x0403 0x6011 +#ftdi channel 1 -ftdi_layout_init 0x0000 0x000b -ftdi_layout_signal nSRST -data 0x0010 -oe 0x0010 -ftdi_layout_signal SWD_EN -data 0 -ftdi_layout_signal SWDIO_OE -data 0 +ftdi layout_init 0x0000 0x000b +ftdi layout_signal nSRST -data 0x0010 -oe 0x0010 +ftdi layout_signal SWD_EN -data 0 +ftdi layout_signal SWDIO_OE -data 0 transport select swd diff --git a/tcl/interface/ftdi/minimodule.cfg b/tcl/interface/ftdi/minimodule.cfg index 5dcce1fcf..6b2d60c07 100644 --- a/tcl/interface/ftdi/minimodule.cfg +++ b/tcl/interface/ftdi/minimodule.cfg @@ -5,12 +5,12 @@ # adapter driver ftdi -ftdi_device_desc "FT2232H MiniModule" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "FT2232H MiniModule" +ftdi vid_pid 0x0403 0x6010 # Every pin set as high impedance except TCK, TDI, TDO and TMS -ftdi_layout_init 0x0008 0x000b +ftdi layout_init 0x0008 0x000b # nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip) # This choice is arbitrary. Use other GPIO pin if desired. -ftdi_layout_signal nSRST -data 0x0020 -oe 0x0020 +ftdi layout_signal nSRST -data 0x0020 -oe 0x0020 diff --git a/tcl/interface/ftdi/minispartan6.cfg b/tcl/interface/ftdi/minispartan6.cfg index 97a6abe04..faf820d7a 100644 --- a/tcl/interface/ftdi/minispartan6.cfg +++ b/tcl/interface/ftdi/minispartan6.cfg @@ -3,12 +3,12 @@ adapter driver ftdi # The miniSpartan6+ sadly doesn't have a custom device description, so we just # have to hope you got it right. -#ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 +#ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 # interface 1 is the uart -ftdi_channel 0 +ftdi channel 0 # just TCK TDI TDO TMS, no reset -ftdi_layout_init 0x0008 0x000b +ftdi layout_init 0x0008 0x000b reset_config none # this generally works fast: the fpga can handle 30MHz, the spi flash can handle # 54MHz with simple read, no dummy cycles, and wait-for-write-completion diff --git a/tcl/interface/ftdi/miniwiggler.cfg b/tcl/interface/ftdi/miniwiggler.cfg index 6e53daede..ebaa97920 100644 --- a/tcl/interface/ftdi/miniwiggler.cfg +++ b/tcl/interface/ftdi/miniwiggler.cfg @@ -25,10 +25,10 @@ # adapter driver ftdi -ftdi_device_desc "DAS JDS miniWiggler V3.1" -ftdi_vid_pid 0x058b 0x0043 +ftdi device_desc "DAS JDS miniWiggler V3.1" +ftdi vid_pid 0x058b 0x0043 -ftdi_channel 0 -ftdi_layout_init 0x0008 0x001b -ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal nSRST -data 0x0200 -oe 0x0200 +ftdi channel 0 +ftdi layout_init 0x0008 0x001b +ftdi layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi layout_signal nSRST -data 0x0200 -oe 0x0200 diff --git a/tcl/interface/ftdi/neodb.cfg b/tcl/interface/ftdi/neodb.cfg index 1cfb3526c..426f5c4c7 100644 --- a/tcl/interface/ftdi/neodb.cfg +++ b/tcl/interface/ftdi/neodb.cfg @@ -5,10 +5,10 @@ # adapter driver ftdi -ftdi_device_desc "Debug Board for Neo1973" -ftdi_vid_pid 0x1457 0x5118 +ftdi device_desc "Debug Board for Neo1973" +ftdi vid_pid 0x1457 0x5118 -ftdi_layout_init 0x0508 0x0f1b -ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100 -ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400 -ftdi_layout_signal nNOR_WP -data 0x0010 -oe 0x0010 +ftdi layout_init 0x0508 0x0f1b +ftdi layout_signal nTRST -data 0x0200 -noe 0x0100 +ftdi layout_signal nSRST -data 0x0800 -noe 0x0400 +ftdi layout_signal nNOR_WP -data 0x0010 -oe 0x0010 diff --git a/tcl/interface/ftdi/ngxtech.cfg b/tcl/interface/ftdi/ngxtech.cfg index 3aa79ab31..962f25baa 100644 --- a/tcl/interface/ftdi/ngxtech.cfg +++ b/tcl/interface/ftdi/ngxtech.cfg @@ -11,9 +11,9 @@ echo "experience with this file to openocd-devel mailing list, so it could be ma echo "as working or fixed." adapter driver ftdi -ftdi_device_desc "NGX JTAG" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "NGX JTAG" +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0508 0x0f1b -ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100 -ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400 +ftdi layout_init 0x0508 0x0f1b +ftdi layout_signal nTRST -data 0x0200 -noe 0x0100 +ftdi layout_signal nSRST -data 0x0800 -noe 0x0400 diff --git a/tcl/interface/ftdi/olimex-arm-jtag-swd.cfg b/tcl/interface/ftdi/olimex-arm-jtag-swd.cfg index 2153fd65f..ace0df98d 100644 --- a/tcl/interface/ftdi/olimex-arm-jtag-swd.cfg +++ b/tcl/interface/ftdi/olimex-arm-jtag-swd.cfg @@ -5,5 +5,5 @@ transport select swd -ftdi_layout_signal SWD_EN -nalias nTRST -ftdi_layout_signal SWDIO_OE -alias TMS +ftdi layout_signal SWD_EN -nalias nTRST +ftdi layout_signal SWDIO_OE -alias TMS diff --git a/tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg b/tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg index c8e3befb7..ca014a4d4 100644 --- a/tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg +++ b/tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg @@ -5,10 +5,10 @@ # adapter driver ftdi -ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-OCD-H" -ftdi_vid_pid 0x15ba 0x002b +ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-OCD-H" +ftdi vid_pid 0x15ba 0x002b -ftdi_layout_init 0x0908 0x0b1b -ftdi_layout_signal nSRST -oe 0x0200 -ftdi_layout_signal nTRST -data 0x0100 -ftdi_layout_signal LED -data 0x0800 +ftdi layout_init 0x0908 0x0b1b +ftdi layout_signal nSRST -oe 0x0200 +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal LED -data 0x0800 diff --git a/tcl/interface/ftdi/olimex-arm-usb-ocd.cfg b/tcl/interface/ftdi/olimex-arm-usb-ocd.cfg index f9126d40d..6b9257583 100644 --- a/tcl/interface/ftdi/olimex-arm-usb-ocd.cfg +++ b/tcl/interface/ftdi/olimex-arm-usb-ocd.cfg @@ -5,10 +5,10 @@ # adapter driver ftdi -ftdi_device_desc "Olimex OpenOCD JTAG" -ftdi_vid_pid 0x15ba 0x0003 +ftdi device_desc "Olimex OpenOCD JTAG" +ftdi vid_pid 0x15ba 0x0003 -ftdi_layout_init 0x0c08 0x0f1b -ftdi_layout_signal nSRST -oe 0x0200 -ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 -ftdi_layout_signal LED -data 0x0800 +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nSRST -oe 0x0200 +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal LED -data 0x0800 diff --git a/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg b/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg index eac25b6da..98fe36784 100644 --- a/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg +++ b/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg @@ -5,10 +5,10 @@ # adapter driver ftdi -ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" -ftdi_vid_pid 0x15ba 0x002a +ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi vid_pid 0x15ba 0x002a -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 +ftdi layout_init 0x0808 0x0a1b +ftdi layout_signal nSRST -oe 0x0200 +ftdi layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi layout_signal LED -data 0x0800 diff --git a/tcl/interface/ftdi/olimex-jtag-tiny.cfg b/tcl/interface/ftdi/olimex-jtag-tiny.cfg index 4811f4dda..ebca496d2 100644 --- a/tcl/interface/ftdi/olimex-jtag-tiny.cfg +++ b/tcl/interface/ftdi/olimex-jtag-tiny.cfg @@ -5,10 +5,10 @@ # adapter driver ftdi -ftdi_device_desc "Olimex OpenOCD JTAG TINY" -ftdi_vid_pid 0x15ba 0x0004 +ftdi device_desc "Olimex OpenOCD JTAG TINY" +ftdi vid_pid 0x15ba 0x0004 -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 +ftdi layout_init 0x0808 0x0a1b +ftdi layout_signal nSRST -oe 0x0200 +ftdi layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi layout_signal LED -data 0x0800 diff --git a/tcl/interface/ftdi/oocdlink.cfg b/tcl/interface/ftdi/oocdlink.cfg index deba4a504..367112a6c 100644 --- a/tcl/interface/ftdi/oocdlink.cfg +++ b/tcl/interface/ftdi/oocdlink.cfg @@ -11,9 +11,9 @@ echo "experience with this file to openocd-devel mailing list, so it could be ma echo "as working or fixed." adapter driver ftdi -ftdi_device_desc "OOCDLink" -ftdi_vid_pid 0x0403 0xbaf8 +ftdi device_desc "OOCDLink" +ftdi vid_pid 0x0403 0xbaf8 -ftdi_layout_init 0x0508 0x0f1b -ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100 -ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400 +ftdi layout_init 0x0508 0x0f1b +ftdi layout_signal nTRST -data 0x0200 -noe 0x0100 +ftdi layout_signal nSRST -data 0x0800 -noe 0x0400 diff --git a/tcl/interface/ftdi/opendous_ftdi.cfg b/tcl/interface/ftdi/opendous_ftdi.cfg index 50f32fb3a..f212bf561 100644 --- a/tcl/interface/ftdi/opendous_ftdi.cfg +++ b/tcl/interface/ftdi/opendous_ftdi.cfg @@ -8,10 +8,10 @@ # adapter driver ftdi -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 -ftdi_channel 1 +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 +ftdi channel 1 -ftdi_layout_init 0x0c08 0x0f1b -ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 -ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/tcl/interface/ftdi/openocd-usb-hs.cfg b/tcl/interface/ftdi/openocd-usb-hs.cfg index 6f67689f6..d1a3ff0a2 100644 --- a/tcl/interface/ftdi/openocd-usb-hs.cfg +++ b/tcl/interface/ftdi/openocd-usb-hs.cfg @@ -5,9 +5,9 @@ # adapter driver ftdi -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0508 0x0f1b -ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100 -ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400 +ftdi layout_init 0x0508 0x0f1b +ftdi layout_signal nTRST -data 0x0200 -noe 0x0100 +ftdi layout_signal nSRST -data 0x0800 -noe 0x0400 diff --git a/tcl/interface/ftdi/openocd-usb.cfg b/tcl/interface/ftdi/openocd-usb.cfg index ed80a05d9..620d20436 100644 --- a/tcl/interface/ftdi/openocd-usb.cfg +++ b/tcl/interface/ftdi/openocd-usb.cfg @@ -5,9 +5,9 @@ # adapter driver ftdi -ftdi_device_desc "Dual RS232" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Dual RS232" +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0508 0x0f1b -ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100 -ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400 +ftdi layout_init 0x0508 0x0f1b +ftdi layout_signal nTRST -data 0x0200 -noe 0x0100 +ftdi layout_signal nSRST -data 0x0800 -noe 0x0400 diff --git a/tcl/interface/ftdi/openrd.cfg b/tcl/interface/ftdi/openrd.cfg index 535c5e896..88b2a6e51 100644 --- a/tcl/interface/ftdi/openrd.cfg +++ b/tcl/interface/ftdi/openrd.cfg @@ -5,10 +5,10 @@ # adapter driver ftdi -ftdi_device_desc "OpenRD JTAGKey FT2232D B" -ftdi_vid_pid 0x0403 0x9e90 -ftdi_channel 0 +ftdi device_desc "OpenRD JTAGKey FT2232D B" +ftdi vid_pid 0x0403 0x9e90 +ftdi channel 0 -ftdi_layout_init 0x0608 0x0f1b -ftdi_layout_signal nTRST -data 0x0200 -ftdi_layout_signal nSRST -noe 0x0400 +ftdi layout_init 0x0608 0x0f1b +ftdi layout_signal nTRST -data 0x0200 +ftdi layout_signal nSRST -noe 0x0400 diff --git a/tcl/interface/ftdi/pipistrello.cfg b/tcl/interface/ftdi/pipistrello.cfg index 2074924a3..11fcf077c 100644 --- a/tcl/interface/ftdi/pipistrello.cfg +++ b/tcl/interface/ftdi/pipistrello.cfg @@ -1,12 +1,12 @@ # http://pipistrello.saanlima.com/ # http://www.saanlima.com/download/pipistrello-v2.0/pipistrello_v2_schematic.pdf adapter driver ftdi -ftdi_device_desc "Pipistrello LX45" -ftdi_vid_pid 0x0403 0x6010 +ftdi device_desc "Pipistrello LX45" +ftdi vid_pid 0x0403 0x6010 # interface 1 is the uart -ftdi_channel 0 +ftdi channel 0 # just TCK TDI TDO TMS, no reset -ftdi_layout_init 0x0008 0x000b +ftdi layout_init 0x0008 0x000b reset_config none # this generally works fast: the fpga can handle 30MHz, the spi flash can handle # 54MHz with simple read, no dummy cycles, and wait-for-write-completion diff --git a/tcl/interface/ftdi/pls_spc5.cfg b/tcl/interface/ftdi/pls_spc5.cfg index 806f920fe..3b3c2d647 100644 --- a/tcl/interface/ftdi/pls_spc5.cfg +++ b/tcl/interface/ftdi/pls_spc5.cfg @@ -27,10 +27,10 @@ # adapter driver ftdi -ftdi_device_desc "PLS USB/JTAG Adapter for SPC5xxx" -ftdi_vid_pid 0x263d 0x4001 +ftdi device_desc "PLS USB/JTAG Adapter for SPC5xxx" +ftdi vid_pid 0x263d 0x4001 -ftdi_channel 0 -ftdi_layout_init 0x0008 0x000b -ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal nSRST -ndata 0x2000 -oe 0x2000 +ftdi channel 0 +ftdi layout_init 0x0008 0x000b +ftdi layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi layout_signal nSRST -ndata 0x2000 -oe 0x2000 diff --git a/tcl/interface/ftdi/redbee-econotag.cfg b/tcl/interface/ftdi/redbee-econotag.cfg index b6f6d23ba..35bedfa7e 100644 --- a/tcl/interface/ftdi/redbee-econotag.cfg +++ b/tcl/interface/ftdi/redbee-econotag.cfg @@ -14,8 +14,8 @@ echo "Please report your experience with this file to openocd-devel mailing list echo "so it could be marked as working or fixed." adapter driver ftdi -ftdi_vid_pid 0x0403 0x6010 +ftdi vid_pid 0x0403 0x6010 -ftdi_layout_init 0x0c08 0x0c2b -ftdi_layout_signal nTRST -data 0x0800 -ftdi_layout_signal nSRST -data 0x0400 +ftdi layout_init 0x0c08 0x0c2b +ftdi layout_signal nTRST -data 0x0800 +ftdi layout_signal nSRST -data 0x0400 diff --git a/tcl/interface/ftdi/redbee-usb.cfg b/tcl/interface/ftdi/redbee-usb.cfg index 52ab93e02..a57176610 100644 --- a/tcl/interface/ftdi/redbee-usb.cfg +++ b/tcl/interface/ftdi/redbee-usb.cfg @@ -14,9 +14,9 @@ echo "Please report your experience with this file to openocd-devel mailing list echo "so it could be marked as working or fixed." adapter driver ftdi -ftdi_vid_pid 0x0403 0x6010 -ftdi_channel 1 +ftdi vid_pid 0x0403 0x6010 +ftdi channel 1 -ftdi_layout_init 0x0c08 0x0c2b -ftdi_layout_signal nTRST -data 0x0800 -ftdi_layout_signal nSRST -data 0x0400 +ftdi layout_init 0x0c08 0x0c2b +ftdi layout_signal nTRST -data 0x0800 +ftdi layout_signal nSRST -data 0x0400 diff --git a/tcl/interface/ftdi/rowley-cc-arm-swd.cfg b/tcl/interface/ftdi/rowley-cc-arm-swd.cfg index 9a96dbd92..fb416db56 100644 --- a/tcl/interface/ftdi/rowley-cc-arm-swd.cfg +++ b/tcl/interface/ftdi/rowley-cc-arm-swd.cfg @@ -6,5 +6,5 @@ transport select swd -ftdi_layout_signal SWD_EN -nalias nTRST -ftdi_layout_signal SWDIO_OE -alias TMS +ftdi layout_signal SWD_EN -nalias nTRST +ftdi layout_signal SWDIO_OE -alias TMS diff --git a/tcl/interface/ftdi/sheevaplug.cfg b/tcl/interface/ftdi/sheevaplug.cfg index e58235032..5929453c1 100644 --- a/tcl/interface/ftdi/sheevaplug.cfg +++ b/tcl/interface/ftdi/sheevaplug.cfg @@ -5,10 +5,10 @@ # adapter driver ftdi -ftdi_device_desc "SheevaPlug JTAGKey FT2232D B" -ftdi_vid_pid 0x9e88 0x9e8f -ftd... [truncated message content] |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-10 14:32:39
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 65c9653cc768f77a5e8cf2af73e0f40d614bdec2 (commit) from c819444e9665888a45fcdaf6691737329a380d00 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 65c9653cc768f77a5e8cf2af73e0f40d614bdec2 Author: Jan Matyas <ma...@co...> Date: Thu Jun 3 16:26:37 2021 +0200 target: add support for 64bit data in mem2array and array2mem - Added support for reading and writing 64-bit data items using TCL commands "mem2array" and "array2mem". Until now, data items only up to 32 bits were supportd. - Cleaned up functions target_array2mem() and target_mem2array(), especially data types of variables and variable declarations (scope). Change-Id: Ia0ba427804f8fd8d7568f12714ab36984d6d5e24 Signed-off-by: Jan Matyas <ma...@co...> Reviewed-on: http://openocd.zylin.com/6286 Tested-by: jenkins Reviewed-by: Marc Schink <de...@za...> Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/doc/openocd.texi b/doc/openocd.texi index daf0a6aa1..1eebe1425 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4821,8 +4821,8 @@ They are not otherwise documented here. @deffn {Command} {$target_name array2mem} arrayname width address count @deffnx {Command} {$target_name mem2array} arrayname width address count These provide an efficient script-oriented interface to memory. -The @code{array2mem} primitive writes bytes, halfwords, or words; -while @code{mem2array} reads them. +The @code{array2mem} primitive writes bytes, halfwords, words +or double-words; while @code{mem2array} reads them. In both cases, the TCL side uses an array, and the target side uses raw memory. @@ -4835,7 +4835,7 @@ and neither store nor return those values. @itemize @item @var{arrayname} ... is the name of an array variable -@item @var{width} ... is 8/16/32 - indicating the memory access size +@item @var{width} ... is 8/16/32/64 - indicating the memory access size @item @var{address} ... is the target memory address @item @var{count} ... is the number of elements to process @end itemize diff --git a/src/target/target.c b/src/target/target.c index 6b53ebd98..3772f8e3e 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -4372,7 +4372,7 @@ COMMAND_HANDLER(handle_profile_command) return retval; } -static int new_int_array_element(Jim_Interp *interp, const char *varname, int idx, uint32_t val) +static int new_u64_array_element(Jim_Interp *interp, const char *varname, int idx, uint64_t val) { char *namebuf; Jim_Obj *nameObjPtr, *valObjPtr; @@ -4383,7 +4383,8 @@ static int new_int_array_element(Jim_Interp *interp, const char *varname, int id return JIM_ERR; nameObjPtr = Jim_NewStringObj(interp, namebuf, -1); - valObjPtr = Jim_NewIntObj(interp, val); + jim_wide wide_val = val; + valObjPtr = Jim_NewWideObj(interp, wide_val); if (!nameObjPtr || !valObjPtr) { free(namebuf); return JIM_ERR; @@ -4418,68 +4419,65 @@ static int jim_mem2array(Jim_Interp *interp, int argc, Jim_Obj *const *argv) static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, Jim_Obj *const *argv) { - long l; - jim_wide wide_addr; - uint32_t width; - int len; - target_addr_t addr; - uint32_t count; - uint32_t v; - const char *varname; - const char *phys; - bool is_phys; - int n, e, retval; - uint32_t i; + int e; - /* argv[1] = name of array to receive the data - * argv[2] = desired width - * argv[3] = memory address - * argv[4] = count of times to read + /* argv[0] = name of array to receive the data + * argv[1] = desired element width in bits + * argv[2] = memory address + * argv[3] = count of times to read + * argv[4] = optional "phys" */ - if (argc < 4 || argc > 5) { Jim_WrongNumArgs(interp, 0, argv, "varname width addr nelems [phys]"); return JIM_ERR; } - varname = Jim_GetString(argv[0], &len); - /* given "foo" get space for worse case "foo(%d)" .. add 20 */ + /* Arg 0: Name of the array variable */ + const char *varname = Jim_GetString(argv[0], NULL); + + /* Arg 1: Bit width of one element */ + long l; e = Jim_GetLong(interp, argv[1], &l); - width = l; if (e != JIM_OK) return e; + const unsigned int width_bits = l; + + if (width_bits != 8 && + width_bits != 16 && + width_bits != 32 && + width_bits != 64) { + Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); + Jim_AppendStrings(interp, Jim_GetResult(interp), + "Invalid width param. Must be one of: 8, 16, 32 or 64.", NULL); + return JIM_ERR; + } + const unsigned int width = width_bits / 8; + /* Arg 2: Memory address */ + jim_wide wide_addr; e = Jim_GetWide(interp, argv[2], &wide_addr); - addr = (target_addr_t)wide_addr; if (e != JIM_OK) return e; + target_addr_t addr = (target_addr_t)wide_addr; + + /* Arg 3: Number of elements to read */ e = Jim_GetLong(interp, argv[3], &l); - len = l; if (e != JIM_OK) return e; - is_phys = false; + size_t len = l; + + /* Arg 4: phys */ + bool is_phys = false; if (argc > 4) { - phys = Jim_GetString(argv[4], &n); - if (!strncmp(phys, "phys", n)) + int str_len = 0; + const char *phys = Jim_GetString(argv[4], &str_len); + if (!strncmp(phys, "phys", str_len)) is_phys = true; else return JIM_ERR; } - switch (width) { - case 8: - width = 1; - break; - case 16: - width = 2; - break; - case 32: - width = 4; - break; - default: - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), "Invalid width param, must be 8/16/32", NULL); - return JIM_ERR; - } + + /* Argument checks */ if (len == 0) { Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); Jim_AppendStrings(interp, Jim_GetResult(interp), "mem2array: zero width read?", NULL); @@ -4490,17 +4488,18 @@ static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, Jim_AppendStrings(interp, Jim_GetResult(interp), "mem2array: addr + len - wraps to zero?", NULL); return JIM_ERR; } - /* absurd transfer size? */ if (len > 65536) { Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), "mem2array: absurd > 64K item request", NULL); + Jim_AppendStrings(interp, Jim_GetResult(interp), + "mem2array: too large read request, exceeds 64K items", NULL); return JIM_ERR; } if ((width == 1) || ((width == 2) && ((addr & 1) == 0)) || - ((width == 4) && ((addr & 3) == 0))) { - /* all is well */ + ((width == 4) && ((addr & 3) == 0)) || + ((width == 8) && ((addr & 7) == 0))) { + /* alignment correct */ } else { char buf[100]; Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); @@ -4514,9 +4513,9 @@ static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, /* Transfer loop */ /* index counter */ - n = 0; + size_t idx = 0; - size_t buffersize = 4096; + const size_t buffersize = 4096; uint8_t *buffer = malloc(buffersize); if (buffer == NULL) return JIM_ERR; @@ -4525,29 +4524,31 @@ static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, e = JIM_OK; while (len) { /* Slurp... in buffer size chunks */ + const unsigned int max_chunk_len = buffersize / width; + const size_t chunk_len = MIN(len, max_chunk_len); /* in elements.. */ - count = len; /* in objects.. */ - if (count > (buffersize / width)) - count = (buffersize / width); - + int retval; if (is_phys) - retval = target_read_phys_memory(target, addr, width, count, buffer); + retval = target_read_phys_memory(target, addr, width, chunk_len, buffer); else - retval = target_read_memory(target, addr, width, count, buffer); + retval = target_read_memory(target, addr, width, chunk_len, buffer); if (retval != ERROR_OK) { /* BOO !*/ - LOG_ERROR("mem2array: Read @ " TARGET_ADDR_FMT ", w=%" PRIu32 ", cnt=%" PRIu32 ", failed", + LOG_ERROR("mem2array: Read @ " TARGET_ADDR_FMT ", w=%u, cnt=%zu, failed", addr, width, - count); + chunk_len); Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); Jim_AppendStrings(interp, Jim_GetResult(interp), "mem2array: cannot read memory", NULL); e = JIM_ERR; break; } else { - v = 0; /* shut up gcc */ - for (i = 0; i < count ; i++, n++) { + for (size_t i = 0; i < chunk_len ; i++, idx++) { + uint64_t v = 0; switch (width) { + case 8: + v = target_buffer_get_u64(target, &buffer[i*width]); + break; case 4: v = target_buffer_get_u32(target, &buffer[i*width]); break; @@ -4558,10 +4559,10 @@ static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, v = buffer[i] & 0x0ff; break; } - new_int_array_element(interp, varname, n, v); + new_u64_array_element(interp, varname, idx, v); } - len -= count; - addr += count * width; + len -= chunk_len; + addr += chunk_len * width; } } @@ -4572,33 +4573,28 @@ static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, return e; } -static int get_int_array_element(Jim_Interp *interp, const char *varname, int idx, uint32_t *val) +static int get_u64_array_element(Jim_Interp *interp, const char *varname, size_t idx, uint64_t *val) { - char *namebuf; - Jim_Obj *nameObjPtr, *valObjPtr; - int result; - long l; - - namebuf = alloc_printf("%s(%d)", varname, idx); + char *namebuf = alloc_printf("%s(%zu)", varname, idx); if (!namebuf) return JIM_ERR; - nameObjPtr = Jim_NewStringObj(interp, namebuf, -1); + Jim_Obj *nameObjPtr = Jim_NewStringObj(interp, namebuf, -1); if (!nameObjPtr) { free(namebuf); return JIM_ERR; } Jim_IncrRefCount(nameObjPtr); - valObjPtr = Jim_GetVariable(interp, nameObjPtr, JIM_ERRMSG); + Jim_Obj *valObjPtr = Jim_GetVariable(interp, nameObjPtr, JIM_ERRMSG); Jim_DecrRefCount(interp, nameObjPtr); free(namebuf); if (valObjPtr == NULL) return JIM_ERR; - result = Jim_GetLong(interp, valObjPtr, &l); - /* printf("%s(%d) => 0%08x\n", varname, idx, val); */ - *val = l; + jim_wide wide_val; + int result = Jim_GetWide(interp, valObjPtr, &wide_val); + *val = wide_val; return result; } @@ -4622,92 +4618,91 @@ static int jim_array2mem(Jim_Interp *interp, int argc, Jim_Obj *const *argv) static int target_array2mem(Jim_Interp *interp, struct target *target, int argc, Jim_Obj *const *argv) { - long l; - jim_wide wide_addr; - uint32_t width; - int len; - target_addr_t addr; - uint32_t count; - uint32_t v; - const char *varname; - const char *phys; - bool is_phys; - int n, e, retval; - uint32_t i; + int e; - /* argv[1] = name of array to get the data - * argv[2] = desired width - * argv[3] = memory address - * argv[4] = count to write + /* argv[0] = name of array from which to read the data + * argv[1] = desired element width in bits + * argv[2] = memory address + * argv[3] = number of elements to write + * argv[4] = optional "phys" */ if (argc < 4 || argc > 5) { Jim_WrongNumArgs(interp, 0, argv, "varname width addr nelems [phys]"); return JIM_ERR; } - varname = Jim_GetString(argv[0], &len); - /* given "foo" get space for worse case "foo(%d)" .. add 20 */ + /* Arg 0: Name of the array variable */ + const char *varname = Jim_GetString(argv[0], NULL); + + /* Arg 1: Bit width of one element */ + long l; e = Jim_GetLong(interp, argv[1], &l); - width = l; if (e != JIM_OK) return e; + const unsigned int width_bits = l; + + if (width_bits != 8 && + width_bits != 16 && + width_bits != 32 && + width_bits != 64) { + Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); + Jim_AppendStrings(interp, Jim_GetResult(interp), + "Invalid width param. Must be one of: 8, 16, 32 or 64.", NULL); + return JIM_ERR; + } + const unsigned int width = width_bits / 8; + /* Arg 2: Memory address */ + jim_wide wide_addr; e = Jim_GetWide(interp, argv[2], &wide_addr); - addr = (target_addr_t)wide_addr; if (e != JIM_OK) return e; + target_addr_t addr = (target_addr_t)wide_addr; + + /* Arg 3: Number of elements to write */ e = Jim_GetLong(interp, argv[3], &l); - len = l; if (e != JIM_OK) return e; - is_phys = false; + size_t len = l; + + /* Arg 4: Phys */ + bool is_phys = false; if (argc > 4) { - phys = Jim_GetString(argv[4], &n); - if (!strncmp(phys, "phys", n)) + int str_len = 0; + const char *phys = Jim_GetString(argv[4], &str_len); + if (!strncmp(phys, "phys", str_len)) is_phys = true; else return JIM_ERR; } - switch (width) { - case 8: - width = 1; - break; - case 16: - width = 2; - break; - case 32: - width = 4; - break; - default: - Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), - "Invalid width param, must be 8/16/32", NULL); - return JIM_ERR; - } + + /* Argument checks */ if (len == 0) { Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); Jim_AppendStrings(interp, Jim_GetResult(interp), "array2mem: zero width read?", NULL); return JIM_ERR; } + if ((addr + (len * width)) < addr) { Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); Jim_AppendStrings(interp, Jim_GetResult(interp), "array2mem: addr + len - wraps to zero?", NULL); return JIM_ERR; } - /* absurd transfer size? */ + if (len > 65536) { Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); Jim_AppendStrings(interp, Jim_GetResult(interp), - "array2mem: absurd > 64K item request", NULL); + "array2mem: too large memory write request, exceeds 64K items", NULL); return JIM_ERR; } if ((width == 1) || ((width == 2) && ((addr & 1) == 0)) || - ((width == 4) && ((addr & 3) == 0))) { - /* all is well */ + ((width == 4) && ((addr & 3) == 0)) || + ((width == 8) && ((addr & 7) == 0))) { + /* alignment correct */ } else { char buf[100]; Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); @@ -4720,27 +4715,34 @@ static int target_array2mem(Jim_Interp *interp, struct target *target, /* Transfer loop */ - /* index counter */ - n = 0; /* assume ok */ e = JIM_OK; - size_t buffersize = 4096; + const size_t buffersize = 4096; uint8_t *buffer = malloc(buffersize); if (buffer == NULL) return JIM_ERR; + /* index counter */ + size_t idx = 0; + while (len) { /* Slurp... in buffer size chunks */ + const unsigned int max_chunk_len = buffersize / width; - count = len; /* in objects.. */ - if (count > (buffersize / width)) - count = (buffersize / width); + const size_t chunk_len = MIN(len, max_chunk_len); /* in elements.. */ - v = 0; /* shut up gcc */ - for (i = 0; i < count; i++, n++) { - get_int_array_element(interp, varname, n, &v); + /* Fill the buffer */ + for (size_t i = 0; i < chunk_len; i++, idx++) { + uint64_t v = 0; + if (get_u64_array_element(interp, varname, idx, &v) != JIM_OK) { + free(buffer); + return JIM_ERR; + } switch (width) { + case 8: + target_buffer_set_u64(target, &buffer[i * width], v); + break; case 4: target_buffer_set_u32(target, &buffer[i * width], v); break; @@ -4752,24 +4754,26 @@ static int target_array2mem(Jim_Interp *interp, struct target *target, break; } } - len -= count; + len -= chunk_len; + /* Write the buffer to memory */ + int retval; if (is_phys) - retval = target_write_phys_memory(target, addr, width, count, buffer); + retval = target_write_phys_memory(target, addr, width, chunk_len, buffer); else - retval = target_write_memory(target, addr, width, count, buffer); + retval = target_write_memory(target, addr, width, chunk_len, buffer); if (retval != ERROR_OK) { /* BOO !*/ - LOG_ERROR("array2mem: Write @ " TARGET_ADDR_FMT ", w=%" PRIu32 ", cnt=%" PRIu32 ", failed", + LOG_ERROR("array2mem: Write @ " TARGET_ADDR_FMT ", w=%u, cnt=%zu, failed", addr, width, - count); + chunk_len); Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); Jim_AppendStrings(interp, Jim_GetResult(interp), "array2mem: cannot read memory", NULL); e = JIM_ERR; break; } - addr += count * width; + addr += chunk_len * width; } free(buffer); ----------------------------------------------------------------------- Summary of changes: doc/openocd.texi | 6 +- src/target/target.c | 268 ++++++++++++++++++++++++++-------------------------- 2 files changed, 139 insertions(+), 135 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-10 14:31:54
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via c819444e9665888a45fcdaf6691737329a380d00 (commit) from 6f439e203289c517360fdc061ca9497fc4c530b8 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit c819444e9665888a45fcdaf6691737329a380d00 Author: Daniel Goehring <dgo...@os...> Date: Tue Apr 6 22:33:13 2021 -0400 target: add 64-bit address array command support Add 64-bit address support to the target mem2array and array2mem commands Change-Id: Ibdcc076ca5581f4fd87e92318aab33907e22d6ce Signed-off-by: Daniel Goehring <dgo...@os...> Reviewed-on: http://openocd.zylin.com/6246 Tested-by: jenkins Reviewed-by: Jan Matyas <ma...@co...> Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/src/target/target.c b/src/target/target.c index 476986c24..6b53ebd98 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -4419,9 +4419,10 @@ static int jim_mem2array(Jim_Interp *interp, int argc, Jim_Obj *const *argv) static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, Jim_Obj *const *argv) { long l; + jim_wide wide_addr; uint32_t width; int len; - uint32_t addr; + target_addr_t addr; uint32_t count; uint32_t v; const char *varname; @@ -4448,8 +4449,8 @@ static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, if (e != JIM_OK) return e; - e = Jim_GetLong(interp, argv[2], &l); - addr = l; + e = Jim_GetWide(interp, argv[2], &wide_addr); + addr = (target_addr_t)wide_addr; if (e != JIM_OK) return e; e = Jim_GetLong(interp, argv[3], &l); @@ -4503,7 +4504,7 @@ static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, } else { char buf[100]; Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - sprintf(buf, "mem2array address: 0x%08" PRIx32 " is not aligned for %" PRIu32 " byte reads", + sprintf(buf, "mem2array address: " TARGET_ADDR_FMT " is not aligned for %" PRIu32 " byte reads", addr, width); Jim_AppendStrings(interp, Jim_GetResult(interp), buf, NULL); @@ -4535,7 +4536,7 @@ static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, retval = target_read_memory(target, addr, width, count, buffer); if (retval != ERROR_OK) { /* BOO !*/ - LOG_ERROR("mem2array: Read @ 0x%08" PRIx32 ", w=%" PRIu32 ", cnt=%" PRIu32 ", failed", + LOG_ERROR("mem2array: Read @ " TARGET_ADDR_FMT ", w=%" PRIu32 ", cnt=%" PRIu32 ", failed", addr, width, count); @@ -4622,9 +4623,10 @@ static int target_array2mem(Jim_Interp *interp, struct target *target, int argc, Jim_Obj *const *argv) { long l; + jim_wide wide_addr; uint32_t width; int len; - uint32_t addr; + target_addr_t addr; uint32_t count; uint32_t v; const char *varname; @@ -4650,8 +4652,8 @@ static int target_array2mem(Jim_Interp *interp, struct target *target, if (e != JIM_OK) return e; - e = Jim_GetLong(interp, argv[2], &l); - addr = l; + e = Jim_GetWide(interp, argv[2], &wide_addr); + addr = (target_addr_t)wide_addr; if (e != JIM_OK) return e; e = Jim_GetLong(interp, argv[3], &l); @@ -4709,7 +4711,7 @@ static int target_array2mem(Jim_Interp *interp, struct target *target, } else { char buf[100]; Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - sprintf(buf, "array2mem address: 0x%08" PRIx32 " is not aligned for %" PRIu32 " byte reads", + sprintf(buf, "array2mem address: " TARGET_ADDR_FMT " is not aligned for %" PRIu32 " byte reads", addr, width); Jim_AppendStrings(interp, Jim_GetResult(interp), buf, NULL); @@ -4758,7 +4760,7 @@ static int target_array2mem(Jim_Interp *interp, struct target *target, retval = target_write_memory(target, addr, width, count, buffer); if (retval != ERROR_OK) { /* BOO !*/ - LOG_ERROR("array2mem: Write @ 0x%08" PRIx32 ", w=%" PRIu32 ", cnt=%" PRIu32 ", failed", + LOG_ERROR("array2mem: Write @ " TARGET_ADDR_FMT ", w=%" PRIu32 ", cnt=%" PRIu32 ", failed", addr, width, count); ----------------------------------------------------------------------- Summary of changes: src/target/target.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-10 14:31:06
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 6f439e203289c517360fdc061ca9497fc4c530b8 (commit) from 4487270ea434782f25f790892c5f7d03b7cbe243 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 6f439e203289c517360fdc061ca9497fc4c530b8 Author: Jan Matyas <ma...@co...> Date: Fri Jun 4 10:44:44 2021 +0200 target/semihosting: Fix of close(): Never close standard streams This change fixes behavior of the SEMIHOSTING_SYS_CLOSE operation. It ensures that OpenOCD's own stdin/stdout/stderr streams are never closed, not even if the target requests it via semihosting. Change-Id: Ia85af5963d1a3516284fd834f7197369a8fb268c Signed-off-by: Jan Matyas <ma...@co...> Reviewed-on: http://openocd.zylin.com/6291 Tested-by: jenkins Reviewed-by: Tim Newsome <ti...@si...> Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/src/target/semihosting_common.c b/src/target/semihosting_common.c index bfb1ecaa7..ffed7350e 100644 --- a/src/target/semihosting_common.c +++ b/src/target/semihosting_common.c @@ -226,18 +226,28 @@ int semihosting_common(struct target *target) return retval; else { int fd = semihosting_get_field(target, 0, fields); - if (semihosting->is_fileio) { - if (fd == 0 || fd == 1 || fd == 2) { + /* Do not allow to close OpenOCD's own standard streams */ + if (fd == 0 || fd == 1 || fd == 2) { + LOG_DEBUG("ignoring semihosting attempt to close %s", + (fd == 0) ? "stdin" : + (fd == 1) ? "stdout" : "stderr"); + /* Just pretend success */ + if (semihosting->is_fileio) { semihosting->result = 0; - break; + } else { + semihosting->result = 0; + semihosting->sys_errno = 0; } + break; + } + /* Close the descriptor */ + if (semihosting->is_fileio) { semihosting->hit_fileio = true; fileio_info->identifier = "close"; fileio_info->param_1 = fd; } else { semihosting->result = close(fd); semihosting->sys_errno = errno; - LOG_DEBUG("close(%d)=%d", fd, (int)semihosting->result); } } ----------------------------------------------------------------------- Summary of changes: src/target/semihosting_common.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-10 14:29:34
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 4487270ea434782f25f790892c5f7d03b7cbe243 (commit) from 554878b9d3f3d5edc640c27a99c607567933b646 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 4487270ea434782f25f790892c5f7d03b7cbe243 Author: Jan Matyas <ma...@co...> Date: Fri Jun 4 11:41:36 2021 +0200 target/semihosting: Capture errno in SEMIHOSTING_SYS_ISTTY Capture the value of "errno" in semihosting isatty() call, as is done in other syscalls. Change-Id: I41b72175635f06c000536f583e3efa30fb57379e Signed-off-by: Jan Matyas <ma...@co...> Reviewed-on: http://openocd.zylin.com/6292 Tested-by: jenkins Reviewed-by: Tim Newsome <ti...@si...> Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/src/target/semihosting_common.c b/src/target/semihosting_common.c index 61a69d1bd..bfb1ecaa7 100644 --- a/src/target/semihosting_common.c +++ b/src/target/semihosting_common.c @@ -615,6 +615,7 @@ int semihosting_common(struct target *target) return retval; int fd = semihosting_get_field(target, 0, fields); semihosting->result = isatty(fd); + semihosting->sys_errno = errno; LOG_DEBUG("isatty(%d)=%d", fd, (int)semihosting->result); } break; ----------------------------------------------------------------------- Summary of changes: src/target/semihosting_common.c | 1 + 1 file changed, 1 insertion(+) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-10 14:28:31
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 554878b9d3f3d5edc640c27a99c607567933b646 (commit) from f723e94f525d2de53047ce88d576c0ec72d95e21 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 554878b9d3f3d5edc640c27a99c607567933b646 Author: Patrick Stewart <pa...@rf...> Date: Thu Jul 6 17:32:31 2017 +0100 tcl/interface/ftdi: Fix Digilent JTAG-SMT2 config Drive the output enable for TMS and TDI Change-Id: Ib23afd2f5149d4ce402d88781e68dcf0f074f395 Signed-off-by: Patrick Stewart <pa...@gm...> Reviewed-on: http://openocd.zylin.com/4179 Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> Reviewed-by: Paul Fertser <fer...@gm...> diff --git a/tcl/interface/ftdi/digilent_jtag_smt2.cfg b/tcl/interface/ftdi/digilent_jtag_smt2.cfg index 493ed6af5..55f278bdc 100644 --- a/tcl/interface/ftdi/digilent_jtag_smt2.cfg +++ b/tcl/interface/ftdi/digilent_jtag_smt2.cfg @@ -10,7 +10,7 @@ adapter driver ftdi ftdi_vid_pid 0x0403 0x6014 -ftdi_layout_init 0x2088 0x3f8b +ftdi_layout_init 0x20e8 0x3feb ftdi_layout_signal nSRST -data 0x2000 ftdi_layout_signal GPIO2 -data 0x2000 ftdi_layout_signal GPIO1 -data 0x0200 ----------------------------------------------------------------------- Summary of changes: tcl/interface/ftdi/digilent_jtag_smt2.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-10 14:27:58
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via f723e94f525d2de53047ce88d576c0ec72d95e21 (commit) from 28c91b8f80937e6ec6521496f363038d9a5f9a04 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit f723e94f525d2de53047ce88d576c0ec72d95e21 Author: Andreas Fritiofson <and...@gm...> Date: Sat Aug 13 10:48:53 2016 +0200 config/ftdi: Add tristate capability to sheevaplug config The legacy ft2232 driver suggests that the adapter has tristate buffers on both nSRST and nTRST, even though they were not used as such. Change-Id: I971692ea6b3439ac93311b89877825a5cc21df46 Signed-off-by: Andreas Fritiofson <and...@gm...> Reviewed-on: http://openocd.zylin.com/3663 Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/tcl/interface/ftdi/sheevaplug.cfg b/tcl/interface/ftdi/sheevaplug.cfg index d4ec72e66..e58235032 100644 --- a/tcl/interface/ftdi/sheevaplug.cfg +++ b/tcl/interface/ftdi/sheevaplug.cfg @@ -10,5 +10,5 @@ ftdi_vid_pid 0x9e88 0x9e8f ftdi_channel 0 ftdi_layout_init 0x0608 0x0f1b -ftdi_layout_signal nTRST -data 0x0200 -ftdi_layout_signal nSRST -noe 0x0400 +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100 +ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400 ----------------------------------------------------------------------- Summary of changes: tcl/interface/ftdi/sheevaplug.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-02 16:16:08
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 28c91b8f80937e6ec6521496f363038d9a5f9a04 (commit) from 81b59e876c249a7ec4eb720e8c74f8f310a59f37 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 28c91b8f80937e6ec6521496f363038d9a5f9a04 Author: Florian Fainelli <f.f...@gm...> Date: Mon Jun 28 09:46:12 2021 -0700 tcl: Update Flyswatter product links The Flyswatter URL is dead and requires us to use web.archive.org since the product is discontinued. The Flyswatter 2 is still active and accessible at a different URL. Change-Id: Ib2d9de70a9728b0f0ef73f5e479bca81f958442c Signed-off-by: Florian Fainelli <f.f...@gm...> Reviewed-on: http://openocd.zylin.com/6337 Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/tcl/interface/ftdi/flyswatter.cfg b/tcl/interface/ftdi/flyswatter.cfg index 5e9d4816d..0b849ad53 100644 --- a/tcl/interface/ftdi/flyswatter.cfg +++ b/tcl/interface/ftdi/flyswatter.cfg @@ -1,7 +1,7 @@ # # TinCanTools Flyswatter # -# http://www.tincantools.com/product.php?productid=16134 +# http://web.archive.org/web/20150419072034/http://www.tincantools.com/JTAG/Flyswatter.html # adapter driver ftdi diff --git a/tcl/interface/ftdi/flyswatter2.cfg b/tcl/interface/ftdi/flyswatter2.cfg index 45dd0bacb..4f4a1f819 100644 --- a/tcl/interface/ftdi/flyswatter2.cfg +++ b/tcl/interface/ftdi/flyswatter2.cfg @@ -1,7 +1,7 @@ # # TinCanTools Flyswatter2 # -# http://www.tincantools.com/product.php?productid=16153 +# https://www.tincantools.com/product/flyswatter2/ # adapter driver ftdi ----------------------------------------------------------------------- Summary of changes: tcl/interface/ftdi/flyswatter.cfg | 2 +- tcl/interface/ftdi/flyswatter2.cfg | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-02 16:15:31
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 81b59e876c249a7ec4eb720e8c74f8f310a59f37 (commit) via b1a8082f59c0fe43a865ff5478f4c73090a12c9e (commit) via aad4f1c1f5a296098b4cad6bd3491d1a68844989 (commit) from 6ad89d61af681e11960082a906357d8e8c3396a1 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 81b59e876c249a7ec4eb720e8c74f8f310a59f37 Author: Marc Schink <de...@za...> Date: Mon Jun 28 13:11:37 2021 +0200 target/cortex_a: Replace printf() with LOG_DEBUG() Change-Id: I38fa8e21959b398033741cbd779b632d572c7ce4 Signed-off-by: Marc Schink <de...@za...> Reviewed-on: http://openocd.zylin.com/6336 Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 2e810b5db..a538766ed 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -1427,7 +1427,7 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoi (brp_list[brp_1].type != BRP_CONTEXT)) && (brp_1 < cortex_a->brp_num)) brp_1++; - printf("brp(CTX) found num: %d\n", brp_1); + LOG_DEBUG("brp(CTX) found num: %d", brp_1); if (brp_1 >= cortex_a->brp_num) { LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); return ERROR_FAIL; @@ -1437,7 +1437,7 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoi (brp_list[brp_2].type != BRP_NORMAL)) && (brp_2 < cortex_a->brp_num)) brp_2++; - printf("brp(IVA) found num: %d\n", brp_2); + LOG_DEBUG("brp(IVA) found num: %d", brp_2); if (brp_2 >= cortex_a->brp_num) { LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); return ERROR_FAIL; commit b1a8082f59c0fe43a865ff5478f4c73090a12c9e Author: Marc Schink <de...@za...> Date: Mon Jun 28 13:10:51 2021 +0200 target/aarch64: Replace printf() with LOG_DEBUG() Change-Id: If32bc320c48259dec4b81d457b848e972bcda784 Signed-off-by: Marc Schink <de...@za...> Reviewed-on: http://openocd.zylin.com/6335 Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/src/target/aarch64.c b/src/target/aarch64.c index d43ade1ff..7853ca3ff 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -1416,7 +1416,7 @@ static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoin (brp_list[brp_1].type != BRP_CONTEXT)) && (brp_1 < aarch64->brp_num)) brp_1++; - printf("brp(CTX) found num: %d\n", brp_1); + LOG_DEBUG("brp(CTX) found num: %d", brp_1); if (brp_1 >= aarch64->brp_num) { LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); return ERROR_FAIL; @@ -1426,7 +1426,7 @@ static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoin (brp_list[brp_2].type != BRP_NORMAL)) && (brp_2 < aarch64->brp_num)) brp_2++; - printf("brp(IVA) found num: %d\n", brp_2); + LOG_DEBUG("brp(IVA) found num: %d", brp_2); if (brp_2 >= aarch64->brp_num) { LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); return ERROR_FAIL; commit aad4f1c1f5a296098b4cad6bd3491d1a68844989 Author: Marc Schink <de...@za...> Date: Mon Jun 28 13:08:48 2021 +0200 target/mips64: Replace printf() with LOG_ERROR() Change-Id: I73956dc3485a23b761aecd869cc37d657c393bde Signed-off-by: Marc Schink <de...@za...> Reviewed-on: http://openocd.zylin.com/6334 Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/src/target/mips64_pracc.c b/src/target/mips64_pracc.c index dbad248fc..64abf5727 100644 --- a/src/target/mips64_pracc.c +++ b/src/target/mips64_pracc.c @@ -283,7 +283,7 @@ int mips64_pracc_exec(struct mips_ejtag *ejtag_info, if (ejtag_ctrl & EJTAG_CTRL_PRNW) { retval = mips64_pracc_exec_write(&ctx, address); if (retval != ERROR_OK) { - printf("ERROR mips64_pracc_exec_write\n"); + LOG_ERROR("mips64_pracc_exec_write() failed"); return retval; } } else { @@ -296,7 +296,7 @@ int mips64_pracc_exec(struct mips_ejtag *ejtag_info, } retval = mips64_pracc_exec_read(&ctx, address); if (retval != ERROR_OK) { - printf("ERROR mips64_pracc_exec_read\n"); + LOG_ERROR("mips64_pracc_exec_read() failed"); return retval; } ----------------------------------------------------------------------- Summary of changes: src/target/aarch64.c | 4 ++-- src/target/cortex_a.c | 4 ++-- src/target/mips64_pracc.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-02 16:14:39
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 6ad89d61af681e11960082a906357d8e8c3396a1 (commit) via c8e643fd9f09849b341942d11866ab45bc7c99a3 (commit) from 66334354b7348da2cb70edbfc117a46f2820a16a (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 6ad89d61af681e11960082a906357d8e8c3396a1 Author: Tim Newsome <ti...@si...> Date: Mon Jun 21 14:37:41 2021 -0700 Add RTOS memory read/write functions. If not implemented, these specify to regular target read/write. However, if individual threads in an RTOS can have different address translation configured then the RTOS support can use this to do the right thing. Use this in hwthread, where of course address translation can be set up differently for different real cores. Change-Id: I62c501cff1f863d855ee197dee7b73204ea8885a Signed-off-by: Tim Newsome <ti...@si...> Reviewed-on: http://openocd.zylin.com/6327 Tested-by: jenkins Reviewed-by: Marc Schink <de...@za...> Reviewed-by: Jan Matyas <ma...@co...> Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/src/rtos/hwthread.c b/src/rtos/hwthread.c index ce2408635..dfa247f2c 100644 --- a/src/rtos/hwthread.c +++ b/src/rtos/hwthread.c @@ -38,6 +38,10 @@ static int hwthread_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, static int hwthread_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]); static int hwthread_smp_init(struct target *target); static int hwthread_set_reg(struct rtos *rtos, uint32_t reg_num, uint8_t *reg_value); +static int hwthread_read_buffer(struct rtos *rtos, target_addr_t address, + uint32_t size, uint8_t *buffer); +static int hwthread_write_buffer(struct rtos *rtos, target_addr_t address, + uint32_t size, const uint8_t *buffer); #define HW_THREAD_NAME_STR_SIZE (32) @@ -58,6 +62,8 @@ const struct rtos_type hwthread_rtos = { .get_symbol_list_to_lookup = hwthread_get_symbol_list_to_lookup, .smp_init = hwthread_smp_init, .set_reg = hwthread_set_reg, + .read_buffer = hwthread_read_buffer, + .write_buffer = hwthread_write_buffer, }; struct hwthread_params { @@ -396,3 +402,33 @@ static int hwthread_create(struct target *target) target->rtos->gdb_thread_packet = hwthread_thread_packet; return 0; } + +static int hwthread_read_buffer(struct rtos *rtos, target_addr_t address, + uint32_t size, uint8_t *buffer) +{ + if (!rtos) + return ERROR_FAIL; + + struct target *target = rtos->target; + + struct target *curr = hwthread_find_thread(target, rtos->current_thread); + if (!curr) + return ERROR_FAIL; + + return target_read_buffer(curr, address, size, buffer); +} + +static int hwthread_write_buffer(struct rtos *rtos, target_addr_t address, + uint32_t size, const uint8_t *buffer) +{ + if (!rtos) + return ERROR_FAIL; + + struct target *target = rtos->target; + + struct target *curr = hwthread_find_thread(target, rtos->current_thread); + if (!curr) + return ERROR_FAIL; + + return target_write_buffer(curr, address, size, buffer); +} diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c index 5fc958db2..2bc8910c2 100644 --- a/src/rtos/rtos.c +++ b/src/rtos/rtos.c @@ -679,3 +679,19 @@ void rtos_free_threadlist(struct rtos *rtos) rtos->current_thread = 0; } } + +int rtos_read_buffer(struct target *target, target_addr_t address, + uint32_t size, uint8_t *buffer) +{ + if (target->rtos->type->read_buffer) + return target->rtos->type->read_buffer(target->rtos, address, size, buffer); + return ERROR_NOT_IMPLEMENTED; +} + +int rtos_write_buffer(struct target *target, target_addr_t address, + uint32_t size, const uint8_t *buffer) +{ + if (target->rtos->type->write_buffer) + return target->rtos->type->write_buffer(target->rtos, address, size, buffer); + return ERROR_NOT_IMPLEMENTED; +} diff --git a/src/rtos/rtos.h b/src/rtos/rtos.h index 20f7de775..81751fe0a 100644 --- a/src/rtos/rtos.h +++ b/src/rtos/rtos.h @@ -82,6 +82,13 @@ struct rtos_type { int (*clean)(struct target *target); char * (*ps_command)(struct target *target); int (*set_reg)(struct rtos *rtos, uint32_t reg_num, uint8_t *reg_value); + /* Implement these if different threads in the RTOS can see memory + * differently (for instance because address translation might be different + * for each thread). */ + int (*read_buffer)(struct rtos *rtos, target_addr_t address, uint32_t size, + uint8_t *buffer); + int (*write_buffer)(struct rtos *rtos, target_addr_t address, uint32_t size, + const uint8_t *buffer); }; struct stack_register_offset { @@ -127,5 +134,9 @@ void rtos_free_threadlist(struct rtos *rtos); int rtos_smp_init(struct target *target); /* function for handling symbol access */ int rtos_qsymbol(struct connection *connection, char const *packet, int packet_size); +int rtos_read_buffer(struct target *target, target_addr_t address, + uint32_t size, uint8_t *buffer); +int rtos_write_buffer(struct target *target, target_addr_t address, + uint32_t size, const uint8_t *buffer); #endif /* OPENOCD_RTOS_RTOS_H */ diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c index d0586d170..9ac982f6c 100644 --- a/src/server/gdb_server.c +++ b/src/server/gdb_server.c @@ -1494,7 +1494,11 @@ static int gdb_read_memory_packet(struct connection *connection, LOG_DEBUG("addr: 0x%16.16" PRIx64 ", len: 0x%8.8" PRIx32 "", addr, len); - retval = target_read_buffer(target, addr, len, buffer); + retval = ERROR_NOT_IMPLEMENTED; + if (target->rtos) + retval = rtos_read_buffer(target, addr, len, buffer); + if (retval == ERROR_NOT_IMPLEMENTED) + retval = target_read_buffer(target, addr, len, buffer); if ((retval != ERROR_OK) && !gdb_report_data_abort) { /* TODO : Here we have to lie and send back all zero's lest stack traces won't work. @@ -1565,7 +1569,11 @@ static int gdb_write_memory_packet(struct connection *connection, if (unhexify(buffer, separator, len) != len) LOG_ERROR("unable to decode memory packet"); - retval = target_write_buffer(target, addr, len, buffer); + retval = ERROR_NOT_IMPLEMENTED; + if (target->rtos) + retval = rtos_write_buffer(target, addr, len, buffer); + if (retval == ERROR_NOT_IMPLEMENTED) + retval = target_write_buffer(target, addr, len, buffer); if (retval == ERROR_OK) gdb_put_packet(connection, "OK", 2); @@ -1634,7 +1642,12 @@ static int gdb_write_memory_binary_packet(struct connection *connection, if (len) { LOG_DEBUG("addr: 0x%" PRIx64 ", len: 0x%8.8" PRIx32 "", addr, len); - retval = target_write_buffer(target, addr, len, (uint8_t *)separator); + retval = ERROR_NOT_IMPLEMENTED; + if (target->rtos) + retval = rtos_write_buffer(target, addr, len, (uint8_t *)separator); + if (retval == ERROR_NOT_IMPLEMENTED) + retval = target_write_buffer(target, addr, len, (uint8_t *)separator); + if (retval != ERROR_OK) gdb_connection->mem_write_error = true; } commit c8e643fd9f09849b341942d11866ab45bc7c99a3 Author: Jan Matyas <ma...@co...> Date: Fri Jun 4 12:54:02 2021 +0200 target: check return value of register get/set callbacks - In "reg" TCL command handler, the return value of register get() and set() callbacks must be checked, in the same manner as it is done in e.g. gdb_set_register_packet() or gdb_get_register_packet(). - Minor cleanup of variable definitions in the "reg" command handler. Change-Id: I8c57e7c087fe31d1abffa3c4d1f79a01af4c9c97 Signed-off-by: Jan Matyas <ma...@co...> Reviewed-on: http://openocd.zylin.com/6293 Tested-by: jenkins Reviewed-by: Marc Schink <de...@za...> Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/src/target/target.c b/src/target/target.c index dbc99b41c..476986c24 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -3059,20 +3059,16 @@ static int handle_target(void *priv) COMMAND_HANDLER(handle_reg_command) { - struct target *target; - struct reg *reg = NULL; - unsigned count = 0; - char *value; - LOG_DEBUG("-"); - target = get_current_target(CMD_CTX); + struct target *target = get_current_target(CMD_CTX); + struct reg *reg = NULL; /* list all available registers for the current target */ if (CMD_ARGC == 0) { struct reg_cache *cache = target->reg_cache; - count = 0; + unsigned int count = 0; while (cache) { unsigned i; @@ -3085,7 +3081,7 @@ COMMAND_HANDLER(handle_reg_command) continue; /* only print cached values if they are valid */ if (reg->valid) { - value = buf_to_hex_str(reg->value, + char *value = buf_to_hex_str(reg->value, reg->size); command_print(CMD, "(%i) %s (/%" PRIu32 "): 0x%s%s", @@ -3113,7 +3109,7 @@ COMMAND_HANDLER(handle_reg_command) COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num); struct reg_cache *cache = target->reg_cache; - count = 0; + unsigned int count = 0; while (cache) { unsigned i; for (i = 0; i < cache->num_regs; i++) { @@ -3151,9 +3147,14 @@ COMMAND_HANDLER(handle_reg_command) if ((CMD_ARGC == 2) && (strcmp(CMD_ARGV[1], "force") == 0)) reg->valid = 0; - if (reg->valid == 0) - reg->type->get(reg); - value = buf_to_hex_str(reg->value, reg->size); + if (reg->valid == 0) { + int retval = reg->type->get(reg); + if (retval != ERROR_OK) { + LOG_ERROR("Could not read register '%s'", reg->name); + return retval; + } + } + char *value = buf_to_hex_str(reg->value, reg->size); command_print(CMD, "%s (/%i): 0x%s", reg->name, (int)(reg->size), value); free(value); return ERROR_OK; @@ -3166,15 +3167,18 @@ COMMAND_HANDLER(handle_reg_command) return ERROR_FAIL; str_to_buf(CMD_ARGV[1], strlen(CMD_ARGV[1]), buf, reg->size, 0); - reg->type->set(reg, buf); - - value = buf_to_hex_str(reg->value, reg->size); - command_print(CMD, "%s (/%i): 0x%s", reg->name, (int)(reg->size), value); - free(value); + int retval = reg->type->set(reg, buf); + if (retval != ERROR_OK) { + LOG_ERROR("Could not write to register '%s'", reg->name); + } else { + char *value = buf_to_hex_str(reg->value, reg->size); + command_print(CMD, "%s (/%i): 0x%s", reg->name, (int)(reg->size), value); + free(value); + } free(buf); - return ERROR_OK; + return retval; } return ERROR_COMMAND_SYNTAX_ERROR; ----------------------------------------------------------------------- Summary of changes: src/rtos/hwthread.c | 36 ++++++++++++++++++++++++++++++++++++ src/rtos/rtos.c | 16 ++++++++++++++++ src/rtos/rtos.h | 11 +++++++++++ src/server/gdb_server.c | 19 ++++++++++++++++--- src/target/target.c | 40 ++++++++++++++++++++++------------------ 5 files changed, 101 insertions(+), 21 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-02 16:13:49
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 66334354b7348da2cb70edbfc117a46f2820a16a (commit) via ac22cdc573225fa5860f25821eed52d92ea633e7 (commit) from 920cacd74c4cd9c54d20c5c0738d8d28a456fdf1 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 66334354b7348da2cb70edbfc117a46f2820a16a Author: Marc Schink <de...@za...> Date: Sun Jun 20 19:04:32 2021 +0200 target/stm8: Remove unused member 'stm8_common' Change-Id: Ie8b59a82142bfdf2ee9395d38b1bedc27de728b8 Signed-off-by: Marc Schink <de...@za...> Reviewed-on: http://openocd.zylin.com/6325 Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/src/target/stm8.c b/src/target/stm8.c index a1653bc57..21fc8c54f 100644 --- a/src/target/stm8.c +++ b/src/target/stm8.c @@ -159,7 +159,6 @@ struct stm8_algorithm { struct stm8_core_reg { uint32_t num; struct target *target; - struct stm8_common *stm8_common; }; enum hw_break_type { @@ -1221,7 +1220,6 @@ static struct reg_cache *stm8_build_reg_cache(struct target *target) for (i = 0; i < num_regs; i++) { arch_info[i].num = stm8_regs[i].id; arch_info[i].target = target; - arch_info[i].stm8_common = stm8; reg_list[i].name = stm8_regs[i].name; reg_list[i].size = stm8_regs[i].bits; commit ac22cdc573225fa5860f25821eed52d92ea633e7 Author: Kevin Burke <ke...@os...> Date: Tue Feb 9 17:27:03 2021 -0500 target/adiv5: Large Physical Address Extension Provides ARM LPAE support to allow 64-bit TAR setting on MEM AP accesses. Tested on a 4-core ARM ARES Processor system using an AXI Access Port. Change-Id: I88f7a0a57a6abb58665032929194a41dd8729f6b Signed-off-by: Kevin Burke <ke...@os...> Signed-off-by: Daniel Goehring <dgo...@os...> Reviewed-on: http://openocd.zylin.com/5576 Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 171c28615..d43ade1ff 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -252,7 +252,7 @@ static int aarch64_init_debug_access(struct target *target) /* Write to memory mapped registers directly with no cache or mmu handling */ static int aarch64_dap_write_memap_register_u32(struct target *target, - uint32_t address, + target_addr_t address, uint32_t value) { int retval; @@ -2571,7 +2571,7 @@ static int aarch64_examine_first(struct target *target) armv8->debug_ap->memaccess_tck = 10; if (!target->dbgbase_set) { - uint32_t dbgbase; + target_addr_t dbgbase; /* Get ROM Table base */ uint32_t apid; int32_t coreidx = target->coreid; @@ -2583,7 +2583,7 @@ static int aarch64_examine_first(struct target *target) &armv8->debug_base, &coreidx); if (retval != ERROR_OK) return retval; - LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32 + LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT " apid: %08" PRIx32, coreidx, armv8->debug_base, apid); } else armv8->debug_base = target->dbgbase; diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 35d686e29..65ac05351 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -13,6 +13,8 @@ * Copyright (C) 2013 by Andreas Fritiofson * * and...@gm... * * * + * Copyright (C) 2019-2021, Ampere Computing LLC * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -86,7 +88,7 @@ uint32_t tar_block_size(uint32_t address) Return the largest block starting at address that does not cross a tar block size alignment boundary */ -static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address) +static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, target_addr_t address) { return tar_autoincr_block - ((tar_autoincr_block - 1) & address); } @@ -113,11 +115,16 @@ static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw) return ERROR_OK; } -static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar) +static int mem_ap_setup_tar(struct adiv5_ap *ap, target_addr_t tar) { if (!ap->tar_valid || tar != ap->tar_value) { /* LOG_DEBUG("DAP: Set TAR %x",tar); */ - int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar); + int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, (uint32_t)(tar & 0xffffffffUL)); + if (retval == ERROR_OK && is_64bit_ap(ap)) { + /* See if bits 63:32 of tar is different from last setting */ + if ((ap->tar_value >> 32) != (tar >> 32)) + retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR64, (uint32_t)(tar >> 32)); + } if (retval != ERROR_OK) { ap->tar_valid = false; return retval; @@ -128,9 +135,15 @@ static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar) return ERROR_OK; } -static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar) +static int mem_ap_read_tar(struct adiv5_ap *ap, target_addr_t *tar) { - int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar); + uint32_t lower; + uint32_t upper = 0; + + int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, &lower); + if (retval == ERROR_OK && is_64bit_ap(ap)) + retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR64, &upper); + if (retval != ERROR_OK) { ap->tar_valid = false; return retval; @@ -142,6 +155,8 @@ static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar) return retval; } + *tar = (((target_addr_t)upper) << 32) | (target_addr_t)lower; + ap->tar_value = *tar; ap->tar_valid = true; return ERROR_OK; @@ -198,7 +213,7 @@ static void mem_ap_update_tar_cache(struct adiv5_ap *ap) * * @return ERROR_OK if the transaction was properly queued, else a fault code. */ -static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar) +static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, target_addr_t tar) { int retval; retval = mem_ap_setup_csw(ap, csw); @@ -221,7 +236,7 @@ static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar * * @return ERROR_OK for success. Otherwise a fault code. */ -int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address, +int mem_ap_read_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value) { int retval; @@ -231,7 +246,7 @@ int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address, */ retval = mem_ap_setup_transfer(ap, CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK), - address & 0xFFFFFFF0); + address & 0xFFFFFFFFFFFFFFF0ull); if (retval != ERROR_OK) return retval; @@ -250,7 +265,7 @@ int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address, * @return ERROR_OK for success; *value holds the result. * Otherwise a fault code. */ -int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address, +int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value) { int retval; @@ -273,7 +288,7 @@ int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address, * * @return ERROR_OK for success. Otherwise a fault code. */ -int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address, +int mem_ap_write_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value) { int retval; @@ -283,7 +298,7 @@ int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address, */ retval = mem_ap_setup_transfer(ap, CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK), - address & 0xFFFFFFF0); + address & 0xFFFFFFFFFFFFFFF0ull); if (retval != ERROR_OK) return retval; @@ -302,7 +317,7 @@ int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address, * * @return ERROR_OK for success; the data was written. Otherwise a fault code. */ -int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address, +int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value) { int retval = mem_ap_write_u32(ap, address, value); @@ -326,13 +341,13 @@ int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address, * @return ERROR_OK on success, otherwise an error code. */ static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, - uint32_t address, bool addrinc) + target_addr_t address, bool addrinc) { struct adiv5_dap *dap = ap->dap; size_t nbytes = size * count; const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF; uint32_t csw_size; - uint32_t addr_xor; + target_addr_t addr_xor; int retval = ERROR_OK; /* TI BE-32 Quirks mode: @@ -433,9 +448,9 @@ static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t siz retval = dap_run(dap); if (retval != ERROR_OK) { - uint32_t tar; + target_addr_t tar; if (mem_ap_read_tar(ap, &tar) == ERROR_OK) - LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar); + LOG_ERROR("Failed to write memory at " TARGET_ADDR_FMT, tar); else LOG_ERROR("Failed to write memory and, additionally, failed to find out where"); } @@ -456,13 +471,13 @@ static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t siz * @return ERROR_OK on success, otherwise an error code. */ static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, - uint32_t adr, bool addrinc) + target_addr_t adr, bool addrinc) { struct adiv5_dap *dap = ap->dap; size_t nbytes = size * count; const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF; uint32_t csw_size; - uint32_t address = adr; + target_addr_t address = adr; int retval = ERROR_OK; /* TI BE-32 Quirks mode: @@ -538,10 +553,10 @@ static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint /* If something failed, read TAR to find out how much data was successfully read, so we can * at least give the caller what we have. */ if (retval != ERROR_OK) { - uint32_t tar; + target_addr_t tar; if (mem_ap_read_tar(ap, &tar) == ERROR_OK) { /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */ - LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar); + LOG_ERROR("Failed to read memory at " TARGET_ADDR_FMT, tar); if (nbytes > tar - address) nbytes = tar - address; } else { @@ -594,25 +609,25 @@ static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint } int mem_ap_read_buf(struct adiv5_ap *ap, - uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address) + uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address) { return mem_ap_read(ap, buffer, size, count, address, true); } int mem_ap_write_buf(struct adiv5_ap *ap, - const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address) + const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address) { return mem_ap_write(ap, buffer, size, count, address, true); } int mem_ap_read_buf_noincr(struct adiv5_ap *ap, - uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address) + uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address) { return mem_ap_read(ap, buffer, size, count, address, false); } int mem_ap_write_buf_noincr(struct adiv5_ap *ap, - const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address) + const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address) { return mem_ap_write(ap, buffer, size, count, address, false); } @@ -761,6 +776,17 @@ int mem_ap_init(struct adiv5_ap *ap) int retval; struct adiv5_dap *dap = ap->dap; + /* Set ap->cfg_reg before calling mem_ap_setup_transfer(). */ + /* mem_ap_setup_transfer() needs to know if the MEM_AP supports LPAE. */ + retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg); + if (retval != ERROR_OK) + return retval; + + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; + + ap->cfg_reg = cfg; ap->tar_valid = false; ap->csw_value = 0; /* force csw and tar write */ retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0); @@ -771,10 +797,6 @@ int mem_ap_init(struct adiv5_ap *ap) if (retval != ERROR_OK) return retval; - retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg); - if (retval != ERROR_OK) - return retval; - retval = dap_run(dap); if (retval != ERROR_OK) return retval; @@ -801,7 +823,7 @@ int mem_ap_init(struct adiv5_ap *ap) ap->unaligned_access_bad = dap->ti_be_32_quirks; LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d", - !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01)); + !!(cfg & MEM_AP_REG_CFG_LD), !!(cfg & MEM_AP_REG_CFG_LA), !!(cfg & MEM_AP_REG_CFG_BE)); return ERROR_OK; } @@ -918,12 +940,22 @@ int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_a } int dap_get_debugbase(struct adiv5_ap *ap, - uint32_t *dbgbase, uint32_t *apid) + target_addr_t *dbgbase, uint32_t *apid) { struct adiv5_dap *dap = ap->dap; int retval; + uint32_t baseptr_upper, baseptr_lower; + + baseptr_upper = 0; + + if (is_64bit_ap(ap)) { + /* Read higher order 32-bits of base address */ + retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseptr_upper); + if (retval != ERROR_OK) + return retval; + } - retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase); + retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, &baseptr_lower); if (retval != ERROR_OK) return retval; retval = dap_queue_ap_read(ap, AP_REG_IDR, apid); @@ -933,31 +965,34 @@ int dap_get_debugbase(struct adiv5_ap *ap, if (retval != ERROR_OK) return retval; + *dbgbase = (((target_addr_t)baseptr_upper) << 32) | baseptr_lower; + return ERROR_OK; } int dap_lookup_cs_component(struct adiv5_ap *ap, - uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx) + target_addr_t dbgbase, uint8_t type, target_addr_t *addr, int32_t *idx) { - uint32_t romentry, entry_offset = 0, component_base, devtype; + uint32_t romentry, entry_offset = 0, devtype; + target_addr_t component_base; int retval; + dbgbase &= 0xFFFFFFFFFFFFF000ull; *addr = 0; do { - retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) | + retval = mem_ap_read_atomic_u32(ap, dbgbase | entry_offset, &romentry); if (retval != ERROR_OK) return retval; - component_base = (dbgbase & 0xFFFFF000) - + (romentry & 0xFFFFF000); + component_base = dbgbase + (target_addr_t)(romentry & 0xFFFFF000); if (romentry & 0x1) { uint32_t c_cid1; retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1); if (retval != ERROR_OK) { - LOG_ERROR("Can't read component with base address 0x%" PRIx32 + LOG_ERROR("Can't read component with base address " TARGET_ADDR_FMT ", the corresponding core might be turned off", component_base); return retval; } @@ -970,9 +1005,7 @@ int dap_lookup_cs_component(struct adiv5_ap *ap, return retval; } - retval = mem_ap_read_atomic_u32(ap, - (component_base & 0xfffff000) | 0xfcc, - &devtype); + retval = mem_ap_read_atomic_u32(ap, component_base | 0xfcc, &devtype); if (retval != ERROR_OK) return retval; if ((devtype & 0xff) == type) { @@ -984,7 +1017,7 @@ int dap_lookup_cs_component(struct adiv5_ap *ap, } } entry_offset += 4; - } while (romentry > 0); + } while ((romentry > 0) && (entry_offset < 0xf00)); if (!*addr) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; @@ -992,7 +1025,7 @@ int dap_lookup_cs_component(struct adiv5_ap *ap, return ERROR_OK; } -static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid) +static int dap_read_part_id(struct adiv5_ap *ap, target_addr_t component_base, uint32_t *cid, uint64_t *pid) { assert((component_base & 0xFFF) == 0); assert(ap != NULL && cid != NULL && pid != NULL); @@ -1179,7 +1212,7 @@ static const struct { }; static int dap_rom_display(struct command_invocation *cmd, - struct adiv5_ap *ap, uint32_t dbgbase, int depth) + struct adiv5_ap *ap, target_addr_t dbgbase, int depth) { int retval; uint64_t pid; @@ -1194,8 +1227,8 @@ static int dap_rom_display(struct command_invocation *cmd, if (depth) snprintf(tabs, sizeof(tabs), "[L%02d] ", depth); - uint32_t base_addr = dbgbase & 0xFFFFF000; - command_print(cmd, "\t\tComponent base address 0x%08" PRIx32, base_addr); + target_addr_t base_addr = dbgbase & 0xFFFFFFFFFFFFF000ull; + command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, base_addr); retval = dap_read_part_id(ap, base_addr, &cid, &pid); if (retval != ERROR_OK) { @@ -1211,7 +1244,7 @@ static int dap_rom_display(struct command_invocation *cmd, /* component may take multiple 4K pages */ uint32_t size = (pid >> 36) & 0xf; if (size > 0) - command_print(cmd, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size)); + command_print(cmd, "\t\tStart address " TARGET_ADDR_FMT, base_addr - 0x1000 * size); command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, pid); @@ -1436,7 +1469,9 @@ int dap_info_command(struct command_invocation *cmd, struct adiv5_ap *ap) { int retval; - uint32_t dbgbase, apid; + uint32_t apid; + target_addr_t dbgbase; + target_addr_t dbgaddr; uint8_t mem_ap; /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ @@ -1476,9 +1511,14 @@ int dap_info_command(struct command_invocation *cmd, */ mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP; if (mem_ap) { - command_print(cmd, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase); + if (is_64bit_ap(ap)) + dbgaddr = 0xFFFFFFFFFFFFFFFFull; + else + dbgaddr = 0xFFFFFFFFul; - if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) { + command_print(cmd, "MEM-AP BASE " TARGET_ADDR_FMT, dbgbase); + + if (dbgbase == dbgaddr || (dbgbase & 0x3) == 0x2) { command_print(cmd, "\tNo ROM table present"); } else { if (dbgbase & 0x01) @@ -1486,7 +1526,7 @@ int dap_info_command(struct command_invocation *cmd, else command_print(cmd, "\tROM table in legacy format"); - dap_rom_display(cmd, ap, dbgbase & 0xFFFFF000, 0); + dap_rom_display(cmd, ap, dbgbase & 0xFFFFFFFFFFFFF000ull, 0); } } @@ -1690,9 +1730,13 @@ COMMAND_HANDLER(handle_dap_info_command) COMMAND_HANDLER(dap_baseaddr_command) { struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); - uint32_t apsel, baseaddr; + uint32_t apsel, baseaddr_lower, baseaddr_upper; + struct adiv5_ap *ap; + target_addr_t baseaddr; int retval; + baseaddr_upper = 0; + switch (CMD_ARGC) { case 0: apsel = dap->apsel; @@ -1714,14 +1758,22 @@ COMMAND_HANDLER(dap_baseaddr_command) * though they're not common for now. This should * use the ID register to verify it's a MEM-AP. */ - retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr); + + ap = dap_ap(dap, apsel); + retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, &baseaddr_lower); + + if (is_64bit_ap(ap) && retval == ERROR_OK) + retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseaddr_upper); if (retval != ERROR_OK) return retval; retval = dap_run(dap); if (retval != ERROR_OK) return retval; - - command_print(CMD, "0x%8.8" PRIx32, baseaddr); + if (is_64bit_ap(ap)) { + baseaddr = (((target_addr_t)baseaddr_upper) << 32) | baseaddr_lower; + command_print(CMD, "0x%016" PRIx64, baseaddr); + } else + command_print(CMD, "0x%08" PRIx32, baseaddr_lower); return retval; } @@ -1885,8 +1937,25 @@ COMMAND_HANDLER(dap_apreg_command) ap->csw_value = value; break; case MEM_AP_REG_TAR: - ap->tar_valid = false; /* invalid, force write */ - retval = mem_ap_setup_tar(ap, value); + retval = dap_queue_ap_write(ap, reg, value); + if (retval == ERROR_OK) + ap->tar_value = (ap->tar_value & ~0xFFFFFFFFull) | value; + else { + /* To track independent writes to TAR and TAR64, two tar_valid flags */ + /* should be used. To keep it simple, tar_valid is only invalidated on a */ + /* write fail. This approach causes a later re-write of the TAR and TAR64 */ + /* if tar_valid is false. */ + ap->tar_valid = false; + } + break; + case MEM_AP_REG_TAR64: + retval = dap_queue_ap_write(ap, reg, value); + if (retval == ERROR_OK) + ap->tar_value = (ap->tar_value & 0xFFFFFFFFull) | (((target_addr_t)value) << 32); + else { + /* See above comment for the MEM_AP_REG_TAR failed write case */ + ap->tar_valid = false; + } break; default: retval = dap_queue_ap_write(ap, reg, value); diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index ce9155ae7..7eb44f2ed 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -31,6 +31,7 @@ #include <helper/list.h> #include "arm_jtag.h" +#include "helper/bits.h" /* three-bit ACK values for SWD access (sent LSB first) */ #define SWD_ACK_OK 0x1 @@ -149,6 +150,10 @@ /* APB: initial value of csw_default */ #define CSW_APB_DEFAULT (CSW_DBGSWENABLE) +/* Fields of the MEM-AP's CFG register */ +#define MEM_AP_REG_CFG_BE BIT(0) +#define MEM_AP_REG_CFG_LA BIT(1) +#define MEM_AP_REG_CFG_LD BIT(2) /* Fields of the MEM-AP's IDR register */ #define IDR_REV (0xFUL << 28) @@ -201,7 +206,7 @@ struct adiv5_ap { * configure the address being read or written * "-1" indicates no cached value. */ - uint32_t tar_value; + target_addr_t tar_value; /** * Configures how many extra tck clocks are added after starting a @@ -220,6 +225,9 @@ struct adiv5_ap { /* true if tar_value is in sync with TAR register */ bool tar_valid; + + /* MEM AP configuration register indicating LPAE support */ + uint32_t cfg_reg; }; @@ -359,6 +367,20 @@ enum ap_type { AP_TYPE_AHB5_AP = 0x5, /* AHB5 Memory-AP. */ }; +/* Check the ap->cfg_reg Long Address field (bit 1) + * + * 0b0: The AP only supports physical addresses 32 bits or smaller + * 0b1: The AP supports physical addresses larger than 32 bits + * + * @param ap The AP used for reading. + * + * @return true for 64 bit, false for 32 bit + */ +static inline bool is_64bit_ap(struct adiv5_ap *ap) +{ + return (ap->cfg_reg & MEM_AP_REG_CFG_LA) != 0; +} + /** * Send an adi-v5 sequence to the DAP. * @@ -528,27 +550,27 @@ static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg, /* Queued MEM-AP memory mapped single word transfers. */ int mem_ap_read_u32(struct adiv5_ap *ap, - uint32_t address, uint32_t *value); + target_addr_t address, uint32_t *value); int mem_ap_write_u32(struct adiv5_ap *ap, - uint32_t address, uint32_t value); + target_addr_t address, uint32_t value); /* Synchronous MEM-AP memory mapped single word transfers. */ int mem_ap_read_atomic_u32(struct adiv5_ap *ap, - uint32_t address, uint32_t *value); + target_addr_t address, uint32_t *value); int mem_ap_write_atomic_u32(struct adiv5_ap *ap, - uint32_t address, uint32_t value); + target_addr_t address, uint32_t value); /* Synchronous MEM-AP memory mapped bus block transfers. */ int mem_ap_read_buf(struct adiv5_ap *ap, - uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); + uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address); int mem_ap_write_buf(struct adiv5_ap *ap, - const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); + const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address); /* Synchronous, non-incrementing buffer functions for accessing fifos. */ int mem_ap_read_buf_noincr(struct adiv5_ap *ap, - uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); + uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address); int mem_ap_write_buf_noincr(struct adiv5_ap *ap, - const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); + const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address); /* Initialisation of the debug system, power domains and registers */ int dap_dp_init(struct adiv5_dap *dap); @@ -560,7 +582,7 @@ void dap_invalidate_cache(struct adiv5_dap *dap); /* Probe the AP for ROM Table location */ int dap_get_debugbase(struct adiv5_ap *ap, - uint32_t *dbgbase, uint32_t *apid); + target_addr_t *dbgbase, uint32_t *apid); /* Probe Access Ports to find a particular type */ int dap_find_ap(struct adiv5_dap *dap, @@ -574,7 +596,7 @@ static inline struct adiv5_ap *dap_ap(struct adiv5_dap *dap, uint8_t ap_num) /* Lookup CoreSight component */ int dap_lookup_cs_component(struct adiv5_ap *ap, - uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx); + target_addr_t dbgbase, uint8_t type, target_addr_t *addr, int32_t *idx); struct target; diff --git a/src/target/arm_dap.c b/src/target/arm_dap.c index 747733dc9..87e232af8 100644 --- a/src/target/arm_dap.c +++ b/src/target/arm_dap.c @@ -36,6 +36,8 @@ extern const struct dap_ops swd_dap_ops; extern const struct dap_ops jtag_dp_ops; extern struct adapter_driver *adapter_driver; +#define ADI_BAD_CFG 0xBAD00000 + /* DAP command support */ struct arm_dap_object { struct list_head lh; @@ -57,6 +59,7 @@ static void dap_instance_init(struct adiv5_dap *dap) dap->ap[i].tar_autoincr_block = (1<<10); /* default CSW value */ dap->ap[i].csw_default = CSW_AHB_DEFAULT; + dap->ap[i].cfg_reg = ADI_BAD_CFG; /* mem_ap configuration reg (large physical addr, etc.) */ } INIT_LIST_HEAD(&dap->cmd_journal); INIT_LIST_HEAD(&dap->cmd_pool); diff --git a/src/target/armv7a.h b/src/target/armv7a.h index 7b6219821..c282554a5 100644 --- a/src/target/armv7a.h +++ b/src/target/armv7a.h @@ -104,7 +104,7 @@ struct armv7a_common { /* Core Debug Unit */ struct arm_dpm dpm; - uint32_t debug_base; + target_addr_t debug_base; struct adiv5_ap *debug_ap; /* mdir */ uint8_t multi_processor_system; diff --git a/src/target/armv8.h b/src/target/armv8.h index f09f3abfd..c30739c8c 100644 --- a/src/target/armv8.h +++ b/src/target/armv8.h @@ -196,7 +196,7 @@ struct armv8_common { /* Core Debug Unit */ struct arm_dpm dpm; - uint32_t debug_base; + target_addr_t debug_base; struct adiv5_ap *debug_ap; const uint32_t *opcodes; diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 7af0d3d7e..2e810b5db 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -2907,7 +2907,7 @@ static int cortex_a_examine_first(struct target *target) armv7a->debug_ap->memaccess_tck = 80; if (!target->dbgbase_set) { - uint32_t dbgbase; + target_addr_t dbgbase; /* Get ROM Table base */ uint32_t apid; int32_t coreidx = target->coreid; @@ -2924,7 +2924,7 @@ static int cortex_a_examine_first(struct target *target) target->cmd_name); return retval; } - LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32, + LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT, target->coreid, armv7a->debug_base); } else armv7a->debug_base = target->dbgbase; ----------------------------------------------------------------------- Summary of changes: src/target/aarch64.c | 6 +- src/target/arm_adi_v5.c | 181 +++++++++++++++++++++++++++++++++--------------- src/target/arm_adi_v5.h | 44 +++++++++--- src/target/arm_dap.c | 3 + src/target/armv7a.h | 2 +- src/target/armv8.h | 2 +- src/target/cortex_a.c | 4 +- src/target/stm8.c | 2 - 8 files changed, 168 insertions(+), 76 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-02 16:12:51
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 920cacd74c4cd9c54d20c5c0738d8d28a456fdf1 (commit) via a489058d7b1d7bab8d0e4db53f98b7762d7482a2 (commit) from 3ad52aa34f6763dddc2a903c255a09f7c7e21ed7 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 920cacd74c4cd9c54d20c5c0738d8d28a456fdf1 Author: Antonio Borneo <bor...@gm...> Date: Sun Jun 6 19:22:30 2021 +0200 rtos/eCos: rename CamelCase symbols Convert CamelCase enum in uppercase and the other symbols in lowercase. Change-Id: I141c55bdfe6ef2a2da28d1da15a283a644ae7cb2 Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6306 Tested-by: jenkins diff --git a/src/rtos/eCos.c b/src/rtos/eCos.c index a9feb8019..b060a812a 100644 --- a/src/rtos/eCos.c +++ b/src/rtos/eCos.c @@ -27,18 +27,18 @@ #include "helper/types.h" #include "rtos_ecos_stackings.h" -static bool eCos_detect_rtos(struct target *target); -static int eCos_create(struct target *target); -static int eCos_update_threads(struct rtos *rtos); -static int eCos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs); -static int eCos_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]); +static bool ecos_detect_rtos(struct target *target); +static int ecos_create(struct target *target); +static int ecos_update_threads(struct rtos *rtos); +static int ecos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs); +static int ecos_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]); -struct eCos_thread_state { +struct ecos_thread_state { int value; const char *desc; }; -static const struct eCos_thread_state eCos_thread_states[] = { +static const struct ecos_thread_state ecos_thread_states[] = { { 0, "Ready" }, { 1, "Sleeping" }, { 2, "Countsleep" }, @@ -47,9 +47,9 @@ static const struct eCos_thread_state eCos_thread_states[] = { { 16, "Exited" } }; -#define ECOS_NUM_STATES ARRAY_SIZE(eCos_thread_states) +#define ECOS_NUM_STATES ARRAY_SIZE(ecos_thread_states) -struct eCos_params { +struct ecos_params { const char *target_name; unsigned char pointer_width; unsigned char thread_stack_offset; @@ -60,7 +60,7 @@ struct eCos_params { const struct rtos_register_stacking *stacking_info; }; -static const struct eCos_params eCos_params_list[] = { +static const struct ecos_params ecos_params_list[] = { { "cortex_m", /* target_name */ 4, /* pointer_width; */ @@ -69,16 +69,16 @@ static const struct eCos_params eCos_params_list[] = { 0x3c, /* thread_state_offset; */ 0xa0, /* thread_next_offset */ 0x4c, /* thread_uniqueid_offset */ - &rtos_eCos_Cortex_M3_stacking /* stacking_info */ + &rtos_ecos_cortex_m3_stacking /* stacking_info */ } }; -enum eCos_symbol_values { - eCos_VAL_thread_list = 0, - eCos_VAL_current_thread_ptr = 1 +enum ecos_symbol_values { + ECOS_VAL_THREAD_LIST = 0, + ECOS_VAL_CURRENT_THREAD_PTR = 1 }; -static const char * const eCos_symbol_list[] = { +static const char * const ecos_symbol_list[] = { "Cyg_Thread::thread_list", "Cyg_Scheduler_Base::current_thread", NULL @@ -87,20 +87,20 @@ static const char * const eCos_symbol_list[] = { const struct rtos_type ecos_rtos = { .name = "eCos", - .detect_rtos = eCos_detect_rtos, - .create = eCos_create, - .update_threads = eCos_update_threads, - .get_thread_reg_list = eCos_get_thread_reg_list, - .get_symbol_list_to_lookup = eCos_get_symbol_list_to_lookup, + .detect_rtos = ecos_detect_rtos, + .create = ecos_create, + .update_threads = ecos_update_threads, + .get_thread_reg_list = ecos_get_thread_reg_list, + .get_symbol_list_to_lookup = ecos_get_symbol_list_to_lookup, }; -static int eCos_update_threads(struct rtos *rtos) +static int ecos_update_threads(struct rtos *rtos) { int retval; int tasks_found = 0; int thread_list_size = 0; - const struct eCos_params *param; + const struct ecos_params *param; if (rtos == NULL) return -1; @@ -108,14 +108,14 @@ static int eCos_update_threads(struct rtos *rtos) if (rtos->rtos_specific_params == NULL) return -3; - param = (const struct eCos_params *) rtos->rtos_specific_params; + param = (const struct ecos_params *) rtos->rtos_specific_params; if (rtos->symbols == NULL) { LOG_ERROR("No symbols for eCos"); return -4; } - if (rtos->symbols[eCos_VAL_thread_list].address == 0) { + if (rtos->symbols[ECOS_VAL_THREAD_LIST].address == 0) { LOG_ERROR("Don't have the thread list head"); return -2; } @@ -124,7 +124,7 @@ static int eCos_update_threads(struct rtos *rtos) rtos_free_threadlist(rtos); /* determine the number of current threads */ - uint32_t thread_list_head = rtos->symbols[eCos_VAL_thread_list].address; + uint32_t thread_list_head = rtos->symbols[ECOS_VAL_THREAD_LIST].address; uint32_t thread_index; target_read_buffer(rtos->target, thread_list_head, @@ -144,7 +144,7 @@ static int eCos_update_threads(struct rtos *rtos) /* read the current thread id */ uint32_t current_thread_addr; retval = target_read_buffer(rtos->target, - rtos->symbols[eCos_VAL_current_thread_ptr].address, + rtos->symbols[ECOS_VAL_CURRENT_THREAD_PTR].address, 4, (uint8_t *)¤t_thread_addr); if (retval != ERROR_OK) @@ -246,7 +246,7 @@ static int eCos_update_threads(struct rtos *rtos) return retval; } - for (i = 0; (i < ECOS_NUM_STATES) && (eCos_thread_states[i].value != thread_status); i++) { + for (i = 0; (i < ECOS_NUM_STATES) && (ecos_thread_states[i].value != thread_status); i++) { /* * empty */ @@ -254,7 +254,7 @@ static int eCos_update_threads(struct rtos *rtos) const char *state_desc; if (i < ECOS_NUM_STATES) - state_desc = eCos_thread_states[i].desc; + state_desc = ecos_thread_states[i].desc; else state_desc = "Unknown state"; @@ -268,7 +268,7 @@ static int eCos_update_threads(struct rtos *rtos) prev_thread_ptr = thread_index; /* Get the location of the next thread structure. */ - thread_index = rtos->symbols[eCos_VAL_thread_list].address; + thread_index = rtos->symbols[ECOS_VAL_THREAD_LIST].address; retval = target_read_buffer(rtos->target, prev_thread_ptr + param->thread_next_offset, param->pointer_width, @@ -283,11 +283,11 @@ static int eCos_update_threads(struct rtos *rtos) return 0; } -static int eCos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, +static int ecos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs) { int retval; - const struct eCos_params *param; + const struct ecos_params *param; if (rtos == NULL) return -1; @@ -298,11 +298,11 @@ static int eCos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, if (rtos->rtos_specific_params == NULL) return -3; - param = (const struct eCos_params *) rtos->rtos_specific_params; + param = (const struct ecos_params *) rtos->rtos_specific_params; /* Find the thread with that thread id */ uint16_t id = 0; - uint32_t thread_list_head = rtos->symbols[eCos_VAL_thread_list].address; + uint32_t thread_list_head = rtos->symbols[ECOS_VAL_THREAD_LIST].address; uint32_t thread_index; target_read_buffer(rtos->target, thread_list_head, param->pointer_width, (uint8_t *)&thread_index); @@ -349,33 +349,33 @@ static int eCos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, return -1; } -static int eCos_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]) +static int ecos_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]) { unsigned int i; *symbol_list = calloc( - ARRAY_SIZE(eCos_symbol_list), sizeof(struct symbol_table_elem)); + ARRAY_SIZE(ecos_symbol_list), sizeof(struct symbol_table_elem)); - for (i = 0; i < ARRAY_SIZE(eCos_symbol_list); i++) - (*symbol_list)[i].symbol_name = eCos_symbol_list[i]; + for (i = 0; i < ARRAY_SIZE(ecos_symbol_list); i++) + (*symbol_list)[i].symbol_name = ecos_symbol_list[i]; return 0; } -static bool eCos_detect_rtos(struct target *target) +static bool ecos_detect_rtos(struct target *target) { if ((target->rtos->symbols != NULL) && - (target->rtos->symbols[eCos_VAL_thread_list].address != 0)) { + (target->rtos->symbols[ECOS_VAL_THREAD_LIST].address != 0)) { /* looks like eCos */ return true; } return false; } -static int eCos_create(struct target *target) +static int ecos_create(struct target *target) { - for (unsigned int i = 0; i < ARRAY_SIZE(eCos_params_list); i++) - if (strcmp(eCos_params_list[i].target_name, target->type->name) == 0) { - target->rtos->rtos_specific_params = (void *)&eCos_params_list[i]; + for (unsigned int i = 0; i < ARRAY_SIZE(ecos_params_list); i++) + if (strcmp(ecos_params_list[i].target_name, target->type->name) == 0) { + target->rtos->rtos_specific_params = (void *)&ecos_params_list[i]; target->rtos->current_thread = 0; target->rtos->thread_details = NULL; return 0; diff --git a/src/rtos/rtos_ecos_stackings.c b/src/rtos/rtos_ecos_stackings.c index ca98d9417..e2119423a 100644 --- a/src/rtos/rtos_ecos_stackings.c +++ b/src/rtos/rtos_ecos_stackings.c @@ -22,7 +22,7 @@ #include "rtos_standard_stackings.h" #include "target/armv7m.h" -static const struct stack_register_offset rtos_eCos_Cortex_M3_stack_offsets[ARMV7M_NUM_CORE_REGS] = { +static const struct stack_register_offset rtos_ecos_cortex_m3_stack_offsets[ARMV7M_NUM_CORE_REGS] = { { ARMV7M_R0, 0x0c, 32 }, /* r0 */ { ARMV7M_R1, 0x10, 32 }, /* r1 */ { ARMV7M_R2, 0x14, 32 }, /* r2 */ @@ -42,10 +42,10 @@ static const struct stack_register_offset rtos_eCos_Cortex_M3_stack_offsets[ARMV { ARMV7M_xPSR, -1, 32 }, /* xPSR */ }; -const struct rtos_register_stacking rtos_eCos_Cortex_M3_stacking = { +const struct rtos_register_stacking rtos_ecos_cortex_m3_stacking = { 0x44, /* stack_registers_size */ -1, /* stack_growth_direction */ ARMV7M_NUM_CORE_REGS, /* num_output_registers */ rtos_generic_stack_align8, /* stack_alignment */ - rtos_eCos_Cortex_M3_stack_offsets /* register_offsets */ + rtos_ecos_cortex_m3_stack_offsets /* register_offsets */ }; diff --git a/src/rtos/rtos_ecos_stackings.h b/src/rtos/rtos_ecos_stackings.h index 951f7de50..d66d05fe9 100644 --- a/src/rtos/rtos_ecos_stackings.h +++ b/src/rtos/rtos_ecos_stackings.h @@ -23,6 +23,6 @@ #include "rtos.h" -extern const struct rtos_register_stacking rtos_eCos_Cortex_M3_stacking; +extern const struct rtos_register_stacking rtos_ecos_cortex_m3_stacking; #endif /* OPENOCD_RTOS_RTOS_ECOS_STACKINGS_H */ commit a489058d7b1d7bab8d0e4db53f98b7762d7482a2 Author: Antonio Borneo <bor...@gm...> Date: Tue May 25 09:55:22 2021 +0200 rtos: rename CamelCase symbols Only one exported symbol from eCos is included in this patch. The eCos code is left untouched to prevent conflicts with patches currently under review. While there, remove an unused camelcase macro Change-Id: I8d22dec6e243c00665d99a8b8ba00474b4f088db Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6305 Tested-by: jenkins Reviewed-by: Marc Schink <de...@za...> diff --git a/src/rtos/FreeRTOS.c b/src/rtos/FreeRTOS.c index 24b829070..a480c4461 100644 --- a/src/rtos/FreeRTOS.c +++ b/src/rtos/FreeRTOS.c @@ -31,18 +31,14 @@ #include "target/armv7m.h" #include "target/cortex_m.h" - - #define FREERTOS_MAX_PRIORITIES 63 -#define FreeRTOS_STRUCT(int_type, ptr_type, list_prev_offset) - /* FIXME: none of the _width parameters are actually observed properly! * you WILL need to edit more if you actually attempt to target a 8/16/64 * bit target! */ -struct FreeRTOS_params { +struct freertos_params { const char *target_name; const unsigned char thread_count_width; const unsigned char pointer_width; @@ -57,7 +53,7 @@ struct FreeRTOS_params { const struct rtos_register_stacking *stacking_info_cm4f_fpu; }; -static const struct FreeRTOS_params FreeRTOS_params_list[] = { +static const struct freertos_params freertos_params_list[] = { { "cortex_m", /* target_name */ 4, /* thread_count_width; */ @@ -68,9 +64,9 @@ static const struct FreeRTOS_params FreeRTOS_params_list[] = { 12, /* list_elem_content_offset */ 0, /* thread_stack_offset; */ 52, /* thread_name_offset; */ - &rtos_standard_Cortex_M3_stacking, /* stacking_info */ - &rtos_standard_Cortex_M4F_stacking, - &rtos_standard_Cortex_M4F_FPU_stacking, + &rtos_standard_cortex_m3_stacking, /* stacking_info */ + &rtos_standard_cortex_m4f_stacking, + &rtos_standard_cortex_m4f_fpu_stacking, }, { "hla_target", /* target_name */ @@ -82,9 +78,9 @@ static const struct FreeRTOS_params FreeRTOS_params_list[] = { 12, /* list_elem_content_offset */ 0, /* thread_stack_offset; */ 52, /* thread_name_offset; */ - &rtos_standard_Cortex_M3_stacking, /* stacking_info */ - &rtos_standard_Cortex_M4F_stacking, - &rtos_standard_Cortex_M4F_FPU_stacking, + &rtos_standard_cortex_m3_stacking, /* stacking_info */ + &rtos_standard_cortex_m4f_stacking, + &rtos_standard_cortex_m4f_fpu_stacking, }, { "nds32_v3", /* target_name */ @@ -96,30 +92,30 @@ static const struct FreeRTOS_params FreeRTOS_params_list[] = { 12, /* list_elem_content_offset */ 0, /* thread_stack_offset; */ 52, /* thread_name_offset; */ - &rtos_standard_NDS32_N1068_stacking, /* stacking_info */ - &rtos_standard_Cortex_M4F_stacking, - &rtos_standard_Cortex_M4F_FPU_stacking, + &rtos_standard_nds32_n1068_stacking, /* stacking_info */ + &rtos_standard_cortex_m4f_stacking, + &rtos_standard_cortex_m4f_fpu_stacking, }, }; -static bool FreeRTOS_detect_rtos(struct target *target); -static int FreeRTOS_create(struct target *target); -static int FreeRTOS_update_threads(struct rtos *rtos); -static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, +static bool freertos_detect_rtos(struct target *target); +static int freertos_create(struct target *target); +static int freertos_update_threads(struct rtos *rtos); +static int freertos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs); -static int FreeRTOS_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]); +static int freertos_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]); -struct rtos_type FreeRTOS_rtos = { +struct rtos_type freertos_rtos = { .name = "FreeRTOS", - .detect_rtos = FreeRTOS_detect_rtos, - .create = FreeRTOS_create, - .update_threads = FreeRTOS_update_threads, - .get_thread_reg_list = FreeRTOS_get_thread_reg_list, - .get_symbol_list_to_lookup = FreeRTOS_get_symbol_list_to_lookup, + .detect_rtos = freertos_detect_rtos, + .create = freertos_create, + .update_threads = freertos_update_threads, + .get_thread_reg_list = freertos_get_thread_reg_list, + .get_symbol_list_to_lookup = freertos_get_symbol_list_to_lookup, }; -enum FreeRTOS_symbol_values { +enum freertos_symbol_values { FREERTOS_VAL_PX_CURRENT_TCB = 0, FREERTOS_VAL_PX_READY_TASKS_LISTS = 1, FREERTOS_VAL_X_DELAYED_TASK_LIST1 = 2, @@ -138,7 +134,7 @@ struct symbols { bool optional; }; -static const struct symbols FreeRTOS_symbol_list[] = { +static const struct symbols freertos_symbol_list[] = { { "pxCurrentTCB", false }, { "pxReadyTasksLists", false }, { "xDelayedTaskList1", false }, @@ -158,16 +154,16 @@ static const struct symbols FreeRTOS_symbol_list[] = { /* may be problems reading if sizes are not 32 bit long integers. */ /* test mallocs for failure */ -static int FreeRTOS_update_threads(struct rtos *rtos) +static int freertos_update_threads(struct rtos *rtos) { int retval; unsigned int tasks_found = 0; - const struct FreeRTOS_params *param; + const struct freertos_params *param; if (rtos->rtos_specific_params == NULL) return -1; - param = (const struct FreeRTOS_params *) rtos->rtos_specific_params; + param = (const struct freertos_params *) rtos->rtos_specific_params; if (rtos->symbols == NULL) { LOG_ERROR("No symbols for FreeRTOS"); @@ -400,11 +396,11 @@ static int FreeRTOS_update_threads(struct rtos *rtos) return 0; } -static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, +static int freertos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs) { int retval; - const struct FreeRTOS_params *param; + const struct freertos_params *param; int64_t stack_ptr = 0; if (rtos == NULL) @@ -416,7 +412,7 @@ static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, if (rtos->rtos_specific_params == NULL) return -1; - param = (const struct FreeRTOS_params *) rtos->rtos_specific_params; + param = (const struct freertos_params *) rtos->rtos_specific_params; /* Read the stack pointer */ uint32_t pointer_casts_are_bad; @@ -456,15 +452,15 @@ static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, if (cm4_fpu_enabled == 1) { /* Read the LR to decide between stacking with or without FPU */ - uint32_t LR_svc = 0; + uint32_t lr_svc = 0; retval = target_read_u32(rtos->target, stack_ptr + 0x20, - &LR_svc); + &lr_svc); if (retval != ERROR_OK) { LOG_OUTPUT("Error reading stack frame from FreeRTOS thread"); return retval; } - if ((LR_svc & 0x10) == 0) + if ((lr_svc & 0x10) == 0) return rtos_generic_stack_read(rtos->target, param->stacking_info_cm4f_fpu, stack_ptr, reg_list, num_regs); else return rtos_generic_stack_read(rtos->target, param->stacking_info_cm4f, stack_ptr, reg_list, num_regs); @@ -472,15 +468,15 @@ static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, return rtos_generic_stack_read(rtos->target, param->stacking_info_cm3, stack_ptr, reg_list, num_regs); } -static int FreeRTOS_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]) +static int freertos_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]) { unsigned int i; *symbol_list = calloc( - ARRAY_SIZE(FreeRTOS_symbol_list), sizeof(struct symbol_table_elem)); + ARRAY_SIZE(freertos_symbol_list), sizeof(struct symbol_table_elem)); - for (i = 0; i < ARRAY_SIZE(FreeRTOS_symbol_list); i++) { - (*symbol_list)[i].symbol_name = FreeRTOS_symbol_list[i].name; - (*symbol_list)[i].optional = FreeRTOS_symbol_list[i].optional; + for (i = 0; i < ARRAY_SIZE(freertos_symbol_list); i++) { + (*symbol_list)[i].symbol_name = freertos_symbol_list[i].name; + (*symbol_list)[i].optional = freertos_symbol_list[i].optional; } return 0; @@ -488,15 +484,15 @@ static int FreeRTOS_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_l #if 0 -static int FreeRTOS_set_current_thread(struct rtos *rtos, threadid_t thread_id) +static int freertos_set_current_thread(struct rtos *rtos, threadid_t thread_id) { return 0; } -static int FreeRTOS_get_thread_ascii_info(struct rtos *rtos, threadid_t thread_id, char **info) +static int freertos_get_thread_ascii_info(struct rtos *rtos, threadid_t thread_id, char **info) { int retval; - const struct FreeRTOS_params *param; + const struct freertos_params *param; if (rtos == NULL) return -1; @@ -507,7 +503,7 @@ static int FreeRTOS_get_thread_ascii_info(struct rtos *rtos, threadid_t thread_i if (rtos->rtos_specific_params == NULL) return -3; - param = (const struct FreeRTOS_params *) rtos->rtos_specific_params; + param = (const struct freertos_params *) rtos->rtos_specific_params; #define FREERTOS_THREAD_NAME_STR_SIZE (200) char tmp_str[FREERTOS_THREAD_NAME_STR_SIZE]; @@ -533,7 +529,7 @@ static int FreeRTOS_get_thread_ascii_info(struct rtos *rtos, threadid_t thread_i #endif -static bool FreeRTOS_detect_rtos(struct target *target) +static bool freertos_detect_rtos(struct target *target) { if ((target->rtos->symbols != NULL) && (target->rtos->symbols[FREERTOS_VAL_PX_READY_TASKS_LISTS].address != 0)) { @@ -543,11 +539,11 @@ static bool FreeRTOS_detect_rtos(struct target *target) return false; } -static int FreeRTOS_create(struct target *target) +static int freertos_create(struct target *target) { - for (unsigned int i = 0; i < ARRAY_SIZE(FreeRTOS_params_list); i++) - if (strcmp(FreeRTOS_params_list[i].target_name, target->type->name) == 0) { - target->rtos->rtos_specific_params = (void *)&FreeRTOS_params_list[i]; + for (unsigned int i = 0; i < ARRAY_SIZE(freertos_params_list); i++) + if (strcmp(freertos_params_list[i].target_name, target->type->name) == 0) { + target->rtos->rtos_specific_params = (void *)&freertos_params_list[i]; return 0; } diff --git a/src/rtos/ThreadX.c b/src/rtos/ThreadX.c index 3b4c2d701..5eadce9ca 100644 --- a/src/rtos/ThreadX.c +++ b/src/rtos/ThreadX.c @@ -35,20 +35,20 @@ static const struct rtos_register_stacking *get_stacking_info_arm926ejs(const st static int is_thread_id_valid(const struct rtos *rtos, int64_t thread_id); static int is_thread_id_valid_arm926ejs(const struct rtos *rtos, int64_t thread_id); -static bool ThreadX_detect_rtos(struct target *target); -static int ThreadX_create(struct target *target); -static int ThreadX_update_threads(struct rtos *rtos); -static int ThreadX_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs); -static int ThreadX_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]); +static bool threadx_detect_rtos(struct target *target); +static int threadx_create(struct target *target); +static int threadx_update_threads(struct rtos *rtos); +static int threadx_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs); +static int threadx_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]); -struct ThreadX_thread_state { +struct threadx_thread_state { int value; const char *desc; }; -static const struct ThreadX_thread_state ThreadX_thread_states[] = { +static const struct threadx_thread_state threadx_thread_states[] = { { 0, "Ready" }, { 1, "Completed" }, { 2, "Terminated" }, @@ -65,7 +65,7 @@ static const struct ThreadX_thread_state ThreadX_thread_states[] = { { 13, "Waiting - Mutex" }, }; -#define THREADX_NUM_STATES ARRAY_SIZE(ThreadX_thread_states) +#define THREADX_NUM_STATES ARRAY_SIZE(threadx_thread_states) #define ARM926EJS_REGISTERS_SIZE_SOLICITED (11 * 4) static const struct stack_register_offset rtos_threadx_arm926ejs_stack_offsets_solicited[] = { @@ -127,7 +127,7 @@ static const struct rtos_register_stacking rtos_threadx_arm926ejs_stacking[] = { }, }; -struct ThreadX_params { +struct threadx_params { const char *target_name; unsigned char pointer_width; unsigned char thread_stack_offset; @@ -140,7 +140,7 @@ struct ThreadX_params { int (*fn_is_thread_id_valid)(const struct rtos *rtos, int64_t thread_id); }; -static const struct ThreadX_params ThreadX_params_list[] = { +static const struct threadx_params threadx_params_list[] = { { "cortex_m", /* target_name */ 4, /* pointer_width; */ @@ -148,7 +148,7 @@ static const struct ThreadX_params ThreadX_params_list[] = { 40, /* thread_name_offset; */ 48, /* thread_state_offset; */ 136, /* thread_next_offset */ - &rtos_standard_Cortex_M3_stacking, /* stacking_info */ + &rtos_standard_cortex_m3_stacking, /* stacking_info */ 1, /* stacking_info_nb */ NULL, /* fn_get_stacking_info */ NULL, /* fn_is_thread_id_valid */ @@ -160,7 +160,7 @@ static const struct ThreadX_params ThreadX_params_list[] = { 40, /* thread_name_offset; */ 48, /* thread_state_offset; */ 136, /* thread_next_offset */ - &rtos_standard_Cortex_R4_stacking, /* stacking_info */ + &rtos_standard_cortex_r4_stacking, /* stacking_info */ 1, /* stacking_info_nb */ NULL, /* fn_get_stacking_info */ NULL, /* fn_is_thread_id_valid */ @@ -179,32 +179,32 @@ static const struct ThreadX_params ThreadX_params_list[] = { }, }; -enum ThreadX_symbol_values { +enum threadx_symbol_values { THREADX_VAL_TX_THREAD_CURRENT_PTR = 0, THREADX_VAL_TX_THREAD_CREATED_PTR = 1, THREADX_VAL_TX_THREAD_CREATED_COUNT = 2, }; -static const char * const ThreadX_symbol_list[] = { +static const char * const threadx_symbol_list[] = { "_tx_thread_current_ptr", "_tx_thread_created_ptr", "_tx_thread_created_count", NULL }; -const struct rtos_type ThreadX_rtos = { +const struct rtos_type threadx_rtos = { .name = "ThreadX", - .detect_rtos = ThreadX_detect_rtos, - .create = ThreadX_create, - .update_threads = ThreadX_update_threads, - .get_thread_reg_list = ThreadX_get_thread_reg_list, - .get_symbol_list_to_lookup = ThreadX_get_symbol_list_to_lookup, + .detect_rtos = threadx_detect_rtos, + .create = threadx_create, + .update_threads = threadx_update_threads, + .get_thread_reg_list = threadx_get_thread_reg_list, + .get_symbol_list_to_lookup = threadx_get_symbol_list_to_lookup, }; static const struct rtos_register_stacking *get_stacking_info(const struct rtos *rtos, int64_t stack_ptr) { - const struct ThreadX_params *param = (const struct ThreadX_params *) rtos->rtos_specific_params; + const struct threadx_params *param = (const struct threadx_params *) rtos->rtos_specific_params; if (param->fn_get_stacking_info != NULL) return param->fn_get_stacking_info(rtos, stack_ptr); @@ -214,12 +214,12 @@ static const struct rtos_register_stacking *get_stacking_info(const struct rtos static int is_thread_id_valid(const struct rtos *rtos, int64_t thread_id) { - const struct ThreadX_params *param; + const struct threadx_params *param; if (rtos->rtos_specific_params == NULL) return 0; /* invalid */ - param = (const struct ThreadX_params *) rtos->rtos_specific_params; + param = (const struct threadx_params *) rtos->rtos_specific_params; if (param->fn_is_thread_id_valid != NULL) return param->fn_is_thread_id_valid(rtos, thread_id); @@ -229,7 +229,7 @@ static int is_thread_id_valid(const struct rtos *rtos, int64_t thread_id) static const struct rtos_register_stacking *get_stacking_info_arm926ejs(const struct rtos *rtos, int64_t stack_ptr) { - const struct ThreadX_params *param = (const struct ThreadX_params *) rtos->rtos_specific_params; + const struct threadx_params *param = (const struct threadx_params *) rtos->rtos_specific_params; int retval; uint32_t flag; @@ -256,12 +256,12 @@ static int is_thread_id_valid_arm926ejs(const struct rtos *rtos, int64_t thread_ return (thread_id != 0 && thread_id != 1); } -static int ThreadX_update_threads(struct rtos *rtos) +static int threadx_update_threads(struct rtos *rtos) { int retval; int tasks_found = 0; int thread_list_size = 0; - const struct ThreadX_params *param; + const struct threadx_params *param; if (rtos == NULL) return -1; @@ -269,7 +269,7 @@ static int ThreadX_update_threads(struct rtos *rtos) if (rtos->rtos_specific_params == NULL) return -3; - param = (const struct ThreadX_params *) rtos->rtos_specific_params; + param = (const struct threadx_params *) rtos->rtos_specific_params; if (rtos->symbols == NULL) { LOG_ERROR("No symbols for ThreadX"); @@ -395,13 +395,13 @@ static int ThreadX_update_threads(struct rtos *rtos) } for (i = 0; (i < THREADX_NUM_STATES) && - (ThreadX_thread_states[i].value != thread_status); i++) { + (threadx_thread_states[i].value != thread_status); i++) { /* empty */ } const char *state_desc; if (i < THREADX_NUM_STATES) - state_desc = ThreadX_thread_states[i].desc; + state_desc = threadx_thread_states[i].desc; else state_desc = "Unknown state"; @@ -431,11 +431,11 @@ static int ThreadX_update_threads(struct rtos *rtos) return 0; } -static int ThreadX_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, +static int threadx_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs) { int retval; - const struct ThreadX_params *param; + const struct threadx_params *param; if (rtos == NULL) return -1; @@ -446,7 +446,7 @@ static int ThreadX_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, if (rtos->rtos_specific_params == NULL) return -3; - param = (const struct ThreadX_params *) rtos->rtos_specific_params; + param = (const struct threadx_params *) rtos->rtos_specific_params; /* Read the stack pointer */ int64_t stack_ptr = 0; @@ -477,19 +477,19 @@ static int ThreadX_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, return rtos_generic_stack_read(rtos->target, stacking_info, stack_ptr, reg_list, num_regs); } -static int ThreadX_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]) +static int threadx_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]) { unsigned int i; *symbol_list = calloc( - ARRAY_SIZE(ThreadX_symbol_list), sizeof(struct symbol_table_elem)); + ARRAY_SIZE(threadx_symbol_list), sizeof(struct symbol_table_elem)); - for (i = 0; i < ARRAY_SIZE(ThreadX_symbol_list); i++) - (*symbol_list)[i].symbol_name = ThreadX_symbol_list[i]; + for (i = 0; i < ARRAY_SIZE(threadx_symbol_list); i++) + (*symbol_list)[i].symbol_name = threadx_symbol_list[i]; return 0; } -static bool ThreadX_detect_rtos(struct target *target) +static bool threadx_detect_rtos(struct target *target) { if ((target->rtos->symbols != NULL) && (target->rtos->symbols[THREADX_VAL_TX_THREAD_CREATED_PTR].address != 0)) { @@ -501,12 +501,12 @@ static bool ThreadX_detect_rtos(struct target *target) #if 0 -static int ThreadX_set_current_thread(struct rtos *rtos, threadid_t thread_id) +static int threadx_set_current_thread(struct rtos *rtos, threadid_t thread_id) { return 0; } -static int ThreadX_get_thread_detail(struct rtos *rtos, +static int threadx_get_thread_detail(struct rtos *rtos, threadid_t thread_id, struct thread_detail *detail) { @@ -516,7 +516,7 @@ static int ThreadX_get_thread_detail(struct rtos *rtos, #define THREADX_THREAD_NAME_STR_SIZE (200) char tmp_str[THREADX_THREAD_NAME_STR_SIZE]; - const struct ThreadX_params *param; + const struct threadx_params *param; if (rtos == NULL) return -1; @@ -527,7 +527,7 @@ static int ThreadX_get_thread_detail(struct rtos *rtos, if (rtos->rtos_specific_params == NULL) return -3; - param = (const struct ThreadX_params *) rtos->rtos_specific_params; + param = (const struct threadx_params *) rtos->rtos_specific_params; if (rtos->symbols == NULL) { LOG_ERROR("No symbols for ThreadX"); @@ -576,13 +576,13 @@ static int ThreadX_get_thread_detail(struct rtos *rtos, } for (i = 0; (i < THREADX_NUM_STATES) && - (ThreadX_thread_states[i].value != thread_status); i++) { + (threadx_thread_states[i].value != thread_status); i++) { /* empty */ } char *state_desc; if (i < THREADX_NUM_STATES) - state_desc = ThreadX_thread_states[i].desc; + state_desc = threadx_thread_states[i].desc; else state_desc = "Unknown state"; @@ -595,11 +595,11 @@ static int ThreadX_get_thread_detail(struct rtos *rtos, #endif -static int ThreadX_create(struct target *target) +static int threadx_create(struct target *target) { - for (unsigned int i = 0; i < ARRAY_SIZE(ThreadX_params_list); i++) - if (strcmp(ThreadX_params_list[i].target_name, target->type->name) == 0) { - target->rtos->rtos_specific_params = (void *)&ThreadX_params_list[i]; + for (unsigned int i = 0; i < ARRAY_SIZE(threadx_params_list); i++) + if (strcmp(threadx_params_list[i].target_name, target->type->name) == 0) { + target->rtos->rtos_specific_params = (void *)&threadx_params_list[i]; target->rtos->current_thread = 0; target->rtos->thread_details = NULL; return 0; diff --git a/src/rtos/chibios.c b/src/rtos/chibios.c index 2a23017cd..cb471b485 100644 --- a/src/rtos/chibios.c +++ b/src/rtos/chibios.c @@ -62,9 +62,9 @@ struct chibios_chdebug { uint8_t cf_off_time; /**< @brief Offset of @p p_time field. */ }; -#define GET_CH_KERNEL_MAJOR(codedVersion) ((codedVersion >> 11) & 0x1f) -#define GET_CH_KERNEL_MINOR(codedVersion) ((codedVersion >> 6) & 0x1f) -#define GET_CH_KERNEL_PATCH(codedVersion) ((codedVersion >> 0) & 0x3f) +#define GET_CH_KERNEL_MAJOR(coded_version) ((coded_version >> 11) & 0x1f) +#define GET_CH_KERNEL_MINOR(coded_version) ((coded_version >> 6) & 0x1f) +#define GET_CH_KERNEL_PATCH(coded_version) ((coded_version >> 0) & 0x3f) /** * @brief ChibiOS thread states. @@ -184,10 +184,10 @@ static int chibios_update_memory_signature(struct rtos *rtos) } /* Convert endianness of version field */ - const uint8_t *versionTarget = (const uint8_t *) + const uint8_t *versiontarget = (const uint8_t *) &signature->ch_version; signature->ch_version = rtos->target->endianness == TARGET_LITTLE_ENDIAN ? - le_to_h_u32(versionTarget) : be_to_h_u32(versionTarget); + le_to_h_u32(versiontarget) : be_to_h_u32(versiontarget); const uint16_t ch_version = signature->ch_version; LOG_INFO("Successfully loaded memory map of ChibiOS/RT target " diff --git a/src/rtos/chromium-ec.c b/src/rtos/chromium-ec.c index 05d5b29b2..1c8f4e3f4 100644 --- a/src/rtos/chromium-ec.c +++ b/src/rtos/chromium-ec.c @@ -36,7 +36,7 @@ static const struct chromium_ec_params chromium_ec_params_list[] = { .task_offset_sp = 0, .task_offset_events = 4, .task_offset_runtime = 8, - .stacking = &rtos_standard_Cortex_M3_stacking, + .stacking = &rtos_standard_cortex_m3_stacking, }, { @@ -46,7 +46,7 @@ static const struct chromium_ec_params chromium_ec_params_list[] = { .task_offset_sp = 0, .task_offset_events = 4, .task_offset_runtime = 8, - .stacking = &rtos_standard_Cortex_M3_stacking, + .stacking = &rtos_standard_cortex_m3_stacking, }, }; diff --git a/src/rtos/eCos.c b/src/rtos/eCos.c index 1b1e73e60..a9feb8019 100644 --- a/src/rtos/eCos.c +++ b/src/rtos/eCos.c @@ -84,7 +84,7 @@ static const char * const eCos_symbol_list[] = { NULL }; -const struct rtos_type eCos_rtos = { +const struct rtos_type ecos_rtos = { .name = "eCos", .detect_rtos = eCos_detect_rtos, diff --git a/src/rtos/embKernel.c b/src/rtos/embKernel.c index 620d16baa..259399bc3 100644 --- a/src/rtos/embKernel.c +++ b/src/rtos/embKernel.c @@ -31,21 +31,21 @@ #define EMBKERNEL_MAX_THREAD_NAME_STR_SIZE (64) -static bool embKernel_detect_rtos(struct target *target); -static int embKernel_create(struct target *target); -static int embKernel_update_threads(struct rtos *rtos); -static int embKernel_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, +static bool embkernel_detect_rtos(struct target *target); +static int embkernel_create(struct target *target); +static int embkernel_update_threads(struct rtos *rtos); +static int embkernel_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs); -static int embKernel_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]); +static int embkernel_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]); -struct rtos_type embKernel_rtos = { +struct rtos_type embkernel_rtos = { .name = "embKernel", - .detect_rtos = embKernel_detect_rtos, - .create = embKernel_create, - .update_threads = embKernel_update_threads, + .detect_rtos = embkernel_detect_rtos, + .create = embkernel_create, + .update_threads = embkernel_update_threads, .get_thread_reg_list = - embKernel_get_thread_reg_list, - .get_symbol_list_to_lookup = embKernel_get_symbol_list_to_lookup, + embkernel_get_thread_reg_list, + .get_symbol_list_to_lookup = embkernel_get_symbol_list_to_lookup, }; enum { @@ -57,7 +57,7 @@ enum { SYMBOL_ID_S_CURRENT_TASK_COUNT = 5, }; -static const char * const embKernel_symbol_list[] = { +static const char * const embkernel_symbol_list[] = { "Rtos::sCurrentTask", "Rtos::sListReady", "Rtos::sListSleep", @@ -66,7 +66,7 @@ static const char * const embKernel_symbol_list[] = { "Rtos::sCurrentTaskCount", NULL }; -struct embKernel_params { +struct embkernel_params { const char *target_name; const unsigned char pointer_width; const unsigned char thread_count_width; @@ -80,7 +80,7 @@ struct embKernel_params { const struct rtos_register_stacking *stacking_info; }; -static const struct embKernel_params embKernel_params_list[] = { +static const struct embkernel_params embkernel_params_list[] = { { "cortex_m", /* target_name */ 4, /* pointer_width */ @@ -92,7 +92,7 @@ static const struct embKernel_params embKernel_params_list[] = { 4, /*thread_priority_width */ 4, /*iterable_next_offset */ 12, /*iterable_task_owner_offset */ - &rtos_embkernel_Cortex_M_stacking, /* stacking_info*/ + &rtos_embkernel_cortex_m_stacking, /* stacking_info*/ }, { "hla_target", /* target_name */ 4, /* pointer_width */ @@ -104,11 +104,11 @@ static const struct embKernel_params embKernel_params_list[] = { 4, /*thread_priority_width */ 4, /*iterable_next_offset */ 12, /*iterable_task_owner_offset */ - &rtos_embkernel_Cortex_M_stacking, /* stacking_info */ + &rtos_embkernel_cortex_m_stacking, /* stacking_info */ } }; -static bool embKernel_detect_rtos(struct target *target) +static bool embkernel_detect_rtos(struct target *target) { if (target->rtos->symbols != NULL) { if (target->rtos->symbols[SYMBOL_ID_S_CURRENT_TASK].address != 0) @@ -117,24 +117,24 @@ static bool embKernel_detect_rtos(struct target *target) return false; } -static int embKernel_create(struct target *target) +static int embkernel_create(struct target *target) { size_t i = 0; - while ((i < ARRAY_SIZE(embKernel_params_list)) && - (0 != strcmp(embKernel_params_list[i].target_name, target->type->name))) + while ((i < ARRAY_SIZE(embkernel_params_list)) && + (0 != strcmp(embkernel_params_list[i].target_name, target->type->name))) i++; - if (i >= ARRAY_SIZE(embKernel_params_list)) { + if (i >= ARRAY_SIZE(embkernel_params_list)) { LOG_WARNING("Could not find target \"%s\" in embKernel compatibility " "list", target->type->name); return -1; } - target->rtos->rtos_specific_params = (void *) &embKernel_params_list[i]; + target->rtos->rtos_specific_params = (void *) &embkernel_params_list[i]; return 0; } -static int embKernel_get_tasks_details(struct rtos *rtos, int64_t iterable, const struct embKernel_params *param, +static int embkernel_get_tasks_details(struct rtos *rtos, int64_t iterable, const struct embkernel_params *param, struct thread_detail *details, const char *state_str) { int64_t task = 0; @@ -181,11 +181,11 @@ static int embKernel_get_tasks_details(struct rtos *rtos, int64_t iterable, cons return 0; } -static int embKernel_update_threads(struct rtos *rtos) +static int embkernel_update_threads(struct rtos *rtos) { /* int i = 0; */ int retval; - const struct embKernel_params *param; + const struct embkernel_params *param; if (rtos == NULL) return -1; @@ -206,7 +206,7 @@ static int embKernel_update_threads(struct rtos *rtos) /* wipe out previous thread details if any */ rtos_free_threadlist(rtos); - param = (const struct embKernel_params *) rtos->rtos_specific_params; + param = (const struct embkernel_params *) rtos->rtos_specific_params; retval = target_read_buffer(rtos->target, rtos->symbols[SYMBOL_ID_S_CURRENT_TASK].address, param->pointer_width, (uint8_t *) &rtos->current_thread); @@ -237,7 +237,7 @@ static int embKernel_update_threads(struct rtos *rtos) return ERROR_FAIL; } - int threadIdx = 0; + int thread_idx = 0; /* Look for ready tasks */ for (int pri = 0; pri < max_used_priority; pri++) { /* Get first item in queue */ @@ -247,9 +247,9 @@ static int embKernel_update_threads(struct rtos *rtos) (uint8_t *) &iterable); if (retval != ERROR_OK) return retval; - for (; iterable && threadIdx < thread_list_size; threadIdx++) { + for (; iterable && thread_idx < thread_list_size; thread_idx++) { /* Get info from this iterable item */ - retval = embKernel_get_tasks_details(rtos, iterable, param, &rtos->thread_details[threadIdx], "Ready"); + retval = embkernel_get_tasks_details(rtos, iterable, param, &rtos->thread_details[thread_idx], "Ready"); if (retval != ERROR_OK) return retval; /* Get next iterable item */ @@ -265,9 +265,9 @@ static int embKernel_update_threads(struct rtos *rtos) (uint8_t *) &iterable); if (retval != ERROR_OK) return retval; - for (; iterable && threadIdx < thread_list_size; threadIdx++) { + for (; iterable && thread_idx < thread_list_size; thread_idx++) { /*Get info from this iterable item */ - retval = embKernel_get_tasks_details(rtos, iterable, param, &rtos->thread_details[threadIdx], "Sleeping"); + retval = embkernel_get_tasks_details(rtos, iterable, param, &rtos->thread_details[thread_idx], "Sleeping"); if (retval != ERROR_OK) return retval; /*Get next iterable item */ @@ -283,9 +283,9 @@ static int embKernel_update_threads(struct rtos *rtos) (uint8_t *) &iterable); if (retval != ERROR_OK) return retval; - for (; iterable && threadIdx < thread_list_size; threadIdx++) { + for (; iterable && thread_idx < thread_list_size; thread_idx++) { /* Get info from this iterable item */ - retval = embKernel_get_tasks_details(rtos, iterable, param, &rtos->thread_details[threadIdx], "Suspended"); + retval = embkernel_get_tasks_details(rtos, iterable, param, &rtos->thread_details[thread_idx], "Suspended"); if (retval != ERROR_OK) return retval; /*Get next iterable item */ @@ -296,16 +296,16 @@ static int embKernel_update_threads(struct rtos *rtos) } rtos->thread_count = 0; - rtos->thread_count = threadIdx; - LOG_OUTPUT("Found %u tasks\n", (unsigned int)threadIdx); + rtos->thread_count = thread_idx; + LOG_OUTPUT("Found %u tasks\n", (unsigned int)thread_idx); return 0; } -static int embKernel_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, +static int embkernel_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs) { int retval; - const struct embKernel_params *param; + const struct embkernel_params *param; int64_t stack_ptr = 0; if (rtos == NULL) @@ -317,7 +317,7 @@ static int embKernel_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, if (rtos->rtos_specific_params == NULL) return -1; - param = (const struct embKernel_params *) rtos->rtos_specific_params; + param = (const struct embkernel_params *) rtos->rtos_specific_params; /* Read the stack pointer */ retval = target_read_buffer(rtos->target, thread_id + param->thread_stack_offset, param->pointer_width, @@ -330,13 +330,13 @@ static int embKernel_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, return rtos_generic_stack_read(rtos->target, param->stacking_info, stack_ptr, reg_list, num_regs); } -static int embKernel_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]) +static int embkernel_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]) { unsigned int i; - *symbol_list = calloc(ARRAY_SIZE(embKernel_symbol_list), sizeof(struct symbol_table_elem)); + *symbol_list = calloc(ARRAY_SIZE(embkernel_symbol_list), sizeof(struct symbol_table_elem)); - for (i = 0; i < ARRAY_SIZE(embKernel_symbol_list); i++) - (*symbol_list)[i].symbol_name = embKernel_symbol_list[i]; + for (i = 0; i < ARRAY_SIZE(embkernel_symbol_list); i++) + (*symbol_list)[i].symbol_name = embkernel_symbol_list[i]; return 0; } diff --git a/src/rtos/linux.c b/src/rtos/linux.c index 4b96a931d..0a15efaac 100644 --- a/src/rtos/linux.c +++ b/src/rtos/linux.c @@ -260,7 +260,7 @@ static int linux_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list static char *linux_ps_command(struct target *target); -const struct rtos_type Linux_os = { +const struct rtos_type linux_rtos = { .name = "linux", .detect_rtos = linux_os_detect, .create = linux_os_create, @@ -431,8 +431,8 @@ static int get_current(struct target *target, int create) buf = reg_list[13]->value; val = get_buffer(target, buf); ti_addr = (val & 0xffffe000); - uint32_t TS_addr = ti_addr + 0xc; - retval = fill_buffer(target, TS_addr, buffer); + uint32_t ts_addr = ti_addr + 0xc; + retval = fill_buffer(target, ts_addr, buffer); if (retval == ERROR_OK) { uint32_t TS = get_buffer(target, buffer); @@ -1163,7 +1163,7 @@ static int linux_thread_extra_info(struct target *target, return ERROR_OK; } -static int linux_gdb_T_packet(struct connection *connection, +static int linux_gdb_t_packet(struct connection *connection, struct target *target, char const *packet, int packet_size) { int64_t threadid; @@ -1304,7 +1304,7 @@ static int linux_thread_packet(struct connection *connection, char const *packet switch (packet[0]) { case 'T': /* Is thread alive?*/ - linux_gdb_T_packet(connection, target, packet, packet_size); + linux_gdb_t_packet(connection, target, packet, packet_size); break; case 'H': /* Set current thread */ /* ( 'c' for step and continue, 'g' for all other operations )*/ diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c index 0374e9b5b..5fc958db2 100644 --- a/src/rtos/rtos.c +++ b/src/rtos/rtos.c @@ -27,30 +27,30 @@ #include "server/gdb_server.h" /* RTOSs */ -extern struct rtos_type FreeRTOS_rtos; -extern struct rtos_type ThreadX_rtos; -extern struct rtos_type eCos_rtos; -extern struct rtos_type Linux_os; +extern struct rtos_type freertos_rtos; +extern struct rtos_type threadx_rtos; +extern struct rtos_type ecos_rtos; +extern struct rtos_type linux_rtos; extern struct rtos_type chibios_rtos; extern struct rtos_type chromium_ec_rtos; -extern struct rtos_type embKernel_rtos; +extern struct rtos_type embkernel_rtos; extern struct rtos_type mqx_rtos; -extern struct rtos_type uCOS_III_rtos; +extern struct rtos_type ucos_iii_rtos; extern struct rtos_type nuttx_rtos; extern struct rtos_type hwthread_rtos; extern struct rtos_type riot_rtos; extern struct rtos_type zephyr_rtos; static struct rtos_type *rtos_types[] = { - &ThreadX_rtos, - &FreeRTOS_rtos, - &eCos_rtos, - &Linux_os, + &threadx_rtos, + &freertos_rtos, + &ecos_rtos, + &linux_rtos, &chibios_rtos, &chromium_ec_rtos, - &embKernel_rtos, + &embkernel_rtos, &mqx_rtos, - &uCOS_III_rtos, + &ucos_iii_rtos, &nuttx_rtos, &riot_rtos, &zephyr_rtos, diff --git a/src/rtos/rtos_embkernel_stackings.c b/src/rtos/rtos_embkernel_stackings.c index 543a8cd2a..cd4c22eac 100644 --- a/src/rtos/rtos_embkernel_stackings.c +++ b/src/rtos/rtos_embkernel_stackings.c @@ -24,7 +24,7 @@ #include "target/armv7m.h" #include "rtos_standard_stackings.h" -static const struct stack_register_offset rtos_embkernel_Cortex_M_stack_offsets[ARMV7M_NUM_CORE_REGS] = { +static const struct stack_register_offset rtos_embkernel_cortex_m_stack_offsets[ARMV7M_NUM_CORE_REGS] = { { ARMV7M_R0, 0x24, 32 }, /* r0 */ { ARMV7M_R1, 0x28, 32 }, /* r1 */ { ARMV7M_R2, 0x2c, 32 }, /* r2 */ @@ -44,10 +44,10 @@ static const struct stack_register_offset rtos_embkernel_Cortex_M_stack_offsets[ { ARMV7M_xPSR, 0x40, 32 }, /* xPSR */ }; -const struct rtos_register_stacking rtos_embkernel_Cortex_M_stacking = { +const struct rtos_register_stacking rtos_embkernel_cortex_m_stacking = { 0x40, /* stack_registers_size */ -1, /* stack_growth_direction */ ARMV7M_NUM_CORE_REGS, /* num_output_registers */ rtos_generic_stack_align8, /* stack_alignment */ - rtos_embkernel_Cortex_M_stack_offsets /* register_offsets */ + rtos_embkernel_cortex_m_stack_offsets /* register_offsets */ }; diff --git a/src/rtos/rtos_embkernel_stackings.h b/src/rtos/rtos_embkernel_stackings.h index 89a0c2f12..7850bebcd 100644 --- a/src/rtos/rtos_embkernel_stackings.h +++ b/src/rtos/rtos_embkernel_stackings.h @@ -25,6 +25,6 @@ #include "rtos.h" -extern const struct rtos_register_stacking rtos_embkernel_Cortex_M_stacking; +extern const struct rtos_register_stacking rtos_embkernel_cortex_m_stacking; #endif /* OPENOCD_RTOS_RTOS_EMBKERNEL_STACKINGS_H */ diff --git a/src/rtos/rtos_riot_stackings.c b/src/rtos/rtos_riot_stackings.c index 23f4d1786..98e02edfc 100644 --- a/src/rtos/rtos_riot_stackings.c +++ b/src/rtos/rtos_riot_stackings.c @@ -32,7 +32,7 @@ static int64_t rtos_riot_cortex_m_stack_align(struct target *target, int64_t stack_ptr) { const int XPSR_OFFSET = 0x40; - return rtos_Cortex_M_stack_align(target, stack_data, stacking, + return rtos_cortex_m_stack_align(target, stack_data, stacking, stack_ptr, XPSR_OFFSET); } diff --git a/src/rtos/rtos_standard_stackings.c b/src/rtos/rtos_standard_stackings.c index 7b054cbbc..90c642a00 100644 --- a/src/rtos/rtos_standard_stackings.c +++ b/src/rtos/rtos_standard_stackings.c @@ -23,7 +23,7 @@ #include "rtos.h" #include "target/armv7m.h" -static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[ARMV7M_NUM_CORE_REGS] = { +static const struct stack_register_offset rtos_standard_cortex_m3_stack_offsets[ARMV7M_NUM_CORE_REGS] = { { ARMV7M_R0, 0x20, 32 }, /* r0 */ { ARMV7M_R1, 0x24, 32 }, /* r1 */ { ARMV7M_R2, 0x28, 32 }, /* r2 */ @@ -43,7 +43,7 @@ static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[ { ARMV7M_xPSR, 0x3c, 32 }, /* xPSR */ }; -static const struct stack_register_offset rtos_standard_Cortex_M4F_stack_offsets[] = { +static const struct stack_register_offset rtos_standard_cortex_m4f_stack_offsets[] = { { ARMV7M_R0, 0x24, 32 }, /* r0 */ { ARMV7M_R1, 0x28, 32 }, /* r1 */ { ARMV7M_R2, 0x2c, 32 }, /* r2 */ @@ -63,7 +63,7 @@ static const struct stack_register_offset rtos_standard_Cortex_M4F_stack_offsets { ARMV7M_xPSR, 0x40, 32 }, /* xPSR */ }; -static const struct stack_register_offset rtos_standard_Cortex_M4F_FPU_stack_offsets[] = { +static const struct stack_register_offset rtos_standard_cortex_m4f_fpu_stack_offsets[] = { { ARMV7M_R0, 0x64, 32 }, /* r0 */ { ARMV7M_R1, 0x68, 32 }, /* r1 */ { ARMV7M_R2, 0x6c, 32 }, /* r2 */ @@ -84,7 +84,7 @@ static const struct stack_register_offset rtos_standard_Cortex_M4F_FPU_stack_off }; -static const struct stack_register_offset rtos_standard_Cortex_R4_stack_offsets[] = { +static const struct stack_register_offset rtos_standard_cortex_r4_stack_offsets[] = { { 0, 0x08, 32 }, /* r0 (a1) */ { 1, 0x0c, 32 }, /* r1 (a2) */ { 2, 0x10, 32 }, /* r2 (a3) */ @@ -113,7 +113,7 @@ static const struct stack_register_offset rtos_standard_Cortex_R4_stack_offsets[ { 26, 0x04, 32 }, /* CSPR */ }; -static const struct stack_register_offset rtos_standard_NDS32_N1068_stack_offsets[] = { +static const struct stack_register_offset rtos_standard_nds32_n1068_stack_offsets[] = { { 0, 0x88, 32 }, /* R0 */ { 1, 0x8C, 32 }, /* R1 */ { 2, 0x14, 32 }, /* R2 */ @@ -199,7 +199,7 @@ int64_t rtos_generic_stack_align8(struct target *target, * This is just a helper function for use in the calculate_process_stack * function for a given architecture/rtos. */ -int64_t rtos_Cortex_M_stack_align(struct target *target, +int64_t rtos_cortex_m_stack_align(struct target *target, const uint8_t *stack_data, const struct rtos_register_stacking *stacking, int64_t stack_ptr, size_t xpsr_offset) { @@ -220,70 +220,70 @@ int64_t rtos_Cortex_M_stack_align(struct target *target, return new_stack_ptr; } -static int64_t rtos_standard_Cortex_M3_stack_align(struct target *target, +static int64_t rtos_standard_cortex_m3_stack_align(struct target *target, const uint8_t *stack_data, const struct rtos_register_stacking *stacking, int64_t stack_ptr) { const int XPSR_OFFSET = 0x3c; - return rtos_Cortex_M_stack_align(target, stack_data, stacking, + return rtos_cortex_m_stack_align(target, stack_data, stacking, stack_ptr, XPSR_OFFSET); } -static int64_t rtos_standard_Cortex_M4F_stack_align(struct target *target, +static int64_t rtos_standard_cortex_m4f_stack_align(struct target *target, const uint8_t *stack_data, const struct rtos_register_stacking *stacking, int64_t stack_ptr) { const int XPSR_OFFSET = 0x40; - return rtos_Cortex_M_stack_align(target, stack_data, stacking, + return rtos_cortex_m_stack_align(target, stack_data, stacking, stack_ptr, XPSR_OFFSET); } -static int64_t rtos_standard_Cortex_M4F_FPU_stack_align(struct target *target, +static int64_t rtos_standard_cortex_m4f_fpu_stack_align(struct target *target, const uint8_t *stack_data, const struct rtos_register_stacking *stacking, int64_t stack_ptr) { const int XPSR_OFFSET = 0x80; - return rtos_Cortex_M_stack_align(target, stack_data, stacking, + return rtos_cortex_m_stack_align(target, stack_data, stacking, stack_ptr, XPSR_OFFSET); } -const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = { +const struct rtos_register_stacking rtos_standard_cortex_m3_stacking = { 0x40, /* stack_registers_size */ -1, /* stack_growth_direction */ ARMV7M_NUM_CORE_REGS, /* num_output_registers */ - rtos_standard_Cortex_M3_stack_align, /* stack_alignment */ - rtos_standard_Cortex_M3_stack_offsets /* register_offsets */ + rtos_standard_cortex_m3_stack_align, /* stack_alignment */ + rtos_standard_cortex_m3_stack_offsets /* register_offsets */ }; -const struct rtos_register_stacking rtos_standard_Cortex_M4F_stacking = { +const struct rtos_register_stacking rtos_standard_cortex_m4f_stacking = { 0x44, /* stack_registers_size 4 more for LR*/ -1, /* stack_growth_direction */ ARMV7M_NUM_CORE_REGS, /* num_output_registers */ - rtos_standard_Cortex_M4F_stack_align, /* stack_alignment */ - rtos_standard_Cortex_M4F_stack_offsets /* register_offsets */ + rtos_standard_cortex_m4f_stack_align, /* stack_alignment */ + rtos_standard_cortex_m4f_stack_offsets /* register_offsets */ }; -const struct rtos_register_stacking rtos_standard_Cortex_M4F_FPU_stacking = { +const struct rtos_register_stacking rtos_standard_cortex_m4f_fpu_stacking = { 0xcc, /* stack_registers_size 4 more for LR + 48 more for FPU S0-S15 register*/ -1, /* stack_growth_direction */ ARMV7M_NUM_CORE_REGS, /* num_output_registers */ - rtos_standard_Cortex_M4F_FPU_stack_align, /* stack_alignment */ - rtos_standard_Cortex_M4F_FPU_stack_offsets /* register_offsets */ + rtos_standard_cortex_m4f_fpu_stack_align, /* stack_alignment */ + rtos_standard_cortex_m4f_fpu_stack_offsets /* register_offsets */ }; -const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking = { +const struct rtos_register_stacking rtos_standard_cortex_r4_stacking = { 0x48, /* stack_registers_size */ -1, /* stack_growth_direction */ 26, /* num_output_registers */ rtos_generic_stack_align8, /* stack_alignment */ - rtos_standard_Cortex_R4_stack_offsets /* register_offsets */ + rtos_standard_cortex_r4_stack_offsets /* register_offsets */ }; -const struct rtos_register_stacking rtos_standard_NDS32_N1068_stacking = { +const struct rtos_register_stacking rtos_standard_nds32_n1068_stacking = { 0x90, /* stack_registers_size */ -1, /* stack_growth_direction */ 32, /* num_output_registers */ rtos_generic_stack_align8, /* stack_alignment */ - rtos_standard_NDS32_N1068_stack_offsets /* register_offsets */ + rtos_standard_nds32_n1068_stack_offsets /* register_offsets */ }; diff --git a/src/rtos/rtos_standard_stackings.h b/src/rtos/rtos_standard_stackings.h index 6971efd1e..ad319d2a0 100644 --- a/src/rtos/rtos_standard_stackings.h +++ b/src/rtos/rtos_standard_stackings.h @@ -25,15 +25,15 @@ #include "rtos.h" -extern const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking; -extern const struct rtos_register_stacking rtos_standard_Cortex_M4F_stacking; -extern const struct rtos_register_stacking rtos_standard_Cortex_M4F_FPU_stacking; -extern const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking; -extern const struct rtos_register_stacking rtos_standard_NDS32_N1068_stacking; +extern const struct rtos_register_stacking rtos_standard_cortex_m3_stacking; +extern const struct rtos_register_stacking rtos_standard_cortex_m4f_stacking; +extern const struct rtos_register_stacking rtos_standard_cortex_m4f_fpu_stacking; +extern const struct rtos_register_stacking rtos_standard_cortex_r4_stacking; +extern const struct rtos_register_stacking rtos_standard_nds32_n1068_stacking; int64_t rtos_generic_stack_align8(struct target *target, const uint8_t *stack_data, const struct rtos_register_stacking *stacking, int64_t stack_ptr); -int64_t rtos_Cortex_M_stack_align(struct target *target, +int64_t rtos_cortex_m_stack_align(struct target *target, const uint8_t *stack_data, const struct rtos_register_stacking *stacking, int64_t stack_ptr, size_t xpsr_offset); diff --git a/src/rtos/rtos_ucos_iii_stackings.c b/src/rtos/rtos_ucos_iii_stackings.c index d093563ba..4ae0d7dc8 100644 --- a/src/rtos/rtos_ucos_iii_stackings.c +++ b/src/rtos/rtos_ucos_iii_stackings.c @@ -26,7 +26,7 @@ #include <target/armv7m.h> #include <target/esirisc.h> -static const struct stack_register_offset rtos_uCOS_III_Cortex_M_stack_offsets[] = { +static const struct stack_register_offset rtos_ucos_iii_cortex_m_stack_offsets[] = { { ARMV7M_R0, 0x20, 32 }, /* r0 */ { ARMV7M_R1, 0x24, 32 }, /* r1 */ { ARMV7M_R2, 0x28, 32 }, /* r2 */ @@ -46,7 +46,7 @@ static const struct stack_register_offset rtos_uCOS_III_Cortex_M_stack_offsets[] { ARMV7M_xPSR, 0x3c, 32 }, /* xPSR */ }; -static const struct stack_register_offset rtos_uCOS_III_eSi_RISC_stack_offsets[] = { +static const struct stack_register_offset rtos_ucos_iii_esi_risc_stack_offsets[] = { { ESIRISC_SP, -2, 32 }, /* sp */ { ESIRISC_RA, 0x48, 32 }, /* ra */ { ESIRISC_R2, 0x44, 32 }, /* r2 */ @@ -67,18 +67,18 @@ static const struct stack_register_offset rtos_uCOS_III_eSi_RISC_stack_offsets[] { ESIRISC_CAS, 0x08, 32 }, /* CAS */ }; -const struct rtos_register_stacking rtos_uCOS_III_Cortex_M_stacking = { +const struct rtos_register_stacking rtos_ucos_iii_cortex_m_stacking = { 0x40, /* stack_registers_size */ -1, /* stack_growth_direction */ - ARRAY_SIZE(rtos_uCOS_III_Cortex_M_stack_offsets), /* num_output_registers */ + ARRAY_SIZE(rtos_ucos_iii_cortex_m_stack_offsets), /* num_output_registers */ rtos_generic_stack_align8, /* stack_alignment */ - rtos_uCOS_III_Cortex_M_stack_offsets /* register_offsets */ + rtos_ucos_iii_cortex_m_stack_offsets /* register_offsets */ }; -const struct rtos_register_stacking rtos_uCOS_III_eSi_RISC_stacking = { +const struct rtos_register_stacking rtos_ucos_iii_esi_risc_stacking = { 0x4c, /* stack_registers_size */ -1, /* stack_growth_direction */ - ARRAY_SIZE(rtos_uCOS_III_eSi_RISC_stack_offsets), /* num_output_registers */ + ARRAY_SIZE(rtos_ucos_iii_esi_risc_stack_offsets), /* num_output_registers */ NULL, /* stack_alignment */ - rtos_uCOS_III_eSi_RISC_stack_offsets /* register_offsets */ + rtos_ucos_iii_esi_risc_stack_offsets /* register_offsets */ }; diff --git a/src/rtos/rtos_ucos_iii_stackings.h b/src/rtos/rtos_ucos_iii_stackings.h index a9398138b..f2f120fd9 100644 --- a/src/rtos/rtos_ucos_iii_stackings.h +++ b/src/rtos/rtos_ucos_iii_stackings.h @@ -25,7 +25,7 @@ #include <rtos/rtos.h> -extern const struct rtos_register_stacking rtos_uCOS_III_Cortex_M_stacking; -extern const struct rtos_register_stacking rtos_uCOS_III_eSi_RISC_stacking; +extern const struct rtos_register_stacking rtos_ucos_iii_cortex_m_stacking; +extern const struct rtos_register_stacking rtos_ucos_iii_esi_risc_stacking; #endif /* OPENOCD_RTOS_RTOS_UCOS_III_STACKINGS_H */ diff --git a/src/rtos/uCOS-III.c b/src/rtos/uCOS-III.c index 1aed4846f..26b53a927 100644 --- a/src/rtos/uCOS-III.c +++ b/src/rtos/uCOS-III.c @@ -37,7 +37,7 @@ #define UCOS_III_MAX_THREADS 256 #endif -struct uCOS_III_params { +struct ucos_iii_params { const char *target_name; const unsigned char pointer_width; symbol_address_t thread_stack_offset; @@ -53,7 +53,7 @@ struct uCOS_III_params { symbol_address_t threads[]; }; -static const struct uCOS_III... [truncated message content] |
From: OpenOCD-Gerrit <ope...@us...> - 2021-07-02 16:12:05
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 3ad52aa34f6763dddc2a903c255a09f7c7e21ed7 (commit) via 11a621c7525fb295d7aa9a786a761e43377104fa (commit) via 1887e2a273797af3d5625ea3d78df3f9ce27ead3 (commit) via 20ee64ae4bc70b836664465daebe828caca7ccbc (commit) via 9e358ac2c0a759982064dd53a974b50ebaeb19f5 (commit) from 3d135a5c70db67ed13cc93eeab0b700f6ef8a412 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 3ad52aa34f6763dddc2a903c255a09f7c7e21ed7 Author: Antonio Borneo <bor...@gm...> Date: Tue May 25 09:53:15 2021 +0200 rtos: convert CamelCase enum in uppercase The eCos code is not part of this patch to prevent conflicts with patches currently under review. Change-Id: I71369165f2eef419b83a79ffcff50287f77949c6 Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6304 Tested-by: jenkins diff --git a/src/rtos/FreeRTOS.c b/src/rtos/FreeRTOS.c index 30c6e34cb..24b829070 100644 --- a/src/rtos/FreeRTOS.c +++ b/src/rtos/FreeRTOS.c @@ -120,17 +120,17 @@ struct rtos_type FreeRTOS_rtos = { }; enum FreeRTOS_symbol_values { - FreeRTOS_VAL_pxCurrentTCB = 0, - FreeRTOS_VAL_pxReadyTasksLists = 1, - FreeRTOS_VAL_xDelayedTaskList1 = 2, - FreeRTOS_VAL_xDelayedTaskList2 = 3, - FreeRTOS_VAL_pxDelayedTaskList = 4, - FreeRTOS_VAL_pxOverflowDelayedTaskList = 5, - FreeRTOS_VAL_xPendingReadyList = 6, - FreeRTOS_VAL_xTasksWaitingTermination = 7, - FreeRTOS_VAL_xSuspendedTaskList = 8, - FreeRTOS_VAL_uxCurrentNumberOfTasks = 9, - FreeRTOS_VAL_uxTopUsedPriority = 10, + FREERTOS_VAL_PX_CURRENT_TCB = 0, + FREERTOS_VAL_PX_READY_TASKS_LISTS = 1, + FREERTOS_VAL_X_DELAYED_TASK_LIST1 = 2, + FREERTOS_VAL_X_DELAYED_TASK_LIST2 = 3, + FREERTOS_VAL_PX_DELAYED_TASK_LIST = 4, + FREERTOS_VAL_PX_OVERFLOW_DELAYED_TASK_LIST = 5, + FREERTOS_VAL_X_PENDING_READY_LIST = 6, + FREERTOS_VAL_X_TASKS_WAITING_TERMINATION = 7, + FREERTOS_VAL_X_SUSPENDED_TASK_LIST = 8, + FREERTOS_VAL_UX_CURRENT_NUMBER_OF_TASKS = 9, + FREERTOS_VAL_UX_TOP_USED_PRIORITY = 10, }; struct symbols { @@ -174,17 +174,17 @@ static int FreeRTOS_update_threads(struct rtos *rtos) return -3; } - if (rtos->symbols[FreeRTOS_VAL_uxCurrentNumberOfTasks].address == 0) { + if (rtos->symbols[FREERTOS_VAL_UX_CURRENT_NUMBER_OF_TASKS].address == 0) { LOG_ERROR("Don't have the number of threads in FreeRTOS"); return -2; } uint32_t thread_list_size = 0; retval = target_read_u32(rtos->target, - rtos->symbols[FreeRTOS_VAL_uxCurrentNumberOfTasks].address, + rtos->symbols[FREERTOS_VAL_UX_CURRENT_NUMBER_OF_TASKS].address, &thread_list_size); LOG_DEBUG("FreeRTOS: Read uxCurrentNumberOfTasks at 0x%" PRIx64 ", value %" PRIu32, - rtos->symbols[FreeRTOS_VAL_uxCurrentNumberOfTasks].address, + rtos->symbols[FREERTOS_VAL_UX_CURRENT_NUMBER_OF_TASKS].address, thread_list_size); if (retval != ERROR_OK) { @@ -198,7 +198,7 @@ static int FreeRTOS_update_threads(struct rtos *rtos) /* read the current thread */ uint32_t pointer_casts_are_bad; retval = target_read_u32(rtos->target, - rtos->symbols[FreeRTOS_VAL_pxCurrentTCB].address, + rtos->symbols[FREERTOS_VAL_PX_CURRENT_TCB].address, &pointer_casts_are_bad); if (retval != ERROR_OK) { LOG_ERROR("Error reading current thread in FreeRTOS thread list"); @@ -206,7 +206,7 @@ static int FreeRTOS_update_threads(struct rtos *rtos) } rtos->current_thread = pointer_casts_are_bad; LOG_DEBUG("FreeRTOS: Read pxCurrentTCB at 0x%" PRIx64 ", value 0x%" PRIx64, - rtos->symbols[FreeRTOS_VAL_pxCurrentTCB].address, + rtos->symbols[FREERTOS_VAL_PX_CURRENT_TCB].address, rtos->current_thread); if ((thread_list_size == 0) || (rtos->current_thread == 0)) { @@ -243,18 +243,18 @@ static int FreeRTOS_update_threads(struct rtos *rtos) } /* Find out how many lists are needed to be read from pxReadyTasksLists, */ - if (rtos->symbols[FreeRTOS_VAL_uxTopUsedPriority].address == 0) { + if (rtos->symbols[FREERTOS_VAL_UX_TOP_USED_PRIORITY].address == 0) { LOG_ERROR("FreeRTOS: uxTopUsedPriority is not defined, consult the OpenOCD manual for a work-around"); return ERROR_FAIL; } uint32_t top_used_priority = 0; retval = target_read_u32(rtos->target, - rtos->symbols[FreeRTOS_VAL_uxTopUsedPriority].address, + rtos->symbols[FREERTOS_VAL_UX_TOP_USED_PRIORITY].address, &top_used_priority); if (retval != ERROR_OK) return retval; LOG_DEBUG("FreeRTOS: Read uxTopUsedPriority at 0x%" PRIx64 ", value %" PRIu32, - rtos->symbols[FreeRTOS_VAL_uxTopUsedPriority].address, + rtos->symbols[FREERTOS_VAL_UX_TOP_USED_PRIORITY].address, top_used_priority); if (top_used_priority > FREERTOS_MAX_PRIORITIES) { LOG_ERROR("FreeRTOS top used priority is unreasonably big, not proceeding: %" PRIu32, @@ -278,14 +278,14 @@ static int FreeRTOS_update_threads(struct rtos *rtos) unsigned int num_lists; for (num_lists = 0; num_lists < config_max_priorities; num_lists++) - list_of_lists[num_lists] = rtos->symbols[FreeRTOS_VAL_pxReadyTasksLists].address + + list_of_lists[num_lists] = rtos->symbols[FREERTOS_VAL_PX_READY_TASKS_LISTS].address + num_lists * param->list_width; - list_of_lists[num_lists++] = rtos->symbols[FreeRTOS_VAL_xDelayedTaskList1].address; - list_of_lists[num_lists++] = rtos->symbols[FreeRTOS_VAL_xDelayedTaskList2].address; - list_of_lists[num_lists++] = rtos->symbols[FreeRTOS_VAL_xPendingReadyList].address; - list_of_lists[num_lists++] = rtos->symbols[FreeRTOS_VAL_xSuspendedTaskList].address; - list_of_lists[num_lists++] = rtos->symbols[FreeRTOS_VAL_xTasksWaitingTermination].address; + list_of_lists[num_lists++] = rtos->symbols[FREERTOS_VAL_X_DELAYED_TASK_LIST1].address; + list_of_lists[num_lists++] = rtos->symbols[FREERTOS_VAL_X_DELAYED_TASK_LIST2].address; + list_of_lists[num_lists++] = rtos->symbols[FREERTOS_VAL_X_PENDING_READY_LIST].address; + list_of_lists[num_lists++] = rtos->symbols[FREERTOS_VAL_X_SUSPENDED_TASK_LIST].address; + list_of_lists[num_lists++] = rtos->symbols[FREERTOS_VAL_X_TASKS_WAITING_TERMINATION].address; for (unsigned int i = 0; i < num_lists; i++) { if (list_of_lists[i] == 0) @@ -536,7 +536,7 @@ static int FreeRTOS_get_thread_ascii_info(struct rtos *rtos, threadid_t thread_i static bool FreeRTOS_detect_rtos(struct target *target) { if ((target->rtos->symbols != NULL) && - (target->rtos->symbols[FreeRTOS_VAL_pxReadyTasksLists].address != 0)) { + (target->rtos->symbols[FREERTOS_VAL_PX_READY_TASKS_LISTS].address != 0)) { /* looks like FreeRTOS */ return true; } diff --git a/src/rtos/ThreadX.c b/src/rtos/ThreadX.c index 53a74f807..3b4c2d701 100644 --- a/src/rtos/ThreadX.c +++ b/src/rtos/ThreadX.c @@ -180,9 +180,9 @@ static const struct ThreadX_params ThreadX_params_list[] = { }; enum ThreadX_symbol_values { - ThreadX_VAL_tx_thread_current_ptr = 0, - ThreadX_VAL_tx_thread_created_ptr = 1, - ThreadX_VAL_tx_thread_created_count = 2, + THREADX_VAL_TX_THREAD_CURRENT_PTR = 0, + THREADX_VAL_TX_THREAD_CREATED_PTR = 1, + THREADX_VAL_TX_THREAD_CREATED_COUNT = 2, }; static const char * const ThreadX_symbol_list[] = { @@ -276,14 +276,14 @@ static int ThreadX_update_threads(struct rtos *rtos) return -4; } - if (rtos->symbols[ThreadX_VAL_tx_thread_created_count].address == 0) { + if (rtos->symbols[THREADX_VAL_TX_THREAD_CREATED_COUNT].address == 0) { LOG_ERROR("Don't have the number of threads in ThreadX"); return -2; } /* read the number of threads */ retval = target_read_buffer(rtos->target, - rtos->symbols[ThreadX_VAL_tx_thread_created_count].address, + rtos->symbols[THREADX_VAL_TX_THREAD_CREATED_COUNT].address, 4, (uint8_t *)&thread_list_size); @@ -297,7 +297,7 @@ static int ThreadX_update_threads(struct rtos *rtos) /* read the current thread id */ retval = target_read_buffer(rtos->target, - rtos->symbols[ThreadX_VAL_tx_thread_current_ptr].address, + rtos->symbols[THREADX_VAL_TX_THREAD_CURRENT_PTR].address, 4, (uint8_t *)&rtos->current_thread); @@ -334,7 +334,7 @@ static int ThreadX_update_threads(struct rtos *rtos) /* Read the pointer to the first thread */ int64_t thread_ptr = 0; retval = target_read_buffer(rtos->target, - rtos->symbols[ThreadX_VAL_tx_thread_created_ptr].address, + rtos->symbols[THREADX_VAL_TX_THREAD_CREATED_PTR].address, param->pointer_width, (uint8_t *)&thread_ptr); if (retval != ERROR_OK) { @@ -492,7 +492,7 @@ static int ThreadX_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_li static bool ThreadX_detect_rtos(struct target *target) { if ((target->rtos->symbols != NULL) && - (target->rtos->symbols[ThreadX_VAL_tx_thread_created_ptr].address != 0)) { + (target->rtos->symbols[THREADX_VAL_TX_THREAD_CREATED_PTR].address != 0)) { /* looks like ThreadX */ return true; } diff --git a/src/rtos/chromium-ec.c b/src/rtos/chromium-ec.c index 1476f1969..05d5b29b2 100644 --- a/src/rtos/chromium-ec.c +++ b/src/rtos/chromium-ec.c @@ -62,13 +62,13 @@ static const char * const chromium_ec_symbol_list[] = { }; enum chromium_ec_symbol_values { - CHROMIUM_EC_VAL_start_called = 0, - CHROMIUM_EC_VAL_current_task, - CHROMIUM_EC_VAL_tasks, - CHROMIUM_EC_VAL_tasks_enabled, - CHROMIUM_EC_VAL_tasks_ready, - CHROMIUM_EC_VAL_task_names, - CHROMIUM_EC_VAL_build_info, + CHROMIUM_EC_VAL_START_CALLED = 0, + CHROMIUM_EC_VAL_CURRENT_TASK, + CHROMIUM_EC_VAL_TASKS, + CHROMIUM_EC_VAL_TASKS_ENABLED, + CHROMIUM_EC_VAL_TASKS_READY, + CHROMIUM_EC_VAL_TASK_NAMES, + CHROMIUM_EC_VAL_BUILD_INFO, CHROMIUM_EC_VAL_COUNT, }; @@ -84,7 +84,7 @@ static bool chromium_ec_detect_rtos(struct target *target) if (!target || !target->rtos || !target->rtos->symbols) return false; - for (sym = CHROMIUM_EC_VAL_start_called; + for (sym = CHROMIUM_EC_VAL_START_CALLED; sym < CHROMIUM_EC_VAL_COUNT; sym++) { if (target->rtos->symbols[sym].address) { LOG_DEBUG("Chromium-EC: Symbol \"%s\" found", @@ -97,7 +97,7 @@ static bool chromium_ec_detect_rtos(struct target *target) } ret = target_read_buffer(target, - target->rtos->symbols[CHROMIUM_EC_VAL_build_info].address, + target->rtos->symbols[CHROMIUM_EC_VAL_BUILD_INFO].address, sizeof(build_info_buf), (uint8_t *)build_info_buf); @@ -107,7 +107,7 @@ static bool chromium_ec_detect_rtos(struct target *target) LOG_INFO("Chromium-EC: Buildinfo: %s", build_info_buf); return target->rtos->symbols && - target->rtos->symbols[CHROMIUM_EC_VAL_start_called].address; + target->rtos->symbols[CHROMIUM_EC_VAL_START_CALLED].address; } static int chromium_ec_create(struct target *target) @@ -143,7 +143,7 @@ static int chromium_ec_get_current_task_ptr(struct rtos *rtos, uint32_t *current return ERROR_FAIL; return target_read_u32(rtos->target, - rtos->symbols[CHROMIUM_EC_VAL_current_task].address, + rtos->symbols[CHROMIUM_EC_VAL_CURRENT_TASK].address, current_task); } @@ -153,7 +153,7 @@ static int chromium_ec_get_num_tasks(struct rtos *rtos, int *num_tasks) int ret, t, found; ret = target_read_u32(rtos->target, - rtos->symbols[CHROMIUM_EC_VAL_tasks_enabled].address, + rtos->symbols[CHROMIUM_EC_VAL_TASKS_ENABLED].address, &tasks_enabled); if (ret != ERROR_OK) { LOG_ERROR("Failed to determine #of tasks"); @@ -213,7 +213,7 @@ static int chromium_ec_update_threads(struct rtos *rtos) /* One check if task switching has started ... */ start_called = 0; - ret = target_read_u32(rtos->target, rtos->symbols[CHROMIUM_EC_VAL_start_called].address, + ret = target_read_u32(rtos->target, rtos->symbols[CHROMIUM_EC_VAL_START_CALLED].address, &start_called); if (ret != ERROR_OK) { LOG_ERROR("Failed to load start_called"); @@ -241,7 +241,7 @@ static int chromium_ec_update_threads(struct rtos *rtos) } tasks_enabled = 0; - ret = target_read_u32(rtos->target, rtos->symbols[CHROMIUM_EC_VAL_tasks_enabled].address, + ret = target_read_u32(rtos->target, rtos->symbols[CHROMIUM_EC_VAL_TASKS_ENABLED].address, &tasks_enabled); if (ret != ERROR_OK) { LOG_ERROR("Failed to load tasks_enabled"); @@ -249,14 +249,14 @@ static int chromium_ec_update_threads(struct rtos *rtos) } tasks_ready = 0; - ret = target_read_u32(rtos->target, rtos->symbols[CHROMIUM_EC_VAL_tasks_ready].address, + ret = target_read_u32(rtos->target, rtos->symbols[CHROMIUM_EC_VAL_TASKS_READY].address, &tasks_ready); if (ret != ERROR_OK) { LOG_ERROR("Failed to load tasks_ready"); return ret; } - thread_ptr = rtos->symbols[CHROMIUM_EC_VAL_tasks].address; + thread_ptr = rtos->symbols[CHROMIUM_EC_VAL_TASKS].address; tasks_found = 0; for (t = 0; t < CROS_EC_MAX_TASKS; t++) { @@ -268,7 +268,7 @@ static int chromium_ec_update_threads(struct rtos *rtos) rtos->thread_details[tasks_found].threadid = thread_ptr; ret = target_read_u32(rtos->target, - rtos->symbols[CHROMIUM_EC_VAL_task_names].address + + rtos->symbols[CHROMIUM_EC_VAL_TASK_NAMES].address + params->ptr_size * t, &name_ptr); if (ret != ERROR_OK) { LOG_ERROR("Failed to read name_ptr"); @@ -348,7 +348,7 @@ static int chromium_ec_get_thread_reg_list(struct rtos *rtos, return ERROR_FAIL; ret = target_read_u32(rtos->target, - rtos->symbols[CHROMIUM_EC_VAL_tasks].address + + rtos->symbols[CHROMIUM_EC_VAL_TASKS].address + params->task_offset_next * t, &stack_ptr); if (ret != ERROR_OK) { diff --git a/src/rtos/embKernel.c b/src/rtos/embKernel.c index 994cbc091..620d16baa 100644 --- a/src/rtos/embKernel.c +++ b/src/rtos/embKernel.c @@ -49,12 +49,12 @@ struct rtos_type embKernel_rtos = { }; enum { - SYMBOL_ID_sCurrentTask = 0, - SYMBOL_ID_sListReady = 1, - SYMBOL_ID_sListSleep = 2, - SYMBOL_ID_sListSuspended = 3, - SYMBOL_ID_sMaxPriorities = 4, - SYMBOL_ID_sCurrentTaskCount = 5, + SYMBOL_ID_S_CURRENT_TASK = 0, + SYMBOL_ID_S_LIST_READY = 1, + SYMBOL_ID_S_LIST_SLEEP = 2, + SYMBOL_ID_S_LIST_SUSPENDED = 3, + SYMBOL_ID_S_MAX_PRIORITIES = 4, + SYMBOL_ID_S_CURRENT_TASK_COUNT = 5, }; static const char * const embKernel_symbol_list[] = { @@ -111,7 +111,7 @@ static const struct embKernel_params embKernel_params_list[] = { static bool embKernel_detect_rtos(struct target *target) { if (target->rtos->symbols != NULL) { - if (target->rtos->symbols[SYMBOL_ID_sCurrentTask].address != 0) + if (target->rtos->symbols[SYMBOL_ID_S_CURRENT_TASK].address != 0) return true; } return false; @@ -198,7 +198,7 @@ static int embKernel_update_threads(struct rtos *rtos) return -4; } - if (rtos->symbols[SYMBOL_ID_sCurrentTask].address == 0) { + if (rtos->symbols[SYMBOL_ID_S_CURRENT_TASK].address == 0) { LOG_ERROR("Don't have the thread list head"); return -2; } @@ -208,7 +208,7 @@ static int embKernel_update_threads(struct rtos *rtos) param = (const struct embKernel_params *) rtos->rtos_specific_params; - retval = target_read_buffer(rtos->target, rtos->symbols[SYMBOL_ID_sCurrentTask].address, param->pointer_width, + retval = target_read_buffer(rtos->target, rtos->symbols[SYMBOL_ID_S_CURRENT_TASK].address, param->pointer_width, (uint8_t *) &rtos->current_thread); if (retval != ERROR_OK) { LOG_ERROR("Error reading current thread in embKernel thread list"); @@ -216,13 +216,13 @@ static int embKernel_update_threads(struct rtos *rtos) } int64_t max_used_priority = 0; - retval = target_read_buffer(rtos->target, rtos->symbols[SYMBOL_ID_sMaxPriorities].address, param->pointer_width, + retval = target_read_buffer(rtos->target, rtos->symbols[SYMBOL_ID_S_MAX_PRIORITIES].address, param->pointer_width, (uint8_t *) &max_used_priority); if (retval != ERROR_OK) return retval; int thread_list_size = 0; - retval = target_read_buffer(rtos->target, rtos->symbols[SYMBOL_ID_sCurrentTaskCount].address, + retval = target_read_buffer(rtos->target, rtos->symbols[SYMBOL_ID_S_CURRENT_TASK_COUNT].address, param->thread_count_width, (uint8_t *) &thread_list_size); if (retval != ERROR_OK) { @@ -243,7 +243,7 @@ static int embKernel_update_threads(struct rtos *rtos) /* Get first item in queue */ int64_t iterable = 0; retval = target_read_buffer(rtos->target, - rtos->symbols[SYMBOL_ID_sListReady].address + (pri * param->rtos_list_size), param->pointer_width, + rtos->symbols[SYMBOL_ID_S_LIST_READY].address + (pri * param->rtos_list_size), param->pointer_width, (uint8_t *) &iterable); if (retval != ERROR_OK) return retval; @@ -261,7 +261,7 @@ static int embKernel_update_threads(struct rtos *rtos) } /* Look for sleeping tasks */ int64_t iterable = 0; - retval = target_read_buffer(rtos->target, rtos->symbols[SYMBOL_ID_sListSleep].address, param->pointer_width, + retval = target_read_buffer(rtos->target, rtos->symbols[SYMBOL_ID_S_LIST_SLEEP].address, param->pointer_width, (uint8_t *) &iterable); if (retval != ERROR_OK) return retval; @@ -279,7 +279,7 @@ static int embKernel_update_threads(struct rtos *rtos) /* Look for suspended tasks */ iterable = 0; - retval = target_read_buffer(rtos->target, rtos->symbols[SYMBOL_ID_sListSuspended].address, param->pointer_width, + retval = target_read_buffer(rtos->target, rtos->symbols[SYMBOL_ID_S_LIST_SUSPENDED].address, param->pointer_width, (uint8_t *) &iterable); if (retval != ERROR_OK) return retval; diff --git a/src/rtos/mqx.c b/src/rtos/mqx.c index 9f895deed..377bca96c 100644 --- a/src/rtos/mqx.c +++ b/src/rtos/mqx.c @@ -49,8 +49,8 @@ /* types */ enum mqx_symbols { - mqx_VAL_mqx_kernel_data, - mqx_VAL_MQX_init_struct, + MQX_VAL_MQX_KERNEL_DATA, + MQX_VAL_MQX_INIT_STRUCT, }; enum mqx_arch { @@ -200,7 +200,7 @@ static int mqx_is_scheduler_running( /* get '_mqx_kernel_data' symbol */ if (ERROR_OK != mqx_get_symbol( - rtos, mqx_VAL_mqx_kernel_data, &kernel_data_symbol + rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_symbol )) { return ERROR_FAIL; } @@ -252,7 +252,7 @@ static bool mqx_detect_rtos( { if ( (target->rtos->symbols != NULL) && - (target->rtos->symbols[mqx_VAL_mqx_kernel_data].address != 0) + (target->rtos->symbols[MQX_VAL_MQX_KERNEL_DATA].address != 0) ) { return true; } @@ -303,7 +303,7 @@ static int mqx_update_threads( return ERROR_FAIL; /* get kernel_data symbol */ if (ERROR_OK != mqx_get_symbol( - rtos, mqx_VAL_mqx_kernel_data, &kernel_data_addr + rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_addr )) { return ERROR_FAIL; } @@ -472,7 +472,7 @@ static int mqx_get_thread_reg_list( return ERROR_FAIL; /* get kernel_data symbol */ if (ERROR_OK != mqx_get_symbol( - rtos, mqx_VAL_mqx_kernel_data, &kernel_data_addr + rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_addr )) { return ERROR_FAIL; } diff --git a/src/rtos/uCOS-III.c b/src/rtos/uCOS-III.c index d62a2199b..1aed4846f 100644 --- a/src/rtos/uCOS-III.c +++ b/src/rtos/uCOS-III.c @@ -101,18 +101,18 @@ static const char * const uCOS_III_symbol_list[] = { }; enum uCOS_III_symbol_values { - uCOS_III_VAL_OSRunning, - uCOS_III_VAL_OSTCBCurPtr, - uCOS_III_VAL_OSTaskDbgListPtr, - uCOS_III_VAL_OSTaskQty, + UCOS_III_VAL_OS_RUNNING, + UCOS_III_VAL_OS_TCB_CUR_PTR, + UCOS_III_VAL_OS_TASK_DBG_LIST_PTR, + UCOS_III_VAL_OS_TASK_QTY, /* also see: contrib/rtos-helpers/uCOS-III-openocd.c */ - uCOS_III_VAL_OS_TCB_StkPtr_offset, - uCOS_III_VAL_OS_TCB_NamePtr_offset, - uCOS_III_VAL_OS_TCB_TaskState_offset, - uCOS_III_VAL_OS_TCB_Prio_offset, - uCOS_III_VAL_OS_TCB_DbgPrevPtr_offset, - uCOS_III_VAL_OS_TCB_DbgNextPtr_offset, + UCOS_III_VAL_OS_TCB_STK_PTR_OFFSET, + UCOS_III_VAL_OS_TCB_NAME_PTR_OFFSET, + UCOS_III_VAL_OS_TCB_TASK_STATE_OFFSET, + UCOS_III_VAL_OS_TCB_PRIO_OFFSET, + UCOS_III_VAL_OS_TCB_DBG_PREV_PTR_OFFSET, + UCOS_III_VAL_OS_TCB_DBG_NEXT_PTR_OFFSET, }; static const char * const uCOS_III_thread_state_list[] = { @@ -173,7 +173,7 @@ static int uCOS_III_find_last_thread_address(struct rtos *rtos, symbol_address_t symbol_address_t thread_list_address = 0; retval = target_read_memory(rtos->target, - rtos->symbols[uCOS_III_VAL_OSTaskDbgListPtr].address, + rtos->symbols[UCOS_III_VAL_OS_TASK_DBG_LIST_PTR].address, params->pointer_width, 1, (void *)&thread_list_address); @@ -212,27 +212,27 @@ static int uCOS_III_update_thread_offsets(struct rtos *rtos) symbol_address_t *thread_offset; } thread_offset_maps[] = { { - uCOS_III_VAL_OS_TCB_StkPtr_offset, + UCOS_III_VAL_OS_TCB_STK_PTR_OFFSET, ¶ms->thread_stack_offset, }, { - uCOS_III_VAL_OS_TCB_NamePtr_offset, + UCOS_III_VAL_OS_TCB_NAME_PTR_OFFSET, ¶ms->thread_name_offset, }, { - uCOS_III_VAL_OS_TCB_TaskState_offset, + UCOS_III_VAL_OS_TCB_TASK_STATE_OFFSET, ¶ms->thread_state_offset, }, { - uCOS_III_VAL_OS_TCB_Prio_offset, + UCOS_III_VAL_OS_TCB_PRIO_OFFSET, ¶ms->thread_priority_offset, }, { - uCOS_III_VAL_OS_TCB_DbgPrevPtr_offset, + UCOS_III_VAL_OS_TCB_DBG_PREV_PTR_OFFSET, ¶ms->thread_prev_offset, }, { - uCOS_III_VAL_OS_TCB_DbgNextPtr_offset, + UCOS_III_VAL_OS_TCB_DBG_NEXT_PTR_OFFSET, ¶ms->thread_next_offset, }, }; @@ -258,7 +258,7 @@ static int uCOS_III_update_thread_offsets(struct rtos *rtos) static bool uCOS_III_detect_rtos(struct target *target) { return target->rtos->symbols != NULL && - target->rtos->symbols[uCOS_III_VAL_OSRunning].address != 0; + target->rtos->symbols[UCOS_III_VAL_OS_RUNNING].address != 0; } static int uCOS_III_reset_handler(struct target *target, enum target_reset_mode reset_mode, void *priv) @@ -312,7 +312,7 @@ static int uCOS_III_update_threads(struct rtos *rtos) uint8_t rtos_running; retval = target_read_u8(rtos->target, - rtos->symbols[uCOS_III_VAL_OSRunning].address, + rtos->symbols[UCOS_III_VAL_OS_RUNNING].address, &rtos_running); if (retval != ERROR_OK) { LOG_ERROR("uCOS-III: failed to read RTOS running"); @@ -350,7 +350,7 @@ static int uCOS_III_update_threads(struct rtos *rtos) symbol_address_t current_thread_address = 0; retval = target_read_memory(rtos->target, - rtos->symbols[uCOS_III_VAL_OSTCBCurPtr].address, + rtos->symbols[UCOS_III_VAL_OS_TCB_CUR_PTR].address, params->pointer_width, 1, (void *)¤t_thread_address); @@ -361,7 +361,7 @@ static int uCOS_III_update_threads(struct rtos *rtos) /* read number of tasks */ retval = target_read_u16(rtos->target, - rtos->symbols[uCOS_III_VAL_OSTaskQty].address, + rtos->symbols[UCOS_III_VAL_OS_TASK_QTY].address, (void *)&rtos->thread_count); if (retval != ERROR_OK) { LOG_ERROR("uCOS-III: failed to read thread count"); commit 11a621c7525fb295d7aa9a786a761e43377104fa Author: Antonio Borneo <bor...@gm...> Date: Sun Apr 25 23:57:01 2021 +0200 server: rename CamelCase symbols No cross dependency, just changes internal to each file/function. Change-Id: I04153a5720b0540bc1998bafe526d523b2ee5515 Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6303 Tested-by: jenkins diff --git a/src/server/server.c b/src/server/server.c index 307266389..ebf88981b 100644 --- a/src/server/server.c +++ b/src/server/server.c @@ -609,7 +609,7 @@ static void sig_handler(int sig) #ifdef _WIN32 -BOOL WINAPI ControlHandler(DWORD dwCtrlType) +BOOL WINAPI control_handler(DWORD ctrl_type) { shutdown_openocd = SHUTDOWN_WITH_SIGNAL_CODE; return TRUE; @@ -634,12 +634,12 @@ int server_host_os_entry(void) * This is an issue if you call init in your config script */ #ifdef _WIN32 - WORD wVersionRequested; - WSADATA wsaData; + WORD version_requested; + WSADATA wsadata; - wVersionRequested = MAKEWORD(2, 2); + version_requested = MAKEWORD(2, 2); - if (WSAStartup(wVersionRequested, &wsaData) != 0) { + if (WSAStartup(version_requested, &wsadata) != 0) { LOG_ERROR("Failed to Open Winsock"); return ERROR_FAIL; } @@ -659,7 +659,7 @@ int server_preinit(void) { #ifdef _WIN32 /* register ctrl-c handler */ - SetConsoleCtrlHandler(ControlHandler, TRUE); + SetConsoleCtrlHandler(control_handler, TRUE); signal(SIGBREAK, sig_handler); signal(SIGINT, sig_handler); @@ -698,7 +698,7 @@ int server_quit(void) target_quit(); #ifdef _WIN32 - SetConsoleCtrlHandler(ControlHandler, FALSE); + SetConsoleCtrlHandler(control_handler, FALSE); return ERROR_OK; #endif commit 1887e2a273797af3d5625ea3d78df3f9ce27ead3 Author: Antonio Borneo <bor...@gm...> Date: Sun Jun 6 17:20:10 2021 +0200 jtag/swd: rename CamelCase macros Change-Id: I4bce678b67d3d2347e88da9507820837697b5aa7 Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6302 Tested-by: jenkins diff --git a/src/jtag/drivers/bitbang.c b/src/jtag/drivers/bitbang.c index df1d601b8..5c4febb20 100644 --- a/src/jtag/drivers/bitbang.c +++ b/src/jtag/drivers/bitbang.c @@ -455,7 +455,7 @@ static void swd_clear_sticky_errors(void) static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk) { LOG_DEBUG("bitbang_swd_read_reg"); - assert(cmd & SWD_CMD_RnW); + assert(cmd & SWD_CMD_RNW); if (queued_retval != ERROR_OK) { LOG_DEBUG("Skip bitbang_swd_read_reg because queued_retval=%d", queued_retval); @@ -478,8 +478,8 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay LOG_DEBUG("%s %s %s reg %X = %08"PRIx32, ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK", - cmd & SWD_CMD_APnDP ? "AP" : "DP", - cmd & SWD_CMD_RnW ? "read" : "write", + cmd & SWD_CMD_APNDP ? "AP" : "DP", + cmd & SWD_CMD_RNW ? "read" : "write", (cmd & SWD_CMD_A32) >> 1, data); @@ -492,7 +492,7 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay } if (value) *value = data; - if (cmd & SWD_CMD_APnDP) + if (cmd & SWD_CMD_APNDP) bitbang_swd_exchange(true, NULL, 0, ap_delay_clk); return; case SWD_ACK_WAIT: @@ -514,7 +514,7 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk) { LOG_DEBUG("bitbang_swd_write_reg"); - assert(!(cmd & SWD_CMD_RnW)); + assert(!(cmd & SWD_CMD_RNW)); if (queued_retval != ERROR_OK) { LOG_DEBUG("Skip bitbang_swd_write_reg because queued_retval=%d", queued_retval); @@ -537,14 +537,14 @@ static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay int ack = buf_get_u32(trn_ack_data_parity_trn, 1, 3); LOG_DEBUG("%s %s %s reg %X = %08"PRIx32, ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK", - cmd & SWD_CMD_APnDP ? "AP" : "DP", - cmd & SWD_CMD_RnW ? "read" : "write", + cmd & SWD_CMD_APNDP ? "AP" : "DP", + cmd & SWD_CMD_RNW ? "read" : "write", (cmd & SWD_CMD_A32) >> 1, buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32)); switch (ack) { case SWD_ACK_OK: - if (cmd & SWD_CMD_APnDP) + if (cmd & SWD_CMD_APNDP) bitbang_swd_exchange(true, NULL, 0, ap_delay_clk); return; case SWD_ACK_WAIT: diff --git a/src/jtag/drivers/buspirate.c b/src/jtag/drivers/buspirate.c index 12bb81e39..616832ea7 100644 --- a/src/jtag/drivers/buspirate.c +++ b/src/jtag/drivers/buspirate.c @@ -1365,7 +1365,7 @@ static uint8_t buspirate_swd_write_header(uint8_t cmd) tmp[5] = 0x07; /* write mode trn_1 */ tmp[6] = 0x07; /* write mode trn_2 */ - to_send = ((cmd & SWD_CMD_RnW) == 0) ? 7 : 5; + to_send = ((cmd & SWD_CMD_RNW) == 0) ? 7 : 5; buspirate_serial_write(buspirate_fd, tmp, to_send); /* read ack */ @@ -1411,7 +1411,7 @@ static void buspirate_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_del uint8_t tmp[16]; LOG_DEBUG("buspirate_swd_read_reg"); - assert(cmd & SWD_CMD_RnW); + assert(cmd & SWD_CMD_RNW); if (queued_retval != ERROR_OK) { LOG_DEBUG("Skip buspirate_swd_read_reg because queued_retval=%d", queued_retval); @@ -1441,8 +1441,8 @@ static void buspirate_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_del LOG_DEBUG("%s %s %s reg %X = %08"PRIx32, ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK", - cmd & SWD_CMD_APnDP ? "AP" : "DP", - cmd & SWD_CMD_RnW ? "read" : "write", + cmd & SWD_CMD_APNDP ? "AP" : "DP", + cmd & SWD_CMD_RNW ? "read" : "write", (cmd & SWD_CMD_A32) >> 1, data); @@ -1455,7 +1455,7 @@ static void buspirate_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_del } if (value) *value = data; - if (cmd & SWD_CMD_APnDP) + if (cmd & SWD_CMD_APNDP) buspirate_swd_idle_clocks(ap_delay_clk); return; case SWD_ACK_WAIT: @@ -1478,7 +1478,7 @@ static void buspirate_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_del uint8_t tmp[16]; LOG_DEBUG("buspirate_swd_write_reg"); - assert(!(cmd & SWD_CMD_RnW)); + assert(!(cmd & SWD_CMD_RNW)); if (queued_retval != ERROR_OK) { LOG_DEBUG("Skip buspirate_swd_write_reg because queued_retval=%d", queued_retval); @@ -1499,14 +1499,14 @@ static void buspirate_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_del LOG_DEBUG("%s %s %s reg %X = %08"PRIx32, ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK", - cmd & SWD_CMD_APnDP ? "AP" : "DP", - cmd & SWD_CMD_RnW ? "read" : "write", + cmd & SWD_CMD_APNDP ? "AP" : "DP", + cmd & SWD_CMD_RNW ? "read" : "write", (cmd & SWD_CMD_A32) >> 1, value); switch (ack) { case SWD_ACK_OK: - if (cmd & SWD_CMD_APnDP) + if (cmd & SWD_CMD_APNDP) buspirate_swd_idle_clocks(ap_delay_clk); return; case SWD_ACK_WAIT: diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c index 4062ace23..e498ea829 100644 --- a/src/jtag/drivers/cmsis_dap.c +++ b/src/jtag/drivers/cmsis_dap.c @@ -787,8 +787,8 @@ static void cmsis_dap_swd_write_from_queue(struct cmsis_dap *dap) uint32_t data = transfer->data; LOG_DEBUG_IO("%s %s reg %x %"PRIx32, - cmd & SWD_CMD_APnDP ? "AP" : "DP", - cmd & SWD_CMD_RnW ? "read" : "write", + cmd & SWD_CMD_APNDP ? "AP" : "DP", + cmd & SWD_CMD_RNW ? "read" : "write", (cmd & SWD_CMD_A32) >> 1, data); /* When proper WAIT handling is implemented in the @@ -802,8 +802,8 @@ static void cmsis_dap_swd_write_from_queue(struct cmsis_dap *dap) * cmsis_dap_cmd_dap_swd_configure() in * cmsis_dap_init(). */ - if (!(cmd & SWD_CMD_RnW) && - !(cmd & SWD_CMD_APnDP) && + if (!(cmd & SWD_CMD_RNW) && + !(cmd & SWD_CMD_APNDP) && (cmd & SWD_CMD_A32) >> 1 == DP_CTRL_STAT && (data & CORUNDETECT)) { LOG_DEBUG("refusing to enable sticky overrun detection"); @@ -811,7 +811,7 @@ static void cmsis_dap_swd_write_from_queue(struct cmsis_dap *dap) } command[idx++] = (cmd >> 1) & 0x0f; - if (!(cmd & SWD_CMD_RnW)) { + if (!(cmd & SWD_CMD_RNW)) { h_u32_to_le(&command[idx], data); idx += 4; } @@ -886,7 +886,7 @@ static void cmsis_dap_swd_read_process(struct cmsis_dap *dap, int timeout_ms) size_t idx = 3; for (int i = 0; i < transfer_count; i++) { struct pending_transfer_result *transfer = &(block->transfers[i]); - if (transfer->cmd & SWD_CMD_RnW) { + if (transfer->cmd & SWD_CMD_RNW) { static uint32_t last_read; uint32_t data = le_to_h_u32(&resp[idx]); uint32_t tmp = data; @@ -895,7 +895,7 @@ static void cmsis_dap_swd_read_process(struct cmsis_dap *dap, int timeout_ms) LOG_DEBUG_IO("Read result: %"PRIx32, data); /* Imitate posted AP reads */ - if ((transfer->cmd & SWD_CMD_APnDP) || + if ((transfer->cmd & SWD_CMD_APNDP) || ((transfer->cmd & SWD_CMD_A32) >> 1 == DP_RDBUFF)) { tmp = last_read; last_read = data; @@ -959,7 +959,7 @@ static void cmsis_dap_swd_queue_cmd(uint8_t cmd, uint32_t *dst, uint32_t data) struct pending_transfer_result *transfer = &(block->transfers[block->transfer_count]); transfer->data = data; transfer->cmd = cmd; - if (cmd & SWD_CMD_RnW) { + if (cmd & SWD_CMD_RNW) { /* Queue a read transaction */ transfer->buffer = dst; } @@ -968,13 +968,13 @@ static void cmsis_dap_swd_queue_cmd(uint8_t cmd, uint32_t *dst, uint32_t data) static void cmsis_dap_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk) { - assert(!(cmd & SWD_CMD_RnW)); + assert(!(cmd & SWD_CMD_RNW)); cmsis_dap_swd_queue_cmd(cmd, NULL, value); } static void cmsis_dap_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk) { - assert(cmd & SWD_CMD_RnW); + assert(cmd & SWD_CMD_RNW); cmsis_dap_swd_queue_cmd(cmd, value, 0); } diff --git a/src/jtag/drivers/ftdi.c b/src/jtag/drivers/ftdi.c index 25406a4c2..1a6ba590b 100644 --- a/src/jtag/drivers/ftdi.c +++ b/src/jtag/drivers/ftdi.c @@ -1112,17 +1112,17 @@ static int ftdi_swd_run_queue(void) LOG_DEBUG_IO("%s %s %s reg %X = %08"PRIx32, ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK", - swd_cmd_queue[i].cmd & SWD_CMD_APnDP ? "AP" : "DP", - swd_cmd_queue[i].cmd & SWD_CMD_RnW ? "read" : "write", + swd_cmd_queue[i].cmd & SWD_CMD_APNDP ? "AP" : "DP", + swd_cmd_queue[i].cmd & SWD_CMD_RNW ? "read" : "write", (swd_cmd_queue[i].cmd & SWD_CMD_A32) >> 1, buf_get_u32(swd_cmd_queue[i].trn_ack_data_parity_trn, - 1 + 3 + (swd_cmd_queue[i].cmd & SWD_CMD_RnW ? 0 : 1), 32)); + 1 + 3 + (swd_cmd_queue[i].cmd & SWD_CMD_RNW ? 0 : 1), 32)); if (ack != SWD_ACK_OK) { queued_retval = ack == SWD_ACK_WAIT ? ERROR_WAIT : ERROR_FAIL; goto skip; - } else if (swd_cmd_queue[i].cmd & SWD_CMD_RnW) { + } else if (swd_cmd_queue[i].cmd & SWD_CMD_RNW) { uint32_t data = buf_get_u32(swd_cmd_queue[i].trn_ack_data_parity_trn, 1 + 3, 32); int parity = buf_get_u32(swd_cmd_queue[i].trn_ack_data_parity_trn, 1 + 3 + 32, 1); @@ -1172,7 +1172,7 @@ static void ftdi_swd_queue_cmd(uint8_t cmd, uint32_t *dst, uint32_t data, uint32 mpsse_clock_data_out(mpsse_ctx, &swd_cmd_queue[i].cmd, 0, 8, SWD_MODE); - if (swd_cmd_queue[i].cmd & SWD_CMD_RnW) { + if (swd_cmd_queue[i].cmd & SWD_CMD_RNW) { /* Queue a read transaction */ swd_cmd_queue[i].dst = dst; @@ -1197,20 +1197,20 @@ static void ftdi_swd_queue_cmd(uint8_t cmd, uint32_t *dst, uint32_t data, uint32 } /* Insert idle cycles after AP accesses to avoid WAIT */ - if (cmd & SWD_CMD_APnDP) + if (cmd & SWD_CMD_APNDP) mpsse_clock_data_out(mpsse_ctx, NULL, 0, ap_delay_clk, SWD_MODE); } static void ftdi_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk) { - assert(cmd & SWD_CMD_RnW); + assert(cmd & SWD_CMD_RNW); ftdi_swd_queue_cmd(cmd, value, 0, ap_delay_clk); } static void ftdi_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk) { - assert(!(cmd & SWD_CMD_RnW)); + assert(!(cmd & SWD_CMD_RNW)); ftdi_swd_queue_cmd(cmd, NULL, value, ap_delay_clk); } diff --git a/src/jtag/drivers/jlink.c b/src/jtag/drivers/jlink.c index 6781e14ff..7a2be61fe 100644 --- a/src/jtag/drivers/jlink.c +++ b/src/jtag/drivers/jlink.c @@ -1978,13 +1978,13 @@ static int jlink_swd_init(void) static void jlink_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk) { - assert(!(cmd & SWD_CMD_RnW)); + assert(!(cmd & SWD_CMD_RNW)); jlink_swd_queue_cmd(cmd, NULL, value, ap_delay_clk); } static void jlink_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk) { - assert(cmd & SWD_CMD_RnW); + assert(cmd & SWD_CMD_RNW); jlink_swd_queue_cmd(cmd, value, 0, ap_delay_clk); } @@ -2237,7 +2237,7 @@ static void jlink_swd_queue_cmd(uint8_t cmd, uint32_t *dst, uint32_t data, uint3 pending_scan_results_buffer[pending_scan_results_length].first = tap_length; - if (cmd & SWD_CMD_RnW) { + if (cmd & SWD_CMD_RNW) { /* Queue a read transaction. */ pending_scan_results_buffer[pending_scan_results_length].length = 32; pending_scan_results_buffer[pending_scan_results_length].buffer = dst; @@ -2257,7 +2257,7 @@ static void jlink_swd_queue_cmd(uint8_t cmd, uint32_t *dst, uint32_t data, uint3 pending_scan_results_length++; /* Insert idle cycles after AP accesses to avoid WAIT. */ - if (cmd & SWD_CMD_APnDP) + if (cmd & SWD_CMD_APNDP) jlink_queue_data_out(NULL, ap_delay_clk); } diff --git a/src/jtag/drivers/kitprog.c b/src/jtag/drivers/kitprog.c index 5538bcd73..00d3f5881 100644 --- a/src/jtag/drivers/kitprog.c +++ b/src/jtag/drivers/kitprog.c @@ -625,13 +625,13 @@ static int kitprog_swd_init(void) static void kitprog_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk) { - assert(!(cmd & SWD_CMD_RnW)); + assert(!(cmd & SWD_CMD_RNW)); kitprog_swd_queue_cmd(cmd, NULL, value); } static void kitprog_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk) { - assert(cmd & SWD_CMD_RnW); + assert(cmd & SWD_CMD_RNW); kitprog_swd_queue_cmd(cmd, value, 0); } @@ -699,8 +699,8 @@ static int kitprog_swd_run_queue(void) * cmsis_dap_cmd_DAP_SWD_Configure() in * cmsis_dap_init(). */ - if (!(cmd & SWD_CMD_RnW) && - !(cmd & SWD_CMD_APnDP) && + if (!(cmd & SWD_CMD_RNW) && + !(cmd & SWD_CMD_APNDP) && (cmd & SWD_CMD_A32) >> 1 == DP_CTRL_STAT && (data & CORUNDETECT)) { LOG_DEBUG("refusing to enable sticky overrun detection"); @@ -708,13 +708,13 @@ static int kitprog_swd_run_queue(void) } LOG_DEBUG_IO("%s %s reg %x %"PRIx32, - cmd & SWD_CMD_APnDP ? "AP" : "DP", - cmd & SWD_CMD_RnW ? "read" : "write", + cmd & SWD_CMD_APNDP ? "AP" : "DP", + cmd & SWD_CMD_RNW ? "read" : "write", (cmd & SWD_CMD_A32) >> 1, data); buffer[write_count++] = (cmd | SWD_CMD_START | SWD_CMD_PARK) & ~SWD_CMD_STOP; read_count++; - if (!(cmd & SWD_CMD_RnW)) { + if (!(cmd & SWD_CMD_RNW)) { buffer[write_count++] = (data) & 0xff; buffer[write_count++] = (data >> 8) & 0xff; buffer[write_count++] = (data >> 16) & 0xff; @@ -761,7 +761,7 @@ static int kitprog_swd_run_queue(void) } for (int i = 0; i < pending_transfer_count; i++) { - if (pending_transfers[i].cmd & SWD_CMD_RnW) { + if (pending_transfers[i].cmd & SWD_CMD_RNW) { uint32_t data = le_to_h_u32(&buffer[read_index]); LOG_DEBUG_IO("Read result: %"PRIx32, data); @@ -802,7 +802,7 @@ static void kitprog_swd_queue_cmd(uint8_t cmd, uint32_t *dst, uint32_t data) pending_transfers[pending_transfer_count].data = data; pending_transfers[pending_transfer_count].cmd = cmd; - if (cmd & SWD_CMD_RnW) { + if (cmd & SWD_CMD_RNW) { /* Queue a read transaction */ pending_transfers[pending_transfer_count].buffer = dst; } diff --git a/src/jtag/drivers/xds110.c b/src/jtag/drivers/xds110.c index 85a1b81db..23a431cf7 100644 --- a/src/jtag/drivers/xds110.c +++ b/src/jtag/drivers/xds110.c @@ -1165,9 +1165,9 @@ static int xds110_swd_switch_seq(enum swd_special_seq seq) static bool xds110_legacy_read_reg(uint8_t cmd, uint32_t *value) { /* Make sure this is a read request */ - bool is_read_request = (0 != (SWD_CMD_RnW & cmd)); + bool is_read_request = (0 != (SWD_CMD_RNW & cmd)); /* Determine whether this is a DP or AP register access */ - uint32_t type = (0 != (SWD_CMD_APnDP & cmd)) ? DAP_AP : DAP_DP; + uint32_t type = (0 != (SWD_CMD_APNDP & cmd)) ? DAP_AP : DAP_DP; /* Determine the AP number from cached SELECT value */ uint32_t ap_num = (xds110.select & 0xff000000) >> 24; /* Extract register address from command */ @@ -1227,9 +1227,9 @@ static bool xds110_legacy_read_reg(uint8_t cmd, uint32_t *value) static bool xds110_legacy_write_reg(uint8_t cmd, uint32_t value) { /* Make sure this isn't a read request */ - bool is_read_request = (0 != (SWD_CMD_RnW & cmd)); + bool is_read_request = (0 != (SWD_CMD_RNW & cmd)); /* Determine whether this is a DP or AP register access */ - uint32_t type = (0 != (SWD_CMD_APnDP & cmd)) ? DAP_AP : DAP_DP; + uint32_t type = (0 != (SWD_CMD_APNDP & cmd)) ? DAP_AP : DAP_DP; /* Determine the AP number from cached SELECT value */ uint32_t ap_num = (xds110.select & 0xff000000) >> 24; /* Extract register address from command */ @@ -1296,7 +1296,7 @@ static int xds110_swd_run_queue(void) result = 0; while (xds110.txn_requests[request] != 0) { cmd = xds110.txn_requests[request++]; - if (0 == (SWD_CMD_RnW & cmd)) { + if (0 == (SWD_CMD_RNW & cmd)) { /* DAP register write command */ value = (uint32_t)(xds110.txn_requests[request++]) << 0; value |= (uint32_t)(xds110.txn_requests[request++]) << 8; @@ -1329,9 +1329,9 @@ static int xds110_swd_run_queue(void) static void xds110_swd_queue_cmd(uint8_t cmd, uint32_t *value) { /* Check if this is a read or write request */ - bool is_read_request = (0 != (SWD_CMD_RnW & cmd)); + bool is_read_request = (0 != (SWD_CMD_RNW & cmd)); /* Determine whether this is a DP or AP register access */ - uint32_t type = (0 != (SWD_CMD_APnDP & cmd)) ? DAP_AP : DAP_DP; + uint32_t type = (0 != (SWD_CMD_APNDP & cmd)) ? DAP_AP : DAP_DP; /* Extract register address from command */ uint32_t address = ((cmd & SWD_CMD_A32) >> 1); uint32_t request_size = (is_read_request) ? 1 : 5; diff --git a/src/jtag/drivers/xlnx-pcie-xvc.c b/src/jtag/drivers/xlnx-pcie-xvc.c index 7b82218d5..27295f596 100644 --- a/src/jtag/drivers/xlnx-pcie-xvc.c +++ b/src/jtag/drivers/xlnx-pcie-xvc.c @@ -535,7 +535,7 @@ static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t res, ack, rpar; int err; - assert(cmd & SWD_CMD_RnW); + assert(cmd & SWD_CMD_RNW); cmd |= SWD_CMD_START | SWD_CMD_PARK; /* cmd + ack */ @@ -558,8 +558,8 @@ static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value, LOG_DEBUG("%s %s %s reg %X = %08"PRIx32, ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK", - cmd & SWD_CMD_APnDP ? "AP" : "DP", - cmd & SWD_CMD_RnW ? "read" : "write", + cmd & SWD_CMD_APNDP ? "AP" : "DP", + cmd & SWD_CMD_RNW ? "read" : "write", (cmd & SWD_CMD_A32) >> 1, res); switch (ack) { @@ -571,7 +571,7 @@ static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value, } if (value) *value = res; - if (cmd & SWD_CMD_APnDP) + if (cmd & SWD_CMD_APNDP) err = xlnx_pcie_xvc_transact(ap_delay_clk, 0, 0, NULL); queued_retval = err; return; @@ -598,7 +598,7 @@ static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t res, ack; int err; - assert(!(cmd & SWD_CMD_RnW)); + assert(!(cmd & SWD_CMD_RNW)); cmd |= SWD_CMD_START | SWD_CMD_PARK; /* cmd + trn + ack */ @@ -621,14 +621,14 @@ static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value, LOG_DEBUG("%s %s %s reg %X = %08"PRIx32, ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK", - cmd & SWD_CMD_APnDP ? "AP" : "DP", - cmd & SWD_CMD_RnW ? "read" : "write", + cmd & SWD_CMD_APNDP ? "AP" : "DP", + cmd & SWD_CMD_RNW ? "read" : "write", (cmd & SWD_CMD_A32) >> 1, value); switch (ack) { case SWD_ACK_OK: - if (cmd & SWD_CMD_APnDP) + if (cmd & SWD_CMD_APNDP) err = xlnx_pcie_xvc_transact(ap_delay_clk, 0, 0, NULL); queued_retval = err; return; diff --git a/src/jtag/swd.h b/src/jtag/swd.h index 487cb85bf..fe28667c6 100644 --- a/src/jtag/swd.h +++ b/src/jtag/swd.h @@ -24,8 +24,8 @@ * first bit on the wire is START */ #define SWD_CMD_START (1 << 0) /* always set */ -#define SWD_CMD_APnDP (1 << 1) /* set only for AP access */ -#define SWD_CMD_RnW (1 << 2) /* set only for read access */ +#define SWD_CMD_APNDP (1 << 1) /* set only for AP access */ +#define SWD_CMD_RNW (1 << 2) /* set only for read access */ #define SWD_CMD_A32 (3 << 3) /* bits A[3:2] of register addr */ #define SWD_CMD_PARITY (1 << 5) /* parity of APnDP|RnW|A32 */ #define SWD_CMD_STOP (0 << 6) /* always clear for synch SWD */ @@ -38,8 +38,8 @@ */ static inline uint8_t swd_cmd(bool is_read, bool is_ap, uint8_t regnum) { - uint8_t cmd = (is_ap ? SWD_CMD_APnDP : 0) - | (is_read ? SWD_CMD_RnW : 0) + uint8_t cmd = (is_ap ? SWD_CMD_APNDP : 0) + | (is_read ? SWD_CMD_RNW : 0) | ((regnum & 0xc) << 1); /* 8 cmd bits 4:1 may be set */ commit 20ee64ae4bc70b836664465daebe828caca7ccbc Author: Antonio Borneo <bor...@gm...> Date: Sun Apr 25 23:41:15 2021 +0200 jtag: rename CamelCase symbols No major cross dependency, just changes internal to each file or function. Change-Id: Ie6258a090ce53de5db65df6a77d57ac6bb899488 Signed-off-by: Antonio Borneo <bor...@gm...> Reviewed-on: http://openocd.zylin.com/6301 Tested-by: jenkins diff --git a/src/jtag/aice/aice_transport.c b/src/jtag/aice/aice_transport.c index 322d8ae5c..7e06760fb 100644 --- a/src/jtag/aice/aice_transport.c +++ b/src/jtag/aice/aice_transport.c @@ -31,7 +31,7 @@ /* */ static int jim_newtap_expected_id(struct jim_nvp *n, struct jim_getopt_info *goi, - struct jtag_tap *pTap) + struct jtag_tap *tap) { jim_wide w; int e = jim_getopt_wide(goi, &w); @@ -41,21 +41,21 @@ static int jim_newtap_expected_id(struct jim_nvp *n, struct jim_getopt_info *goi return e; } - unsigned expected_len = sizeof(uint32_t) * pTap->expected_ids_cnt; + unsigned expected_len = sizeof(uint32_t) * tap->expected_ids_cnt; uint32_t *new_expected_ids = malloc(expected_len + sizeof(uint32_t)); if (new_expected_ids == NULL) { Jim_SetResultFormatted(goi->interp, "no memory"); return JIM_ERR; } - assert(pTap->expected_ids); - memcpy(new_expected_ids, pTap->expected_ids, expected_len); + assert(tap->expected_ids); + memcpy(new_expected_ids, tap->expected_ids, expected_len); - new_expected_ids[pTap->expected_ids_cnt] = w; + new_expected_ids[tap->expected_ids_cnt] = w; - free(pTap->expected_ids); - pTap->expected_ids = new_expected_ids; - pTap->expected_ids_cnt++; + free(tap->expected_ids); + tap->expected_ids = new_expected_ids; + tap->expected_ids_cnt++; return JIM_OK; } @@ -65,7 +65,7 @@ static int jim_newtap_expected_id(struct jim_nvp *n, struct jim_getopt_info *goi /* */ static int jim_aice_newtap_cmd(struct jim_getopt_info *goi) { - struct jtag_tap *pTap; + struct jtag_tap *tap; int x; int e; struct jim_nvp *n; @@ -75,8 +75,8 @@ static int jim_aice_newtap_cmd(struct jim_getopt_info *goi) {.name = NULL, .value = -1}, }; - pTap = calloc(1, sizeof(struct jtag_tap)); - if (!pTap) { + tap = calloc(1, sizeof(struct jtag_tap)); + if (!tap) { Jim_SetResultFormatted(goi->interp, "no memory"); return JIM_ERR; } @@ -87,41 +87,41 @@ static int jim_aice_newtap_cmd(struct jim_getopt_info *goi) if (goi->argc < 3) { Jim_SetResultFormatted(goi->interp, "Missing CHIP TAP OPTIONS ...."); - free(pTap); + free(tap); return JIM_ERR; } const char *tmp; jim_getopt_string(goi, &tmp, NULL); - pTap->chip = strdup(tmp); + tap->chip = strdup(tmp); jim_getopt_string(goi, &tmp, NULL); - pTap->tapname = strdup(tmp); + tap->tapname = strdup(tmp); /* name + dot + name + null */ - x = strlen(pTap->chip) + 1 + strlen(pTap->tapname) + 1; + x = strlen(tap->chip) + 1 + strlen(tap->tapname) + 1; cp = malloc(x); - sprintf(cp, "%s.%s", pTap->chip, pTap->tapname); - pTap->dotted_name = cp; + sprintf(cp, "%s.%s", tap->chip, tap->tapname); + tap->dotted_name = cp; LOG_DEBUG("Creating New Tap, Chip: %s, Tap: %s, Dotted: %s, %d params", - pTap->chip, pTap->tapname, pTap->dotted_name, goi->argc); + tap->chip, tap->tapname, tap->dotted_name, goi->argc); while (goi->argc) { e = jim_getopt_nvp(goi, opts, &n); if (e != JIM_OK) { jim_getopt_nvp_unknown(goi, opts, 0); free(cp); - free(pTap); + free(tap); return e; } LOG_DEBUG("Processing option: %s", n->name); switch (n->value) { case NTAP_OPT_EXPECTED_ID: - e = jim_newtap_expected_id(n, goi, pTap); + e = jim_newtap_expected_id(n, goi, tap); if (JIM_OK != e) { free(cp); - free(pTap); + free(tap); return e; } break; @@ -129,9 +129,9 @@ static int jim_aice_newtap_cmd(struct jim_getopt_info *goi) } /* while (goi->argc) */ /* default is enabled-after-reset */ - pTap->enabled = !pTap->disabled_after_reset; + tap->enabled = !tap->disabled_after_reset; - jtag_tap_init(pTap); + jtag_tap_init(tap); return JIM_OK; } diff --git a/src/jtag/drivers/libusb_helper.c b/src/jtag/drivers/libusb_helper.c index 18fe4bad4..e214eb701 100644 --- a/src/jtag/drivers/libusb_helper.c +++ b/src/jtag/drivers/libusb_helper.c @@ -158,7 +158,7 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[], struct libusb_device_handle **out, adapter_get_alternate_serial_fn adapter_get_alternate_serial) { - int cnt, idx, errCode; + int cnt, idx, err_code; int retval = ERROR_FAIL; bool serial_mismatch = false; struct libusb_device_handle *libusb_handle = NULL; @@ -180,11 +180,11 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[], if (jtag_usb_get_location() && !jtag_libusb_location_equal(devs[idx])) continue; - errCode = libusb_open(devs[idx], &libusb_handle); + err_code = libusb_open(devs[idx], &libusb_handle); - if (errCode) { + if (err_code) { LOG_ERROR("libusb_open() failed with %s", - libusb_error_name(errCode)); + libusb_error_name(err_code)); continue; } @@ -222,13 +222,13 @@ void jtag_libusb_close(struct libusb_device_handle *dev) libusb_exit(jtag_libusb_context); } -int jtag_libusb_control_transfer(struct libusb_device_handle *dev, uint8_t requestType, - uint8_t request, uint16_t wValue, uint16_t wIndex, char *bytes, +int jtag_libusb_control_transfer(struct libusb_device_handle *dev, uint8_t request_type, + uint8_t request, uint16_t value, uint16_t index, char *bytes, uint16_t size, unsigned int timeout) { int transferred = 0; - transferred = libusb_control_transfer(dev, requestType, request, wValue, wIndex, + transferred = libusb_control_transfer(dev, request_type, request, value, index, (unsigned char *)bytes, size, timeout); if (transferred < 0) @@ -275,28 +275,28 @@ int jtag_libusb_set_configuration(struct libusb_device_handle *devh, int configuration) { struct libusb_device *udev = libusb_get_device(devh); - int retCode = -99; + int retval = -99; struct libusb_config_descriptor *config = NULL; int current_config = -1; - retCode = libusb_get_configuration(devh, ¤t_config); - if (retCode != 0) - return retCode; + retval = libusb_get_configuration(devh, ¤t_config); + if (retval != 0) + return retval; - retCode = libusb_get_config_descriptor(udev, configuration, &config); - if (retCode != 0 || config == NULL) - return retCode; + retval = libusb_get_config_descriptor(udev, configuration, &config); + if (retval != 0 || config == NULL) + return retval; /* Only change the configuration if it is not already set to the same one. Otherwise this issues a lightweight reset and hangs LPC-Link2 with JLink firmware. */ if (current_config != config->bConfigurationValue) - retCode = libusb_set_configuration(devh, config->bConfigurationValue); + retval = libusb_set_configuration(devh, config->bConfigurationValue); libusb_free_config_descriptor(config); - return retCode; + return retval; } int jtag_libusb_choose_interface(struct libusb_device_handle *devh, diff --git a/src/jtag/drivers/libusb_helper.h b/src/jtag/drivers/libusb_helper.h index 3e77865d6..6087128d2 100644 --- a/src/jtag/drivers/libusb_helper.h +++ b/src/jtag/drivers/libusb_helper.h @@ -33,8 +33,8 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[], adapter_get_alternate_serial_fn adapter_get_alternate_serial); void jtag_libusb_close(struct libusb_device_handle *dev); int jtag_libusb_control_transfer(struct libusb_device_handle *dev, - uint8_t requestType, uint8_t request, uint16_t wValue, - uint16_t wIndex, char *bytes, uint16_t size, unsigned int timeout); + uint8_t request_type, uint8_t request, uint16_t value, + uint16_t index, char *bytes, uint16_t size, unsigned int timeout); int jtag_libusb_bulk_write(struct libusb_device_handle *dev, int ep, char *bytes, int size, int timeout, int *transferred); int jtag_libusb_bulk_read(struct libusb_device_handle *dev, int ep, diff --git a/src/jtag/drivers/rlink.c b/src/jtag/drivers/rlink.c index a88731f4a..07e22ffb7 100644 --- a/src/jtag/drivers/rlink.c +++ b/src/jtag/drivers/rlink.c @@ -97,14 +97,14 @@ #define ST7_PC_TDO ST7_PC_IO9 #define ST7_PA_DBGACK ST7_PA_IO10 -static struct libusb_device_handle *pHDev; +static struct libusb_device_handle *hdev; /* * ep1 commands are up to USB_EP1OUT_SIZE bytes in length. * This function takes care of zeroing the unused bytes before sending the packet. * Any reply packet is not handled by this function. */ -static int ep1_generic_commandl(struct libusb_device_handle *pHDev_param, size_t length, ...) +static int ep1_generic_commandl(struct libusb_device_handle *hdev_param, size_t length, ...) { uint8_t usb_buffer[USB_EP1OUT_SIZE]; uint8_t *usb_buffer_p; @@ -130,7 +130,7 @@ static int ep1_generic_commandl(struct libusb_device_handle *pHDev_param, size_t ); usb_ret = jtag_libusb_bulk_write( - pHDev_param, + hdev_param, USB_EP1OUT_ADDR, (char *)usb_buffer, sizeof(usb_buffer), USB_TIMEOUT_MS, @@ -144,7 +144,7 @@ static int ep1_generic_commandl(struct libusb_device_handle *pHDev_param, size_t #if 0 static ssize_t ep1_memory_read( - struct libusb_device_handle *pHDev_param, uint16_t addr, + struct libusb_device_handle *hdev_param, uint16_t addr, size_t length, uint8_t *buffer) { uint8_t usb_buffer[USB_EP1OUT_SIZE]; @@ -174,7 +174,7 @@ static ssize_t ep1_memory_read( usb_buffer[3] = length; usb_ret = jtag_libusb_bulk_write( - pHDev_param, USB_EP1OUT_ADDR, + hdev_param, USB_EP1OUT_ADDR, (char *)usb_buffer, sizeof(usb_buffer), USB_TIMEOUT_MS, &transferred @@ -184,7 +184,7 @@ static ssize_t ep1_memory_read( break; usb_ret = jtag_libusb_bulk_read( - pHDev_param, USB_EP1IN_ADDR, + hdev_param, USB_EP1IN_ADDR, (char *)buffer, length, USB_TIMEOUT_MS, &transferred @@ -203,7 +203,7 @@ static ssize_t ep1_memory_read( } #endif -static ssize_t ep1_memory_write(struct libusb_device_handle *pHDev_param, uint16_t addr, +static ssize_t ep1_memory_write(struct libusb_device_handle *hdev_param, uint16_t addr, size_t length, uint8_t const *buffer) { uint8_t usb_buffer[USB_EP1OUT_SIZE]; @@ -239,7 +239,7 @@ static ssize_t ep1_memory_write(struct libusb_device_handle *pHDev_param, uint16 int transferred; usb_ret = jtag_libusb_bulk_write( - pHDev_param, USB_EP1OUT_ADDR, + hdev_param, USB_EP1OUT_ADDR, (char *)usb_buffer, sizeof(usb_buffer), USB_TIMEOUT_MS, &transferred @@ -259,7 +259,7 @@ static ssize_t ep1_memory_write(struct libusb_device_handle *pHDev_param, uint16 #if 0 -static ssize_t ep1_memory_writel(struct libusb_device_handle *pHDev_param, uint16_t addr, +static ssize_t ep1_memory_writel(struct libusb_device_handle *hdev_param, uint16_t addr, size_t length, ...) { uint8_t buffer[USB_EP1OUT_SIZE - 4]; @@ -279,7 +279,7 @@ static ssize_t ep1_memory_writel(struct libusb_device_handle *pHDev_param, uint1 remain--; } - return ep1_memory_write(pHDev_param, addr, length, buffer); + return ep1_memory_write(hdev_param, addr, length, buffer); } #endif @@ -296,7 +296,7 @@ static ssize_t ep1_memory_writel(struct libusb_device_handle *pHDev_param, uint1 static uint8_t dtc_entry_download; /* The buffer is specially formatted to represent a valid image to load into the DTC. */ -static int dtc_load_from_buffer(struct libusb_device_handle *pHDev_param, const uint8_t *buffer, +static int dtc_load_from_buffer(struct libusb_device_handle *hdev_param, const uint8_t *buffer, size_t length) { struct header_s { @@ -312,7 +312,7 @@ static int dtc_load_from_buffer(struct libusb_device_handle *pHDev_param, const /* Stop the DTC before loading anything. */ usb_err = ep1_generic_commandl( - pHDev_param, 1, + hdev_param, 1, EP1_CMD_DTC_STOP ); if (usb_err < 0) @@ -346,7 +346,7 @@ static int dtc_load_from_buffer(struct libusb_device_handle *pHDev_param, const case DTCLOAD_LOAD: /* Send the DTC program to ST7 RAM. */ usb_err = ep1_memory_write( - pHDev_param, + hdev_param, DTC_LOAD_BUFFER, header->length + 1, buffer ); @@ -355,7 +355,7 @@ static int dtc_load_from_buffer(struct libusb_device_handle *pHDev_param, const /* Load it into the DTC. */ usb_err = ep1_generic_commandl( - pHDev_param, 3, + hdev_param, 3, EP1_CMD_DTC_LOAD, (DTC_LOAD_BUFFER >> 8), DTC_LOAD_BUFFER @@ -367,7 +367,7 @@ static int dtc_load_from_buffer(struct libusb_device_handle *pHDev_param, const case DTCLOAD_RUN: usb_err = ep1_generic_commandl( - pHDev_param, 3, + hdev_param, 3, EP1_CMD_DTC_CALL, buffer[0], EP1_CMD_DTC_WAIT @@ -383,7 +383,7 @@ static int dtc_load_from_buffer(struct libusb_device_handle *pHDev_param, const case DTCLOAD_LUT: usb_err = ep1_memory_write( - pHDev_param, + hdev_param, ST7_USB_BUF_EP0OUT + lut_start, header->length + 1, buffer ); @@ -415,7 +415,7 @@ static int dtc_start_download(void) /* set up for download mode and make sure EP2 is set up to transmit */ usb_err = ep1_generic_commandl( - pHDev, 7, + hdev, 7, EP1_CMD_DTC_STOP, EP1_CMD_SET_UPLOAD, @@ -430,7 +430,7 @@ static int dtc_start_download(void) /* read back ep2txr */ usb_err = jtag_libusb_bulk_read( - pHDev, USB_EP1IN_ADDR, + hdev, USB_EP1IN_ADDR, (char *)&ep2txr, 1, USB_TIMEOUT_MS, &transferred @@ -439,7 +439,7 @@ static int dtc_start_download(void) return usb_err; usb_err = ep1_generic_commandl( - pHDev, 13, + hdev, 13, EP1_CMD_MEMORY_WRITE, /* preinitialize poll byte */ DTC_STATUS_POLL_BYTE >> 8, @@ -460,7 +460,7 @@ static int dtc_start_download(void) /* wait for completion */ usb_err = jtag_libusb_bulk_read( - pHDev, USB_EP1IN_ADDR, + hdev, USB_EP1IN_ADDR, (char *)&ep2txr, 1, USB_TIMEOUT_MS, &transferred @@ -470,7 +470,7 @@ static int dtc_start_download(void) } static int dtc_run_download( - struct libusb_device_handle *pHDev_param, + struct libusb_device_handle *hdev_param, uint8_t *command_buffer, int command_buffer_size, uint8_t *reply_buffer, @@ -485,7 +485,7 @@ static int dtc_run_download( LOG_DEBUG("%d/%d", command_buffer_size, reply_buffer_size); usb_err = jtag_libusb_bulk_write( - pHDev_param, + hdev_param, USB_EP2OUT_ADDR, (char *)command_buffer, USB_EP2BANK_SIZE, USB_TIMEOUT_MS, @@ -498,7 +498,7 @@ static int dtc_run_download( /* Wait for DTC to finish running command buffer */ for (i = 50;; ) { usb_err = ep1_generic_commandl( - pHDev_param, 4, + hdev_param, 4, EP1_CMD_MEMORY_READ, DTC_STATUS_POLL_BYTE >> 8, @@ -509,7 +509,7 @@ static int dtc_run_download( return usb_err; usb_err = jtag_libusb_bulk_read( - pHDev_param, + hdev_param, USB_EP1IN_ADDR, &dtc_status, 1, USB_TIMEOUT_MS, @@ -530,7 +530,7 @@ static int dtc_run_download( if (reply_buffer && reply_buffer_size) { usb_err = jtag_libusb_bulk_read( - pHDev_param, + hdev_param, USB_EP2IN_ADDR, (char *)reply_buffer, reply_buffer_size, USB_TIMEOUT_MS, @@ -656,7 +656,7 @@ static int dtc_queue_run(void) dtc_queue.cmd_buffer[dtc_queue.cmd_index++] = DTC_CMD_STOP; - usb_err = dtc_run_download(pHDev, + usb_err = dtc_run_download(hdev, dtc_queue.cmd_buffer, dtc_queue.cmd_index, reply_buffer, sizeof(reply_buffer) ); @@ -940,7 +940,7 @@ static void rlink_reset(int trst, int srst) /* Read port A for bit op */ usb_err = ep1_generic_commandl( - pHDev, 4, + hdev, 4, EP1_CMD_MEMORY_READ, ST7_PADR >> 8, ST7_PADR, @@ -952,7 +952,7 @@ static void rlink_reset(int trst, int srst) } usb_err = jtag_libusb_bulk_read( - pHDev, USB_EP1IN_ADDR, + hdev, USB_EP1IN_ADDR, (char *)&bitmap, 1, USB_TIMEOUT_MS, &transferred @@... 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