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From: OpenOCD-Gerrit <ope...@us...> - 2021-09-02 06:43:20
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 385eedfc6f0b82c5d6715c740ee40bdce983ef04 (commit)
from a098816a6557e5882bf088ab12a06b94934f30ce (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 385eedfc6f0b82c5d6715c740ee40bdce983ef04
Author: Wealian Liao <WH...@nu...>
Date: Thu Nov 26 10:25:09 2020 +0800
flash/nor: add support for Nuvoton NPCX series flash
Added NPCX flash driver to support the Nuvoton NPCX series
microcontrollers. Add config file for NPCX series.
Change-Id: Ia10b019a3521f59ad1e10ccdc56827ba30c3eac8
Signed-off-by: Wealian Liao <WH...@nu...>
Signed-off-by: Mulin Chao <ml...@nu...>
Reviewed-on: https://review.openocd.org/c/openocd/+/5950
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/contrib/loaders/flash/npcx/Makefile b/contrib/loaders/flash/npcx/Makefile
new file mode 100644
index 000000000..293bd02da
--- /dev/null
+++ b/contrib/loaders/flash/npcx/Makefile
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+BIN2C = ../../../../src/helper/bin2char.sh
+
+# Toolchain used in makefile
+CROSS_COMPILE ?= arm-none-eabi-
+CC = $(CROSS_COMPILE)gcc
+CPLUS = $(CROSS_COMPILE)g++
+CPP = $(CROSS_COMPILE)cpp
+LD = $(CROSS_COMPILE)gcc
+AS = $(CROSS_COMPILE)as
+OBJCOPY = $(CROSS_COMPILE)objcopy
+OBJDUMP = $(CROSS_COMPILE)objdump
+OBJSIZE = $(CROSS_COMPILE)size
+
+TARGET = npcx_algo
+OBJS := npcx_flash.o
+FLAGS = -mthumb -Os -ffunction-sections -fdata-sections -g -gdwarf-3 --specs=nano.specs
+FLAGS += -gstrict-dwarf -Wall -fno-strict-aliasing --asm
+
+CFLAGS = -c -I. -mcpu=cortex-m4 -fpack-struct
+
+PRE_LD_FILE = npcx_flash.lds
+LD_FILE = npcx_flash_generated.lds
+LDFLAGS = -Wl,-Map,lfw.map -Wl,-T$(LD_FILE) -nostartfiles
+
+all: $(TARGET).inc
+
+# Implicit rules
+%.o: %.c
+ -@ echo CC $@ from $<
+ @$(CC) $< $(FLAGS) $(CFLAGS) -o $@
+
+ $(LD_FILE): $(PRE_LD_FILE)
+ -@ echo Generate $@ from $<
+ -@$(CPP) $(PRE_LD_FILE) | grep -v '^#' >>$(LD_FILE)
+
+$(TARGET).elf: $(OBJS) $(LD_FILE)
+ -@ echo LD $@ from $<
+ @$(LD) -o $@ $< $(FLAGS) $(LDFLAGS)
+
+%.bin: %.elf
+ -@ echo OBJCOPY $@ from $<
+ -@ $(OBJCOPY) $< -O binary $@
+ -@ $(OBJSIZE) $< --format=berkeley
+
+%.inc: %.bin
+ @echo 'Building target: $@'
+ @echo 'Invoking Bin2Char Script'
+ $(BIN2C) < $< > $@
+ rm $< $*.elf
+ @echo 'Finished building target: $@'
+ @echo ' '
+
+clean:
+ @echo 'Cleaning Targets and Build Artifacts'
+ rm -rf *.inc *.bin *.elf *.map
+ rm -rf *.o *.d
+ rm -rf $(LD_FILE)
+ @echo 'Finished clean'
+ @echo ' '
+
+.PRECIOUS: %.bin
+
+.PHONY: all clean
diff --git a/contrib/loaders/flash/npcx/npcx_algo.inc b/contrib/loaders/flash/npcx/npcx_algo.inc
new file mode 100644
index 000000000..4312fdb1b
--- /dev/null
+++ b/contrib/loaders/flash/npcx/npcx_algo.inc
@@ -0,0 +1,60 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
+0x08,0xb5,0xdf,0xf8,0x08,0xd0,0x00,0xf0,0x2f,0xf9,0x00,0x00,0x48,0x15,0x0c,0x20,
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diff --git a/contrib/loaders/flash/npcx/npcx_flash.c b/contrib/loaders/flash/npcx/npcx_flash.c
new file mode 100644
index 000000000..d60624ae8
--- /dev/null
+++ b/contrib/loaders/flash/npcx/npcx_flash.c
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * Copyright (C) 2020 by Nuvoton Technology Corporation
+ * Mulin Chao <ml...@nu...>
+ * Wealian Liao <WH...@nu...>
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include "npcx_flash.h"
+
+/*----------------------------------------------------------------------------
+ * NPCX flash driver
+ *----------------------------------------------------------------------------*/
+static void flash_execute_cmd(uint8_t code, uint8_t cts)
+{
+ /* Set UMA code */
+ NPCX_UMA_CODE = code;
+ /* Execute UMA flash transaction by CTS setting */
+ NPCX_UMA_CTS = cts;
+ /* Wait for transaction completed */
+ while (NPCX_IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
+ ;
+}
+
+static void flash_cs_level(uint8_t level)
+{
+ /* Program chip select pin to high/low level */
+ if (level)
+ NPCX_SET_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1);
+ else
+ NPCX_CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1);
+}
+
+static void flash_set_address(uint32_t dest_addr)
+{
+ uint8_t *addr = (uint8_t *)&dest_addr;
+
+ /* Set target flash address */
+ NPCX_UMA_AB2 = addr[2];
+ NPCX_UMA_AB1 = addr[1];
+ NPCX_UMA_AB0 = addr[0];
+}
+
+void delay(uint32_t i)
+{
+ while (i--)
+ ;
+}
+
+static int flash_wait_ready(uint32_t timeout)
+{
+ /* Chip Select down. -- Burst mode */
+ flash_cs_level(0);
+
+ /* Command for Read status register */
+ flash_execute_cmd(NPCX_CMD_READ_STATUS_REG, NPCX_MASK_CMD_ONLY);
+ while (timeout > 0) {
+ /* Read status register */
+ NPCX_UMA_CTS = NPCX_MASK_RD_1BYTE;
+ while (NPCX_IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
+ ;
+
+ if (!(NPCX_UMA_DB0 & NPCX_SPI_FLASH_SR1_BUSY))
+ break;
+
+ if (--timeout > 0)
+ delay(100);
+
+ }; /* Wait for Busy clear */
+
+ /* Chip Select high. */
+ flash_cs_level(1);
+
+ if (timeout == 0)
+ return NPCX_FLASH_STATUS_FAILED_TIMEOUT;
+
+ return NPCX_FLASH_STATUS_OK;
+}
+
+static int flash_write_enable(void)
+{
+ /* Write enable command */
+ flash_execute_cmd(NPCX_CMD_WRITE_EN, NPCX_MASK_CMD_ONLY);
+
+ /* Wait for flash is not busy */
+ int status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
+ if (status != NPCX_FLASH_STATUS_OK)
+ return status;
+
+ if (NPCX_UMA_DB0 & NPCX_SPI_FLASH_SR1_WEL)
+ return NPCX_FLASH_STATUS_OK;
+ else
+ return NPCX_FLASH_STATUS_FAILED;
+}
+
+static void flash_burst_write(uint32_t dest_addr, uint16_t bytes,
+ const uint8_t *data)
+{
+ /* Chip Select down -- Burst mode */
+ flash_cs_level(0);
+
+ /* Set write address */
+ flash_set_address(dest_addr);
+ /* Start programming */
+ flash_execute_cmd(NPCX_CMD_FLASH_PROGRAM, NPCX_MASK_CMD_WR_ADR);
+ for (uint32_t i = 0; i < bytes; i++) {
+ flash_execute_cmd(*data, NPCX_MASK_CMD_WR_ONLY);
+ data++;
+ }
+
+ /* Chip Select up */
+ flash_cs_level(1);
+}
+
+/* The data to write cannot cross 256 Bytes boundary */
+static int flash_program_write(uint32_t addr, uint32_t size,
+ const uint8_t *data)
+{
+ int status = flash_write_enable();
+ if (status != NPCX_FLASH_STATUS_OK)
+ return status;
+
+ flash_burst_write(addr, size, data);
+ return flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
+}
+
+int flash_physical_write(uint32_t offset, uint32_t size, const uint8_t *data)
+{
+ int status;
+ uint32_t trunk_start = (offset + 0xff) & ~0xff;
+
+ /* write head */
+ uint32_t dest_addr = offset;
+ uint32_t write_len = ((trunk_start - offset) > size) ? size : (trunk_start - offset);
+
+ if (write_len) {
+ status = flash_program_write(dest_addr, write_len, data);
+ if (status != NPCX_FLASH_STATUS_OK)
+ return status;
+ data += write_len;
+ }
+
+ dest_addr = trunk_start;
+ size -= write_len;
+
+ /* write remaining data*/
+ while (size > 0) {
+ write_len = (size > NPCX_FLASH_WRITE_SIZE) ?
+ NPCX_FLASH_WRITE_SIZE : size;
+
+ status = flash_program_write(dest_addr, write_len, data);
+ if (status != NPCX_FLASH_STATUS_OK)
+ return status;
+
+ data += write_len;
+ dest_addr += write_len;
+ size -= write_len;
+ }
+
+ return NPCX_FLASH_STATUS_OK;
+}
+
+int flash_physical_erase(uint32_t offset, uint32_t size)
+{
+ /* Alignment has been checked in upper layer */
+ for (; size > 0; size -= NPCX_FLASH_ERASE_SIZE,
+ offset += NPCX_FLASH_ERASE_SIZE) {
+ /* Enable write */
+ int status = flash_write_enable();
+ if (status != NPCX_FLASH_STATUS_OK)
+ return status;
+
+ /* Set erase address */
+ flash_set_address(offset);
+ /* Start erase */
+ flash_execute_cmd(NPCX_CMD_SECTOR_ERASE, NPCX_MASK_CMD_ADR);
+ /* Wait erase completed */
+ status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
+ if (status != NPCX_FLASH_STATUS_OK)
+ return status;
+ }
+
+ return NPCX_FLASH_STATUS_OK;
+}
+
+int flash_physical_erase_all(void)
+{
+ /* Enable write */
+ int status = flash_write_enable();
+ if (status != NPCX_FLASH_STATUS_OK)
+ return status;
+
+ /* Start erase */
+ flash_execute_cmd(NPCX_CMD_CHIP_ERASE, NPCX_MASK_CMD_ONLY);
+
+ /* Wait erase completed */
+ status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
+ if (status != NPCX_FLASH_STATUS_OK)
+ return status;
+
+ return NPCX_FLASH_STATUS_OK;
+}
+
+int flash_physical_clear_stsreg(void)
+{
+ /* Enable write */
+ int status = flash_write_enable();
+ if (status != NPCX_FLASH_STATUS_OK)
+ return status;
+
+ NPCX_UMA_DB0 = 0x0;
+ NPCX_UMA_DB1 = 0x0;
+
+ /* Write status register 1/2 */
+ flash_execute_cmd(NPCX_CMD_WRITE_STATUS_REG, NPCX_MASK_CMD_WR_2BYTE);
+
+ /* Wait writing completed */
+ status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
+ if (status != NPCX_FLASH_STATUS_OK)
+ return status;
+
+ /* Read status register 1/2 for checking */
+ flash_execute_cmd(NPCX_CMD_READ_STATUS_REG, NPCX_MASK_CMD_RD_1BYTE);
+ if (NPCX_UMA_DB0 != 0x00)
+ return NPCX_FLASH_STATUS_FAILED;
+ flash_execute_cmd(NPCX_CMD_READ_STATUS_REG2, NPCX_MASK_CMD_RD_1BYTE);
+ if (NPCX_UMA_DB0 != 0x00)
+ return NPCX_FLASH_STATUS_FAILED;
+
+ return NPCX_FLASH_STATUS_OK;
+}
+
+int flash_get_id(uint32_t *id)
+{
+ flash_execute_cmd(NPCX_CMD_READ_ID, NPCX_MASK_CMD_RD_3BYTE);
+ *id = NPCX_UMA_DB0 << 16 | NPCX_UMA_DB1 << 8 | NPCX_UMA_DB2;
+
+ return NPCX_FLASH_STATUS_OK;
+}
+
+/*----------------------------------------------------------------------------
+ * flash loader function
+ *----------------------------------------------------------------------------*/
+uint32_t flashloader_init(struct npcx_flash_params *params)
+{
+ /* Initialize params buffers */
+ memset(params, 0, sizeof(struct npcx_flash_params));
+
+ return NPCX_FLASH_STATUS_OK;
+}
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *----------------------------------------------------------------------------*/
+/* flashloader parameter structure */
+__attribute__ ((section(".buffers.g_cfg")))
+volatile struct npcx_flash_params g_cfg;
+/* data buffer */
+__attribute__ ((section(".buffers.g_buf")))
+uint8_t g_buf[NPCX_FLASH_LOADER_BUFFER_SIZE];
+
+int main(void)
+{
+ uint32_t id;
+
+ /* set buffer */
+ flashloader_init((struct npcx_flash_params *)&g_cfg);
+
+ /* Avoid F_CS0 toggles while programming the internal flash. */
+ NPCX_SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
+
+ /* clear flash status registers */
+ int status = flash_physical_clear_stsreg();
+ if (status != NPCX_FLASH_STATUS_OK) {
+ while (1)
+ g_cfg.sync = status;
+ }
+
+ while (1) {
+ /* wait command*/
+ while (g_cfg.sync == NPCX_FLASH_LOADER_WAIT)
+ ;
+
+ /* command handler */
+ switch (g_cfg.cmd) {
+ case NPCX_FLASH_CMD_GET_FLASH_ID:
+ status = flash_get_id(&id);
+ if (status == NPCX_FLASH_STATUS_OK) {
+ g_buf[0] = id & 0xff;
+ g_buf[1] = (id >> 8) & 0xff;
+ g_buf[2] = (id >> 16) & 0xff;
+ g_buf[3] = 0x00;
+ }
+ break;
+ case NPCX_FLASH_CMD_ERASE_SECTORS:
+ status = flash_physical_erase(g_cfg.addr, g_cfg.len);
+ break;
+ case NPCX_FLASH_CMD_ERASE_ALL:
+ status = flash_physical_erase_all();
+ break;
+ case NPCX_FLASH_CMD_PROGRAM:
+ status = flash_physical_write(g_cfg.addr,
+ g_cfg.len,
+ g_buf);
+ break;
+ default:
+ status = NPCX_FLASH_STATUS_FAILED_UNKNOWN_COMMAND;
+ break;
+ }
+
+ /* clear & set result for next command */
+ if (status != NPCX_FLASH_STATUS_OK) {
+ g_cfg.sync = status;
+ while (1)
+ ;
+ } else {
+ g_cfg.sync = NPCX_FLASH_LOADER_WAIT;
+ }
+ }
+
+ return 0;
+}
+
+__attribute__ ((section(".stack")))
+__attribute__ ((used))
+static uint32_t stack[NPCX_FLASH_LOADER_STACK_SIZE / 4];
+extern uint32_t _estack;
+extern uint32_t _bss;
+extern uint32_t _ebss;
+
+__attribute__ ((section(".entry")))
+void entry(void)
+{
+ /* set sp from end of stack */
+ __asm(" ldr sp, =_estack - 4");
+
+ main();
+
+ __asm(" bkpt #0x00");
+}
diff --git a/contrib/loaders/flash/npcx/npcx_flash.h b/contrib/loaders/flash/npcx/npcx_flash.h
new file mode 100644
index 000000000..cc4f1ad50
--- /dev/null
+++ b/contrib/loaders/flash/npcx/npcx_flash.h
@@ -0,0 +1,179 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * Copyright (C) 2020 by Nuvoton Technology Corporation
+ * Mulin Chao <ml...@nu...>
+ * Wealian Liao <WH...@nu...>
+ */
+
+#ifndef OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_H
+#define OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_H
+
+#include "npcx_flash_config.h"
+
+/* Bit functions */
+#define NPCX_SET_BIT(reg, bit) ((reg) |= (0x1 << (bit)))
+#define NPCX_CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit))))
+#define NPCX_IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1))
+
+/* Field functions */
+#define NPCX_GET_POS_FIELD(pos, size) (pos)
+#define NPCX_GET_SIZE_FIELD(pos, size) (size)
+#define NPCX_FIELD_POS(field) NPCX_GET_POS_##field
+#define NPCX_FIELD_SIZE(field) NPCX_GET_SIZE_##field
+/* Read field functions */
+#define NPCX_GET_FIELD(reg, field) \
+ _NPCX_GET_FIELD_((reg), NPCX_FIELD_POS(field), NPCX_FIELD_SIZE(field))
+#define _NPCX_GET_FIELD_(reg, f_pos, f_size) \
+ (((reg) >> (f_pos)) & ((1 << (f_size)) - 1))
+/* Write field functions */
+#define NPCX_SET_FIELD(reg, field, value) \
+ _NPCX_SET_FIELD_((reg), NPCX_FIELD_POS(field), NPCX_FIELD_SIZE(field), (value))
+#define _NPCX_SET_FIELD_(reg, f_pos, f_size, value) \
+ ((reg) = ((reg) & (~(((1 << (f_size)) - 1) << (f_pos)))) | ((value) << (f_pos)))
+
+/* Register definitions */
+#define NPCX_REG32_ADDR(addr) ((volatile uint32_t *)(addr))
+#define NPCX_REG16_ADDR(addr) ((volatile uint16_t *)(addr))
+#define NPCX_REG8_ADDR(addr) ((volatile uint8_t *)(addr))
+
+#define NPCX_HW_BYTE(addr) (*NPCX_REG8_ADDR(addr))
+#define NPCX_HW_WORD(addr) (*NPCX_REG16_ADDR(addr))
+#define NPCX_HW_DWORD(addr) (*NPCX_REG32_ADDR(addr))
+
+/* Devalt */
+#define NPCX_SCFG_BASE_ADDR 0x400C3000
+#define NPCX_DEVCNT NPCX_HW_BYTE(NPCX_SCFG_BASE_ADDR + 0x000)
+#define NPCX_DEVALT(n) NPCX_HW_BYTE(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
+
+#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2)
+#define NPCX_DEVCNT_JEN0_HEN 4
+#define NPCX_DEVCNT_JEN1_HEN 5
+#define NPCX_DEVCNT_F_SPI_TRIS 6
+
+/* Pin-mux for SPI/FIU */
+#define NPCX_DEVALT0_SPIP_SL 0
+#define NPCX_DEVALT0_GPIO_NO_SPIP 3
+#define NPCX_DEVALT0_F_SPI_CS1_2 4
+#define NPCX_DEVALT0_F_SPI_CS1_1 5
+#define NPCX_DEVALT0_F_SPI_QUAD 6
+#define NPCX_DEVALT0_NO_F_SPI 7
+
+/* Flash Interface Unit (FIU) registers */
+#define NPCX_FIU_BASE_ADDR 0x40020000
+#define NPCX_FIU_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x000)
+#define NPCX_BURST_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x001)
+#define NPCX_RESP_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x002)
+#define NPCX_SPI_FL_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x014)
+#define NPCX_UMA_CODE NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x016)
+#define NPCX_UMA_AB0 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x017)
+#define NPCX_UMA_AB1 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x018)
+#define NPCX_UMA_AB2 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x019)
+#define NPCX_UMA_DB0 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01A)
+#define NPCX_UMA_DB1 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01B)
+#define NPCX_UMA_DB2 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01C)
+#define NPCX_UMA_DB3 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01D)
+#define NPCX_UMA_CTS NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01E)
+#define NPCX_UMA_ECTS NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01F)
+#define NPCX_UMA_DB0_3 NPCX_HW_DWORD(NPCX_FIU_BASE_ADDR + 0x020)
+#define NPCX_FIU_RD_CMD NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x030)
+#define NPCX_FIU_DMM_CYC NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x032)
+#define NPCX_FIU_EXT_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x033)
+#define NPCX_FIU_UMA_AB0_3 NPCX_HW_DWORD(NPCX_FIU_BASE_ADDR + 0x034)
+
+/* FIU register fields */
+#define NPCX_RESP_CFG_IAD_EN 0
+#define NPCX_RESP_CFG_DEV_SIZE_EX 2
+#define NPCX_UMA_CTS_A_SIZE 3
+#define NPCX_UMA_CTS_C_SIZE 4
+#define NPCX_UMA_CTS_RD_WR 5
+#define NPCX_UMA_CTS_DEV_NUM 6
+#define NPCX_UMA_CTS_EXEC_DONE 7
+#define NPCX_UMA_ECTS_SW_CS0 0
+#define NPCX_UMA_ECTS_SW_CS1 1
+#define NPCX_UMA_ECTS_SEC_CS 2
+#define NPCX_UMA_ECTS_UMA_LOCK 3
+
+/* Flash UMA commands for npcx internal SPI flash */
+#define NPCX_CMD_READ_ID 0x9F
+#define NPCX_CMD_READ_MAN_DEV_ID 0x90
+#define NPCX_CMD_WRITE_EN 0x06
+#define NPCX_CMD_WRITE_STATUS 0x50
+#define NPCX_CMD_READ_STATUS_REG 0x05
+#define NPCX_CMD_READ_STATUS_REG2 0x35
+#define NPCX_CMD_WRITE_STATUS_REG 0x01
+#define NPCX_CMD_FLASH_PROGRAM 0x02
+#define NPCX_CMD_SECTOR_ERASE 0x20
+#define NPCX_CMD_PROGRAM_UINT_SIZE 0x08
+#define NPCX_CMD_PAGE_SIZE 0x00
+#define NPCX_CMD_READ_ID_TYPE 0x47
+#define NPCX_CMD_FAST_READ 0x0B
+#define NPCX_CMD_CHIP_ERASE 0xC7
+
+/*
+ * Status registers for SPI flash
+ */
+#define NPCX_SPI_FLASH_SR2_SUS (1 << 7)
+#define NPCX_SPI_FLASH_SR2_CMP (1 << 6)
+#define NPCX_SPI_FLASH_SR2_LB3 (1 << 5)
+#define NPCX_SPI_FLASH_SR2_LB2 (1 << 4)
+#define NPCX_SPI_FLASH_SR2_LB1 (1 << 3)
+#define NPCX_SPI_FLASH_SR2_QE (1 << 1)
+#define NPCX_SPI_FLASH_SR2_SRP1 (1 << 0)
+#define NPCX_SPI_FLASH_SR1_SRP0 (1 << 7)
+#define NPCX_SPI_FLASH_SR1_SEC (1 << 6)
+#define NPCX_SPI_FLASH_SR1_TB (1 << 5)
+#define NPCX_SPI_FLASH_SR1_BP2 (1 << 4)
+#define NPCX_SPI_FLASH_SR1_BP1 (1 << 3)
+#define NPCX_SPI_FLASH_SR1_BP0 (1 << 2)
+#define NPCX_SPI_FLASH_SR1_WEL (1 << 1)
+#define NPCX_SPI_FLASH_SR1_BUSY (1 << 0)
+
+#define NPCX_MASK_CMD_ONLY (0xC0)
+#define NPCX_MASK_CMD_ADR (0xC0 | 0x08)
+#define NPCX_MASK_CMD_ADR_WR (0xC0 | 0x20 | 0x08 | 0x01)
+#define NPCX_MASK_RD_1BYTE (0xC0 | 0x10 | 0x01)
+#define NPCX_MASK_RD_2BYTE (0xC0 | 0x10 | 0x02)
+#define NPCX_MASK_RD_3BYTE (0xC0 | 0x10 | 0x03)
+#define NPCX_MASK_RD_4BYTE (0xC0 | 0x10 | 0x04)
+#define NPCX_MASK_CMD_RD_1BYTE (0xC0 | 0x01)
+#define NPCX_MASK_CMD_RD_2BYTE (0xC0 | 0x02)
+#define NPCX_MASK_CMD_RD_3BYTE (0xC0 | 0x03)
+#define NPCX_MASK_CMD_RD_4BYTE (0xC0 | 0x04)
+#define NPCX_MASK_CMD_WR_ONLY (0xC0 | 0x20)
+#define NPCX_MASK_CMD_WR_1BYTE (0xC0 | 0x20 | 0x10 | 0x01)
+#define NPCX_MASK_CMD_WR_2BYTE (0xC0 | 0x20 | 0x10 | 0x02)
+#define NPCX_MASK_CMD_WR_ADR (0xC0 | 0x20 | 0x08)
+
+/* Flash loader parameters */
+struct __attribute__((__packed__)) npcx_flash_params {
+ uint32_t addr; /* Address in flash */
+ uint32_t len; /* Number of bytes */
+ uint32_t cmd; /* Command */
+ uint32_t sync; /* Handshake signal */
+};
+
+/* Flash trigger signal */
+enum npcx_flash_handshake {
+ NPCX_FLASH_LOADER_WAIT = 0x0, /* Idle */
+ NPCX_FLASH_LOADER_EXECUTE = 0xFFFFFFFF /* Execute Command */
+};
+
+/* Flash loader command */
+enum npcx_flash_commands {
+ NPCX_FLASH_CMD_NO_ACTION = 0, /* No action, default value */
+ NPCX_FLASH_CMD_GET_FLASH_ID, /* Get the internal flash ID */
+ NPCX_FLASH_CMD_ERASE_SECTORS, /* Erase unprotected sectors */
+ NPCX_FLASH_CMD_ERASE_ALL, /* Erase all */
+ NPCX_FLASH_CMD_PROGRAM, /* Program data */
+};
+
+/* Status */
+enum npcx_flash_status {
+ NPCX_FLASH_STATUS_OK = 0,
+ NPCX_FLASH_STATUS_FAILED_UNKNOWN_COMMAND,
+ NPCX_FLASH_STATUS_FAILED,
+ NPCX_FLASH_STATUS_FAILED_TIMEOUT,
+};
+
+#endif /* OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_H */
diff --git a/contrib/loaders/flash/npcx/npcx_flash.lds b/contrib/loaders/flash/npcx/npcx_flash.lds
new file mode 100644
index 000000000..0d782523a
--- /dev/null
+++ b/contrib/loaders/flash/npcx/npcx_flash.lds
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include "npcx_flash_config.h"
+
+/* Application memory map */
+MEMORY {
+ /* buffer + parameters */
+ BUFFER (RWX) : ORIGIN = NPCX_FLASH_LOADER_PARAMS_ADDR,
+ LENGTH = NPCX_FLASH_LOADER_PARAMS_SIZE + NPCX_FLASH_LOADER_BUFFER_SIZE
+
+ PROGRAM (RWX) : ORIGIN = NPCX_FLASH_LOADER_PROGRAM_ADDR,
+ LENGTH = NPCX_FLASH_LOADER_PROGRAM_SIZE
+}
+
+/* Sections used for flashing */
+SECTIONS
+{
+ .buffers (NOLOAD) :
+ {
+ _buffers = .;
+ *(.buffers.g_cfg)
+ *(.buffers.g_buf)
+ *(.buffers*)
+ _ebuffers = .;
+ } > BUFFER
+
+ .text :
+ {
+ _text = .;
+ *(.entry*)
+ *(.text*)
+ _etext = .;
+ } > PROGRAM
+
+ .data :
+ { _data = .;
+ *(.rodata*)
+ *(.data*)
+ _edata = .;
+ } > PROGRAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ _ebss = .;
+ __bss_end__ = .;
+ } > PROGRAM
+
+ .stack (NOLOAD) :
+ {
+ _stack = .;
+ *(.stack*)
+ _estack = .;
+ } > PROGRAM
+}
diff --git a/contrib/loaders/flash/npcx/npcx_flash_config.h b/contrib/loaders/flash/npcx/npcx_flash_config.h
new file mode 100644
index 000000000..9ec1c5e33
--- /dev/null
+++ b/contrib/loaders/flash/npcx/npcx_flash_config.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * Copyright (C) 2021 by Nuvoton Technology Corporation
+ * Mulin Chao <ml...@nu...>
+ * Wealian Liao <WH...@nu...>
+ */
+
+#ifndef OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_CONFIG_H
+#define OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_CONFIG_H
+
+#define NPCX_FLASH_ABORT_TIMEOUT 0xFFFFFF
+
+/* NPCX chip information */
+#define NPCX_FLASH_WRITE_SIZE 256L /* One page size for write */
+#define NPCX_FLASH_ERASE_SIZE 0x1000
+
+/* NPCX flash loader information */
+#define NPCX_FLASH_LOADER_WORKING_ADDR 0x200C0000
+#define NPCX_FLASH_LOADER_PARAMS_ADDR NPCX_FLASH_LOADER_WORKING_ADDR
+#define NPCX_FLASH_LOADER_PARAMS_SIZE 16
+#define NPCX_FLASH_LOADER_BUFFER_ADDR (NPCX_FLASH_LOADER_PARAMS_ADDR + NPCX_FLASH_LOADER_PARAMS_SIZE)
+#define NPCX_FLASH_LOADER_BUFFER_SIZE NPCX_FLASH_ERASE_SIZE
+#define NPCX_FLASH_LOADER_PROGRAM_ADDR (NPCX_FLASH_LOADER_BUFFER_ADDR + NPCX_FLASH_LOADER_BUFFER_SIZE)
+#define NPCX_FLASH_LOADER_PROGRAM_SIZE 0x1000
+
+/* Stack size in byte. 4 byte size alignment */
+#define NPCX_FLASH_LOADER_STACK_SIZE 400
+
+
+#endif /* OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_CONFIG_H */
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 2759a39d3..9c94c7168 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6777,6 +6777,17 @@ Show information about flash driver.
@end deffn
+@deffn {Flash Driver} {npcx}
+All versions of the NPCX microcontroller families from Nuvoton include internal
+flash. The NPCX flash driver supports the NPCX family of devices. The driver
+automatically recognizes the specific version's flash parameters and
+autoconfigures itself. The flash bank starts at address 0x64000000.
+
+@example
+flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME
+@end example
+@end deffn
+
@deffn {Flash Driver} {nrf5}
All members of the nRF51 microcontroller families from Nordic Semiconductor
include internal flash and use ARM Cortex-M0 core.
diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am
index 532670436..a5ef42210 100644
--- a/src/flash/nor/Makefile.am
+++ b/src/flash/nor/Makefile.am
@@ -44,6 +44,7 @@ NOR_DRIVERS = \
%D%/mrvlqspi.c \
%D%/niietcm4.c \
%D%/non_cfi.c \
+ %D%/npcx.c \
%D%/nrf5.c \
%D%/numicro.c \
%D%/ocl.c \
diff --git a/src/flash/nor/drivers.c b/src/flash/nor/drivers.c
index 6eadc756b..3e35c0954 100644
--- a/src/flash/nor/drivers.c
+++ b/src/flash/nor/drivers.c
@@ -56,6 +56,7 @@ extern const struct flash_driver mdr_flash;
extern const struct flash_driver mrvlqspi_flash;
extern const struct flash_driver msp432_flash;
extern const struct flash_driver niietcm4_flash;
+extern const struct flash_driver npcx_flash;
extern const struct flash_driver nrf5_flash;
extern const struct flash_driver nrf51_flash;
extern const struct flash_driver numicro_flash;
@@ -130,6 +131,7 @@ static const struct flash_driver * const flash_drivers[] = {
&mrvlqspi_flash,
&msp432_flash,
&niietcm4_flash,
+ &npcx_flash,
&nrf5_flash,
&nrf51_flash,
&numicro_flash,
diff --git a/src/flash/nor/npcx.c b/src/flash/nor/npcx.c
new file mode 100644
index 000000000..af623e577
--- /dev/null
+++ b/src/flash/nor/npcx.c
@@ -0,0 +1,524 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * Copyright (C) 2020 by Nuvoton Technology Corporation
+ * Mulin Chao <ml...@nu...>
+ * Wealian Liao <WH...@nu...>
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include <helper/binarybuffer.h>
+#include <helper/time_support.h>
+#include <target/armv7m.h>
+#include "../../../contrib/loaders/flash/npcx/npcx_flash.h"
+
+/* NPCX flash loader */
+const uint8_t npcx_algo[] = {
+#include "../../../contrib/loaders/flash/npcx/npcx_algo.inc"
+};
+
+#define NPCX_FLASH_TIMEOUT_MS 8000
+#define NPCX_FLASH_BASE_ADDR 0x64000000
+
+/* flash list */
+enum npcx_flash_device_index {
+ NPCX_FLASH_256KB = 0,
+ NPCX_FLASH_512KB = 1,
+ NPCX_FLASH_1MB = 2,
+ NPCX_FLASH_UNKNOWN,
+};
+
+struct npcx_flash_bank {
+ const char *family_name;
+ uint32_t sector_length;
+ bool probed;
+ enum npcx_flash_device_index flash;
+ struct working_area *working_area;
+ struct armv7m_algorithm armv7m_info;
+ const uint8_t *algo_code;
+ uint32_t algo_size;
+ uint32_t algo_working_size;
+ uint32_t buffer_addr;
+ uint32_t params_addr;
+};
+
+struct npcx_flash_info {
+ char *name;
+ uint32_t id;
+ uint32_t size;
+};
+
+static const struct npcx_flash_info flash_info[] = {
+ [NPCX_FLASH_256KB] = {
+ .name = "256KB Flash",
+ .id = 0xEF4012,
+ .size = 256 * 1024,
+ },
+ [NPCX_FLASH_512KB] = {
+ .name = "512KB Flash",
+ .id = 0xEF4013,
+ .size = 512 * 1024,
+ },
+ [NPCX_FLASH_1MB] = {
+ .name = "1MB Flash",
+ .id = 0xEF4014,
+ .size = 1024 * 1024,
+ },
+ [NPCX_FLASH_UNKNOWN] = {
+ .name = "Unknown Flash",
+ .size = 0xFFFFFFFF,
+ },
+};
+
+static int npcx_init(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct npcx_flash_bank *npcx_bank = bank->driver_priv;
+
+ /* Check for working area to use for flash helper algorithm */
+ if (npcx_bank->working_area) {
+ target_free_working_area(target, npcx_bank->working_area);
+ npcx_bank->working_area = NULL;
+ }
+
+ int retval = target_alloc_working_area(target, npcx_bank->algo_working_size,
+ &npcx_bank->working_area);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Confirm the defined working address is the area we need to use */
+ if (npcx_bank->working_area->address != NPCX_FLASH_LOADER_WORKING_ADDR) {
+ LOG_ERROR("%s: Invalid working address", npcx_bank->family_name);
+ LOG_INFO("Hint: Use '-work-area-phys 0x%" PRIx32 "' in your target configuration",
+ NPCX_FLASH_LOADER_WORKING_ADDR);
+ target_free_working_area(target, npcx_bank->working_area);
+ npcx_bank->working_area = NULL;
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ /* Write flash helper algorithm into target memory */
+ retval = target_write_buffer(target, NPCX_FLASH_LOADER_PROGRAM_ADDR,
+ npcx_bank->algo_size, npcx_bank->algo_code);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("%s: Failed to load flash helper algorithm",
+ npcx_bank->family_name);
+ target_free_working_area(target, npcx_bank->working_area);
+ npcx_bank->working_area = NULL;
+ return retval;
+ }
+
+ /* Initialize the ARMv7 specific info to run the algorithm */
+ npcx_bank->armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ npcx_bank->armv7m_info.core_mode = ARM_MODE_THREAD;
+
+ /* Begin executing the flash helper algorithm */
+ retval = target_start_algorithm(target, 0, NULL, 0, NULL,
+ NPCX_FLASH_LOADER_PROGRAM_ADDR, 0,
+ &npcx_bank->armv7m_info);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("%s: Failed to start flash helper algorithm",
+ npcx_bank->family_name);
+ target_free_working_area(target, npcx_bank->working_area);
+ npcx_bank->working_area = NULL;
+ return retval;
+ }
+
+ /*
+ * At this point, the algorithm is running on the target and
+ * ready to receive commands and data to flash the target
+ */
+
+ return retval;
+}
+
+static int npcx_quit(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct npcx_flash_bank *npcx_bank = bank->driver_priv;
+
+ /* Regardless of the algo's status, attempt to halt the target */
+ (void)target_halt(target);
+
+ /* Now confirm target halted and clean up from flash helper algorithm */
+ int retval = target_wait_algorithm(target, 0, NULL, 0, NULL, 0,
+ NPCX_FLASH_TIMEOUT_MS, &npcx_bank->armv7m_info);
+
+ target_free_working_area(target, npcx_bank->working_area);
+ npcx_bank->working_area = NULL;
+
+ return retval;
+}
+
+static int npcx_wait_algo_done(struct flash_bank *bank, uint32_t params_addr)
+{
+ struct target *target = bank->target;
+ struct npcx_flash_bank *npcx_bank = bank->driver_priv;
+ uint32_t status_addr = params_addr + offsetof(struct npcx_flash_params, sync);
+ uint32_t status;
+ int64_t start_ms = timeval_ms();
+
+ do {
+ int retval = target_read_u32(target, status_addr, &status);
+ if (retval != ERROR_OK)
+ return retval;
+
+ keep_alive();
+
+ int64_t elapsed_ms = timeval_ms() - start_ms;
+ if (elapsed_ms > NPCX_FLASH_TIMEOUT_MS)
+ break;
+ } while (status == NPCX_FLASH_LOADER_EXECUTE);
+
+ if (status != NPCX_FLASH_LOADER_WAIT) {
+ LOG_ERROR("%s: Flash operation failed, status=0x%" PRIx32,
+ npcx_bank->family_name,
+ status);
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+static enum npcx_flash_device_index npcx_get_flash_id(struct flash_bank *bank, uint32_t *flash_id)
+{
+ struct target *target = bank->target;
+ struct npcx_flash_bank *npcx_bank = bank->driver_priv;
+ struct npcx_flash_params algo_params;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ int retval = npcx_init(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set up algorithm parameters for get flash ID command */
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.cmd, NPCX_FLASH_CMD_GET_FLASH_ID);
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.sync, NPCX_FLASH_LOADER_WAIT);
+
+ /* Issue flash helper algorithm parameters for get flash ID */
+ retval = target_write_buffer(target, npcx_bank->params_addr,
+ sizeof(algo_params), (uint8_t *)&algo_params);
+ if (retval != ERROR_OK) {
+ (void)npcx_quit(bank);
+ return retval;
+ }
+
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.sync, NPCX_FLASH_LOADER_EXECUTE);
+ retval = target_write_buffer(target, npcx_bank->params_addr,
+ sizeof(algo_params), (uint8_t *)&algo_params);
+
+ /* If no error, wait for finishing */
+ if (retval == ERROR_OK) {
+ retval = npcx_wait_algo_done(bank, npcx_bank->params_addr);
+ if (retval == ERROR_OK)
+ target_read_u32(target, NPCX_FLASH_LOADER_BUFFER_ADDR, flash_id);
+ }
+
+ /* Regardless of errors, try to close down algo */
+ (void)npcx_quit(bank);
+
+ return retval;
+}
+
+static int npcx_get_flash(uint32_t flash_id)
+{
+ for (uint32_t i = 0; i < ARRAY_SIZE(flash_info) - 1; i++) {
+ if (flash_info[i].id == flash_id)
+ return i;
+ }
+
+ return NPCX_FLASH_UNKNOWN;
+}
+
+static int npcx_probe(struct flash_bank *bank)
+{
+ struct npcx_flash_bank *npcx_bank = bank->driver_priv;
+ uint32_t sector_length = NPCX_FLASH_ERASE_SIZE;
+ uint32_t flash_id;
+
+ /* Set up appropriate flash helper algorithm */
+ npcx_bank->algo_code = npcx_algo;
+ npcx_bank->algo_size = sizeof(npcx_algo);
+ npcx_bank->algo_working_size = NPCX_FLASH_LOADER_PARAMS_SIZE +
+ NPCX_FLASH_LOADER_BUFFER_SIZE +
+ NPCX_FLASH_LOADER_PROGRAM_SIZE;
+ npcx_bank->buffer_addr = NPCX_FLASH_LOADER_BUFFER_ADDR;
+ npcx_bank->params_addr = NPCX_FLASH_LOADER_PARAMS_ADDR;
+
+ int retval = npcx_get_flash_id(bank, &flash_id);
+ if (retval != ERROR_OK)
+ return retval;
+
+ npcx_bank->flash = npcx_get_flash(flash_id);
+
+ unsigned int num_sectors = flash_info[npcx_bank->flash].size / sector_length;
+
+ bank->sectors = calloc(num_sectors, sizeof(struct flash_sector));
+ if (!bank->sectors) {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
+
+ bank->base = NPCX_FLASH_BASE_ADDR;
+ bank->num_sectors = num_sectors;
+ bank->size = num_sectors * sector_length;
+ bank->write_start_alignment = 0;
+ bank->write_end_alignment = 0;
+ npcx_bank->sector_length = sector_length;
+
+ for (unsigned int i = 0; i < num_sectors; i++) {
+ bank->sectors[i].offset = i * sector_length;
+ bank->sectors[i].size = sector_length;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = 0;
+ }
+
+ /* We've successfully determined the stats on the flash bank */
+ npcx_bank->probed = true;
+
+ /* If we fall through to here, then all went well */
+ return ERROR_OK;
+}
+
+static int npcx_auto_probe(struct flash_bank *bank)
+{
+ struct npcx_flash_bank *npcx_bank = bank->driver_priv;
+ int retval = ERROR_OK;
+
+ if (!npcx_bank->probed)
+ retval = npcx_probe(bank);
+
+ return retval;
+}
+
+FLASH_BANK_COMMAND_HANDLER(npcx_flash_bank_command)
+{
+ struct npcx_flash_bank *npcx_bank;
+
+ if (CMD_ARGC < 6)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ npcx_bank = calloc(1, sizeof(struct npcx_flash_bank));
+ if (!npcx_bank) {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
+
+ /* Initialize private flash information */
+ npcx_bank->family_name = "npcx";
+ npcx_bank->sector_length = NPCX_FLASH_ERASE_SIZE;
+
+ /* Finish initialization of bank */
+ bank->driver_priv = npcx_bank;
+ bank->next = NULL;
+
+ return ERROR_OK;
+}
+
+static int npcx_chip_erase(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct npcx_flash_bank *npcx_bank = bank->driver_priv;
+ struct npcx_flash_params algo_params;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ /* Make sure we've probed the flash to get the device and size */
+ int retval = npcx_auto_probe(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = npcx_init(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set up algorithm parameters for chip erase command */
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.cmd, NPCX_FLASH_CMD_ERASE_ALL);
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.sync, NPCX_FLASH_LOADER_WAIT);
+
+ /* Set algorithm parameters */
+ retval = target_write_buffer(target, npcx_bank->params_addr,
+ sizeof(algo_params), (uint8_t *)&algo_params);
+ if (retval != ERROR_OK) {
+ (void)npcx_quit(bank);
+ return retval;
+ }
+
+ /* Issue flash helper algorithm parameters for chip erase */
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.sync, NPCX_FLASH_LOADER_EXECUTE);
+ retval = target_write_buffer(target, npcx_bank->params_addr,
+ sizeof(algo_params), (uint8_t *)&algo_params);
+
+ /* If no error, wait for chip erase finish */
+ if (retval == ERROR_OK)
+ retval = npcx_wait_algo_done(bank, npcx_bank->params_addr);
+
+ /* Regardless of errors, try to close down algo */
+ (void)npcx_quit(bank);
+
+ return retval;
+}
+
+static int npcx_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
+{
+ struct target *target = bank->target;
+ struct npcx_flash_bank *npcx_bank = bank->driver_priv;
+ struct npcx_flash_params algo_params;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if ((first == 0) && (last == (bank->num_sectors - 1))) {
+ /* Request chip erase */
+ return npcx_chip_erase(bank);
+ }
+
+ uint32_t address = first * npcx_bank->sector_length;
+ uint32_t length = (last - first + 1) * npcx_bank->sector_length;
+
+ /* Make sure we've probed the flash to get the device and size */
+ int retval = npcx_auto_probe(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = npcx_init(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set up algorithm parameters for erase command */
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.addr, address);
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.len, length);
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.cmd, NPCX_FLASH_CMD_ERASE_SECTORS);
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.sync, NPCX_FLASH_LOADER_WAIT);
+
+ /* Set algorithm parameters */
+ retval = target_write_buffer(target, npcx_bank->params_addr,
+ sizeof(algo_params), (uint8_t *)&algo_params);
+ if (retval != ERROR_OK) {
+ (void)npcx_quit(bank);
+ return retval;
+ }
+
+ /* Issue flash helper algorithm parameters for erase */
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.sync, NPCX_FLASH_LOADER_EXECUTE);
+ retval = target_write_buffer(target, npcx_bank->params_addr,
+ sizeof(algo_params), (uint8_t *)&algo_params);
+
+ /* If no error, wait for erase to finish */
+ if (retval == ERROR_OK)
+ retval = npcx_wait_algo_done(bank, npcx_bank->params_addr);
+
+ /* Regardless of errors, try to close down algo */
+ (void)npcx_quit(bank);
+
+ return retval;
+}
+
+static int npcx_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ struct npcx_flash_bank *npcx_bank = bank->driver_priv;
+ struct npcx_flash_params algo_params;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ /* Make sure we've probed the flash to get the device and size */
+ int retval = npcx_auto_probe(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = npcx_init(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Initialize algorithm parameters to default values */
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.cmd, NPCX_FLASH_CMD_PROGRAM);
+
+ uint32_t address = offset;
+
+ while (count > 0) {
+ uint32_t size = (count > NPCX_FLASH_LOADER_BUFFER_SIZE) ?
+ NPCX_FLASH_LOADER_BUFFER_SIZE : count;
+
+ /* Put the data into buffer */
+ retval = target_write_buffer(target, npcx_bank->buffer_addr,
+ size, buffer);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Unable to write data to target memory");
+ break;
+ }
+
+ /* Update algo parameters for flash write */
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.addr, address);
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.len, size);
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.sync, NPCX_FLASH_LOADER_WAIT);
+
+ /* Set algorithm parameters */
+ retval = target_write_buffer(target, npcx_bank->params_addr,
+ sizeof(algo_params), (uint8_t *)&algo_params);
+ if (retval != ERROR_OK)
+ break;
+
+ /* Issue flash helper algorithm parameters for flash write */
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.sync, NPCX_FLASH_LOADER_EXECUTE);
+ retval = target_write_buffer(target, npcx_bank->params_addr,
+ sizeof(algo_params), (uint8_t *)&algo_params);
+ if (retval != ERROR_OK)
+ break;
+
+ /* Wait for flash write finish */
+ retval = npcx_wait_algo_done(bank, npcx_bank->params_addr);
+ if (retval != ERROR_OK)
+ break;
+
+ count -= size;
+ buffer += size;
+ address += size;
+ }
+
+ /* Regardless of errors, try to close down algo */
+ (void)npcx_quit(bank);
+
+ return retval;
+}
+
+static int npcx_info(struct flash_bank *bank, struct command_invocation *cmd)
+{
+ struct npcx_flash_bank *npcx_bank = bank->driver_priv;
+
+ command_print_sameline(cmd, "%s flash: %s\n",
+ npcx_bank->family_name,
+ flash_info[npcx_bank->flash].name);
+
+ return ERROR_OK;
+}
+
+const struct flash_driver npcx_flash = {
+ .name = "npcx",
+ .flash_bank_command = npcx_flash_bank_command,
+ .erase = npcx_erase,
+ .write = npcx_write,
+ .read = default_flash_read,
+ .probe = npcx_probe,
+ .auto_probe = npcx_auto_probe,
+ .erase_check = default_flash_blank_check,
+ .info = npcx_info,
+ .free_driver_priv = default_flash_free_driver_priv,
+};
diff --git a/tcl/board/npcx_evb.cfg b/tcl/board/npcx_evb.cfg
new file mode 100644
index 000000000..4f28bc964
--- /dev/null
+++ b/tcl/board/npcx_evb.cfg
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Nuvoton NPCX Evaluation Board
+
+source [find interface/jlink.cfg]
+transport select swd
+
+source [find target/npcx.cfg]
diff --git a/tcl/target/npcx.cfg b/tcl/target/npcx.cfg
new file mode 100644
index 000000000..1a21e1f7f
--- /dev/null
+++ b/tcl/target/npcx.cfg
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for Nuvoton NPCX Cortex-M4 Series
+
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+# Set Chipname
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME NPCX_M4
+}
+
+# SWD DAP ID of Nuvoton NPCX Cortex-M4.
+if { [info exists CPUDAPID ] } {
+ set _CPUDAPID $CPUDAPID
+} else {
+ set _CPUDAPID 0x4BA00477
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 32kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x8000
+}
+
+# Debug Adapter Target Settings
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x200c0000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# Initial JTAG/SWD speed
+# For safety purposes, set for the lowest cpu clock configuration
+# 4MHz / 6 = 666KHz, so use 600KHz for it
+adapter speed 600
+
+# For safety purposes, set for the lowest cpu clock configuration
+$_TARGETNAME configure -event reset-start {adapter speed 600}
+
+# use sysresetreq to perform a system reset
+cortex_m reset_config sysresetreq
+
+# flash configuration
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME
-----------------------------------------------------------------------
Summary of changes:
contrib/loaders/flash/npcx/Makefile | 65 +++
contrib/loaders/flash/npcx/npcx_algo.inc | 60 +++
contrib/loaders/flash/npcx/npcx_flash.c | 342 ++++++++++++++++
contrib/loaders/flash/npcx/npcx_flash.h | 179 +++++++++
contrib/loaders/flash/npcx/npcx_flash.lds | 58 +++
contrib/loaders/flash/npcx/npcx_flash_config.h | 31 ++
doc/openocd.texi | 11 +
src/flash/nor/Makefile.am | 1 +
src/flash/nor/drivers.c | 2 +
src/flash/nor/npcx.c | 524 +++++++++++++++++++++++++
tcl/board/npcx_evb.cfg | 8 +
tcl/target/npcx.cfg | 51 +++
12 files changed, 1332 insertions(+)
create mode 100644 contrib/loaders/flash/npcx/Makefile
create mode 100644 contrib/loaders/flash/npcx/npcx_algo.inc
create mode 100644 contrib/loaders/flash/npcx/npcx_flash.c
create mode 100644 contrib/loaders/flash/npcx/npcx_flash.h
create mode 100644 contrib/loaders/flash/npcx/npcx_flash.lds
create mode 100644 contrib/loaders/flash/npcx/npcx_flash_config.h
create mode 100644 src/flash/nor/npcx.c
create mode 100644 tcl/board/npcx_evb.cfg
create mode 100644 tcl/target/npcx.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-08-31 04:13:19
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a098816a6557e5882bf088ab12a06b94934f30ce (commit)
via 259e400276e939f7c8503068312e940dc25bdf46 (commit)
from 9a9e9e2c666dcb4987421f89d3b09ff9951cb0a1 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit a098816a6557e5882bf088ab12a06b94934f30ce
Author: Tarek BOCHKATI <tar...@gm...>
Date: Thu Aug 19 01:30:38 2021 +0100
server/telnet: add variables auto-completion
Change-Id: Ie690afad18065cde8d754c8af50dacd9f467c8e5
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6442
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/server/telnet_server.c b/src/server/telnet_server.c
index 13fbc3fda..2ebcff163 100644
--- a/src/server/telnet_server.c
+++ b/src/server/telnet_server.c
@@ -592,16 +592,30 @@ static void telnet_auto_complete(struct connection *connection)
LIST_HEAD(matches);
- /* user command sequence, either at line beginning
- * or we start over after these characters ';', '[', '{' */
+ /* - user command sequence, either at line beginning
+ * or we start over after these characters ';', '[', '{'
+ * - user variable sequence, start after the character '$'
+ * and do not contain white spaces */
+ bool is_variable_auto_completion = false;
+ bool have_spaces = false;
size_t seq_start = (t_con->line_cursor == 0) ? 0 : (t_con->line_cursor - 1);
- while (seq_start > 0) {
+ while (1) {
char c = t_con->line[seq_start];
+
if (c == ';' || c == '[' || c == '{') {
seq_start++;
break;
+ } else if (c == ' ') {
+ have_spaces = true;
+ } else if (c == '$' && !have_spaces) {
+ is_variable_auto_completion = true;
+ seq_start++;
+ break;
}
+ if (seq_start == 0)
+ break;
+
seq_start--;
}
@@ -631,7 +645,12 @@ static void telnet_auto_complete(struct connection *connection)
query[usr_cmd_len] = '\0';
/* filter commands */
- char *query_cmd = alloc_printf("_telnet_autocomplete_helper {%s*}", query);
+ char *query_cmd;
+
+ if (is_variable_auto_completion)
+ query_cmd = alloc_printf("lsort [info vars {%s*}]", query);
+ else
+ query_cmd = alloc_printf("_telnet_autocomplete_helper {%s*}", query);
if (!query_cmd) {
LOG_ERROR("Out of memory");
@@ -659,20 +678,22 @@ static void telnet_auto_complete(struct connection *connection)
/* validate the command */
bool ignore_cmd = false;
- Jim_Cmd *jim_cmd = Jim_GetCommand(command_context->interp, elem, JIM_NONE);
-
- if (!jim_cmd) {
- /* Why we are here? Let's ignore it! */
- ignore_cmd = true;
- } else if (jimcmd_is_oocd_command(jim_cmd)) {
- struct command *cmd = jimcmd_privdata(jim_cmd);
+ if (!is_variable_auto_completion) {
+ Jim_Cmd *jim_cmd = Jim_GetCommand(command_context->interp, elem, JIM_NONE);
- if (cmd && !cmd->handler && !cmd->jim_handler) {
- /* Initial part of a multi-word command. Ignore it! */
- ignore_cmd = true;
- } else if (cmd && cmd->mode == COMMAND_CONFIG) {
- /* Not executable after config phase. Ignore it! */
+ if (!jim_cmd) {
+ /* Why we are here? Let's ignore it! */
ignore_cmd = true;
+ } else if (jimcmd_is_oocd_command(jim_cmd)) {
+ struct command *cmd = jimcmd_privdata(jim_cmd);
+
+ if (cmd && !cmd->handler && !cmd->jim_handler) {
+ /* Initial part of a multi-word command. Ignore it! */
+ ignore_cmd = true;
+ } else if (cmd && cmd->mode == COMMAND_CONFIG) {
+ /* Not executable after config phase. Ignore it! */
+ ignore_cmd = true;
+ }
}
}
commit 259e400276e939f7c8503068312e940dc25bdf46
Author: Tarek BOCHKATI <tar...@gm...>
Date: Wed Aug 18 18:41:49 2021 +0100
server/telnet: simplify telnet_input function
running complexity on this file tells that:
NOTE: proc telnet_input in file telnet_server.c line 576
nesting depth reached level 8
==> *seriously consider rewriting the procedure*.
Complexity Scores
Score | ln-ct | nc-lns| file-name(line): proc-name
319 272 226 src/server/telnet_server.c(576): telnet_input
total nc-lns 226
so try to reduce the complexity score of telnet_input function
Change-Id: I64ecb0c54da83c27a343f2a1df99fc8f9484572a
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6440
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/server/telnet_server.c b/src/server/telnet_server.c
index 36b017c58..13fbc3fda 100644
--- a/src/server/telnet_server.c
+++ b/src/server/telnet_server.c
@@ -320,6 +320,32 @@ static void telnet_history_down(struct connection *connection)
telnet_history_go(connection, next_history);
}
+static void telnet_history_add(struct connection *connection)
+{
+ struct telnet_connection *t_con = connection->priv;
+
+ /* save only non-blank not repeating lines in the history */
+ char *prev_line = t_con->history[(t_con->current_history > 0) ?
+ t_con->current_history - 1 : TELNET_LINE_HISTORY_SIZE-1];
+
+ if (*t_con->line && (!prev_line || strcmp(t_con->line, prev_line))) {
+ /* if the history slot is already taken, free it */
+ free(t_con->history[t_con->next_history]);
+
+ /* add line to history */
+ t_con->history[t_con->next_history] = strdup(t_con->line);
+
+ /* wrap history at TELNET_LINE_HISTORY_SIZE */
+ t_con->next_history = (t_con->next_history + 1) % TELNET_LINE_HISTORY_SIZE;
+
+ /* current history line starts at the new entry */
+ t_con->current_history = t_con->next_history;
+
+ free(t_con->history[t_con->current_history]);
+ t_con->history[t_con->current_history] = strdup("");
+ }
+}
+
static int telnet_history_print(struct connection *connection)
{
struct telnet_connection *tc;
@@ -423,6 +449,137 @@ static bool telnet_insert(struct connection *connection, const void *data, size_
return true;
}
+static void telnet_delete_character(struct connection *connection)
+{
+ struct telnet_connection *t_con = connection->priv;
+
+ if (t_con->line_cursor == 0)
+ return;
+
+ if (t_con->line_cursor != t_con->line_size) {
+ size_t i;
+ telnet_write(connection, "\b", 1);
+ t_con->line_cursor--;
+ t_con->line_size--;
+ memmove(t_con->line + t_con->line_cursor,
+ t_con->line + t_con->line_cursor + 1,
+ t_con->line_size -
+ t_con->line_cursor);
+
+ telnet_write(connection,
+ t_con->line + t_con->line_cursor,
+ t_con->line_size -
+ t_con->line_cursor);
+ telnet_write(connection, " \b", 2);
+ for (i = t_con->line_cursor; i < t_con->line_size; i++)
+ telnet_write(connection, "\b", 1);
+ } else {
+ t_con->line_size--;
+ t_con->line_cursor--;
+ /* back space: move the 'printer' head one char
+ * back, overwrite with space, move back again */
+ telnet_write(connection, "\b \b", 3);
+ }
+}
+
+static void telnet_remove_character(struct connection *connection)
+{
+ struct telnet_connection *t_con = connection->priv;
+
+ if (t_con->line_cursor < t_con->line_size) {
+ size_t i;
+ t_con->line_size--;
+ /* remove char from line buffer */
+ memmove(t_con->line + t_con->line_cursor,
+ t_con->line + t_con->line_cursor + 1,
+ t_con->line_size - t_con->line_cursor);
+
+ /* print remainder of buffer */
+ telnet_write(connection, t_con->line + t_con->line_cursor,
+ t_con->line_size - t_con->line_cursor);
+ /* overwrite last char with whitespace */
+ telnet_write(connection, " \b", 2);
+
+ /* move back to cursor position*/
+ for (i = t_con->line_cursor; i < t_con->line_size; i++)
+ telnet_write(connection, "\b", 1);
+ }
+}
+
+static int telnet_exec_line(struct connection *connection)
+{
+ struct telnet_connection *t_con = connection->priv;
+ struct command_context *command_context = connection->cmd_ctx;
+ int retval;
+
+ telnet_write(connection, "\r\n\x00", 3);
+
+ if (strcmp(t_con->line, "history") == 0) {
+ retval = telnet_history_print(connection);
+
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+ }
+
+ telnet_history_add(connection);
+
+ t_con->line_size = 0;
+
+ /* to suppress prompt in log callback during command execution */
+ t_con->prompt_visible = false;
+
+ if (strcmp(t_con->line, "shutdown") == 0)
+ telnet_save_history(t_con);
+
+ retval = command_run_line(command_context, t_con->line);
+
+ t_con->line_cursor = 0;
+ t_con->prompt_visible = true;
+
+ if (retval == ERROR_COMMAND_CLOSE_CONNECTION)
+ return ERROR_SERVER_REMOTE_CLOSED;
+
+ /* the prompt is always placed at the line beginning */
+ telnet_write(connection, "\r", 1);
+
+ retval = telnet_prompt(connection);
+ if (retval == ERROR_SERVER_REMOTE_CLOSED)
+ return ERROR_SERVER_REMOTE_CLOSED;
+
+ return ERROR_OK;
+}
+
+static void telnet_cut_line_to_end(struct connection *connection)
+{
+ struct telnet_connection *t_con = connection->priv;
+
+ /* FIXME: currently this function does not save to clipboard */
+
+ if (t_con->line_cursor < t_con->line_size) {
+ /* overwrite with space, until end of line, move back */
+ for (size_t i = t_con->line_cursor; i < t_con->line_size; i++)
+ telnet_write(connection, " ", 1);
+ for (size_t i = t_con->line_cursor; i < t_con->line_size; i++)
+ telnet_write(connection, "\b", 1);
+ t_con->line[t_con->line_cursor] = '\0';
+ t_con->line_size = t_con->line_cursor;
+ }
+}
+
+static void telnet_interrupt(struct connection *connection)
+{
+ struct telnet_connection *t_con = connection->priv;
+
+ /* print '^C' at line end, and display a new command prompt */
+ telnet_move_cursor(connection, t_con->line_size);
+ telnet_write(connection, "^C\n\r", 4);
+ t_con->line_cursor = 0;
+ t_con->line_size = 0;
+ telnet_prompt(connection);
+}
+
static void telnet_auto_complete(struct connection *connection)
{
struct telnet_connection *t_con = connection->priv;
@@ -591,7 +748,6 @@ static int telnet_input(struct connection *connection)
unsigned char buffer[TELNET_BUFFER_SIZE];
unsigned char *buf_p;
struct telnet_connection *t_con = connection->priv;
- struct command_context *command_context = connection->cmd_ctx;
bytes_read = connection_read(connection, buffer, TELNET_BUFFER_SIZE);
@@ -630,108 +786,20 @@ static int telnet_input(struct connection *connection)
}
t_con->line[t_con->line_size] = 0;
- telnet_write(connection, "\r\n\x00", 3);
-
- if (strcmp(t_con->line, "history") == 0) {
- retval = telnet_history_print(connection);
-
- if (retval != ERROR_OK)
- return retval;
-
- continue;
- }
-
- /* save only non-blank not repeating lines in the history */
- char *prev_line = t_con->history[(t_con->current_history > 0) ?
- t_con->current_history - 1 : TELNET_LINE_HISTORY_SIZE-1];
- if (*t_con->line && (!prev_line ||
- strcmp(t_con->line, prev_line))) {
- /* if the history slot is already taken, free it */
- free(t_con->history[t_con->next_history]);
-
- /* add line to history */
- t_con->history[t_con->next_history] = strdup(t_con->line);
-
- /* wrap history at TELNET_LINE_HISTORY_SIZE */
- t_con->next_history = (t_con->next_history + 1) %
- TELNET_LINE_HISTORY_SIZE;
-
- /* current history line starts at the new entry */
- t_con->current_history =
- t_con->next_history;
-
- free(t_con->history[t_con->current_history]);
- t_con->history[t_con->current_history] = strdup("");
- }
-
- t_con->line_size = 0;
-
- /* to suppress prompt in log callback during command execution */
- t_con->prompt_visible = false;
-
- if (strcmp(t_con->line, "shutdown") == 0)
- telnet_save_history(t_con);
-
- retval = command_run_line(command_context, t_con->line);
-
- t_con->line_cursor = 0;
- t_con->prompt_visible = true;
-
- if (retval == ERROR_COMMAND_CLOSE_CONNECTION)
- return ERROR_SERVER_REMOTE_CLOSED;
-
- /* the prompt is always * placed at the line beginning */
- telnet_write(connection, "\r", 1);
-
- retval = telnet_prompt(connection);
- if (retval == ERROR_SERVER_REMOTE_CLOSED)
- return ERROR_SERVER_REMOTE_CLOSED;
-
+ retval = telnet_exec_line(connection);
+ if (retval != ERROR_OK)
+ return retval;
} else if ((*buf_p == 0x7f) || (*buf_p == 0x8)) { /* delete character */
- if (t_con->line_cursor > 0) {
- if (t_con->line_cursor != t_con->line_size) {
- size_t i;
- telnet_write(connection, "\b", 1);
- t_con->line_cursor--;
- t_con->line_size--;
- memmove(t_con->line + t_con->line_cursor,
- t_con->line + t_con->line_cursor + 1,
- t_con->line_size -
- t_con->line_cursor);
-
- telnet_write(connection,
- t_con->line + t_con->line_cursor,
- t_con->line_size -
- t_con->line_cursor);
- telnet_write(connection, " \b", 2);
- for (i = t_con->line_cursor; i < t_con->line_size; i++)
- telnet_write(connection, "\b", 1);
- } else {
- t_con->line_size--;
- t_con->line_cursor--;
- /* back space: move the 'printer' head one char
- * back, overwrite with space, move back again */
- telnet_write(connection, "\b \b", 3);
- }
- }
+ telnet_delete_character(connection);
} else if (*buf_p == 0x15) { /* clear line */
telnet_clear_line(connection, t_con);
} else if (*buf_p == CTRL('B')) { /* cursor left */
- if (t_con->line_cursor > 0) {
- telnet_write(connection, "\b", 1);
- t_con->line_cursor--;
- }
+ telnet_move_cursor(connection, t_con->line_cursor - 1);
t_con->state = TELNET_STATE_DATA;
} else if (*buf_p == CTRL('C')) { /* interrupt */
- /* print '^C' at line end, and display a new command prompt */
- telnet_move_cursor(connection, t_con->line_size);
- telnet_write(connection, "^C\n\r", 4);
- t_con->line_cursor = 0;
- t_con->line_size = 0;
- telnet_prompt(connection);
+ telnet_interrupt(connection);
} else if (*buf_p == CTRL('F')) { /* cursor right */
- if (t_con->line_cursor < t_con->line_size)
- telnet_write(connection, t_con->line + t_con->line_cursor++, 1);
+ telnet_move_cursor(connection, t_con->line_cursor + 1);
t_con->state = TELNET_STATE_DATA;
} else if (*buf_p == CTRL('P')) { /* cursor up */
telnet_history_up(connection);
@@ -742,15 +810,7 @@ static int telnet_input(struct connection *connection)
} else if (*buf_p == CTRL('E')) { /* move the cursor to the end of the line */
telnet_move_cursor(connection, t_con->line_size);
} else if (*buf_p == CTRL('K')) { /* kill line to end */
- if (t_con->line_cursor < t_con->line_size) {
- /* overwrite with space, until end of line, move back */
- for (size_t i = t_con->line_cursor; i < t_con->line_size; i++)
- telnet_write(connection, " ", 1);
- for (size_t i = t_con->line_cursor; i < t_con->line_size; i++)
- telnet_write(connection, "\b", 1);
- t_con->line[t_con->line_cursor] = '\0';
- t_con->line_size = t_con->line_cursor;
- }
+ telnet_cut_line_to_end(connection);
} else if (*buf_p == '\t') {
telnet_auto_complete(connection);
} else {
@@ -788,15 +848,10 @@ static int telnet_input(struct connection *connection)
case TELNET_STATE_ESCAPE:
if (t_con->last_escape == '[') {
if (*buf_p == 'D') { /* cursor left */
- if (t_con->line_cursor > 0) {
- telnet_write(connection, "\b", 1);
- t_con->line_cursor--;
- }
+ telnet_move_cursor(connection, t_con->line_cursor - 1);
t_con->state = TELNET_STATE_DATA;
} else if (*buf_p == 'C') { /* cursor right */
- if (t_con->line_cursor < t_con->line_size)
- telnet_write(connection,
- t_con->line + t_con->line_cursor++, 1);
+ telnet_move_cursor(connection, t_con->line_cursor + 1);
t_con->state = TELNET_STATE_DATA;
} else if (*buf_p == 'A') { /* cursor up */
telnet_history_up(connection);
@@ -816,25 +871,7 @@ static int telnet_input(struct connection *connection)
} else if (t_con->last_escape == '3') {
/* Remove character */
if (*buf_p == '~') {
- if (t_con->line_cursor < t_con->line_size) {
- size_t i;
- t_con->line_size--;
- /* remove char from line buffer */
- memmove(t_con->line + t_con->line_cursor,
- t_con->line + t_con->line_cursor + 1,
- t_con->line_size - t_con->line_cursor);
-
- /* print remainder of buffer */
- telnet_write(connection, t_con->line + t_con->line_cursor,
- t_con->line_size - t_con->line_cursor);
- /* overwrite last char with whitespace */
- telnet_write(connection, " \b", 2);
-
- /* move back to cursor position*/
- for (i = t_con->line_cursor; i < t_con->line_size; i++)
- telnet_write(connection, "\b", 1);
- }
-
+ telnet_remove_character(connection);
t_con->state = TELNET_STATE_DATA;
} else
t_con->state = TELNET_STATE_DATA;
-----------------------------------------------------------------------
Summary of changes:
src/server/telnet_server.c | 352 ++++++++++++++++++++++++++-------------------
1 file changed, 205 insertions(+), 147 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-08-30 13:54:32
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 9a9e9e2c666dcb4987421f89d3b09ff9951cb0a1 (commit)
from 70cd395f3f0b7f7974125ce6e728980e855626ea (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 9a9e9e2c666dcb4987421f89d3b09ff9951cb0a1
Author: Tarek BOCHKATI <tar...@gm...>
Date: Wed Aug 18 19:55:48 2021 +0100
server/telnet: enhance telnet_move_cursor
instrument the telnet_move_cursor to detect when there is no change
of cursor position and if the requested new position is out of bounds.
Change-Id: I24da877e538a458da6d2f8ddc2a681eee404d2cb
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6441
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/server/telnet_server.c b/src/server/telnet_server.c
index f7b3f6449..36b017c58 100644
--- a/src/server/telnet_server.c
+++ b/src/server/telnet_server.c
@@ -352,10 +352,14 @@ static int telnet_history_print(struct connection *connection)
static void telnet_move_cursor(struct connection *connection, size_t pos)
{
- struct telnet_connection *tc;
+ struct telnet_connection *tc = connection->priv;
size_t tmp;
- tc = connection->priv;
+ if (pos == tc->line_cursor) /* nothing to do */
+ return;
+
+ if (pos > tc->line_size) /* out of bounds */
+ return;
if (pos < tc->line_cursor) {
tmp = tc->line_cursor - pos;
-----------------------------------------------------------------------
Summary of changes:
src/server/telnet_server.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-08-30 13:54:13
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 70cd395f3f0b7f7974125ce6e728980e855626ea (commit)
from efe944dfc9fa9041ec2e006b702e9830f60f04bc (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 70cd395f3f0b7f7974125ce6e728980e855626ea
Author: Tarek BOCHKATI <tar...@gm...>
Date: Tue Aug 17 13:29:56 2021 +0100
server/telnet: support 'CTRL+C'
like in terminal 'CTRL+C':
- keeps the line content so the user can refer to it (like copy/paste)
- marks the line with '^C', as hint that the command was not executed
- permit the user to write a new command
Change-Id: Ib784c827d64fdc439a35db461d8387a62d3bfbbf
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6439
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/server/telnet_server.c b/src/server/telnet_server.c
index 253591ec9..f7b3f6449 100644
--- a/src/server/telnet_server.c
+++ b/src/server/telnet_server.c
@@ -718,6 +718,13 @@ static int telnet_input(struct connection *connection)
t_con->line_cursor--;
}
t_con->state = TELNET_STATE_DATA;
+ } else if (*buf_p == CTRL('C')) { /* interrupt */
+ /* print '^C' at line end, and display a new command prompt */
+ telnet_move_cursor(connection, t_con->line_size);
+ telnet_write(connection, "^C\n\r", 4);
+ t_con->line_cursor = 0;
+ t_con->line_size = 0;
+ telnet_prompt(connection);
} else if (*buf_p == CTRL('F')) { /* cursor right */
if (t_con->line_cursor < t_con->line_size)
telnet_write(connection, t_con->line + t_con->line_cursor++, 1);
-----------------------------------------------------------------------
Summary of changes:
src/server/telnet_server.c | 7 +++++++
1 file changed, 7 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2021-08-30 13:53:56
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via efe944dfc9fa9041ec2e006b702e9830f60f04bc (commit)
from 12e2dfd31ff07d9d13c7f66b799fad90a2698428 (commit)
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- Log -----------------------------------------------------------------
commit efe944dfc9fa9041ec2e006b702e9830f60f04bc
Author: Tarek BOCHKATI <tar...@gm...>
Date: Tue Aug 17 13:24:56 2021 +0100
server/telnet: cleanup the if statement mixed style
Change-Id: Ie5f67288511d46fa196bc9f41e6af5504244adaa
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6438
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/server/telnet_server.c b/src/server/telnet_server.c
index 697efa1a7..253591ec9 100644
--- a/src/server/telnet_server.c
+++ b/src/server/telnet_server.c
@@ -602,16 +602,16 @@ static int telnet_input(struct connection *connection)
while (bytes_read) {
switch (t_con->state) {
case TELNET_STATE_DATA:
- if (*buf_p == 0xff)
+ if (*buf_p == 0xff) {
t_con->state = TELNET_STATE_IAC;
- else {
+ } else {
if (isprint(*buf_p)) { /* printable character */
telnet_insert(connection, buf_p, 1);
- } else { /* non-printable */
+ } else { /* non-printable */
if (*buf_p == 0x1b) { /* escape */
t_con->state = TELNET_STATE_ESCAPE;
t_con->last_escape = '\x00';
- } else if ((*buf_p == 0xd) || (*buf_p == 0xa)) { /* CR/LF */
+ } else if ((*buf_p == 0xd) || (*buf_p == 0xa)) { /* CR/LF */
int retval;
/* skip over combinations with CR/LF and NUL characters */
@@ -710,9 +710,9 @@ static int telnet_input(struct connection *connection)
telnet_write(connection, "\b \b", 3);
}
}
- } else if (*buf_p == 0x15) /* clear line */
+ } else if (*buf_p == 0x15) { /* clear line */
telnet_clear_line(connection, t_con);
- else if (*buf_p == CTRL('B')) { /* cursor left */
+ } else if (*buf_p == CTRL('B')) { /* cursor left */
if (t_con->line_cursor > 0) {
telnet_write(connection, "\b", 1);
t_con->line_cursor--;
@@ -722,15 +722,15 @@ static int telnet_input(struct connection *connection)
if (t_con->line_cursor < t_con->line_size)
telnet_write(connection, t_con->line + t_con->line_cursor++, 1);
t_con->state = TELNET_STATE_DATA;
- } else if (*buf_p == CTRL('P')) /* cursor up */
+ } else if (*buf_p == CTRL('P')) { /* cursor up */
telnet_history_up(connection);
- else if (*buf_p == CTRL('N')) /* cursor down */
+ } else if (*buf_p == CTRL('N')) { /* cursor down */
telnet_history_down(connection);
- else if (*buf_p == CTRL('A'))
+ } else if (*buf_p == CTRL('A')) { /* move the cursor to the beginning of the line */
telnet_move_cursor(connection, 0);
- else if (*buf_p == CTRL('E'))
+ } else if (*buf_p == CTRL('E')) { /* move the cursor to the end of the line */
telnet_move_cursor(connection, t_con->line_size);
- else if (*buf_p == CTRL('K')) { /* kill line to end */
+ } else if (*buf_p == CTRL('K')) { /* kill line to end */
if (t_con->line_cursor < t_con->line_size) {
/* overwrite with space, until end of line, move back */
for (size_t i = t_con->line_cursor; i < t_con->line_size; i++)
@@ -740,10 +740,11 @@ static int telnet_input(struct connection *connection)
t_con->line[t_con->line_cursor] = '\0';
t_con->line_size = t_con->line_cursor;
}
- } else if (*buf_p == '\t')
+ } else if (*buf_p == '\t') {
telnet_auto_complete(connection);
- else
+ } else {
LOG_DEBUG("unhandled nonprintable: %2.2x", *buf_p);
+ }
}
}
break;
@@ -796,10 +797,11 @@ static int telnet_input(struct connection *connection)
} else if (*buf_p == 'H') { /* home key */
telnet_move_cursor(connection, 0);
t_con->state = TELNET_STATE_DATA;
- } else if (*buf_p == '3')
+ } else if (*buf_p == '3') {
t_con->last_escape = *buf_p;
- else
+ } else {
t_con->state = TELNET_STATE_DATA;
+ }
} else if (t_con->last_escape == '3') {
/* Remove character */
if (*buf_p == '~') {
-----------------------------------------------------------------------
Summary of changes:
src/server/telnet_server.c | 32 +++++++++++++++++---------------
1 file changed, 17 insertions(+), 15 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-08-30 13:52:38
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 12e2dfd31ff07d9d13c7f66b799fad90a2698428 (commit)
from b3a51bbb590cca6d6536532d8c0965748410f277 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 12e2dfd31ff07d9d13c7f66b799fad90a2698428
Author: Antonio Borneo <bor...@gm...>
Date: Sat May 15 23:14:18 2021 +0200
Makefile: drop warning suppression on win build
Commit dcdf71c21b99 ("- fix signed/unsigned build errors under
win32. Thanks Zach Welch <zw...@su...>") in 2009 prevents
gcc warnings on sign/unsigned comparisons while building for Win
on folders 'helper' and 'server'.
In 2011, commit b69119668ed8 ("RTOS Thread awareness support wip")
uses the same method on the new folder 'rtos'.
In mean time, all the incorrect sign/unsigned comparisons has been
fixed and no warning is present with the default -Wextra flag that
implies -Wsign-compare.
The comment:
# FD_* macros are sloppy with their signs on MinGW32 platform
seems linked to some old implementation of MinGW32 include file
that doesn't apply on current versions.
Remove the obsolete hacks to suppress the warnings.
Change-Id: I76dba9e54a647d3b9fbf1b7e9ae1844e3d7adc9a
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6254
Tested-by: jenkins
Reviewed-by: Xiaofan Chen <xia...@gm...>
diff --git a/src/helper/Makefile.am b/src/helper/Makefile.am
index 0d886843c..c1aeebf00 100644
--- a/src/helper/Makefile.am
+++ b/src/helper/Makefile.am
@@ -30,12 +30,6 @@ noinst_LTLIBRARIES += %D%/libhelper.la
%D%/jep106.inc \
%D%/jim-nvp.h
-%C%_libhelper_la_CFLAGS = $(AM_CFLAGS)
-if IS_MINGW
-# FD_* macros are sloppy with their signs on MinGW32 platform
-%C%_libhelper_la_CFLAGS += -Wno-sign-compare
-endif
-
STARTUP_TCL_SRCS += %D%/startup.tcl
EXTRA_DIST += \
%D%/bin2char.sh \
diff --git a/src/rtos/Makefile.am b/src/rtos/Makefile.am
index 49cb830e5..f09ac21a2 100644
--- a/src/rtos/Makefile.am
+++ b/src/rtos/Makefile.am
@@ -31,10 +31,3 @@ noinst_LTLIBRARIES += %D%/librtos.la
%D%/rtos_riot_stackings.h \
%D%/rtos_ucos_iii_stackings.h \
%D%/nuttx_header.h
-
-%C%_librtos_la_CFLAGS = $(AM_CFLAGS)
-
-if IS_MINGW
-# FD_* macros are sloppy with their signs on MinGW32 platform
-%C%_librtos_la_CFLAGS += -Wno-sign-compare
-endif
diff --git a/src/server/Makefile.am b/src/server/Makefile.am
index 5f7469a84..fb5248bfd 100644
--- a/src/server/Makefile.am
+++ b/src/server/Makefile.am
@@ -14,10 +14,4 @@ noinst_LTLIBRARIES += %D%/libserver.la
%D%/ipdbg.c \
%D%/ipdbg.h
-%C%_libserver_la_CFLAGS = $(AM_CFLAGS)
-if IS_MINGW
-# FD_* macros are sloppy with their signs on MinGW32 platform
-%C%_libserver_la_CFLAGS += -Wno-sign-compare
-endif
-
STARTUP_TCL_SRCS += %D%/startup.tcl
-----------------------------------------------------------------------
Summary of changes:
src/helper/Makefile.am | 6 ------
src/rtos/Makefile.am | 7 -------
src/server/Makefile.am | 6 ------
3 files changed, 19 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2021-08-30 13:52:13
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b3a51bbb590cca6d6536532d8c0965748410f277 (commit)
from c281c64469de3c92b2fad0933722cb95b710b02a (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit b3a51bbb590cca6d6536532d8c0965748410f277
Author: Antonio Borneo <bor...@gm...>
Date: Sun May 16 00:48:49 2021 +0200
helper: remove fix for libusb pre-v1.0.9
Libusb v1.0.9 has been released on April 2012. We can reasonably
expect that every user has already updated his system to a libusb
newer of equel to v1.0.9.
Remove the fix for older libusb.
Change-Id: I0c40e53d7af85a11b0bb265bbf8035857a2dfce1
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6253
Tested-by: jenkins
Reviewed-by: Xiaofan Chen <xia...@gm...>
diff --git a/configure.ac b/configure.ac
index bd2e5c4f9..a178284ee 100644
--- a/configure.ac
+++ b/configure.ac
@@ -570,9 +570,6 @@ AS_IF([test "x$build_xlnx_pcie_xvc" = "xyes"], [
PKG_CHECK_MODULES([LIBUSB1], [libusb-1.0], [
use_libusb1=yes
AC_DEFINE([HAVE_LIBUSB1], [1], [Define if you have libusb-1.x])
- PKG_CHECK_EXISTS([libusb-1.0 >= 1.0.9],
- [AC_DEFINE([HAVE_LIBUSB_ERROR_NAME], [1], [Define if your libusb has libusb_error_name()])],
- [AC_MSG_WARN([libusb-1.x older than 1.0.9 detected, consider updating])])
LIBUSB1_CFLAGS=`echo $LIBUSB1_CFLAGS | sed 's/-I/-isystem /'`
AC_MSG_NOTICE([libusb-1.0 header bug workaround: LIBUSB1_CFLAGS changed to "$LIBUSB1_CFLAGS"])
PKG_CHECK_EXISTS([libusb-1.0 >= 1.0.16],
diff --git a/src/helper/Makefile.am b/src/helper/Makefile.am
index 42cee80d3..0d886843c 100644
--- a/src/helper/Makefile.am
+++ b/src/helper/Makefile.am
@@ -1,7 +1,5 @@
noinst_LTLIBRARIES += %D%/libhelper.la
-%C%_libhelper_la_CPPFLAGS = $(AM_CPPFLAGS) $(LIBUSB1_CFLAGS)
-
%C%_libhelper_la_SOURCES = \
%D%/binarybuffer.c \
%D%/options.c \
diff --git a/src/helper/replacements.c b/src/helper/replacements.c
index 81b1976d0..c34b17ec5 100644
--- a/src/helper/replacements.c
+++ b/src/helper/replacements.c
@@ -275,45 +275,3 @@ int win_select(int max_fd, fd_set *rfds, fd_set *wfds, fd_set *efds, struct time
return retcode;
}
#endif
-
-#if defined HAVE_LIBUSB1 && !defined HAVE_LIBUSB_ERROR_NAME
-#include <libusb.h>
-/* Verbatim from git://git.libusb.org/libusb.git tag 1.0.9
- * The libusb_error enum is compatible down to v0.9.1
- */
-const char *libusb_error_name(int error_code)
-{
- enum libusb_error error = error_code;
- switch (error) {
- case LIBUSB_SUCCESS:
- return "LIBUSB_SUCCESS";
- case LIBUSB_ERROR_IO:
- return "LIBUSB_ERROR_IO";
- case LIBUSB_ERROR_INVALID_PARAM:
- return "LIBUSB_ERROR_INVALID_PARAM";
- case LIBUSB_ERROR_ACCESS:
- return "LIBUSB_ERROR_ACCESS";
- case LIBUSB_ERROR_NO_DEVICE:
- return "LIBUSB_ERROR_NO_DEVICE";
- case LIBUSB_ERROR_NOT_FOUND:
- return "LIBUSB_ERROR_NOT_FOUND";
- case LIBUSB_ERROR_BUSY:
- return "LIBUSB_ERROR_BUSY";
- case LIBUSB_ERROR_TIMEOUT:
- return "LIBUSB_ERROR_TIMEOUT";
- case LIBUSB_ERROR_OVERFLOW:
- return "LIBUSB_ERROR_OVERFLOW";
- case LIBUSB_ERROR_PIPE:
- return "LIBUSB_ERROR_PIPE";
- case LIBUSB_ERROR_INTERRUPTED:
- return "LIBUSB_ERROR_INTERRUPTED";
- case LIBUSB_ERROR_NO_MEM:
- return "LIBUSB_ERROR_NO_MEM";
- case LIBUSB_ERROR_NOT_SUPPORTED:
- return "LIBUSB_ERROR_NOT_SUPPORTED";
- case LIBUSB_ERROR_OTHER:
- return "LIBUSB_ERROR_OTHER";
- }
- return "**UNKNOWN**";
-}
-#endif
diff --git a/src/helper/replacements.h b/src/helper/replacements.h
index 5aecf4182..4d70d9cf3 100644
--- a/src/helper/replacements.h
+++ b/src/helper/replacements.h
@@ -328,8 +328,4 @@ typedef struct {
#endif /* HAVE_ELF64 */
-#if defined HAVE_LIBUSB1 && !defined HAVE_LIBUSB_ERROR_NAME
-const char *libusb_error_name(int error_code);
-#endif /* defined HAVE_LIBUSB1 && !defined HAVE_LIBUSB_ERROR_NAME */
-
#endif /* OPENOCD_HELPER_REPLACEMENTS_H */
-----------------------------------------------------------------------
Summary of changes:
configure.ac | 3 ---
src/helper/Makefile.am | 2 --
src/helper/replacements.c | 42 ------------------------------------------
src/helper/replacements.h | 4 ----
4 files changed, 51 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-08-30 07:52:53
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via c281c64469de3c92b2fad0933722cb95b710b02a (commit)
from c2ad18d68b79b0466782b945a2ef4bb723071282 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit c281c64469de3c92b2fad0933722cb95b710b02a
Author: Tarek BOCHKATI <tar...@gm...>
Date: Sun Aug 29 16:02:58 2021 +0100
flash/stm32l4x: free write_algorithm work area if no space left for the buffer
If the remaining memory for the buffer is less than 256 bytes,
the memory allocated for the write algorithm in the target is not freed.
Fixes: ba131f30a079 (Flash driver for STM32G0xx and STM32G4xx)
Change-Id: Ic649f6c39799d76725b0c69ff3a009a3f510e17f
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6486
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index b8635fe75..3c055616f 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -1353,6 +1353,7 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
buffer_size = target_get_working_area_avail(target) & ~(2 * sizeof(uint32_t) - 1);
if (buffer_size < 256) {
LOG_WARNING("large enough working area not available, can't do block memory writes");
+ target_free_working_area(target, write_algorithm);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
} else if (buffer_size > 16384) {
/* probably won't benefit from more than 16k ... */
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32l4x.c | 1 +
1 file changed, 1 insertion(+)
hooks/post-receive
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From: OpenOCD-Gerrit <ope...@us...> - 2021-08-30 07:52:22
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via c2ad18d68b79b0466782b945a2ef4bb723071282 (commit)
from 6c1e1a212a8c044ae778c526851fe909bf219e90 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit c2ad18d68b79b0466782b945a2ef4bb723071282
Author: Tarek BOCHKATI <tar...@gm...>
Date: Tue Mar 16 16:10:59 2021 +0100
flash/stm32l4x: add support of STM32U57x/U58x
this device flash registers are quite similar to STM32L5
with this changes :
- flash size is up to 2MB
- 2MB variants are always dual bank
- 1MB and 512KB variants could be dual bank (contiguous addressing)
depending on DUALBANK bit(21)
- flash data width is 16 bytes (quad-word)
Change-Id: Id13c552270ce1071479ad418526e8a39ebe83cb1
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6108
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 4404807a6..2759a39d3 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -7302,7 +7302,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@deffn {Flash Driver} {stm32l4x}
-All members of the STM32 G0, G4, L4, L4+, L5, WB and WL
+All members of the STM32 G0, G4, L4, L4+, L5, U5, WB and WL
microcontroller families from STMicroelectronics include internal flash
and use ARM Cortex-M0+, M4 and M33 cores.
The driver automatically recognizes a number of these chips using
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index 8d463ac05..b8635fe75 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -133,6 +133,9 @@
#define F_HAS_TZ BIT(2)
/* this flag indicates if the device has the same flash registers as STM32L5 */
#define F_HAS_L5_FLASH_REGS BIT(3)
+/* this flag indicates that programming should be done in quad-word
+ * the default programming word size is double-word */
+#define F_QUAD_WORD_PROG BIT(4)
/* end of STM32L4 flags ******************************************************/
@@ -236,6 +239,7 @@ struct stm32l4_flash_bank {
bool dual_bank_mode;
int hole_sectors;
uint32_t user_bank_size;
+ uint32_t data_width;
uint32_t cr_bker_mask;
uint32_t sr_bsy_mask;
uint32_t wrpxxr_mask;
@@ -265,7 +269,7 @@ struct stm32l4_wrp {
};
/* human readable list of families this drivers supports (sorted alphabetically) */
-static const char *device_families = "STM32G0/G4/L4/L4+/L5/WB/WL";
+static const char *device_families = "STM32G0/G4/L4/L4+/L5/U5/WB/WL";
static const struct stm32l4_rev stm32_415_revs[] = {
{ 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
@@ -323,6 +327,10 @@ static const struct stm32l4_rev stm32_479_revs[] = {
{ 0x1000, "A" },
};
+static const struct stm32l4_rev stm32_482_revs[] = {
+ { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2000, "B" },
+};
+
static const struct stm32l4_rev stm32_495_revs[] = {
{ 0x2001, "2.1" },
};
@@ -504,6 +512,18 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.otp_base = 0x1FFF7000,
.otp_size = 1024,
},
+ {
+ .id = 0x482,
+ .revs = stm32_482_revs,
+ .num_revs = ARRAY_SIZE(stm32_482_revs),
+ .device_str = "STM32U57/U58xx",
+ .max_flash_size_kb = 2048,
+ .flags = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x0BFA07A0,
+ .otp_base = 0x0BFA0000,
+ .otp_size = 512,
+ },
{
.id = 0x495,
.revs = stm32_495_revs,
@@ -559,10 +579,6 @@ FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
return ERROR_FAIL; /* Checkme: What better error to use?*/
bank->driver_priv = stm32l4_info;
- /* The flash write must be aligned to a double word (8-bytes) boundary.
- * Ask the flash infrastructure to ensure required alignment */
- bank->write_start_alignment = bank->write_end_alignment = 8;
-
stm32l4_info->probed = false;
stm32l4_info->otp_enabled = false;
stm32l4_info->user_bank_size = bank->size;
@@ -1297,11 +1313,12 @@ static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first,
return stm32l4_write_all_wrpxy(bank, wrpxy, n_wrp);
}
-/* Count is in double-words */
+/* count is the size divided by stm32l4_info->data_width */
static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
uint32_t buffer_size;
struct working_area *write_algorithm;
struct working_area *source;
@@ -1328,7 +1345,11 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
return retval;
}
- /* memory buffer, size *must* be multiple of dword plus one dword for rp and one for wp */
+ /* memory buffer, size *must* be multiple of stm32l4_info->data_width
+ * plus one dword for rp and one for wp */
+ /* FIXME, currently only STM32U5 devices do have a different data_width,
+ * but STM32U5 device flash programming does not go through this function
+ * so temporarily continue to consider the default data_width = 8 */
buffer_size = target_get_working_area_avail(target) & ~(2 * sizeof(uint32_t) - 1);
if (buffer_size < 256) {
LOG_WARNING("large enough working area not available, can't do block memory writes");
@@ -1360,7 +1381,7 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
buf_set_u32(reg_params[4].value, 0, 32, stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX));
buf_set_u32(reg_params[5].value, 0, 32, stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX));
- retval = target_run_flash_async_algorithm(target, buffer, count, 8,
+ retval = target_run_flash_async_algorithm(target, buffer, count, stm32l4_info->data_width,
0, NULL,
ARRAY_SIZE(reg_params), reg_params,
source->address, source->size,
@@ -1396,10 +1417,11 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
return retval;
}
-/* Count is in double-words */
+/* count is the size divided by stm32l4_info->data_width */
static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
struct target *target = bank->target;
uint32_t address = bank->base + offset;
int retval = ERROR_OK;
@@ -1417,8 +1439,9 @@ static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uin
/* write directly to flash memory */
const uint8_t *src = buffer;
+ const uint32_t data_width_in_words = stm32l4_info->data_width / 4;
while (count--) {
- retval = target_write_memory(target, address, 4, 2, src);
+ retval = target_write_memory(target, address, 4, data_width_in_words, src);
if (retval != ERROR_OK)
return retval;
@@ -1427,8 +1450,8 @@ static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uin
if (retval != ERROR_OK)
return retval;
- src += 8;
- address += 8;
+ src += stm32l4_info->data_width;
+ address += stm32l4_info->data_width;
}
/* reset PG in FLASH_CR */
@@ -1455,10 +1478,13 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
return ERROR_TARGET_NOT_HALTED;
}
- /* The flash write must be aligned to a double word (8-bytes) boundary.
+ /* ensure that stm32l4_info->data_width is 'at least' a multiple of dword */
+ assert(stm32l4_info->data_width % 8 == 0);
+
+ /* The flash write must be aligned to the 'stm32l4_info->data_width' boundary.
* The flash infrastructure ensures it, do just a security check */
- assert(offset % 8 == 0);
- assert(count % 8 == 0);
+ assert(offset % stm32l4_info->data_width == 0);
+ assert(count % stm32l4_info->data_width == 0);
/* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
* data to be written does not go into a gap:
@@ -1520,6 +1546,12 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
if ((stm32l4_info->part_info->id == 0x467) && stm32l4_info->dual_bank_mode) {
LOG_INFO("Couldn't use the flash loader in dual-bank mode");
use_flashloader = false;
+ } else if (stm32l4_info->part_info->id == 0x482) {
+ /**
+ * FIXME the current flashloader does not support writing in quad-words
+ * which is required for STM32U5 devices.
+ */
+ use_flashloader = false;
}
if (use_flashloader) {
@@ -1530,15 +1562,16 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5))
LOG_INFO("RDP level is 0.5, the work-area should reside in non-secure RAM");
- retval = stm32l4_write_block(bank, buffer, offset, count / 8);
+ retval = stm32l4_write_block(bank, buffer, offset,
+ count / stm32l4_info->data_width);
}
if (!use_flashloader || retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
LOG_INFO("falling back to single memory accesses");
- retval = stm32l4_write_block_without_loader(bank, buffer, offset, count / 8);
+ retval = stm32l4_write_block_without_loader(bank, buffer, offset,
+ count / stm32l4_info->data_width);
}
-
err_lock:
retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
@@ -1657,9 +1690,14 @@ static int stm32l4_probe(struct flash_bank *bank)
stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
stm32l4_info->flash_regs_base = stm32l4_info->part_info->flash_regs_base;
+ stm32l4_info->data_width = (part_info->flags & F_QUAD_WORD_PROG) ? 16 : 8;
stm32l4_info->cr_bker_mask = FLASH_BKER;
stm32l4_info->sr_bsy_mask = FLASH_BSY;
+ /* Set flash write alignment boundaries.
+ * Ask the flash infrastructure to ensure required alignment */
+ bank->write_start_alignment = bank->write_end_alignment = stm32l4_info->data_width;
+
/* initialise the flash registers layout */
if (part_info->flags & F_HAS_L5_FLASH_REGS)
stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
@@ -1852,6 +1890,18 @@ static int stm32l4_probe(struct flash_bank *bank)
stm32l4_info->bank1_sectors = num_pages / 2;
}
break;
+ case 0x482: /* STM32U57/U58xx */
+ /* if flash size is max (2M) the device is always dual bank
+ * otherwise check DUALBANK bit(21)
+ */
+ page_size_kb = 8;
+ num_pages = flash_size_kb / page_size_kb;
+ stm32l4_info->bank1_sectors = num_pages;
+ if ((flash_size_kb == part_info->max_flash_size_kb) || (stm32l4_info->optr & BIT(21))) {
+ stm32l4_info->dual_bank_mode = true;
+ stm32l4_info->bank1_sectors = num_pages / 2;
+ }
+ break;
case 0x495: /* STM32WB5x */
case 0x496: /* STM32WB3x */
/* single bank flash */
diff --git a/src/flash/startup.tcl b/src/flash/startup.tcl
index 0a26da08b..93ef82ce6 100644
--- a/src/flash/startup.tcl
+++ b/src/flash/startup.tcl
@@ -114,9 +114,10 @@ proc stm32f7x args { eval stm32f2x $args }
proc stm32l0x args { eval stm32lx $args }
proc stm32l1x args { eval stm32lx $args }
-# stm32[g0|g4|wb|wl] uses the same flash driver as the stm32l4x
+# stm32[g0|g4|l5|u5|wb|wl] uses the same flash driver as the stm32l4x
proc stm32g0x args { eval stm32l4x $args }
proc stm32g4x args { eval stm32l4x $args }
proc stm32l5x args { eval stm32l4x $args }
+proc stm32u5x args { eval stm32l4x $args }
proc stm32wbx args { eval stm32l4x $args }
proc stm32wlx args { eval stm32l4x $args }
diff --git a/tcl/target/stm32u5x.cfg b/tcl/target/stm32u5x.cfg
new file mode 100644
index 000000000..2c2c0e037
--- /dev/null
+++ b/tcl/target/stm32u5x.cfg
@@ -0,0 +1,207 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32u5x family
+
+#
+# stm32u5 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32u5x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ if { [using_jtag] } {
+ # See STM Document RM0438
+ # RM0456 Rev1, Section 65.2.8 JTAG debug port - Table 661. JTAG-DP data registers
+ # Corresponds to Cortex®-M33 JTAG debug port ID code
+ set _CPUTAPID 0x0ba04477
+ } {
+ # SWD IDCODE (single drop, arm)
+ set _CPUTAPID 0x0be12477
+ }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+ jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+# use non-secure RAM by default
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# create sec/ns flash and otp memories (sizes will be probed)
+flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+ # if srst is not fitted use SYSRESETREQ to
+ # perform a soft reset
+ cortex_m reset_config sysresetreq
+}
+
+proc is_secure {} {
+ # read Debug Security Control and Status Regsiter (DSCSR) and check CDS (bit 16)
+ set DSCSR [mrw 0xE000EE08]
+ return [expr {($DSCSR & (1 << 16)) != 0}]
+}
+
+proc clock_config_160_mhz {} {
+ set offset [expr {[is_secure] ? 0x10000000 : 0}]
+ # MCU clock is at MSI 4MHz after reset, set MCU freq at 160 MHz with PLL
+
+ # Enable voltage range 1 for frequency above 100 Mhz
+ # RCC_AHB3ENR = PWREN
+ mww [expr {0x46020C94 + $offset}] 0x00000004
+ # delay for register clock enable (read back reg)
+ mrw [expr {0x56020C94 + $offset}]
+ # PWR_VOSR : VOS Range 1
+ mww [expr {0x4602080C + $offset}] 0x00030000
+ # delay for register write (read back reg)
+ mrw [expr {0x4602080C + $offset}]
+ # FLASH_ACR : 4 WS for 160 MHz HCLK
+ mww [expr {0x40022000 + $offset}] 0x00000004
+ # RCC_PLL1CFGR => PLL1M=0000=/1, PLL1SRC=MSI 4MHz
+ mww [expr {0x46020C28 + $offset}] 0x00000001
+ # RCC_PLL1DIVR => PLL1P=PLL1Q=PLL1R=000001=/2, PLL1N=0x4F=80
+ # fVCO = 4 x 80 /1 = 320
+ # SYSCLOCK = fVCO/PLL1R = 320/2 = 160 MHz
+ mmw [expr {0x46020C34 + $offset}] 0x0000004F 0
+ # RCC_PLL1CFGR => PLL1REN=1
+ mmw [expr {0x46020C28 + $offset}] 0x00040000 0
+ # RCC_CR |= PLL1ON
+ mmw [expr {0x46020C00 + $offset}] 0x01000000 0
+ # while !(RCC_CR & PLL1RDY)
+ while {!([mrw [expr {0x46020C00 + $offset}]] & 0x02000000)} {}
+ # RCC_CFGR1 |= SW_PLL
+ mmw [expr {0x46020C1C + $offset}] 0x00000003 0
+ # while ((RCC_CFGR1 & SWS) != PLL)
+ while {([mrw [expr {0x46020C1C + $offset}]] & 0x0C) != 0x0C} {}
+}
+
+proc ahb_ap_non_secure_access {} {
+ # SPROT=1=Non Secure access, Priv=1
+ [[target current] cget -dap] apcsw 0x4B000000 0x4F000000
+}
+
+proc ahb_ap_secure_access {} {
+ # SPROT=0=Secure access, Priv=1
+ [[target current] cget -dap] apcsw 0x0B000000 0x4F000000
+}
+
+$_TARGETNAME configure -event reset-init {
+ clock_config_160_mhz
+ # Boost JTAG frequency
+ adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+ # Reset clock is MSI (4 MHz)
+ adapter speed 480
+}
+
+$_TARGETNAME configure -event examine-end {
+ # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+ mmw 0xE0044004 0x00000006 0
+
+ # Stop watchdog counters during halt
+ # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+ mmw 0xE0044008 0x00001800 0
+}
+
+$_TARGETNAME configure -event halted {
+ set secure [is_secure]
+
+ if {$secure} {
+ set secure_str "Secure"
+ ahb_ap_secure_access
+ } else {
+ set secure_str "Non-Secure"
+ ahb_ap_non_secure_access
+ }
+
+ # print the secure state only when it changes
+ set _TARGETNAME [target current]
+ global $_TARGETNAME.secure
+
+ if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
+ echo "CPU in $secure_str state"
+ # update saved security state
+ set $_TARGETNAME.secure $secure
+ }
+}
+
+$_TARGETNAME configure -event gdb-flash-erase-start {
+ set use_secure_workarea 0
+ # check if FLASH_OPTR.TZEN is enabled
+ set FLASH_OPTR [mrw 0x40022040]
+ if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
+ echo "TZEN option bit disabled"
+ ahb_ap_non_secure_access
+ } else {
+ ahb_ap_secure_access
+ echo "TZEN option bit enabled"
+
+ # check if FLASH_OPTR.RDP is not Level 0.5
+ if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
+ set use_secure_workarea 1
+ }
+ }
+
+ set _TARGETNAME [target current]
+ set workarea_addr [$_TARGETNAME cget -work-area-phys]
+ echo "workarea_addr $workarea_addr"
+
+ if {$use_secure_workarea} {
+ set workarea_addr [expr {$workarea_addr | 0x10000000}]
+ } else {
+ set workarea_addr [expr {$workarea_addr & ~0x10000000}]
+ }
+
+ $_TARGETNAME configure -work-area-phys $workarea_addr
+}
+
+$_TARGETNAME configure -event trace-config {
+ # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+ # change this value accordingly to configure trace pins
+ # assignment
+ mmw 0xE0044004 0x00000020 0
+}
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 2 +-
src/flash/nor/stm32l4x.c | 86 ++++++++++++++++++++++++-------
src/flash/startup.tcl | 3 +-
tcl/target/{stm32l5x.cfg => stm32u5x.cfg} | 67 +++++++++++++-----------
4 files changed, 108 insertions(+), 50 deletions(-)
copy tcl/target/{stm32l5x.cfg => stm32u5x.cfg} (75%)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-08-26 13:13:30
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 6c1e1a212a8c044ae778c526851fe909bf219e90 (commit)
from 64fbd607874bbe9726cf1d09c2cbf547bd9d804c (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 6c1e1a212a8c044ae778c526851fe909bf219e90
Author: Tarek BOCHKATI <tar...@gm...>
Date: Thu Feb 4 22:43:52 2021 +0100
flash/stm32l4x: add support of STM32WL5x dual core
according the RM0453, the second core have a different Flash CR and SR
registers for flash operations (called C2CR and C2SR).
so we need to a different flash_regs than older L4 devices.
@see stm32wl_cpu2_flash_regs
the C2CR register don't contain LOCK and OPTLOCK bits, and this explain
the addition of new register index called STM32_FLASH_CR_WLK_INDEX to
look-up the CR with lock, to be used in locking/unlocking the flash.
note: DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
to solve this read the UID64 (IEEE 64-bit unique device ID register)
Change-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6050
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index ff804bbaf..8d463ac05 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -27,7 +27,7 @@
#include <helper/align.h>
#include <helper/binarybuffer.h>
#include <target/algorithm.h>
-#include <target/armv7m.h>
+#include <target/cortex_m.h>
#include "bits.h"
#include "stm32l4x.h"
@@ -80,6 +80,9 @@
*
* RM0461 (STM32WLEx)
* http://www.st.com/resource/en/reference_manual/dm00530369.pdf
+ *
+ * RM0453 (STM32WL5x)
+ * http://www.st.com/resource/en/reference_manual/dm00451556.pdf
*/
/* STM32G0xxx series for reference.
@@ -139,6 +142,9 @@ enum stm32l4_flash_reg_index {
STM32_FLASH_OPTKEYR_INDEX,
STM32_FLASH_SR_INDEX,
STM32_FLASH_CR_INDEX,
+ /* for some devices like STM32WL5x, the CPU2 have a dedicated C2CR register w/o LOCKs,
+ * so it uses the C2CR for flash operations and CR for checking locks and locking */
+ STM32_FLASH_CR_WLK_INDEX, /* FLASH_CR_WITH_LOCK */
STM32_FLASH_OPTR_INDEX,
STM32_FLASH_WRP1AR_INDEX,
STM32_FLASH_WRP1BR_INDEX,
@@ -167,6 +173,18 @@ static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
[STM32_FLASH_WRP2BR_INDEX] = 0x050,
};
+static const uint32_t stm32wl_cpu2_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
+ [STM32_FLASH_ACR_INDEX] = 0x000,
+ [STM32_FLASH_KEYR_INDEX] = 0x008,
+ [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
+ [STM32_FLASH_SR_INDEX] = 0x060,
+ [STM32_FLASH_CR_INDEX] = 0x064,
+ [STM32_FLASH_CR_WLK_INDEX] = 0x014,
+ [STM32_FLASH_OPTR_INDEX] = 0x020,
+ [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
+ [STM32_FLASH_WRP1BR_INDEX] = 0x030,
+};
+
static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
[STM32_FLASH_ACR_INDEX] = 0x000,
[STM32_FLASH_KEYR_INDEX] = 0x008, /* NSKEYR */
@@ -514,7 +532,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.id = 0x497,
.revs = stm32_497_revs,
.num_revs = ARRAY_SIZE(stm32_497_revs),
- .device_str = "STM32WLEx",
+ .device_str = "STM32WLEx/WL5x",
.max_flash_size_kb = 256,
.flags = F_NONE,
.flash_regs_base = 0x58004000,
@@ -789,14 +807,22 @@ static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
return ERROR_OK;
}
+static inline int stm32l4_get_flash_cr_with_lock_index(struct flash_bank *bank)
+{
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ return (stm32l4_info->flash_regs[STM32_FLASH_CR_WLK_INDEX]) ?
+ STM32_FLASH_CR_WLK_INDEX : STM32_FLASH_CR_INDEX;
+}
+
static int stm32l4_unlock_reg(struct flash_bank *bank)
{
+ const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
uint32_t ctrl;
/* first check if not already unlocked
* otherwise writing on STM32_FLASH_KEYR will fail
*/
- int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
+ int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
if (retval != ERROR_OK)
return retval;
@@ -812,7 +838,7 @@ static int stm32l4_unlock_reg(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
- retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
+ retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
if (retval != ERROR_OK)
return retval;
@@ -826,9 +852,10 @@ static int stm32l4_unlock_reg(struct flash_bank *bank)
static int stm32l4_unlock_option_reg(struct flash_bank *bank)
{
+ const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
uint32_t ctrl;
- int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
+ int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
if (retval != ERROR_OK)
return retval;
@@ -844,7 +871,7 @@ static int stm32l4_unlock_option_reg(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
- retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
+ retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
if (retval != ERROR_OK)
return retval;
@@ -884,7 +911,8 @@ static int stm32l4_perform_obl_launch(struct flash_bank *bank)
stm32l4_info->probed = false;
err_lock:
- retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK | FLASH_OPTLOCK);
+ retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank),
+ FLASH_LOCK | FLASH_OPTLOCK);
if (retval != ERROR_OK)
return retval;
@@ -930,7 +958,8 @@ static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
err_lock:
- retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK | FLASH_OPTLOCK);
+ retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank),
+ FLASH_LOCK | FLASH_OPTLOCK);
stm32l4_info->flash_regs = saved_flash_regs;
if (retval != ERROR_OK)
@@ -1124,7 +1153,7 @@ static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
}
err_lock:
- retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
+ retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
/* restore all FLASH pages as non-secure */
@@ -1511,7 +1540,7 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
err_lock:
- retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
+ retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
/* restore all FLASH pages as non-secure */
@@ -1540,6 +1569,30 @@ static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
return ERROR_OK;
}
+ /* Workaround for STM32WL5x devices:
+ * DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
+ * to solve this read the UID64 (IEEE 64-bit unique device ID register) */
+
+ struct cortex_m_common *cortex_m = target_to_cm(bank->target);
+
+ if (cortex_m->core_info->partno == CORTEX_M0P_PARTNO && cortex_m->armv7m.debug_ap->ap_num == 1) {
+ uint32_t uid64_ids;
+
+ /* UID64 is contains
+ * - Bits 63:32 : DEVNUM (unique device number, different for each individual device)
+ * - Bits 31:08 : STID (company ID) = 0x0080E1
+ * - Bits 07:00 : DEVID (device ID) = 0x15
+ *
+ * read only the fixed values {STID,DEVID} from UID64_IDS to identify the device as STM32WLx
+ */
+ retval = target_read_u32(bank->target, UID64_IDS, &uid64_ids);
+ if (retval == ERROR_OK && uid64_ids == UID64_IDS_STM32WL) {
+ /* force the DEV_ID to 0x497 and the REV_ID to unknown */
+ *id = 0x00000497;
+ return ERROR_OK;
+ }
+ }
+
LOG_ERROR("can't get the device id");
return (retval == ERROR_OK) ? ERROR_FAIL : retval;
}
@@ -1570,6 +1623,7 @@ static const char *get_stm32l4_bank_type_str(struct flash_bank *bank)
static int stm32l4_probe(struct flash_bank *bank)
{
struct target *target = bank->target;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
const struct stm32l4_part_info *part_info;
uint16_t flash_size_kb = 0xffff;
@@ -1722,7 +1776,6 @@ static int stm32l4_probe(struct flash_bank *bank)
case 0x466: /* STM32G03/G04xx */
case 0x468: /* STM32G43/G44xx */
case 0x479: /* STM32G49/G4Axx */
- case 0x497: /* STM32WLEx */
/* single bank flash */
page_size_kb = 2;
num_pages = flash_size_kb / page_size_kb;
@@ -1806,6 +1859,14 @@ static int stm32l4_probe(struct flash_bank *bank)
num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages;
break;
+ case 0x497: /* STM32WLEx/WL5x */
+ /* single bank flash */
+ page_size_kb = 2;
+ num_pages = flash_size_kb / page_size_kb;
+ stm32l4_info->bank1_sectors = num_pages;
+ if (armv7m->debug_ap->ap_num == 1)
+ stm32l4_info->flash_regs = stm32wl_cpu2_flash_regs;
+ break;
default:
LOG_ERROR("unsupported device");
return ERROR_FAIL;
@@ -1953,7 +2014,7 @@ static int stm32l4_mass_erase(struct flash_bank *bank)
retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
err_lock:
- retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
+ retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
/* restore all FLASH pages as non-secure */
diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h
index 098604875..7b9162b08 100644
--- a/src/flash/nor/stm32l4x.h
+++ b/src/flash/nor/stm32l4x.h
@@ -83,6 +83,9 @@
#define DBGMCU_IDCODE_G0 0x40015800
#define DBGMCU_IDCODE_L4_G4 0xE0042000
#define DBGMCU_IDCODE_L5 0xE0044000
+#define UID64_DEVNUM 0x1FFF7580
+#define UID64_IDS 0x1FFF7584
+#define UID64_IDS_STM32WL 0x0080E115
#define STM32_FLASH_BANK_BASE 0x08000000
#define STM32_FLASH_S_BANK_BASE 0x0C000000
diff --git a/tcl/target/stm32wlx.cfg b/tcl/target/stm32wlx.cfg
index 961850ad1..edb3fb32b 100644
--- a/tcl/target/stm32wlx.cfg
+++ b/tcl/target/stm32wlx.cfg
@@ -12,16 +12,47 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME stm32wlx
}
-set _ENDIAN little
+if { [info exists DUAL_CORE] } {
+ set $_CHIPNAME.DUAL_CORE $DUAL_CORE
+ unset DUAL_CORE
+} else {
+ set $_CHIPNAME.DUAL_CORE 0
+}
+
+if { [info exists WKUP_CM0P] } {
+ set $_CHIPNAME.WKUP_CM0P $WKUP_CM0P
+ unset WKUP_CM0P
+} else {
+ set $_CHIPNAME.WKUP_CM0P 0
+}
+
+# Issue a warning when hla is used, and fallback to single core configuration
+if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
+ echo "Warning : hla does not support multicore debugging"
+ set $_CHIPNAME.DUAL_CORE 0
+ set $_CHIPNAME.WKUP_CM0P 0
+}
+# setup the Work-area start address and size
# Work-area is a space in RAM used for flash programming
-# By default use 20kB
+
+# Memory map for known devices:
+# STM32WL x5JC x5JB x5J8
+# FLASH 256 128 64
+# SRAM1 32 16 0
+# SRAM2 32 32 20
+
+# By default use 8kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
- set _WORKAREASIZE 0x5000
+ set _WORKAREASIZE 0x2000
}
+# Use SRAM2 as work area (some devices do not have SRAM1):
+set WORKAREASTART_CM4 0x20008000
+set WORKAREASTART_CM0P [expr {$WORKAREASTART_CM4 + $_WORKAREASIZE}]
+
#jtag scan chain
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
@@ -41,36 +72,20 @@ if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5
}
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
-flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
-
-# Common knowledges tells JTAG speed should be <= F_CPU/6.
-# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
-# the safe side.
-#
-# Note that there is a pretty wide band where things are
-# more or less stable, see http://openocd.zylin.com/#/c/3366/
-adapter speed 500
+target create $_CHIPNAME.cpu0 cortex_m -endian little -dap $_CHIPNAME.dap
-adapter srst delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
+$_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM4 -work-area-size $_WORKAREASIZE -work-area-backup 0
-reset_config srst_nogate
+flash bank $_CHIPNAME.flash.cpu0 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu0
+flash bank $_CHIPNAME.otp.cpu0 stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu0
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
- cortex_m reset_config sysresetreq
+ $_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
}
-$_TARGETNAME configure -event reset-init {
+$_CHIPNAME.cpu0 configure -event reset-init {
# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
# 2 WS compliant with VOS=Range1 and 24 MHz.
@@ -80,12 +95,12 @@ $_TARGETNAME configure -event reset-init {
adapter speed 4000
}
-$_TARGETNAME configure -event reset-start {
+$_CHIPNAME.cpu0 configure -event reset-start {
# Reset clock is MSI (4 MHz)
adapter speed 500
}
-$_TARGETNAME configure -event examine-end {
+$_CHIPNAME.cpu0 configure -event examine-end {
# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0
@@ -93,8 +108,80 @@ $_TARGETNAME configure -event examine-end {
# Stop watchdog counters during halt
# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE004203C 0x00001800 0
+
+ set _CHIPNAME [stm32wlx_get_chipname]
+ global $_CHIPNAME.WKUP_CM0P
+
+ if {[set $_CHIPNAME.WKUP_CM0P]} {
+ stm32wlx_wkup_cm0p
+ }
}
-$_TARGETNAME configure -event trace-config {
+$_CHIPNAME.cpu0 configure -event trace-config {
# nothing to do
}
+
+if {[set $_CHIPNAME.DUAL_CORE]} {
+ target create $_CHIPNAME.cpu1 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
+
+ $_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM0P -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+ flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1
+ flash bank $_CHIPNAME.otp.cpu1 stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu1
+
+ if {![using_hla]} {
+ # if srst is not fitted use SYSRESETREQ to
+ # perform a soft reset
+ $_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
+ }
+
+ proc stm32wlx_wkup_cm0p {} {
+ set _CHIPNAME [stm32wlx_get_chipname]
+
+ # enable CPU2 boot after reset and after wakeup from Stop or Standby mode
+ # PWR_CR4 |= C2BOOT
+ stm32wlx_mmw $_CHIPNAME.cpu0 0x5800040C 0x00008000 0
+ }
+}
+
+# get _CHIPNAME from current target
+proc stm32wlx_get_chipname {} {
+ set t [target current]
+ set sep [string last "." $t]
+ if {$sep == -1} {
+ return $t
+ }
+ return [string range $t 0 [expr $sep - 1]]
+}
+
+# like mrw, but with target selection
+proc stm32wlx_mrw {used_target reg} {
+ set value ""
+ $used_target mem2array value 32 $reg 1
+ return $value(0)
+}
+
+# like mmw, but with target selection
+proc stm32wlx_mmw {used_target reg setbits clearbits} {
+ set old [stm32wlx_mrw $used_target $reg]
+ set new [expr {($old & ~$clearbits) | $setbits}]
+ $used_target mww $reg $new
+}
+
+# Make sure that cpu0 is selected
+targets $_CHIPNAME.cpu0
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32l4x.c | 85 ++++++++++++++++++++++++----
src/flash/nor/stm32l4x.h | 3 +
tcl/target/stm32wlx.cfg | 143 +++++++++++++++++++++++++++++++++++++----------
3 files changed, 191 insertions(+), 40 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-08-26 06:39:22
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 64fbd607874bbe9726cf1d09c2cbf547bd9d804c (commit)
from 43d31a8fd507a7d15083b487cf06d3f934e25843 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 64fbd607874bbe9726cf1d09c2cbf547bd9d804c
Author: Sebastiaan de Schaetzen <seb...@gm...>
Date: Sun Aug 15 23:26:23 2021 +0100
flash/stm32l4x: prevent undefined behavior warnings caused by signed integer operations
When running OpenOCD with -fsanitize=undefined, a warning is emitted
for an bit-shifting operation whose result cannot be stored in a
signed integer.
This is because (1 << 31) overflows a signed integer, which is
undefined behavior. By making each of the bit masks act on an
unsigned number, the warning is avoided.
Whether this warning emitted by UBSan would ever manifest into a real
error is debatable, but fixing this does make UBSan happy.
Change-Id: I0455a26b234cb4f5e239a6ba90023d28380e9464
Signed-off-by: Sebastiaan de Schaetzen <seb...@gm...>
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6429
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Oleksij Rempel <li...@re...>
Tested-by: jenkins
diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h
index ba809ff40..098604875 100644
--- a/src/flash/nor/stm32l4x.h
+++ b/src/flash/nor/stm32l4x.h
@@ -19,34 +19,44 @@
#ifndef OPENOCD_FLASH_NOR_STM32L4X
#define OPENOCD_FLASH_NOR_STM32L4X
+/* IMPORTANT: this file is included by stm32l4x driver and flashloader,
+ * so please when changing this file, do not forget to check the flashloader */
+
+/* FIXME: #include "helper/bits.h" cause build errors when compiling
+ * the flashloader, for now just redefine the needed 'BIT 'macro */
+
+#ifndef BIT
+#define BIT(nr) (1UL << (nr))
+#endif
+
/* FLASH_CR register bits */
-#define FLASH_PG (1 << 0)
-#define FLASH_PER (1 << 1)
-#define FLASH_MER1 (1 << 2)
+#define FLASH_PG BIT(0)
+#define FLASH_PER BIT(1)
+#define FLASH_MER1 BIT(2)
#define FLASH_PAGE_SHIFT 3
-#define FLASH_BKER (1 << 11)
-#define FLASH_BKER_G0 (1 << 13)
-#define FLASH_MER2 (1 << 15)
-#define FLASH_STRT (1 << 16)
-#define FLASH_OPTSTRT (1 << 17)
-#define FLASH_EOPIE (1 << 24)
-#define FLASH_ERRIE (1 << 25)
-#define FLASH_OBL_LAUNCH (1 << 27)
-#define FLASH_OPTLOCK (1 << 30)
-#define FLASH_LOCK (1 << 31)
+#define FLASH_BKER BIT(11)
+#define FLASH_BKER_G0 BIT(13)
+#define FLASH_MER2 BIT(15)
+#define FLASH_STRT BIT(16)
+#define FLASH_OPTSTRT BIT(17)
+#define FLASH_EOPIE BIT(24)
+#define FLASH_ERRIE BIT(25)
+#define FLASH_OBL_LAUNCH BIT(27)
+#define FLASH_OPTLOCK BIT(30)
+#define FLASH_LOCK BIT(31)
/* FLASH_SR register bits */
-#define FLASH_BSY (1 << 16)
-#define FLASH_BSY2 (1 << 17)
+#define FLASH_BSY BIT(16)
+#define FLASH_BSY2 BIT(17)
/* Fast programming not used => related errors not used*/
-#define FLASH_PGSERR (1 << 7) /* Programming sequence error */
-#define FLASH_SIZERR (1 << 6) /* Size error */
-#define FLASH_PGAERR (1 << 5) /* Programming alignment error */
-#define FLASH_WRPERR (1 << 4) /* Write protection error */
-#define FLASH_PROGERR (1 << 3) /* Programming error */
-#define FLASH_OPERR (1 << 1) /* Operation error */
-#define FLASH_EOP (1 << 0) /* End of operation */
+#define FLASH_PGSERR BIT(7) /* Programming sequence error */
+#define FLASH_SIZERR BIT(6) /* Size error */
+#define FLASH_PGAERR BIT(5) /* Programming alignment error */
+#define FLASH_WRPERR BIT(4) /* Write protection error */
+#define FLASH_PROGERR BIT(3) /* Programming error */
+#define FLASH_OPERR BIT(1) /* Operation error */
+#define FLASH_EOP BIT(0) /* End of operation */
#define FLASH_ERROR (FLASH_PGSERR | FLASH_SIZERR | FLASH_PGAERR | \
FLASH_WRPERR | FLASH_PROGERR | FLASH_OPERR)
@@ -60,7 +70,7 @@
/* FLASH_OPTR register bits */
#define FLASH_RDP_MASK 0xFF
-#define FLASH_TZEN (1 << 31)
+#define FLASH_TZEN BIT(31)
/* FLASH secure block based bank 1/2 register offsets */
#define FLASH_SECBB1(X) (0x80 + 4 * (X - 1))
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32l4x.h | 56 ++++++++++++++++++++++++++++--------------------
1 file changed, 33 insertions(+), 23 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-08-26 06:38:42
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 43d31a8fd507a7d15083b487cf06d3f934e25843 (commit)
from e7e46ba61e6d0bf06f65f352e8607db1dda83da1 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 43d31a8fd507a7d15083b487cf06d3f934e25843
Author: Tarek BOCHKATI <tar...@gm...>
Date: Tue Jan 19 13:26:48 2021 +0100
flash/stm32l4x: add support of STM32G0Bx/G0Cx devices
this device has a dual bank flash architecture up to 512 KB (page 2KB)
reference: RM0444 Rev 5
notes:
- 128k variant is always single bank
- 256k variant flash is contiguous (no gap) in dual bank mode
- BKER is bit 13 vs bit 11 for other devices
> added cr_bker_mask in stm32l4_flash_bank struct
- BSY2 for bank 2 operations
> added sr_bsy_mask in stm32l4_flash_bank struct
> proposed optimization: always wait for (BSY1 | BSY2) with
STM32G0Bx/G0Cx devices only (for L4+ devices BSY2=PEMPTY)
TODO: update flashloader to use the proper BSY bits
temporarily don't use the loader in dual bank mode
Change-Id: I54b0c93b494e7209da818791d15edd8cd42c2732
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6036
Reviewed-by: Oleksij Rempel <li...@re...>
Tested-by: jenkins
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index 32dff35e0..ff804bbaf 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -218,6 +218,8 @@ struct stm32l4_flash_bank {
bool dual_bank_mode;
int hole_sectors;
uint32_t user_bank_size;
+ uint32_t cr_bker_mask;
+ uint32_t sr_bsy_mask;
uint32_t wrpxxr_mask;
const struct stm32l4_part_info *part_info;
uint32_t flash_regs_base;
@@ -275,6 +277,10 @@ static const struct stm32l4_rev stm32_466_revs[] = {
{ 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
};
+static const struct stm32l4_rev stm32_467_revs[] = {
+ { 0x1000, "A" },
+};
+
static const struct stm32l4_rev stm32_468_revs[] = {
{ 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
};
@@ -396,6 +402,18 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.otp_base = 0x1FFF7000,
.otp_size = 1024,
},
+ {
+ .id = 0x467,
+ .revs = stm32_467_revs,
+ .num_revs = ARRAY_SIZE(stm32_467_revs),
+ .device_str = "STM32G0Bx/G0Cx",
+ .max_flash_size_kb = 512,
+ .flags = F_HAS_DUAL_BANK,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF75E0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
{
.id = 0x468,
.revs = stm32_468_revs,
@@ -691,6 +709,7 @@ static inline int stm32l4_write_flash_reg_by_index(struct flash_bank *bank,
static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
{
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
uint32_t status;
int retval = ERROR_OK;
@@ -700,7 +719,7 @@ static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
- if ((status & FLASH_BSY) == 0)
+ if ((status & stm32l4_info->sr_bsy_mask) == 0)
break;
if (timeout-- <= 0) {
LOG_ERROR("timed out waiting for flash");
@@ -1092,7 +1111,7 @@ static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
if (i >= stm32l4_info->bank1_sectors) {
uint8_t snb;
snb = i - stm32l4_info->bank1_sectors;
- erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
+ erase_flags |= snb << FLASH_PAGE_SHIFT | stm32l4_info->cr_bker_mask;
} else
erase_flags |= i << FLASH_PAGE_SHIFT;
retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, erase_flags);
@@ -1463,7 +1482,18 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
if (retval != ERROR_OK)
goto err_lock;
- if (stm32l4_info->use_flashloader) {
+ /**
+ * FIXME update the flash loader to use a custom FLASH_SR_BSY mask
+ * Workaround for STM32G0Bx/G0Cx devices in dual bank mode,
+ * as the flash loader does not use the SR_BSY2
+ */
+ bool use_flashloader = stm32l4_info->use_flashloader;
+ if ((stm32l4_info->part_info->id == 0x467) && stm32l4_info->dual_bank_mode) {
+ LOG_INFO("Couldn't use the flash loader in dual-bank mode");
+ use_flashloader = false;
+ }
+
+ if (use_flashloader) {
/* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
* the debug is possible only in non-secure state.
* Thus means the flashloader will run in non-secure mode,
@@ -1474,7 +1504,7 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
retval = stm32l4_write_block(bank, buffer, offset, count / 8);
}
- if (!stm32l4_info->use_flashloader || retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
+ if (!use_flashloader || retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
LOG_INFO("falling back to single memory accesses");
retval = stm32l4_write_block_without_loader(bank, buffer, offset, count / 8);
}
@@ -1573,6 +1603,8 @@ static int stm32l4_probe(struct flash_bank *bank)
stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
stm32l4_info->flash_regs_base = stm32l4_info->part_info->flash_regs_base;
+ stm32l4_info->cr_bker_mask = FLASH_BKER;
+ stm32l4_info->sr_bsy_mask = FLASH_BSY;
/* initialise the flash registers layout */
if (part_info->flags & F_HAS_L5_FLASH_REGS)
@@ -1696,6 +1728,20 @@ static int stm32l4_probe(struct flash_bank *bank)
num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages;
break;
+ case 0x467: /* STM32G0B/G0Cxx */
+ /* single/dual bank depending on bit(21) */
+ page_size_kb = 2;
+ num_pages = flash_size_kb / page_size_kb;
+ stm32l4_info->bank1_sectors = num_pages;
+ stm32l4_info->cr_bker_mask = FLASH_BKER_G0;
+
+ /* check DUAL_BANK bit */
+ if (stm32l4_info->optr & BIT(21)) {
+ stm32l4_info->sr_bsy_mask = FLASH_BSY | FLASH_BSY2;
+ stm32l4_info->dual_bank_mode = true;
+ stm32l4_info->bank1_sectors = num_pages / 2;
+ }
+ break;
case 0x469: /* STM32G47/G48xx */
/* STM32G47/8 can be single/dual bank:
* if DUAL_BANK = 0 -> single bank
diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h
index b8f3d8c5b..ba809ff40 100644
--- a/src/flash/nor/stm32l4x.h
+++ b/src/flash/nor/stm32l4x.h
@@ -24,7 +24,8 @@
#define FLASH_PER (1 << 1)
#define FLASH_MER1 (1 << 2)
#define FLASH_PAGE_SHIFT 3
-#define FLASH_CR_BKER (1 << 11)
+#define FLASH_BKER (1 << 11)
+#define FLASH_BKER_G0 (1 << 13)
#define FLASH_MER2 (1 << 15)
#define FLASH_STRT (1 << 16)
#define FLASH_OPTSTRT (1 << 17)
@@ -36,6 +37,7 @@
/* FLASH_SR register bits */
#define FLASH_BSY (1 << 16)
+#define FLASH_BSY2 (1 << 17)
/* Fast programming not used => related errors not used*/
#define FLASH_PGSERR (1 << 7) /* Programming sequence error */
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32l4x.c | 54 ++++++++++++++++++++++++++++++++++++++++++++----
src/flash/nor/stm32l4x.h | 4 +++-
2 files changed, 53 insertions(+), 5 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-08-26 06:38:03
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit e7e46ba61e6d0bf06f65f352e8607db1dda83da1
Author: Tarek BOCHKATI <tar...@gm...>
Date: Sat Aug 14 00:09:29 2021 +0100
flash/stm32l4x: remove stm32l4_part_info.default_flash_regs
This struct element is replaced by the usage of F_HAS_L5_FLASH_REGS flag:
since over this driver stm32l4_flash_regs is the default register layout,
and the only exception is STM32L5 family,
so it's simpler to manage it using a flag.
Note: the same flag will be used with STM32U5 devices, as they have
the same registers layout, which explains the move of stm32l5_s_flash_regs
before the switch(device_id) in order to not re-write this for STM32U5.
Change-Id: I3b67a6f558d9350f609a22524012b6fceb7de7c2
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6435
Reviewed-by: Oleksij Rempel <li...@re...>
Tested-by: jenkins
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index 5bc23090f..32dff35e0 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -206,7 +206,6 @@ struct stm32l4_part_info {
const uint16_t max_flash_size_kb;
const uint32_t flags; /* one bit per feature, see STM32L4 flags: macros F_XXX */
const uint32_t flash_regs_base;
- const uint32_t *default_flash_regs;
const uint32_t fsize_addr;
const uint32_t otp_base;
const uint32_t otp_size;
@@ -321,7 +320,6 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.max_flash_size_kb = 1024,
.flags = F_HAS_DUAL_BANK,
.flash_regs_base = 0x40022000,
- .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
.otp_base = 0x1FFF7000,
.otp_size = 1024,
@@ -334,7 +332,6 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.max_flash_size_kb = 256,
.flags = F_NONE,
.flash_regs_base = 0x40022000,
- .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
.otp_base = 0x1FFF7000,
.otp_size = 1024,
@@ -347,7 +344,6 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.max_flash_size_kb = 128,
.flags = F_NONE,
.flash_regs_base = 0x40022000,
- .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
.otp_base = 0x1FFF7000,
.otp_size = 1024,
@@ -360,7 +356,6 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.max_flash_size_kb = 1024,
.flags = F_HAS_DUAL_BANK,
.flash_regs_base = 0x40022000,
- .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
.otp_base = 0x1FFF7000,
.otp_size = 1024,
@@ -373,7 +368,6 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.max_flash_size_kb = 512,
.flags = F_NONE,
.flash_regs_base = 0x40022000,
- .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
.otp_base = 0x1FFF7000,
.otp_size = 1024,
@@ -386,7 +380,6 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.max_flash_size_kb = 128,
.flags = F_NONE,
.flash_regs_base = 0x40022000,
- .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
.otp_base = 0x1FFF7000,
.otp_size = 1024,
@@ -399,7 +392,6 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.max_flash_size_kb = 64,
.flags = F_NONE,
.flash_regs_base = 0x40022000,
- .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
.otp_base = 0x1FFF7000,
.otp_size = 1024,
@@ -412,7 +404,6 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.max_flash_size_kb = 128,
.flags = F_NONE,
.flash_regs_base = 0x40022000,
- .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
.otp_base = 0x1FFF7000,
.otp_size = 1024,
@@ -425,7 +416,6 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.max_flash_size_kb = 512,
.flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
.flash_regs_base = 0x40022000,
- .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
.otp_base = 0x1FFF7000,
.otp_size = 1024,
@@ -438,7 +428,6 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.max_flash_size_kb = 2048,
.flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
.flash_regs_base = 0x40022000,
- .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
.otp_base = 0x1FFF7000,
.otp_size = 1024,
@@ -451,7 +440,6 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.max_flash_size_kb = 1024,
.flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
.flash_regs_base = 0x40022000,
- .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
.otp_base = 0x1FFF7000,
.otp_size = 1024,
@@ -464,7 +452,6 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.max_flash_size_kb = 512,
.flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
.flash_regs_base = 0x40022000,
- .default_flash_regs = stm32l5_ns_flash_regs,
.fsize_addr = 0x0BFA05E0,
.otp_base = 0x0BFA0000,
.otp_size = 512,
@@ -477,7 +464,6 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.max_flash_size_kb = 512,
.flags = F_NONE,
.flash_regs_base = 0x40022000,
- .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
.otp_base = 0x1FFF7000,
.otp_size = 1024,
@@ -490,7 +476,6 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.max_flash_size_kb = 1024,
.flags = F_NONE,
.flash_regs_base = 0x58004000,
- .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
.otp_base = 0x1FFF7000,
.otp_size = 1024,
@@ -503,7 +488,6 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.max_flash_size_kb = 512,
.flags = F_NONE,
.flash_regs_base = 0x58004000,
- .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
.otp_base = 0x1FFF7000,
.otp_size = 1024,
@@ -516,7 +500,6 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.max_flash_size_kb = 256,
.flags = F_NONE,
.flash_regs_base = 0x58004000,
- .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
.otp_base = 0x1FFF7000,
.otp_size = 1024,
@@ -1590,7 +1573,12 @@ static int stm32l4_probe(struct flash_bank *bank)
stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
stm32l4_info->flash_regs_base = stm32l4_info->part_info->flash_regs_base;
- stm32l4_info->flash_regs = stm32l4_info->part_info->default_flash_regs;
+
+ /* initialise the flash registers layout */
+ if (part_info->flags & F_HAS_L5_FLASH_REGS)
+ stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
+ else
+ stm32l4_info->flash_regs = stm32l4_flash_regs;
/* read flash option register */
retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &stm32l4_info->optr);
@@ -1599,6 +1587,17 @@ static int stm32l4_probe(struct flash_bank *bank)
stm32l4_sync_rdp_tzen(bank);
+ /* for devices with trustzone, use flash secure registers when TZEN=1 and RDP is LEVEL_0 */
+ if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
+ if (part_info->flags & F_HAS_L5_FLASH_REGS) {
+ stm32l4_info->flash_regs_base |= STM32L5_REGS_SEC_OFFSET;
+ stm32l4_info->flash_regs = stm32l5_s_flash_regs;
+ } else {
+ LOG_ERROR("BUG: device supported incomplete");
+ return ERROR_NOT_IMPLEMENTED;
+ }
+ }
+
if (part_info->flags & F_HAS_TZ)
LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
stm32l4_info->tzen,
@@ -1753,15 +1752,6 @@ static int stm32l4_probe(struct flash_bank *bank)
num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages / 2;
}
-
- /**
- * by default use the non-secure registers,
- * switch secure registers if TZ is enabled and RDP is LEVEL_0
- */
- if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
- stm32l4_info->flash_regs_base |= 0x10000000;
- stm32l4_info->flash_regs = stm32l5_s_flash_regs;
- }
break;
case 0x495: /* STM32WB5x */
case 0x496: /* STM32WB3x */
diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h
index ebc6ed95a..b8f3d8c5b 100644
--- a/src/flash/nor/stm32l4x.h
+++ b/src/flash/nor/stm32l4x.h
@@ -75,4 +75,6 @@
#define STM32_FLASH_BANK_BASE 0x08000000
#define STM32_FLASH_S_BANK_BASE 0x0C000000
+#define STM32L5_REGS_SEC_OFFSET 0x10000000
+
#endif
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32l4x.c | 44 +++++++++++++++++---------------------------
src/flash/nor/stm32l4x.h | 2 ++
2 files changed, 19 insertions(+), 27 deletions(-)
hooks/post-receive
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From: OpenOCD-Gerrit <ope...@us...> - 2021-08-26 06:27:53
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 1247eee4e6e55889b14bec8d81c4748767bb67b8 (commit)
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- Log -----------------------------------------------------------------
commit 1247eee4e6e55889b14bec8d81c4748767bb67b8
Author: Tarek BOCHKATI <tar...@gm...>
Date: Tue May 25 11:54:50 2021 +0100
flash/stm32l4x: introduce flash programming without loader
this capability permits to program the flash if we cannot reserve a workarea.
the introduction the command 'stm32l4x flashloader <bank_id> [enable|disable]'
helps to automatically skip using the flashloader if needed.
Change-Id: Id29213c85ee5c7c487cfee21554f5a7ea50db6c9
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6273
Reviewed-by: Oleksij Rempel <li...@re...>
Tested-by: jenkins
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 33812499a..4404807a6 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -7344,6 +7344,13 @@ Unlocks the entire stm32 device.
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
+@deffn Command {stm32l4x flashloader} num [@option{enable} | @option{disable}]
+Enables or disables the flashloader usage (enabled by default),
+when disabled it will fall back to direct memory access to program the Flash or OTP memories.
+if neither @option{enabled} nor @option{disable} are specified, the command will display
+the current configuration.
+@end deffn
+
@deffn {Command} {stm32l4x mass_erase} num
Mass erases the entire stm32l4x device.
The @var{num} parameter is a value shown by @command{flash banks}.
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index de36d56c7..5bc23090f 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -116,6 +116,7 @@
/* Erase time can be as high as 25ms, 10x this and assume it's toast... */
#define FLASH_ERASE_TIMEOUT 250
+#define FLASH_WRITE_TIMEOUT 50
/* relevant STM32L4 flags ****************************************************/
@@ -223,6 +224,7 @@ struct stm32l4_flash_bank {
uint32_t flash_regs_base;
const uint32_t *flash_regs;
bool otp_enabled;
+ bool use_flashloader;
enum stm32l4_rdp rdp;
bool tzen;
uint32_t optr;
@@ -545,6 +547,7 @@ FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
stm32l4_info->probed = false;
stm32l4_info->otp_enabled = false;
stm32l4_info->user_bank_size = bank->size;
+ stm32l4_info->use_flashloader = true;
return ERROR_OK;
}
@@ -1362,6 +1365,49 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
return retval;
}
+/* Count is in double-words */
+static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ uint32_t address = bank->base + offset;
+ int retval = ERROR_OK;
+
+ /* wait for BSY bit */
+ retval = stm32l4_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* set PG in FLASH_CR */
+ retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_PG);
+ if (retval != ERROR_OK)
+ return retval;
+
+
+ /* write directly to flash memory */
+ const uint8_t *src = buffer;
+ while (count--) {
+ retval = target_write_memory(target, address, 4, 2, src);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* wait for BSY bit */
+ retval = stm32l4_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ src += 8;
+ address += 8;
+ }
+
+ /* reset PG in FLASH_CR */
+ retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, 0);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return retval;
+}
+
static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
@@ -1434,14 +1480,22 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
if (retval != ERROR_OK)
goto err_lock;
- /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
- * the debug is possible only in non-secure state.
- * Thus means the flashloader will run in non-secure mode,
- * and the workarea need to be in non-secure RAM */
- if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5))
- LOG_INFO("RDP level is 0.5, the work-area should reside in non-secure RAM");
+ if (stm32l4_info->use_flashloader) {
+ /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
+ * the debug is possible only in non-secure state.
+ * Thus means the flashloader will run in non-secure mode,
+ * and the workarea need to be in non-secure RAM */
+ if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5))
+ LOG_INFO("RDP level is 0.5, the work-area should reside in non-secure RAM");
+
+ retval = stm32l4_write_block(bank, buffer, offset, count / 8);
+ }
+
+ if (!stm32l4_info->use_flashloader || retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
+ LOG_INFO("falling back to single memory accesses");
+ retval = stm32l4_write_block_without_loader(bank, buffer, offset, count / 8);
+ }
- retval = stm32l4_write_block(bank, buffer, offset, count / 8);
err_lock:
retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
@@ -2017,6 +2071,26 @@ COMMAND_HANDLER(stm32l4_handle_trustzone_command)
return stm32l4_perform_obl_launch(bank);
}
+COMMAND_HANDLER(stm32l4_handle_flashloader_command)
+{
+ if (CMD_ARGC < 1 || CMD_ARGC > 2)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+
+ if (CMD_ARGC == 2)
+ COMMAND_PARSE_ENABLE(CMD_ARGV[1], stm32l4_info->use_flashloader);
+
+ command_print(CMD, "FlashLoader usage is %s", stm32l4_info->use_flashloader ? "enabled" : "disabled");
+
+ return ERROR_OK;
+}
+
COMMAND_HANDLER(stm32l4_handle_option_load_command)
{
if (CMD_ARGC != 1)
@@ -2222,6 +2296,13 @@ static const struct command_registration stm32l4_exec_command_handlers[] = {
.usage = "bank_id",
.help = "Unlock entire protected flash device.",
},
+ {
+ .name = "flashloader",
+ .handler = stm32l4_handle_flashloader_command,
+ .mode = COMMAND_EXEC,
+ .usage = "<bank_id> [enable|disable]",
+ .help = "Configure the flashloader usage",
+ },
{
.name = "mass_erase",
.handler = stm32l4_handle_mass_erase_command,
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 7 ++++
src/flash/nor/stm32l4x.c | 95 ++++++++++++++++++++++++++++++++++++++++++++----
2 files changed, 95 insertions(+), 7 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-08-26 06:22:03
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via e609d5a5de84b3daf8b9524143e41a6c0713fd8f (commit)
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- Log -----------------------------------------------------------------
commit e609d5a5de84b3daf8b9524143e41a6c0713fd8f
Author: Tarek BOCHKATI <tar...@gm...>
Date: Fri Jan 22 13:15:52 2021 +0100
flash/stm32l4x: STM32L5 support programming when TZEN=1 and RDP=0x55
when RDP level is 0.5 the provided work-area should reside in non-secure RAM
to ensure that:
- add a hint in the driver level
- reduce the usage of secure RAM only when TZEN=1 and RDP is not 0.5
(check the target configuration file)
Change-Id: Idbf2325e609b84ef8480eefdb49a176fdf7e07c7
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6035
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Oleksij Rempel <li...@re...>
Tested-by: jenkins
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index db8d5e78d..de36d56c7 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -1434,6 +1434,13 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
if (retval != ERROR_OK)
goto err_lock;
+ /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
+ * the debug is possible only in non-secure state.
+ * Thus means the flashloader will run in non-secure mode,
+ * and the workarea need to be in non-secure RAM */
+ if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5))
+ LOG_INFO("RDP level is 0.5, the work-area should reside in non-secure RAM");
+
retval = stm32l4_write_block(bank, buffer, offset, count / 8);
err_lock:
diff --git a/tcl/target/stm32l5x.cfg b/tcl/target/stm32l5x.cfg
index 02297e369..0616df1cb 100644
--- a/tcl/target/stm32l5x.cfg
+++ b/tcl/target/stm32l5x.cfg
@@ -173,7 +173,11 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
} {
ahb_ap_secure_access
echo "TZEN option bit enabled"
- set use_secure_workarea 1
+
+ # check if FLASH_OPTR.RDP is not Level 0.5
+ if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
+ set use_secure_workarea 1
+ }
}
set workarea_addr [$_TARGETNAME cget -work-area-phys]
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32l4x.c | 7 +++++++
tcl/target/stm32l5x.cfg | 6 +++++-
2 files changed, 12 insertions(+), 1 deletion(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2021-08-26 06:19:39
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via c9d40366ad55ea3a83f2ff438aab1e62da653169 (commit)
from 80d323c6e82b0256da4a671b1acbdceb54de9a82 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit c9d40366ad55ea3a83f2ff438aab1e62da653169
Author: Tarek BOCHKATI <tar...@gm...>
Date: Thu Nov 12 17:19:40 2020 +0100
flash/stm32l4x: STM32L5 support programming when TZEN=1 and RDP=0xAA
STM32L5 flash memory is aliased to 0x0C000000, this address mapping
is used for secure applications. (0x08000000 for non-secure)
this change allows the programming of secure and non-secure flash
when trustzone is enabled and RDP level is 0
Change-Id: I89d1f1b5d493cf01a142ca4dbfef5a3731cab96e
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/5936
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index 06d4ac1ea..db8d5e78d 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -127,6 +127,8 @@
#define F_USE_ALL_WRPXX BIT(1)
/* this flag indicates if the device embeds a TrustZone security feature */
#define F_HAS_TZ BIT(2)
+/* this flag indicates if the device has the same flash registers as STM32L5 */
+#define F_HAS_L5_FLASH_REGS BIT(3)
/* end of STM32L4 flags ******************************************************/
@@ -166,10 +168,23 @@ static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
[STM32_FLASH_ACR_INDEX] = 0x000,
- [STM32_FLASH_KEYR_INDEX] = 0x008,
+ [STM32_FLASH_KEYR_INDEX] = 0x008, /* NSKEYR */
+ [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
+ [STM32_FLASH_SR_INDEX] = 0x020, /* NSSR */
+ [STM32_FLASH_CR_INDEX] = 0x028, /* NSCR */
+ [STM32_FLASH_OPTR_INDEX] = 0x040,
+ [STM32_FLASH_WRP1AR_INDEX] = 0x058,
+ [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
+ [STM32_FLASH_WRP2AR_INDEX] = 0x068,
+ [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
+};
+
+static const uint32_t stm32l5_s_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
+ [STM32_FLASH_ACR_INDEX] = 0x000,
+ [STM32_FLASH_KEYR_INDEX] = 0x00C, /* SECKEYR */
[STM32_FLASH_OPTKEYR_INDEX] = 0x010,
- [STM32_FLASH_SR_INDEX] = 0x020,
- [STM32_FLASH_CR_INDEX] = 0x028,
+ [STM32_FLASH_SR_INDEX] = 0x024, /* SECSR */
+ [STM32_FLASH_CR_INDEX] = 0x02C, /* SECCR */
[STM32_FLASH_OPTR_INDEX] = 0x040,
[STM32_FLASH_WRP1AR_INDEX] = 0x058,
[STM32_FLASH_WRP1BR_INDEX] = 0x05C,
@@ -205,6 +220,7 @@ struct stm32l4_flash_bank {
uint32_t user_bank_size;
uint32_t wrpxxr_mask;
const struct stm32l4_part_info *part_info;
+ uint32_t flash_regs_base;
const uint32_t *flash_regs;
bool otp_enabled;
enum stm32l4_rdp rdp;
@@ -444,7 +460,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_472_revs),
.device_str = "STM32L55/L56xx",
.max_flash_size_kb = 512,
- .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ,
+ .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
.flash_regs_base = 0x40022000,
.default_flash_regs = stm32l5_ns_flash_regs,
.fsize_addr = 0x0BFA05E0,
@@ -653,7 +669,7 @@ static void stm32l4_sync_rdp_tzen(struct flash_bank *bank)
static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
{
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
- return stm32l4_info->part_info->flash_regs_base + reg_offset;
+ return stm32l4_info->flash_regs_base + reg_offset;
}
static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank,
@@ -725,6 +741,49 @@ static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
return retval;
}
+/** set all FLASH_SECBB registers to the same value */
+static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
+{
+ /* This function should be used only with device with TrustZone, do just a security check */
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ assert(stm32l4_info->part_info->flags & F_HAS_TZ);
+
+ /* based on RM0438 Rev6 for STM32L5x devices:
+ * to modify a page block-based security attribution, it is recommended to
+ * 1- check that no flash operation is ongoing on the related page
+ * 2- add ISB instruction after modifying the page security attribute in SECBBxRy
+ * this step is not need in case of JTAG direct access
+ */
+ int retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* write SECBBxRy registers */
+ LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value);
+
+ const uint8_t secbb_regs[] = {
+ FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */
+ FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */
+ };
+
+
+ unsigned int num_secbb_regs = ARRAY_SIZE(secbb_regs);
+
+ /* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers
+ * then consider only the first half of secbb_regs
+ */
+ if (!stm32l4_info->dual_bank_mode)
+ num_secbb_regs /= 2;
+
+ for (unsigned int i = 0; i < num_secbb_regs; i++) {
+ retval = stm32l4_write_flash_reg(bank, secbb_regs[i], value);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ return ERROR_OK;
+}
+
static int stm32l4_unlock_reg(struct flash_bank *bank)
{
uint32_t ctrl;
@@ -831,6 +890,7 @@ err_lock:
static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
uint32_t value, uint32_t mask)
{
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
uint32_t optiondata;
int retval, retval2;
@@ -838,6 +898,12 @@ static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
if (retval != ERROR_OK)
return retval;
+ /* for STM32L5 and similar devices, use always non-secure
+ * registers for option bytes programming */
+ const uint32_t *saved_flash_regs = stm32l4_info->flash_regs;
+ if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
+ stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
+
retval = stm32l4_unlock_reg(bank);
if (retval != ERROR_OK)
goto err_lock;
@@ -860,6 +926,7 @@ static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
err_lock:
retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK | FLASH_OPTLOCK);
+ stm32l4_info->flash_regs = saved_flash_regs;
if (retval != ERROR_OK)
return retval;
@@ -1007,6 +1074,16 @@ static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
return ERROR_TARGET_NOT_HALTED;
}
+ if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
+ /* set all FLASH pages as secure */
+ retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
+ if (retval != ERROR_OK) {
+ /* restore all FLASH pages as non-secure */
+ stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
+ return retval;
+ }
+ }
+
retval = stm32l4_unlock_reg(bank);
if (retval != ERROR_OK)
goto err_lock;
@@ -1044,6 +1121,13 @@ static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
err_lock:
retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
+ if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
+ /* restore all FLASH pages as non-secure */
+ int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
+ if (retval3 != ERROR_OK)
+ return retval3;
+ }
+
if (retval != ERROR_OK)
return retval;
@@ -1281,6 +1365,7 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
int retval = ERROR_OK, retval2;
if (stm32l4_is_otp(bank) && !stm32l4_otp_is_enabled(bank)) {
@@ -1335,6 +1420,16 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
if (retval != ERROR_OK)
return retval;
+ if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
+ /* set all FLASH pages as secure */
+ retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
+ if (retval != ERROR_OK) {
+ /* restore all FLASH pages as non-secure */
+ stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
+ return retval;
+ }
+ }
+
retval = stm32l4_unlock_reg(bank);
if (retval != ERROR_OK)
goto err_lock;
@@ -1344,6 +1439,13 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
err_lock:
retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
+ if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
+ /* restore all FLASH pages as non-secure */
+ int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
+ if (retval3 != ERROR_OK)
+ return retval3;
+ }
+
if (retval != ERROR_OK) {
LOG_ERROR("block write failed");
return retval;
@@ -1426,6 +1528,7 @@ static int stm32l4_probe(struct flash_bank *bank)
LOG_INFO("device idcode = 0x%08" PRIx32 " (%s - Rev %s : 0x%04x)",
stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
+ stm32l4_info->flash_regs_base = stm32l4_info->part_info->flash_regs_base;
stm32l4_info->flash_regs = stm32l4_info->part_info->default_flash_regs;
/* read flash option register */
@@ -1461,7 +1564,7 @@ static int stm32l4_probe(struct flash_bank *bank)
stm32l4_info->probed = true;
return ERROR_OK;
- } else if (bank->base != STM32_FLASH_BANK_BASE) {
+ } else if (bank->base != STM32_FLASH_BANK_BASE && bank->base != STM32_FLASH_S_BANK_BASE) {
LOG_ERROR("invalid bank base address");
return ERROR_FAIL;
}
@@ -1589,6 +1692,15 @@ static int stm32l4_probe(struct flash_bank *bank)
num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages / 2;
}
+
+ /**
+ * by default use the non-secure registers,
+ * switch secure registers if TZ is enabled and RDP is LEVEL_0
+ */
+ if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
+ stm32l4_info->flash_regs_base |= 0x10000000;
+ stm32l4_info->flash_regs = stm32l5_s_flash_regs;
+ }
break;
case 0x495: /* STM32WB5x */
case 0x496: /* STM32WB3x */
@@ -1714,6 +1826,16 @@ static int stm32l4_mass_erase(struct flash_bank *bank)
return ERROR_TARGET_NOT_HALTED;
}
+ if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
+ /* set all FLASH pages as secure */
+ retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
+ if (retval != ERROR_OK) {
+ /* restore all FLASH pages as non-secure */
+ stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
+ return retval;
+ }
+ }
+
retval = stm32l4_unlock_reg(bank);
if (retval != ERROR_OK)
goto err_lock;
@@ -1736,6 +1858,13 @@ static int stm32l4_mass_erase(struct flash_bank *bank)
err_lock:
retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
+ if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
+ /* restore all FLASH pages as non-secure */
+ int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
+ if (retval3 != ERROR_OK)
+ return retval3;
+ }
+
if (retval != ERROR_OK)
return retval;
diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h
index 41b5ff82d..ebc6ed95a 100644
--- a/src/flash/nor/stm32l4x.h
+++ b/src/flash/nor/stm32l4x.h
@@ -60,11 +60,19 @@
#define FLASH_RDP_MASK 0xFF
#define FLASH_TZEN (1 << 31)
+/* FLASH secure block based bank 1/2 register offsets */
+#define FLASH_SECBB1(X) (0x80 + 4 * (X - 1))
+#define FLASH_SECBB2(X) (0xA0 + 4 * (X - 1))
+
+#define FLASH_SECBB_SECURE 0xFFFFFFFF
+#define FLASH_SECBB_NON_SECURE 0
+
/* other registers */
#define DBGMCU_IDCODE_G0 0x40015800
#define DBGMCU_IDCODE_L4_G4 0xE0042000
#define DBGMCU_IDCODE_L5 0xE0044000
#define STM32_FLASH_BANK_BASE 0x08000000
+#define STM32_FLASH_S_BANK_BASE 0x0C000000
#endif
diff --git a/tcl/target/stm32l5x.cfg b/tcl/target/stm32l5x.cfg
index 92083b9e0..02297e369 100644
--- a/tcl/target/stm32l5x.cfg
+++ b/tcl/target/stm32l5x.cfg
@@ -52,9 +52,10 @@ target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
# use non-secure RAM by default
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-# declare non-secure flash
-flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
-flash bank $_CHIPNAME.otp stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
+# create sec/ns flash and otp memories (sizes will be probed)
+flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
# Common knowledges tells JTAG speed should be <= F_CPU/6.
# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
@@ -77,30 +78,47 @@ if {![using_hla]} {
cortex_m reset_config sysresetreq
}
+proc is_secure {} {
+ # read Debug Security Control and Status Regsiter (DSCSR) and check CDS (bit 16)
+ set DSCSR [mrw 0xE000EE08]
+ return [expr {($DSCSR & (1 << 16)) != 0}]
+}
+
proc clock_config_110_mhz {} {
+ set offset [expr {[is_secure] ? 0x10000000 : 0}]
# MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
# RCC_APB1ENR1 = PWREN
- mww 0x40021058 0x10000000
+ mww [expr {0x40021058 + $offset}] 0x10000000
# delay for register clock enable (read back reg)
- mrw 0x40021058
+ mrw [expr {0x40021058 + $offset}]
# PWR_CR1 : VOS Range 0
- mww 0x40007000 0
+ mww [expr {0x40007000 + $offset}] 0
# while (PWR_SR2 & VOSF)
- while {([mrw 0x40007014] & 0x0400)} {}
+ while {([mrw [expr {0x40007014 + $offset}]] & 0x0400)} {}
# FLASH_ACR : 5 WS for 110 MHz HCLK
mww 0x40022000 0x00000005
# RCC_PLLCFGR = PLLP=PLLQ=0, PLLR=00=2, PLLREN=1, PLLN=55, PLLM=0000=1, PLLSRC=MSI 4MHz
# fVCO = 4 x 55 /1 = 220
# SYSCLOCK = fVCO/PLLR = 220/2 = 110 MHz
- mww 0x4002100C 0x01003711
+ mww [expr {0x4002100C + $offset}] 0x01003711
# RCC_CR |= PLLON
- mmw 0x40021000 0x01000000 0
+ mmw [expr {0x40021000 + $offset}] 0x01000000 0
# while !(RCC_CR & PLLRDY)
- while {!([mrw 0x40021000] & 0x02000000)} {}
+ while {!([mrw [expr {0x40021000 + $offset}]] & 0x02000000)} {}
# RCC_CFGR |= SW_PLL
- mmw 0x40021008 0x00000003 0
+ mmw [expr {0x40021008 + $offset}] 0x00000003 0
# while ((RCC_CFGR & SWS) != PLL)
- while {([mrw 0x40021008] & 0x0C) != 0x0C} {}
+ while {([mrw [expr {0x40021008 + $offset}]] & 0x0C) != 0x0C} {}
+}
+
+proc ahb_ap_non_secure_access {} {
+ # SPROT=1=Non Secure access, Priv=1
+ [[target current] cget -dap] apcsw 0x4B000000 0x4F000000
+}
+
+proc ahb_ap_secure_access {} {
+ # SPROT=0=Secure access, Priv=1
+ [[target current] cget -dap] apcsw 0x0B000000 0x4F000000
}
$_TARGETNAME configure -event reset-init {
@@ -123,6 +141,53 @@ $_TARGETNAME configure -event examine-end {
mmw 0xE0044008 0x00001800 0
}
+$_TARGETNAME configure -event halted {
+ set secure [is_secure]
+
+ if {$secure} {
+ set secure_str "Secure"
+ ahb_ap_secure_access
+ } else {
+ set secure_str "Non-Secure"
+ ahb_ap_non_secure_access
+ }
+
+ # print the secure state only when it changes
+ set _TARGETNAME [target current]
+ global $_TARGETNAME.secure
+
+ if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
+ echo "CPU in $secure_str state"
+ # update saved security state
+ set $_TARGETNAME.secure $secure
+ }
+}
+
+$_TARGETNAME configure -event gdb-flash-erase-start {
+ set use_secure_workarea 0
+ # check if FLASH_OPTR.TZEN is enabled
+ set FLASH_OPTR [mrw 0x40022040]
+ if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
+ echo "TZEN option bit disabled"
+ ahb_ap_non_secure_access
+ } {
+ ahb_ap_secure_access
+ echo "TZEN option bit enabled"
+ set use_secure_workarea 1
+ }
+
+ set workarea_addr [$_TARGETNAME cget -work-area-phys]
+ echo "workarea_addr $workarea_addr"
+
+ if {$use_secure_workarea} {
+ set workarea_addr [expr {$workarea_addr | 0x10000000}]
+ } {
+ set workarea_addr [expr {$workarea_addr & ~0x10000000}]
+ }
+
+ $_TARGETNAME configure -work-area-phys $workarea_addr
+}
+
$_TARGETNAME configure -event trace-config {
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32l4x.c | 141 +++++++++++++++++++++++++++++++++++++++++++++--
src/flash/nor/stm32l4x.h | 8 +++
tcl/target/stm32l5x.cfg | 89 ++++++++++++++++++++++++++----
3 files changed, 220 insertions(+), 18 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-08-26 06:19:18
|
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- Log -----------------------------------------------------------------
commit 80d323c6e82b0256da4a671b1acbdceb54de9a82
Author: Tarek BOCHKATI <tar...@gm...>
Date: Tue Nov 10 19:15:54 2020 +0100
flash/stm32l4x: introduce auto-probe when OPTR is changed
auto re-probing is ensured by having optr cache set in the
last probe operation.
this will help to detect if flash options have been modified by the
running application or by the user using direct register access.
Change-Id: I05cd7ab9e83a7fc26ac6cff175b3c11b0efa2eb5
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/5935
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Oleksij Rempel <li...@re...>
Tested-by: jenkins
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index 6370d17be..06d4ac1ea 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -209,6 +209,7 @@ struct stm32l4_flash_bank {
bool otp_enabled;
enum stm32l4_rdp rdp;
bool tzen;
+ uint32_t optr;
};
enum stm32_bank_id {
@@ -620,16 +621,16 @@ static inline bool stm32l4_otp_is_enabled(struct flash_bank *bank)
return stm32l4_info->otp_enabled;
}
-static void stm32l4_sync_rdp_tzen(struct flash_bank *bank, uint32_t optr_value)
+static void stm32l4_sync_rdp_tzen(struct flash_bank *bank)
{
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
bool tzen = false;
if (stm32l4_info->part_info->flags & F_HAS_TZ)
- tzen = (optr_value & FLASH_TZEN) != 0;
+ tzen = (stm32l4_info->optr & FLASH_TZEN) != 0;
- uint32_t rdp = optr_value & FLASH_RDP_MASK;
+ uint32_t rdp = stm32l4_info->optr & FLASH_RDP_MASK;
/* for devices without TrustZone:
* RDP level 0 and 2 values are to 0xAA and 0xCC
@@ -1396,7 +1397,6 @@ static int stm32l4_probe(struct flash_bank *bank)
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
const struct stm32l4_part_info *part_info;
uint16_t flash_size_kb = 0xffff;
- uint32_t options;
stm32l4_info->probed = false;
@@ -1429,11 +1429,11 @@ static int stm32l4_probe(struct flash_bank *bank)
stm32l4_info->flash_regs = stm32l4_info->part_info->default_flash_regs;
/* read flash option register */
- retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &options);
+ retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &stm32l4_info->optr);
if (retval != ERROR_OK)
return retval;
- stm32l4_sync_rdp_tzen(bank, options);
+ stm32l4_sync_rdp_tzen(bank);
if (part_info->flags & F_HAS_TZ)
LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
@@ -1515,7 +1515,7 @@ static int stm32l4_probe(struct flash_bank *bank)
stm32l4_info->bank1_sectors = num_pages;
/* check DUAL_BANK bit[21] if the flash is less than 1M */
- if (flash_size_kb == 1024 || (options & BIT(21))) {
+ if (flash_size_kb == 1024 || (stm32l4_info->optr & BIT(21))) {
stm32l4_info->dual_bank_mode = true;
stm32l4_info->bank1_sectors = num_pages / 2;
}
@@ -1541,7 +1541,7 @@ static int stm32l4_probe(struct flash_bank *bank)
page_size_kb = 4;
num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages;
- if (options & BIT(22)) {
+ if (stm32l4_info->optr & BIT(22)) {
stm32l4_info->dual_bank_mode = true;
page_size_kb = 2;
num_pages = flash_size_kb / page_size_kb;
@@ -1565,8 +1565,8 @@ static int stm32l4_probe(struct flash_bank *bank)
num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages;
use_dbank_bit = flash_size_kb == part_info->max_flash_size_kb;
- if ((use_dbank_bit && (options & BIT(22))) ||
- (!use_dbank_bit && (options & BIT(21)))) {
+ if ((use_dbank_bit && (stm32l4_info->optr & BIT(22))) ||
+ (!use_dbank_bit && (stm32l4_info->optr & BIT(21)))) {
stm32l4_info->dual_bank_mode = true;
page_size_kb = 4;
num_pages = flash_size_kb / page_size_kb;
@@ -1582,8 +1582,8 @@ static int stm32l4_probe(struct flash_bank *bank)
num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages;
use_dbank_bit = flash_size_kb == part_info->max_flash_size_kb;
- if ((use_dbank_bit && (options & BIT(22))) ||
- (!use_dbank_bit && (options & BIT(21)))) {
+ if ((use_dbank_bit && (stm32l4_info->optr & BIT(22))) ||
+ (!use_dbank_bit && (stm32l4_info->optr & BIT(21)))) {
stm32l4_info->dual_bank_mode = true;
page_size_kb = 2;
num_pages = flash_size_kb / page_size_kb;
@@ -1660,8 +1660,17 @@ static int stm32l4_probe(struct flash_bank *bank)
static int stm32l4_auto_probe(struct flash_bank *bank)
{
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
- if (stm32l4_info->probed)
- return ERROR_OK;
+ if (stm32l4_info->probed) {
+ uint32_t optr_cur;
+
+ /* read flash option register and re-probe if optr value is changed */
+ int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &optr_cur);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (stm32l4_info->optr == optr_cur)
+ return ERROR_OK;
+ }
return stm32l4_probe(bank);
}
@@ -1827,12 +1836,11 @@ COMMAND_HANDLER(stm32l4_handle_trustzone_command)
return ERROR_FAIL;
}
- uint32_t optr;
- retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &optr);
+ retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &stm32l4_info->optr);
if (retval != ERROR_OK)
return retval;
- stm32l4_sync_rdp_tzen(bank, optr);
+ stm32l4_sync_rdp_tzen(bank);
if (CMD_ARGC == 1) {
/* only display the TZEN value */
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32l4x.c | 42 +++++++++++++++++++++++++-----------------
1 file changed, 25 insertions(+), 17 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2021-08-26 06:17:36
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 84291d02692fe69d75ccd3ce11dea4522ad988a0 (commit)
from 1bce8d3d80490d66b56c2283e3ffee81a655a80a (commit)
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- Log -----------------------------------------------------------------
commit 84291d02692fe69d75ccd3ce11dea4522ad988a0
Author: Tarek BOCHKATI <tar...@gm...>
Date: Wed Mar 25 22:47:08 2020 +0100
flash/stm32l4x: introduce 'stm32l4x trustzone [enable|disable]' command
this command will help to enable/disable or display the TrustZone security,
using the TZEN option bit.
Note: This command works only with devices with TrustZone, eg. STM32L5.
Note: This command will perform an OBL_Launch after modifying the TZEN.
Change-Id: I4aef15bf57d09c1658d37858143d23b1d43de1f0
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/5542
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 340e6b65b..33812499a 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -7400,6 +7400,14 @@ write protected areas in a specific @var{device_bank}
Forces a re-load of the option byte registers. Will cause a system reset of the device.
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
+
+@deffn Command {stm32l4x trustzone} num [@option{enable} | @option{disable}]
+Enables or disables Global TrustZone Security, using the TZEN option bit.
+If neither @option{enabled} nor @option{disable} are specified, the command will display
+the TrustZone status.
+@emph{Note:} This command works only with devices with TrustZone, eg. STM32L5.
+@emph{Note:} This command will perform an OBL_Launch after modifying the TZEN.
+@end deffn
@end deffn
@deffn {Flash Driver} {str7x}
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index 5287ff6b3..6370d17be 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -791,6 +791,42 @@ static int stm32l4_unlock_option_reg(struct flash_bank *bank)
return ERROR_OK;
}
+static int stm32l4_perform_obl_launch(struct flash_bank *bank)
+{
+ int retval, retval2;
+
+ retval = stm32l4_unlock_reg(bank);
+ if (retval != ERROR_OK)
+ goto err_lock;
+
+ retval = stm32l4_unlock_option_reg(bank);
+ if (retval != ERROR_OK)
+ goto err_lock;
+
+ /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
+ * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
+ * "Note: If the read protection is set while the debugger is still
+ * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
+ */
+
+ /* "Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset" */
+ /* Due to this reset ST-Link reports an SWD_DP_ERROR, despite the write was successful,
+ * then just ignore the returned value */
+ stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OBL_LAUNCH);
+
+ /* Need to re-probe after change */
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ stm32l4_info->probed = false;
+
+err_lock:
+ retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK | FLASH_OPTLOCK);
+
+ if (retval != ERROR_OK)
+ return retval;
+
+ return retval2;
+}
+
static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
uint32_t value, uint32_t mask)
{
@@ -1775,9 +1811,9 @@ COMMAND_HANDLER(stm32l4_handle_option_write_command)
return retval;
}
-COMMAND_HANDLER(stm32l4_handle_option_load_command)
+COMMAND_HANDLER(stm32l4_handle_trustzone_command)
{
- if (CMD_ARGC != 1)
+ if (CMD_ARGC < 1 || CMD_ARGC > 2)
return ERROR_COMMAND_SYNTAX_ERROR;
struct flash_bank *bank;
@@ -1785,28 +1821,78 @@ COMMAND_HANDLER(stm32l4_handle_option_load_command)
if (retval != ERROR_OK)
return retval;
- retval = stm32l4_unlock_reg(bank);
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ if (!(stm32l4_info->part_info->flags & F_HAS_TZ)) {
+ LOG_ERROR("This device does not have a TrustZone");
+ return ERROR_FAIL;
+ }
+
+ uint32_t optr;
+ retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &optr);
if (retval != ERROR_OK)
return retval;
- retval = stm32l4_unlock_option_reg(bank);
+ stm32l4_sync_rdp_tzen(bank, optr);
+
+ if (CMD_ARGC == 1) {
+ /* only display the TZEN value */
+ LOG_INFO("Global TrustZone Security is %s", stm32l4_info->tzen ? "enabled" : "disabled");
+ return ERROR_OK;
+ }
+
+ bool new_tzen;
+ COMMAND_PARSE_ENABLE(CMD_ARGV[1], new_tzen);
+
+ if (new_tzen == stm32l4_info->tzen) {
+ LOG_INFO("The requested TZEN is already programmed");
+ return ERROR_OK;
+ }
+
+ if (new_tzen) {
+ if (stm32l4_info->rdp != RDP_LEVEL_0) {
+ LOG_ERROR("TZEN can be set only when RDP level is 0");
+ return ERROR_FAIL;
+ }
+ retval = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
+ FLASH_TZEN, FLASH_TZEN);
+ } else {
+ /* Deactivation of TZEN (from 1 to 0) is only possible when the RDP is
+ * changing to level 0 (from level 1 to level 0 or from level 0.5 to level 0). */
+ if (stm32l4_info->rdp != RDP_LEVEL_1 && stm32l4_info->rdp != RDP_LEVEL_0_5) {
+ LOG_ERROR("Deactivation of TZEN is only possible when the RDP is changing to level 0");
+ return ERROR_FAIL;
+ }
+
+ retval = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
+ RDP_LEVEL_0, FLASH_RDP_MASK | FLASH_TZEN);
+ }
+
if (retval != ERROR_OK)
return retval;
- /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
- * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
- * "Note: If the read protection is set while the debugger is still
- * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
- */
- retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OBL_LAUNCH);
+ return stm32l4_perform_obl_launch(bank);
+}
- command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
+COMMAND_HANDLER(stm32l4_handle_option_load_command)
+{
+ if (CMD_ARGC != 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
- /* Need to re-probe after change */
- struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
- stm32l4_info->probed = false;
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (retval != ERROR_OK)
+ return retval;
- return retval;
+ retval = stm32l4_perform_obl_launch(bank);
+ if (retval != ERROR_OK) {
+ command_print(CMD, "stm32l4x option load failed");
+ return retval;
+ }
+
+
+ command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
+
+ return ERROR_OK;
}
COMMAND_HANDLER(stm32l4_handle_lock_command)
@@ -2013,6 +2099,13 @@ static const struct command_registration stm32l4_exec_command_handlers[] = {
.usage = "bank_id reg_offset value mask",
.help = "Write device option bit fields with provided value.",
},
+ {
+ .name = "trustzone",
+ .handler = stm32l4_handle_trustzone_command,
+ .mode = COMMAND_EXEC,
+ .usage = "<bank_id> [enable|disable]",
+ .help = "Configure TrustZone security",
+ },
{
.name = "wrp_info",
.handler = stm32l4_handle_wrp_info_command,
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 8 +++
src/flash/nor/stm32l4x.c | 123 +++++++++++++++++++++++++++++++++++++++++------
2 files changed, 116 insertions(+), 15 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2021-08-26 06:17:03
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 1bce8d3d80490d66b56c2283e3ffee81a655a80a (commit)
from 76ba25a8a570d5e465e9ed3afdd36cf837fcb6a1 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 1bce8d3d80490d66b56c2283e3ffee81a655a80a
Author: Tarek BOCHKATI <tar...@gm...>
Date: Thu Jul 29 10:35:26 2021 +0100
flash/stm32l4x: do not report bank mode before probing [FIX]
in line 1391, get_stm32l4_bank_type_str(bank) will always output the same
value "Flash single" since the variable stm32l4_info->dual_bank_mode is false
by default, stm32l4_info->dual_bank_mode will be set correctly afterward
in the switch case at line 1467
thus the need to remove the usage of get_stm32l4_bank_type_str(bank) before
stm32l4_info->dual_bank_mode initialization.
Fixes: 64c2e03b23d9 ("flash/nor: improved API of flash_driver.info & fixed buffer overruns")
Change-Id: Ia8dc7e144e0ded6143682eb514c247f27859ff81
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6411
Reviewed-by: Oleksij Rempel <li...@re...>
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index d770cdfa5..5287ff6b3 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -1387,9 +1387,8 @@ static int stm32l4_probe(struct flash_bank *bank)
const char *rev_str = get_stm32l4_rev_str(bank);
const uint16_t rev_id = stm32l4_info->idcode >> 16;
- LOG_INFO("device idcode = 0x%08" PRIx32 " (%s - Rev %s : 0x%04x - %s-bank)",
- stm32l4_info->idcode, part_info->device_str, rev_str, rev_id,
- get_stm32l4_bank_type_str(bank));
+ LOG_INFO("device idcode = 0x%08" PRIx32 " (%s - Rev %s : 0x%04x)",
+ stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
stm32l4_info->flash_regs = stm32l4_info->part_info->default_flash_regs;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32l4x.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2021-08-25 03:48:16
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 76ba25a8a570d5e465e9ed3afdd36cf837fcb6a1 (commit)
from 3f1c15d2a718c9d417c859172f2b1736a769d822 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 76ba25a8a570d5e465e9ed3afdd36cf837fcb6a1
Author: Oleksij Rempel <o.r...@pe...>
Date: Sun Mar 14 18:19:06 2021 +0100
tcl: add lattice ECP5 family support
Add support for ECP5 FPGA targets and board based on this chips:
Radiona ULX3S and Lambdaconcept ECPIX-5
Change-Id: I932fc6e2458cda7d63ac21579acddea5b53410bc
Signed-off-by: Oleksij Rempel <o.r...@pe...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6112
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/contrib/60-openocd.rules b/contrib/60-openocd.rules
index 8e2fd4665..a6ff995e1 100644
--- a/contrib/60-openocd.rules
+++ b/contrib/60-openocd.rules
@@ -24,6 +24,8 @@ ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6011", MODE="660", GROUP="plugdev",
# Original FT232H VID:PID
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6014", MODE="660", GROUP="plugdev", TAG+="uaccess"
+# Original FT231XQ VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015", MODE="660", GROUP="plugdev", TAG+="uaccess"
# DISTORTEC JTAG-lock-pick Tiny 2
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="8220", MODE="660", GROUP="plugdev", TAG+="uaccess"
diff --git a/tcl/board/lambdaconcept_ecpix-5.cfg b/tcl/board/lambdaconcept_ecpix-5.cfg
new file mode 100644
index 000000000..19b9c1cb4
--- /dev/null
+++ b/tcl/board/lambdaconcept_ecpix-5.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# LambdaConcept ECPIX-5
+# http://docs.lambdaconcept.com/ecpix-5/
+# Currently there are following board variants:
+# ECPIX-5 45F - LFE5UM5G-45F
+# ECPIX-5 85F - LFE5UM5G-85F
+#
+# This boards have two JTAG interfaces:
+# - CN4, micro USB port connected to FT2232HQ chip:
+# ADBUS0 TCK
+# ADBUS1 TDI
+# ADBUS2 TDO
+# ADBUS3 TMS
+# BDBUS0 UART_TXD
+# BDBUS1 UART_RXD
+# This interface should be used with following config:
+# interface/ftdi/lambdaconcept_ecpix-5.cfg
+# - CN3, 6 pin connector
+# See schematics for more details:
+# http://docs.lambdaconcept.com/ecpix-5/_static/resources/SCH_ECPIX-5_R02.PDF
+#
+# No reset lines are implemented. So it is not possible to remote reset the FPGA
+# by using any of this interfaces
+
+source [find interface/ftdi/lambdaconcept_ecpix-5.cfg]
+source [find fpga/lattice_ecp5.cfg]
diff --git a/tcl/board/radiona_ulx3s.cfg b/tcl/board/radiona_ulx3s.cfg
new file mode 100644
index 000000000..eb9b02719
--- /dev/null
+++ b/tcl/board/radiona_ulx3s.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Radiona ULX3S
+# https://radiona.org/ulx3s/
+# Currently there are following board variants:
+# CS-ULX3S-01 - LFE5U 12F
+# CS-ULX3S-02 - LFE5U 45F
+# CS-ULX3S-03 - LFE5U 85F
+#
+# two JTAG interfaces:
+# - US1, micro USB port connected to FT231XQ
+# This interface should be used with following config:
+# interface/ft232r/radiona_ulx3s.cfg
+# - J4, 6 pin connector
+#
+# Both of this interfaces share the JTAG lines (TDI, TMS, TCK, TDO) between
+# Lattice ECP5 FPGA chip and ESP32 WiFi controller.
+# Note: TRST_N of the ESP32 is pulled up by default and can be pulled down over
+# J3 interface.
+# See schematics for more information:
+# https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf
+# https://github.com/emard/ulx3s/blob/master/doc/schematics_v314.pdf
+# https://github.com/emard/ulx3s/blob/master/doc/schematics_v315.pdf
+# https://github.com/emard/ulx3s/blob/master/doc/schematics_v316.pdf
+
+source [find interface/ft232r/radiona_ulx3s.cfg]
+source [find fpga/lattice_ecp5.cfg]
diff --git a/tcl/fpga/lattice_ecp5.cfg b/tcl/fpga/lattice_ecp5.cfg
new file mode 100644
index 000000000..a94ada740
--- /dev/null
+++ b/tcl/fpga/lattice_ecp5.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $_CHIPNAME
+} else {
+ set _CHIPNAME ecp5
+}
+
+# Lattice ECP5 family
+# TAP IDs are extracted from BSDL files found on this page:
+# https://www.latticesemi.com/Products/FPGAandCPLD/ECP5
+#
+# 0x01111043 - LAE5UM_25F/LFE5UM_25F
+# 0x01112043 - LAE5UM_45F/LFE5UM_45F
+# 0x01113043 - LAE5UM_85F/LFE5UM_85
+# 0x21111043 - LFE5U_12F
+# 0x41111043 - LFE5U_25F
+# 0x41112043 - LFE5U_45F
+# 0x41113043 - LFE5U_85F
+# 0x81111043 - LFE5UM5G-25
+# 0x81112043 - LFE5UM5G-45
+# 0x81113043 - LFE5UM5G-85
+
+jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
+ -expected-id 0x01111043 -expected-id 0x01112043 -expected-id 0x01113043 \
+ -expected-id 0x21111043 -expected-id 0x41111043 -expected-id 0x41112043 \
+ -expected-id 0x41113043 -expected-id 0x81111043 -expected-id 0x81112043 \
+ -expected-id 0x81113043
diff --git a/tcl/interface/ft232r/radiona_ulx3s.cfg b/tcl/interface/ft232r/radiona_ulx3s.cfg
new file mode 100644
index 000000000..424777e9e
--- /dev/null
+++ b/tcl/interface/ft232r/radiona_ulx3s.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# This adapter is integrated in to Radiona ULX3S board:
+# board/radiona_ulx3s.cfg
+# See schematics for the ft232r layout:
+# https://github.com/emard/ulx3s/blob/master/doc/schematics_v316.pdf
+
+adapter driver ft232r
+adapter speed 1000
+ft232r_vid_pid 0x0403 0x6015
+ft232r_tck_num DSR
+ft232r_tms_num DCD
+ft232r_tdi_num RI
+ft232r_tdo_num CTS
+ft232r_trst_num RTS
+ft232r_srst_num DTR
diff --git a/tcl/interface/ftdi/lambdaconcept_ecpix-5.cfg b/tcl/interface/ftdi/lambdaconcept_ecpix-5.cfg
new file mode 100644
index 000000000..b61caff64
--- /dev/null
+++ b/tcl/interface/ftdi/lambdaconcept_ecpix-5.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# This adapter is integrated in to LambdaConcept ECPIX-5 board:
+# interface/ftdi/lambdaconcept_ecpix-5.cfg
+# See schematics for the ftdi layout:
+# http://docs.lambdaconcept.com/ecpix-5/_static/resources/SCH_ECPIX-5_R02.PDF
+
+adapter driver ftdi
+adapter speed 10000
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0xfff8 0xfffb
+transport select jtag
-----------------------------------------------------------------------
Summary of changes:
contrib/60-openocd.rules | 2 ++
tcl/board/lambdaconcept_ecpix-5.cfg | 27 +++++++++++++++++++++++++++
tcl/board/radiona_ulx3s.cfg | 27 +++++++++++++++++++++++++++
tcl/fpga/lattice_ecp5.cfg | 28 ++++++++++++++++++++++++++++
tcl/interface/ft232r/radiona_ulx3s.cfg | 16 ++++++++++++++++
tcl/interface/ftdi/lambdaconcept_ecpix-5.cfg | 14 ++++++++++++++
6 files changed, 114 insertions(+)
create mode 100644 tcl/board/lambdaconcept_ecpix-5.cfg
create mode 100644 tcl/board/radiona_ulx3s.cfg
create mode 100644 tcl/fpga/lattice_ecp5.cfg
create mode 100644 tcl/interface/ft232r/radiona_ulx3s.cfg
create mode 100644 tcl/interface/ftdi/lambdaconcept_ecpix-5.cfg
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From: OpenOCD-Gerrit <ope...@us...> - 2021-08-22 20:28:22
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generated because a ref change was pushed to the repository containing
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commit 3f1c15d2a718c9d417c859172f2b1736a769d822
Author: root <aca...@fr...>
Date: Thu Jun 3 11:37:37 2021 +0200
target/adi_v5_jtag: Add support for 8-bit IR JTAG-DP
As per Arm Debug Interface Architecture Specification (ADIv5.0 to
ADIv5.2), B3.3.1, the JTAG-DP as an IR length of 4 or 8 bits
depending on the ARM implementation. The current code
only support 4-bit and this patch extends the support to 8-bit IR.
Not tested back yet on a 4-bit target.
Change-Id: Ie4f875dc336caf014c6cfced57574b54d0970623
Signed-off-by: Antoine C. <aca...@fr...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6285
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index 998c51cfb..be625807c 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -43,10 +43,10 @@
/*#define DEBUG_WAIT*/
/* JTAG instructions/registers for JTAG-DP and SWJ-DP */
-#define JTAG_DP_ABORT 0x8
-#define JTAG_DP_DPACC 0xA
-#define JTAG_DP_APACC 0xB
-#define JTAG_DP_IDCODE 0xE
+#define JTAG_DP_ABORT 0xF8
+#define JTAG_DP_DPACC 0xFA
+#define JTAG_DP_APACC 0xFB
+#define JTAG_DP_IDCODE 0xFE
/* three-bit ACK values for DPACC and APACC reads */
#define JTAG_ACK_OK_FAULT 0x2
-----------------------------------------------------------------------
Summary of changes:
src/target/adi_v5_jtag.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-08-22 20:27:03
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commit 347b88a3e1997566dc44dae118de8252138833ff
Author: Antonio Borneo <bor...@gm...>
Date: Wed Aug 4 17:50:02 2021 +0200
cortex_a: use the ap number specified at target create
Current implementation ignores the flag '-ap-num' provided to
command 'target create' and searches for the first AP of APB type.
If specified, use the ap number.
Change-Id: If1ac12345220d14a4a60515efe46dc2a2eac079a
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6413
Tested-by: jenkins
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 8ef196e34..b1f22067f 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2886,16 +2886,21 @@ static int cortex_a_examine_first(struct target *target)
struct cortex_a_common *cortex_a = target_to_cortex_a(target);
struct armv7a_common *armv7a = &cortex_a->armv7a_common;
struct adiv5_dap *swjdp = armv7a->arm.dap;
+ struct adiv5_private_config *pc = target->private_config;
int i;
int retval = ERROR_OK;
uint32_t didr, cpuid, dbg_osreg, dbg_idpfr1;
- /* Search for the APB-AP - it is needed for access to debug registers */
- retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
- if (retval != ERROR_OK) {
- LOG_ERROR("Could not find APB-AP for debug access");
- return retval;
+ if (pc->ap_num == DP_APSEL_INVALID) {
+ /* Search for the APB-AP - it is needed for access to debug registers */
+ retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Could not find APB-AP for debug access");
+ return retval;
+ }
+ } else {
+ armv7a->debug_ap = dap_ap(swjdp, pc->ap_num);
}
retval = mem_ap_init(armv7a->debug_ap);
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_a.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-08-22 20:26:29
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commit 7a61a006decf828f0f75e0602cc17d6efb897f57
Author: Antonio Borneo <bor...@gm...>
Date: Sun Aug 8 13:51:33 2021 +0200
jep106: use packed jedec manufacturer code
JEP106 encodes JEDEC-assigned manufacture code as:
a) a sequence of zero or more escape codes 0x7f;
b) an odd-parity bit of the next 7 bits;
c) 7 bits.
The same code is often represented as a single value composed by
the logical OR between:
- the number of escape codes in a), shifted left by 7 positions;
- the 7 bits in c).
This is the preferred packed representation used by this change.
Currently there are only two uses of JEP106 in openocd to get the
manufacturer name:
- to decode the JTAG IDCODE of each TAP, where the JEP106 code is
already packed as in the preferred representation above in bits
IDCODE[11:1];
- to decode the ARM CoreSight PIDR register, where the JEP106 code
is split in 3 parts:
= PIDR3[3:0], corresponding to bits [10:7] of the packed code;
= PIDR2[2:0], corresponding to bits [6:4] of the packed code;
= PIDR1[7:4], corresponding to bits [3:0] of the packed code.
Wrap the existing JEP106 decode function in a simpler API using
the packed code.
Simplify the callers by skipping the bit unpacking.
Change the manufacturer code in CoreSight table dap_partnums[] to
match the packed representation, by removing the always-one bit 7
erroneously taken from PIDR bit JEDEC and included in the former
table.
Change-Id: I63eb4da9e6801fab25e330f1f6b792d2fd619493
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6418
Tested-by: jenkins
diff --git a/src/helper/jep106.c b/src/helper/jep106.c
index 33dc61c91..5cf769aab 100644
--- a/src/helper/jep106.c
+++ b/src/helper/jep106.c
@@ -27,7 +27,7 @@ static const char * const jep106[][126] = {
#include "jep106.inc"
};
-const char *jep106_manufacturer(unsigned bank, unsigned id)
+const char *jep106_table_manufacturer(unsigned int bank, unsigned int id)
{
if (id < 1 || id > 126) {
LOG_DEBUG("BUG: Caller passed out-of-range JEP106 ID!");
diff --git a/src/helper/jep106.h b/src/helper/jep106.h
index 08445803e..61b177a2f 100644
--- a/src/helper/jep106.h
+++ b/src/helper/jep106.h
@@ -27,6 +27,11 @@
* manufacturer associated with bank and id, or one of the strings
* "<invalid>" and "<unknown>".
*/
-const char *jep106_manufacturer(unsigned bank, unsigned id);
+const char *jep106_table_manufacturer(unsigned int bank, unsigned int id);
+
+static inline const char *jep106_manufacturer(unsigned int manufacturer)
+{
+ return jep106_table_manufacturer(manufacturer >> 7, manufacturer & 0x7f);
+}
#endif /* OPENOCD_HELPER_JEP106_H */
diff --git a/src/jtag/core.c b/src/jtag/core.c
index 13366e01b..7da2a6c35 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -1072,8 +1072,6 @@ void jtag_sleep(uint32_t us)
#define JTAG_MAX_AUTO_TAPS 20
-#define EXTRACT_JEP106_BANK(X) (((X) & 0xf00) >> 8)
-#define EXTRACT_JEP106_ID(X) (((X) & 0xfe) >> 1)
#define EXTRACT_MFG(X) (((X) & 0xffe) >> 1)
#define EXTRACT_PART(X) (((X) & 0xffff000) >> 12)
#define EXTRACT_VER(X) (((X) & 0xf0000000) >> 28)
@@ -1141,7 +1139,7 @@ static void jtag_examine_chain_display(enum log_levels level, const char *msg,
name, msg,
(unsigned int)idcode,
(unsigned int)EXTRACT_MFG(idcode),
- jep106_manufacturer(EXTRACT_JEP106_BANK(idcode), EXTRACT_JEP106_ID(idcode)),
+ jep106_manufacturer(EXTRACT_MFG(idcode)),
(unsigned int)EXTRACT_PART(idcode),
(unsigned int)EXTRACT_VER(idcode));
}
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 65a8bc4c7..c29554239 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1123,7 +1123,7 @@ static int dap_read_part_id(struct adiv5_ap *ap, target_addr_t component_base, u
#define ANY_ID 0x1000
-#define ARM_ID 0x4BB
+#define ARM_ID 0x23B
static const struct {
uint16_t designer_id;
@@ -1216,22 +1216,22 @@ static const struct {
{ ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
{ ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
{ ARM_ID, 0xd0b, "Cortex-A76 Debug", "(Debug Unit)", },
- { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
- { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
- { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
- { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
- { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
- { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
- { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
- { 0x1bf, 0x100, "Brahma-B53 Debug", "(Debug Unit)", },
- { 0x1bf, 0x9d3, "Brahma-B53 PMU", "(Performance Monitor Unit)", },
- { 0x1bf, 0x4a1, "Brahma-B53 ROM", "(ROM Table)", },
- { 0x1bf, 0x721, "Brahma-B53 ROM", "(ROM Table)", },
- { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
- { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
- { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
- { 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", },
- { 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
+ { 0x017, 0x9af, "MSP432 ROM", "(ROM Table)" },
+ { 0x01f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
+ { 0x041, 0x1db, "XMC4500 ROM", "(ROM Table)" },
+ { 0x041, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
+ { 0x041, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
+ { 0x065, 0x000, "SHARC+/Blackfin+", "", },
+ { 0x070, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
+ { 0x0bf, 0x100, "Brahma-B53 Debug", "(Debug Unit)", },
+ { 0x0bf, 0x9d3, "Brahma-B53 PMU", "(Performance Monitor Unit)", },
+ { 0x0bf, 0x4a1, "Brahma-B53 ROM", "(ROM Table)", },
+ { 0x0bf, 0x721, "Brahma-B53 ROM", "(ROM Table)", },
+ { 0x1eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
+ { 0x1eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
+ { 0x1eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
+ { 0x1eb, 0x302, "Denver Debug", "(Debug Unit)", },
+ { 0x1eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
/* legacy comment: 0x113: what? */
{ ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
{ ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
@@ -1276,12 +1276,12 @@ static int dap_rom_display(struct command_invocation *cmd,
uint8_t class = (cid >> 12) & 0xf;
uint16_t part_num = pid & 0xfff;
- uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
+ uint16_t designer_id = ((pid >> 32) & 0xf) << 7 | ((pid >> 12) & 0x7f);
- if (designer_id & 0x80) {
+ if (pid & 0x00080000) {
/* JEP106 code */
command_print(cmd, "\t\tDesigner is 0x%03" PRIx16 ", %s",
- designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
+ designer_id, jep106_manufacturer(designer_id));
} else {
/* Legacy ASCII ID, clear invalid bits */
designer_id &= 0x7f;
-----------------------------------------------------------------------
Summary of changes:
src/helper/jep106.c | 2 +-
src/helper/jep106.h | 7 ++++++-
src/jtag/core.c | 4 +---
src/target/arm_adi_v5.c | 40 ++++++++++++++++++++--------------------
4 files changed, 28 insertions(+), 25 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-08-22 20:25:45
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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commit 66175577e1f5b89470bafa1e613e10307996a3fb
Author: Antonio Borneo <bor...@gm...>
Date: Wed Aug 11 17:03:18 2021 +0200
arm_adi_v5: update coresight class names
Update the list of ARM coresight classes wrt to latest ARM
documentation.
Use c99 array designator to easily track changes in future.
Add a comment for the entry "OptimoDE DESS". It was added in 2009
by David Brownell, but Google cannot find any reference other than
this line in openocd code its associated commit. It should not be
an issue keeping it as is.
Change-Id: Ia3b646131ee68ca5263095c3a0aeaf75c004b324
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6431
Tested-by: jenkins
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 0c4b80ca1..65a8bc4c7 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -865,15 +865,30 @@ int dap_to_jtag(struct adiv5_dap *dap)
return dap_send_sequence(dap, SWD_TO_JTAG);
}
-/* CID interpretation -- see ARM IHI 0029B section 3
- * and ARM IHI 0031A table 13-3.
+/* CID interpretation -- see ARM IHI 0029E table B2-7
+ * and ARM IHI 0031E table D1-2.
+ *
+ * From 2009/11/25 commit 21378f58b604:
+ * "OptimoDE DESS" is ARM's semicustom DSPish stuff.
+ * Let's keep it as is, for the time being
*/
static const char *class_description[16] = {
- "Reserved", "ROM table", "Reserved", "Reserved",
- "Reserved", "Reserved", "Reserved", "Reserved",
- "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
- "Reserved", "OptimoDE DESS",
- "Generic IP component", "PrimeCell or System component"
+ [0x0] = "Generic verification component",
+ [0x1] = "ROM table",
+ [0x2] = "Reserved",
+ [0x3] = "Reserved",
+ [0x4] = "Reserved",
+ [0x5] = "Reserved",
+ [0x6] = "Reserved",
+ [0x7] = "Reserved",
+ [0x8] = "Reserved",
+ [0x9] = "CoreSight component",
+ [0xA] = "Reserved",
+ [0xB] = "Peripheral Test Block",
+ [0xC] = "Reserved",
+ [0xD] = "OptimoDE DESS", /* see above */
+ [0xE] = "Generic IP component",
+ [0xF] = "CoreLink, PrimeCell or System component",
};
static bool is_dap_cid_ok(uint32_t cid)
-----------------------------------------------------------------------
Summary of changes:
src/target/arm_adi_v5.c | 29 ++++++++++++++++++++++-------
1 file changed, 22 insertions(+), 7 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-08-22 20:25:14
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commit 6933dd0231f5b91a33996c1c013eb2459ffd2e87
Author: Antonio Borneo <bor...@gm...>
Date: Thu Aug 12 00:14:29 2021 +0200
command: log the command only when it is executed
In case of multi-word commands, the command dispatcher is nested
called at each word during command name parsing.
The improper position of the call to script_debug() causes the
command line to be logged once at each parsed word.
In the example of command "cpu arm disassemble 0" the full command
is logged three times for "cpu", "arm" and "disassemble":
Debug: 656617 61843 command.c:201 script_debug(): command - cpu arm disassemble 0
Debug: 656618 61843 command.c:201 script_debug(): command - cpu arm disassemble 0
Debug: 656619 61843 command.c:201 script_debug(): command - cpu arm disassemble 0
Call script_debug() only when the parsing is terminated and the
command handler is going to be executed.
Change-Id: Ide4cb01b3b38912e2e24b073c94a9560f92d30bb
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6436
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
diff --git a/src/helper/command.c b/src/helper/command.c
index 42cb8c71e..e5529d97f 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -954,8 +954,6 @@ static int exec_command(Jim_Interp *interp, struct command_context *cmd_ctx,
static int jim_command_dispatch(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
{
- script_debug(interp, argc, argv);
-
/* check subcommands */
if (argc > 1) {
char *s = alloc_printf("%s %s", Jim_GetString(argv[0], NULL), Jim_GetString(argv[1], NULL));
@@ -971,6 +969,8 @@ static int jim_command_dispatch(Jim_Interp *interp, int argc, Jim_Obj * const *a
Jim_DecrRefCount(interp, js);
}
+ script_debug(interp, argc, argv);
+
struct command *c = jim_to_command(interp);
if (!c->jim_handler && !c->handler) {
Jim_EvalObjPrefix(interp, Jim_NewStringObj(interp, "usage", -1), 1, argv);
-----------------------------------------------------------------------
Summary of changes:
src/helper/command.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
