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From: OpenOCD-Gerrit <ope...@us...> - 2021-11-20 14:42:04
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 8457a1be10d1463b40c020867ad4dc2513c93a4b (commit)
from 6441fe8d9d29d7720e1272e1a5b166535116d172 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 8457a1be10d1463b40c020867ad4dc2513c93a4b
Author: Tim Newsome <ti...@si...>
Date: Tue Oct 12 11:06:44 2021 -0700
target: Use target_addr_t for algorithm addresses.
Otherwise 64-bit addresses can't work.
Signed-off-by: Tim Newsome <ti...@si...>
Change-Id: Id9f92ff8a1602153cc06810bcf515a9d0a89c81b
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6662
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/target.c b/src/target/target.c
index 35e9b5332..ed6f655ea 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -839,7 +839,7 @@ static int target_soft_reset_halt(struct target *target)
int target_run_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_param,
- uint32_t entry_point, uint32_t exit_point,
+ target_addr_t entry_point, target_addr_t exit_point,
int timeout_ms, void *arch_info)
{
int retval = ERROR_FAIL;
@@ -880,7 +880,7 @@ done:
int target_start_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
- uint32_t entry_point, uint32_t exit_point,
+ target_addr_t entry_point, target_addr_t exit_point,
void *arch_info)
{
int retval = ERROR_FAIL;
@@ -924,7 +924,7 @@ done:
int target_wait_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
- uint32_t exit_point, int timeout_ms,
+ target_addr_t exit_point, int timeout_ms,
void *arch_info)
{
int retval = ERROR_FAIL;
diff --git a/src/target/target.h b/src/target/target.h
index 1e19434e4..99ec2be10 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -547,7 +547,7 @@ int target_step(struct target *target,
int target_run_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_param,
- uint32_t entry_point, uint32_t exit_point,
+ target_addr_t entry_point, target_addr_t exit_point,
int timeout_ms, void *arch_info);
/**
@@ -558,7 +558,7 @@ int target_run_algorithm(struct target *target,
int target_start_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
- uint32_t entry_point, uint32_t exit_point,
+ target_addr_t entry_point, target_addr_t exit_point,
void *arch_info);
/**
@@ -569,7 +569,7 @@ int target_start_algorithm(struct target *target,
int target_wait_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
- uint32_t exit_point, int timeout_ms,
+ target_addr_t exit_point, int timeout_ms,
void *arch_info);
/**
-----------------------------------------------------------------------
Summary of changes:
src/target/target.c | 6 +++---
src/target/target.h | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-11-20 14:40:30
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 6441fe8d9d29d7720e1272e1a5b166535116d172 (commit)
from f8bd2566a936c7909f2b602bba3c83cc833afaea (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 6441fe8d9d29d7720e1272e1a5b166535116d172
Author: Tim Newsome <ti...@si...>
Date: Tue Oct 5 10:03:19 2021 -0700
riscv: Clear type 6 triggers on connecting.
I missed this when I first add mcontrol6 support.
https://github.com/riscv/riscv-openocd/pull/648
Change-Id: I1a2706c7ea3a6757ed5083091cd2c764a8b0267c
Signed-off-by: Tim Newsome <ti...@si...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6684
Tested-by: jenkins
Reviewed-by: Jan Matyas <ma...@co...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 084939e11..407b7e279 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -3569,6 +3569,10 @@ int riscv_enumerate_triggers(struct target *target)
if (tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
riscv_set_register(target, GDB_REGNO_TDATA1, 0);
break;
+ case 6:
+ if (tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
+ riscv_set_register(target, GDB_REGNO_TDATA1, 0);
+ break;
}
}
-----------------------------------------------------------------------
Summary of changes:
src/target/riscv/riscv.c | 4 ++++
1 file changed, 4 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-11-20 14:39:42
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via f8bd2566a936c7909f2b602bba3c83cc833afaea (commit)
from ee670f9dcee606141112a7552d8409788f3caf7f (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit f8bd2566a936c7909f2b602bba3c83cc833afaea
Author: Jan Matyas <501...@us...>
Date: Thu Nov 4 17:48:23 2021 +0100
riscv: Regenerated debug_defines.h and encoding.h
The main intention is to get access to some of the CSRs
that were so far unknown to OpenOCD (tinfo, mcountinhibit, ...).
https://github.com/riscv/riscv-openocd/pull/659
Signed-off-by: Tim Newsome <ti...@si...>
Change-Id: I824fdb558d5c1f73432b0f56f3b0b4d865eceeba
Reviewed-on: https://review.openocd.org/c/openocd/+/6682
Tested-by: jenkins
Reviewed-by: Jan Matyas <ma...@co...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/riscv/debug_defines.h b/src/target/riscv/debug_defines.h
index b5104d530..5c9eef4ea 100644
--- a/src/target/riscv/debug_defines.h
+++ b/src/target/riscv/debug_defines.h
@@ -1,6 +1,6 @@
/*
* This file is auto-generated by running 'make debug_defines.h' in
- * https://github.com/riscv/riscv-debug-spec/ (63c985f)
+ * https://github.com/riscv/riscv-debug-spec/ (3dfe4f7)
* License: Creative Commons Attribution 4.0 International Public License (CC BY 4.0)
*/
@@ -266,7 +266,7 @@
*
* 1: An {\tt ebreak} instruction was executed. (priority 3)
*
- * 2: The Trigger Module caused a breakpoint exception. (priority 4)
+ * 2: A Trigger Module trigger fired with action=0. (priority 4)
*
* 3: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq.
* (priority 1)
@@ -461,7 +461,7 @@
*
* \FcsrTcontrolMpte and \FcsrTcontrolMte provide one solution to a problem
* regarding triggers with action=0 firing in M-mode trap handlers. See
- * Section~\ref{sec:mmtrigger} for more details.
+ * Section~\ref{sec:nativetrigger} for more details.
*
* When a trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of
* \FcsrTcontrolMte.
@@ -811,8 +811,9 @@
#define CSR_MCONTROL6_VU_LENGTH 1
#define CSR_MCONTROL6_VU (0x1ULL << CSR_MCONTROL6_VU_OFFSET)
/*
- * If this bit is implemented, the hardware sets it when this
- * trigger matches. The trigger's user can set or clear it at any
+ * If this bit is implemented then it must become set when this
+ * trigger fires and may become set when this trigger matches.
+ * The trigger's user can set or clear it at any
* time. It is used to determine which
* trigger(s) matched. If the bit is not implemented, it is always 0
* and writing it has no effect.
@@ -1237,7 +1238,8 @@
#define CSR_ETRIGGER_VU (0x1ULL << CSR_ETRIGGER_VU_OFFSET)
/*
* When set, non-maskable interrupts cause this
- * trigger to fire, regardless of the values of \FcsrEtriggerM, \FcsrEtriggerS, and \FcsrEtriggerU.
+ * trigger to fire, regardless of the values of \FcsrEtriggerM,
+ * \FcsrEtriggerS, \FcsrEtriggerU, \FcsrEtriggerVs, and \FcsrEtriggerVu.
*/
#define CSR_ETRIGGER_NMI_OFFSET 10
#define CSR_ETRIGGER_NMI_LENGTH 1
@@ -1361,10 +1363,15 @@
* 1: This trigger will only match if the low bits of
* \RcsrScontext equal \FcsrTextraThirtytwoSvalue.
*
- * 2: This trigger will only match if the currently active ASID
- * value, from either \Rsatp or \Rvsatp,
- * equals the lower ASIDMAX (defined in the Privileged Spec) bits of
+ * 2: This trigger will only match if:
+ * \begin{itemize}[noitemsep,nolistsep]
+ * \item the mode is VS-mode or VU-mode and ASID in \Rvsatp
+ * equals the lower ASIDMAX (defined in the Privileged Spec) bits
+ * of \FcsrTextraThirtytwoSvalue.
+ * \item in all other modes, ASID in \Rsatp equals the lower
+ * ASIDMAX (defined in the Privileged Spec) bits of
* \FcsrTextraThirtytwoSvalue.
+ * \end{itemize}
*
* This field should be tied to 0 when S-mode is not supported.
*/
diff --git a/src/target/riscv/encoding.h b/src/target/riscv/encoding.h
index 4a035e288..4445f0bd2 100644
--- a/src/target/riscv/encoding.h
+++ b/src/target/riscv/encoding.h
@@ -1,6 +1,6 @@
/*
* This file is auto-generated by running 'make ../riscv-openocd/src/target/riscv/encoding.h' in
- * https://github.com/riscv/riscv-opcodes (876ee63)
+ * https://github.com/riscv/riscv-opcodes (6c34f60)
*/
/* See LICENSE for license details. */
@@ -14,7 +14,7 @@
#define MSTATUS_MIE 0x00000008
#define MSTATUS_UPIE 0x00000010
#define MSTATUS_SPIE 0x00000020
-#define MSTATUS_HPIE 0x00000040
+#define MSTATUS_UBE 0x00000040
#define MSTATUS_MPIE 0x00000080
#define MSTATUS_SPP 0x00000100
#define MSTATUS_VS 0x00000600
@@ -30,14 +30,22 @@
#define MSTATUS32_SD 0x80000000
#define MSTATUS_UXL 0x0000000300000000
#define MSTATUS_SXL 0x0000000C00000000
+#define MSTATUS_SBE 0x0000001000000000
+#define MSTATUS_MBE 0x0000002000000000
#define MSTATUS_GVA 0x0000004000000000
#define MSTATUS_MPV 0x0000008000000000
#define MSTATUS64_SD 0x8000000000000000
+#define MSTATUSH_SBE 0x00000010
+#define MSTATUSH_MBE 0x00000020
+#define MSTATUSH_GVA 0x00000040
+#define MSTATUSH_MPV 0x00000080
+
#define SSTATUS_UIE 0x00000001
#define SSTATUS_SIE 0x00000002
#define SSTATUS_UPIE 0x00000010
#define SSTATUS_SPIE 0x00000020
+#define SSTATUS_UBE 0x00000040
#define SSTATUS_SPP 0x00000100
#define SSTATUS_VS 0x00000600
#define SSTATUS_FS 0x00006000
@@ -48,10 +56,6 @@
#define SSTATUS_UXL 0x0000000300000000
#define SSTATUS64_SD 0x8000000000000000
-#define SSTATUS_VS_MASK (SSTATUS_SIE | SSTATUS_SPIE | \
- SSTATUS_SPP | SSTATUS_SUM | \
- SSTATUS_MXR | SSTATUS_UXL)
-
#define HSTATUS_VSXL 0x300000000
#define HSTATUS_VTSR 0x00400000
#define HSTATUS_VTW 0x00200000
@@ -205,12 +209,6 @@
#define IRQ_COP 12
#define IRQ_HOST 13
-#define DEFAULT_RSTVEC 0x00001000
-#define CLINT_BASE 0x02000000
-#define CLINT_SIZE 0x000c0000
-#define EXT_IO_BASE 0x40000000
-#define DRAM_BASE 0x80000000
-
/* page table entry (PTE) fields */
#define PTE_V 0x001 /* Valid */
#define PTE_R 0x002 /* Read */
@@ -221,6 +219,10 @@
#define PTE_A 0x040 /* Accessed */
#define PTE_D 0x080 /* Dirty */
#define PTE_SOFT 0x300 /* Reserved for Software */
+#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */
+#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */
+#define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */
+#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */
#define PTE_PPN_SHIFT 10
@@ -347,18 +349,12 @@
#define MASK_AUIPC 0x7f
#define MATCH_ADDI 0x13
#define MASK_ADDI 0x707f
-#define MATCH_SLLI 0x1013
-#define MASK_SLLI 0xfc00707f
#define MATCH_SLTI 0x2013
#define MASK_SLTI 0x707f
#define MATCH_SLTIU 0x3013
#define MASK_SLTIU 0x707f
#define MATCH_XORI 0x4013
#define MASK_XORI 0x707f
-#define MATCH_SRLI 0x5013
-#define MASK_SRLI 0xfc00707f
-#define MATCH_SRAI 0x40005013
-#define MASK_SRAI 0xfc00707f
#define MATCH_ORI 0x6013
#define MASK_ORI 0x707f
#define MATCH_ANDI 0x7013
@@ -427,6 +423,12 @@
#define MASK_LWU 0x707f
#define MATCH_SD 0x3023
#define MASK_SD 0x707f
+#define MATCH_SLLI 0x1013
+#define MASK_SLLI 0xfc00707f
+#define MATCH_SRLI 0x5013
+#define MASK_SRLI 0xfc00707f
+#define MATCH_SRAI 0x40005013
+#define MASK_SRAI 0xfc00707f
#define MATCH_MUL 0x2000033
#define MASK_MUL 0xfe00707f
#define MATCH_MULH 0x2001033
@@ -715,12 +717,216 @@
#define MASK_FCVT_Q_L 0xfff0007f
#define MATCH_FCVT_Q_LU 0xd6300053
#define MASK_FCVT_Q_LU 0xfff0007f
+#define MATCH_ANDN 0x40007033
+#define MASK_ANDN 0xfe00707f
+#define MATCH_ORN 0x40006033
+#define MASK_ORN 0xfe00707f
+#define MATCH_XNOR 0x40004033
+#define MASK_XNOR 0xfe00707f
+#define MATCH_SLO 0x20001033
+#define MASK_SLO 0xfe00707f
+#define MATCH_SRO 0x20005033
+#define MASK_SRO 0xfe00707f
+#define MATCH_ROL 0x60001033
+#define MASK_ROL 0xfe00707f
+#define MATCH_ROR 0x60005033
+#define MASK_ROR 0xfe00707f
+#define MATCH_BCLR 0x48001033
+#define MASK_BCLR 0xfe00707f
+#define MATCH_BSET 0x28001033
+#define MASK_BSET 0xfe00707f
+#define MATCH_BINV 0x68001033
+#define MASK_BINV 0xfe00707f
+#define MATCH_BEXT 0x48005033
+#define MASK_BEXT 0xfe00707f
+#define MATCH_GORC 0x28005033
+#define MASK_GORC 0xfe00707f
+#define MATCH_GREV 0x68005033
+#define MASK_GREV 0xfe00707f
+#define MATCH_SLOI 0x20001013
+#define MASK_SLOI 0xfc00707f
+#define MATCH_SROI 0x20005013
+#define MASK_SROI 0xfc00707f
+#define MATCH_RORI 0x60005013
+#define MASK_RORI 0xfc00707f
+#define MATCH_BCLRI 0x48001013
+#define MASK_BCLRI 0xfc00707f
+#define MATCH_BSETI 0x28001013
+#define MASK_BSETI 0xfc00707f
+#define MATCH_BINVI 0x68001013
+#define MASK_BINVI 0xfc00707f
+#define MATCH_BEXTI 0x48005013
+#define MASK_BEXTI 0xfc00707f
+#define MATCH_GORCI 0x28005013
+#define MASK_GORCI 0xfc00707f
+#define MATCH_GREVI 0x68005013
+#define MASK_GREVI 0xfc00707f
+#define MATCH_CMIX 0x6001033
+#define MASK_CMIX 0x600707f
+#define MATCH_CMOV 0x6005033
+#define MASK_CMOV 0x600707f
+#define MATCH_FSL 0x4001033
+#define MASK_FSL 0x600707f
+#define MATCH_FSR 0x4005033
+#define MASK_FSR 0x600707f
+#define MATCH_FSRI 0x4005013
+#define MASK_FSRI 0x400707f
+#define MATCH_CLZ 0x60001013
+#define MASK_CLZ 0xfff0707f
+#define MATCH_CTZ 0x60101013
+#define MASK_CTZ 0xfff0707f
+#define MATCH_CPOP 0x60201013
+#define MASK_CPOP 0xfff0707f
+#define MATCH_SEXT_B 0x60401013
+#define MASK_SEXT_B 0xfff0707f
+#define MATCH_SEXT_H 0x60501013
+#define MASK_SEXT_H 0xfff0707f
+#define MATCH_CRC32_B 0x61001013
+#define MASK_CRC32_B 0xfff0707f
+#define MATCH_CRC32_H 0x61101013
+#define MASK_CRC32_H 0xfff0707f
+#define MATCH_CRC32_W 0x61201013
+#define MASK_CRC32_W 0xfff0707f
+#define MATCH_CRC32C_B 0x61801013
+#define MASK_CRC32C_B 0xfff0707f
+#define MATCH_CRC32C_H 0x61901013
+#define MASK_CRC32C_H 0xfff0707f
+#define MATCH_CRC32C_W 0x61a01013
+#define MASK_CRC32C_W 0xfff0707f
+#define MATCH_SH1ADD 0x20002033
+#define MASK_SH1ADD 0xfe00707f
+#define MATCH_SH2ADD 0x20004033
+#define MASK_SH2ADD 0xfe00707f
+#define MATCH_SH3ADD 0x20006033
+#define MASK_SH3ADD 0xfe00707f
+#define MATCH_CLMUL 0xa001033
+#define MASK_CLMUL 0xfe00707f
+#define MATCH_CLMULR 0xa002033
+#define MASK_CLMULR 0xfe00707f
+#define MATCH_CLMULH 0xa003033
+#define MASK_CLMULH 0xfe00707f
+#define MATCH_MIN 0xa004033
+#define MASK_MIN 0xfe00707f
+#define MATCH_MINU 0xa005033
+#define MASK_MINU 0xfe00707f
+#define MATCH_MAX 0xa006033
+#define MASK_MAX 0xfe00707f
+#define MATCH_MAXU 0xa007033
+#define MASK_MAXU 0xfe00707f
+#define MATCH_SHFL 0x8001033
+#define MASK_SHFL 0xfe00707f
+#define MATCH_UNSHFL 0x8005033
+#define MASK_UNSHFL 0xfe00707f
+#define MATCH_BCOMPRESS 0x8006033
+#define MASK_BCOMPRESS 0xfe00707f
+#define MATCH_BDECOMPRESS 0x48006033
+#define MASK_BDECOMPRESS 0xfe00707f
+#define MATCH_PACK 0x8004033
+#define MASK_PACK 0xfe00707f
+#define MATCH_PACKU 0x48004033
+#define MASK_PACKU 0xfe00707f
+#define MATCH_PACKH 0x8007033
+#define MASK_PACKH 0xfe00707f
+#define MATCH_BFP 0x48007033
+#define MASK_BFP 0xfe00707f
+#define MATCH_SHFLI 0x8001013
+#define MASK_SHFLI 0xfe00707f
+#define MATCH_UNSHFLI 0x8005013
+#define MASK_UNSHFLI 0xfe00707f
+#define MATCH_XPERM4 0x28002033
+#define MASK_XPERM4 0xfe00707f
+#define MATCH_XPERM8 0x28004033
+#define MASK_XPERM8 0xfe00707f
+#define MATCH_XPERM16 0x28006033
+#define MASK_XPERM16 0xfe00707f
+#define MATCH_BMATFLIP 0x60301013
+#define MASK_BMATFLIP 0xfff0707f
+#define MATCH_CRC32_D 0x61301013
+#define MASK_CRC32_D 0xfff0707f
+#define MATCH_CRC32C_D 0x61b01013
+#define MASK_CRC32C_D 0xfff0707f
+#define MATCH_BMATOR 0x8003033
+#define MASK_BMATOR 0xfe00707f
+#define MATCH_BMATXOR 0x48003033
+#define MASK_BMATXOR 0xfe00707f
+#define MATCH_SLLI_UW 0x800101b
+#define MASK_SLLI_UW 0xfc00707f
+#define MATCH_ADD_UW 0x800003b
+#define MASK_ADD_UW 0xfe00707f
+#define MATCH_SLOW 0x2000103b
+#define MASK_SLOW 0xfe00707f
+#define MATCH_SROW 0x2000503b
+#define MASK_SROW 0xfe00707f
+#define MATCH_ROLW 0x6000103b
+#define MASK_ROLW 0xfe00707f
+#define MATCH_RORW 0x6000503b
+#define MASK_RORW 0xfe00707f
+#define MATCH_SBCLRW 0x4800103b
+#define MASK_SBCLRW 0xfe00707f
+#define MATCH_SBSETW 0x2800103b
+#define MASK_SBSETW 0xfe00707f
+#define MATCH_SBINVW 0x6800103b
+#define MASK_SBINVW 0xfe00707f
+#define MATCH_SBEXTW 0x4800503b
+#define MASK_SBEXTW 0xfe00707f
+#define MATCH_GORCW 0x2800503b
+#define MASK_GORCW 0xfe00707f
+#define MATCH_GREVW 0x6800503b
+#define MASK_GREVW 0xfe00707f
+#define MATCH_SLOIW 0x2000101b
+#define MASK_SLOIW 0xfe00707f
+#define MATCH_SROIW 0x2000501b
+#define MASK_SROIW 0xfe00707f
+#define MATCH_RORIW 0x6000501b
+#define MASK_RORIW 0xfe00707f
+#define MATCH_SBCLRIW 0x4800101b
+#define MASK_SBCLRIW 0xfe00707f
+#define MATCH_SBSETIW 0x2800101b
+#define MASK_SBSETIW 0xfe00707f
+#define MATCH_SBINVIW 0x6800101b
+#define MASK_SBINVIW 0xfe00707f
+#define MATCH_GORCIW 0x2800501b
+#define MASK_GORCIW 0xfe00707f
+#define MATCH_GREVIW 0x6800501b
+#define MASK_GREVIW 0xfe00707f
+#define MATCH_FSLW 0x400103b
+#define MASK_FSLW 0x600707f
+#define MATCH_FSRW 0x400503b
+#define MASK_FSRW 0x600707f
+#define MATCH_FSRIW 0x400501b
+#define MASK_FSRIW 0x600707f
+#define MATCH_CLZW 0x6000101b
+#define MASK_CLZW 0xfff0707f
+#define MATCH_CTZW 0x6010101b
+#define MASK_CTZW 0xfff0707f
+#define MATCH_CPOPW 0x6020101b
+#define MASK_CPOPW 0xfff0707f
+#define MATCH_SH1ADD_UW 0x2000203b
+#define MASK_SH1ADD_UW 0xfe00707f
+#define MATCH_SH2ADD_UW 0x2000403b
+#define MASK_SH2ADD_UW 0xfe00707f
+#define MATCH_SH3ADD_UW 0x2000603b
+#define MASK_SH3ADD_UW 0xfe00707f
+#define MATCH_SHFLW 0x800103b
+#define MASK_SHFLW 0xfe00707f
+#define MATCH_UNSHFLW 0x800503b
+#define MASK_UNSHFLW 0xfe00707f
+#define MATCH_BCOMPRESSW 0x800603b
+#define MASK_BCOMPRESSW 0xfe00707f
+#define MATCH_BDECOMPRESSW 0x4800603b
+#define MASK_BDECOMPRESSW 0xfe00707f
+#define MATCH_PACKW 0x800403b
+#define MASK_PACKW 0xfe00707f
+#define MATCH_PACKUW 0x4800403b
+#define MASK_PACKUW 0xfe00707f
+#define MATCH_BFPW 0x4800703b
+#define MASK_BFPW 0xfe00707f
+#define MATCH_XPERM32 0x28000033
+#define MASK_XPERM32 0xfe00707f
#define MATCH_ECALL 0x73
#define MASK_ECALL 0xffffffff
#define MATCH_EBREAK 0x100073
#define MASK_EBREAK 0xffffffff
-#define MATCH_URET 0x200073
-#define MASK_URET 0xffffffff
#define MATCH_SRET 0x10200073
#define MASK_SRET 0xffffffff
#define MATCH_MRET 0x30200073
@@ -743,6 +949,146 @@
#define MASK_CSRRSI 0x707f
#define MATCH_CSRRCI 0x7073
#define MASK_CSRRCI 0x707f
+#define MATCH_SINVAL_VMA 0x16000073
+#define MASK_SINVAL_VMA 0xfe007fff
+#define MATCH_SFENCE_W_INVAL 0x18000073
+#define MASK_SFENCE_W_INVAL 0xffffffff
+#define MATCH_SFENCE_INVAL_IR 0x18100073
+#define MASK_SFENCE_INVAL_IR 0xffffffff
+#define MATCH_HINVAL_VVMA 0x36000073
+#define MASK_HINVAL_VVMA 0xfe007fff
+#define MATCH_HINVAL_GVMA 0x76000073
+#define MASK_HINVAL_GVMA 0xfe007fff
+#define MATCH_FADD_H 0x4000053
+#define MASK_FADD_H 0xfe00007f
+#define MATCH_FSUB_H 0xc000053
+#define MASK_FSUB_H 0xfe00007f
+#define MATCH_FMUL_H 0x14000053
+#define MASK_FMUL_H 0xfe00007f
+#define MATCH_FDIV_H 0x1c000053
+#define MASK_FDIV_H 0xfe00007f
+#define MATCH_FSGNJ_H 0x24000053
+#define MASK_FSGNJ_H 0xfe00707f
+#define MATCH_FSGNJN_H 0x24001053
+#define MASK_FSGNJN_H 0xfe00707f
+#define MATCH_FSGNJX_H 0x24002053
+#define MASK_FSGNJX_H 0xfe00707f
+#define MATCH_FMIN_H 0x2c000053
+#define MASK_FMIN_H 0xfe00707f
+#define MATCH_FMAX_H 0x2c001053
+#define MASK_FMAX_H 0xfe00707f
+#define MATCH_FCVT_H_S 0x44000053
+#define MASK_FCVT_H_S 0xfff0007f
+#define MATCH_FCVT_S_H 0x40200053
+#define MASK_FCVT_S_H 0xfff0007f
+#define MATCH_FSQRT_H 0x5c000053
+#define MASK_FSQRT_H 0xfff0007f
+#define MATCH_FLE_H 0xa4000053
+#define MASK_FLE_H 0xfe00707f
+#define MATCH_FLT_H 0xa4001053
+#define MASK_FLT_H 0xfe00707f
+#define MATCH_FEQ_H 0xa4002053
+#define MASK_FEQ_H 0xfe00707f
+#define MATCH_FCVT_W_H 0xc4000053
+#define MASK_FCVT_W_H 0xfff0007f
+#define MATCH_FCVT_WU_H 0xc4100053
+#define MASK_FCVT_WU_H 0xfff0007f
+#define MATCH_FMV_X_H 0xe4000053
+#define MASK_FMV_X_H 0xfff0707f
+#define MATCH_FCLASS_H 0xe4001053
+#define MASK_FCLASS_H 0xfff0707f
+#define MATCH_FCVT_H_W 0xd4000053
+#define MASK_FCVT_H_W 0xfff0007f
+#define MATCH_FCVT_H_WU 0xd4100053
+#define MASK_FCVT_H_WU 0xfff0007f
+#define MATCH_FMV_H_X 0xf4000053
+#define MASK_FMV_H_X 0xfff0707f
+#define MATCH_FLH 0x1007
+#define MASK_FLH 0x707f
+#define MATCH_FSH 0x1027
+#define MASK_FSH 0x707f
+#define MATCH_FMADD_H 0x4000043
+#define MASK_FMADD_H 0x600007f
+#define MATCH_FMSUB_H 0x4000047
+#define MASK_FMSUB_H 0x600007f
+#define MATCH_FNMSUB_H 0x400004b
+#define MASK_FNMSUB_H 0x600007f
+#define MATCH_FNMADD_H 0x400004f
+#define MASK_FNMADD_H 0x600007f
+#define MATCH_FCVT_H_D 0x44100053
+#define MASK_FCVT_H_D 0xfff0007f
+#define MATCH_FCVT_D_H 0x42200053
+#define MASK_FCVT_D_H 0xfff0007f
+#define MATCH_FCVT_H_Q 0x44300053
+#define MASK_FCVT_H_Q 0xfff0007f
+#define MATCH_FCVT_Q_H 0x46200053
+#define MASK_FCVT_Q_H 0xfff0007f
+#define MATCH_FCVT_L_H 0xc4200053
+#define MASK_FCVT_L_H 0xfff0007f
+#define MATCH_FCVT_LU_H 0xc4300053
+#define MASK_FCVT_LU_H 0xfff0007f
+#define MATCH_FCVT_H_L 0xd4200053
+#define MASK_FCVT_H_L 0xfff0007f
+#define MATCH_FCVT_H_LU 0xd4300053
+#define MASK_FCVT_H_LU 0xfff0007f
+#define MATCH_SM4ED 0x30000033
+#define MASK_SM4ED 0x3e00707f
+#define MATCH_SM4KS 0x34000033
+#define MASK_SM4KS 0x3e00707f
+#define MATCH_SM3P0 0x10801013
+#define MASK_SM3P0 0xfff0707f
+#define MATCH_SM3P1 0x10901013
+#define MASK_SM3P1 0xfff0707f
+#define MATCH_SHA256SUM0 0x10001013
+#define MASK_SHA256SUM0 0xfff0707f
+#define MATCH_SHA256SUM1 0x10101013
+#define MASK_SHA256SUM1 0xfff0707f
+#define MATCH_SHA256SIG0 0x10201013
+#define MASK_SHA256SIG0 0xfff0707f
+#define MATCH_SHA256SIG1 0x10301013
+#define MASK_SHA256SIG1 0xfff0707f
+#define MATCH_AES32ESMI 0x26000033
+#define MASK_AES32ESMI 0x3e00707f
+#define MATCH_AES32ESI 0x22000033
+#define MASK_AES32ESI 0x3e00707f
+#define MATCH_AES32DSMI 0x2e000033
+#define MASK_AES32DSMI 0x3e00707f
+#define MATCH_AES32DSI 0x2a000033
+#define MASK_AES32DSI 0x3e00707f
+#define MATCH_SHA512SUM0R 0x50000033
+#define MASK_SHA512SUM0R 0xfe00707f
+#define MATCH_SHA512SUM1R 0x52000033
+#define MASK_SHA512SUM1R 0xfe00707f
+#define MATCH_SHA512SIG0L 0x54000033
+#define MASK_SHA512SIG0L 0xfe00707f
+#define MATCH_SHA512SIG0H 0x5c000033
+#define MASK_SHA512SIG0H 0xfe00707f
+#define MATCH_SHA512SIG1L 0x56000033
+#define MASK_SHA512SIG1L 0xfe00707f
+#define MATCH_SHA512SIG1H 0x5e000033
+#define MASK_SHA512SIG1H 0xfe00707f
+#define MATCH_AES64KS1I 0x31001013
+#define MASK_AES64KS1I 0xff00707f
+#define MATCH_AES64IM 0x30001013
+#define MASK_AES64IM 0xfff0707f
+#define MATCH_AES64KS2 0x7e000033
+#define MASK_AES64KS2 0xfe00707f
+#define MATCH_AES64ESM 0x36000033
+#define MASK_AES64ESM 0xfe00707f
+#define MATCH_AES64ES 0x32000033
+#define MASK_AES64ES 0xfe00707f
+#define MATCH_AES64DSM 0x3e000033
+#define MASK_AES64DSM 0xfe00707f
+#define MATCH_AES64DS 0x3a000033
+#define MASK_AES64DS 0xfe00707f
+#define MATCH_SHA512SUM0 0x10401013
+#define MASK_SHA512SUM0 0xfff0707f
+#define MATCH_SHA512SUM1 0x10501013
+#define MASK_SHA512SUM1 0xfff0707f
+#define MATCH_SHA512SIG0 0x10601013
+#define MASK_SHA512SIG0 0xfff0707f
+#define MATCH_SHA512SIG1 0x10701013
+#define MASK_SHA512SIG1 0xfff0707f
#define MATCH_C_NOP 0x1
#define MASK_C_NOP 0xffff
#define MATCH_C_ADDI16SP 0x6101
@@ -881,10 +1227,16 @@
#define MASK_CUSTOM3_RD_RS1 0x707f
#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
+#define MATCH_VSETIVLI 0xc0007057
+#define MASK_VSETIVLI 0xc000707f
#define MATCH_VSETVLI 0x7057
#define MASK_VSETVLI 0x8000707f
#define MATCH_VSETVL 0x80007057
#define MASK_VSETVL 0xfe00707f
+#define MATCH_VLM_V 0x2b00007
+#define MASK_VLM_V 0xfff0707f
+#define MATCH_VSM_V 0x2b00027
+#define MASK_VSM_V 0xfff0707f
#define MATCH_VLE8_V 0x7
#define MASK_VLE8_V 0x1df0707f
#define MATCH_VLE16_V 0x5007
@@ -917,6 +1269,38 @@
#define MASK_VSE512_V 0x1df0707f
#define MATCH_VSE1024_V 0x10007027
#define MASK_VSE1024_V 0x1df0707f
+#define MATCH_VLUXEI8_V 0x4000007
+#define MASK_VLUXEI8_V 0x1c00707f
+#define MATCH_VLUXEI16_V 0x4005007
+#define MASK_VLUXEI16_V 0x1c00707f
+#define MATCH_VLUXEI32_V 0x4006007
+#define MASK_VLUXEI32_V 0x1c00707f
+#define MATCH_VLUXEI64_V 0x4007007
+#define MASK_VLUXEI64_V 0x1c00707f
+#define MATCH_VLUXEI128_V 0x14000007
+#define MASK_VLUXEI128_V 0x1c00707f
+#define MATCH_VLUXEI256_V 0x14005007
+#define MASK_VLUXEI256_V 0x1c00707f
+#define MATCH_VLUXEI512_V 0x14006007
+#define MASK_VLUXEI512_V 0x1c00707f
+#define MATCH_VLUXEI1024_V 0x14007007
+#define MASK_VLUXEI1024_V 0x1c00707f
+#define MATCH_VSUXEI8_V 0x4000027
+#define MASK_VSUXEI8_V 0x1c00707f
+#define MATCH_VSUXEI16_V 0x4005027
+#define MASK_VSUXEI16_V 0x1c00707f
+#define MATCH_VSUXEI32_V 0x4006027
+#define MASK_VSUXEI32_V 0x1c00707f
+#define MATCH_VSUXEI64_V 0x4007027
+#define MASK_VSUXEI64_V 0x1c00707f
+#define MATCH_VSUXEI128_V 0x14000027
+#define MASK_VSUXEI128_V 0x1c00707f
+#define MATCH_VSUXEI256_V 0x14005027
+#define MASK_VSUXEI256_V 0x1c00707f
+#define MATCH_VSUXEI512_V 0x14006027
+#define MASK_VSUXEI512_V 0x1c00707f
+#define MATCH_VSUXEI1024_V 0x14007027
+#define MASK_VSUXEI1024_V 0x1c00707f
#define MATCH_VLSE8_V 0x8000007
#define MASK_VLSE8_V 0x1c00707f
#define MATCH_VLSE16_V 0x8005007
@@ -949,54 +1333,38 @@
#define MASK_VSSE512_V 0x1c00707f
#define MATCH_VSSE1024_V 0x18007027
#define MASK_VSSE1024_V 0x1c00707f
-#define MATCH_VLXEI8_V 0xc000007
-#define MASK_VLXEI8_V 0x1c00707f
-#define MATCH_VLXEI16_V 0xc005007
-#define MASK_VLXEI16_V 0x1c00707f
-#define MATCH_VLXEI32_V 0xc006007
-#define MASK_VLXEI32_V 0x1c00707f
-#define MATCH_VLXEI64_V 0xc007007
-#define MASK_VLXEI64_V 0x1c00707f
-#define MATCH_VLXEI128_V 0x1c000007
-#define MASK_VLXEI128_V 0x1c00707f
-#define MATCH_VLXEI256_V 0x1c005007
-#define MASK_VLXEI256_V 0x1c00707f
-#define MATCH_VLXEI512_V 0x1c006007
-#define MASK_VLXEI512_V 0x1c00707f
-#define MATCH_VLXEI1024_V 0x1c007007
-#define MASK_VLXEI1024_V 0x1c00707f
-#define MATCH_VSXEI8_V 0xc000027
-#define MASK_VSXEI8_V 0x1c00707f
-#define MATCH_VSXEI16_V 0xc005027
-#define MASK_VSXEI16_V 0x1c00707f
-#define MATCH_VSXEI32_V 0xc006027
-#define MASK_VSXEI32_V 0x1c00707f
-#define MATCH_VSXEI64_V 0xc007027
-#define MASK_VSXEI64_V 0x1c00707f
-#define MATCH_VSXEI128_V 0x1c000027
-#define MASK_VSXEI128_V 0x1c00707f
-#define MATCH_VSXEI256_V 0x1c005027
-#define MASK_VSXEI256_V 0x1c00707f
-#define MATCH_VSXEI512_V 0x1c006027
-#define MASK_VSXEI512_V 0x1c00707f
-#define MATCH_VSXEI1024_V 0x1c007027
-#define MASK_VSXEI1024_V 0x1c00707f
-#define MATCH_VSUXEI8_V 0x4000027
-#define MASK_VSUXEI8_V 0x1c00707f
-#define MATCH_VSUXEI16_V 0x4005027
-#define MASK_VSUXEI16_V 0x1c00707f
-#define MATCH_VSUXEI32_V 0x4006027
-#define MASK_VSUXEI32_V 0x1c00707f
-#define MATCH_VSUXEI64_V 0x4007027
-#define MASK_VSUXEI64_V 0x1c00707f
-#define MATCH_VSUXEI128_V 0x14000027
-#define MASK_VSUXEI128_V 0x1c00707f
-#define MATCH_VSUXEI256_V 0x14005027
-#define MASK_VSUXEI256_V 0x1c00707f
-#define MATCH_VSUXEI512_V 0x14006027
-#define MASK_VSUXEI512_V 0x1c00707f
-#define MATCH_VSUXEI1024_V 0x14007027
-#define MASK_VSUXEI1024_V 0x1c00707f
+#define MATCH_VLOXEI8_V 0xc000007
+#define MASK_VLOXEI8_V 0x1c00707f
+#define MATCH_VLOXEI16_V 0xc005007
+#define MASK_VLOXEI16_V 0x1c00707f
+#define MATCH_VLOXEI32_V 0xc006007
+#define MASK_VLOXEI32_V 0x1c00707f
+#define MATCH_VLOXEI64_V 0xc007007
+#define MASK_VLOXEI64_V 0x1c00707f
+#define MATCH_VLOXEI128_V 0x1c000007
+#define MASK_VLOXEI128_V 0x1c00707f
+#define MATCH_VLOXEI256_V 0x1c005007
+#define MASK_VLOXEI256_V 0x1c00707f
+#define MATCH_VLOXEI512_V 0x1c006007
+#define MASK_VLOXEI512_V 0x1c00707f
+#define MATCH_VLOXEI1024_V 0x1c007007
+#define MASK_VLOXEI1024_V 0x1c00707f
+#define MATCH_VSOXEI8_V 0xc000027
+#define MASK_VSOXEI8_V 0x1c00707f
+#define MATCH_VSOXEI16_V 0xc005027
+#define MASK_VSOXEI16_V 0x1c00707f
+#define MATCH_VSOXEI32_V 0xc006027
+#define MASK_VSOXEI32_V 0x1c00707f
+#define MATCH_VSOXEI64_V 0xc007027
+#define MASK_VSOXEI64_V 0x1c00707f
+#define MATCH_VSOXEI128_V 0x1c000027
+#define MASK_VSOXEI128_V 0x1c00707f
+#define MATCH_VSOXEI256_V 0x1c005027
+#define MASK_VSOXEI256_V 0x1c00707f
+#define MATCH_VSOXEI512_V 0x1c006027
+#define MASK_VSOXEI512_V 0x1c00707f
+#define MATCH_VSOXEI1024_V 0x1c007027
+#define MASK_VSOXEI1024_V 0x1c00707f
#define MATCH_VLE8FF_V 0x1000007
#define MASK_VLE8FF_V 0x1df0707f
#define MATCH_VLE16FF_V 0x1005007
@@ -1133,8 +1501,8 @@
#define MASK_VFWNMSAC_VF 0xfc00707f
#define MATCH_VFADD_VV 0x1057
#define MASK_VFADD_VV 0xfc00707f
-#define MATCH_VFREDSUM_VS 0x4001057
-#define MASK_VFREDSUM_VS 0xfc00707f
+#define MATCH_VFREDUSUM_VS 0x4001057
+#define MASK_VFREDUSUM_VS 0xfc00707f
#define MATCH_VFSUB_VV 0x8001057
#define MASK_VFSUB_VV 0xfc00707f
#define MATCH_VFREDOSUM_VS 0xc001057
@@ -1227,12 +1595,16 @@
#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f
#define MATCH_VFSQRT_V 0x4c001057
#define MASK_VFSQRT_V 0xfc0ff07f
+#define MATCH_VFRSQRT7_V 0x4c021057
+#define MASK_VFRSQRT7_V 0xfc0ff07f
+#define MATCH_VFREC7_V 0x4c029057
+#define MASK_VFREC7_V 0xfc0ff07f
#define MATCH_VFCLASS_V 0x4c081057
#define MASK_VFCLASS_V 0xfc0ff07f
#define MATCH_VFWADD_VV 0xc0001057
#define MASK_VFWADD_VV 0xfc00707f
-#define MATCH_VFWREDSUM_VS 0xc4001057
-#define MASK_VFWREDSUM_VS 0xfc00707f
+#define MATCH_VFWREDUSUM_VS 0xc4001057
+#define MASK_VFWREDUSUM_VS 0xfc00707f
#define MATCH_VFWSUB_VV 0xc8001057
#define MASK_VFWSUB_VV 0xfc00707f
#define MATCH_VFWREDOSUM_VS 0xcc001057
@@ -1243,8 +1615,6 @@
#define MASK_VFWSUB_WV 0xfc00707f
#define MATCH_VFWMUL_VV 0xe0001057
#define MASK_VFWMUL_VV 0xfc00707f
-#define MATCH_VFDOT_VV 0xe4001057
-#define MASK_VFDOT_VV 0xfc00707f
#define MATCH_VFWMACC_VV 0xf0001057
#define MASK_VFWMACC_VV 0xfc00707f
#define MATCH_VFWNMACC_VV 0xf4001057
@@ -1282,11 +1652,15 @@
#define MATCH_VADC_VXM 0x40004057
#define MASK_VADC_VXM 0xfe00707f
#define MATCH_VMADC_VXM 0x44004057
-#define MASK_VMADC_VXM 0xfc00707f
+#define MASK_VMADC_VXM 0xfe00707f
+#define MATCH_VMADC_VX 0x46004057
+#define MASK_VMADC_VX 0xfe00707f
#define MATCH_VSBC_VXM 0x48004057
#define MASK_VSBC_VXM 0xfe00707f
#define MATCH_VMSBC_VXM 0x4c004057
-#define MASK_VMSBC_VXM 0xfc00707f
+#define MASK_VMSBC_VXM 0xfe00707f
+#define MATCH_VMSBC_VX 0x4e004057
+#define MASK_VMSBC_VX 0xfe00707f
#define MATCH_VMERGE_VXM 0x5c004057
#define MASK_VMERGE_VXM 0xfe00707f
#define MATCH_VMV_V_X 0x5e004057
@@ -1335,14 +1709,6 @@
#define MASK_VNCLIPU_WX 0xfc00707f
#define MATCH_VNCLIP_WX 0xbc004057
#define MASK_VNCLIP_WX 0xfc00707f
-#define MATCH_VQMACCU_VX 0xf0004057
-#define MASK_VQMACCU_VX 0xfc00707f
-#define MATCH_VQMACC_VX 0xf4004057
-#define MASK_VQMACC_VX 0xfc00707f
-#define MATCH_VQMACCUS_VX 0xf8004057
-#define MASK_VQMACCUS_VX 0xfc00707f
-#define MATCH_VQMACCSU_VX 0xfc004057
-#define MASK_VQMACCSU_VX 0xfc00707f
#define MATCH_VADD_VV 0x57
#define MASK_VADD_VV 0xfc00707f
#define MATCH_VSUB_VV 0x8000057
@@ -1368,11 +1734,15 @@
#define MATCH_VADC_VVM 0x40000057
#define MASK_VADC_VVM 0xfe00707f
#define MATCH_VMADC_VVM 0x44000057
-#define MASK_VMADC_VVM 0xfc00707f
+#define MASK_VMADC_VVM 0xfe00707f
+#define MATCH_VMADC_VV 0x46000057
+#define MASK_VMADC_VV 0xfe00707f
#define MATCH_VSBC_VVM 0x48000057
#define MASK_VSBC_VVM 0xfe00707f
#define MATCH_VMSBC_VVM 0x4c000057
-#define MASK_VMSBC_VVM 0xfc00707f
+#define MASK_VMSBC_VVM 0xfe00707f
+#define MATCH_VMSBC_VV 0x4e000057
+#define MASK_VMSBC_VV 0xfe00707f
#define MATCH_VMERGE_VVM 0x5c000057
#define MASK_VMERGE_VVM 0xfe00707f
#define MATCH_VMV_V_V 0x5e000057
@@ -1421,16 +1791,6 @@
#define MASK_VWREDSUMU_VS 0xfc00707f
#define MATCH_VWREDSUM_VS 0xc4000057
#define MASK_VWREDSUM_VS 0xfc00707f
-#define MATCH_VDOTU_VV 0xe0000057
-#define MASK_VDOTU_VV 0xfc00707f
-#define MATCH_VDOT_VV 0xe4000057
-#define MASK_VDOT_VV 0xfc00707f
-#define MATCH_VQMACCU_VV 0xf0000057
-#define MASK_VQMACCU_VV 0xfc00707f
-#define MATCH_VQMACC_VV 0xf4000057
-#define MASK_VQMACC_VV 0xfc00707f
-#define MATCH_VQMACCSU_VV 0xfc000057
-#define MASK_VQMACCSU_VV 0xfc00707f
#define MATCH_VADD_VI 0x3057
#define MASK_VADD_VI 0xfc00707f
#define MATCH_VRSUB_VI 0xc003057
@@ -1450,7 +1810,9 @@
#define MATCH_VADC_VIM 0x40003057
#define MASK_VADC_VIM 0xfe00707f
#define MATCH_VMADC_VIM 0x44003057
-#define MASK_VMADC_VIM 0xfc00707f
+#define MASK_VMADC_VIM 0xfe00707f
+#define MATCH_VMADC_VI 0x46003057
+#define MASK_VMADC_VI 0xfe00707f
#define MATCH_VMERGE_VIM 0x5c003057
#define MASK_VMERGE_VIM 0xfe00707f
#define MATCH_VMV_V_I 0x5e003057
@@ -1563,8 +1925,8 @@
#define MASK_VIOTA_M 0xfc0ff07f
#define MATCH_VID_V 0x5008a057
#define MASK_VID_V 0xfdfff07f
-#define MATCH_VPOPC_M 0x40082057
-#define MASK_VPOPC_M 0xfc0ff07f
+#define MATCH_VCPOP_M 0x40082057
+#define MASK_VCPOP_M 0xfc0ff07f
#define MATCH_VFIRST_M 0x4008a057
#define MASK_VFIRST_M 0xfc0ff07f
#define MATCH_VDIVU_VV 0x80002057
@@ -1759,6 +2121,658 @@
#define MASK_VAMOMINUEI64_V 0xf800707f
#define MATCH_VAMOMAXUEI64_V 0xe000702f
#define MASK_VAMOMAXUEI64_V 0xf800707f
+#define MATCH_ADD8 0x48000077
+#define MASK_ADD8 0xfe00707f
+#define MATCH_ADD16 0x40000077
+#define MASK_ADD16 0xfe00707f
+#define MATCH_ADD64 0xc0001077
+#define MASK_ADD64 0xfe00707f
+#define MATCH_AVE 0xe0000077
+#define MASK_AVE 0xfe00707f
+#define MATCH_BITREV 0xe6000077
+#define MASK_BITREV 0xfe00707f
+#define MATCH_BITREVI 0xe8000077
+#define MASK_BITREVI 0xfc00707f
+#define MATCH_BPICK 0x3077
+#define MASK_BPICK 0x600707f
+#define MATCH_CLRS8 0xae000077
+#define MASK_CLRS8 0xfff0707f
+#define MATCH_CLRS16 0xae800077
+#define MASK_CLRS16 0xfff0707f
+#define MATCH_CLRS32 0xaf800077
+#define MASK_CLRS32 0xfff0707f
+#define MATCH_CLO8 0xae300077
+#define MASK_CLO8 0xfff0707f
+#define MATCH_CLO16 0xaeb00077
+#define MASK_CLO16 0xfff0707f
+#define MATCH_CLO32 0xafb00077
+#define MASK_CLO32 0xfff0707f
+#define MATCH_CLZ8 0xae100077
+#define MASK_CLZ8 0xfff0707f
+#define MATCH_CLZ16 0xae900077
+#define MASK_CLZ16 0xfff0707f
+#define MATCH_CLZ32 0xaf900077
+#define MASK_CLZ32 0xfff0707f
+#define MATCH_CMPEQ8 0x4e000077
+#define MASK_CMPEQ8 0xfe00707f
+#define MATCH_CMPEQ16 0x4c000077
+#define MASK_CMPEQ16 0xfe00707f
+#define MATCH_CRAS16 0x44000077
+#define MASK_CRAS16 0xfe00707f
+#define MATCH_CRSA16 0x46000077
+#define MASK_CRSA16 0xfe00707f
+#define MATCH_INSB 0xac000077
+#define MASK_INSB 0xff80707f
+#define MATCH_KABS8 0xad000077
+#define MASK_KABS8 0xfff0707f
+#define MATCH_KABS16 0xad100077
+#define MASK_KABS16 0xfff0707f
+#define MATCH_KABSW 0xad400077
+#define MASK_KABSW 0xfff0707f
+#define MATCH_KADD8 0x18000077
+#define MASK_KADD8 0xfe00707f
+#define MATCH_KADD16 0x10000077
+#define MASK_KADD16 0xfe00707f
+#define MATCH_KADD64 0x90001077
+#define MASK_KADD64 0xfe00707f
+#define MATCH_KADDH 0x4001077
+#define MASK_KADDH 0xfe00707f
+#define MATCH_KADDW 0x1077
+#define MASK_KADDW 0xfe00707f
+#define MATCH_KCRAS16 0x14000077
+#define MASK_KCRAS16 0xfe00707f
+#define MATCH_KCRSA16 0x16000077
+#define MASK_KCRSA16 0xfe00707f
+#define MATCH_KDMBB 0xa001077
+#define MASK_KDMBB 0xfe00707f
+#define MATCH_KDMBT 0x1a001077
+#define MASK_KDMBT 0xfe00707f
+#define MATCH_KDMTT 0x2a001077
+#define MASK_KDMTT 0xfe00707f
+#define MATCH_KDMABB 0xd2001077
+#define MASK_KDMABB 0xfe00707f
+#define MATCH_KDMABT 0xe2001077
+#define MASK_KDMABT 0xfe00707f
+#define MATCH_KDMATT 0xf2001077
+#define MASK_KDMATT 0xfe00707f
+#define MATCH_KHM8 0x8e000077
+#define MASK_KHM8 0xfe00707f
+#define MATCH_KHMX8 0x9e000077
+#define MASK_KHMX8 0xfe00707f
+#define MATCH_KHM16 0x86000077
+#define MASK_KHM16 0xfe00707f
+#define MATCH_KHMX16 0x96000077
+#define MASK_KHMX16 0xfe00707f
+#define MATCH_KHMBB 0xc001077
+#define MASK_KHMBB 0xfe00707f
+#define MATCH_KHMBT 0x1c001077
+#define MASK_KHMBT 0xfe00707f
+#define MATCH_KHMTT 0x2c001077
+#define MASK_KHMTT 0xfe00707f
+#define MATCH_KMABB 0x5a001077
+#define MASK_KMABB 0xfe00707f
+#define MATCH_KMABT 0x6a001077
+#define MASK_KMABT 0xfe00707f
+#define MATCH_KMATT 0x7a001077
+#define MASK_KMATT 0xfe00707f
+#define MATCH_KMADA 0x48001077
+#define MASK_KMADA 0xfe00707f
+#define MATCH_KMAXDA 0x4a001077
+#define MASK_KMAXDA 0xfe00707f
+#define MATCH_KMADS 0x5c001077
+#define MASK_KMADS 0xfe00707f
+#define MATCH_KMADRS 0x6c001077
+#define MASK_KMADRS 0xfe00707f
+#define MATCH_KMAXDS 0x7c001077
+#define MASK_KMAXDS 0xfe00707f
+#define MATCH_KMAR64 0x94001077
+#define MASK_KMAR64 0xfe00707f
+#define MATCH_KMDA 0x38001077
+#define MASK_KMDA 0xfe00707f
+#define MATCH_KMXDA 0x3a001077
+#define MASK_KMXDA 0xfe00707f
+#define MATCH_KMMAC 0x60001077
+#define MASK_KMMAC 0xfe00707f
+#define MATCH_KMMAC_U 0x70001077
+#define MASK_KMMAC_U 0xfe00707f
+#define MATCH_KMMAWB 0x46001077
+#define MASK_KMMAWB 0xfe00707f
+#define MATCH_KMMAWB_U 0x56001077
+#define MASK_KMMAWB_U 0xfe00707f
+#define MATCH_KMMAWB2 0xce001077
+#define MASK_KMMAWB2 0xfe00707f
+#define MATCH_KMMAWB2_U 0xde001077
+#define MASK_KMMAWB2_U 0xfe00707f
+#define MATCH_KMMAWT 0x66001077
+#define MASK_KMMAWT 0xfe00707f
+#define MATCH_KMMAWT_U 0x76001077
+#define MASK_KMMAWT_U 0xfe00707f
+#define MATCH_KMMAWT2 0xee001077
+#define MASK_KMMAWT2 0xfe00707f
+#define MATCH_KMMAWT2_U 0xfe001077
+#define MASK_KMMAWT2_U 0xfe00707f
+#define MATCH_KMMSB 0x42001077
+#define MASK_KMMSB 0xfe00707f
+#define MATCH_KMMSB_U 0x52001077
+#define MASK_KMMSB_U 0xfe00707f
+#define MATCH_KMMWB2 0x8e001077
+#define MASK_KMMWB2 0xfe00707f
+#define MATCH_KMMWB2_U 0x9e001077
+#define MASK_KMMWB2_U 0xfe00707f
+#define MATCH_KMMWT2 0xae001077
+#define MASK_KMMWT2 0xfe00707f
+#define MATCH_KMMWT2_U 0xbe001077
+#define MASK_KMMWT2_U 0xfe00707f
+#define MATCH_KMSDA 0x4c001077
+#define MASK_KMSDA 0xfe00707f
+#define MATCH_KMSXDA 0x4e001077
+#define MASK_KMSXDA 0xfe00707f
+#define MATCH_KMSR64 0x96001077
+#define MASK_KMSR64 0xfe00707f
+#define MATCH_KSLLW 0x26001077
+#define MASK_KSLLW 0xfe00707f
+#define MATCH_KSLLIW 0x36001077
+#define MASK_KSLLIW 0xfe00707f
+#define MATCH_KSLL8 0x6c000077
+#define MASK_KSLL8 0xfe00707f
+#define MATCH_KSLLI8 0x7c800077
+#define MASK_KSLLI8 0xff80707f
+#define MATCH_KSLL16 0x64000077
+#define MASK_KSLL16 0xfe00707f
+#define MATCH_KSLLI16 0x75000077
+#define MASK_KSLLI16 0xff00707f
+#define MATCH_KSLRA8 0x5e000077
+#define MASK_KSLRA8 0xfe00707f
+#define MATCH_KSLRA8_U 0x6e000077
+#define MASK_KSLRA8_U 0xfe00707f
+#define MATCH_KSLRA16 0x56000077
+#define MASK_KSLRA16 0xfe00707f
+#define MATCH_KSLRA16_U 0x66000077
+#define MASK_KSLRA16_U 0xfe00707f
+#define MATCH_KSLRAW 0x6e001077
+#define MASK_KSLRAW 0xfe00707f
+#define MATCH_KSLRAW_U 0x7e001077
+#define MASK_KSLRAW_U 0xfe00707f
+#define MATCH_KSTAS16 0xc4002077
+#define MASK_KSTAS16 0xfe00707f
+#define MATCH_KSTSA16 0xc6002077
+#define MASK_KSTSA16 0xfe00707f
+#define MATCH_KSUB8 0x1a000077
+#define MASK_KSUB8 0xfe00707f
+#define MATCH_KSUB16 0x12000077
+#define MASK_KSUB16 0xfe00707f
+#define MATCH_KSUB64 0x92001077
+#define MASK_KSUB64 0xfe00707f
+#define MATCH_KSUBH 0x6001077
+#define MASK_KSUBH 0xfe00707f
+#define MATCH_KSUBW 0x2001077
+#define MASK_KSUBW 0xfe00707f
+#define MATCH_KWMMUL 0x62001077
+#define MASK_KWMMUL 0xfe00707f
+#define MATCH_KWMMUL_U 0x72001077
+#define MASK_KWMMUL_U 0xfe00707f
+#define MATCH_MADDR32 0xc4001077
+#define MASK_MADDR32 0xfe00707f
+#define MATCH_MAXW 0xf2000077
+#define MASK_MAXW 0xfe00707f
+#define MATCH_MINW 0xf0000077
+#define MASK_MINW 0xfe00707f
+#define MATCH_MSUBR32 0xc6001077
+#define MASK_MSUBR32 0xfe00707f
+#define MATCH_MULR64 0xf0001077
+#define MASK_MULR64 0xfe00707f
+#define MATCH_MULSR64 0xe0001077
+#define MASK_MULSR64 0xfe00707f
+#define MATCH_PBSAD 0xfc000077
+#define MASK_PBSAD 0xfe00707f
+#define MATCH_PBSADA 0xfe000077
+#define MASK_PBSADA 0xfe00707f
+#define MATCH_PKBB16 0xe001077
+#define MASK_PKBB16 0xfe00707f
+#define MATCH_PKBT16 0x1e001077
+#define MASK_PKBT16 0xfe00707f
+#define MATCH_PKTT16 0x2e001077
+#define MASK_PKTT16 0xfe00707f
+#define MATCH_PKTB16 0x3e001077
+#define MASK_PKTB16 0xfe00707f
+#define MATCH_RADD8 0x8000077
+#define MASK_RADD8 0xfe00707f
+#define MATCH_RADD16 0x77
+#define MASK_RADD16 0xfe00707f
+#define MATCH_RADD64 0x80001077
+#define MASK_RADD64 0xfe00707f
+#define MATCH_RADDW 0x20001077
+#define MASK_RADDW 0xfe00707f
+#define MATCH_RCRAS16 0x4000077
+#define MASK_RCRAS16 0xfe00707f
+#define MATCH_RCRSA16 0x6000077
+#define MASK_RCRSA16 0xfe00707f
+#define MATCH_RSTAS16 0xb4002077
+#define MASK_RSTAS16 0xfe00707f
+#define MATCH_RSTSA16 0xb6002077
+#define MASK_RSTSA16 0xfe00707f
+#define MATCH_RSUB8 0xa000077
+#define MASK_RSUB8 0xfe00707f
+#define MATCH_RSUB16 0x2000077
+#define MASK_RSUB16 0xfe00707f
+#define MATCH_RSUB64 0x82001077
+#define MASK_RSUB64 0xfe00707f
+#define MATCH_RSUBW 0x22001077
+#define MASK_RSUBW 0xfe00707f
+#define MATCH_SCLIP8 0x8c000077
+#define MASK_SCLIP8 0xff80707f
+#define MATCH_SCLIP16 0x84000077
+#define MASK_SCLIP16 0xff00707f
+#define MATCH_SCLIP32 0xe4000077
+#define MASK_SCLIP32 0xfe00707f
+#define MATCH_SCMPLE8 0x1e000077
+#define MASK_SCMPLE8 0xfe00707f
+#define MATCH_SCMPLE16 0x1c000077
+#define MASK_SCMPLE16 0xfe00707f
+#define MATCH_SCMPLT8 0xe000077
+#define MASK_SCMPLT8 0xfe00707f
+#define MATCH_SCMPLT16 0xc000077
+#define MASK_SCMPLT16 0xfe00707f
+#define MATCH_SLL8 0x5c000077
+#define MASK_SLL8 0xfe00707f
+#define MATCH_SLLI8 0x7c000077
+#define MASK_SLLI8 0xff80707f
+#define MATCH_SLL16 0x54000077
+#define MASK_SLL16 0xfe00707f
+#define MATCH_SLLI16 0x74000077
+#define MASK_SLLI16 0xff00707f
+#define MATCH_SMAL 0x5e001077
+#define MASK_SMAL 0xfe00707f
+#define MATCH_SMALBB 0x88001077
+#define MASK_SMALBB 0xfe00707f
+#define MATCH_SMALBT 0x98001077
+#define MASK_SMALBT 0xfe00707f
+#define MATCH_SMALTT 0xa8001077
+#define MASK_SMALTT 0xfe00707f
+#define MATCH_SMALDA 0x8c001077
+#define MASK_SMALDA 0xfe00707f
+#define MATCH_SMALXDA 0x9c001077
+#define MASK_SMALXDA 0xfe00707f
+#define MATCH_SMALDS 0x8a001077
+#define MASK_SMALDS 0xfe00707f
+#define MATCH_SMALDRS 0x9a001077
+#define MASK_SMALDRS 0xfe00707f
+#define MATCH_SMALXDS 0xaa001077
+#define MASK_SMALXDS 0xfe00707f
+#define MATCH_SMAR64 0x84001077
+#define MASK_SMAR64 0xfe00707f
+#define MATCH_SMAQA 0xc8000077
+#define MASK_SMAQA 0xfe00707f
+#define MATCH_SMAQA_SU 0xca000077
+#define MASK_SMAQA_SU 0xfe00707f
+#define MATCH_SMAX8 0x8a000077
+#define MASK_SMAX8 0xfe00707f
+#define MATCH_SMAX16 0x82000077
+#define MASK_SMAX16 0xfe00707f
+#define MATCH_SMBB16 0x8001077
+#define MASK_SMBB16 0xfe00707f
+#define MATCH_SMBT16 0x18001077
+#define MASK_SMBT16 0xfe00707f
+#define MATCH_SMTT16 0x28001077
+#define MASK_SMTT16 0xfe00707f
+#define MATCH_SMDS 0x58001077
+#define MASK_SMDS 0xfe00707f
+#define MATCH_SMDRS 0x68001077
+#define MASK_SMDRS 0xfe00707f
+#define MATCH_SMXDS 0x78001077
+#define MASK_SMXDS 0xfe00707f
+#define MATCH_SMIN8 0x88000077
+#define MASK_SMIN8 0xfe00707f
+#define MATCH_SMIN16 0x80000077
+#define MASK_SMIN16 0xfe00707f
+#define MATCH_SMMUL 0x40001077
+#define MASK_SMMUL 0xfe00707f
+#define MATCH_SMMUL_U 0x50001077
+#define MASK_SMMUL_U 0xfe00707f
+#define MATCH_SMMWB 0x44001077
+#define MASK_SMMWB 0xfe00707f
+#define MATCH_SMMWB_U 0x54001077
+#define MASK_SMMWB_U 0xfe00707f
+#define MATCH_SMMWT 0x64001077
+#define MASK_SMMWT 0xfe00707f
+#define MATCH_SMMWT_U 0x74001077
+#define MASK_SMMWT_U 0xfe00707f
+#define MATCH_SMSLDA 0xac001077
+#define MASK_SMSLDA 0xfe00707f
+#define MATCH_SMSLXDA 0xbc001077
+#define MASK_SMSLXDA 0xfe00707f
+#define MATCH_SMSR64 0x86001077
+#define MASK_SMSR64 0xfe00707f
+#define MATCH_SMUL8 0xa8000077
+#define MASK_SMUL8 0xfe00707f
+#define MATCH_SMULX8 0xaa000077
+#define MASK_SMULX8 0xfe00707f
+#define MATCH_SMUL16 0xa0000077
+#define MASK_SMUL16 0xfe00707f
+#define MATCH_SMULX16 0xa2000077
+#define MASK_SMULX16 0xfe00707f
+#define MATCH_SRA_U 0x24001077
+#define MASK_SRA_U 0xfe00707f
+#define MATCH_SRAI_U 0xd4001077
+#define MASK_SRAI_U 0xfc00707f
+#define MATCH_SRA8 0x58000077
+#define MASK_SRA8 0xfe00707f
+#define MATCH_SRA8_U 0x68000077
+#define MASK_SRA8_U 0xfe00707f
+#define MATCH_SRAI8 0x78000077
+#define MASK_SRAI8 0xff80707f
+#define MATCH_SRAI8_U 0x78800077
+#define MASK_SRAI8_U 0xff80707f
+#define MATCH_SRA16 0x50000077
+#define MASK_SRA16 0xfe00707f
+#define MATCH_SRA16_U 0x60000077
+#define MASK_SRA16_U 0xfe00707f
+#define MATCH_SRAI16 0x70000077
+#define MASK_SRAI16 0xff00707f
+#define MATCH_SRAI16_U 0x71000077
+#define MASK_SRAI16_U 0xff00707f
+#define MATCH_SRL8 0x5a000077
+#define MASK_SRL8 0xfe00707f
+#define MATCH_SRL8_U 0x6a000077
+#define MASK_SRL8_U 0xfe00707f
+#define MATCH_SRLI8 0x7a000077
+#define MASK_SRLI8 0xff80707f
+#define MATCH_SRLI8_U 0x7a800077
+#define MASK_SRLI8_U 0xff80707f
+#define MATCH_SRL16 0x52000077
+#define MASK_SRL16 0xfe00707f
+#define MATCH_SRL16_U 0x62000077
+#define MASK_SRL16_U 0xfe00707f
+#define MATCH_SRLI16 0x72000077
+#define MASK_SRLI16 0xff00707f
+#define MATCH_SRLI16_U 0x73000077
+#define MASK_SRLI16_U 0xff00707f
+#define MATCH_STAS16 0xf4002077
+#define MASK_STAS16 0xfe00707f
+#define MATCH_STSA16 0xf6002077
+#define MASK_STSA16 0xfe00707f
+#define MATCH_SUB8 0x4a000077
+#define MASK_SUB8 0xfe00707f
+#define MATCH_SUB16 0x42000077
+#define MASK_SUB16 0xfe00707f
+#define MATCH_SUB64 0xc2001077
+#define MASK_SUB64 0xfe00707f
+#define MATCH_SUNPKD810 0xac800077
+#define MASK_SUNPKD810 0xfff0707f
+#define MATCH_SUNPKD820 0xac900077
+#define MASK_SUNPKD820 0xfff0707f
+#define MATCH_SUNPKD830 0xaca00077
+#define MASK_SUNPKD830 0xfff0707f
+#define MATCH_SUNPKD831 0xacb00077
+#define MASK_SUNPKD831 0xfff0707f
+#define MATCH_SUNPKD832 0xad300077
+#define MASK_SUNPKD832 0xfff0707f
+#define MATCH_SWAP8 0xad800077
+#define MASK_SWAP8 0xfff0707f
+#define MATCH_UCLIP8 0x8d000077
+#define MASK_UCLIP8 0xff80707f
+#define MATCH_UCLIP16 0x85000077
+#define MASK_UCLIP16 0xff00707f
+#define MATCH_UCLIP32 0xf4000077
+#define MASK_UCLIP32 0xfe00707f
+#define MATCH_UCMPLE8 0x3e000077
+#define MASK_UCMPLE8 0xfe00707f
+#define MATCH_UCMPLE16 0x3c000077
+#define MASK_UCMPLE16 0xfe00707f
+#define MATCH_UCMPLT8 0x2e000077
+#define MASK_UCMPLT8 0xfe00707f
+#define MATCH_UCMPLT16 0x2c000077
+#define MASK_UCMPLT16 0xfe00707f
+#define MATCH_UKADD8 0x38000077
+#define MASK_UKADD8 0xfe00707f
+#define MATCH_UKADD16 0x30000077
+#define MASK_UKADD16 0xfe00707f
+#define MATCH_UKADD64 0xb0001077
+#define MASK_UKADD64 0xfe00707f
+#define MATCH_UKADDH 0x14001077
+#define MASK_UKADDH 0xfe00707f
+#define MATCH_UKADDW 0x10001077
+#define MASK_UKADDW 0xfe00707f
+#define MATCH_UKCRAS16 0x34000077
+#define MASK_UKCRAS16 0xfe00707f
+#define MATCH_UKCRSA16 0x36000077
+#define MASK_UKCRSA16 0xfe00707f
+#define MATCH_UKMAR64 0xb4001077
+#define MASK_UKMAR64 0xfe00707f
+#define MATCH_UKMSR64 0xb6001077
+#define MASK_UKMSR64 0xfe00707f
+#define MATCH_UKSTAS16 0xe4002077
+#define MASK_UKSTAS16 0xfe00707f
+#define MATCH_UKSTSA16 0xe6002077
+#define MASK_UKSTSA16 0xfe00707f
+#define MATCH_UKSUB8 0x3a000077
+#define MASK_UKSUB8 0xfe00707f
+#define MATCH_UKSUB16 0x32000077
+#define MASK_UKSUB16 0xfe00707f
+#define MATCH_UKSUB64 0xb2001077
+#define MASK_UKSUB64 0xfe00707f
+#define MATCH_UKSUBH 0x16001077
+#define MASK_UKSUBH 0xfe00707f
+#define MATCH_UKSUBW 0x12001077
+#define MASK_UKSUBW 0xfe00707f
+#define MATCH_UMAR64 0xa4001077
+#define MASK_UMAR64 0xfe00707f
+#define MATCH_UMAQA 0xcc000077
+#define MASK_UMAQA 0xfe00707f
+#define MATCH_UMAX8 0x9a000077
+#define MASK_UMAX8 0xfe00707f
+#define MATCH_UMAX16 0x92000077
+#define MASK_UMAX16 0xfe00707f
+#define MATCH_UMIN8 0x98000077
+#define MASK_UMIN8 0xfe00707f
+#define MATCH_UMIN16 0x90000077
+#define MASK_UMIN16 0xfe00707f
+#define MATCH_UMSR64 0xa6001077
+#define MASK_UMSR64 0xfe00707f
+#define MATCH_UMUL8 0xb8000077
+#define MASK_UMUL8 0xfe00707f
+#define MATCH_UMULX8 0xba000077
+#define MASK_UMULX8 0xfe00707f
+#define MATCH_UMUL16 0xb0000077
+#define MASK_UMUL16 0xfe00707f
+#define MATCH_UMULX16 0xb2000077
+#define MASK_UMULX16 0xfe00707f
+#define MATCH_URADD8 0x28000077
+#define MASK_URADD8 0xfe00707f
+#define MATCH_URADD16 0x20000077
+#define MASK_URADD16 0xfe00707f
+#define MATCH_URADD64 0xa0001077
+#define MASK_URADD64 0xfe00707f
+#define MATCH_URADDW 0x30001077
+#define MASK_URADDW 0xfe00707f
+#define MATCH_URCRAS16 0x24000077
+#define MASK_URCRAS16 0xfe00707f
+#define MATCH_URCRSA16 0x26000077
+#define MASK_URCRSA16 0xfe00707f
+#define MATCH_URSTAS16 0xd4002077
+#define MASK_URSTAS16 0xfe00707f
+#define MATCH_URSTSA16 0xd6002077
+#define MASK_URSTSA16 0xfe00707f
+#define MATCH_URSUB8 0x2a000077
+#define MASK_URSUB8 0xfe00707f
+#define MATCH_URSUB16 0x22000077
+#define MASK_URSUB16 0xfe00707f
+#define MATCH_URSUB64 0xa2001077
+#define MASK_URSUB64 0xfe00707f
+#define MATCH_URSUBW 0x32001077
+#define MASK_URSUBW 0xfe00707f
+#define MATCH_WEXTI 0xde000077
+#define MASK_WEXTI 0xfe00707f
+#define MATCH_WEXT 0xce000077
+#define MASK_WEXT 0xfe00707f
+#define MATCH_ZUNPKD810 0xacc00077
+#define MASK_ZUNPKD810 0xfff0707f
+#define MATCH_ZUNPKD820 0xacd00077
+#define MASK_ZUNPKD820 0xfff0707f
+#define MATCH_ZUNPKD830 0xace00077
+#define MASK_ZUNPKD830 0xfff0707f
+#define MATCH_ZUNPKD831 0xacf00077
+#define MASK_ZUNPKD831 0xfff0707f
+#define MATCH_ZUNPKD832 0xad700077
+#define MASK_ZUNPKD832 0xfff0707f
+#define MATCH_ADD32 0x40002077
+#define MASK_ADD32 0xfe00707f
+#define MATCH_CRAS32 0x44002077
+#define MASK_CRAS32 0xfe00707f
+#define MATCH_CRSA32 0x46002077
+#define MASK_CRSA32 0xfe00707f
+#define MATCH_KABS32 0xad200077
+#define MASK_KABS32 0xfff0707f
+#define MATCH_KADD32 0x10002077
+#define MASK_KADD32 0xfe00707f
+#define MATCH_KCRAS32 0x14002077
+#define MASK_KCRAS32 0xfe00707f
+#define MATCH_KCRSA32 0x16002077
+#define MASK_KCRSA32 0xfe00707f
+#define MATCH_KDMBB16 0xda001077
+#define MASK_KDMBB16 0xfe00707f
+#define MATCH_KDMBT16 0xea001077
+#define MASK_KDMBT16 0xfe00707f
+#define MATCH_KDMTT16 0xfa001077
+#define MASK_KDMTT16 0xfe00707f
+#define MATCH_KDMABB16 0xd8001077
+#define MASK_KDMABB16 0xfe00707f
+#define MATCH_KDMABT16 0xe8001077
+#define MASK_KDMABT16 0xfe00707f
+#define MATCH_KDMATT16 0xf8001077
+#define MASK_KDMATT16 0xfe00707f
+#define MATCH_KHMBB16 0xdc001077
+#define MASK_KHMBB16 0xfe00707f
+#define MATCH_KHMBT16 0xec001077
+#define MASK_KHMBT16 0xfe00707f
+#define MATCH_KHMTT16 0xfc001077
+#define MASK_KHMTT16 0xfe00707f
+#define MATCH_KMABB32 0x5a002077
+#define MASK_KMABB32 0xfe00707f
+#define MATCH_KMABT32 0x6a002077
+#define MASK_KMABT32 0xfe00707f
+#define MATCH_KMATT32 0x7a002077
+#define MASK_KMATT32 0xfe00707f
+#define MATCH_KMAXDA32 0x4a002077
+#define MASK_KMAXDA32 0xfe00707f
+#define MATCH_KMDA32 0x38002077
+#define MASK_KMDA32 0xfe00707f
+#define MATCH_KMXDA32 0x3a002077
+#define MASK_KMXDA32 0xfe00707f
+#define MATCH_KMADS32 0x5c002077
+#define MASK_KMADS32 0xfe00707f
+#define MATCH_KMADRS32 0x6c002077
+#define MASK_KMADRS32 0xfe00707f
+#define MATCH_KMAXDS32 0x7c002077
+#define MASK_KMAXDS32 0xfe00707f
+#define MATCH_KMSDA32 0x4c002077
+#define MASK_KMSDA32 0xfe00707f
+#define MATCH_KMSXDA32 0x4e002077
+#define MASK_KMSXDA32 0xfe00707f
+#define MATCH_KSLL32 0x64002077
+#define MASK_KSLL32 0xfe00707f
+#define MATCH_KSLLI32 0x84002077
+#define MASK_KSLLI32 0xfe00707f
+#define MATCH_KSLRA32 0x56002077
+#define MASK_KSLRA32 0xfe00707f
+#define MATCH_KSLRA32_U 0x66002077
+#define MASK_KSLRA32_U 0xfe00707f
+#define MATCH_KSTAS32 0xc0002077
+#define MASK_KSTAS32 0xfe00707f
+#define MATCH_KSTSA32 0xc2002077
+#define MASK_KSTSA32 0xfe00707f
+#define MATCH_KSUB32 0x12002077
+#define MASK_KSUB32 0xfe00707f
+#define MATCH_PKBB32 0xe002077
+#define MASK_PKBB32 0xfe00707f
+#define MATCH_PKBT32 0x1e002077
+#define MASK_PKBT32 0xfe00707f
+#define MATCH_PKTT32 0x2e002077
+#define MASK_PKTT32 0xfe00707f
+#define MATCH_PKTB32 0x3e002077
+#define MASK_PKTB32 0xfe00707f
+#define MATCH_RADD32 0x2077
+#define MASK_RADD32 0xfe00707f
+#define MATCH_RCRAS32 0x4002077
+#define MASK_RCRAS32 0xfe00707f
+#define MATCH_RCRSA32 0x6002077
+#define MASK_RCRSA32 0xfe00707f
+#define MATCH_RSTAS32 0xb0002077
+#define MASK_RSTAS32 0xfe00707f
+#define MATCH_RSTSA32 0xb2002077
+#define MASK_RSTSA32 0xfe00707f
+#define MATCH_RSUB32 0x2002077
+#define MASK_RSUB32 0xfe00707f
+#define MATCH_SLL32 0x54002077
+#define MASK_SLL32 0xfe00707f
+#define MATCH_SLLI32 0x74002077
+#define MASK_SLLI32 0xfe00707f
+#define MATCH_SMAX32 0x92002077
+#define MASK_SMAX32 0xfe00707f
+#define MATCH_SMBT32 0x18002077
+#define MASK_SMBT32 0xfe00707f
+#define MATCH_SMTT32 0x28002077
+#define MASK_SMTT32 0xfe00707f
+#define MATCH_SMDS32 0x58002077
+#define MASK_SMDS32 0xfe00707f
+#define MATCH_SMDRS32 0x68002077
+#define MASK_SMDRS32 0xfe00707f
+#define MATCH_SMXDS32 0x78002077
+#define MASK_SMXDS32 0xfe00707f
+#define MATCH_SMIN32 0x90002077
+#define MASK_SMIN32 0xfe00707f
+#define MATCH_SRA32 0x50002077
+#define MASK_SRA32 0xfe00707f
+#define MATCH_SRA32_U 0x60002077
+#define MASK_SRA32_U 0xfe00707f
+#define MATCH_SRAI32 0x70002077
+#define MASK_SRAI32 0xfe00707f
+#define MATCH_SRAI32_U 0x80002077
+#define MASK_SRAI32_U 0xfe00707f
+#define MATCH_SRAIW_U 0x34001077
+#define MASK_SRAIW_U 0xfe00707f
+#define MATCH_SRL32 0x52002077
+#define MASK_SRL32 0xfe00707f
+#define MATCH_SRL32_U 0x62002077
+#define MASK_SRL32_U 0xfe00707f
+#define MATCH_SRLI32 0x72002077
+#define MASK_SRLI32 0xfe00707f
+#define MATCH_SRLI32_U 0x82002077
+#define MASK_SRLI32_U 0xfe00707f
+#define MATCH_STAS32 0xf0002077
+#define MASK_STAS32 0xfe00707f
+#define MATCH_STSA32 0xf2002077
+#define MASK_STSA32 0xfe00707f
+#define MATCH_SUB32 0x42002077
+#define MASK_SUB32 0xfe00707f
+#define MATCH_UKADD32 0x30002077
+#define MASK_UKADD32 0xfe00707f
+#define MATCH_UKCRAS32 0x34002077
+#define MASK_UKCRAS32 0xfe00707f
+#define MATCH_UKCRSA32 0x36002077
+#define MASK_UKCRSA32 0xfe00707f
+#define MATCH_UKSTAS32 0xe0002077
+#define MASK_UKSTAS32 0xfe00707f
+#define MATCH_UKSTSA32 0xe2002077
+#define MASK_UKSTSA32 0xfe00707f
+#define MATCH_UKSUB32 0x32002077
+#define MASK_UKSUB32 0xfe00707f
+#define MATCH_UMAX32 0xa2002077
+#define MASK_UMAX32 0xfe00707f
+#define MATCH_UMIN32 0xa0002077
+#define MASK_UMIN32 0xfe00707f
+#define MATCH_URADD32 0x20002077
+#define MASK_URADD32 0xfe00707f
+#define MATCH_URCRAS32 0x24002077
+#define MASK_URCRAS32 0xfe00707f
+#define MATCH_URCRSA32 0x26002077
+#define MASK_URCRSA32 0xfe00707f
+#define MATCH_URSTAS32 0xd0002077
+#define MASK_URSTAS32 0xfe00707f
+#define MATCH_URSTSA32 0xd2002077
+#define MASK_URSTSA32 0xfe00707f
+#define MATCH_URSUB32 0x22002077
+#define MASK_URSUB32 0xfe00707f
#define MATCH_VMVNFR_V 0x9e003057
#define MASK_VMVNFR_V 0xfe00707f
#define MATCH_VL1R_V 0x2800007
@@ -1769,21 +2783,24 @@
#define MASK_VL4R_V 0xfff0707f
#define MATCH_VL8R_V 0x1e807007
#define MASK_VL8R_V 0xfff0707f
+#define MATCH_VLE1_V 0x2b00007
+#define MASK_VLE1_V 0xfff0707f
+#define MATCH_VSE1_V 0x2b00027
+#define MASK_VSE1_V 0xfff0707f
+#define MATCH_VFREDSUM_VS 0x4001057
+#define MASK_VFREDSUM_VS 0xfc00707f
+#define MATCH_VFWREDSUM_VS 0xc4001057
+#define MASK_VFWREDSUM_VS 0xfc00707f
+#define MATCH_VPOPC_M 0x40082057
+#define MASK_VPOPC_M 0xfc0ff07f
#define CSR_FFLAGS 0x1
#define CSR_FRM 0x2
#define CSR_FCSR 0x3
-#define CSR_USTATUS 0x0
-#define CSR_UIE 0x4
-#define CSR_UTVEC 0x5
#define CSR_VSTART 0x8
#define CSR_VXSAT 0x9
#define CSR_VXRM 0xa
#define CSR_VCSR 0xf
-#define CSR_USCRATCH 0x40
-#define CSR_UEPC 0x41
-#define CSR_UCAUSE 0x42
-#define CSR_UTVAL 0x43
-#define CSR_UIP 0x44
+#define CSR_SEED 0x15
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
#define CSR_INSTRET 0xc02
@@ -1831,6 +2848,7 @@
#define CSR_STVAL 0x143
#define CSR_SIP 0x144
#define CSR_SATP 0x180
+#define CSR_SCONTEXT 0x5a8
#define CSR_VSSTATUS 0x200
#define CSR_VSIE 0x204
#define CSR_VSTVEC 0x205
@@ -1852,6 +2870,7 @@
#define CSR_HVIP 0x645
#define CSR_HTINST 0x64a
#define CSR_HGATP 0x680
+#define CSR_HCONTEXT 0x6a8
#define CSR_HGEIP 0xe12
#define CSR_UTVT 0x7
#define CSR_UNXTI 0x45
@@ -1907,6 +2926,10 @@
#define CSR_TDATA1 0x7a1
#define CSR_TDATA2 0x7a2
#define CSR_TDATA3 0x7a3
+#define CSR_TINFO 0x7a4
+#define CSR_TCONTROL 0x7a5
+#define CSR_MCONTEXT 0x7a8
+#define CSR_MSCONTEXT 0x7aa
#define CSR_DCSR 0x7b0
#define CSR_DPC 0x7b1
#define CSR_DSCRATCH0 0x7b2
@@ -2095,12 +3118,9 @@ DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
-DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
-DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
-DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
@@ -2135,6 +3155,9 @@ DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
DECLARE_INSN(ld, MATCH_LD, MASK_LD)
DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
@@ -2279,9 +3302,111 @@ DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
+DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN)
+DECLARE_INSN(orn, MATCH_ORN, MASK_ORN)
+DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR)
+DECLARE_INSN(slo, MATCH_SLO, MASK_SLO)
+DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
+DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
+DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
+DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
+DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
+DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
+DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
+DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC)
+DECLARE_INSN(grev, MATCH_GREV, MASK_GREV)
+DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI)
+DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI)
+DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
+DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
+DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
+DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
+DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI)
+DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
+DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
+DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
+DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV)
+DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL)
+DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
+DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
+DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
+DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
+DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)
+DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
+DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
+DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B)
+DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H)
+DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W)
+DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B)
+DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H)
+DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W)
+DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD)
+DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD)
+DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD)
+DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
+DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
+DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
+DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
+DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
+DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
+DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
+DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL)
+DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL)
+DECLARE_INSN(bcompress, MATCH_BCOMPRESS, MASK_BCOMPRESS)
+DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS)
+DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
+DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU)
+DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
+DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP)
+DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI)
+DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI)
+DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4)
+DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8)
+DECLARE_INSN(xperm16, MATCH_XPERM16, MASK_XPERM16)
+DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP)
+DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
+DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
+DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
+DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
+DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
+DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW)
+DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW)
+DECLARE_INSN(srow, MATCH_SROW, MASK_SROW)
+DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
+DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
+DECLARE_INSN(sbclrw, MATCH_SBCLRW, MASK_SBCLRW)
+DECLARE_INSN(sbsetw, MATCH_SBSETW, MASK_SBSETW)
+DECLARE_INSN(sbinvw, MATCH_SBINVW, MASK_SBINVW)
+DECLARE_INSN(sbextw, MATCH_SBEXTW, MASK_SBEXTW)
+DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW)
+DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW)
+DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW)
+DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW)
+DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
+DECLARE_INSN(sbclriw, MATCH_SBCLRIW, MASK_SBCLRIW)
+DECLARE_INSN(sbsetiw, MATCH_SBSETIW, MASK_SBSETIW)
+DECLARE_INSN(sbinviw, MATCH_SBINVIW, MASK_SBINVIW)
+DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW)
+DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW)
+DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
+DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
+DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
+DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
+DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
+DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW)
+DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW)
+DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW)
+DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW)
+DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
+DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
+DECLARE_INSN(bcompressw, MATCH_BCOMPRESSW, MASK_BCOMPRESSW)
+DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW)
+DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
+DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW)
+DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW)
+DECLARE_INSN(xperm32, MATCH_XPERM32, MASK_XPERM32)
DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
-DECLARE_INSN(uret, MATCH_URET, MASK_URET)
DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
@@ -2293,6 +3418,76 @@ DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA)
+DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL)
+DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR)
+DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA)
+DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA)
+DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
+DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
+DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H)
+DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H)
+DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H)
+DECLARE_INSN(fsgnjn_h...
[truncated message content] |
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-11-20 14:39:07
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via ee670f9dcee606141112a7552d8409788f3caf7f (commit)
from d385dfbab44dc669c037b87c2e5b5c52accfcbe3 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit ee670f9dcee606141112a7552d8409788f3caf7f
Author: Antonio Borneo <bor...@gm...>
Date: Mon Nov 8 09:42:41 2021 +0100
jimtcl: update to master branch 20211108
Today's version of jimtcl includes a fix for autoconf >= 2.70 and
a minor fix for warnings with GCC 11.
To prepare for next jimtcl 0.81, let's merge and test the updated
master branch.
Change-Id: I455cc708f7d4786461978e38b6ac71816e2c9825
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6674
Tested-by: jenkins
diff --git a/jimtcl b/jimtcl
index 2d66360c6..70b007b63 160000
--- a/jimtcl
+++ b/jimtcl
@@ -1 +1 @@
-Subproject commit 2d66360c61d2a89d4008e8bad12ae3aa5f0331e2
+Subproject commit 70b007b63669a709b0e8aef34a22658047815cc2
-----------------------------------------------------------------------
Summary of changes:
jimtcl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-11-20 14:38:13
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via d385dfbab44dc669c037b87c2e5b5c52accfcbe3 (commit)
from fdaa16506d121f4d4616a2bcafe7dee017d55d81 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit d385dfbab44dc669c037b87c2e5b5c52accfcbe3
Author: Antonio Borneo <bor...@gm...>
Date: Thu Nov 11 23:48:10 2021 +0100
adi_v5_swd: add comment to describe debug flag 'do_sync'
Change-Id: I1f7f0eed7a6e3626f5fde841ec7fa1d29906db29
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6696
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c
index a21bf25b9..5e4fd2222 100644
--- a/src/target/adi_v5_swd.c
+++ b/src/target/adi_v5_swd.c
@@ -53,6 +53,7 @@
#include <jtag/swd.h>
+/* for debug, set do_sync to true to force synchronous transfers */
static bool do_sync;
static void swd_finish_read(struct adiv5_dap *dap)
-----------------------------------------------------------------------
Summary of changes:
src/target/adi_v5_swd.c | 1 +
1 file changed, 1 insertion(+)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2021-11-20 14:37:46
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via fdaa16506d121f4d4616a2bcafe7dee017d55d81 (commit)
from 560f0d83392bafc03d674e13880940d52d3f7f94 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit fdaa16506d121f4d4616a2bcafe7dee017d55d81
Author: Antonio Borneo <bor...@gm...>
Date: Thu Nov 11 22:29:32 2021 +0100
ftdi: add support to switch to/from dormant state
Partially extracted from https://review.openocd.org/4935
Change-Id: Ia3f197b257434a1a7979fdbc08936c7c541db1e2
Signed-off-by: Antonio Borneo <bor...@gm...>
Signed-off-by: graham sanderson <gra...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6693
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Andreas Fritiofson <and...@gm...>
diff --git a/src/jtag/drivers/ftdi.c b/src/jtag/drivers/ftdi.c
index 6e2e18450..d03a4ca23 100644
--- a/src/jtag/drivers/ftdi.c
+++ b/src/jtag/drivers/ftdi.c
@@ -1238,11 +1238,31 @@ static int ftdi_swd_switch_seq(enum swd_special_seq seq)
ftdi_swd_swdio_en(true);
mpsse_clock_data_out(mpsse_ctx, swd_seq_jtag_to_swd, 0, swd_seq_jtag_to_swd_len, SWD_MODE);
break;
+ case JTAG_TO_DORMANT:
+ LOG_DEBUG("JTAG-to-DORMANT");
+ ftdi_swd_swdio_en(true);
+ mpsse_clock_data_out(mpsse_ctx, swd_seq_jtag_to_dormant, 0, swd_seq_jtag_to_dormant_len, SWD_MODE);
+ break;
case SWD_TO_JTAG:
LOG_DEBUG("SWD-to-JTAG");
ftdi_swd_swdio_en(true);
mpsse_clock_data_out(mpsse_ctx, swd_seq_swd_to_jtag, 0, swd_seq_swd_to_jtag_len, SWD_MODE);
break;
+ case SWD_TO_DORMANT:
+ LOG_DEBUG("SWD-to-DORMANT");
+ ftdi_swd_swdio_en(true);
+ mpsse_clock_data_out(mpsse_ctx, swd_seq_swd_to_dormant, 0, swd_seq_swd_to_dormant_len, SWD_MODE);
+ break;
+ case DORMANT_TO_SWD:
+ LOG_DEBUG("DORMANT-to-SWD");
+ ftdi_swd_swdio_en(true);
+ mpsse_clock_data_out(mpsse_ctx, swd_seq_dormant_to_swd, 0, swd_seq_dormant_to_swd_len, SWD_MODE);
+ break;
+ case DORMANT_TO_JTAG:
+ LOG_DEBUG("DORMANT-to-JTAG");
+ ftdi_swd_swdio_en(true);
+ mpsse_clock_data_out(mpsse_ctx, swd_seq_dormant_to_jtag, 0, swd_seq_dormant_to_jtag_len, SWD_MODE);
+ break;
default:
LOG_ERROR("Sequence %d not supported", seq);
return ERROR_FAIL;
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/ftdi.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-11-20 14:36:17
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 560f0d83392bafc03d674e13880940d52d3f7f94 (commit)
from b4aa144c326e2f86f52ac48d4cb560f88a1f2b97 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 560f0d83392bafc03d674e13880940d52d3f7f94
Author: Antonio Borneo <bor...@gm...>
Date: Thu Nov 11 22:13:55 2021 +0100
jlink: add support to switch to/from dormant state
Change-Id: Ifeda21ab7a40926166045f211b9e772aedff715d
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6692
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/jtag/drivers/jlink.c b/src/jtag/drivers/jlink.c
index ce1e9bfb7..0414ec710 100644
--- a/src/jtag/drivers/jlink.c
+++ b/src/jtag/drivers/jlink.c
@@ -2148,11 +2148,31 @@ static int jlink_swd_switch_seq(enum swd_special_seq seq)
s = swd_seq_jtag_to_swd;
s_len = swd_seq_jtag_to_swd_len;
break;
+ case JTAG_TO_DORMANT:
+ LOG_DEBUG("JTAG-to-DORMANT");
+ s = swd_seq_jtag_to_dormant;
+ s_len = swd_seq_jtag_to_dormant_len;
+ break;
case SWD_TO_JTAG:
LOG_DEBUG("SWD-to-JTAG");
s = swd_seq_swd_to_jtag;
s_len = swd_seq_swd_to_jtag_len;
break;
+ case SWD_TO_DORMANT:
+ LOG_DEBUG("SWD-to-DORMANT");
+ s = swd_seq_swd_to_dormant;
+ s_len = swd_seq_swd_to_dormant_len;
+ break;
+ case DORMANT_TO_SWD:
+ LOG_DEBUG("DORMANT-to-SWD");
+ s = swd_seq_dormant_to_swd;
+ s_len = swd_seq_dormant_to_swd_len;
+ break;
+ case DORMANT_TO_JTAG:
+ LOG_DEBUG("DORMANT-to-JTAG");
+ s = swd_seq_dormant_to_jtag;
+ s_len = swd_seq_dormant_to_jtag_len;
+ break;
default:
LOG_ERROR("Sequence %d not supported", seq);
return ERROR_FAIL;
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/jlink.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2021-11-20 14:35:10
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b4aa144c326e2f86f52ac48d4cb560f88a1f2b97 (commit)
from ed44acce26edf259f5b238b972a6a4fe2597ca48 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit b4aa144c326e2f86f52ac48d4cb560f88a1f2b97
Author: Antonio Borneo <bor...@gm...>
Date: Thu Nov 11 16:44:27 2021 +0100
drivers/bitbang: add support to switch to/from dormant state
While there, replace the SWD_CMD_PARK macro to the magic number.
Change-Id: Id9094dcb2b010b9e894a5ed9e4a99d2287e5969c
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6691
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/jtag/drivers/bitbang.c b/src/jtag/drivers/bitbang.c
index 5c4febb20..d202a0596 100644
--- a/src/jtag/drivers/bitbang.c
+++ b/src/jtag/drivers/bitbang.c
@@ -434,10 +434,26 @@ static int bitbang_swd_switch_seq(enum swd_special_seq seq)
LOG_DEBUG("JTAG-to-SWD");
bitbang_swd_exchange(false, (uint8_t *)swd_seq_jtag_to_swd, 0, swd_seq_jtag_to_swd_len);
break;
+ case JTAG_TO_DORMANT:
+ LOG_DEBUG("JTAG-to-DORMANT");
+ bitbang_swd_exchange(false, (uint8_t *)swd_seq_jtag_to_dormant, 0, swd_seq_jtag_to_dormant_len);
+ break;
case SWD_TO_JTAG:
LOG_DEBUG("SWD-to-JTAG");
bitbang_swd_exchange(false, (uint8_t *)swd_seq_swd_to_jtag, 0, swd_seq_swd_to_jtag_len);
break;
+ case SWD_TO_DORMANT:
+ LOG_DEBUG("SWD-to-DORMANT");
+ bitbang_swd_exchange(false, (uint8_t *)swd_seq_swd_to_dormant, 0, swd_seq_swd_to_dormant_len);
+ break;
+ case DORMANT_TO_SWD:
+ LOG_DEBUG("DORMANT-to-SWD");
+ bitbang_swd_exchange(false, (uint8_t *)swd_seq_dormant_to_swd, 0, swd_seq_dormant_to_swd_len);
+ break;
+ case DORMANT_TO_JTAG:
+ LOG_DEBUG("DORMANT-to-JTAG");
+ bitbang_swd_exchange(false, (uint8_t *)swd_seq_dormant_to_jtag, 0, swd_seq_dormant_to_jtag_len);
+ break;
default:
LOG_ERROR("Sequence %d not supported", seq);
return ERROR_FAIL;
@@ -465,7 +481,7 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay
for (;;) {
uint8_t trn_ack_data_parity_trn[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)];
- cmd |= SWD_CMD_START | (1 << 7);
+ cmd |= SWD_CMD_START | SWD_CMD_PARK;
bitbang_swd_exchange(false, &cmd, 0, 8);
bitbang_interface->swdio_drive(false);
@@ -526,7 +542,7 @@ static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay
buf_set_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32, value);
buf_set_u32(trn_ack_data_parity_trn, 1 + 3 + 1 + 32, 1, parity_u32(value));
- cmd |= SWD_CMD_START | (1 << 7);
+ cmd |= SWD_CMD_START | SWD_CMD_PARK;
bitbang_swd_exchange(false, &cmd, 0, 8);
bitbang_interface->swdio_drive(false);
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/bitbang.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2021-11-20 14:30:28
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via ed44acce26edf259f5b238b972a6a4fe2597ca48 (commit)
from 0432ac83997c2e3aef18ab545be35a28ec6d8c11 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit ed44acce26edf259f5b238b972a6a4fe2597ca48
Author: Antonio Borneo <bor...@gm...>
Date: Thu Nov 11 16:42:51 2021 +0100
cmsis_dap: add support for dormant-to-jtag
Change-Id: I4a51f3772cd94d7dda5a66a1d13acd24d0d0c63c
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6690
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c
index 19649b71c..c0898fc30 100644
--- a/src/jtag/drivers/cmsis_dap.c
+++ b/src/jtag/drivers/cmsis_dap.c
@@ -1134,6 +1134,11 @@ static int cmsis_dap_swd_switch_seq(enum swd_special_seq seq)
s = swd_seq_dormant_to_swd;
s_len = swd_seq_dormant_to_swd_len;
break;
+ case DORMANT_TO_JTAG:
+ LOG_DEBUG("DORMANT-to-JTAG");
+ s = swd_seq_dormant_to_jtag;
+ s_len = swd_seq_dormant_to_jtag_len;
+ break;
default:
LOG_ERROR("Sequence %d not supported", seq);
return ERROR_FAIL;
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/cmsis_dap.c | 5 +++++
1 file changed, 5 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2021-11-20 14:29:22
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 0432ac83997c2e3aef18ab545be35a28ec6d8c11 (commit)
from caa16981364d747c1c71edaf156e8a4faa83b02b (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 0432ac83997c2e3aef18ab545be35a28ec6d8c11
Author: Antonio Borneo <bor...@gm...>
Date: Thu Nov 11 16:39:39 2021 +0100
arm_adi_v5: add missing enum DORMANT_TO_JTAG
Add the value DORMANT_TO_JTAG in the enum listing the SWJ-DP
switching sequences.
The corresponding bit-sequence is already available.
Change-Id: I6f1ffd29a8f5729ec70ce0303248bc251409d37d
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6689
Reviewed-by: Tomas Vanek <va...@fb...>
Tested-by: jenkins
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 0e1b95f50..fa0a78a7e 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -191,6 +191,7 @@ enum swd_special_seq {
SWD_TO_JTAG,
SWD_TO_DORMANT,
DORMANT_TO_SWD,
+ DORMANT_TO_JTAG,
};
/**
-----------------------------------------------------------------------
Summary of changes:
src/target/arm_adi_v5.h | 1 +
1 file changed, 1 insertion(+)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-11-18 21:14:41
|
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generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
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- Log -----------------------------------------------------------------
commit caa16981364d747c1c71edaf156e8a4faa83b02b
Author: Andreas Fritiofson <and...@gm...>
Date: Mon Nov 8 18:09:56 2021 +0100
cortex_m: Restore fast register reads if no polling is needed
If the target is in a state where S_REGRDY polling is necessary (slow
clock, low power state...?), OpenOCD will continue to use the slow
path even if the condition is temporary and the target at a later
point would be capable of fast reads again.
Revert to fast reads if a full register dump can be made without need
for polling any of the registers; presumably it will succeed the next
time too.
Change-Id: I557f0d90b7ce6f9d81aa409b6400fc9c83d16008
Signed-off-by: Andreas Fritiofson <and...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6678
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 82d5eff80..721cf0a24 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -183,6 +183,7 @@ static int cortex_m_load_core_reg_u32(struct target *target,
cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
if (cortex_m->dcb_dhcsr & S_REGRDY)
break;
+ cortex_m->slow_register_read = true; /* Polling (still) needed. */
if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) {
LOG_ERROR("Timeout waiting for DCRDR transfer ready");
return ERROR_TIMEOUT_REACHED;
@@ -204,9 +205,14 @@ static int cortex_m_load_core_reg_u32(struct target *target,
static int cortex_m_slow_read_all_regs(struct target *target)
{
+ struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = target_to_armv7m(target);
const unsigned int num_regs = armv7m->arm.core_cache->num_regs;
+ /* Opportunistically restore fast read, it'll revert to slow
+ * if any register needed polling in cortex_m_load_core_reg_u32(). */
+ cortex_m->slow_register_read = false;
+
for (unsigned int reg_id = 0; reg_id < num_regs; reg_id++) {
struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
if (r->exist) {
@@ -215,6 +221,10 @@ static int cortex_m_slow_read_all_regs(struct target *target)
return retval;
}
}
+
+ if (!cortex_m->slow_register_read)
+ LOG_DEBUG("Switching back to fast register reads");
+
return ERROR_OK;
}
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_m.c | 10 ++++++++++
1 file changed, 10 insertions(+)
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- Log -----------------------------------------------------------------
commit 88f429ead019fd6df96ec15f0d897385f3cef0d0
Author: Tomas Vanek <va...@fb...>
Date: Tue Feb 5 09:39:11 2019 +0100
target/cortex_m: faster reading of all CPU registers
Without the change cortex_m_debug_entry() reads all registers
calling cortex_m_load_core_reg_u32() for each register with
a poor usage of JTAG/SWD queue.
It is time consuming, especially on an USB FS based adapter.
Moreover if target_request debugmsgs are enabled, DCB_DCRDR
is saved and restored on each register read.
This change introduces cortex_m_fast_read_all_regs()
which queues all register reads and a single dap_run() transaction
does all work.
cortex_m_fast_read_all_regs() reads all registers unconditionally
regardless register cache is valid or not. This is a difference
from the original cortex_m_debug_entry() code.
cortex_m_debug_entry times from -d3 log, Cortex-M4F and CMSIS-DAP
(Kinetis K28F-FRDM kit)
target_request | time [ms]
debugmsgs | without the change | with the change
---------------+--------------------+-----------------
disable | 186 | 27
enable | 232 | 29
Added checking of DHCSR.S_REGRDY flag. If "not ready" is seen,
cortex_m->slow_register_read is set and fallback to the old
register read method cortex_m_slow_read_all_regs() is used
instead of cortex_m_fast_read_all_regs().
Change-Id: I0665d94b97ede217394640871dc451ec93410254
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/5321
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <and...@gm...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index ffc8ca875..0a51ad4d6 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -251,7 +251,7 @@ static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
return ERROR_OK;
}
-static uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
+uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
{
switch (arm_reg_id) {
case ARMV7M_R0 ... ARMV7M_R14:
@@ -289,7 +289,7 @@ static uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
}
}
-static bool armv7m_map_reg_packing(unsigned int arm_reg_id,
+bool armv7m_map_reg_packing(unsigned int arm_reg_id,
unsigned int *reg32_id, uint32_t *offset)
{
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 2816a9145..d33e57492 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -309,6 +309,11 @@ int armv7m_invalidate_core_regs(struct target *target);
int armv7m_restore_context(struct target *target);
+uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id);
+
+bool armv7m_map_reg_packing(unsigned int arm_reg_id,
+ unsigned int *reg32_id, uint32_t *offset);
+
int armv7m_checksum_memory(struct target *target,
target_addr_t address, uint32_t count, uint32_t *checksum);
int armv7m_blank_check_memory(struct target *target,
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index ba7bc17b5..82d5eff80 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -202,6 +202,163 @@ static int cortex_m_load_core_reg_u32(struct target *target,
return retval;
}
+static int cortex_m_slow_read_all_regs(struct target *target)
+{
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ const unsigned int num_regs = armv7m->arm.core_cache->num_regs;
+
+ for (unsigned int reg_id = 0; reg_id < num_regs; reg_id++) {
+ struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
+ if (r->exist) {
+ int retval = armv7m->arm.read_core_reg(target, r, reg_id, ARM_MODE_ANY);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+ }
+ return ERROR_OK;
+}
+
+static int cortex_m_queue_reg_read(struct target *target, uint32_t regsel,
+ uint32_t *reg_value, uint32_t *dhcsr)
+{
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ int retval;
+
+ retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DHCSR, dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, reg_value);
+}
+
+static int cortex_m_fast_read_all_regs(struct target *target)
+{
+ struct cortex_m_common *cortex_m = target_to_cm(target);
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ int retval;
+ uint32_t dcrdr;
+
+ /* because the DCB_DCRDR is used for the emulated dcc channel
+ * we have to save/restore the DCB_DCRDR when used */
+ if (target->dbg_msg_enabled) {
+ retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ const unsigned int num_regs = armv7m->arm.core_cache->num_regs;
+ const unsigned int n_r32 = ARMV7M_LAST_REG - ARMV7M_CORE_FIRST_REG + 1
+ + ARMV7M_FPU_LAST_REG - ARMV7M_FPU_FIRST_REG + 1;
+ /* we need one 32-bit word for each register except FP D0..D15, which
+ * need two words */
+ uint32_t r_vals[n_r32];
+ uint32_t dhcsr[n_r32];
+
+ unsigned int wi = 0; /* write index to r_vals and dhcsr arrays */
+ unsigned int reg_id; /* register index in the reg_list, ARMV7M_R0... */
+ for (reg_id = 0; reg_id < num_regs; reg_id++) {
+ struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
+ if (!r->exist)
+ continue; /* skip non existent registers */
+
+ if (r->size <= 8) {
+ /* Any 8-bit or shorter register is unpacked from a 32-bit
+ * container register. Skip it now. */
+ continue;
+ }
+
+ uint32_t regsel = armv7m_map_id_to_regsel(reg_id);
+ retval = cortex_m_queue_reg_read(target, regsel, &r_vals[wi],
+ &dhcsr[wi]);
+ if (retval != ERROR_OK)
+ return retval;
+ wi++;
+
+ assert(r->size == 32 || r->size == 64);
+ if (r->size == 32)
+ continue; /* done with 32-bit register */
+
+ assert(reg_id >= ARMV7M_FPU_FIRST_REG && reg_id <= ARMV7M_FPU_LAST_REG);
+ /* the odd part of FP register (S1, S3...) */
+ retval = cortex_m_queue_reg_read(target, regsel + 1, &r_vals[wi],
+ &dhcsr[wi]);
+ if (retval != ERROR_OK)
+ return retval;
+ wi++;
+ }
+
+ assert(wi <= n_r32);
+
+ retval = dap_run(armv7m->debug_ap->dap);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (target->dbg_msg_enabled) {
+ /* restore DCB_DCRDR - this needs to be in a separate
+ * transaction otherwise the emulated DCC channel breaks */
+ retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ bool not_ready = false;
+ for (unsigned int i = 0; i < wi; i++) {
+ if ((dhcsr[i] & S_REGRDY) == 0) {
+ not_ready = true;
+ LOG_DEBUG("Register %u was not ready during fast read", i);
+ }
+ cortex_m_cumulate_dhcsr_sticky(cortex_m, dhcsr[i]);
+ }
+
+ if (not_ready) {
+ /* Any register was not ready,
+ * fall back to slow read with S_REGRDY polling */
+ return ERROR_TIMEOUT_REACHED;
+ }
+
+ LOG_DEBUG("read %u 32-bit registers", wi);
+
+ unsigned int ri = 0; /* read index from r_vals array */
+ for (reg_id = 0; reg_id < num_regs; reg_id++) {
+ struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
+ if (!r->exist)
+ continue; /* skip non existent registers */
+
+ r->dirty = false;
+
+ unsigned int reg32_id;
+ uint32_t offset;
+ if (armv7m_map_reg_packing(reg_id, ®32_id, &offset)) {
+ /* Unpack a partial register from 32-bit container register */
+ struct reg *r32 = &armv7m->arm.core_cache->reg_list[reg32_id];
+
+ /* The container register ought to precede all regs unpacked
+ * from it in the reg_list. So the value should be ready
+ * to unpack */
+ assert(r32->valid);
+ buf_cpy(r32->value + offset, r->value, r->size);
+
+ } else {
+ assert(r->size == 32 || r->size == 64);
+ buf_set_u32(r->value, 0, 32, r_vals[ri++]);
+
+ if (r->size == 64) {
+ assert(reg_id >= ARMV7M_FPU_FIRST_REG && reg_id <= ARMV7M_FPU_LAST_REG);
+ /* the odd part of FP register (S1, S3...) */
+ buf_set_u32(r->value + 4, 0, 32, r_vals[ri++]);
+ }
+ }
+ r->valid = true;
+ }
+ assert(ri == wi);
+
+ return retval;
+}
+
static int cortex_m_store_core_reg_u32(struct target *target,
uint32_t regsel, uint32_t value)
{
@@ -610,7 +767,6 @@ static int cortex_m_examine_exception_reason(struct target *target)
static int cortex_m_debug_entry(struct target *target)
{
- int i;
uint32_t xPSR;
int retval;
struct cortex_m_common *cortex_m = target_to_cm(target);
@@ -646,16 +802,21 @@ static int cortex_m_debug_entry(struct target *target)
secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
}
- /* Examine target state and mode
- * First load register accessible through core debug port */
- int num_regs = arm->core_cache->num_regs;
-
- for (i = 0; i < num_regs; i++) {
- r = &armv7m->arm.core_cache->reg_list[i];
- if (r->exist && !r->valid)
- arm->read_core_reg(target, r, i, ARM_MODE_ANY);
+ /* Load all registers to arm.core_cache */
+ if (!cortex_m->slow_register_read) {
+ retval = cortex_m_fast_read_all_regs(target);
+ if (retval == ERROR_TIMEOUT_REACHED) {
+ cortex_m->slow_register_read = true;
+ LOG_DEBUG("Switched to slow register read");
+ }
}
+ if (cortex_m->slow_register_read)
+ retval = cortex_m_slow_read_all_regs(target);
+
+ if (retval != ERROR_OK)
+ return retval;
+
r = arm->cpsr;
xPSR = buf_get_u32(r->value, 0, 32);
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index a5dfbf856..57ef1e7e8 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -238,6 +238,8 @@ struct cortex_m_common {
const struct cortex_m_part_info *core_info;
struct armv7m_common armv7m;
+ bool slow_register_read; /* A register has not been ready, poll S_REGRDY */
+
int apsel;
/* Whether this target has the erratum that makes C_MASKINTS not apply to
-----------------------------------------------------------------------
Summary of changes:
src/target/armv7m.c | 4 +-
src/target/armv7m.h | 5 ++
src/target/cortex_m.c | 179 +++++++++++++++++++++++++++++++++++++++++++++++---
src/target/cortex_m.h | 2 +
4 files changed, 179 insertions(+), 11 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-11-18 21:09:46
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 65d7629183288595177301ce262dac4ba716618b (commit)
from 0dcf95c7171b702d70ec326f8c1a63cbc9255b6f (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 65d7629183288595177301ce262dac4ba716618b
Author: Antonio Borneo <bor...@gm...>
Date: Mon Oct 14 19:03:48 2019 +0200
cortex_m: poll S_REGRDY on register r/w
Accordingly to arm documentation [1], chapter C1.6.4, the
operation to read/write from/to core registers can require time,
and the specific flag DHCSR.S_REGRDY has to be polled to verify
that the operation has been completed.
The lack of check on S_REGRDY causes OpenOCD to fail handling
correctly the core registers on a Cortex-M4 emulated in a slow
FPGA, and it could also fail on devices clocked at very low speed
while using a fast adapter.
Poll S_REGRDY as specified in [1] while either reading or writing
the core registers.
A timeout of 0.5s is added. This could still be too small in some
extremely slow cases, but at least now we log the timeout event,
which can help tracking down such odd issue.
During register read include in the polling loop the read of DCRSR
and to flush the JTAG queue only once.
During register write, relax the write in DCRSR by removing the
atomicity that is now useless since followed by the atomic read to
S_REGRDY.
During register read include the read of DCRSR inside the polling
loop to relax the read of S_REGRDY since followed by the atomic
read to DCRSR.
This change has the drawback of adding other transfers to the
adapter while reading/writing the registers, so it is expected to
introduce some speed degradation during step-by-step.
[1] DDI0403E - "ARMv7-M Architecture Reference Manual"
Change-Id: I61f454248f11a3bec6dcf4c58a50c5c996d7ef81
Signed-off-by: Antonio Borneo <bor...@gm...>
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/5319
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 655825227..ba7bc17b5 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -53,6 +53,9 @@
* any longer.
*/
+/* Timeout for register r/w */
+#define DHCSR_S_REGRDY_TIMEOUT (500)
+
/* Supported Cortex-M Cores */
static const struct cortex_m_part_info cortex_m_parts[] = {
{
@@ -148,9 +151,11 @@ static int cortex_m_read_dhcsr_atomic_sticky(struct target *target)
static int cortex_m_load_core_reg_u32(struct target *target,
uint32_t regsel, uint32_t *value)
{
+ struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = target_to_armv7m(target);
int retval;
- uint32_t dcrdr;
+ uint32_t dcrdr, tmp_value;
+ int64_t then;
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
@@ -164,9 +169,28 @@ static int cortex_m_load_core_reg_u32(struct target *target,
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
- if (retval != ERROR_OK)
- return retval;
+ /* check if value from register is ready and pre-read it */
+ then = timeval_ms();
+ while (1) {
+ retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DHCSR,
+ &cortex_m->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR,
+ &tmp_value);
+ if (retval != ERROR_OK)
+ return retval;
+ cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
+ if (cortex_m->dcb_dhcsr & S_REGRDY)
+ break;
+ if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) {
+ LOG_ERROR("Timeout waiting for DCRDR transfer ready");
+ return ERROR_TIMEOUT_REACHED;
+ }
+ keep_alive();
+ }
+
+ *value = tmp_value;
if (target->dbg_msg_enabled) {
/* restore DCB_DCRDR - this needs to be in a separate
@@ -181,9 +205,11 @@ static int cortex_m_load_core_reg_u32(struct target *target,
static int cortex_m_store_core_reg_u32(struct target *target,
uint32_t regsel, uint32_t value)
{
+ struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = target_to_armv7m(target);
int retval;
uint32_t dcrdr;
+ int64_t then;
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
@@ -197,10 +223,27 @@ static int cortex_m_store_core_reg_u32(struct target *target,
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regsel | DCRSR_WNR);
+ retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel | DCRSR_WNR);
if (retval != ERROR_OK)
return retval;
+ /* check if value is written into register */
+ then = timeval_ms();
+ while (1) {
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
+ &cortex_m->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
+ cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
+ if (cortex_m->dcb_dhcsr & S_REGRDY)
+ break;
+ if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) {
+ LOG_ERROR("Timeout waiting for DCRDR transfer ready");
+ return ERROR_TIMEOUT_REACHED;
+ }
+ keep_alive();
+ }
+
if (target->dbg_msg_enabled) {
/* restore DCB_DCRDR - this needs to be in a separate
* transaction otherwise the emulated DCC channel breaks */
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_m.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 48 insertions(+), 5 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-11-18 21:08:15
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- Log -----------------------------------------------------------------
commit 0dcf95c7171b702d70ec326f8c1a63cbc9255b6f
Author: Tomas Vanek <va...@fb...>
Date: Thu Apr 22 10:41:50 2021 +0200
target/cortex_m: cumulate DHCSR sticky bits
DCB DHCSR register contains S_RETIRE_ST and S_RESET_ST bits cleared
on a read.
The change introduces a helper function cortex_m_cumulate_dhcsr_sticky().
Call this function each time DHCSR is read to preserve S_RESET_ST state
in the case of a reset event was detected.
Introduce cortex_m_read_dhcsr_atomic_sticky() convenience helper to
read DHCSR, store it to cortex_m->dcb_dhcsr and cumulate sticky bits.
The cumulated state of S_RESET_ST is read and cleared in cortex_m_poll()
Change-Id: Ib679599f850fd219fb9418c6ff32eed7cf5740da
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6180
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index d4affa683..655825227 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -118,6 +118,33 @@ static int cortex_m_store_core_reg_u32(struct target *target,
uint32_t num, uint32_t value);
static void cortex_m_dwt_free(struct target *target);
+/** DCB DHCSR register contains S_RETIRE_ST and S_RESET_ST bits cleared
+ * on a read. Call this helper function each time DHCSR is read
+ * to preserve S_RESET_ST state in case of a reset event was detected.
+ */
+static inline void cortex_m_cumulate_dhcsr_sticky(struct cortex_m_common *cortex_m,
+ uint32_t dhcsr)
+{
+ cortex_m->dcb_dhcsr_cumulated_sticky |= dhcsr;
+}
+
+/** Read DCB DHCSR register to cortex_m->dcb_dhcsr and cumulate
+ * sticky bits in cortex_m->dcb_dhcsr_cumulated_sticky
+ */
+static int cortex_m_read_dhcsr_atomic_sticky(struct target *target)
+{
+ struct cortex_m_common *cortex_m = target_to_cm(target);
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+
+ int retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
+ &cortex_m->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
+
+ cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
+ return ERROR_OK;
+}
+
static int cortex_m_load_core_reg_u32(struct target *target,
uint32_t regsel, uint32_t *value)
{
@@ -362,11 +389,12 @@ static int cortex_m_endreset_event(struct target *target)
if (retval != ERROR_OK)
return retval;
- /* Enable debug requests */
- retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+ retval = cortex_m_read_dhcsr_atomic_sticky(target);
if (retval != ERROR_OK)
return retval;
+
if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
+ /* Enable debug requests */
retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
if (retval != ERROR_OK)
return retval;
@@ -428,7 +456,9 @@ static int cortex_m_endreset_event(struct target *target)
register_cache_invalidate(armv7m->arm.core_cache);
/* make sure we have latest dhcsr flags */
- retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+ retval = cortex_m_read_dhcsr_atomic_sticky(target);
+ if (retval != ERROR_OK)
+ return retval;
return retval;
}
@@ -552,7 +582,8 @@ static int cortex_m_debug_entry(struct target *target)
cortex_m_set_maskints_for_halt(target);
cortex_m_clear_halt(target);
- retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+
+ retval = cortex_m_read_dhcsr_atomic_sticky(target);
if (retval != ERROR_OK)
return retval;
@@ -636,7 +667,7 @@ static int cortex_m_poll(struct target *target)
struct armv7m_common *armv7m = &cortex_m->armv7m;
/* Read from Debug Halting Control and Status Register */
- retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+ retval = cortex_m_read_dhcsr_atomic_sticky(target);
if (retval != ERROR_OK) {
target->state = TARGET_UNKNOWN;
return retval;
@@ -657,12 +688,13 @@ static int cortex_m_poll(struct target *target)
detected_failure = ERROR_FAIL;
/* refresh status bits */
- retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+ retval = cortex_m_read_dhcsr_atomic_sticky(target);
if (retval != ERROR_OK)
return retval;
}
- if (cortex_m->dcb_dhcsr & S_RESET_ST) {
+ if (cortex_m->dcb_dhcsr_cumulated_sticky & S_RESET_ST) {
+ cortex_m->dcb_dhcsr_cumulated_sticky &= ~S_RESET_ST;
if (target->state != TARGET_RESET) {
target->state = TARGET_RESET;
LOG_INFO("%s: external reset detected", target_name(target));
@@ -709,7 +741,12 @@ static int cortex_m_poll(struct target *target)
}
if (target->state == TARGET_UNKNOWN) {
- /* check if processor is retiring instructions or sleeping */
+ /* Check if processor is retiring instructions or sleeping.
+ * Unlike S_RESET_ST here we test if the target *is* running now,
+ * not if it has been running (possibly in the past). Instructions are
+ * typically processed much faster than OpenOCD polls DHCSR so S_RETIRE_ST
+ * is read always 1. That's the reason not to use dcb_dhcsr_cumulated_sticky.
+ */
if (cortex_m->dcb_dhcsr & S_RETIRE_ST || cortex_m->dcb_dhcsr & S_SLEEP) {
target->state = TARGET_RUNNING;
retval = ERROR_OK;
@@ -811,7 +848,7 @@ static int cortex_m_soft_reset_halt(struct target *target)
register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
while (timeout < 100) {
- retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+ retval = cortex_m_read_dhcsr_atomic_sticky(target);
if (retval == ERROR_OK) {
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
&cortex_m->nvic_dfsr);
@@ -1076,9 +1113,7 @@ static int cortex_m_step(struct target *target, int current,
/* Wait for pending handlers to complete or timeout */
do {
- retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
- DCB_DHCSR,
- &cortex_m->dcb_dhcsr);
+ retval = cortex_m_read_dhcsr_atomic_sticky(target);
if (retval != ERROR_OK) {
target->state = TARGET_UNKNOWN;
return retval;
@@ -1113,7 +1148,7 @@ static int cortex_m_step(struct target *target, int current,
}
}
- retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+ retval = cortex_m_read_dhcsr_atomic_sticky(target);
if (retval != ERROR_OK)
return retval;
@@ -1191,8 +1226,8 @@ static int cortex_m_assert_reset(struct target *target)
}
/* Enable debug requests */
- int retval;
- retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+ int retval = cortex_m_read_dhcsr_atomic_sticky(target);
+
/* Store important errors instead of failing and proceed to reset assert */
if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
@@ -2136,11 +2171,13 @@ int cortex_m_examine(struct target *target)
armv7m->debug_ap->tar_autoincr_block = (1 << 12);
}
- /* Enable debug requests */
retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
+ cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
+
if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
+ /* Enable debug requests */
uint32_t dhcsr = (cortex_m->dcb_dhcsr | C_DEBUGEN) & ~(C_HALT | C_STEP | C_MASKINTS);
retval = target_write_u32(target, DCB_DHCSR, DBGKEY | (dhcsr & 0x0000FFFFUL));
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 16fc8ab70..a5dfbf856 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -213,6 +213,7 @@ struct cortex_m_common {
/* Context information */
uint32_t dcb_dhcsr;
+ uint32_t dcb_dhcsr_cumulated_sticky;
uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
commit 111dcbeb1a54f629866449efe0c3b17ec1ab8957
Author: Tomas Vanek <va...@fb...>
Date: Mon Nov 8 15:40:24 2021 +0100
target/cortex_m: use cortex_m->dcb_dhcsr in cortex_m_soft_reset_halt()
cortex_m->dcb_dhcsr caches status of DHCSR register.
Use it instead of local variable in cortex_m_soft_reset_halt()
like in other code.
Extracted from [1].
[1] Antonio Borneo: 6207: cortex_m: rework handling of dcb_dhcsr
Link: https://review.openocd.org/c/openocd/+/6207
Change-Id: I9a0aeba0b6b0b4969f05f4a32fc2fc8d244f56ca
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6677
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index f68260603..d4affa683 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -776,7 +776,6 @@ static int cortex_m_soft_reset_halt(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
- uint32_t dcb_dhcsr = 0;
int retval, timeout = 0;
/* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
@@ -812,25 +811,23 @@ static int cortex_m_soft_reset_halt(struct target *target)
register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
while (timeout < 100) {
- retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval == ERROR_OK) {
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
&cortex_m->nvic_dfsr);
if (retval != ERROR_OK)
return retval;
- if ((dcb_dhcsr & S_HALT)
+ if ((cortex_m->dcb_dhcsr & S_HALT)
&& (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
- LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
- "DFSR 0x%08x",
- (unsigned) dcb_dhcsr,
- (unsigned) cortex_m->nvic_dfsr);
+ LOG_DEBUG("system reset-halted, DHCSR 0x%08" PRIx32 ", DFSR 0x%08" PRIx32,
+ cortex_m->dcb_dhcsr, cortex_m->nvic_dfsr);
cortex_m_poll(target);
/* FIXME restore user's vector catch config */
return ERROR_OK;
} else
LOG_DEBUG("waiting for system reset-halt, "
- "DHCSR 0x%08x, %d ms",
- (unsigned) dcb_dhcsr, timeout);
+ "DHCSR 0x%08" PRIx32 ", %d ms",
+ cortex_m->dcb_dhcsr, timeout);
}
timeout++;
alive_sleep(1);
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_m.c | 82 ++++++++++++++++++++++++++++++++++++---------------
src/target/cortex_m.h | 1 +
2 files changed, 59 insertions(+), 24 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2021-11-18 21:08:03
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b502947a1427aabe9c4e9ab0b3dd9e45f51e5b62 (commit)
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- Log -----------------------------------------------------------------
commit b502947a1427aabe9c4e9ab0b3dd9e45f51e5b62
Author: Tomas Vanek <va...@fb...>
Date: Mon Nov 8 14:24:33 2021 +0100
cortex_m: use cortex_m_write_debug_halt_mask() in cortex_m_single_step_core()
cortex_m_single_step_core() used mem_ap_write_atomic_u32() to manipulate
dhcsr bits unlike the rest of code, where a specialized function
cortex_m_write_debug_halt_mask() takes place.
Unify setting of dhcsr bits and use cortex_m_write_debug_halt_mask() here as well.
Extracted from [1].
[1] Antonio Borneo: 6207: cortex_m: rework handling of dcb_dhcsr
Link: https://review.openocd.org/c/openocd/+/6207
Change-Id: I9ef05ce88a9dce42e1d3d5404a4fe87ec86b5fe8
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6676
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 3412c5677..f68260603 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -301,7 +301,6 @@ static int cortex_m_clear_halt(struct target *target)
static int cortex_m_single_step_core(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
- struct armv7m_common *armv7m = &cortex_m->armv7m;
int retval;
/* Mask interrupts before clearing halt, if not done already. This avoids
@@ -309,13 +308,11 @@ static int cortex_m_single_step_core(struct target *target)
* HALT can put the core into an unknown state.
*/
if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
- retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
- DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
+ retval = cortex_m_write_debug_halt_mask(target, C_MASKINTS, 0);
if (retval != ERROR_OK)
return retval;
}
- retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
- DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
+ retval = cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG(" ");
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_m.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2021-11-18 02:18:14
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via aa8a79809ef9e6b97d45da60508d902da0e3270e (commit)
from 5a0b4889d0d46639b38effd24102f0d5fca1ca31 (commit)
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- Log -----------------------------------------------------------------
commit aa8a79809ef9e6b97d45da60508d902da0e3270e
Author: Janco Kock <ja...@fa...>
Date: Fri Oct 22 16:06:22 2021 +0200
flash/nor/at91samd: Add SAMR35J18B support
Add support for the mcu SAMR35J18B
Signed-off-by: Janco <ja...@fa...>
Change-Id: I45d801485ad1c16d1b3086516a2b6d71d13f3fc7
Reviewed-on: https://review.openocd.org/c/openocd/+/6664
Reviewed-by: Tomas Vanek <va...@fb...>
Tested-by: jenkins
diff --git a/src/flash/nor/at91samd.c b/src/flash/nor/at91samd.c
index 5cefd1766..a8fab486c 100644
--- a/src/flash/nor/at91samd.c
+++ b/src/flash/nor/at91samd.c
@@ -251,6 +251,7 @@ static const struct samd_part saml21_parts[] = {
/* SAMR34/R35 parts have integrated SAML21 with a lora radio */
{ 0x28, "SAMR34J18", 256, 32 },
+ { 0x2B, "SAMR35J18", 256, 32 },
};
/* Known SAML22 parts. */
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/at91samd.c | 1 +
1 file changed, 1 insertion(+)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-11-15 15:36:24
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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commit 5a0b4889d0d46639b38effd24102f0d5fca1ca31
Author: asier70 <as...@gm...>
Date: Wed Sep 1 22:00:51 2021 +0200
flash/nor/stm32f1x: Add support for GD32E23x
GD32E23x from GigaDevice is cortex-M23 microcontroller and it can work with the stm32f1x driver.
Modifications are similar to this done for GD32F1x0 in #6164 (https://review.openocd.org/c/openocd/+/6164).
Configuration file is added because its cortex-M23 CPU ID is different.
I think that GigaDevice microcontrollers should be handled in an independent unit to separate them from STM32,
but nowadays quick solution is welcome.
Signed-off-by: asier70Andrzej SierżÄga <as...@gm...>
Change-Id: I91f31f5f66808bc50a8f607ac2c107e6b7c5e2b8
Reviewed-on: https://review.openocd.org/c/openocd/+/6527
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index c7ffc4f42..a6da1675e 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -7120,8 +7120,8 @@ applied to all of them.
@deffn {Flash Driver} {stm32f1x}
All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
-from STMicroelectronics and all members of the GD32F1x0 and GD32F3x0 microcontroller
-families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4 cores.
+from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller
+families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores.
The driver automatically recognizes a number of these chips using
the chip identification register, and autoconfigures itself.
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index 3bda9bc20..6744779e9 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -640,6 +640,9 @@ static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
case CORTEX_M4_PARTNO: /* STM32F3x devices */
device_id_register = 0xE0042000;
break;
+ case CORTEX_M23_PARTNO: /* GD32E23x devices */
+ device_id_register = 0x40015800;
+ break;
default:
LOG_ERROR("Cannot identify target as a stm32x");
return ERROR_FAIL;
@@ -674,6 +677,9 @@ static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_i
case CORTEX_M4_PARTNO: /* STM32F3x devices */
flash_size_reg = 0x1FFFF7CC;
break;
+ case CORTEX_M23_PARTNO: /* GD32E23x devices */
+ flash_size_reg = 0x1FFFF7E0;
+ break;
default:
LOG_ERROR("Cannot identify target as a stm32x");
return ERROR_FAIL;
@@ -756,8 +762,8 @@ static int stm32x_probe(struct flash_bank *bank)
page_size = 1024;
stm32x_info->ppage_size = 4;
max_flash_size_in_kb = 128;
- /* GigaDevice GD32F1x0 & GD32F3x0 series devices share DEV_ID
- with STM32F101/2/3 medium-density line,
+ /* GigaDevice GD32F1x0 & GD32F3x0 & GD32E23x series devices
+ share DEV_ID with STM32F101/2/3 medium-density line,
however they use a REV_ID different from any STM32 device.
The main difference is another offset of user option bits
(like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
@@ -774,6 +780,11 @@ static int stm32x_probe(struct flash_bank *bank)
stm32x_info->user_data_offset = 16;
stm32x_info->option_offset = 6;
break;
+ case 0x1909: /* gd32e23x */
+ stm32x_info->user_data_offset = 16;
+ stm32x_info->option_offset = 6;
+ max_flash_size_in_kb = 64;
+ break;
}
break;
case 0x412: /* stm32f1x low-density */
@@ -984,6 +995,10 @@ static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *c
device_str = "GD32F3x0";
break;
+ case 0x1909: /* gd32e23x */
+ device_str = "GD32E23x";
+ break;
+
case 0x2000:
rev_str = "B";
break;
diff --git a/src/flash/startup.tcl b/src/flash/startup.tcl
index 93ef82ce6..16cbe1950 100644
--- a/src/flash/startup.tcl
+++ b/src/flash/startup.tcl
@@ -121,3 +121,6 @@ proc stm32l5x args { eval stm32l4x $args }
proc stm32u5x args { eval stm32l4x $args }
proc stm32wbx args { eval stm32l4x $args }
proc stm32wlx args { eval stm32l4x $args }
+
+# gd32e23x uses the same flash driver as the stm32f1x
+proc gd32e23x args { eval stm32f1x $args }
diff --git a/tcl/target/gd32e23x.cfg b/tcl/target/gd32e23x.cfg
new file mode 100644
index 000000000..250427413
--- /dev/null
+++ b/tcl/target/gd32e23x.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for GigaDevice gd32e23x Cortex-M23 Series
+
+# https://www.gigadevice.com/microcontroller/gd32e230c8t6/
+
+#
+# gd32e23x devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME gd32e23x
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB (as found on some GD32E230s)
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x1000
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+ set _FLASH_SIZE $FLASH_SIZE
+} else {
+ # autodetect size
+ set _FLASH_SIZE 0
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # this is the SW-DP tap id not the jtag tap id
+ set _CPUTAPID 0x0bf11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
+
+# SWD speed (may be updated to higher value in board config file)
+adapter speed 1000
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+ # if srst is not fitted use SYSRESETREQ to
+ # perform a soft reset
+ cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+ # Debug clock enable
+ # RCU_APB2EN |= DBGMCUEN
+ mmw 0x40021018 0x00400000 0
+
+ # Stop watchdog counters during halt
+ # DBG_CTL0 |= WWDGT_HOLD | FWDGT_HOLD | STB_HOLD | DSLP_HOLD | SLP_HOLD
+ mmw 0x40015804 0x00000307 0
+}
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 4 +--
src/flash/nor/stm32f1x.c | 19 ++++++++++--
src/flash/startup.tcl | 3 ++
tcl/target/{stm32f1x.cfg => gd32e23x.cfg} | 51 +++++++++++--------------------
4 files changed, 40 insertions(+), 37 deletions(-)
copy tcl/target/{stm32f1x.cfg => gd32e23x.cfg} (54%)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-11-13 22:36:27
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
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- Log -----------------------------------------------------------------
commit a498a3deaaec7ee87d73cf753bdddefaf4779666
Author: Antonio Borneo <bor...@gm...>
Date: Sat Nov 13 14:38:21 2021 +0100
jtagspi: fix build on MacOS
Commit be57b0ab847e ("Update jtagspi driver for 1-, 2- and 4-byte
addresses") introduces two incorrect format string for uint32_t
data types.
This cause build failure on MacOS:
src/flash/nor/jtagspi.c:474:35: error: format specifies type 'unsigned char'
but the argument has type 'uint32_t' (aka 'unsigned int') [-Werror,-Wformat]
LOG_DEBUG("status=0x%02" PRIx8, *status);
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
src/flash/nor/jtagspi.c:513:65: error: format specifies type 'unsigned char'
but the argument has type 'uint32_t' (aka 'unsigned int') [-Werror,-Wformat]
LOG_ERROR("Cannot enable write to flash. Status=0x%02" PRIx8, status);
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~
Fix the format string.
Change-Id: I209053317c8b26c35c6f11be0553ccccc698c551
Signed-off-by: Antonio Borneo <bor...@gm...>
Fixes: be57b0ab847e ("Update jtagspi driver for 1-, 2- and 4-byte addresses")
Reviewed-on: https://review.openocd.org/c/openocd/+/6701
Reviewed-by: Tomas Vanek <va...@fb...>
Tested-by: jenkins
diff --git a/src/flash/nor/jtagspi.c b/src/flash/nor/jtagspi.c
index 9d377ce70..a5672c63e 100644
--- a/src/flash/nor/jtagspi.c
+++ b/src/flash/nor/jtagspi.c
@@ -471,7 +471,7 @@ static int jtagspi_read_status(struct flash_bank *bank, uint32_t *status)
int err = jtagspi_cmd(bank, SPIFLASH_READ_STATUS, NULL, 0, &buf, -1);
if (err == ERROR_OK) {
*status = buf;
- LOG_DEBUG("status=0x%02" PRIx8, *status);
+ LOG_DEBUG("status=0x%02" PRIx32, *status);
}
return err;
}
@@ -510,7 +510,7 @@ static int jtagspi_write_enable(struct flash_bank *bank)
return retval;
if ((status & SPIFLASH_WE_BIT) == 0) {
- LOG_ERROR("Cannot enable write to flash. Status=0x%02" PRIx8, status);
+ LOG_ERROR("Cannot enable write to flash. Status=0x%02" PRIx32, status);
return ERROR_FAIL;
}
return ERROR_OK;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/jtagspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-11-13 10:53:52
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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- Log -----------------------------------------------------------------
commit 9d574aa3fab6e6d802fab4ededb24b73542ef2b9
Author: Tarek BOCHKATI <tar...@gm...>
Date: Wed Oct 20 12:13:01 2021 +0100
flash/stm32h7x: don't read flash size using the H74/H75x CPU2
CPU2 (Cortex-M4) cannot read flash size register.
assume the maximum flash size without triggering an error message
Change-Id: I5c3328b7cc42e3aa57165075021227d7936f3d26
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6670
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c
index e6a4efc19..a3e304351 100644
--- a/src/flash/nor/stm32h7x.c
+++ b/src/flash/nor/stm32h7x.c
@@ -21,7 +21,7 @@
#include "imp.h"
#include <helper/binarybuffer.h>
#include <target/algorithm.h>
-#include <target/armv7m.h>
+#include <target/cortex_m.h>
/* Erase time can be as high as 1000ms, 10x this and it's toast... */
@@ -759,6 +759,7 @@ static int stm32x_read_id_code(struct flash_bank *bank, uint32_t *id)
static int stm32x_probe(struct flash_bank *bank)
{
struct target *target = bank->target;
+ struct cortex_m_common *cortex_m = target_to_cm(target);
struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
uint16_t flash_size_in_kb;
uint32_t device_id;
@@ -797,15 +798,19 @@ static int stm32x_probe(struct flash_bank *bank)
LOG_DEBUG("flash_regs_base: 0x%" PRIx32, stm32x_info->flash_regs_base);
/* get flash size from target */
- retval = target_read_u16(target, stm32x_info->part_info->fsize_addr, &flash_size_in_kb);
+ /* STM32H74x/H75x, the second core (Cortex-M4) cannot read the flash size */
+ retval = ERROR_FAIL;
+ if (device_id == DEVID_STM32H74_H75XX && cortex_m->core_info->partno == CORTEX_M4_PARTNO)
+ LOG_WARNING("%s cannot read the flash size register", target_name(target));
+ else
+ retval = target_read_u16(target, stm32x_info->part_info->fsize_addr, &flash_size_in_kb);
+
if (retval != ERROR_OK) {
/* read error when device has invalid value, set max flash size */
flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
+ LOG_INFO("assuming %" PRIu16 "k flash", flash_size_in_kb);
} else
- LOG_INFO("flash size probed value %" PRIu16, flash_size_in_kb);
-
-
-
+ LOG_INFO("flash size probed value %" PRIu16 "k", flash_size_in_kb);
/* setup bank size */
const uint32_t bank1_base = FLASH_BANK0_ADDRESS;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32h7x.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-11-13 10:53:28
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 50f977b0581408891ef8dbeeda3fc64e3ef0619a (commit)
from 3f778c7c63cbd293c30144a88c041f845f1eb46d (commit)
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- Log -----------------------------------------------------------------
commit 50f977b0581408891ef8dbeeda3fc64e3ef0619a
Author: Tarek BOCHKATI <tar...@gm...>
Date: Wed Oct 20 12:10:44 2021 +0100
flash/stm32h7x: avoid using magic numbers for device ids
Change-Id: I4d682ee828404974abd9a42f98b840d77835cfe0
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6669
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c
index 89ba75dad..e6a4efc19 100644
--- a/src/flash/nor/stm32h7x.c
+++ b/src/flash/nor/stm32h7x.c
@@ -100,6 +100,11 @@
#define FLASH_REG_BASE_B0 0x52002000
#define FLASH_REG_BASE_B1 0x52002100
+/* Supported device IDs */
+#define DEVID_STM32H74_H75XX 0x450
+#define DEVID_STM32H7A_H7BXX 0x480
+#define DEVID_STM32H72_H73XX 0x483
+
struct stm32h7x_rev {
uint16_t rev;
const char *str;
@@ -139,24 +144,24 @@ enum stm32h7x_opt_rdp {
OPT_RDP_L2 = 0xcc
};
-static const struct stm32h7x_rev stm32_450_revs[] = {
+static const struct stm32h7x_rev stm32h74_h75xx_revs[] = {
{ 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2001, "X" }, { 0x2003, "V" },
};
-static const struct stm32h7x_rev stm32_480_revs[] = {
+static const struct stm32h7x_rev stm32h7a_h7bxx_revs[] = {
{ 0x1000, "A"},
};
-static const struct stm32h7x_rev stm32_483_revs[] = {
+static const struct stm32h7x_rev stm32h72_h73xx_revs[] = {
{ 0x1000, "A" }, { 0x1001, "Z" },
};
-static uint32_t stm32x_compute_flash_cr_450_483(uint32_t cmd, int snb)
+static uint32_t stm32h74_h75xx_compute_flash_cr(uint32_t cmd, int snb)
{
return cmd | (snb << 8);
}
-static uint32_t stm32x_compute_flash_cr_480(uint32_t cmd, int snb)
+static uint32_t stm32h7a_h7bxx_compute_flash_cr(uint32_t cmd, int snb)
{
/* save FW and START bits, to be right shifted by 2 bits later */
const uint32_t tmp = cmd & (FLASH_FW | FLASH_START);
@@ -169,9 +174,9 @@ static uint32_t stm32x_compute_flash_cr_480(uint32_t cmd, int snb)
static const struct stm32h7x_part_info stm32h7x_parts[] = {
{
- .id = 0x450,
- .revs = stm32_450_revs,
- .num_revs = ARRAY_SIZE(stm32_450_revs),
+ .id = DEVID_STM32H74_H75XX,
+ .revs = stm32h74_h75xx_revs,
+ .num_revs = ARRAY_SIZE(stm32h74_h75xx_revs),
.device_str = "STM32H74x/75x",
.page_size_kb = 128,
.block_size = 32,
@@ -181,12 +186,12 @@ static const struct stm32h7x_part_info stm32h7x_parts[] = {
.fsize_addr = 0x1FF1E880,
.wps_group_size = 1,
.wps_mask = 0xFF,
- .compute_flash_cr = stm32x_compute_flash_cr_450_483,
+ .compute_flash_cr = stm32h74_h75xx_compute_flash_cr,
},
{
- .id = 0x480,
- .revs = stm32_480_revs,
- .num_revs = ARRAY_SIZE(stm32_480_revs),
+ .id = DEVID_STM32H7A_H7BXX,
+ .revs = stm32h7a_h7bxx_revs,
+ .num_revs = ARRAY_SIZE(stm32h7a_h7bxx_revs),
.device_str = "STM32H7Ax/7Bx",
.page_size_kb = 8,
.block_size = 16,
@@ -196,12 +201,12 @@ static const struct stm32h7x_part_info stm32h7x_parts[] = {
.fsize_addr = 0x08FFF80C,
.wps_group_size = 4,
.wps_mask = 0xFFFFFFFF,
- .compute_flash_cr = stm32x_compute_flash_cr_480,
+ .compute_flash_cr = stm32h7a_h7bxx_compute_flash_cr,
},
{
- .id = 0x483,
- .revs = stm32_483_revs,
- .num_revs = ARRAY_SIZE(stm32_483_revs),
+ .id = DEVID_STM32H72_H73XX,
+ .revs = stm32h72_h73xx_revs,
+ .num_revs = ARRAY_SIZE(stm32h72_h73xx_revs),
.device_str = "STM32H72x/73x",
.page_size_kb = 128,
.block_size = 32,
@@ -211,7 +216,7 @@ static const struct stm32h7x_part_info stm32h7x_parts[] = {
.fsize_addr = 0x1FF1E880,
.wps_group_size = 1,
.wps_mask = 0xFF,
- .compute_flash_cr = stm32x_compute_flash_cr_450_483,
+ .compute_flash_cr = stm32h74_h75xx_compute_flash_cr,
},
};
@@ -808,8 +813,8 @@ static int stm32x_probe(struct flash_bank *bank)
bool has_dual_bank = stm32x_info->part_info->has_dual_bank;
switch (device_id) {
- case 0x450:
- case 0x480:
+ case DEVID_STM32H74_H75XX:
+ case DEVID_STM32H7A_H7BXX:
/* For STM32H74x/75x and STM32H7Ax/Bx
* - STM32H7xxxI devices contains dual bank, 1 Mbyte each
* - STM32H7xxxG devices contains dual bank, 512 Kbyte each
@@ -822,7 +827,7 @@ static int stm32x_probe(struct flash_bank *bank)
/* flash size is 2M or 1M */
flash_size_in_kb /= 2;
break;
- case 0x483:
+ case DEVID_STM32H72_H73XX:
break;
default:
LOG_ERROR("unsupported device");
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32h7x.c | 45 +++++++++++++++++++++++++--------------------
1 file changed, 25 insertions(+), 20 deletions(-)
hooks/post-receive
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From: OpenOCD-Gerrit <ope...@us...> - 2021-11-13 10:52:51
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 3f778c7c63cbd293c30144a88c041f845f1eb46d
Author: Tarek BOCHKATI <tar...@gm...>
Date: Wed Nov 3 16:22:22 2021 +0100
stlink (tcp): manage scattered stlink-server responses
detected in ubuntu 20.04
sometimes, the stlink-server response could be segmented on multiple
packets.
this causes stlink_tcp_send_cmd to fail with the following msg:
Error: failed to receive USB CMD response
because the received_size < expected size
to fix the issue, do recv in a loop till all data is received
or timeout is reached.
Change-Id: I46cc60c231b4cc52f150ead268f843bc60c41149
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6671
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c
index b51a0c2ba..87e6ddc20 100644
--- a/src/jtag/drivers/stlink_usb.c
+++ b/src/jtag/drivers/stlink_usb.c
@@ -37,6 +37,7 @@
#include <helper/binarybuffer.h>
#include <helper/bits.h>
#include <helper/system.h>
+#include <helper/time_support.h>
#include <jtag/interface.h>
#include <jtag/hla/hla_layout.h>
#include <jtag/hla/hla_transport.h>
@@ -926,17 +927,35 @@ static int stlink_tcp_send_cmd(void *handle, int send_size, int recv_size, bool
return ERROR_FAIL;
}
- keep_alive();
-
/* read the TCP response */
- int received_size = recv(h->tcp_backend_priv.fd, (void *)h->tcp_backend_priv.recv_buf, recv_size, 0);
- if (received_size != recv_size) {
- LOG_ERROR("failed to receive USB CMD response");
- if (received_size == -1)
+ int retval = ERROR_OK;
+ int remaining_bytes = recv_size;
+ uint8_t *recv_buf = h->tcp_backend_priv.recv_buf;
+ const int64_t timeout = timeval_ms() + 1000; /* 1 second */
+
+ while (remaining_bytes > 0) {
+ if (timeval_ms() > timeout) {
+ LOG_DEBUG("received size %d (expected %d)", recv_size - remaining_bytes, recv_size);
+ retval = ERROR_TIMEOUT_REACHED;
+ break;
+ }
+
+ keep_alive();
+ int received = recv(h->tcp_backend_priv.fd, (void *)recv_buf, remaining_bytes, 0);
+
+ if (received == -1) {
LOG_DEBUG("socket recv error: %s (errno %d)", strerror(errno), errno);
- else
- LOG_DEBUG("received size %d (expected %d)", received_size, recv_size);
- return ERROR_FAIL;
+ retval = ERROR_FAIL;
+ break;
+ }
+
+ recv_buf += received;
+ remaining_bytes -= received;
+ }
+
+ if (retval != ERROR_OK) {
+ LOG_ERROR("failed to receive USB CMD response");
+ return retval;
}
if (check_tcp_status) {
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/stlink_usb.c | 37 ++++++++++++++++++++++++++++---------
1 file changed, 28 insertions(+), 9 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-11-13 10:52:18
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit a4f8bf7a9041eb37cf5b8df441935664809f13ac
Author: Jan Matyas <ma...@co...>
Date: Mon Nov 1 15:28:28 2021 +0100
helper/log: Add macros for target-related errors/warnings/...
This commit introduces macros for target related log entries
(error, warning, ...) which is a very common operation in OpenOCD:
* LOG_TARGET_ERROR
* LOG_TARGET_WARNING
* LOG_TARGET_INFO
* LOG_TARGET_DEBUG
* LOG_TARGET_DEBUG_IO
The goal is to have one macro for this common operation and to
make such log entries look the same way - to make it more readable
for humans as well easier for parsing via scripts.
Change-Id: I6166565fc9040b03d3fca5c3aa44a1ccbcf96ad2
Signed-off-by: Jan Matyas <ma...@co...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6667
Tested-by: jenkins
Reviewed-by: Tim Newsome <ti...@si...>
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/helper/log.h b/src/helper/log.h
index 34ff835b8..621d467b4 100644
--- a/src/helper/log.h
+++ b/src/helper/log.h
@@ -143,6 +143,23 @@ extern int debug_level;
#define LOG_OUTPUT(expr ...) \
log_printf(LOG_LVL_OUTPUT, __FILE__, __LINE__, __func__, expr)
+/* Output a log entry that is related to a given target */
+
+#define LOG_TARGET_DEBUG_IO(target, fmt_str, ...) \
+ LOG_DEBUG_IO("[%s] " fmt_str, target_name(target), ##__VA_ARGS__)
+
+#define LOG_TARGET_DEBUG(target, fmt_str, ...) \
+ LOG_DEBUG("[%s] " fmt_str, target_name(target), ##__VA_ARGS__)
+
+#define LOG_TARGET_INFO(target, fmt_str, ...) \
+ LOG_INFO("[%s] " fmt_str, target_name(target), ##__VA_ARGS__)
+
+#define LOG_TARGET_WARNING(target, fmt_str, ...) \
+ LOG_WARNING("[%s] " fmt_str, target_name(target), ##__VA_ARGS__)
+
+#define LOG_TARGET_ERROR(target, fmt_str, ...) \
+ LOG_ERROR("[%s] " fmt_str, target_name(target), ##__VA_ARGS__)
+
/* general failures
* error codes < 100
*/
-----------------------------------------------------------------------
Summary of changes:
src/helper/log.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
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From: OpenOCD-Gerrit <ope...@us...> - 2021-11-13 10:51:44
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from ac1a632ba13efa77393cecf29bd29410db60cada (commit)
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- Log -----------------------------------------------------------------
commit e9a569aa18230766ae0bb6dd1a6dc843eb8c087b
Author: Antonio Borneo <bor...@gm...>
Date: Thu Oct 7 18:13:21 2021 +0200
jtag/adapter: fix memory leak on usb location
At exit, free the memory allocated to hold the USB location.
Change-Id: I050701f4dc8be14fd40e8add9d0b047461fa0d1c
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6646
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
diff --git a/src/jtag/adapter.c b/src/jtag/adapter.c
index a5a6222a9..c30019c17 100644
--- a/src/jtag/adapter.c
+++ b/src/jtag/adapter.c
@@ -120,6 +120,8 @@ int adapter_quit(void)
LOG_ERROR("failed: %d", result);
}
+ free(adapter_config.usb_location);
+
struct jtag_tap *t = jtag_all_taps();
while (t) {
struct jtag_tap *n = t->next_tap;
-----------------------------------------------------------------------
Summary of changes:
src/jtag/adapter.c | 2 ++
1 file changed, 2 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-11-13 10:51:26
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via ac1a632ba13efa77393cecf29bd29410db60cada (commit)
from 3c50288612cde9ce5d8f3004f5ad287abd80753e (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit ac1a632ba13efa77393cecf29bd29410db60cada
Author: Antonio Borneo <bor...@gm...>
Date: Thu Oct 7 15:07:57 2021 +0200
jtag: remove file driver.h
The only purpose of include file driver.h was to expose the API
to register the adapter's commands.
Move the prototype in adapter.h, already used by openocd.c.
Change-Id: Ie1090c60ef9e5bac5ea187c87bed6e7b08d9671c
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6645
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
diff --git a/src/jtag/Makefile.am b/src/jtag/Makefile.am
index cbdfb2054..23424f5a2 100644
--- a/src/jtag/Makefile.am
+++ b/src/jtag/Makefile.am
@@ -25,7 +25,6 @@ include %D%/drivers/Makefile.am
%D%/tcl.c \
%D%/swim.c \
%D%/commands.h \
- %D%/driver.h \
%D%/interface.h \
%D%/interfaces.h \
%D%/minidriver.h \
diff --git a/src/jtag/adapter.c b/src/jtag/adapter.c
index 0320d295d..a5a6222a9 100644
--- a/src/jtag/adapter.c
+++ b/src/jtag/adapter.c
@@ -886,7 +886,7 @@ static const struct command_registration interface_command_handlers[] = {
* @todo Remove internal assumptions that all debug adapters use JTAG for
* transport. Various types and data structures are not named generically.
*/
-int interface_register_commands(struct command_context *ctx)
+int adapter_register_commands(struct command_context *ctx)
{
return register_commands(ctx, NULL, interface_command_handlers);
}
diff --git a/src/jtag/adapter.h b/src/jtag/adapter.h
index a66fef1a7..8b73c0c9e 100644
--- a/src/jtag/adapter.h
+++ b/src/jtag/adapter.h
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
+ * Copyright (C) 2005 by Dominic Rath <Dom...@gm...>
* Copyright (c) 2018 Pengutronix, Oleksij Rempel <ke...@pe...>
*/
@@ -12,6 +13,9 @@
struct command_context;
+/** Register the adapter's commands */
+int adapter_register_commands(struct command_context *ctx);
+
/** Initialize debug adapter upon startup. */
int adapter_init(struct command_context *cmd_ctx);
diff --git a/src/jtag/driver.h b/src/jtag/driver.h
deleted file mode 100644
index ae00414c4..000000000
--- a/src/jtag/driver.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/***************************************************************************
- * Copyright (C) 2005 by Dominic Rath *
- * Dom...@gm... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
- ***************************************************************************/
-
-#ifndef OPENOCD_JTAG_DRIVER_H
-#define OPENOCD_JTAG_DRIVER_H
-
-struct command_context;
-
-int interface_register_commands(struct command_context *ctx);
-
-#endif /* OPENOCD_JTAG_DRIVER_H */
diff --git a/src/openocd.c b/src/openocd.c
index e8c526bfd..0292ba445 100644
--- a/src/openocd.c
+++ b/src/openocd.c
@@ -28,7 +28,6 @@
#include "openocd.h"
#include <jtag/adapter.h>
-#include <jtag/driver.h>
#include <jtag/jtag.h>
#include <transport/transport.h>
#include <helper/util.h>
@@ -313,7 +312,7 @@ static struct command_context *setup_command_handler(Jim_Interp *interp)
&log_register_commands,
&rtt_server_register_commands,
&transport_register_commands,
- &interface_register_commands,
+ &adapter_register_commands,
&target_register_commands,
&flash_register_commands,
&nand_register_commands,
-----------------------------------------------------------------------
Summary of changes:
src/jtag/Makefile.am | 1 -
src/jtag/adapter.c | 2 +-
src/jtag/adapter.h | 4 ++++
src/jtag/driver.h | 26 --------------------------
src/openocd.c | 3 +--
5 files changed, 6 insertions(+), 30 deletions(-)
delete mode 100644 src/jtag/driver.h
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2021-11-13 10:51:04
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 3c50288612cde9ce5d8f3004f5ad287abd80753e (commit)
from 679dcd0b52f6bafe848eb48e714764d37a101bb5 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 3c50288612cde9ce5d8f3004f5ad287abd80753e
Author: Antonio Borneo <bor...@gm...>
Date: Thu Oct 7 14:59:29 2021 +0200
jtag: align adapter speed code to new structure
Rename the jtag_XXX functions as adapter_XXX.
Rename internal variables.
Adapt log messages and comments text.
Change-Id: I67f209c67074899cd58bad495055def03f0d1bcf
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6644
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
diff --git a/src/jtag/adapter.c b/src/jtag/adapter.c
index 991338be8..0320d295d 100644
--- a/src/jtag/adapter.c
+++ b/src/jtag/adapter.c
@@ -85,18 +85,18 @@ int adapter_init(struct command_context *cmd_ctx)
return ERROR_JTAG_INIT_FAILED;
}
- int requested_khz = jtag_get_speed_khz();
+ int requested_khz = adapter_get_speed_khz();
int actual_khz = requested_khz;
- int jtag_speed_var = 0;
- retval = jtag_get_speed(&jtag_speed_var);
+ int speed_var = 0;
+ retval = adapter_get_speed(&speed_var);
if (retval != ERROR_OK)
return retval;
- retval = adapter_driver->speed(jtag_speed_var);
+ retval = adapter_driver->speed(speed_var);
if (retval != ERROR_OK)
return retval;
- retval = jtag_get_speed_readable(&actual_khz);
+ retval = adapter_get_speed_readable(&actual_khz);
if (retval != ERROR_OK)
- LOG_INFO("adapter-specific clock speed value %d", jtag_speed_var);
+ LOG_INFO("adapter-specific clock speed value %d", speed_var);
else if (actual_khz) {
/* Adaptive clocking -- JTAG-specific */
if ((adapter_config.clock_mode == CLOCK_MODE_RCLK)
@@ -130,31 +130,31 @@ int adapter_quit(void)
return ERROR_OK;
}
-unsigned jtag_get_speed_khz(void)
+unsigned int adapter_get_speed_khz(void)
{
return adapter_config.speed_khz;
}
-static int adapter_khz_to_speed(unsigned khz, int *speed)
+static int adapter_khz_to_speed(unsigned int khz, int *speed)
{
- LOG_DEBUG("convert khz to interface specific speed value");
+ LOG_DEBUG("convert khz to adapter specific speed value");
adapter_config.speed_khz = khz;
if (!is_adapter_initialized())
return ERROR_OK;
- LOG_DEBUG("have interface set up");
+ LOG_DEBUG("have adapter set up");
if (!adapter_driver->khz) {
- LOG_ERROR("Translation from khz to jtag_speed not implemented");
+ LOG_ERROR("Translation from khz to adapter speed not implemented");
return ERROR_FAIL;
}
int speed_div1;
- int retval = adapter_driver->khz(jtag_get_speed_khz(), &speed_div1);
+ int retval = adapter_driver->khz(adapter_get_speed_khz(), &speed_div1);
if (retval != ERROR_OK)
return retval;
*speed = speed_div1;
return ERROR_OK;
}
-static int jtag_rclk_to_speed(unsigned fallback_speed_khz, int *speed)
+static int adapter_rclk_to_speed(unsigned int fallback_speed_khz, int *speed)
{
int retval = adapter_khz_to_speed(0, speed);
if ((retval != ERROR_OK) && fallback_speed_khz) {
@@ -164,61 +164,61 @@ static int jtag_rclk_to_speed(unsigned fallback_speed_khz, int *speed)
return retval;
}
-static int jtag_set_speed(int speed)
+static int adapter_set_speed(int speed)
{
/* this command can be called during CONFIG,
- * in which case jtag isn't initialized */
+ * in which case adapter isn't initialized */
return is_adapter_initialized() ? adapter_driver->speed(speed) : ERROR_OK;
}
-int jtag_config_khz(unsigned khz)
+int adapter_config_khz(unsigned int khz)
{
- LOG_DEBUG("handle jtag khz");
+ LOG_DEBUG("handle adapter khz");
adapter_config.clock_mode = CLOCK_MODE_KHZ;
int speed = 0;
int retval = adapter_khz_to_speed(khz, &speed);
- return (retval != ERROR_OK) ? retval : jtag_set_speed(speed);
+ return (retval != ERROR_OK) ? retval : adapter_set_speed(speed);
}
-int jtag_config_rclk(unsigned fallback_speed_khz)
+int adapter_config_rclk(unsigned int fallback_speed_khz)
{
- LOG_DEBUG("handle jtag rclk");
+ LOG_DEBUG("handle adapter rclk");
adapter_config.clock_mode = CLOCK_MODE_RCLK;
adapter_config.rclk_fallback_speed_khz = fallback_speed_khz;
int speed = 0;
- int retval = jtag_rclk_to_speed(fallback_speed_khz, &speed);
- return (retval != ERROR_OK) ? retval : jtag_set_speed(speed);
+ int retval = adapter_rclk_to_speed(fallback_speed_khz, &speed);
+ return (retval != ERROR_OK) ? retval : adapter_set_speed(speed);
}
-int jtag_get_speed(int *speed)
+int adapter_get_speed(int *speed)
{
switch (adapter_config.clock_mode) {
case CLOCK_MODE_KHZ:
- adapter_khz_to_speed(jtag_get_speed_khz(), speed);
+ adapter_khz_to_speed(adapter_get_speed_khz(), speed);
break;
case CLOCK_MODE_RCLK:
- jtag_rclk_to_speed(adapter_config.rclk_fallback_speed_khz, speed);
+ adapter_rclk_to_speed(adapter_config.rclk_fallback_speed_khz, speed);
break;
default:
- LOG_ERROR("BUG: unknown jtag clock mode");
+ LOG_ERROR("BUG: unknown adapter clock mode");
return ERROR_FAIL;
}
return ERROR_OK;
}
-int jtag_get_speed_readable(int *khz)
+int adapter_get_speed_readable(int *khz)
{
- int jtag_speed_var = 0;
- int retval = jtag_get_speed(&jtag_speed_var);
+ int speed_var = 0;
+ int retval = adapter_get_speed(&speed_var);
if (retval != ERROR_OK)
return retval;
if (!is_adapter_initialized())
return ERROR_OK;
if (!adapter_driver->speed_div) {
- LOG_ERROR("Translation from jtag_speed to khz not implemented");
+ LOG_ERROR("Translation from adapter speed to khz not implemented");
return ERROR_FAIL;
}
- return adapter_driver->speed_div(jtag_speed_var, khz);
+ return adapter_driver->speed_div(speed_var, khz);
}
/*
@@ -640,13 +640,13 @@ COMMAND_HANDLER(handle_adapter_speed_command)
unsigned khz = 0;
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], khz);
- retval = jtag_config_khz(khz);
+ retval = adapter_config_khz(khz);
if (retval != ERROR_OK)
return retval;
}
- int cur_speed = jtag_get_speed_khz();
- retval = jtag_get_speed_readable(&cur_speed);
+ int cur_speed = adapter_get_speed_khz();
+ retval = adapter_get_speed_readable(&cur_speed);
if (retval != ERROR_OK)
return retval;
diff --git a/src/jtag/adapter.h b/src/jtag/adapter.h
index b2405e984..a66fef1a7 100644
--- a/src/jtag/adapter.h
+++ b/src/jtag/adapter.h
@@ -27,28 +27,28 @@ const char *adapter_usb_get_location(void);
/** @returns true if USB location string is "<dev_bus>-<port_path[0]>[.<port_path[1]>[...]]" */
bool adapter_usb_location_equal(uint8_t dev_bus, uint8_t *port_path, size_t path_len);
-/** @returns The current JTAG speed setting. */
-int jtag_get_speed(int *speed);
+/** @returns The current adapter speed setting. */
+int adapter_get_speed(int *speed);
/**
* Given a @a speed setting, use the interface @c speed_div callback to
* adjust the setting.
- * @param speed The speed setting to convert back to readable KHz.
+ * @param speed The speed setting to convert back to readable kHz.
* @returns ERROR_OK if the interface has not been initialized or on success;
* otherwise, the error code produced by the @c speed_div callback.
*/
-int jtag_get_speed_readable(int *speed);
+int adapter_get_speed_readable(int *speed);
-/** Attempt to configure the interface for the specified KHz. */
-int jtag_config_khz(unsigned khz);
+/** Attempt to configure the adapter for the specified kHz. */
+int adapter_config_khz(unsigned int khz);
/**
* Attempt to enable RTCK/RCLK. If that fails, fallback to the
* specified frequency.
*/
-int jtag_config_rclk(unsigned fallback_speed_khz);
+int adapter_config_rclk(unsigned int fallback_speed_khz);
-/** Retrieves the clock speed of the JTAG interface in KHz. */
-unsigned jtag_get_speed_khz(void);
+/** Retrieves the clock speed of the adapter in kHz. */
+unsigned int adapter_get_speed_khz(void);
#endif /* OPENOCD_JTAG_ADAPTER_H */
diff --git a/src/jtag/drivers/amt_jtagaccel.c b/src/jtag/drivers/amt_jtagaccel.c
index b73c66161..c204f237a 100644
--- a/src/jtag/drivers/amt_jtagaccel.c
+++ b/src/jtag/drivers/amt_jtagaccel.c
@@ -199,7 +199,7 @@ static void amt_jtagaccel_state_move(void)
aw_scan_tms_5 = 0x40 | (tms_scan[0] & 0x1f);
AMT_AW(aw_scan_tms_5);
int jtag_speed = 0;
- int retval = jtag_get_speed(&jtag_speed);
+ int retval = adapter_get_speed(&jtag_speed);
assert(retval == ERROR_OK);
if (jtag_speed > 3 || rtck_enabled)
amt_wait_scan_busy();
@@ -255,7 +255,7 @@ static void amt_jtagaccel_scan(bool ir_scan, enum scan_type type, uint8_t *buffe
uint8_t aw_tms_scan;
uint8_t tms_scan[2];
int jtag_speed_var;
- int retval = jtag_get_speed(&jtag_speed_var);
+ int retval = adapter_get_speed(&jtag_speed_var);
assert(retval == ERROR_OK);
if (ir_scan)
diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c
index 289ffcd92..19649b71c 100644
--- a/src/jtag/drivers/cmsis_dap.c
+++ b/src/jtag/drivers/cmsis_dap.c
@@ -1145,7 +1145,7 @@ static int cmsis_dap_swd_switch_seq(enum swd_special_seq seq)
/* Atmel EDBG needs renew clock setting after SWJ_Sequence
* otherwise default frequency is used */
- return cmsis_dap_cmd_dap_swj_clock(jtag_get_speed_khz());
+ return cmsis_dap_cmd_dap_swj_clock(adapter_get_speed_khz());
}
static int cmsis_dap_swd_open(void)
@@ -1262,7 +1262,7 @@ static int cmsis_dap_init(void)
/* Now try to connect to the target
* TODO: This is all SWD only @ present */
- retval = cmsis_dap_cmd_dap_swj_clock(jtag_get_speed_khz());
+ retval = cmsis_dap_cmd_dap_swj_clock(adapter_get_speed_khz());
if (retval != ERROR_OK)
goto init_err;
diff --git a/src/jtag/drivers/ftdi.c b/src/jtag/drivers/ftdi.c
index 5e7eae073..6e2e18450 100644
--- a/src/jtag/drivers/ftdi.c
+++ b/src/jtag/drivers/ftdi.c
@@ -699,7 +699,7 @@ static int ftdi_initialize(void)
mpsse_loopback_config(mpsse_ctx, false);
- freq = mpsse_set_frequency(mpsse_ctx, jtag_get_speed_khz() * 1000);
+ freq = mpsse_set_frequency(mpsse_ctx, adapter_get_speed_khz() * 1000);
return mpsse_flush(mpsse_ctx);
}
diff --git a/src/jtag/drivers/jlink.c b/src/jtag/drivers/jlink.c
index 12ac05fa6..ce1e9bfb7 100644
--- a/src/jtag/drivers/jlink.c
+++ b/src/jtag/drivers/jlink.c
@@ -811,7 +811,7 @@ static int jlink_init(void)
jtag_sleep(3000);
jlink_tap_init();
- jlink_speed(jtag_get_speed_khz());
+ jlink_speed(adapter_get_speed_khz());
if (iface == JAYLINK_TIF_JTAG) {
/*
diff --git a/src/jtag/drivers/parport.c b/src/jtag/drivers/parport.c
index 714cb1daa..9273e3ec2 100644
--- a/src/jtag/drivers/parport.c
+++ b/src/jtag/drivers/parport.c
@@ -458,9 +458,9 @@ COMMAND_HANDLER(parport_handle_parport_toggling_time_command)
}
parport_toggling_time_ns = ns;
- retval = jtag_get_speed(&wait_states);
+ retval = adapter_get_speed(&wait_states);
if (retval != ERROR_OK) {
- /* if jtag_get_speed fails then the clock_mode
+ /* if adapter_get_speed fails then the clock_mode
* has not been configured, this happens if parport_toggling_time is
* called before the adapter speed is set */
LOG_INFO("no parport speed set - defaulting to zero wait states");
diff --git a/src/jtag/drivers/vsllink.c b/src/jtag/drivers/vsllink.c
index 5d771443c..9cec2bea7 100644
--- a/src/jtag/drivers/vsllink.c
+++ b/src/jtag/drivers/vsllink.c
@@ -324,7 +324,7 @@ static int vsllink_init(void)
versaloon_interface.adaptors.gpio.config(0, GPIO_TRST, 0,
GPIO_TRST, GPIO_TRST);
versaloon_interface.adaptors.swd.init(0);
- vsllink_swd_frequency(jtag_get_speed_khz() * 1000);
+ vsllink_swd_frequency(adapter_get_speed_khz() * 1000);
vsllink_swd_switch_seq(JTAG_TO_SWD);
} else {
@@ -340,7 +340,7 @@ static int vsllink_init(void)
}
versaloon_interface.adaptors.jtag_raw.init(0);
- versaloon_interface.adaptors.jtag_raw.config(0, jtag_get_speed_khz());
+ versaloon_interface.adaptors.jtag_raw.config(0, adapter_get_speed_khz());
versaloon_interface.adaptors.gpio.config(0, GPIO_SRST | GPIO_TRST,
GPIO_TRST, GPIO_SRST, GPIO_SRST);
}
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 8bf4ea9c1..566c406b9 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -1041,13 +1041,13 @@ COMMAND_HANDLER(handle_jtag_rclk_command)
unsigned khz = 0;
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], khz);
- retval = jtag_config_rclk(khz);
+ retval = adapter_config_rclk(khz);
if (retval != ERROR_OK)
return retval;
}
- int cur_khz = jtag_get_speed_khz();
- retval = jtag_get_speed_readable(&cur_khz);
+ int cur_khz = adapter_get_speed_khz();
+ retval = adapter_get_speed_readable(&cur_khz);
if (retval != ERROR_OK)
return retval;
diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index ebe02e66d..9f8762e34 100644
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -381,7 +381,7 @@ int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_in
}
unsigned num_clocks =
- ((uint64_t)(ejtag_info->scan_delay) * jtag_get_speed_khz() + 500000) / 1000000;
+ ((uint64_t)(ejtag_info->scan_delay) * adapter_get_speed_khz() + 500000) / 1000000;
uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ALL);
@@ -1011,7 +1011,7 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
unsigned num_clocks = 0; /* like in legacy code */
if (ejtag_info->mode != 0)
- num_clocks = ((uint64_t)(ejtag_info->scan_delay) * jtag_get_speed_khz() + 500000) / 1000000;
+ num_clocks = ((uint64_t)(ejtag_info->scan_delay) * adapter_get_speed_khz() + 500000) / 1000000;
for (int i = 0; i < count; i++) {
jtag_add_clocks(num_clocks);
diff --git a/src/target/mips64_pracc.c b/src/target/mips64_pracc.c
index d68521d63..81a4cfbfa 100644
--- a/src/target/mips64_pracc.c
+++ b/src/target/mips64_pracc.c
@@ -1387,7 +1387,7 @@ int mips64_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info,
/* like in legacy code */
unsigned num_clocks = 0;
if (ejtag_info->mode != 0)
- num_clocks = ((uint64_t)(ejtag_info->scan_delay) * jtag_get_speed_khz() + 500000) / 1000000;
+ num_clocks = ((uint64_t)(ejtag_info->scan_delay) * adapter_get_speed_khz() + 500000) / 1000000;
LOG_DEBUG("num_clocks=%d", num_clocks);
for (i = 0; i < count; i++) {
jtag_add_clocks(num_clocks);
-----------------------------------------------------------------------
Summary of changes:
src/jtag/adapter.c | 68 ++++++++++++++++++++--------------------
src/jtag/adapter.h | 18 +++++------
src/jtag/drivers/amt_jtagaccel.c | 4 +--
src/jtag/drivers/cmsis_dap.c | 4 +--
src/jtag/drivers/ftdi.c | 2 +-
src/jtag/drivers/jlink.c | 2 +-
src/jtag/drivers/parport.c | 4 +--
src/jtag/drivers/vsllink.c | 4 +--
src/jtag/tcl.c | 6 ++--
src/target/mips32_pracc.c | 4 +--
src/target/mips64_pracc.c | 2 +-
11 files changed, 59 insertions(+), 59 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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