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From: OpenOCD-Gerrit <ope...@us...> - 2022-08-20 15:39:30
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 44e21b41df593d3349c07c2de5e088ea82a37042 (commit)
from ce5ca9f7ba782ea9fba8ecd5fc1cb9407fd27949 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 44e21b41df593d3349c07c2de5e088ea82a37042
Author: Ian Thompson <ia...@ca...>
Date: Sun Jul 10 17:35:50 2022 -0700
Generic Xtensa target config files
- Add new Xtensa TCL board files
- Add new Xtensa KC705 on-board FTDI interface
- Add new generic Xtensa and VDebug Xtensa target files
Signed-off-by: Ian Thompson <ia...@ca...>
Change-Id: I4acb15c83d1b7b8e6063833ce829530cb22a795e
Reviewed-on: https://review.openocd.org/c/openocd/+/7083
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/board/xtensa-kc705-ext.cfg b/tcl/board/xtensa-kc705-ext.cfg
new file mode 100644
index 000000000..6be06817c
--- /dev/null
+++ b/tcl/board/xtensa-kc705-ext.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence KC705 FPGA Development Platform for Xtensa targets
+# Can be used with various external adapters, e.g. Flyswatter2 or JLink
+#
+
+adapter speed 10000
+
+# KC705 supports JTAG only
+transport select jtag
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
diff --git a/tcl/board/xtensa-kc705-onboard.cfg b/tcl/board/xtensa-kc705-onboard.cfg
new file mode 100644
index 000000000..f0a616cd7
--- /dev/null
+++ b/tcl/board/xtensa-kc705-onboard.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence KC705 FPGA Development Platform for Xtensa targets
+# Can be used with on-board (FTDI) adapter or various external adapters
+#
+
+source [find interface/ftdi/xt_kc705_ml605.cfg]
+adapter speed 10000
+
+# KC705 supports JTAG only
+transport select jtag
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
diff --git a/tcl/board/xtensa-palladium-vdebug.cfg b/tcl/board/xtensa-palladium-vdebug.cfg
new file mode 100644
index 000000000..d4a700e36
--- /dev/null
+++ b/tcl/board/xtensa-palladium-vdebug.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# for Palladium emulation systems
+#
+
+source [find interface/vdebug.cfg]
+
+# vdebug select JTAG transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+source [find target/vd_xtensa_jtag.cfg]
diff --git a/tcl/interface/ftdi/xt_kc705_ml605.cfg b/tcl/interface/ftdi/xt_kc705_ml605.cfg
new file mode 100644
index 000000000..f62f2c291
--- /dev/null
+++ b/tcl/interface/ftdi/xt_kc705_ml605.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Xilinx KC705 / ML605 with Xtensa daughtercard; onboard USB/FT2232
+#
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6010
+# Specify "ftdi_serial <identifier>" here as needed
+
+ftdi_layout_init 0x0010 0x007b
+ftdi_layout_signal nTRST -data 0x0010
+ftdi_layout_signal nSRST -ndata 0x0020
diff --git a/tcl/target/vd_xtensa_jtag.cfg b/tcl/target/vd_xtensa_jtag.cfg
new file mode 100644
index 000000000..88f5bcc07
--- /dev/null
+++ b/tcl/target/vd_xtensa_jtag.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# for Palladium emulation systems
+#
+
+# TODO: Enable backdoor memory access
+# set _MEMSTART 0x00000000
+# set _MEMSIZE 0x100000
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path dut_top.JTAG 10ns
+# DMA Memories to access backdoor (up to 4)
+# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
+
+# Configure Xtensa core parameters next
+# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
+
+# register target
+proc vdebug_examine_end {} {
+# vdebug register_target
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { vdebug_examine_end }
diff --git a/tcl/target/xtensa.cfg b/tcl/target/xtensa.cfg
new file mode 100644
index 000000000..ef594f996
--- /dev/null
+++ b/tcl/target/xtensa.cfg
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Target Support for Xtensa Processors
+#
+
+set xtensa_ids { 0x120034e5 0x120134e5
+ 0x209034e5 0x209134e5 0x209234e5 0x209334e5 0x209434e5 0x209534e5 0x209634e5 0x209734e5
+ 0x20a034e5 0x20a134e5 0x20a234e5 0x20a334e5 0x20a434e5 0x20a534e5 0x20a634e5 0x20a734e5 0x20a834e5
+ 0x20b034e5 }
+set expected_xtensa_ids {}
+foreach i $xtensa_ids {
+ lappend expected_xtensa_ids -expected-id $i
+}
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME xtensa
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPARGLIST "-expected-id $CPUTAPID"
+} else {
+ set _CPUTAPARGLIST [join $expected_xtensa_ids]
+}
+
+set _TARGETNAME $_CHIPNAME
+set _CPU0NAME cpu
+set _TAPNAME $_CHIPNAME.$_CPU0NAME
+
+if { [info exists XTENSA_DAP] } {
+ source [find target/swj-dp.tcl]
+ # SWD mode ignores the -irlen parameter
+ eval swj_newdap $_CHIPNAME cpu -irlen 4 $_CPUTAPARGLIST
+ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+ set _TARGETNAME $_CHIPNAME.cpu
+ target create $_TARGETNAME xtensa -dap $_CHIPNAME.dap
+} else {
+ # JTAG direct (without DAP)
+ eval jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 $_CPUTAPARGLIST
+ target create $_TARGETNAME xtensa -chain-position $_TAPNAME
+}
+
+$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
+
+gdb_report_register_access_error enable
-----------------------------------------------------------------------
Summary of changes:
tcl/board/xtensa-kc705-ext.cfg | 12 +++++++++
tcl/board/xtensa-kc705-onboard.cfg | 13 ++++++++++
tcl/board/xtensa-palladium-vdebug.cfg | 16 ++++++++++++
tcl/interface/ftdi/xt_kc705_ml605.cfg | 11 +++++++++
tcl/target/vd_xtensa_jtag.cfg | 27 ++++++++++++++++++++
tcl/target/xtensa.cfg | 46 +++++++++++++++++++++++++++++++++++
6 files changed, 125 insertions(+)
create mode 100644 tcl/board/xtensa-kc705-ext.cfg
create mode 100644 tcl/board/xtensa-kc705-onboard.cfg
create mode 100644 tcl/board/xtensa-palladium-vdebug.cfg
create mode 100644 tcl/interface/ftdi/xt_kc705_ml605.cfg
create mode 100644 tcl/target/vd_xtensa_jtag.cfg
create mode 100644 tcl/target/xtensa.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-20 15:39:09
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via ce5ca9f7ba782ea9fba8ecd5fc1cb9407fd27949 (commit)
from be2e5c6c35f77fecb4df2a19cec05cceac500ca9 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit ce5ca9f7ba782ea9fba8ecd5fc1cb9407fd27949
Author: Ian Thompson <ia...@ca...>
Date: Fri Jun 24 22:27:32 2022 -0700
target: add generic Xtensa LX support
Generic Xtensa LX support extends the original Espressif/Xtensa
patch-set to support arbitrary Xtensa configurations, as defined in
a core-specific .cfg file. Not yet fully-featured. Additional
functionality to be added:
- Xtensa NX support
- DAP/SWD support
- File-IO support
- Generic Xtensa multi-core support
Valgrind-clean, no new Clang analyzer warnings
Signed-off-by: Ian Thompson <ia...@ca...>
Change-Id: I08e7bf8fa57c25b5d0cb75a1aa7a2ac13a380c52
Reviewed-on: https://review.openocd.org/c/openocd/+/7055
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erh...@es...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 9a5ab9a18..0df25406f 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4906,6 +4906,7 @@ And two debug interfaces cores:
@item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD.
@item @code{xscale} -- this is actually an architecture,
not a CPU type. It is based on the ARMv5 architecture.
+@item @code{xtensa} -- this is a generic Cadence/Tensilica Xtensa core.
@end itemize
@end deffn
@@ -10935,33 +10936,150 @@ OpenOCD supports debugging STM8 through the STMicroelectronics debug
protocol SWIM, @pxref{swimtransport,,SWIM}.
@section Xtensa Architecture
-Xtensa processors are based on a modular, highly flexible 32-bit RISC architecture
-that can easily scale from a tiny, cache-less controller or task engine to a high-performance
-SIMD/VLIW DSP provided by Cadence.
-@url{https://www.cadence.com/en_US/home/tools/ip/tensilica-ip/tensilica-xtensa-controllers-and-extensible-processors.html}.
-OpenOCD supports generic Xtensa processors implementation which can be customized by
-simply providing vendor-specific core configuration which controls every configurable
+Xtensa is a highly-customizable, user-extensible microprocessor and DSP
+architecture for complex embedded systems provided by Cadence Design
+Systems, Inc. See the
+@uref{https://www.cadence.com/en_US/home/tools/ip/tensilica-ip.html, Tensilica IP}
+website for additional information and documentation.
+
+OpenOCD supports generic Xtensa processor implementations which can be customized by
+providing a core-specific configuration file which describes every enabled
Xtensa architecture option, e.g. number of address registers, exceptions, reduced
-size instructions support, memory banks configuration etc. Also OpenOCD supports SMP
-configurations for Xtensa processors with any number of cores and allows to configure
-their debug signals interconnection (so-called "break/stall networks") which control how
-debug signals are distributed among cores. Xtensa "break networks" are compatible with
-ARM's Cross Trigger Interface (CTI). For debugging code on Xtensa chips OpenOCD
-uses JTAG protocol. Currently OpenOCD implements several Epsressif Xtensa-based chips of
+size instructions support, memory banks configuration etc. OpenOCD also supports SMP
+configurations for Xtensa processors with any number of cores and allows configuring
+their debug interconnect (termed "break/stall networks"), which control how debug
+signals are distributed among cores. Xtensa "break networks" are compatible with
+ARM's Cross Trigger Interface (CTI). OpenOCD implements both generic Xtensa targets
+as well as several Espressif Xtensa-based chips from the
@uref{https://www.espressif.com/en/products/socs, ESP32 family}.
-@subsection General Xtensa Commands
+OCD sessions for Xtensa processor and DSP targets are accessed via the Xtensa
+Debug Module (XDM), which provides external connectivity either through a
+traditional JTAG interface or an ARM DAP interface. If used, the DAP interface
+can control Xtensa targets through JTAG or SWD probes.
+
+@subsection Xtensa Core Configuration
+
+Due to the high level of configurability in Xtensa cores, the Xtensa target
+configuration comprises two categories:
+
+@enumerate
+@item Base Xtensa support common to all core configurations, and
+@item Core-specific support as configured for individual cores.
+@end enumerate
+
+All common Xtensa support is built into the OpenOCD Xtensa target layer and
+is enabled through a combination of TCL scripts: the target-specific
+@file{target/xtensa.cfg} and a board-specific @file{board/xtensa-*.cfg},
+similar to other target architectures.
+
+Importantly, core-specific configuration information must be provided by
+the user, and takes the form of an @file{xtensa-core-XXX.cfg} TCL script that
+defines the core's configurable features through a series of Xtensa
+configuration commands (detailed below).
+
+This core-specific @file{xtensa-core-XXX.cfg} file is typically either:
+
+@itemize @bullet
+@item Located within the Xtensa core configuration build as
+@file{src/config/xtensa-core-openocd.cfg}, or
+@item Generated by running the command @code{xt-gdb --dump-oocd-config}
+from the Xtensa processor tool-chain's command-line tools.
+@end itemize
+
+NOTE: @file{xtensa-core-XXX.cfg} must match the target Xtensa hardware
+connected to OpenOCD.
+
+Some example Xtensa configurations are bundled with OpenOCD for reference:
+@itemize @bullet
+@item Cadence Palladium VDebug emulation target. The user can combine their
+@file{xtensa-core-XXX.cfg} with the provided
+@file{board/xtensa-palladium-vdebug.cfg} to debug an emulated Xtensa RTL design.
+@item NXP MIMXRT685-EVK evaluation kit. The relevant configuration files are
+@file{board/xtensa-rt685-jlink.cfg} and @file{board/xtensa-core-nxp_rt600.cfg}.
+Additional information is provided by
+@uref{https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt600-evaluation-kit:MIMXRT685-EVK,
+NXP}.
+@end itemize
+
+@subsection Xtensa Configuration Commands
+
+@deffn {Command} {xtensa xtdef} (@option{LX}|@option{NX})
+Configure the Xtensa target architecture. Currently, Xtensa support is limited
+to LX6, LX7, and NX cores.
+@end deffn
+
+@deffn {Command} {xtensa xtopt} option value
+Configure Xtensa target options that are relevant to the debug subsystem.
+@var{option} is one of: @option{arnum}, @option{windowed},
+@option{cpenable}, @option{exceptions}, @option{intnum}, @option{hipriints},
+@option{excmlevel}, @option{intlevels}, @option{debuglevel},
+@option{ibreaknum}, or @option{dbreaknum}. @var{value} is an integer with
+the exact range determined by each particular option.
+
+NOTE: Some options are specific to Xtensa LX or Xtensa NX architecture, while
+others may be common to both but have different valid ranges.
+@end deffn
+
+@deffn {Command} {xtensa xtmem} (@option{iram}|@option{dram}|@option{sram}|@option{irom}|@option{drom}|@option{srom}) baseaddr bytes
+Configure Xtensa target memory. Memory type determines access rights,
+where RAMs are read/write while ROMs are read-only. @var{baseaddr} and
+@var{bytes} are both integers, typically hexadecimal and decimal, respectively.
+@end deffn
+
+@deffn {Command} {xtensa xtmem} (@option{icache}|@option{dcache}) linebytes cachebytes ways [writeback]
+Configure Xtensa processor cache. All parameters are required except for
+the optional @option{writeback} parameter; all are integers.
+@end deffn
+
+@deffn {Command} {xtensa xtmpu} numfgseg minsegsz lockable execonly
+Configure an Xtensa Memory Protection Unit (MPU). MPUs can restrict access
+and/or control cacheability of specific address ranges, but are lighter-weight
+than a full traditional MMU. All parameters are required; all are integers.
+@end deffn
+
+@deffn {Command} {xtensa xtmmu} numirefillentries numdrefillentries
+(Xtensa-LX only) Configure an Xtensa Memory Management Unit (MMU). Both
+parameters are required; both are integers.
+@end deffn
+
+@deffn {Command} {xtensa xtregs} numregs
+Configure the total number of registers for the Xtensa core. Configuration
+logic expects to subsequently process this number of @code{xtensa xtreg}
+definitions. @var{numregs} is an integer.
+@end deffn
+
+@deffn {Command} {xtensa xtregfmt} (@option{sparse}|@option{contiguous}) [general]
+Configure the type of register map used by GDB to access the Xtensa core.
+Generic Xtensa tools (e.g. xt-gdb) require @option{sparse} mapping (default) while
+Espressif tools expect @option{contiguous} mapping. Contiguous mapping takes an
+additional, optional integer parameter @option{numgregs}, which specifies the number
+of general registers used in handling g/G packets.
+@end deffn
+
+@deffn {Command} {xtensa xtreg} name offset
+Configure an Xtensa core register. All core registers are 32 bits wide,
+while TIE and user registers may have variable widths. @var{name} is a
+character string identifier while @var{offset} is a hexadecimal integer.
+@end deffn
+
+@subsection Xtensa Operation Commands
+
+@deffn {Command} {xtensa maskisr} (@option{on}|@option{off})
+(Xtensa-LX only) Mask or unmask Xtensa interrupts during instruction step.
+When masked, an interrupt that occurs during a step operation is handled and
+its ISR is executed, with the user's debug session returning after potentially
+executing many instructions. When unmasked, a triggered interrupt will result
+in execution progressing the requested number of instructions into the relevant
+vector/ISR code.
+@end deffn
@deffn {Command} {xtensa set_permissive} (0|1)
By default accessing memory beyond defined regions is forbidden. This commnd controls memory access address check.
When set to (1), skips access controls and address range check before read/write memory.
@end deffn
-@deffn {Command} {xtensa maskisr} (on|off)
-Selects whether interrupts will be disabled during stepping over single instruction. The default configuration is (off).
-@end deffn
-
@deffn {Command} {xtensa smpbreak} [none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]
Configures debug signals connection ("break network") for currently selected core.
@itemize @bullet
@@ -10985,6 +11103,13 @@ This feature is not well implemented and tested yet.
@end itemize
@end deffn
+@deffn {Command} {xtensa exe} <ascii-encoded hexadecimal instruction bytes>
+Execute arbitrary instruction(s) provided as an ascii string. The string represents an integer
+number of instruction bytes, thus its length must be even.
+@end deffn
+
+@subsection Xtensa Performance Monitor Configuration
+
@deffn {Command} {xtensa perfmon_enable} <counter_id> <select> [mask] [kernelcnt] [tracelevel]
Enable and start performance counter.
@itemize @bullet
@@ -11004,6 +11129,8 @@ whether to count.
Dump performance counter value. If no argument specified, dumps all counters.
@end deffn
+@subsection Xtensa Trace Configuration
+
@deffn {Command} {xtensa tracestart} [pc <pcval>/[<maskbitcount>]] [after <n> [ins|words]]
Set up and start a HW trace. Optionally set PC address range to trigger tracing stop when reached during program execution.
This command also allows to specify the amount of data to capture after stop trigger activation.
diff --git a/src/target/espressif/Makefile.am b/src/target/espressif/Makefile.am
index df002b33b..1b4f8062e 100644
--- a/src/target/espressif/Makefile.am
+++ b/src/target/espressif/Makefile.am
@@ -7,8 +7,5 @@ noinst_LTLIBRARIES += %D%/libespressif.la
%D%/esp_xtensa_smp.c \
%D%/esp_xtensa_smp.h \
%D%/esp32.c \
- %D%/esp32.h \
%D%/esp32s2.c \
- %D%/esp32s2.h \
- %D%/esp32s3.c \
- %D%/esp32s3.h
+ %D%/esp32s3.c
diff --git a/src/target/espressif/esp32.c b/src/target/espressif/esp32.c
index de8f1aacf..a083627fb 100644
--- a/src/target/espressif/esp32.c
+++ b/src/target/espressif/esp32.c
@@ -14,7 +14,6 @@
#include <target/target_type.h>
#include <target/smp.h>
#include "assert.h"
-#include "esp32.h"
#include "esp_xtensa_smp.h"
/*
@@ -70,204 +69,6 @@ implementation.
#define ESP32_RTC_CNTL_SW_CPU_STALL_REG (ESP32_RTCCNTL_BASE + 0xac)
#define ESP32_RTC_CNTL_SW_CPU_STALL_DEF 0x0
-
-/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
- *xtensa-overlay */
-static const unsigned int esp32_gdb_regs_mapping[ESP32_NUM_REGS] = {
- XT_REG_IDX_PC,
- XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
- XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
- XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
- XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
- XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
- XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
- XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
- XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
- XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
- XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
- XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
- XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
- XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
- XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
- XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
- XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
- XT_REG_IDX_LBEG, XT_REG_IDX_LEND, XT_REG_IDX_LCOUNT, XT_REG_IDX_SAR,
- XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
- XT_REG_IDX_PS, XT_REG_IDX_THREADPTR, XT_REG_IDX_BR, XT_REG_IDX_SCOMPARE1,
- XT_REG_IDX_ACCLO, XT_REG_IDX_ACCHI,
- XT_REG_IDX_M0, XT_REG_IDX_M1, XT_REG_IDX_M2, XT_REG_IDX_M3,
- ESP32_REG_IDX_EXPSTATE,
- ESP32_REG_IDX_F64R_LO,
- ESP32_REG_IDX_F64R_HI,
- ESP32_REG_IDX_F64S,
- XT_REG_IDX_F0, XT_REG_IDX_F1, XT_REG_IDX_F2, XT_REG_IDX_F3,
- XT_REG_IDX_F4, XT_REG_IDX_F5, XT_REG_IDX_F6, XT_REG_IDX_F7,
- XT_REG_IDX_F8, XT_REG_IDX_F9, XT_REG_IDX_F10, XT_REG_IDX_F11,
- XT_REG_IDX_F12, XT_REG_IDX_F13, XT_REG_IDX_F14, XT_REG_IDX_F15,
- XT_REG_IDX_FCR, XT_REG_IDX_FSR, XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE,
- XT_REG_IDX_MEMCTL, XT_REG_IDX_ATOMCTL, XT_REG_IDX_OCD_DDR,
- XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
- XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
- XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
- XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
- XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
- XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
- XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
- XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
- XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
- XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
- XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
- XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
- XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
- XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
- XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
- XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
- XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
- XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
- XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
- XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
- XT_REG_IDX_FAULT_INFO,
- XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
- XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
- XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
- XT_REG_IDX_TRAX_MEMEND,
- XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
- XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
- XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
-};
-
-static const struct xtensa_user_reg_desc esp32_user_regs[ESP32_NUM_REGS - XT_NUM_REGS] = {
- { "expstate", 0xE6, 0, 32, &xtensa_user_reg_u32_type },
- { "f64r_lo", 0xEA, 0, 32, &xtensa_user_reg_u32_type },
- { "f64r_hi", 0xEB, 0, 32, &xtensa_user_reg_u32_type },
- { "f64s", 0xEC, 0, 32, &xtensa_user_reg_u32_type },
-};
-
-static const struct xtensa_config esp32_xtensa_cfg = {
- .density = true,
- .aregs_num = XT_AREGS_NUM_MAX,
- .windowed = true,
- .coproc = true,
- .fp_coproc = true,
- .loop = true,
- .miscregs_num = 4,
- .threadptr = true,
- .boolean = true,
- .reloc_vec = true,
- .proc_id = true,
- .cond_store = true,
- .mac16 = true,
- .user_regs_num = ARRAY_SIZE(esp32_user_regs),
- .user_regs = esp32_user_regs,
- .fetch_user_regs = xtensa_fetch_user_regs_u32,
- .queue_write_dirty_user_regs = xtensa_queue_write_dirty_user_regs_u32,
- .gdb_general_regs_num = ESP32_NUM_REGS_G_COMMAND,
- .gdb_regs_mapping = esp32_gdb_regs_mapping,
- .irom = {
- .count = 2,
- .regions = {
- {
- .base = ESP32_IROM_LOW,
- .size = ESP32_IROM_HIGH - ESP32_IROM_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- {
- .base = ESP32_IROM_MASK_LOW,
- .size = ESP32_IROM_MASK_HIGH - ESP32_IROM_MASK_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- }
- },
- .iram = {
- .count = 2,
- .regions = {
- {
- .base = ESP32_IRAM_LOW,
- .size = ESP32_IRAM_HIGH - ESP32_IRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_RTC_IRAM_LOW,
- .size = ESP32_RTC_IRAM_HIGH - ESP32_RTC_IRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- }
- },
- .drom = {
- .count = 1,
- .regions = {
- {
- .base = ESP32_DROM_LOW,
- .size = ESP32_DROM_HIGH - ESP32_DROM_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- }
- },
- .dram = {
- .count = 6,
- .regions = {
- {
- .base = ESP32_DRAM_LOW,
- .size = ESP32_DRAM_HIGH - ESP32_DRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_RTC_DRAM_LOW,
- .size = ESP32_RTC_DRAM_HIGH - ESP32_RTC_DRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_RTC_DATA_LOW,
- .size = ESP32_RTC_DATA_HIGH - ESP32_RTC_DATA_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_EXTRAM_DATA_LOW,
- .size = ESP32_EXTRAM_DATA_HIGH - ESP32_EXTRAM_DATA_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_DR_REG_LOW,
- .size = ESP32_DR_REG_HIGH - ESP32_DR_REG_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_SYS_RAM_LOW,
- .size = ESP32_SYS_RAM_HIGH - ESP32_SYS_RAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- }
- },
- .exc = {
- .enabled = true,
- },
- .irq = {
- .enabled = true,
- .irq_num = 32,
- },
- .high_irq = {
- .enabled = true,
- .excm_level = 3,
- .nmi_num = 1,
- },
- .tim_irq = {
- .enabled = true,
- .comp_num = 3,
- },
- .debug = {
- .enabled = true,
- .irq_level = 6,
- .ibreaks_num = 2,
- .dbreaks_num = 2,
- .icount_sz = 32,
- },
- .trace = {
- .enabled = true,
- .mem_sz = ESP32_TRACEMEM_BLOCK_SZ,
- .reversed_mem_access = true,
- },
-};
-
/* 0 - don't care, 1 - TMS low, 2 - TMS high */
enum esp32_flash_bootstrap {
FBS_DONTCARE = 0,
@@ -401,7 +202,8 @@ static int esp32_soc_reset(struct target *target)
alive_sleep(10);
xtensa_poll(target);
if (timeval_ms() >= timeout) {
- LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d", target->state);
+ LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d",
+ target->state);
get_timeout = true;
break;
}
@@ -481,7 +283,6 @@ static int esp32_virt2phys(struct target *target,
return ERROR_FAIL;
}
-
/* The TDI pin is also used as a flash Vcc bootstrap pin. If we reset the CPU externally, the last state of the TDI pin
* can allow the power to an 1.8V flash chip to be raised to 3.3V, or the other way around. Users can use the
* esp32 flashbootstrap command to set a level, and this routine will make sure the tdi line will return to
@@ -544,7 +345,7 @@ static int esp32_target_create(struct target *target, Jim_Interp *interp)
return ERROR_FAIL;
}
- int ret = esp_xtensa_smp_init_arch_info(target, &esp32->esp_xtensa_smp, &esp32_xtensa_cfg,
+ int ret = esp_xtensa_smp_init_arch_info(target, &esp32->esp_xtensa_smp,
&esp32_dm_cfg, &esp32_chip_ops);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to init arch info!");
diff --git a/src/target/espressif/esp32.h b/src/target/espressif/esp32.h
deleted file mode 100644
index f07c08d41..000000000
--- a/src/target/espressif/esp32.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/***************************************************************************
- * ESP32 target for OpenOCD *
- * Copyright (C) 2017 Espressif Systems Ltd. *
- ***************************************************************************/
-
-#ifndef OPENOCD_TARGET_ESP32_H
-#define OPENOCD_TARGET_ESP32_H
-
-#include <target/xtensa/xtensa_regs.h>
-
-#define ESP32_DROM_LOW 0x3F400000
-#define ESP32_DROM_HIGH 0x3F800000
-#define ESP32_IROM_LOW 0x400D0000
-#define ESP32_IROM_HIGH 0x40400000
-
-/* Number of registers returned directly by the G command
- * Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
-#define ESP32_NUM_REGS_G_COMMAND 105
-
-enum esp32_reg_id {
- /* chip specific registers that extend ISA go after ISA-defined ones */
- ESP32_REG_IDX_EXPSTATE = XT_USR_REG_START,
- ESP32_REG_IDX_F64R_LO,
- ESP32_REG_IDX_F64R_HI,
- ESP32_REG_IDX_F64S,
- ESP32_NUM_REGS,
-};
-
-#endif /* OPENOCD_TARGET_ESP32_H */
diff --git a/src/target/espressif/esp32s2.c b/src/target/espressif/esp32s2.c
index bbf7ff5af..0bcd20f2d 100644
--- a/src/target/espressif/esp32s2.c
+++ b/src/target/espressif/esp32s2.c
@@ -14,7 +14,6 @@
#include <target/target.h>
#include <target/target_type.h>
#include "esp_xtensa.h"
-#include "esp32s2.h"
/* Overall memory map
* TODO: read memory configuration from target registers */
@@ -89,190 +88,6 @@
#define ESP32_S2_DR_REG_UART_BASE 0x3f400000
#define ESP32_S2_REG_UART_BASE(i) (ESP32_S2_DR_REG_UART_BASE + (i) * 0x10000)
#define ESP32_S2_UART_DATE_REG(i) (ESP32_S2_REG_UART_BASE(i) + 0x74)
-
-/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
- * xtensa-overlay */
-static const unsigned int esp32s2_gdb_regs_mapping[ESP32_S2_NUM_REGS] = {
- XT_REG_IDX_PC,
- XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
- XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
- XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
- XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
- XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
- XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
- XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
- XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
- XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
- XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
- XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
- XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
- XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
- XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
- XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
- XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
- XT_REG_IDX_SAR,
- XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
- XT_REG_IDX_PS, XT_REG_IDX_THREADPTR,
- ESP32_S2_REG_IDX_GPIOOUT,
- XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE, XT_REG_IDX_OCD_DDR,
- XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
- XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
- XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
- XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
- XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
- XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
- XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
- XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
- XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
- XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
- XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
- XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
- XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
- XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
- XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
- XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
- XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
- XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
- XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
- XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
- XT_REG_IDX_FAULT_INFO,
- XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
- XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
- XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
- XT_REG_IDX_TRAX_MEMEND,
- XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
- XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
- XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
-};
-
-static const struct xtensa_user_reg_desc esp32s2_user_regs[ESP32_S2_NUM_REGS - XT_NUM_REGS] = {
- { "gpio_out", 0x00, 0, 32, &xtensa_user_reg_u32_type },
-};
-
-static const struct xtensa_config esp32s2_xtensa_cfg = {
- .density = true,
- .aregs_num = XT_AREGS_NUM_MAX,
- .windowed = true,
- .coproc = true,
- .miscregs_num = 4,
- .reloc_vec = true,
- .proc_id = true,
- .threadptr = true,
- .user_regs_num = ARRAY_SIZE(esp32s2_user_regs),
- .user_regs = esp32s2_user_regs,
- .fetch_user_regs = xtensa_fetch_user_regs_u32,
- .queue_write_dirty_user_regs = xtensa_queue_write_dirty_user_regs_u32,
- .gdb_general_regs_num = ESP32_S2_NUM_REGS_G_COMMAND,
- .gdb_regs_mapping = esp32s2_gdb_regs_mapping,
- .irom = {
- .count = 2,
- .regions = {
- {
- .base = ESP32_S2_IROM_LOW,
- .size = ESP32_S2_IROM_HIGH - ESP32_S2_IROM_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- {
- .base = ESP32_S2_IROM_MASK_LOW,
- .size = ESP32_S2_IROM_MASK_HIGH - ESP32_S2_IROM_MASK_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- }
- },
- .iram = {
- .count = 2,
- .regions = {
- {
- .base = ESP32_S2_IRAM_LOW,
- .size = ESP32_S2_IRAM_HIGH - ESP32_S2_IRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S2_RTC_IRAM_LOW,
- .size = ESP32_S2_RTC_IRAM_HIGH - ESP32_S2_RTC_IRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- }
- },
- .drom = {
- .count = 2,
- .regions = {
- {
- .base = ESP32_S2_DROM0_LOW,
- .size = ESP32_S2_DROM0_HIGH - ESP32_S2_DROM0_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- {
- .base = ESP32_S2_DROM1_LOW,
- .size = ESP32_S2_DROM1_HIGH - ESP32_S2_DROM1_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- }
- },
- .dram = {
- .count = 6,
- .regions = {
- {
- .base = ESP32_S2_DRAM_LOW,
- .size = ESP32_S2_DRAM_HIGH - ESP32_S2_DRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S2_RTC_DRAM_LOW,
- .size = ESP32_S2_RTC_DRAM_HIGH - ESP32_S2_RTC_DRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S2_RTC_DATA_LOW,
- .size = ESP32_S2_RTC_DATA_HIGH - ESP32_S2_RTC_DATA_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S2_EXTRAM_DATA_LOW,
- .size = ESP32_S2_EXTRAM_DATA_HIGH - ESP32_S2_EXTRAM_DATA_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S2_DR_REG_LOW,
- .size = ESP32_S2_DR_REG_HIGH - ESP32_S2_DR_REG_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S2_SYS_RAM_LOW,
- .size = ESP32_S2_SYS_RAM_HIGH - ESP32_S2_SYS_RAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- }
- },
- .exc = {
- .enabled = true,
- },
- .irq = {
- .enabled = true,
- .irq_num = 32,
- },
- .high_irq = {
- .enabled = true,
- .excm_level = 3,
- .nmi_num = 1,
- },
- .tim_irq = {
- .enabled = true,
- .comp_num = 3,
- },
- .debug = {
- .enabled = true,
- .irq_level = 6,
- .ibreaks_num = 2,
- .dbreaks_num = 2,
- .icount_sz = 32,
- },
- .trace = {
- .enabled = true,
- .mem_sz = ESP32_S2_TRACEMEM_BLOCK_SZ,
- },
-};
-
struct esp32s2_common {
struct esp_xtensa_common esp_xtensa;
};
@@ -313,7 +128,7 @@ int esp32s2_soft_reset_halt(struct target *target)
int res = esp32s2_soc_reset(target);
if (res != ERROR_OK)
return res;
- return xtensa_assert_reset(target);
+ return xtensa_soft_reset_halt(target);
}
static int esp32s2_set_peri_reg_mask(struct target *target,
@@ -476,7 +291,8 @@ static int esp32s2_soc_reset(struct target *target)
alive_sleep(10);
xtensa_poll(target);
if (timeval_ms() >= timeout) {
- LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d", target->state);
+ LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d",
+ target->state);
return ERROR_TARGET_TIMEOUT;
}
}
@@ -638,7 +454,7 @@ static int esp32s2_target_create(struct target *target, Jim_Interp *interp)
return ERROR_FAIL;
}
- int ret = esp_xtensa_init_arch_info(target, &esp32->esp_xtensa, &esp32s2_xtensa_cfg, &esp32s2_dm_cfg);
+ int ret = esp_xtensa_init_arch_info(target, &esp32->esp_xtensa, &esp32s2_dm_cfg);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to init arch info!");
free(esp32);
@@ -653,10 +469,6 @@ static int esp32s2_target_create(struct target *target, Jim_Interp *interp)
static const struct command_registration esp32s2_command_handlers[] = {
{
- .name = "xtensa",
- .mode = COMMAND_ANY,
- .help = "Xtensa commands group",
- .usage = "",
.chain = xtensa_command_handlers,
},
COMMAND_REGISTRATION_DONE
diff --git a/src/target/espressif/esp32s2.h b/src/target/espressif/esp32s2.h
deleted file mode 100644
index 26fc7a198..000000000
--- a/src/target/espressif/esp32s2.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/***************************************************************************
- * ESP32-S2 target for OpenOCD *
- * Copyright (C) 2019 Espressif Systems Ltd. *
- ***************************************************************************/
-
-#ifndef OPENOCD_TARGET_ESP32S2_H
-#define OPENOCD_TARGET_ESP32S2_H
-
-#include <target/xtensa/xtensa_regs.h>
-
-#define ESP32_S2_DROM_LOW 0x3f000000
-#define ESP32_S2_DROM_HIGH 0x3ff80000
-#define ESP32_S2_IROM_LOW 0x40080000
-#define ESP32_S2_IROM_HIGH 0x40800000
-
-/* Number of registers returned directly by the G command
- * Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
-#define ESP32_S2_NUM_REGS_G_COMMAND 72
-
-enum esp32s2_reg_id {
- /* chip specific registers that extend ISA go after ISA-defined ones */
- ESP32_S2_REG_IDX_GPIOOUT = XT_USR_REG_START,
- ESP32_S2_NUM_REGS,
-};
-
-#endif /* OPENOCD_TARGET_ESP32S2_H */
diff --git a/src/target/espressif/esp32s3.c b/src/target/espressif/esp32s3.c
index b5487407f..b87005901 100644
--- a/src/target/espressif/esp32s3.c
+++ b/src/target/espressif/esp32s3.c
@@ -14,7 +14,6 @@
#include <target/target_type.h>
#include <target/smp.h>
#include "assert.h"
-#include "esp32s3.h"
#include "esp_xtensa_smp.h"
/*
@@ -75,246 +74,10 @@ implementation.
#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG (ESP32_S3_RTCCNTL_BASE + 0xBC)
#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF 0x0
-/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
- *xtensa-overlay */
-static const unsigned int esp32s3_gdb_regs_mapping[ESP32_S3_NUM_REGS] = {
- XT_REG_IDX_PC,
- XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
- XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
- XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
- XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
- XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
- XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
- XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
- XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
- XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
- XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
- XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
- XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
- XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
- XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
- XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
- XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
- XT_REG_IDX_LBEG, XT_REG_IDX_LEND, XT_REG_IDX_LCOUNT, XT_REG_IDX_SAR,
- XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
- XT_REG_IDX_PS, XT_REG_IDX_THREADPTR, XT_REG_IDX_BR, XT_REG_IDX_SCOMPARE1,
- XT_REG_IDX_ACCLO, XT_REG_IDX_ACCHI,
- XT_REG_IDX_M0, XT_REG_IDX_M1, XT_REG_IDX_M2, XT_REG_IDX_M3,
- ESP32_S3_REG_IDX_GPIOOUT,
- XT_REG_IDX_F0, XT_REG_IDX_F1, XT_REG_IDX_F2, XT_REG_IDX_F3,
- XT_REG_IDX_F4, XT_REG_IDX_F5, XT_REG_IDX_F6, XT_REG_IDX_F7,
- XT_REG_IDX_F8, XT_REG_IDX_F9, XT_REG_IDX_F10, XT_REG_IDX_F11,
- XT_REG_IDX_F12, XT_REG_IDX_F13, XT_REG_IDX_F14, XT_REG_IDX_F15,
- XT_REG_IDX_FCR, XT_REG_IDX_FSR,
- ESP32_S3_REG_IDX_ACCX_0, ESP32_S3_REG_IDX_ACCX_1,
- ESP32_S3_REG_IDX_QACC_H_0, ESP32_S3_REG_IDX_QACC_H_1, ESP32_S3_REG_IDX_QACC_H_2,
- ESP32_S3_REG_IDX_QACC_H_3, ESP32_S3_REG_IDX_QACC_H_4,
- ESP32_S3_REG_IDX_QACC_L_0, ESP32_S3_REG_IDX_QACC_L_1, ESP32_S3_REG_IDX_QACC_L_2,
- ESP32_S3_REG_IDX_QACC_L_3, ESP32_S3_REG_IDX_QACC_L_4,
- ESP32_S3_REG_IDX_SAR_BYTE, ESP32_S3_REG_IDX_FFT_BIT_WIDTH,
- ESP32_S3_REG_IDX_UA_STATE_0, ESP32_S3_REG_IDX_UA_STATE_1, ESP32_S3_REG_IDX_UA_STATE_2,
- ESP32_S3_REG_IDX_UA_STATE_3,
- ESP32_S3_REG_IDX_Q0, ESP32_S3_REG_IDX_Q1, ESP32_S3_REG_IDX_Q2, ESP32_S3_REG_IDX_Q3,
- ESP32_S3_REG_IDX_Q4, ESP32_S3_REG_IDX_Q5, ESP32_S3_REG_IDX_Q6, ESP32_S3_REG_IDX_Q7,
-
- XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE,
- XT_REG_IDX_MEMCTL, XT_REG_IDX_ATOMCTL, XT_REG_IDX_OCD_DDR,
- XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
- XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
- XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
- XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
- XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
- XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
- XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
- XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
- XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
- XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
- XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
- XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
- XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
-
- XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
- XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
- XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
- XT_REG_IDX_FAULT_INFO,
- XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
- XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
- XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
- XT_REG_IDX_TRAX_MEMEND,
- XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
- XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
- XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
- XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
- XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
- XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
- XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
-};
-
-/* actually this table contains user + TIE registers
- * TODO: for TIE registers we need to specify custom access functions instead of `xtensa_user_reg_xxx_type`*/
-static const struct xtensa_user_reg_desc esp32s3_user_regs[ESP32_S3_NUM_REGS - XT_NUM_REGS] = {
- { "gpio_out", 0x00, 0, 32, &xtensa_user_reg_u32_type },
- { "accx_0", 0x01, 0, 32, &xtensa_user_reg_u32_type },
- { "accx_1", 0x02, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_h_0", 0x03, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_h_1", 0x04, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_h_2", 0x05, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_h_3", 0x06, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_h_4", 0x07, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_l_0", 0x08, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_l_1", 0x09, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_l_2", 0x0A, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_l_3", 0x0B, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_l_4", 0x0C, 0, 32, &xtensa_user_reg_u32_type },
- { "sar_byte", 0x0D, 0, 32, &xtensa_user_reg_u32_type },
- { "fft_bit_width", 0x0E, 0, 32, &xtensa_user_reg_u32_type },
- { "ua_state_0", 0x0F, 0, 32, &xtensa_user_reg_u32_type },
- { "ua_state_1", 0x10, 0, 32, &xtensa_user_reg_u32_type },
- { "ua_state_2", 0x11, 0, 32, &xtensa_user_reg_u32_type },
- { "ua_state_3", 0x12, 0, 32, &xtensa_user_reg_u32_type },
- { "q0", 0x13, 0, 128, &xtensa_user_reg_u128_type },
- { "q1", 0x14, 0, 128, &xtensa_user_reg_u128_type },
- { "q2", 0x15, 0, 128, &xtensa_user_reg_u128_type },
- { "q3", 0x16, 0, 128, &xtensa_user_reg_u128_type },
- { "q4", 0x17, 0, 128, &xtensa_user_reg_u128_type },
- { "q5", 0x18, 0, 128, &xtensa_user_reg_u128_type },
- { "q6", 0x19, 0, 128, &xtensa_user_reg_u128_type },
- { "q7", 0x20, 0, 128, &xtensa_user_reg_u128_type },
-};
-
struct esp32s3_common {
struct esp_xtensa_smp_common esp_xtensa_smp;
};
-static int esp32s3_fetch_user_regs(struct target *target);
-static int esp32s3_queue_write_dirty_user_regs(struct target *target);
-
-static const struct xtensa_config esp32s3_xtensa_cfg = {
- .density = true,
- .aregs_num = XT_AREGS_NUM_MAX,
- .windowed = true,
- .coproc = true,
- .fp_coproc = true,
- .loop = true,
- .miscregs_num = 4,
- .threadptr = true,
- .boolean = true,
- .reloc_vec = true,
- .proc_id = true,
- .cond_store = true,
- .mac16 = true,
- .user_regs_num = ARRAY_SIZE(esp32s3_user_regs),
- .user_regs = esp32s3_user_regs,
- .fetch_user_regs = esp32s3_fetch_user_regs,
- .queue_write_dirty_user_regs = esp32s3_queue_write_dirty_user_regs,
- .gdb_general_regs_num = ESP32_S3_NUM_REGS_G_COMMAND,
- .gdb_regs_mapping = esp32s3_gdb_regs_mapping,
- .irom = {
- .count = 2,
- .regions = {
- {
- .base = ESP32_S3_IROM_LOW,
- .size = ESP32_S3_IROM_HIGH - ESP32_S3_IROM_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- {
- .base = ESP32_S3_IROM_MASK_LOW,
- .size = ESP32_S3_IROM_MASK_HIGH - ESP32_S3_IROM_MASK_LOW,
- .access = XT_MEM_ACCESS_READ,
- }
- }
- },
- .iram = {
- .count = 2,
- .regions = {
- {
- .base = ESP32_S3_IRAM_LOW,
- .size = ESP32_S3_IRAM_HIGH - ESP32_S3_IRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S3_RTC_IRAM_LOW,
- .size = ESP32_S3_RTC_IRAM_HIGH - ESP32_S3_RTC_IRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- }
- },
- .drom = {
- .count = 1,
- .regions = {
- {
- .base = ESP32_S3_DROM_LOW,
- .size = ESP32_S3_DROM_HIGH - ESP32_S3_DROM_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- }
- },
- .dram = {
- .count = 4,
- .regions = {
- {
- .base = ESP32_S3_DRAM_LOW,
- .size = ESP32_S3_DRAM_HIGH - ESP32_S3_DRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S3_RTC_DRAM_LOW,
- .size = ESP32_S3_RTC_DRAM_HIGH - ESP32_S3_RTC_DRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S3_RTC_DATA_LOW,
- .size = ESP32_S3_RTC_DATA_HIGH - ESP32_S3_RTC_DATA_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S3_SYS_RAM_LOW,
- .size = ESP32_S3_SYS_RAM_HIGH - ESP32_S3_SYS_RAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- }
- },
- .exc = {
- .enabled = true,
- },
- .irq = {
- .enabled = true,
- .irq_num = 32,
- },
- .high_irq = {
- .enabled = true,
- .excm_level = 3,
- .nmi_num = 1,
- },
- .tim_irq = {
- .enabled = true,
- .comp_num = 3,
- },
- .debug = {
- .enabled = true,
- .irq_level = 6,
- .ibreaks_num = 2,
- .dbreaks_num = 2,
- .icount_sz = 32,
- },
- .trace = {
- .enabled = true,
- .mem_sz = ESP32_S3_TRACEMEM_BLOCK_SZ,
- },
-};
-
-static int esp32s3_fetch_user_regs(struct target *target)
-{
- LOG_DEBUG("%s: user regs fetching is not implemented!", target_name(target));
- return ERROR_OK;
-}
-
-static int esp32s3_queue_write_dirty_user_regs(struct target *target)
-{
- LOG_DEBUG("%s: user regs writing is not implemented!", target_name(target));
- return ERROR_OK;
-}
-
/* Reset ESP32-S3's peripherals.
* 1. OpenOCD makes sure the target is halted; if not, tries to halt it.
* If that fails, tries to reset it (via OCD) and then halt.
@@ -537,7 +300,6 @@ static int esp32s3_virt2phys(struct target *target,
return ERROR_FAIL;
}
-
static int esp32s3_target_init(struct command_context *cmd_ctx, struct target *target)
{
return esp_xtensa_target_init(cmd_ctx, target);
@@ -577,7 +339,6 @@ static int esp32s3_target_create(struct target *target, Jim_Interp *interp)
int ret = esp_xtensa_smp_init_arch_info(target,
&esp32s3->esp_xtensa_smp,
- &esp32s3_xtensa_cfg,
&esp32s3_dm_cfg,
&esp32s3_chip_ops);
if (ret != ERROR_OK) {
diff --git a/src/target/espressif/esp32s3.h b/src/target/espressif/esp32s3.h
deleted file mode 100644
index a7d57ec02..000000000
--- a/src/target/espressif/esp32s3.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/***************************************************************************
- * ESP32-S3 target for OpenOCD *
- * Copyright (C) 2020 Espressif Systems Ltd. *
- ***************************************************************************/
-
-#ifndef OPENOCD_TARGET_ESP32S3_H
-#define OPENOCD_TARGET_ESP32S3_H
-
-#include <target/xtensa/xtensa_regs.h>
-
-#define ESP32_S3_DROM_LOW 0x3C000000
-#define ESP32_S3_DROM_HIGH 0x3D000000
-#define ESP32_S3_IROM_LOW 0x42000000
-#define ESP32_S3_IROM_HIGH 0x44000000
-
-/*Number of registers returned directly by the G command
- *Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
-#define ESP32_S3_NUM_REGS_G_COMMAND 128
-
-enum esp32s3_reg_id {
- /* chip specific registers that extend ISA go after ISA-defined ones */
- ESP32_S3_REG_IDX_GPIOOUT = XT_NUM_REGS,
- ESP32_S3_REG_IDX_ACCX_0,
- ESP32_S3_REG_IDX_ACCX_1,
- ESP32_S3_REG_IDX_QACC_H_0,
- ESP32_S3_REG_IDX_QACC_H_1,
- ESP32_S3_REG_IDX_QACC_H_2,
- ESP32_S3_REG_IDX_QACC_H_3,
- ESP32_S3_REG_IDX_QACC_H_4,
- ESP32_S3_REG_IDX_QACC_L_0,
- ESP32_S3_REG_IDX_QACC_L_1,
- ESP32_S3_REG_IDX_QACC_L_2,
- ESP32_S3_REG_IDX_QACC_L_3,
- ESP32_S3_REG_IDX_QACC_L_4,
- ESP32_S3_REG_IDX_SAR_BYTE,
- ESP32_S3_REG_IDX_FFT_BIT_WIDTH,
- ESP32_S3_REG_IDX_UA_STATE_0,
- ESP32_S3_REG_IDX_UA_STATE_1,
- ESP32_S3_REG_IDX_UA_STATE_2,
- ESP32_S3_REG_IDX_UA_STATE_3,
- ESP32_S3_REG_IDX_Q0,
- ESP32_S3_REG_IDX_Q1,
- ESP32_S3_REG_IDX_Q2,
- ESP32_S3_REG_IDX_Q3,
- ESP32_S3_REG_IDX_Q4,
- ESP32_S3_REG_IDX_Q5,
- ESP32_S3_REG_IDX_Q6,
- ESP32_S3_REG_IDX_Q7,
- ESP32_S3_NUM_REGS,
-};
-
-#endif /* OPENOCD_TARGET_ESP32S3_H */
diff --git a/src/target/espressif/esp_xtensa.c b/src/target/espressif/esp_xtensa.c
index ce1601289..fcd42eac3 100644
--- a/src/target/espressif/esp_xtensa.c
+++ b/src/target/espressif/esp_xtensa.c
@@ -17,10 +17,9 @@
int esp_xtensa_init_arch_info(struct target *target,
struct esp_xtensa_common *esp_xtensa,
- const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg)
{
- return xtensa_init_arch_info(target, &esp_xtensa->xtensa, xtensa_cfg, dm_cfg);
+ return xtensa_init_arch_info(target, &esp_xtensa->xtensa, dm_cfg);
}
int esp_xtensa_target_init(struct command_context *cmd_ctx, struct target *target)
diff --git a/src/target/espressif/esp_xtensa.h b/src/target/espressif/esp_xtensa.h
index 4bbbd756c..61e87c086 100644
--- a/src/target/espressif/esp_xtensa.h
+++ b/src/target/espressif/esp_xtensa.h
@@ -23,7 +23,6 @@ static inline struct esp_xtensa_common *target_to_esp_xtensa(struct target *targ
int esp_xtensa_init_arch_info(struct target *target,
struct esp_xtensa_common *esp_xtensa,
- const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg);
int esp_xtensa_target_init(struct command_context *cmd_ctx, struct target *target);
void esp_xtensa_target_deinit(struct target *target);
diff --git a/src/target/espressif/esp_xtensa_smp.c b/src/target/espressif/esp_xtensa_smp.c
index 606066247..b109f3c5e 100644
--- a/src/target/espressif/esp_xtensa_smp.c
+++ b/src/target/espressif/esp_xtensa_smp.c
@@ -450,11 +450,10 @@ int esp_xtensa_smp_watchpoint_remove(struct target *target, struct watchpoint *w
int esp_xtensa_smp_init_arch_info(struct target *target,
struct esp_xtensa_smp_common *esp_xtensa_smp,
- const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg,
const struct esp_xtensa_smp_chip_ops *chip_ops)
{
- int ret = esp_xtensa_init_arch_info(target, &esp_xtensa_smp->esp_xtensa, xtensa_cfg, dm_cfg);
+ int ret = esp_xtensa_init_arch_info(target, &esp_xtensa_smp->esp_xtensa, dm_cfg);
if (ret != ERROR_OK)
return ret;
esp_xtensa_smp->chip_ops = chip_ops;
@@ -467,6 +466,139 @@ int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *t
return esp_xtensa_target_init(cmd_ctx, target);
}
+COMMAND_HANDLER(esp_xtensa_smp_cmd_xtdef)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ if (target->smp && CMD_ARGC > 0) {
+ struct target_list *head;
+ struct target *curr;
+ foreach_smp_target(head, target->smp_targets) {
+ curr = head->target;
+ int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtdef_do,
+ target_to_xtensa(curr));
+ if (ret != ERROR_OK)
+ return ret;
+ }
+ return ERROR_OK;
+ }
+ return CALL_COMMAND_HANDLER(xtensa_cmd_xtdef_do,
+ target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_xtopt)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ if (target->smp && CMD_ARGC > 0) {
+ struct target_list *head;
+ struct target *curr;
+ foreach_smp_target(head, target->smp_targets) {
+ curr = head->target;
+ int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtopt_do,
+ target_to_xtensa(curr));
+ if (ret != ERROR_OK)
+ return ret;
+ }
+ return ERROR_OK;
+ }
+ return CALL_COMMAND_HANDLER(xtensa_cmd_xtopt_do,
+ target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmem)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ if (target->smp && CMD_ARGC > 0) {
+ struct target_list *head;
+ struct target *curr;
+ foreach_smp_target(head, target->smp_targets) {
+ curr = head->target;
+ int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmem_do,
+ target_to_xtensa(curr));
+ if (ret != ERROR_OK)
+ return ret;
+ }
+ return ERROR_OK;
+ }
+ return CALL_COMMAND_HANDLER(xtensa_cmd_xtmem_do,
+ target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmpu)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ if (target->smp && CMD_ARGC > 0) {
+ struct target_list *head;
+ struct target *curr;
+ foreach_smp_target(head, target->smp_targets) {
+ curr = head->target;
+ int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmpu_do,
+ target_to_xtensa(curr));
+ if (ret != ERROR_OK)
+ return ret;
+ }
+ return ERROR_OK;
+ }
+ return CALL_COMMAND_HANDLER(xtensa_cmd_xtmpu_do,
+ target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmmu)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ if (target->smp && CMD_ARGC > 0) {
+ struct target_list *head;
+ struct target *curr;
+ foreach_smp_target(head, target->smp_targets) {
+ curr = head->target;
+ int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmmu_do,
+ target_to_xtensa(curr));
+ if (ret != ERROR_OK)
+ return ret;
+ }
+ return ERROR_OK;
+ }
+ return CALL_COMMAND_HANDLER(xtensa_cmd_xtmmu_do,
+ target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_xtreg)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ if (target->smp && CMD_ARGC > 0) {
+ struct target_list *head;
+ struct target *curr;
+ foreach_smp_target(head, target->smp_targets) {
+ curr = head->target;
+ int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtreg_do,
+ target_to_xtensa(curr));
+ if (ret != ERROR_OK)
+ return ret;
+ }
+ return ERROR_OK;
+ }
+ return CALL_COMMAND_HANDLER(xtensa_cmd_xtreg_do,
+ target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_xtregfmt)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ if (target->smp && CMD_ARGC > 0) {
+ struct target_list *head;
+ struct target *curr;
+ foreach_smp_target(head, target->smp_targets) {
+ curr = head->target;
+ int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtregfmt_do,
+ target_to_xtensa(curr));
+ if (ret != ERROR_OK)
+ return ret;
+ }
+ return ERROR_OK;
+ }
+ return CALL_COMMAND_HANDLER(xtensa_cmd_xtregfmt_do,
+ target_to_xtensa(target));
+}
+
COMMAND_HANDLER(esp_xtensa_smp_cmd_permissive_mode)
{
struct target *target = get_current_target(CMD_CTX);
@@ -632,6 +764,62 @@ COMMAND_HANDLER(esp_xtensa_smp_cmd_tracedump)
}
const struct command_registration esp_xtensa_smp_xtensa_command_handlers[] = {
+ {
+ .name = "xtdef",
+ .handler = esp_xtensa_smp_cmd_xtdef,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure Xtensa core type",
+ .usage = "<type>",
+ },
+ {
+ .name = "xtopt",
+ .handler = esp_xtensa_smp_cmd_xtopt,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure Xtensa core option",
+ .usage = "<name> <value>",
+ },
+ {
+ .name = "xtmem",
+ .handler = esp_xtensa_smp_cmd_xtmem,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure Xtensa memory/cache option",
+ .usage = "<type> [parameters]",
+ },
+ {
+ .name = "xtmmu",
+ .handler = esp_xtensa_smp_cmd_xtmmu,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure Xtensa MMU option",
+ .usage = "<NIREFILLENTRIES> <NDREFILLENTRIES> <IVARWAY56> <DVARWAY56>",
+ },
+ {
+ .name = "xtmpu",
+ .handler = esp_xtensa_smp_cmd_xtmpu,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure Xtensa MPU option",
+ .usage = "<num FG seg> <min seg size> <lockable> <executeonly>",
+ },
+ {
+ .name = "xtreg",
+ .handler = esp_xtensa_smp_cmd_xtreg,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure Xtensa register",
+ .usage = "<regname> <regnum>",
+ },
+ {
+ .name = "xtregs",
+ .handler = esp_xtensa_smp_cmd_xtreg,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure number of Xtensa registers",
+ .usage = "<numregs>",
+ },
+ {
+ .name = "xtregfmt",
+ .handler = esp_xtensa_smp_cmd_xtregfmt,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure format of Xtensa register map",
+ .usage = "<numgregs>",
+ },
{
.name = "set_permissive",
.handler = esp_xtensa_smp_cmd_permissive_mode,
diff --git a/src/target/espressif/esp_xtensa_smp.h b/src/target/espressif/esp_xtensa_smp.h
index 159125d37..bafd42066 100644
--- a/src/target/espressif/esp_xtensa_smp.h
+++ b/src/target/espressif/esp_xtensa_smp.h
@@ -43,7 +43,6 @@ int esp_xtensa_smp_handle_target_event(struct target *target, enum target_event
int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *target);
int esp_xtensa_smp_init_arch_info(struct target *target,
struct esp_xtensa_smp_common *esp_xtensa_smp,
- const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg,
const struct esp_xtensa_smp_chip_ops *chip_ops);
diff --git a/src/target/target.c b/src/target/target.c
index 10a25efde..9b07dbf61 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -77,6 +77,7 @@ extern struct target_type fa526_target;
extern struct target_type feroceon_target;
extern struct target_type dragonite_target;
extern struct target_type xscale_target;
+extern struct target_type xtensa_chip_target;
extern struct target_type cortexm_target;
extern struct target_type cortexa_target;
extern struct target_type aarch64_target;
@@ -118,6 +119,7 @@ static struct target_type *target_types[] = {
&feroceon_target,
&dragonite_target,
&xscale_target,
+ &xtensa_chip_target,
&cortexm_target,
&cortexa_target,
&cortexr4_target,
diff --git a/src/target/xtensa/Makefile.am b/src/target/xtensa/Makefile.am
index a11e58530..94c7c4a85 100644
--- a/src/target/xtensa/Makefile.am
+++ b/src/target/xtensa/Makefile.am
@@ -4,6 +4,8 @@ noinst_LTLIBRARIES += %D%/libxtensa.la
%C%_libxtensa_la_SOURCES = \
%D%/xtensa.c \
%D%/xtensa.h \
+ %D%/xtensa_chip.c \
+ %D%/xtensa_chip.h \
%D%/xtensa_debug_module.c \
%D%/xtensa_debug_module.h \
%D%/xtensa_regs.h
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index 6f9d77e6c..fe0f43882 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -2,6 +2,7 @@
/***************************************************************************
* Generic Xtensa target API for OpenOCD *
+ * Copyright (C) 2020-2022 Cadence Design Systems, Inc. *
* Copyright (C) 2016-2019 Espressif Systems Ltd. *
* Derived from esp108.c *
* Author: Angus Gratton gu...@pr... *
@@ -16,325 +17,270 @@
#include <helper/align.h>
#include <target/register.h>
+#include "xtensa_chip.h"
#include "xtensa.h"
-
-#define _XT_INS_FORMAT_RSR(OPCODE, SR, T) ((OPCODE) \
- | (((SR) & 0xFF) << 8) \
+/* Swap 4-bit Xtensa opcodes and fields */
+#define XT_NIBSWAP8(V) \
+ ((((V) & 0x0F) << 4) \
+ | (((V) & 0xF0) >> 4))
+
+#define XT_NIBSWAP16(V) \
+ ((((V) & 0x000F) << 12) \
+ | (((V) & 0x00F0) << 4) \
+ | (((V) & 0x0F00) >> 4) \
+ | (((V) & 0xF000) >> 12))
+
+#define XT_NIBSWAP24(V) \
+ ((((V) & 0x00000F) << 20) \
+ | (((V) & 0x0000F0) << 12) \
+ | (((V) & 0x000F00) << 4) \
+ | (((V) & 0x00F000) >> 4) \
+ | (((V) & 0x0F0000) >> 12) \
+ | (((V) & 0xF00000) >> 20))
+
+/* _XT_INS_FORMAT_*()
+ * Instruction formatting converted from little-endian inputs
+ * and shifted to the MSB-side of DIR for BE systems.
+ */
+#define _XT_INS_FORMAT_RSR(X, OPCODE, SR, T) \
+ (XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \
+ | (((T) & 0x0F) << 16) \
+ | (((SR) & 0xFF) << 8)) << 8 \
+ : (OPCODE) \
+ | (((SR) & 0xFF) << 8) \
| (((T) & 0x0F) << 4))
-#define _XT_INS_FORMAT_RRR(OPCODE, ST, R) ((OPCODE) \
- | (((ST) & 0xFF) << 4) \
+#define _XT_INS_FORMAT_RRR(X, OPCODE, ST, R) \
+ (XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \
+ | ((XT_NIBSWAP8((ST) & 0xFF)) << 12) \
+ | (((R) & 0x0F) << 8)) << 8 \
+ : (OPCODE) \
+ | (((ST) & 0xFF) << 4) \
| (((R) & 0x0F) << 12))
-#define _XT_INS_FORMAT_RRRN(OPCODE, S, T, IMM4) ((OPCODE) \
- | (((T) & 0x0F) << 4) \
- | (((S) & 0x0F) << 8) \
+#define _XT_INS_FORMAT_RRRN(X, OPCODE, S, T, IMM4) \
+ (XT_ISBE(X) ? (XT_NIBSWAP16(OPCODE) \
+ | (((T) & 0x0F) << 8) \
+ | (((S) & 0x0F) << 4) \
+ | ((IMM4) & 0x0F)) << 16 \
+ : (OPCODE) \
+ | (((T) & 0x0F) << 4) \
+ | (((S) & 0x0F) << 8) \
| (((IMM4) & 0x0F) << 12))
-#define _XT_INS_FORMAT_RRI8(OPCODE, R, S, T, IMM8) ((OPCODE) \
- | (((IMM8) & 0xFF) << 16) \
- | (((R) & 0x0F) << 12) \
- | (((S) & 0x0F) << 8) \
+#define _XT_INS_FORMAT_RRI8(X, OPCODE, R, S, T, IMM8) \
+ (XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \
+ | (((T) & 0x0F) << 16) \
+ | (((S) & 0x0F) << 12) \
+ | (((R) & 0x0F) << 8) \
+ | ((IMM8) & 0xFF)) << 8 \
+ : (OPCODE) \
+ | (((IMM8) & 0xFF) << 16) \
+ | (((R) & 0x0F) << 12) \
+ | (((S) & 0x0F) << 8) \
| (((T) & 0x0F) << 4))
-#define _XT_INS_FORMAT_RRI4(OPCODE, IMM4, R, S, T) ((OPCODE) \
- | (((IMM4) & 0x0F) << 20) \
- | (((R) & 0x0F) << 12) \
- | (((S) & 0x0F) << 8) \
+#define _XT_INS_FORMAT_RRI4(X, OPCODE, IMM4, R, S, T) \
+ (XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \
+ | (((T) & 0x0F) << 16) \
+ | (((S) & 0x0F) << 12) \
+ | (((R) & 0x0F) << 8)) << 8 \
+ | ((IMM4) & 0x0F) \
+ : (OPCODE) \
+ | (((IMM4) & 0x0F) << 20) \
+ | (((R) & 0x0F) << 12) \
+ | (((S) & 0x0F) << 8) \
| (((T) & 0x0F) << 4))
/* Xtensa processor instruction opcodes
- * "Return From Debug Operation" to Normal */
-#define XT_INS_RFDO 0xf1e000
+*/
+/* "Return From Debug Operation" to Normal */
+#define XT_INS_RFDO(X) (XT_ISBE(X) ? 0x000e1f << 8 : 0xf1e000)
/* "Return From Debug and Dispatch" - allow sw debugging stuff to take over */
-#define XT_INS_RFDD 0xf1e010
+#define XT_INS_RFDD(X) (XT_ISBE(X) ? 0x010e1f << 8 : 0xf1e010)
/* Load to DDR register, increase addr register */
-#define XT_INS_LDDR32P(S) (0x0070E0 | ((S) << 8))
+#define XT_INS_LDDR32P(X, S) (XT_ISBE(X) ? (0x0E0700 | ((S) << 12)) << 8 : (0x0070E0 | ((S) << 8)))
/* Store from DDR register, increase addr register */
-#define XT_INS_SDDR32P(S) (0x0070F0 | ((S) << 8))
-
-/* Load 32-bit Indirect from A(S) + 4 * IMM8 to A(T) */
-#define XT_INS_L32I(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x002002, 0, S, T, IMM8)
-/* Load 16-bit Unsigned from A(S) + 2 * IMM8 to A(T) */
-#define XT_INS_L16UI(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x001002, 0, S, T, IMM8)
-/* Load 8-bit Unsigned from A(S) + IMM8 to A(T) */
-#define XT_INS_L8UI(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x000002, 0, S, T, IMM8)
-
-/* Store 32-bit Indirect to A(S) + 4 * IMM8 from A(T) */
-#define XT_INS_S32I(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x006002, 0, S, T, IMM8)
-/* Store 16-bit to A(S) + 2 * IMM8 from A(T) */
-#define XT_INS_S16I(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x005002, 0, S, T, IMM8)
-/* Store 8-bit to A(S) + IMM8 from A(T) */
-#define XT_INS_S8I(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x004002, 0, S, T, IMM8)
+#define XT_INS_SDDR32P(X, S) (XT_ISBE(X) ? (0x0F0700 | ((S) << 12)) << 8 : (0x0070F0 | ((S) << 8)))
+
+/* Load 32-bit Indirect from A(S)+4*IMM8 to A(T) */
+#define XT_INS_L32I(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x002002, 0, S, T, IMM8)
+/* Load 16-bit Unsigned from A(S)+2*IMM8 to A(T) */
+#define XT_INS_L16UI(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x001002, 0, S, T, IMM8)
+/* Load 8-bit Unsigned f...
[truncated message content] |
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-20 15:32:31
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via be2e5c6c35f77fecb4df2a19cec05cceac500ca9 (commit)
from 9ffeedb5794e5ebe7b3a7d7fd63fde4d7124c0dd (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit be2e5c6c35f77fecb4df2a19cec05cceac500ca9
Author: Jae Hyun Yoo <qui...@qu...>
Date: Thu Jan 20 12:07:58 2022 -0800
tcl/interface: add linuxgpiod cfg for Aspeed AST2600
Add linuxgpiod cfg for Aspeed AST2600 for a case if JTAG master needs
to be implemented using linuxgpiod intead of hardware JTAG master mode.
These AST2600 GPIOs will be mapped to JTAG/SWD signals.
+-----------+-------------+-------------+
| signal | GPIO name | gpio offset |
+-----------+-------------+-------------+
| TCK/SWCLK | GPIOI2 | 66 |
| TMS/SWDIO | GPIOI3 | 67 |
| TDI | GPIOI1 | 65 |
| TDO | GPIOI4 | 68 |
| nTRST | GPIOI0 | 64 |
+-----------+-------------+-------------+
Signed-off-by: Jae Hyun Yoo <qui...@qu...>
Change-Id: I19278402b0895be12d38c0ecea8fdbc56fd491b8
Reviewed-on: https://review.openocd.org/c/openocd/+/7112
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/tcl/interface/ast2600-gpiod.cfg b/tcl/interface/ast2600-gpiod.cfg
new file mode 100644
index 000000000..5cad02fbd
--- /dev/null
+++ b/tcl/interface/ast2600-gpiod.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Use AST2600 GPIO through linuxgpiod
+#
+# +-----------+-------------+-------------+
+# | signal | GPIO name | gpio offset |
+# +-----------+-------------+-------------+
+# | TCK/SWCLK | GPIOI2 | 66 |
+# | TMS/SWDIO | GPIOI3 | 67 |
+# | TDI | GPIOI1 | 65 |
+# | TDO | GPIOI4 | 68 |
+# | nTRST | GPIOI0 | 64 |
+# +-----------+-------------+-------------+
+
+adapter driver linuxgpiod
+
+adapter gpio trst 64 -chip 0
+adapter gpio tdi 65 -chip 0
+adapter gpio tck 66 -chip 0
+adapter gpio swclk 66 -chip 0
+adapter gpio tms 67 -chip 0
+adapter gpio swdio 67 -chip 0
+adapter gpio tdo 68 -chip 0
+
+reset_config trst_only separate trst_push_pull
-----------------------------------------------------------------------
Summary of changes:
tcl/interface/ast2600-gpiod.cfg | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 tcl/interface/ast2600-gpiod.cfg
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-20 15:30:20
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 9ffeedb5794e5ebe7b3a7d7fd63fde4d7124c0dd (commit)
from 5f46de2e79db6377410107961ed81fae7e61c39f (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 9ffeedb5794e5ebe7b3a7d7fd63fde4d7124c0dd
Author: Jae Hyun Yoo <qui...@qu...>
Date: Thu Jan 20 12:31:18 2022 -0800
tcl/fpga: add Lattice MachXO3 family support
Add support for Lattice MachXO3 FPGA family.
Signed-off-by: Jae Hyun Yoo <qui...@qu...>
Change-Id: I01fcec0ee458e809246e4505019d15047655dd47
Reviewed-on: https://review.openocd.org/c/openocd/+/7113
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/fpga/lattice_machxo3.cfg b/tcl/fpga/lattice_machxo3.cfg
new file mode 100644
index 000000000..37fa05430
--- /dev/null
+++ b/tcl/fpga/lattice_machxo3.cfg
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME machxo3
+}
+
+# Lattice MachXO3 family
+# TAP IDs are extracted from BSDL files found on this page:
+# https://www.latticesemi.com/Products/FPGAandCPLD/MachXO3
+#
+# 0x412b2043 - LCMXO3L_1300E_XXUWG36/XXMG121
+# 0x412b3043 - LCMXO3L_2100E_XXMG121/XXMG256/XXUWG49
+# 0x412b4043 - LCMXO3L_4300E_XXMG121/XXMG324/XXUWG81
+# 0x412b5043 - LCMXO3L_6900E_XXMG256/XXMG324
+# 0x412b6043 - LCMXO3L_9400E_XXBG256/XXMG256
+# 0x412bb043 - LCMXO3L_2100C_XXBG256
+# 0x412bc043 - LCMXO3L_4300C_XXBG256/XXBG324
+# 0x412bd043 - LCMXO3L_6900C_XXBG256/XXBG324/XXBG400
+# 0x412be043 - LCMXO3L_9400C_XXBG256/XXBG400/XXBG484
+# 0x612b2043 - LCMXO3LF_1300E_XXMG121/XXUWG36
+# 0x612b3043 - LCMXO3LF_2100E_XXMG121/XXMG256/XXUWG49
+# 0x612b4043 - LCMXO3LF_4300E_XXMG121/XXMG256/XXMG324/XXUWG81
+# 0x612b5043 - LCMXO3LF_6900E_XXMG256/XXMG324
+# 0x612b6043 - LCMXO3LF_9400E_XXBG256/XXMG256
+# 0x612bb043 - LCMXO3LF_2100C_XXBG256
+# 0x612bc043 - LCMXO3LF_4300C_XXBG256/XXBG324
+# 0x612bd043 - LCMXO3LF_6900C_XXBG256/XXBG324/XXBG400
+# 0x612be043 - LCMXO3LF_9400C_XXBG256/XXBG400/XXBG484
+# 0xc12b2043 - LCMXO3L_640E_XXMG121
+# 0xc12b4043 - LCMXO3L_2100E_XXMG324
+# 0xc12bb043 - LCMXO3L_1300C_XXBG256/XXMG256
+# 0xc12bc043 - LCMXO3L_2100C_XXBG324
+# 0xc12bd043 - LCMXO3L_4300C_XXBG400
+# 0xe12b2043 - LCMXO3LF_640E_XXMG121
+# 0xe12b3043 - LCMXO3LF_1300E_XXMG256
+# 0xe12b4043 - LCMXO3LF_2100E_XXMG324
+# 0xe12bb043 - LCMXO3LF_1300C_XXBG256
+# 0xe12bc043 - LCMXO3LF_2100C_XXBG324
+# 0xe12bd043 - LCMXO3LF_4300C_XXBG400
+
+jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
+ -expected-id 0x412b2043 -expected-id 0x412b3043 -expected-id 0x412b4043 \
+ -expected-id 0x412b5043 -expected-id 0x412b6043 -expected-id 0x412bb043 \
+ -expected-id 0x412bc043 -expected-id 0x412bd043 -expected-id 0x412be043 \
+ -expected-id 0x612b2043 -expected-id 0x612b3043 -expected-id 0x612b4043 \
+ -expected-id 0x612b5043 -expected-id 0x612b6043 -expected-id 0x612bb043 \
+ -expected-id 0x612bc043 -expected-id 0x612bd043 -expected-id 0x612be043 \
+ -expected-id 0xc12b2043 -expected-id 0xc12b4043 -expected-id 0xc12bb043 \
+ -expected-id 0xc12bc043 -expected-id 0xc12bd043 -expected-id 0xe12b2043 \
+ -expected-id 0xe12b3043 -expected-id 0xe12b4043 -expected-id 0xe12bb043 \
+ -expected-id 0xe12bc043 -expected-id 0xe12bd043
-----------------------------------------------------------------------
Summary of changes:
tcl/fpga/lattice_machxo3.cfg | 53 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 tcl/fpga/lattice_machxo3.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-20 15:29:42
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 5f46de2e79db6377410107961ed81fae7e61c39f (commit)
from c271958850e27de62557ce75fae658b2abd1f3ba (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 5f46de2e79db6377410107961ed81fae7e61c39f
Author: MadSquirrel <ben...@ci...>
Date: Sat Jun 4 22:01:11 2022 +0200
server/gdb_server: Add support for default thread, use by IDA debugger
Signed-off-by: Benoit Forgette <ben...@ci...>
Change-Id: Ia3a29a3377be650f0ccad11a0ae4fe4da78b3ab4
Reviewed-on: https://review.openocd.org/c/openocd/+/7017
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 1e50b43f3..5cffa23d1 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -3030,128 +3030,127 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p
gdb_running_type = 's';
bool fake_step = false;
- if (strncmp(parse, "s:", 2) == 0) {
- struct target *ct = target;
- int current_pc = 1;
- int64_t thread_id;
+ struct target *ct = target;
+ int current_pc = 1;
+ int64_t thread_id;
+ parse++;
+ packet_size--;
+ if (parse[0] == ':') {
char *endp;
-
- parse += 2;
- packet_size -= 2;
-
+ parse++;
+ packet_size--;
thread_id = strtoll(parse, &endp, 16);
if (endp) {
packet_size -= endp - parse;
parse = endp;
}
+ } else {
+ thread_id = 0;
+ }
+
+ if (target->rtos) {
+ /* FIXME: why is this necessary? rtos state should be up-to-date here already! */
+ rtos_update_threads(target);
- if (target->rtos) {
- /* FIXME: why is this necessary? rtos state should be up-to-date here already! */
- rtos_update_threads(target);
+ target->rtos->gdb_target_for_threadid(connection, thread_id, &ct);
- target->rtos->gdb_target_for_threadid(connection, thread_id, &ct);
+ /*
+ * check if the thread to be stepped is the current rtos thread
+ * if not, we must fake the step
+ */
+ if (target->rtos->current_thread != thread_id)
+ fake_step = true;
+ }
- /*
- * check if the thread to be stepped is the current rtos thread
- * if not, we must fake the step
- */
- if (target->rtos->current_thread != thread_id)
- fake_step = true;
- }
+ if (parse[0] == ';') {
+ ++parse;
+ --packet_size;
- if (parse[0] == ';') {
- ++parse;
- --packet_size;
+ if (parse[0] == 'c') {
+ parse += 1;
- if (parse[0] == 'c') {
+ /* check if thread-id follows */
+ if (parse[0] == ':') {
+ int64_t tid;
parse += 1;
- /* check if thread-id follows */
- if (parse[0] == ':') {
- int64_t tid;
- parse += 1;
-
- tid = strtoll(parse, &endp, 16);
- if (tid == thread_id) {
- /*
- * Special case: only step a single thread (core),
- * keep the other threads halted. Currently, only
- * aarch64 target understands it. Other target types don't
- * care (nobody checks the actual value of 'current')
- * and it doesn't really matter. This deserves
- * a symbolic constant and a formal interface documentation
- * at a later time.
- */
- LOG_DEBUG("request to step current core only");
- /* uncomment after checking that indeed other targets are safe */
- /*current_pc = 2;*/
- }
+ tid = strtoll(parse, NULL, 16);
+ if (tid == thread_id) {
+ /*
+ * Special case: only step a single thread (core),
+ * keep the other threads halted. Currently, only
+ * aarch64 target understands it. Other target types don't
+ * care (nobody checks the actual value of 'current')
+ * and it doesn't really matter. This deserves
+ * a symbolic constant and a formal interface documentation
+ * at a later time.
+ */
+ LOG_DEBUG("request to step current core only");
+ /* uncomment after checking that indeed other targets are safe */
+ /*current_pc = 2;*/
}
}
}
+ }
- LOG_DEBUG("target %s single-step thread %"PRIx64, target_name(ct), thread_id);
- gdb_connection->output_flag = GDB_OUTPUT_ALL;
- target_call_event_callbacks(ct, TARGET_EVENT_GDB_START);
-
- /*
- * work around an annoying gdb behaviour: when the current thread
- * is changed in gdb, it assumes that the target can follow and also
- * make the thread current. This is an assumption that cannot hold
- * for a real target running a multi-threading OS. We just fake
- * the step to not trigger an internal error in gdb. See
- * https://sourceware.org/bugzilla/show_bug.cgi?id=22925 for details
- */
- if (fake_step) {
- int sig_reply_len;
- char sig_reply[128];
-
- LOG_DEBUG("fake step thread %"PRIx64, thread_id);
+ LOG_DEBUG("target %s single-step thread %"PRIx64, target_name(ct), thread_id);
+ gdb_connection->output_flag = GDB_OUTPUT_ALL;
+ target_call_event_callbacks(ct, TARGET_EVENT_GDB_START);
- sig_reply_len = snprintf(sig_reply, sizeof(sig_reply),
- "T05thread:%016"PRIx64";", thread_id);
+ /*
+ * work around an annoying gdb behaviour: when the current thread
+ * is changed in gdb, it assumes that the target can follow and also
+ * make the thread current. This is an assumption that cannot hold
+ * for a real target running a multi-threading OS. We just fake
+ * the step to not trigger an internal error in gdb. See
+ * https://sourceware.org/bugzilla/show_bug.cgi?id=22925 for details
+ */
+ if (fake_step) {
+ int sig_reply_len;
+ char sig_reply[128];
- gdb_put_packet(connection, sig_reply, sig_reply_len);
- gdb_connection->output_flag = GDB_OUTPUT_NO;
+ LOG_DEBUG("fake step thread %"PRIx64, thread_id);
- return true;
- }
+ sig_reply_len = snprintf(sig_reply, sizeof(sig_reply),
+ "T05thread:%016"PRIx64";", thread_id);
- /* support for gdb_sync command */
- if (gdb_connection->sync) {
- gdb_connection->sync = false;
- if (ct->state == TARGET_HALTED) {
- LOG_DEBUG("stepi ignored. GDB will now fetch the register state "
- "from the target.");
- gdb_sig_halted(connection);
- gdb_connection->output_flag = GDB_OUTPUT_NO;
- } else
- gdb_connection->frontend_state = TARGET_RUNNING;
- return true;
- }
+ gdb_put_packet(connection, sig_reply, sig_reply_len);
+ gdb_connection->output_flag = GDB_OUTPUT_NO;
- retval = target_step(ct, current_pc, 0, 0);
- if (retval == ERROR_TARGET_NOT_HALTED)
- LOG_INFO("target %s was not halted when step was requested", target_name(ct));
+ return true;
+ }
- /* if step was successful send a reply back to gdb */
- if (retval == ERROR_OK) {
- retval = target_poll(ct);
- if (retval != ERROR_OK)
- LOG_DEBUG("error polling target %s after successful step", target_name(ct));
- /* send back signal information */
- gdb_signal_reply(ct, connection);
- /* stop forwarding log packets! */
+ /* support for gdb_sync command */
+ if (gdb_connection->sync) {
+ gdb_connection->sync = false;
+ if (ct->state == TARGET_HALTED) {
+ LOG_DEBUG("stepi ignored. GDB will now fetch the register state "
+ "from the target.");
+ gdb_sig_halted(connection);
gdb_connection->output_flag = GDB_OUTPUT_NO;
} else
gdb_connection->frontend_state = TARGET_RUNNING;
- } else {
- LOG_ERROR("Unknown vCont packet");
- return false;
+ return true;
}
+
+ retval = target_step(ct, current_pc, 0, 0);
+ if (retval == ERROR_TARGET_NOT_HALTED)
+ LOG_INFO("target %s was not halted when step was requested", target_name(ct));
+
+ /* if step was successful send a reply back to gdb */
+ if (retval == ERROR_OK) {
+ retval = target_poll(ct);
+ if (retval != ERROR_OK)
+ LOG_DEBUG("error polling target %s after successful step", target_name(ct));
+ /* send back signal information */
+ gdb_signal_reply(ct, connection);
+ /* stop forwarding log packets! */
+ gdb_connection->output_flag = GDB_OUTPUT_NO;
+ } else
+ gdb_connection->frontend_state = TARGET_RUNNING;
return true;
}
-
+ LOG_ERROR("Unknown vCont packet");
return false;
}
-----------------------------------------------------------------------
Summary of changes:
src/server/gdb_server.c | 185 ++++++++++++++++++++++++------------------------
1 file changed, 92 insertions(+), 93 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-20 15:29:20
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via c271958850e27de62557ce75fae658b2abd1f3ba (commit)
from 9cd714cd145a73a4f43bdfc37554f4d5ab05f92b (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit c271958850e27de62557ce75fae658b2abd1f3ba
Author: Erhan Kurubas <erh...@es...>
Date: Thu Aug 11 01:32:25 2022 +0200
target/semihosting: drop type casting from semihosting->result
Also used type helper (PRId64) to specify format of int64_t
Signed-off-by: Erhan Kurubas <erh...@es...>
Change-Id: I594863eab594aff621c26fefcc69a1872e9730ee
Reviewed-on: https://review.openocd.org/c/openocd/+/7111
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/semihosting_common.c b/src/target/semihosting_common.c
index e31ff6fd4..c449b0539 100644
--- a/src/target/semihosting_common.c
+++ b/src/target/semihosting_common.c
@@ -406,7 +406,7 @@ int semihosting_common(struct target *target)
} else {
semihosting->result = close(fd);
semihosting->sys_errno = errno;
- LOG_DEBUG("close(%d)=%d", fd, (int)semihosting->result);
+ LOG_DEBUG("close(%d)=%" PRId64, fd, semihosting->result);
}
}
break;
@@ -631,10 +631,10 @@ int semihosting_common(struct target *target)
semihosting->result = fstat(fd, &buf);
if (semihosting->result == -1) {
semihosting->sys_errno = errno;
- LOG_DEBUG("fstat(%d)=%d", fd, (int)semihosting->result);
+ LOG_DEBUG("fstat(%d)=%" PRId64, fd, semihosting->result);
break;
}
- LOG_DEBUG("fstat(%d)=%d", fd, (int)semihosting->result);
+ LOG_DEBUG("fstat(%d)=%" PRId64, fd, semihosting->result);
semihosting->result = buf.st_size;
}
break;
@@ -691,8 +691,7 @@ int semihosting_common(struct target *target)
if (retval != ERROR_OK)
return retval;
}
- LOG_DEBUG("SYS_GET_CMDLINE=[%s],%d", arg,
- (int)semihosting->result);
+ LOG_DEBUG("SYS_GET_CMDLINE=[%s], %" PRId64, arg, semihosting->result);
}
break;
@@ -784,7 +783,7 @@ int semihosting_common(struct target *target)
int fd = semihosting_get_field(target, 0, fields);
semihosting->result = isatty(fd);
semihosting->sys_errno = errno;
- LOG_DEBUG("isatty(%d)=%d", fd, (int)semihosting->result);
+ LOG_DEBUG("isatty(%d)=%" PRId64, fd, semihosting->result);
}
break;
@@ -902,22 +901,19 @@ int semihosting_common(struct target *target)
semihosting->result = fd;
semihosting->stdin_fd = fd;
semihosting->sys_errno = errno;
- LOG_DEBUG("dup(STDIN)=%d",
- (int)semihosting->result);
+ LOG_DEBUG("dup(STDIN)=%" PRId64, semihosting->result);
} else if (mode < 8) {
int fd = dup(STDOUT_FILENO);
semihosting->result = fd;
semihosting->stdout_fd = fd;
semihosting->sys_errno = errno;
- LOG_DEBUG("dup(STDOUT)=%d",
- (int)semihosting->result);
+ LOG_DEBUG("dup(STDOUT)=%" PRId64, semihosting->result);
} else {
int fd = dup(STDERR_FILENO);
semihosting->result = fd;
semihosting->stderr_fd = fd;
semihosting->sys_errno = errno;
- LOG_DEBUG("dup(STDERR)=%d",
- (int)semihosting->result);
+ LOG_DEBUG("dup(STDERR)=%" PRId64, semihosting->result);
}
} else {
/* cygwin requires the permission setting
@@ -927,8 +923,7 @@ int semihosting_common(struct target *target)
open_host_modeflags[mode],
0644);
semihosting->sys_errno = errno;
- LOG_DEBUG("open('%s')=%d", fn,
- (int)semihosting->result);
+ LOG_DEBUG("open('%s')=%" PRId64, fn, semihosting->result);
}
}
free(fn);
@@ -991,11 +986,11 @@ int semihosting_common(struct target *target)
semihosting->sys_errno = ENOMEM;
} else {
semihosting->result = semihosting_read(semihosting, fd, buf, len);
- LOG_DEBUG("read(%d, 0x%" PRIx64 ", %zu)=%d",
+ LOG_DEBUG("read(%d, 0x%" PRIx64 ", %zu)=%" PRId64,
fd,
addr,
len,
- (int)semihosting->result);
+ semihosting->result);
if (semihosting->result >= 0) {
retval = target_write_buffer(target, addr,
semihosting->result,
@@ -1031,7 +1026,7 @@ int semihosting_common(struct target *target)
return ERROR_FAIL;
}
semihosting->result = semihosting_getchar(semihosting, semihosting->stdin_fd);
- LOG_DEBUG("getchar()=%d", (int)semihosting->result);
+ LOG_DEBUG("getchar()=%" PRId64, semihosting->result);
break;
case SEMIHOSTING_SYS_REMOVE: /* 0x0E */
@@ -1077,8 +1072,7 @@ int semihosting_common(struct target *target)
fn[len] = 0;
semihosting->result = remove((char *)fn);
semihosting->sys_errno = errno;
- LOG_DEBUG("remove('%s')=%d", fn,
- (int)semihosting->result);
+ LOG_DEBUG("remove('%s')=%" PRId64, fn, semihosting->result);
free(fn);
}
@@ -1147,9 +1141,7 @@ int semihosting_common(struct target *target)
semihosting->result = rename((char *)fn1,
(char *)fn2);
semihosting->sys_errno = errno;
- LOG_DEBUG("rename('%s', '%s')=%d", fn1, fn2,
- (int)semihosting->result);
-
+ LOG_DEBUG("rename('%s', '%s')=%" PRId64 " %d", fn1, fn2, semihosting->result, errno);
free(fn1);
free(fn2);
}
@@ -1194,8 +1186,7 @@ int semihosting_common(struct target *target)
} else {
semihosting->result = lseek(fd, pos, SEEK_SET);
semihosting->sys_errno = errno;
- LOG_DEBUG("lseek(%d, %d)=%d", fd, (int)pos,
- (int)semihosting->result);
+ LOG_DEBUG("lseek(%d, %d)=%" PRId64, fd, (int)pos, semihosting->result);
if (semihosting->result == pos)
semihosting->result = 0;
}
@@ -1254,9 +1245,7 @@ int semihosting_common(struct target *target)
cmd[len] = 0;
semihosting->result = system(
(const char *)cmd);
- LOG_DEBUG("system('%s')=%d",
- cmd,
- (int)semihosting->result);
+ LOG_DEBUG("system('%s')=%" PRId64, cmd, semihosting->result);
}
free(cmd);
@@ -1335,11 +1324,11 @@ int semihosting_common(struct target *target)
}
semihosting->result = semihosting_write(semihosting, fd, buf, len);
semihosting->sys_errno = errno;
- LOG_DEBUG("write(%d, 0x%" PRIx64 ", %zu)=%d",
+ LOG_DEBUG("write(%d, 0x%" PRIx64 ", %zu)=%" PRId64,
fd,
addr,
len,
- (int)semihosting->result);
+ semihosting->result);
if (semihosting->result >= 0) {
/* The number of bytes that are NOT written.
* */
-----------------------------------------------------------------------
Summary of changes:
src/target/semihosting_common.c | 47 ++++++++++++++++-------------------------
1 file changed, 18 insertions(+), 29 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-15 13:27:37
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 9cd714cd145a73a4f43bdfc37554f4d5ab05f92b (commit)
from 290eac04b93cd2f98e0a921e9dbf73b0822ae33b (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 9cd714cd145a73a4f43bdfc37554f4d5ab05f92b
Author: Erhan Kurubas <erh...@es...>
Date: Tue Aug 2 01:15:12 2022 +0200
target/espressif: remove author lines from esp32xx and xtensa files
Some files have author info some doesn't. For the consistency we removed all.
Signed-off-by: Erhan Kurubas <erh...@es...>
Change-Id: Ie6f1ec012302e3a954c75c5106f12820722cb715
Reviewed-on: https://review.openocd.org/c/openocd/+/7104
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/esp_usb_jtag.c b/src/jtag/drivers/esp_usb_jtag.c
index a73984a3a..d280c6ad8 100644
--- a/src/jtag/drivers/esp_usb_jtag.c
+++ b/src/jtag/drivers/esp_usb_jtag.c
@@ -1,20 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Espressif USB to Jtag adapter *
* Copyright (C) 2020 Espressif Systems (Shanghai) Co. Ltd. *
- * Author: Jeroen Domburg <je...@es...> *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
diff --git a/src/target/espressif/esp32.c b/src/target/espressif/esp32.c
index 29d94a272..de8f1aacf 100644
--- a/src/target/espressif/esp32.c
+++ b/src/target/espressif/esp32.c
@@ -3,8 +3,6 @@
/***************************************************************************
* ESP32 target API for OpenOCD *
* Copyright (C) 2016-2019 Espressif Systems Ltd. *
- * Author: Dmitry Yakovlev <dm...@es...> *
- * Author: Alexey Gerenkov <al...@es...> *
***************************************************************************/
#ifdef HAVE_CONFIG_H
diff --git a/src/target/espressif/esp32s2.c b/src/target/espressif/esp32s2.c
index 4251e84c9..bbf7ff5af 100644
--- a/src/target/espressif/esp32s2.c
+++ b/src/target/espressif/esp32s2.c
@@ -3,7 +3,6 @@
/***************************************************************************
* ESP32-S2 target for OpenOCD *
* Copyright (C) 2019 Espressif Systems Ltd. *
- * Author: Alexey Gerenkov <al...@es...> *
***************************************************************************/
#ifdef HAVE_CONFIG_H
diff --git a/src/target/espressif/esp32s2.h b/src/target/espressif/esp32s2.h
index adaabbf85..26fc7a198 100644
--- a/src/target/espressif/esp32s2.h
+++ b/src/target/espressif/esp32s2.h
@@ -3,7 +3,6 @@
/***************************************************************************
* ESP32-S2 target for OpenOCD *
* Copyright (C) 2019 Espressif Systems Ltd. *
- * Author: Alexey Gerenkov <al...@es...> *
***************************************************************************/
#ifndef OPENOCD_TARGET_ESP32S2_H
diff --git a/src/target/espressif/esp_xtensa.c b/src/target/espressif/esp_xtensa.c
index cc2888b0d..ce1601289 100644
--- a/src/target/espressif/esp_xtensa.c
+++ b/src/target/espressif/esp_xtensa.c
@@ -3,7 +3,6 @@
/***************************************************************************
* Espressif Xtensa target API for OpenOCD *
* Copyright (C) 2019 Espressif Systems Ltd. *
- * Author: Alexey Gerenkov <al...@es...> *
***************************************************************************/
#ifdef HAVE_CONFIG_H
diff --git a/src/target/espressif/esp_xtensa.h b/src/target/espressif/esp_xtensa.h
index e3507e31e..4bbbd756c 100644
--- a/src/target/espressif/esp_xtensa.h
+++ b/src/target/espressif/esp_xtensa.h
@@ -3,7 +3,6 @@
/***************************************************************************
* Generic ESP xtensa target implementation for OpenOCD *
* Copyright (C) 2019 Espressif Systems Ltd. *
- * Author: Alexey Gerenkov <al...@es...> *
***************************************************************************/
#ifndef OPENOCD_TARGET_ESP_XTENSA_H
diff --git a/src/target/espressif/esp_xtensa_smp.c b/src/target/espressif/esp_xtensa_smp.c
index 7c2c72331..606066247 100644
--- a/src/target/espressif/esp_xtensa_smp.c
+++ b/src/target/espressif/esp_xtensa_smp.c
@@ -3,7 +3,6 @@
/***************************************************************************
* ESP Xtensa SMP target API for OpenOCD *
* Copyright (C) 2020 Espressif Systems Ltd. Co *
- * Author: Alexey Gerenkov <al...@es...> *
***************************************************************************/
#ifdef HAVE_CONFIG_H
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index f04132e68..6f9d77e6c 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -5,9 +5,6 @@
* Copyright (C) 2016-2019 Espressif Systems Ltd. *
* Derived from esp108.c *
* Author: Angus Gratton gu...@pr... *
- * Author: Jeroen Domburg <je...@es...> *
- * Author: Alexey Gerenkov <al...@es...> *
- * Author: Andrey Gramakov <and...@es...> *
***************************************************************************/
#ifdef HAVE_CONFIG_H
diff --git a/src/target/xtensa/xtensa.h b/src/target/xtensa/xtensa.h
index 86b6a9c9b..d6000d80e 100644
--- a/src/target/xtensa/xtensa.h
+++ b/src/target/xtensa/xtensa.h
@@ -3,7 +3,6 @@
/***************************************************************************
* Generic Xtensa target *
* Copyright (C) 2019 Espressif Systems Ltd. *
- * Author: Alexey Gerenkov <al...@es...> *
***************************************************************************/
#ifndef OPENOCD_TARGET_XTENSA_H
diff --git a/src/target/xtensa/xtensa_debug_module.h b/src/target/xtensa/xtensa_debug_module.h
index 88f9eb2a7..189a6c97a 100644
--- a/src/target/xtensa/xtensa_debug_module.h
+++ b/src/target/xtensa/xtensa_debug_module.h
@@ -3,11 +3,8 @@
/***************************************************************************
* Xtensa debug module API *
* Copyright (C) 2019 Espressif Systems Ltd. *
- * <al...@es...> *
- * *
* Derived from original ESP8266 target. *
- * Copyright (C) 2015 by Angus Gratton *
- * gu...@pr... *
+ * Author: Angus Gratton gu...@pr... *
***************************************************************************/
#ifndef OPENOCD_TARGET_XTENSA_DEBUG_MODULE_H
diff --git a/src/target/xtensa/xtensa_regs.h b/src/target/xtensa/xtensa_regs.h
index 632400abf..7009a2a5f 100644
--- a/src/target/xtensa/xtensa_regs.h
+++ b/src/target/xtensa/xtensa_regs.h
@@ -4,8 +4,8 @@
* Generic Xtensa target API for OpenOCD *
* Copyright (C) 2016-2019 Espressif Systems Ltd. *
* Author: Angus Gratton gu...@pr... *
- * Author: Jeroen Domburg <je...@es...> *
***************************************************************************/
+
#ifndef OPENOCD_TARGET_XTENSA_REGS_H
#define OPENOCD_TARGET_XTENSA_REGS_H
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/esp_usb_jtag.c | 16 ++--------------
src/target/espressif/esp32.c | 2 --
src/target/espressif/esp32s2.c | 1 -
src/target/espressif/esp32s2.h | 1 -
src/target/espressif/esp_xtensa.c | 1 -
src/target/espressif/esp_xtensa.h | 1 -
src/target/espressif/esp_xtensa_smp.c | 1 -
src/target/xtensa/xtensa.c | 3 ---
src/target/xtensa/xtensa.h | 1 -
src/target/xtensa/xtensa_debug_module.h | 5 +----
src/target/xtensa/xtensa_regs.h | 2 +-
11 files changed, 4 insertions(+), 30 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-15 13:25:17
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 290eac04b93cd2f98e0a921e9dbf73b0822ae33b (commit)
via 903f2e92a143acf66fcaa82e628c1672fdd0da9f (commit)
from ace028262ba0bda0e921afb11e6eb7d87708d889 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 290eac04b93cd2f98e0a921e9dbf73b0822ae33b
Author: Steve Marple <ste...@go...>
Date: Tue Jun 21 23:06:25 2022 +0100
drivers/linuxgpiod: Migrate to adapter gpio commands
Use the new "adapter gpio" commands to configure the GPIOs used by the
linuxgpiod driver.
Adds support for drive mode and resistor pull options on all signals.
Change-Id: Ic90cb4f06db82435294228b6793330107a9f3606
Signed-off-by: Steve Marple <ste...@go...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7048
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 27a552286..9a5ab9a18 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -3401,87 +3401,14 @@ See @file{interface/beaglebone-swd-native.cfg} for a sample configuration file.
@deffn {Interface Driver} {linuxgpiod}
-Linux provides userspace access to GPIO through libgpiod since Linux kernel version v4.6.
-The driver emulates either JTAG or SWD transport through bitbanging.
-
-See @file{interface/dln-2-gpiod.cfg} for a sample config.
-
-@deffn {Config Command} {linuxgpiod gpiochip} @var{chip}
-Set the GPIO chip number for all GPIOs used by linuxgpiod. If GPIOs use
-different GPIO chips then the individual GPIO configuration commands (i.e., not
-@command{linuxgpiod jtag_nums} or @command{linuxgpiod swd_nums}) can be used to
-set chip numbers independently for each GPIO.
-@end deffn
-
-@deffn {Config Command} {linuxgpiod jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
-Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order). Must
-be specified to enable JTAG transport. These pins can also be specified
-individually.
-@end deffn
-
-@deffn {Config Command} {linuxgpiod tck_num} [@var{chip}] @var{tck}
-Set TCK GPIO number, and optionally TCK chip number. Must be specified to enable
-JTAG transport. Can also be specified using the configuration command
-@command{linuxgpiod jtag_nums}.
-@end deffn
-
-@deffn {Config Command} {linuxgpiod tms_num} [@var{chip}] @var{tms}
-Set TMS GPIO number, and optionally TMS chip number. Must be specified to enable
-JTAG transport. Can also be specified using the configuration command
-@command{linuxgpiod jtag_nums}.
-@end deffn
-
-@deffn {Config Command} {linuxgpiod tdo_num} [@var{chip}] @var{tdo}
-Set TDO GPIO number, and optionally TDO chip number. Must be specified to enable
-JTAG transport. Can also be specified using the configuration command
-@command{linuxgpiod jtag_nums}.
-@end deffn
-
-@deffn {Config Command} {linuxgpiod tdi_num} [@var{chip}] @var{tdi}
-Set TDI GPIO number, and optionally TDI chip number. Must be specified to enable
-JTAG transport. Can also be specified using the configuration command
-@command{linuxgpiod jtag_nums}.
-@end deffn
-
-@deffn {Config Command} {linuxgpiod trst_num} [@var{chip}] @var{trst}
-Set TRST GPIO number, and optionally TRST chip number. Must be specified to
-enable TRST.
-@end deffn
-
-@deffn {Config Command} {linuxgpiod swd_nums} @var{swclk} @var{swdio}
-Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
-specified to enable SWD transport. These pins can also be specified
-individually.
-@end deffn
-
-@deffn {Config Command} {linuxgpiod swclk_num} [@var{chip}] @var{swclk}
-Set SWCLK GPIO number, and optionally SWCLK chip number. Must be specified to
-enable SWD transport. Can also be specified using the configuration command
-@command{linuxgpiod swd_nums}.
-@end deffn
-
-@deffn {Config Command} {linuxgpiod swdio_num} [@var{chip}] @var{swdio}
-Set SWDIO GPIO number, and optionally SWDIO chip number. Must be specified to
-enable SWD transport. Can also be specified using the configuration command
-@command{linuxgpiod swd_nums}.
-@end deffn
-
-@deffn {Config Command} {linuxgpiod swdio_dir_num} [@var{chip}] @var{swdio_dir}
-Set SWDIO direction control GPIO number, and optionally SWDIO direction control
-chip number. If specified, this GPIO can be used to control the direction of an
-external buffer connected to the SWDIO GPIO (set=output mode, clear=input mode).
-@end deffn
-
-@deffn {Config Command} {linuxgpiod srst_num} [@var{chip}] @var{srst}
-Set SRST GPIO number, and optionally SRST chip number. Must be specified to
-enable SRST.
-@end deffn
-
-@deffn {Config Command} {linuxgpiod led_num} [@var{chip}] @var{led}
-Set activity LED GPIO number, and optionally activity LED chip number. If not
-specified an activity LED is not enabled.
-@end deffn
-
+Linux provides userspace access to GPIO through libgpiod since Linux kernel
+version v4.6. The driver emulates either JTAG or SWD transport through
+bitbanging. There are no driver-specific commands, all GPIO configuration is
+handled by the generic command @ref{adapter gpio, @command{adapter gpio}}. This
+driver supports the resistor pull options provided by the @command{adapter gpio}
+command but the underlying hardware may not be able to support them.
+
+See @file{interface/dln-2-gpiod.cfg} for a sample configuration file.
@end deffn
diff --git a/src/jtag/drivers/linuxgpiod.c b/src/jtag/drivers/linuxgpiod.c
index 0e96d82e5..e8e93a55b 100644
--- a/src/jtag/drivers/linuxgpiod.c
+++ b/src/jtag/drivers/linuxgpiod.c
@@ -14,67 +14,41 @@
#endif
#include <gpiod.h>
+#include <jtag/adapter.h>
#include <jtag/interface.h>
#include <transport/transport.h>
#include "bitbang.h"
-/* gpio numbers for each gpio. Negative values are invalid */
-static int tck_gpio = -1;
-static int tms_gpio = -1;
-static int tdi_gpio = -1;
-static int tdo_gpio = -1;
-static int trst_gpio = -1;
-static int srst_gpio = -1;
-static int swclk_gpio = -1;
-static int swdio_gpio = -1;
-static int swdio_dir_gpio = -1;
-static int led_gpio = -1;
-static int gpiochip = -1;
-static int tck_gpiochip = -1;
-static int tms_gpiochip = -1;
-static int tdi_gpiochip = -1;
-static int tdo_gpiochip = -1;
-static int trst_gpiochip = -1;
-static int srst_gpiochip = -1;
-static int swclk_gpiochip = -1;
-static int swdio_gpiochip = -1;
-static int swdio_dir_gpiochip = -1;
-static int led_gpiochip = -1;
-
-static struct gpiod_chip *gpiod_chip_tck;
-static struct gpiod_chip *gpiod_chip_tms;
-static struct gpiod_chip *gpiod_chip_tdi;
-static struct gpiod_chip *gpiod_chip_tdo;
-static struct gpiod_chip *gpiod_chip_trst;
-static struct gpiod_chip *gpiod_chip_srst;
-static struct gpiod_chip *gpiod_chip_swclk;
-static struct gpiod_chip *gpiod_chip_swdio;
-static struct gpiod_chip *gpiod_chip_swdio_dir;
-static struct gpiod_chip *gpiod_chip_led;
-
-static struct gpiod_line *gpiod_tck;
-static struct gpiod_line *gpiod_tms;
-static struct gpiod_line *gpiod_tdi;
-static struct gpiod_line *gpiod_tdo;
-static struct gpiod_line *gpiod_trst;
-static struct gpiod_line *gpiod_swclk;
-static struct gpiod_line *gpiod_swdio;
-static struct gpiod_line *gpiod_swdio_dir;
-static struct gpiod_line *gpiod_srst;
-static struct gpiod_line *gpiod_led;
+static struct gpiod_chip *gpiod_chip[ADAPTER_GPIO_IDX_NUM] = {};
+static struct gpiod_line *gpiod_line[ADAPTER_GPIO_IDX_NUM] = {};
static int last_swclk;
static int last_swdio;
static bool last_stored;
static bool swdio_input;
-static bool swdio_dir_is_active_high = true;
+
+static const struct adapter_gpio_config *adapter_gpio_config;
+
+/*
+ * Helper function to determine if gpio config is valid
+ *
+ * Assume here that there will be less than 10000 gpios per gpiochip, and less
+ * than 1000 gpiochips.
+ */
+static bool is_gpio_config_valid(enum adapter_gpio_config_index idx)
+{
+ return adapter_gpio_config[idx].chip_num >= 0
+ && adapter_gpio_config[idx].chip_num < 1000
+ && adapter_gpio_config[idx].gpio_num >= 0
+ && adapter_gpio_config[idx].gpio_num < 10000;
+}
/* Bitbang interface read of TDO */
static bb_value_t linuxgpiod_read(void)
{
int retval;
- retval = gpiod_line_get_value(gpiod_tdo);
+ retval = gpiod_line_get_value(gpiod_line[ADAPTER_GPIO_IDX_TDO]);
if (retval < 0) {
LOG_WARNING("reading tdo failed");
return 0;
@@ -107,20 +81,20 @@ static int linuxgpiod_write(int tck, int tms, int tdi)
}
if (tdi != last_tdi) {
- retval = gpiod_line_set_value(gpiod_tdi, tdi);
+ retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_TDI], tdi);
if (retval < 0)
LOG_WARNING("writing tdi failed");
}
if (tms != last_tms) {
- retval = gpiod_line_set_value(gpiod_tms, tms);
+ retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_TMS], tms);
if (retval < 0)
LOG_WARNING("writing tms failed");
}
/* write clk last */
if (tck != last_tck) {
- retval = gpiod_line_set_value(gpiod_tck, tck);
+ retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_TCK], tck);
if (retval < 0)
LOG_WARNING("writing tck failed");
}
@@ -136,7 +110,7 @@ static int linuxgpiod_swdio_read(void)
{
int retval;
- retval = gpiod_line_get_value(gpiod_swdio);
+ retval = gpiod_line_get_value(gpiod_line[ADAPTER_GPIO_IDX_SWDIO]);
if (retval < 0) {
LOG_WARNING("Fail read swdio");
return 0;
@@ -154,23 +128,23 @@ static void linuxgpiod_swdio_drive(bool is_output)
* https://stackoverflow.com/questions/58735140/
* this would change in future libgpiod
*/
- gpiod_line_release(gpiod_swdio);
+ gpiod_line_release(gpiod_line[ADAPTER_GPIO_IDX_SWDIO]);
if (is_output) {
- if (gpiod_swdio_dir) {
- retval = gpiod_line_set_value(gpiod_swdio_dir, swdio_dir_is_active_high ? 1 : 0);
+ if (gpiod_line[ADAPTER_GPIO_IDX_SWDIO_DIR]) {
+ retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_SWDIO_DIR], 1);
if (retval < 0)
LOG_WARNING("Fail set swdio_dir");
}
- retval = gpiod_line_request_output(gpiod_swdio, "OpenOCD", 1);
+ retval = gpiod_line_request_output(gpiod_line[ADAPTER_GPIO_IDX_SWDIO], "OpenOCD", 1);
if (retval < 0)
LOG_WARNING("Fail request_output line swdio");
} else {
- retval = gpiod_line_request_input(gpiod_swdio, "OpenOCD");
+ retval = gpiod_line_request_input(gpiod_line[ADAPTER_GPIO_IDX_SWDIO], "OpenOCD");
if (retval < 0)
LOG_WARNING("Fail request_input line swdio");
- if (gpiod_swdio_dir) {
- retval = gpiod_line_set_value(gpiod_swdio_dir, swdio_dir_is_active_high ? 0 : 1);
+ if (gpiod_line[ADAPTER_GPIO_IDX_SWDIO_DIR]) {
+ retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_SWDIO_DIR], 0);
if (retval < 0)
LOG_WARNING("Fail set swdio_dir");
}
@@ -186,7 +160,7 @@ static int linuxgpiod_swd_write(int swclk, int swdio)
if (!swdio_input) {
if (!last_stored || (swdio != last_swdio)) {
- retval = gpiod_line_set_value(gpiod_swdio, swdio);
+ retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_SWDIO], swdio);
if (retval < 0)
LOG_WARNING("Fail set swdio");
}
@@ -194,7 +168,7 @@ static int linuxgpiod_swd_write(int swclk, int swdio)
/* write swclk last */
if (!last_stored || (swclk != last_swclk)) {
- retval = gpiod_line_set_value(gpiod_swclk, swclk);
+ retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_SWCLK], swclk);
if (retval < 0)
LOG_WARNING("Fail set swclk");
}
@@ -210,10 +184,10 @@ static int linuxgpiod_blink(int on)
{
int retval;
- if (!gpiod_led)
+ if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_LED))
return ERROR_OK;
- retval = gpiod_line_set_value(gpiod_led, on);
+ retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_LED], on);
if (retval < 0)
LOG_WARNING("Fail set led");
return retval;
@@ -239,16 +213,18 @@ static int linuxgpiod_reset(int trst, int srst)
LOG_DEBUG("linuxgpiod_reset");
- /* assume active low */
- if (gpiod_srst) {
- retval1 = gpiod_line_set_value(gpiod_srst, srst ? 0 : 1);
+ /*
+ * active low behaviour handled by "adaptor gpio" command and
+ * GPIOD_LINE_REQUEST_FLAG_ACTIVE_LOW flag when requesting the line.
+ */
+ if (gpiod_line[ADAPTER_GPIO_IDX_SRST]) {
+ retval1 = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_SRST], srst);
if (retval1 < 0)
LOG_WARNING("set srst value failed");
}
- /* assume active low */
- if (gpiod_trst) {
- retval2 = gpiod_line_set_value(gpiod_trst, trst ? 0 : 1);
+ if (gpiod_line[ADAPTER_GPIO_IDX_TRST]) {
+ retval2 = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_TRST], trst);
if (retval2 < 0)
LOG_WARNING("set trst value failed");
}
@@ -256,109 +232,134 @@ static int linuxgpiod_reset(int trst, int srst)
return ((retval1 < 0) || (retval2 < 0)) ? ERROR_FAIL : ERROR_OK;
}
-/*
- * Helper function to determine if gpio number is valid
- *
- * Assume here that there will be less than 10000 gpios per gpiochip
- */
-static bool is_gpio_valid(int gpio)
-{
- return gpio >= 0 && gpio < 10000;
-}
-
static bool linuxgpiod_jtag_mode_possible(void)
{
- if (!is_gpio_valid(tck_gpio))
+ if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TCK))
return false;
- if (!is_gpio_valid(tms_gpio))
+ if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TMS))
return false;
- if (!is_gpio_valid(tdi_gpio))
+ if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TDI))
return false;
- if (!is_gpio_valid(tdo_gpio))
+ if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TDO))
return false;
return true;
}
static bool linuxgpiod_swd_mode_possible(void)
{
- if (!is_gpio_valid(swclk_gpio))
+ if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_SWCLK))
return false;
- if (!is_gpio_valid(swdio_gpio))
+ if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_SWDIO))
return false;
return true;
}
-static inline void helper_release(struct gpiod_line *line, struct gpiod_chip *chip)
+static inline void helper_release(enum adapter_gpio_config_index idx)
{
- if (line)
- gpiod_line_release(line);
- if (chip)
- gpiod_chip_close(chip);
+ if (gpiod_line[idx]) {
+ gpiod_line_release(gpiod_line[idx]);
+ gpiod_line[idx] = NULL;
+ }
+ if (gpiod_chip[idx]) {
+ gpiod_chip_close(gpiod_chip[idx]);
+ gpiod_chip[idx] = NULL;
+ }
}
static int linuxgpiod_quit(void)
{
- helper_release(gpiod_led, gpiod_chip_led);
- helper_release(gpiod_srst, gpiod_chip_srst);
- helper_release(gpiod_swdio, gpiod_chip_swdio);
- helper_release(gpiod_swdio_dir, gpiod_chip_swdio_dir);
- helper_release(gpiod_swclk, gpiod_chip_swclk);
- helper_release(gpiod_trst, gpiod_chip_trst);
- helper_release(gpiod_tms, gpiod_chip_tms);
- helper_release(gpiod_tck, gpiod_chip_tck);
- helper_release(gpiod_tdi, gpiod_chip_tdi);
- helper_release(gpiod_tdo, gpiod_chip_tdo);
+ LOG_DEBUG("linuxgpiod_quit");
+ for (int i = 0; i < ADAPTER_GPIO_IDX_NUM; ++i)
+ helper_release(i);
return ERROR_OK;
}
-static struct gpiod_line *helper_get_line(const char *label,
- struct gpiod_chip *gpiod_chip, unsigned int offset,
- int val, int dir, int flags)
+int helper_get_line(enum adapter_gpio_config_index idx)
{
- struct gpiod_line *line;
- int retval;
+ if (!is_gpio_config_valid(idx))
+ return ERROR_OK;
+
+ int dir = GPIOD_LINE_REQUEST_DIRECTION_INPUT, flags = 0, val = 0, retval;
+
+ gpiod_chip[idx] = gpiod_chip_open_by_number(adapter_gpio_config[idx].chip_num);
+ if (!gpiod_chip[idx]) {
+ LOG_ERROR("Cannot open LinuxGPIOD chip %d for %s", adapter_gpio_config[idx].chip_num,
+ adapter_gpio_get_name(idx));
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ gpiod_line[idx] = gpiod_chip_get_line(gpiod_chip[idx], adapter_gpio_config[idx].gpio_num);
+ if (!gpiod_line[idx]) {
+ LOG_ERROR("Error get line %s", adapter_gpio_get_name(idx));
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ switch (adapter_gpio_config[idx].init_state) {
+ case ADAPTER_GPIO_INIT_STATE_INPUT:
+ dir = GPIOD_LINE_REQUEST_DIRECTION_INPUT;
+ break;
+ case ADAPTER_GPIO_INIT_STATE_INACTIVE:
+ dir = GPIOD_LINE_REQUEST_DIRECTION_OUTPUT;
+ val = 0;
+ break;
+ case ADAPTER_GPIO_INIT_STATE_ACTIVE:
+ dir = GPIOD_LINE_REQUEST_DIRECTION_OUTPUT;
+ val = 1;
+ break;
+ }
+
+ switch (adapter_gpio_config[idx].drive) {
+ case ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL:
+ break;
+ case ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN:
+ flags |= GPIOD_LINE_REQUEST_FLAG_OPEN_DRAIN;
+ break;
+ case ADAPTER_GPIO_DRIVE_MODE_OPEN_SOURCE:
+ flags |= GPIOD_LINE_REQUEST_FLAG_OPEN_SOURCE;
+ break;
+ }
- line = gpiod_chip_get_line(gpiod_chip, offset);
- if (!line) {
- LOG_ERROR("Error get line %s", label);
- return NULL;
+ switch (adapter_gpio_config[idx].pull) {
+ case ADAPTER_GPIO_PULL_NONE:
+#ifdef GPIOD_LINE_REQUEST_FLAG_BIAS_DISABLE
+ flags |= GPIOD_LINE_REQUEST_FLAG_BIAS_DISABLE;
+#endif
+ break;
+ case ADAPTER_GPIO_PULL_UP:
+#ifdef GPIOD_LINE_REQUEST_FLAG_BIAS_PULL_UP
+ flags |= GPIOD_LINE_REQUEST_FLAG_BIAS_PULL_UP;
+#else
+ LOG_WARNING("linuxgpiod: ignoring request for pull-up on %s: not supported by gpiod v%s",
+ adapter_gpio_get_name(idx), gpiod_version_string());
+#endif
+ break;
+ case ADAPTER_GPIO_PULL_DOWN:
+#ifdef GPIOD_LINE_REQUEST_FLAG_BIAS_PULL_DOWN
+ flags |= GPIOD_LINE_REQUEST_FLAG_BIAS_PULL_DOWN;
+#else
+ LOG_WARNING("linuxgpiod: ignoring request for pull-down on %s: not supported by gpiod v%s",
+ adapter_gpio_get_name(idx), gpiod_version_string());
+#endif
+ break;
}
+ if (adapter_gpio_config[idx].active_low)
+ flags |= GPIOD_LINE_REQUEST_FLAG_ACTIVE_LOW;
+
struct gpiod_line_request_config config = {
.consumer = "OpenOCD",
.request_type = dir,
.flags = flags,
};
- retval = gpiod_line_request(line, &config, val);
+ retval = gpiod_line_request(gpiod_line[idx], &config, val);
if (retval < 0) {
- LOG_ERROR("Error requesting gpio line %s", label);
- return NULL;
+ LOG_ERROR("Error requesting gpio line %s", adapter_gpio_get_name(idx));
+ return ERROR_JTAG_INIT_FAILED;
}
- return line;
-}
-
-static struct gpiod_line *helper_get_input_line(const char *label,
- struct gpiod_chip *gpiod_chip, unsigned int offset)
-{
- return helper_get_line(label, gpiod_chip, offset, 0,
- GPIOD_LINE_REQUEST_DIRECTION_INPUT, 0);
-}
-
-static struct gpiod_line *helper_get_output_line(const char *label,
- struct gpiod_chip *gpiod_chip, unsigned int offset, int val)
-{
- return helper_get_line(label, gpiod_chip, offset, val,
- GPIOD_LINE_REQUEST_DIRECTION_OUTPUT, 0);
-}
-
-static struct gpiod_line *helper_get_open_drain_output_line(const char *label,
- struct gpiod_chip *gpiod_chip, unsigned int offset, int val)
-{
- return helper_get_line(label, gpiod_chip, offset, val,
- GPIOD_LINE_REQUEST_DIRECTION_OUTPUT, GPIOD_LINE_REQUEST_FLAG_OPEN_DRAIN);
+ return ERROR_OK;
}
static int linuxgpiod_init(void)
@@ -366,11 +367,11 @@ static int linuxgpiod_init(void)
LOG_INFO("Linux GPIOD JTAG/SWD bitbang driver");
bitbang_interface = &linuxgpiod_bitbang;
+ adapter_gpio_config = adapter_gpio_get_config();
/*
- * Configure TDO as an input, and TDI, TCK, TMS, TRST, SRST
- * as outputs. Drive TDI and TCK low, and TMS/TRST/SRST high.
- * For SWD, SWCLK and SWDIO are configures as output high.
+ * Configure JTAG/SWD signals. Default directions and initial states are handled
+ * by adapter.c and "adapter gpio" command.
*/
if (transport_is_jtag()) {
@@ -379,129 +380,44 @@ static int linuxgpiod_init(void)
goto out_error;
}
- gpiod_chip_tdo = gpiod_chip_open_by_number(tdo_gpiochip);
- if (!gpiod_chip_tdo) {
- LOG_ERROR("Cannot open LinuxGPIOD tdo_gpiochip %d", tdo_gpiochip);
- goto out_error;
- }
- gpiod_chip_tdi = gpiod_chip_open_by_number(tdi_gpiochip);
- if (!gpiod_chip_tdi) {
- LOG_ERROR("Cannot open LinuxGPIOD tdi_gpiochip %d", tdi_gpiochip);
- goto out_error;
- }
- gpiod_chip_tck = gpiod_chip_open_by_number(tck_gpiochip);
- if (!gpiod_chip_tck) {
- LOG_ERROR("Cannot open LinuxGPIOD tck_gpiochip %d", tck_gpiochip);
- goto out_error;
- }
- gpiod_chip_tms = gpiod_chip_open_by_number(tms_gpiochip);
- if (!gpiod_chip_tms) {
- LOG_ERROR("Cannot open LinuxGPIOD tms_gpiochip %d", tms_gpiochip);
- goto out_error;
- }
-
- gpiod_tdo = helper_get_input_line("tdo", gpiod_chip_tdo, tdo_gpio);
- if (!gpiod_tdo)
- goto out_error;
-
- gpiod_tdi = helper_get_output_line("tdi", gpiod_chip_tdi, tdi_gpio, 0);
- if (!gpiod_tdi)
- goto out_error;
-
- gpiod_tck = helper_get_output_line("tck", gpiod_chip_tck, tck_gpio, 0);
- if (!gpiod_tck)
- goto out_error;
-
- gpiod_tms = helper_get_output_line("tms", gpiod_chip_tms, tms_gpio, 1);
- if (!gpiod_tms)
- goto out_error;
-
- if (is_gpio_valid(trst_gpio)) {
- gpiod_chip_trst = gpiod_chip_open_by_number(trst_gpiochip);
- if (!gpiod_chip_trst) {
- LOG_ERROR("Cannot open LinuxGPIOD trst_gpiochip %d", trst_gpiochip);
+ if (helper_get_line(ADAPTER_GPIO_IDX_TDO) != ERROR_OK ||
+ helper_get_line(ADAPTER_GPIO_IDX_TDI) != ERROR_OK ||
+ helper_get_line(ADAPTER_GPIO_IDX_TCK) != ERROR_OK ||
+ helper_get_line(ADAPTER_GPIO_IDX_TMS) != ERROR_OK ||
+ helper_get_line(ADAPTER_GPIO_IDX_TRST) != ERROR_OK)
goto out_error;
- }
-
- if (jtag_get_reset_config() & RESET_TRST_OPEN_DRAIN)
- gpiod_trst = helper_get_open_drain_output_line("trst", gpiod_chip_trst, trst_gpio, 1);
- else
- gpiod_trst = helper_get_output_line("trst", gpiod_chip_trst, trst_gpio, 1);
-
- if (!gpiod_trst)
- goto out_error;
- }
}
if (transport_is_swd()) {
+ int retval1, retval2;
if (!linuxgpiod_swd_mode_possible()) {
LOG_ERROR("Require swclk and swdio gpio for SWD mode");
goto out_error;
}
- gpiod_chip_swclk = gpiod_chip_open_by_number(swclk_gpiochip);
- if (!gpiod_chip_swclk) {
- LOG_ERROR("Cannot open LinuxGPIOD swclk_gpiochip %d", swclk_gpiochip);
- goto out_error;
+ /*
+ * swdio and its buffer should be initialized in the order that prevents
+ * two outputs from being connected together. This will occur if the
+ * swdio GPIO is configured as an output while the external buffer is
+ * configured to send the swdio signal from the target to the GPIO.
+ */
+ if (adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].init_state == ADAPTER_GPIO_INIT_STATE_INPUT) {
+ retval1 = helper_get_line(ADAPTER_GPIO_IDX_SWDIO);
+ retval2 = helper_get_line(ADAPTER_GPIO_IDX_SWDIO_DIR);
+ } else {
+ retval1 = helper_get_line(ADAPTER_GPIO_IDX_SWDIO_DIR);
+ retval2 = helper_get_line(ADAPTER_GPIO_IDX_SWDIO);
}
- gpiod_chip_swdio = gpiod_chip_open_by_number(swdio_gpiochip);
- if (!gpiod_chip_swdio) {
- LOG_ERROR("Cannot open LinuxGPIOD swdio_gpiochip %d", swdio_gpiochip);
+ if (retval1 != ERROR_OK || retval2 != ERROR_OK)
goto out_error;
- }
-
- if (is_gpio_valid(swdio_dir_gpio)) {
- gpiod_chip_swdio_dir = gpiod_chip_open_by_number(swdio_dir_gpiochip);
- if (!gpiod_chip_swdio_dir) {
- LOG_ERROR("Cannot open LinuxGPIOD swdio_dir_gpiochip %d", swdio_dir_gpiochip);
- goto out_error;
- }
- }
- gpiod_swclk = helper_get_output_line("swclk", gpiod_chip_swclk, swclk_gpio, 1);
- if (!gpiod_swclk)
- goto out_error;
-
- /* Set buffer direction before making SWDIO an output */
- if (is_gpio_valid(swdio_dir_gpio)) {
- gpiod_swdio_dir = helper_get_output_line("swdio_dir", gpiod_chip_swdio_dir, swdio_dir_gpio,
- swdio_dir_is_active_high ? 1 : 0);
- if (!gpiod_swdio_dir)
- goto out_error;
- }
-
- gpiod_swdio = helper_get_output_line("swdio", gpiod_chip_swdio, swdio_gpio, 1);
- if (!gpiod_swdio)
+ if (helper_get_line(ADAPTER_GPIO_IDX_SWCLK) != ERROR_OK)
goto out_error;
}
- if (is_gpio_valid(srst_gpio)) {
- gpiod_chip_srst = gpiod_chip_open_by_number(srst_gpiochip);
- if (!gpiod_chip_srst) {
- LOG_ERROR("Cannot open LinuxGPIOD srst_gpiochip %d", srst_gpiochip);
- goto out_error;
- }
-
- if (jtag_get_reset_config() & RESET_SRST_PUSH_PULL)
- gpiod_srst = helper_get_output_line("srst", gpiod_chip_srst, srst_gpio, 1);
- else
- gpiod_srst = helper_get_open_drain_output_line("srst", gpiod_chip_srst, srst_gpio, 1);
-
- if (!gpiod_srst)
- goto out_error;
- }
-
- if (is_gpio_valid(led_gpio)) {
- gpiod_chip_led = gpiod_chip_open_by_number(led_gpiochip);
- if (!gpiod_chip_led) {
- LOG_ERROR("Cannot open LinuxGPIOD led_gpiochip %d", led_gpiochip);
- goto out_error;
- }
-
- gpiod_led = helper_get_output_line("led", gpiod_chip_led, led_gpio, 0);
- if (!gpiod_led)
+ if (helper_get_line(ADAPTER_GPIO_IDX_SRST) != ERROR_OK ||
+ helper_get_line(ADAPTER_GPIO_IDX_LED) != ERROR_OK)
goto out_error;
- }
return ERROR_OK;
@@ -511,241 +427,6 @@ out_error:
return ERROR_JTAG_INIT_FAILED;
}
-COMMAND_HELPER(linuxgpiod_helper_gpionum, const char *name, int *chip, int *line)
-{
- int i = 0;
- if (CMD_ARGC > 2)
- return ERROR_COMMAND_SYNTAX_ERROR;
- if (CMD_ARGC == 2) {
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], *chip);
- i = 1;
- }
- if (CMD_ARGC > 0)
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[i], *line);
- command_print(CMD, "LinuxGPIOD %s: chip = %d, num = %d", name, *chip, *line);
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionums)
-{
- if (CMD_ARGC == 4) {
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tms_gpio);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], tdi_gpio);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], tdo_gpio);
- } else if (CMD_ARGC != 0) {
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
-
- command_print(CMD,
- "LinuxGPIOD nums: tck = %d, tms = %d, tdi = %d, tdo = %d",
- tck_gpio, tms_gpio, tdi_gpio, tdo_gpio);
-
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_tck)
-{
- return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "tck", &tck_gpiochip,
- &tck_gpio);
-}
-
-COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_tms)
-{
- return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "tms", &tms_gpiochip,
- &tms_gpio);
-}
-
-COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_tdo)
-{
- return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "tdo", &tdo_gpiochip,
- &tdo_gpio);
-}
-
-COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_tdi)
-{
- return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "tdi", &tdi_gpiochip,
- &tdi_gpio);
-}
-
-COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_srst)
-{
- return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "srst", &srst_gpiochip,
- &srst_gpio);
-}
-
-COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_trst)
-{
- return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "trst", &trst_gpiochip,
- &trst_gpio);
-}
-
-COMMAND_HANDLER(linuxgpiod_handle_swd_gpionums)
-{
- if (CMD_ARGC == 2) {
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swclk_gpio);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], swdio_gpio);
- } else if (CMD_ARGC != 0) {
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
-
- command_print(CMD,
- "LinuxGPIOD nums: swclk = %d, swdio = %d",
- swclk_gpio, swdio_gpio);
-
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(linuxgpiod_handle_swd_gpionum_swclk)
-{
- return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "swclk", &swclk_gpiochip,
- &swclk_gpio);
-}
-
-COMMAND_HANDLER(linuxgpiod_handle_swd_gpionum_swdio)
-{
- return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "swdio", &swdio_gpiochip,
- &swdio_gpio);
-}
-
-COMMAND_HANDLER(linuxgpiod_handle_swd_gpionum_swdio_dir)
-{
- return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "swdio_dir", &swdio_dir_gpiochip,
- &swdio_dir_gpio);
-}
-
-COMMAND_HANDLER(linuxgpiod_handle_gpionum_led)
-{
- return CALL_COMMAND_HANDLER(linuxgpiod_helper_gpionum, "led", &led_gpiochip,
- &led_gpio);
-}
-
-COMMAND_HANDLER(linuxgpiod_handle_gpiochip)
-{
- if (CMD_ARGC == 1) {
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], gpiochip);
- tck_gpiochip = gpiochip;
- tms_gpiochip = gpiochip;
- tdi_gpiochip = gpiochip;
- tdo_gpiochip = gpiochip;
- trst_gpiochip = gpiochip;
- srst_gpiochip = gpiochip;
- swclk_gpiochip = gpiochip;
- swdio_gpiochip = gpiochip;
- swdio_dir_gpiochip = gpiochip;
- led_gpiochip = gpiochip;
- }
-
- command_print(CMD, "LinuxGPIOD gpiochip = %d", gpiochip);
- return ERROR_OK;
-}
-
-static const struct command_registration linuxgpiod_subcommand_handlers[] = {
- {
- .name = "jtag_nums",
- .handler = linuxgpiod_handle_jtag_gpionums,
- .mode = COMMAND_CONFIG,
- .help = "gpio numbers for tck, tms, tdi, tdo. (in that order)",
- .usage = "tck tms tdi tdo",
- },
- {
- .name = "tck_num",
- .handler = linuxgpiod_handle_jtag_gpionum_tck,
- .mode = COMMAND_CONFIG,
- .help = "gpio chip number (optional) and gpio number for tck.",
- .usage = "[chip] tck",
- },
- {
- .name = "tms_num",
- .handler = linuxgpiod_handle_jtag_gpionum_tms,
- .mode = COMMAND_CONFIG,
- .help = "gpio chip number (optional) and gpio number for tms.",
- .usage = "[chip] tms",
- },
- {
- .name = "tdo_num",
- .handler = linuxgpiod_handle_jtag_gpionum_tdo,
- .mode = COMMAND_CONFIG,
- .help = "gpio chip number (optional) and gpio number for tdo.",
- .usage = "[chip] tdo",
- },
- {
- .name = "tdi_num",
- .handler = linuxgpiod_handle_jtag_gpionum_tdi,
- .mode = COMMAND_CONFIG,
- .help = "gpio chip number (optional) and gpio number for tdi.",
- .usage = "[chip] tdi",
- },
- {
- .name = "srst_num",
- .handler = linuxgpiod_handle_jtag_gpionum_srst,
- .mode = COMMAND_CONFIG,
- .help = "gpio chip number (optional) and gpio number for srst.",
- .usage = "[chip] srst",
- },
- {
- .name = "trst_num",
- .handler = linuxgpiod_handle_jtag_gpionum_trst,
- .mode = COMMAND_CONFIG,
- .help = "gpio chip number (optional) and gpio number for trst.",
- .usage = "[chip] trst",
- },
- {
- .name = "swd_nums",
- .handler = linuxgpiod_handle_swd_gpionums,
- .mode = COMMAND_CONFIG,
- .help = "gpio numbers for swclk, swdio. (in that order)",
- .usage = "swclk swdio",
- },
- {
- .name = "swclk_num",
- .handler = linuxgpiod_handle_swd_gpionum_swclk,
- .mode = COMMAND_CONFIG,
- .help = "gpio chip number (optional) and gpio number for swclk.",
- .usage = "[chip] swclk",
- },
- {
- .name = "swdio_num",
- .handler = linuxgpiod_handle_swd_gpionum_swdio,
- .mode = COMMAND_CONFIG,
- .help = "gpio chip number (optional) and gpio number for swdio.",
- .usage = "[chip] swdio",
- },
- {
- .name = "swdio_dir_num",
- .handler = linuxgpiod_handle_swd_gpionum_swdio_dir,
- .mode = COMMAND_CONFIG,
- .help = "gpio chip number (optional) and gpio number for swdio_dir.",
- .usage = "[chip] swdio_dir",
- },
- {
- .name = "led_num",
- .handler = linuxgpiod_handle_gpionum_led,
- .mode = COMMAND_CONFIG,
- .help = "gpio chip number (optional) and gpio number for LED.",
- .usage = "[chip] led",
- },
- {
- .name = "gpiochip",
- .handler = linuxgpiod_handle_gpiochip,
- .mode = COMMAND_CONFIG,
- .help = "number of the gpiochip.",
- .usage = "gpiochip",
- },
- COMMAND_REGISTRATION_DONE
-};
-
-static const struct command_registration linuxgpiod_command_handlers[] = {
- {
- .name = "linuxgpiod",
- .mode = COMMAND_ANY,
- .help = "perform linuxgpiod management",
- .chain = linuxgpiod_subcommand_handlers,
- .usage = "",
- },
- COMMAND_REGISTRATION_DONE
-};
-
static const char *const linuxgpiod_transport[] = { "swd", "jtag", NULL };
static struct jtag_interface linuxgpiod_interface = {
@@ -756,7 +437,6 @@ static struct jtag_interface linuxgpiod_interface = {
struct adapter_driver linuxgpiod_adapter_driver = {
.name = "linuxgpiod",
.transports = linuxgpiod_transport,
- .commands = linuxgpiod_command_handlers,
.init = linuxgpiod_init,
.quit = linuxgpiod_quit,
diff --git a/src/jtag/startup.tcl b/src/jtag/startup.tcl
index a72775e66..1a638a30f 100644
--- a/src/jtag/startup.tcl
+++ b/src/jtag/startup.tcl
@@ -535,74 +535,72 @@ proc bcm2835gpio_peripheral_base args {
lappend _telnet_autocomplete_skip linuxgpiod_jtag_nums
proc linuxgpiod_jtag_nums args {
- echo "DEPRECATED! use 'linuxgpiod jtag_nums' not 'linuxgpiod_jtag_nums'"
- eval linuxgpiod jtag_nums $args
+ eval adapter_gpio_jtag_nums $args
}
lappend _telnet_autocomplete_skip linuxgpiod_tck_num
proc linuxgpiod_tck_num args {
- echo "DEPRECATED! use 'linuxgpiod tck_num' not 'linuxgpiod_tck_num'"
- eval linuxgpiod tck_num $args
+ eval adapter_gpio_helper tck $args
}
lappend _telnet_autocomplete_skip linuxgpiod_tms_num
proc linuxgpiod_tms_num args {
- echo "DEPRECATED! use 'linuxgpiod tms_num' not 'linuxgpiod_tms_num'"
- eval linuxgpiod tms_num $args
+ eval adapter_gpio_helper tms $args
}
lappend _telnet_autocomplete_skip linuxgpiod_tdo_num
proc linuxgpiod_tdo_num args {
- echo "DEPRECATED! use 'linuxgpiod tdo_num' not 'linuxgpiod_tdo_num'"
- eval linuxgpiod tdo_num $args
+ eval adapter_gpio_helper tdo $args
}
lappend _telnet_autocomplete_skip linuxgpiod_tdi_num
proc linuxgpiod_tdi_num args {
- echo "DEPRECATED! use 'linuxgpiod tdi_num' not 'linuxgpiod_tdi_num'"
- eval linuxgpiod tdi_num $args
+ eval adapter_gpio_helper tdi $args
}
lappend _telnet_autocomplete_skip linuxgpiod_srst_num
proc linuxgpiod_srst_num args {
- echo "DEPRECATED! use 'linuxgpiod srst_num' not 'linuxgpiod_srst_num'"
- eval linuxgpiod srst_num $args
+ eval adapter_gpio_helper srst $args
}
lappend _telnet_autocomplete_skip linuxgpiod_trst_num
proc linuxgpiod_trst_num args {
- echo "DEPRECATED! use 'linuxgpiod trst_num' not 'linuxgpiod_trst_num'"
- eval linuxgpiod trst_num $args
+ eval adapter_gpio_helper trst $args
}
lappend _telnet_autocomplete_skip linuxgpiod_swd_nums
proc linuxgpiod_swd_nums args {
- echo "DEPRECATED! use 'linuxgpiod swd_nums' not 'linuxgpiod_swd_nums'"
- eval linuxgpiod swd_nums $args
+ eval adapter_gpio_swd_nums $args
}
lappend _telnet_autocomplete_skip linuxgpiod_swclk_num
proc linuxgpiod_swclk_num args {
- echo "DEPRECATED! use 'linuxgpiod swclk_num' not 'linuxgpiod_swclk_num'"
- eval linuxgpiod swclk_num $args
+ eval adapter_gpio_helper swclk $args
}
lappend _telnet_autocomplete_skip linuxgpiod_swdio_num
proc linuxgpiod_swdio_num args {
- echo "DEPRECATED! use 'linuxgpiod swdio_num' not 'linuxgpiod_swdio_num'"
- eval linuxgpiod swdio_num $args
+ eval adapter_gpio_helper swdio $args
}
lappend _telnet_autocomplete_skip linuxgpiod_led_num
proc linuxgpiod_led_num args {
- echo "DEPRECATED! use 'linuxgpiod led_num' not 'linuxgpiod_led_num'"
- eval linuxgpiod led_num $args
+ eval adapter_gpio_helper led $args
}
lappend _telnet_autocomplete_skip linuxgpiod_gpiochip
proc linuxgpiod_gpiochip args {
- echo "DEPRECATED! use 'linuxgpiod gpiochip' not 'linuxgpiod_gpiochip'"
- eval linuxgpiod gpiochip $args
+ echo "DEPRECATED! use 'adapter <signal_name> -chip' not 'linuxgpiod_gpiochip'"
+ switch [llength $args] {
+ 0 { }
+ 1 {
+ foreach sig_name {tck tms tdi tdo trst srst swclk swdio swdio_dir led} {
+ eval adapter gpio $sig_name -chip $args
+ }
+ }
+ default {return -code 1 -level 1 "linuxgpiod_gpiochip: syntax error"}
+ }
+ eval adapter gpio
}
lappend _telnet_autocomplete_skip sysfsgpio_jtag_nums
@@ -863,6 +861,87 @@ proc "xds110 serial" {args} {
eval adapter serial $args
}
+lappend _telnet_autocomplete_skip linuxgpiod
+# linuxgpiod command completely removed, this is required for the sub-commands to work
+proc linuxgpiod {subcommand args} {
+ eval {"linuxgpiod $subcommand"} $args
+}
+
+lappend _telnet_autocomplete_skip "linuxgpiod tck_num"
+proc "linuxgpiod tck_num" {args} {
+ eval adapter_gpio_helper tck $args
+}
+
+lappend _telnet_autocomplete_skip "linuxgpiod tms_num"
+proc "linuxgpiod tms_num" {args} {
+ eval adapter_gpio_helper tms $args
+}
+
+lappend _telnet_autocomplete_skip "linuxgpiod tdi_num"
+proc "linuxgpiod tdi_num" {args} {
+ eval adapter_gpio_helper tdi $args
+}
+
+lappend _telnet_autocomplete_skip "linuxgpiod tdo_num"
+proc "linuxgpiod tdo_num" {args} {
+ eval adapter_gpio_helper tdo $args
+}
+
+lappend _telnet_autocomplete_skip "linuxgpiod trst_num"
+proc "linuxgpiod trst_num" {args} {
+ eval adapter_gpio_helper trst $args
+}
+
+lappend _telnet_autocomplete_skip "linuxgpiod srst_num"
+proc "linuxgpiod srst_num" {args} {
+ eval adapter_gpio_helper srst $args
+}
+
+lappend _telnet_autocomplete_skip "linuxgpiod swclk_num"
+proc "linuxgpiod swclk_num" {args} {
+ eval adapter_gpio_helper swclk $args
+}
+
+lappend _telnet_autocomplete_skip "linuxgpiod swdio_num"
+proc "linuxgpiod swdio_num" {args} {
+ eval adapter_gpio_helper swdio $args
+}
+
+lappend _telnet_autocomplete_skip "linuxgpiod swdio_dir_num"
+proc "linuxgpiod swdio_dir_num" {args} {
+ eval adapter_gpio_helper swdio_dir $args
+}
+
+lappend _telnet_autocomplete_skip "linuxgpiod led_num"
+proc "linuxgpiod led_num" {args} {
+ eval adapter_gpio_helper led $args
+}
+
+lappend _telnet_autocomplete_skip "linuxgpiod gpiochip"
+proc "linuxgpiod gpiochip" {num} {
+ echo "DEPRECATED! use 'adapter <signal_name> -chip' not 'linuxgpiod gpiochip'"
+ foreach sig_name {tck tms tdi tdo trst srst swclk swdio swdio_dir led} {
+ eval adapter gpio $sig_name -chip $num
+ }
+ eval adapter gpio
+}
+
+lappend _telnet_autocomplete_skip "linuxgpiod jtag_nums"
+proc "linuxgpiod jtag_nums" {tck_num tms_num tdi_num tdo_num} {
+ echo "DEPRECATED! use 'adapter gpio tck; adapter gpio tms; adapter gpio tdi; adapter gpio tdo' not 'linuxgpiod jtag_nums'"
+ eval adapter gpio tck $tck_num
+ eval adapter gpio tms $tms_num
+ eval adapter gpio tdi $tdi_num
+ eval adapter gpio tdo $tdo_num
+}
+
+lappend _telnet_autocomplete_skip "linuxgpiod swd_nums"
+proc "linuxgpiod swd_nums" {swclk swdio} {
+ echo "DEPRECATED! use 'adapter gpio swclk; adapter gpio swdio' not 'linuxgpiod jtag_nums'"
+ eval adapter gpio swclk $swclk
+ eval adapter gpio swdio $swdio
+}
+
lappend _telnet_autocomplete_skip "am335xgpio jtag_nums"
proc "am335xgpio jtag_nums" {tck_num tms_num tdi_num tdo_num} {
echo "DEPRECATED! use 'adapter gpio tck; adapter gpio tms; adapter gpio tdi; adapter gpio tdo' not 'am335xgpio jtag_nums'"
diff --git a/tcl/interface/dln-2-gpiod.cfg b/tcl/interface/dln-2-gpiod.cfg
index cd6061fd9..c9e33881f 100644
--- a/tcl/interface/dln-2-gpiod.cfg
+++ b/tcl/interface/dln-2-gpiod.cfg
@@ -17,11 +17,14 @@
adapter driver linuxgpiod
-linuxgpiod gpiochip 0
-linuxgpiod jtag_nums 2 3 4 1
-linuxgpiod trst_num 5
-linuxgpiod swd_nums 2 3
-linuxgpiod srst_num 0
-linuxgpiod led_num 6
+adapter gpio srst 0 -chip 0
+adapter gpio tdo 1 -chip 0
+adapter gpio tck 2 -chip 0
+adapter gpio swclk 2 -chip 0
+adapter gpio tms 3 -chip 0
+adapter gpio swdio 3 -chip 0
+adapter gpio tdi 4 -chip 0
+adapter gpio trst 5 -chip 0
+adapter gpio led 6 -chip 0
reset_config trst_and_srst separate srst_push_pull
diff --git a/testing/test-linuxgpiod-deprecated-commands.cfg b/testing/test-linuxgpiod-deprecated-commands.cfg
new file mode 100644
index 000000000..3d4f5cb4c
--- /dev/null
+++ b/testing/test-linuxgpiod-deprecated-commands.cfg
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# OpenOCD script to test that the deprecated "linuxgpiod *" and "linuxgpiod_*"
+# commands produce the expected results. Run this command as:
+# openocd -f <path>/test-linuxgpiod-deprecated-commands.cfg
+
+# Raise an error if the "actual" value does not match the "expected" value. Trim
+# whitespace (including newlines) from strings before comparing.
+proc expected_value {expected actual} {
+ if {[string trim $expected] ne [string trim $actual]} {
+ error [puts "ERROR: '${actual}' != '${expected}'"]
+ }
+}
+
+adapter driver linuxgpiod
+puts "Driver is '[adapter name]'"
+expected_value "linuxgpiod" [adapter name]
+echo [adapter gpio]
+
+#####################################
+# Test the "linuxgpiod *" commands
+
+# Change the GPIO chip for all signals. Don't check directly here, do so when
+# each signal command is tested.
+linuxgpiod gpiochip 0
+
+linuxgpiod jtag_nums 1 2 3 4
+expected_value "adapter gpio tck (output): num 1, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tck]
+expected_value "adapter gpio tms (output): num 2, chip 0, active-high, push-pull, pull-none, init-state active" [eval adapter gpio tms]
+expected_value "adapter gpio tdi (output): num 3, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tdi]
+expected_value "adapter gpio tdo (input): num 4, chip 0, active-high, pull-none, init-state input" [eval adapter gpio tdo]
+
+linuxgpiod tck_num 5
+expected_value "adapter gpio tck (output): num 5, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tck]
+
+linuxgpiod tms_num 6
+expected_value "adapter gpio tms (output): num 6, chip 0, active-high, push-pull, pull-none, init-state active" [eval adapter gpio tms]
+
+linuxgpiod tdi_num 7
+expected_value "adapter gpio tdi (output): num 7, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tdi]
+
+linuxgpiod tdo_num 8
+expected_value "adapter gpio tdo (input): num 8, chip 0, active-high, pull-none, init-state input" [eval adapter gpio tdo]
+
+linuxgpiod swd_nums 9 10
+expected_value "adapter gpio swclk (output): num 9, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swclk]
+expected_value "adapter gpio swdio (bidirectional): num 10, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swdio]
+
+linuxgpiod swclk_num 11
+expected_value "adapter gpio swclk (output): num 11, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swclk]
+
+linuxgpiod swdio_num 12
+expected_value "adapter gpio swdio (bidirectional): num 12, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swdio]
+
+linuxgpiod swdio_dir_num 13
+expected_value "adapter gpio swdio_dir (output): num 13, chip 0, active-high, push-pull, pull-none" [eval adapter gpio swdio_dir]
+
+linuxgpiod srst_num 14
+expected_value "adapter gpio srst (output): num 14, chip 0, active-low, pull-none, init-state inactive" [eval adapter gpio srst]
+
+linuxgpiod trst_num 15
+expected_value "adapter gpio trst (output): num 15, chip 0, active-low, pull-none, init-state inactive" [eval adapter gpio trst]
+
+linuxgpiod led_num 16
+expected_value "adapter gpio led (output): num 16, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio led]
+
+#####################################
+# Test the old linuxgpiod_* commands
+
+# Change the GPIO chip for all signals. Don't check directly here, do so when
+# each signal command is tested.
+linuxgpiod_gpiochip 1
+
+linuxgpiod_jtag_nums 17 18 19 20
+expected_value "adapter gpio tck (output): num 17, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tck]
+expected_value "adapter gpio tms (output): num 18, chip 1, active-high, push-pull, pull-none, init-state active" [eval adapter gpio tms]
+expected_value "adapter gpio tdi (output): num 19, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tdi]
+expected_value "adapter gpio tdo (input): num 20, chip 1, active-high, pull-none, init-state input" [eval adapter gpio tdo]
+
+linuxgpiod_tck_num 21
+expected_value "adapter gpio tck (output): num 21, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tck]
+
+linuxgpiod_tms_num 22
+expected_value "adapter gpio tms (output): num 22, chip 1, active-high, push-pull, pull-none, init-state active" [eval adapter gpio tms]
+
+linuxgpiod_tdi_num 23
+expected_value "adapter gpio tdi (output): num 23, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tdi]
+
+linuxgpiod_tdo_num 24
+expected_value "adapter gpio tdo (input): num 24, chip 1, active-high, pull-none, init-state input" [eval adapter gpio tdo]
+
+linuxgpiod_swd_nums 25 26
+expected_value "adapter gpio swclk (output): num 25, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swclk]
+expected_value "adapter gpio swdio (bidirectional): num 26, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swdio]
+
+linuxgpiod_swclk_num 27
+expected_value "adapter gpio swclk (output): num 27, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swclk]
+
+linuxgpiod_swdio_num 28
+expected_value "adapter gpio swdio (bidirectional): num 28, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swdio]
+
+linuxgpiod_led_num 29
+expected_value "adapter gpio led (output): num 29, chip 1, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio led]
+
+puts "SUCCESS"
commit 903f2e92a143acf66fcaa82e628c1672fdd0da9f
Author: Steve Marple <ste...@go...>
Date: Wed Jun 22 15:43:51 2022 +0100
drivers/am335xgpio: Release resources on error and when quitting
The /dev/mem file descriptor can be closed without invalidating the
mappings so close as soon as possible.
munmap() all memory, either on error or from quit.
Change-Id: I9466edd2f43791e64f2dce719957c67728f3ec06
Signed-off-by: Steve Marple <ste...@go...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7047
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/am335xgpio.c b/src/jtag/drivers/am335xgpio.c
index 5b68b6d6f..ae58b1640 100644
--- a/src/jtag/drivers/am335xgpio.c
+++ b/src/jtag/drivers/am335xgpio.c
@@ -377,6 +377,13 @@ static bool am335xgpio_swd_mode_possible(void)
return true;
}
+static void am335xgpio_munmap(void)
+{
+ for (unsigned int i = 0; i < AM335XGPIO_NUM_GPIO_CHIPS && am335xgpio_gpio_chip_mmap_addr[i] != MAP_FAILED; ++i)
+ if (munmap((void *)am335xgpio_gpio_chip_mmap_addr[i], sysconf(_SC_PAGE_SIZE)) < 0)
+ LOG_ERROR("Cannot unmap GPIO memory for chip %d: %s", i, strerror(errno));
+}
+
static int am335xgpio_init(void)
{
LOG_INFO("AM335x GPIO JTAG/SWD bitbang driver");
@@ -410,10 +417,12 @@ static int am335xgpio_init(void)
if (am335xgpio_gpio_chip_mmap_addr[i] == MAP_FAILED) {
LOG_ERROR("mmap: %s", strerror(errno));
+ am335xgpio_munmap();
close(dev_mem_fd);
return ERROR_JTAG_INIT_FAILED;
}
}
+ close(dev_mem_fd);
/* Configure JTAG/SWD signals. Default directions and initial states are handled
* by adapter.c and "adapter gpio" command.
@@ -476,6 +485,8 @@ static int am335xgpio_quit(void)
restore_gpio(ADAPTER_GPIO_IDX_SRST);
restore_gpio(ADAPTER_GPIO_IDX_LED);
+ am335xgpio_munmap();
+
return ERROR_OK;
}
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 89 +---
src/jtag/drivers/am335xgpio.c | 11 +
src/jtag/drivers/linuxgpiod.c | 636 ++++++------------------
src/jtag/startup.tcl | 127 ++++-
tcl/interface/dln-2-gpiod.cfg | 15 +-
testing/test-linuxgpiod-deprecated-commands.cfg | 105 ++++
6 files changed, 394 insertions(+), 589 deletions(-)
create mode 100644 testing/test-linuxgpiod-deprecated-commands.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-15 13:25:05
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via ace028262ba0bda0e921afb11e6eb7d87708d889 (commit)
via 82fd4005427b6774a754b791bdf384f3ef45072d (commit)
from 3adbec9aab95808222071eb09014f28fbb6ad1be (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit ace028262ba0bda0e921afb11e6eb7d87708d889
Author: Steve Marple <ste...@go...>
Date: Tue May 17 21:51:17 2022 +0100
drivers/am335xgpio: Migrate to adapter gpio commands
Use the new "adapter gpio" commands to configure the GPIOs used by the
am335xgpio driver. The AM335x has 4 GPIO 'chips' (chip number 0-3
inclusive), with each one providing 32 GPIOs (gpio_num 0-31 inclusive).
Change-Id: I7c63c0e4763657ea51790c43fc40d32b7c3580bb
Signed-off-by: Steve Marple <ste...@go...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6984
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 083f946c4..27a552286 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -3387,86 +3387,16 @@ registers directly. The memory mapping requires read and write permission to
kernel memory; if /dev/gpiomem exists it will be used, otherwise /dev/mem will
be used. The driver restores the GPIO state on exit.
-All four GPIO ports are available. GPIOs numbered 0 to 31 are mapped to GPIO port
-0, GPIO numbers 32 to 63 are mapped to GPIO port 1 and so on.
-
-See @file{interface/beaglebone-swd-native.cfg} for a sample configuration file.
-
-@deffn {Config Command} {am335xgpio jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
-Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order).
-Must be specified to enable JTAG transport. These pins can also be specified
-individually.
-@end deffn
-
-@deffn {Config Command} {am335xgpio tck_num} @var{tck}
-Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be
-specified using the configuration command @command{am335xgpio jtag_nums}.
-@end deffn
-
-@deffn {Config Command} {am335xgpio tms_num} @var{tms}
-Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be
-specified using the configuration command @command{am335xgpio jtag_nums}.
-@end deffn
-
-@deffn {Config Command} {am335xgpio tdo_num} @var{tdo}
-Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be
-specified using the configuration command @command{am335xgpio jtag_nums}.
-@end deffn
-
-@deffn {Config Command} {am335xgpio tdi_num} @var{tdi}
-Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be
-specified using the configuration command @command{am335xgpio jtag_nums}.
-@end deffn
-
-@deffn {Config Command} {am335xgpio swd_nums} @var{swclk} @var{swdio}
-Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
-specified to enable SWD transport. These pins can also be specified individually.
-@end deffn
-
-@deffn {Config Command} {am335xgpio swclk_num} @var{swclk}
-Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be
-specified using the configuration command @command{am335xgpio swd_nums}.
-@end deffn
-
-@deffn {Config Command} {am335xgpio swdio_num} @var{swdio}
-Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be
-specified using the configuration command @command{am335xgpio swd_nums}.
-@end deffn
-
-@deffn {Config Command} {am335xgpio swdio_dir_num} @var{swdio_dir}
-Set SWDIO direction control pin GPIO number. If specified, this pin can be used
-to control the direction of an external buffer on the SWDIO pin. The direction
-control state can be set with the command @command{am335xgpio
-swdio_dir_output_state}. If not specified this feature is disabled.
-@end deffn
-
-@deffn {Config Command} {am335xgpio swdio_dir_output_state} @var{output_state}
-Set the state required for an external SWDIO buffer to be an output. Valid
-values are @option{on} (default) and @option{off}.
-@end deffn
-
-@deffn {Config Command} {am335xgpio srst_num} @var{srst}
-Set SRST GPIO number. Must be specified to enable SRST.
-@end deffn
-
-@deffn {Config Command} {am335xgpio trst_num} @var{trst}
-Set TRST GPIO number. Must be specified to enable TRST.
-@end deffn
-
-@deffn {Config Command} {am335xgpio led_num} @var{led}
-Set activity LED GPIO number. If not specified an activity LED is not enabled.
-@end deffn
-
-@deffn {Config Command} {am335xgpio led_on_state} @var{on_state}
-Set required logic level for the LED to be on. Valid values are @option{on}
-(default) and @option{off}.
-@end deffn
+All four GPIO ports are available. GPIO configuration is handled by the generic
+command @ref{adapter gpio, @command{adapter gpio}}.
@deffn {Config Command} {am335xgpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified
speed_coeff defaults to 600000 and speed_offset defaults to 575.
@end deffn
+See @file{interface/beaglebone-swd-native.cfg} for a sample configuration file.
+
@end deffn
diff --git a/src/jtag/drivers/am335xgpio.c b/src/jtag/drivers/am335xgpio.c
index 62e276737..5b68b6d6f 100644
--- a/src/jtag/drivers/am335xgpio.c
+++ b/src/jtag/drivers/am335xgpio.c
@@ -10,23 +10,24 @@
#include "config.h"
#endif
+#include <jtag/adapter.h>
#include <jtag/interface.h>
#include <transport/transport.h>
#include "bitbang.h"
#include <sys/mman.h>
-/*
- * GPIO register base addresses. Values taken from "AM335x and AMIC110 Sitara
+/* GPIO register base addresses. Values taken from "AM335x and AMIC110 Sitara
* Processors Technical Reference Manual", Chapter 2 Memory Map.
*/
-#define AM335XGPIO_NUM_GPIO_PORTS 4
+#define AM335XGPIO_NUM_GPIO_PER_CHIP 32
+#define AM335XGPIO_NUM_GPIO_CHIPS 4
#define AM335XGPIO_GPIO0_HW_ADDR 0x44E07000
#define AM335XGPIO_GPIO1_HW_ADDR 0x4804C000
#define AM335XGPIO_GPIO2_HW_ADDR 0x481AC000
#define AM335XGPIO_GPIO3_HW_ADDR 0x481AE000
-/* 32-bit offsets from GPIO port base address. Values taken from "AM335x and
+/* 32-bit offsets from GPIO chip base address. Values taken from "AM335x and
* AMIC110 Sitara Processors Technical Reference Manual", Chapter 25
* General-Purpose Input/Output.
*/
@@ -36,34 +37,34 @@
#define AM335XGPIO_GPIO_CLEARDATAOUT_OFFSET (0x190 / 4)
#define AM335XGPIO_GPIO_SETDATAOUT_OFFSET (0x194 / 4)
-/* GPIOs are integer values; need to map to a port module, and the pin within
- * that module. GPIOs 0 to 31 map to GPIO0, 32 to 63 to GPIO1 etc. This scheme
- * matches that used by Linux on the BeagleBone.
- */
-#define AM335XGPIO_PORT_NUM(gpio_num) ((gpio_num) / 32)
-#define AM335XGPIO_BIT_NUM(gpio_num) ((gpio_num) % 32)
-#define AM335XGPIO_BIT_MASK(gpio_num) BIT(AM335XGPIO_BIT_NUM(gpio_num))
+#define AM335XGPIO_READ_REG(chip_num, offset) \
+ (*(am335xgpio_gpio_chip_mmap_addr[(chip_num)] + (offset)))
-#define AM335XGPIO_READ_REG(gpio_num, offset) \
- (*(am335xgpio_gpio_port_mmap_addr[AM335XGPIO_PORT_NUM(gpio_num)] + (offset)))
+#define AM335XGPIO_WRITE_REG(chip_num, offset, value) \
+ (*(am335xgpio_gpio_chip_mmap_addr[(chip_num)] + (offset)) = (value))
-#define AM335XGPIO_WRITE_REG(gpio_num, offset, value) \
- (*(am335xgpio_gpio_port_mmap_addr[AM335XGPIO_PORT_NUM(gpio_num)] + (offset)) = (value))
+#define AM335XGPIO_SET_REG_BITS(chip_num, offset, bit_mask) \
+ (*(am335xgpio_gpio_chip_mmap_addr[(chip_num)] + (offset)) |= (bit_mask))
-#define AM335XGPIO_SET_REG_BITS(gpio_num, offset, bit_mask) \
- (*(am335xgpio_gpio_port_mmap_addr[AM335XGPIO_PORT_NUM(gpio_num)] + (offset)) |= (bit_mask))
+#define AM335XGPIO_CLEAR_REG_BITS(chip_num, offset, bit_mask) \
+ (*(am335xgpio_gpio_chip_mmap_addr[(chip_num)] + (offset)) &= ~(bit_mask))
-#define AM335XGPIO_CLEAR_REG_BITS(gpio_num, offset, bit_mask) \
- (*(am335xgpio_gpio_port_mmap_addr[AM335XGPIO_PORT_NUM(gpio_num)] + (offset)) &= ~(bit_mask))
+#define AM335XGPIO_SET_INPUT(gpio_config) \
+ AM335XGPIO_SET_REG_BITS((gpio_config)->chip_num, AM335XGPIO_GPIO_OE_OFFSET, BIT((gpio_config)->gpio_num))
+#define AM335XGPIO_SET_OUTPUT(gpio_config) \
+ AM335XGPIO_CLEAR_REG_BITS((gpio_config)->chip_num, AM335XGPIO_GPIO_OE_OFFSET, BIT((gpio_config)->gpio_num))
+#define AM335XGPIO_SET_HIGH(gpio_config) \
+ AM335XGPIO_WRITE_REG((gpio_config)->chip_num, AM335XGPIO_GPIO_SETDATAOUT_OFFSET, BIT((gpio_config)->gpio_num))
+#define AM335XGPIO_SET_LOW(gpio_config) \
+ AM335XGPIO_WRITE_REG((gpio_config)->chip_num, AM335XGPIO_GPIO_CLEARDATAOUT_OFFSET, BIT((gpio_config)->gpio_num))
-enum amx335gpio_gpio_mode {
+enum amx335gpio_initial_gpio_mode {
AM335XGPIO_GPIO_MODE_INPUT,
- AM335XGPIO_GPIO_MODE_OUTPUT, /* To set output mode but not state */
AM335XGPIO_GPIO_MODE_OUTPUT_LOW,
AM335XGPIO_GPIO_MODE_OUTPUT_HIGH,
};
-static const uint32_t am335xgpio_gpio_port_hw_addr[AM335XGPIO_NUM_GPIO_PORTS] = {
+static const uint32_t am335xgpio_gpio_chip_hw_addr[AM335XGPIO_NUM_GPIO_CHIPS] = {
AM335XGPIO_GPIO0_HW_ADDR,
AM335XGPIO_GPIO1_HW_ADDR,
AM335XGPIO_GPIO2_HW_ADDR,
@@ -71,117 +72,151 @@ static const uint32_t am335xgpio_gpio_port_hw_addr[AM335XGPIO_NUM_GPIO_PORTS] =
};
/* Memory-mapped address pointers */
-static volatile uint32_t *am335xgpio_gpio_port_mmap_addr[AM335XGPIO_NUM_GPIO_PORTS];
+static volatile uint32_t *am335xgpio_gpio_chip_mmap_addr[AM335XGPIO_NUM_GPIO_CHIPS];
static int dev_mem_fd;
-
-/* GPIO numbers for each signal. Negative values are invalid */
-static int tck_gpio = -1;
-static enum amx335gpio_gpio_mode tck_gpio_mode;
-static int tms_gpio = -1;
-static enum amx335gpio_gpio_mode tms_gpio_mode;
-static int tdi_gpio = -1;
-static enum amx335gpio_gpio_mode tdi_gpio_mode;
-static int tdo_gpio = -1;
-static enum amx335gpio_gpio_mode tdo_gpio_mode;
-static int trst_gpio = -1;
-static enum amx335gpio_gpio_mode trst_gpio_mode;
-static int srst_gpio = -1;
-static enum amx335gpio_gpio_mode srst_gpio_mode;
-static int swclk_gpio = -1;
-static enum amx335gpio_gpio_mode swclk_gpio_mode;
-static int swdio_gpio = -1;
-static enum amx335gpio_gpio_mode swdio_gpio_mode;
-static int swdio_dir_gpio = -1;
-static enum amx335gpio_gpio_mode swdio_dir_gpio_mode;
-static int led_gpio = -1;
-static enum amx335gpio_gpio_mode led_gpio_mode = -1;
-
-static bool swdio_dir_is_active_high = true; /* Active state means output */
-static bool led_is_active_high = true;
+static enum amx335gpio_initial_gpio_mode initial_gpio_mode[ADAPTER_GPIO_IDX_NUM];
/* Transition delay coefficients */
static int speed_coeff = 600000;
static int speed_offset = 575;
static unsigned int jtag_delay;
-static int is_gpio_valid(int gpio_num)
-{
- return gpio_num >= 0 && gpio_num < (32 * AM335XGPIO_NUM_GPIO_PORTS);
-}
+static const struct adapter_gpio_config *adapter_gpio_config;
-static int get_gpio_value(int gpio_num)
+static bool is_gpio_config_valid(const struct adapter_gpio_config *gpio_config)
{
- unsigned int shift = AM335XGPIO_BIT_NUM(gpio_num);
- return (AM335XGPIO_READ_REG(gpio_num, AM335XGPIO_GPIO_DATAIN_OFFSET) >> shift) & 1;
+ return gpio_config->chip_num >= 0
+ && gpio_config->chip_num < AM335XGPIO_NUM_GPIO_CHIPS
+ && gpio_config->gpio_num >= 0
+ && gpio_config->gpio_num < AM335XGPIO_NUM_GPIO_PER_CHIP;
}
-static void set_gpio_value(int gpio_num, int value)
+static int get_gpio_value(const struct adapter_gpio_config *gpio_config)
{
- if (value)
- AM335XGPIO_WRITE_REG(gpio_num, AM335XGPIO_GPIO_SETDATAOUT_OFFSET, AM335XGPIO_BIT_MASK(gpio_num));
- else
- AM335XGPIO_WRITE_REG(gpio_num, AM335XGPIO_GPIO_CLEARDATAOUT_OFFSET, AM335XGPIO_BIT_MASK(gpio_num));
+ unsigned int shift = gpio_config->gpio_num;
+ uint32_t value = AM335XGPIO_READ_REG(gpio_config->chip_num, AM335XGPIO_GPIO_DATAIN_OFFSET);
+ value = (value >> shift) & 1;
+ return value ^ (gpio_config->active_low ? 1 : 0);
}
-static enum amx335gpio_gpio_mode get_gpio_mode(int gpio_num)
+static void set_gpio_value(const struct adapter_gpio_config *gpio_config, int value)
{
- if (AM335XGPIO_READ_REG(gpio_num, AM335XGPIO_GPIO_OE_OFFSET) & AM335XGPIO_BIT_MASK(gpio_num)) {
- return AM335XGPIO_GPIO_MODE_INPUT;
- } else {
- /* Return output level too so that pin mode can be fully restored */
- if (AM335XGPIO_READ_REG(gpio_num, AM335XGPIO_GPIO_DATAOUT_OFFSET) & AM335XGPIO_BIT_MASK(gpio_num))
- return AM335XGPIO_GPIO_MODE_OUTPUT_HIGH;
+ value = value ^ (gpio_config->active_low ? 1 : 0);
+ switch (gpio_config->drive) {
+ case ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL:
+ if (value)
+ AM335XGPIO_SET_HIGH(gpio_config);
else
- return AM335XGPIO_GPIO_MODE_OUTPUT_LOW;
+ AM335XGPIO_SET_LOW(gpio_config);
+ /* For performance reasons assume the GPIO is already set as an output
+ * and therefore the call can be omitted here.
+ */
+ break;
+ case ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN:
+ if (value) {
+ AM335XGPIO_SET_INPUT(gpio_config);
+ } else {
+ AM335XGPIO_SET_LOW(gpio_config);
+ AM335XGPIO_SET_OUTPUT(gpio_config);
+ }
+ break;
+ case ADAPTER_GPIO_DRIVE_MODE_OPEN_SOURCE:
+ if (value) {
+ AM335XGPIO_SET_HIGH(gpio_config);
+ AM335XGPIO_SET_OUTPUT(gpio_config);
+ } else {
+ AM335XGPIO_SET_INPUT(gpio_config);
+ }
+ break;
}
}
-static void set_gpio_mode(int gpio_num, enum amx335gpio_gpio_mode gpio_mode)
+static enum amx335gpio_initial_gpio_mode get_gpio_mode(const struct adapter_gpio_config *gpio_config)
{
- if (gpio_mode == AM335XGPIO_GPIO_MODE_INPUT) {
- AM335XGPIO_SET_REG_BITS(gpio_num, AM335XGPIO_GPIO_OE_OFFSET, AM335XGPIO_BIT_MASK(gpio_num));
- return;
- }
-
- if (gpio_mode == AM335XGPIO_GPIO_MODE_OUTPUT_LOW)
- set_gpio_value(gpio_num, 0);
- if (gpio_mode == AM335XGPIO_GPIO_MODE_OUTPUT_HIGH)
- set_gpio_value(gpio_num, 1);
+ if (AM335XGPIO_READ_REG(gpio_config->chip_num, AM335XGPIO_GPIO_OE_OFFSET) & BIT(gpio_config->gpio_num))
+ return AM335XGPIO_GPIO_MODE_INPUT;
- if (gpio_mode == AM335XGPIO_GPIO_MODE_OUTPUT ||
- gpio_mode == AM335XGPIO_GPIO_MODE_OUTPUT_LOW ||
- gpio_mode == AM335XGPIO_GPIO_MODE_OUTPUT_HIGH) {
- AM335XGPIO_CLEAR_REG_BITS(gpio_num, AM335XGPIO_GPIO_OE_OFFSET, AM335XGPIO_BIT_MASK(gpio_num));
- }
+ /* Return output level too so that pin mode can be fully restored */
+ if (AM335XGPIO_READ_REG(gpio_config->chip_num, AM335XGPIO_GPIO_DATAOUT_OFFSET) & BIT(gpio_config->gpio_num))
+ return AM335XGPIO_GPIO_MODE_OUTPUT_HIGH;
+ return AM335XGPIO_GPIO_MODE_OUTPUT_LOW;
}
-static const char *get_gpio_mode_name(enum amx335gpio_gpio_mode gpio_mode)
+static const char *get_gpio_mode_name(enum amx335gpio_initial_gpio_mode gpio_mode)
{
switch (gpio_mode) {
case AM335XGPIO_GPIO_MODE_INPUT:
return "input";
- case AM335XGPIO_GPIO_MODE_OUTPUT:
- return "output";
case AM335XGPIO_GPIO_MODE_OUTPUT_LOW:
return "output (low)";
case AM335XGPIO_GPIO_MODE_OUTPUT_HIGH:
return "output (high)";
- default:
- return "unknown";
+ }
+ return "unknown";
+}
+
+static void initialize_gpio(enum adapter_gpio_config_index idx)
+{
+ if (!is_gpio_config_valid(&adapter_gpio_config[idx]))
+ return;
+
+ initial_gpio_mode[idx] = get_gpio_mode(&adapter_gpio_config[idx]);
+ LOG_DEBUG("saved GPIO mode for %s (GPIO %d %d): %s",
+ adapter_gpio_get_name(idx), adapter_gpio_config[idx].chip_num, adapter_gpio_config[idx].gpio_num,
+ get_gpio_mode_name(initial_gpio_mode[idx]));
+
+ if (adapter_gpio_config[idx].pull != ADAPTER_GPIO_PULL_NONE) {
+ LOG_WARNING("am335xgpio does not support pull-up or pull-down settings (signal %s)",
+ adapter_gpio_get_name(idx));
+ }
+
+ switch (adapter_gpio_config[idx].init_state) {
+ case ADAPTER_GPIO_INIT_STATE_INACTIVE:
+ set_gpio_value(&adapter_gpio_config[idx], 0);
+ break;
+ case ADAPTER_GPIO_INIT_STATE_ACTIVE:
+ set_gpio_value(&adapter_gpio_config[idx], 1);
+ break;
+ case ADAPTER_GPIO_INIT_STATE_INPUT:
+ AM335XGPIO_SET_INPUT(&adapter_gpio_config[idx]);
+ break;
+ }
+
+ /* Direction for non push-pull is already set by set_gpio_value() */
+ if (adapter_gpio_config[idx].drive == ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL)
+ AM335XGPIO_SET_OUTPUT(&adapter_gpio_config[idx]);
+}
+
+static void restore_gpio(enum adapter_gpio_config_index idx)
+{
+ if (is_gpio_config_valid(&adapter_gpio_config[idx])) {
+ switch (initial_gpio_mode[idx]) {
+ case AM335XGPIO_GPIO_MODE_INPUT:
+ AM335XGPIO_SET_INPUT(&adapter_gpio_config[idx]);
+ break;
+ case AM335XGPIO_GPIO_MODE_OUTPUT_LOW:
+ AM335XGPIO_SET_LOW(&adapter_gpio_config[idx]);
+ AM335XGPIO_SET_OUTPUT(&adapter_gpio_config[idx]);
+ break;
+ case AM335XGPIO_GPIO_MODE_OUTPUT_HIGH:
+ AM335XGPIO_SET_HIGH(&adapter_gpio_config[idx]);
+ AM335XGPIO_SET_OUTPUT(&adapter_gpio_config[idx]);
+ break;
+ }
}
}
static bb_value_t am335xgpio_read(void)
{
- return get_gpio_value(tdo_gpio) ? BB_HIGH : BB_LOW;
+ return get_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_TDO]) ? BB_HIGH : BB_LOW;
}
static int am335xgpio_write(int tck, int tms, int tdi)
{
- set_gpio_value(tdi_gpio, tdi);
- set_gpio_value(tms_gpio, tms);
- set_gpio_value(tck_gpio, tck); /* Write clock last */
+ set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_TDI], tdi);
+ set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_TMS], tms);
+ set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_TCK], tck); /* Write clock last */
for (unsigned int i = 0; i < jtag_delay; ++i)
asm volatile ("");
@@ -191,8 +226,8 @@ static int am335xgpio_write(int tck, int tms, int tdi)
static int am335xgpio_swd_write(int swclk, int swdio)
{
- set_gpio_value(swdio_gpio, swdio);
- set_gpio_value(swclk_gpio, swclk); /* Write clock last */
+ set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO], swdio);
+ set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK], swclk); /* Write clock last */
for (unsigned int i = 0; i < jtag_delay; ++i)
asm volatile ("");
@@ -203,49 +238,45 @@ static int am335xgpio_swd_write(int swclk, int swdio)
/* (1) assert or (0) deassert reset lines */
static int am335xgpio_reset(int trst, int srst)
{
- /* assume active low */
- if (is_gpio_valid(srst_gpio)) {
- if (jtag_get_reset_config() & RESET_SRST_PUSH_PULL)
- set_gpio_mode(srst_gpio, srst ? AM335XGPIO_GPIO_MODE_OUTPUT_LOW : AM335XGPIO_GPIO_MODE_OUTPUT_HIGH);
- else
- set_gpio_mode(srst_gpio, srst ? AM335XGPIO_GPIO_MODE_OUTPUT_LOW : AM335XGPIO_GPIO_MODE_INPUT);
- }
+ /* As the "adapter reset_config" command keeps the srst and trst gpio drive
+ * mode settings in sync we can use our standard set_gpio_value() function
+ * that honours drive mode and active low.
+ */
+ if (is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_SRST]))
+ set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SRST], srst);
- /* assume active low */
- if (is_gpio_valid(trst_gpio)) {
- if (jtag_get_reset_config() & RESET_TRST_OPEN_DRAIN)
- set_gpio_mode(trst_gpio, trst ? AM335XGPIO_GPIO_MODE_OUTPUT_LOW : AM335XGPIO_GPIO_MODE_INPUT);
- else
- set_gpio_mode(trst_gpio, trst ? AM335XGPIO_GPIO_MODE_OUTPUT_LOW : AM335XGPIO_GPIO_MODE_OUTPUT_HIGH);
- }
+ if (is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_TRST]))
+ set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_TRST], trst);
- LOG_DEBUG("am335xgpio_reset(%d, %d), trst_gpio: %d (%s), srst_gpio: %d (%s)",
+ LOG_DEBUG("am335xgpio_reset(%d, %d), trst_gpio: %d %d, srst_gpio: %d %d",
trst, srst,
- trst_gpio, get_gpio_mode_name(get_gpio_mode(trst_gpio)),
- srst_gpio, get_gpio_mode_name(get_gpio_mode(srst_gpio)));
+ adapter_gpio_config[ADAPTER_GPIO_IDX_TRST].chip_num, adapter_gpio_config[ADAPTER_GPIO_IDX_TRST].gpio_num,
+ adapter_gpio_config[ADAPTER_GPIO_IDX_SRST].chip_num, adapter_gpio_config[ADAPTER_GPIO_IDX_SRST].gpio_num);
return ERROR_OK;
}
static void am335xgpio_swdio_drive(bool is_output)
{
if (is_output) {
- set_gpio_value(swdio_dir_gpio, swdio_dir_is_active_high ? 1 : 0);
- set_gpio_mode(swdio_gpio, AM335XGPIO_GPIO_MODE_OUTPUT);
+ if (is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO_DIR]))
+ set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO_DIR], 1);
+ AM335XGPIO_SET_OUTPUT(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO]);
} else {
- set_gpio_mode(swdio_gpio, AM335XGPIO_GPIO_MODE_INPUT);
- set_gpio_value(swdio_dir_gpio, swdio_dir_is_active_high ? 0 : 1);
+ AM335XGPIO_SET_INPUT(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO]);
+ if (is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO_DIR]))
+ set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO_DIR], 0);
}
}
static int am335xgpio_swdio_read(void)
{
- return get_gpio_value(swdio_gpio);
+ return get_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO]);
}
static int am335xgpio_blink(int on)
{
- if (is_gpio_valid(led_gpio))
- set_gpio_value(led_gpio, (!on ^ led_is_active_high) ? 1 : 0);
+ if (is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_LED]))
+ set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_LED], on);
return ERROR_OK;
}
@@ -283,144 +314,6 @@ static int am335xgpio_speed(int speed)
return ERROR_OK;
}
-COMMAND_HANDLER(am335xgpio_handle_jtag_gpionums)
-{
- if (CMD_ARGC == 4) {
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tms_gpio);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], tdi_gpio);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], tdo_gpio);
- } else if (CMD_ARGC != 0) {
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
-
- command_print(CMD, "AM335x GPIO config: tck = %d, tms = %d, tdi = %d, tdo = %d",
- tck_gpio, tms_gpio, tdi_gpio, tdo_gpio);
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_tck)
-{
- if (CMD_ARGC == 1)
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio);
-
- command_print(CMD, "AM335x GPIO config: tck = %d", tck_gpio);
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_tms)
-{
- if (CMD_ARGC == 1)
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tms_gpio);
-
- command_print(CMD, "AM335x GPIO config: tms = %d", tms_gpio);
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_tdo)
-{
- if (CMD_ARGC == 1)
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tdo_gpio);
-
- command_print(CMD, "AM335x GPIO config: tdo = %d", tdo_gpio);
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_tdi)
-{
- if (CMD_ARGC == 1)
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tdi_gpio);
-
- command_print(CMD, "AM335x GPIO config: tdi = %d", tdi_gpio);
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_srst)
-{
- if (CMD_ARGC == 1)
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], srst_gpio);
-
- command_print(CMD, "AM335x GPIO config: srst = %d", srst_gpio);
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_trst)
-{
- if (CMD_ARGC == 1)
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], trst_gpio);
-
- command_print(CMD, "AM335x GPIO config: trst = %d", trst_gpio);
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(am335xgpio_handle_swd_gpionums)
-{
- if (CMD_ARGC == 2) {
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swclk_gpio);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], swdio_gpio);
- } else if (CMD_ARGC != 0) {
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
-
- command_print(CMD, "AM335x GPIO config: swclk = %d, swdio = %d", swclk_gpio, swdio_gpio);
-
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(am335xgpio_handle_swd_gpionum_swclk)
-{
- if (CMD_ARGC == 1)
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swclk_gpio);
-
- command_print(CMD, "AM335x GPIO config: swclk = %d", swclk_gpio);
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(am335xgpio_handle_swd_gpionum_swdio)
-{
- if (CMD_ARGC == 1)
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swdio_gpio);
-
- command_print(CMD, "AM335x GPIO config: swdio = %d", swdio_gpio);
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(am335xgpio_handle_swd_gpionum_swdio_dir)
-{
- if (CMD_ARGC == 1)
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swdio_dir_gpio);
-
- command_print(CMD, "AM335x GPIO config: swdio_dir = %d", swdio_dir_gpio);
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(am335xgpio_handle_swd_dir_output_state)
-{
- if (CMD_ARGC == 1)
- COMMAND_PARSE_BOOL(CMD_ARGV[0], swdio_dir_is_active_high, "high", "low");
-
- command_print(CMD, "AM335x GPIO config: swdio_dir_output_state = %s", swdio_dir_is_active_high ? "high" : "low");
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(am335xgpio_handle_gpionum_led)
-{
- if (CMD_ARGC == 1)
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], led_gpio);
-
- command_print(CMD, "AM335x GPIO config: led = %d", led_gpio);
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(am335xgpio_handle_led_on_state)
-{
- if (CMD_ARGC == 1)
- COMMAND_PARSE_BOOL(CMD_ARGV[0], led_is_active_high, "high", "low");
-
- command_print(CMD, "AM335x GPIO config: led_on_state = %s", led_is_active_high ? "high" : "low");
- return ERROR_OK;
-}
-
COMMAND_HANDLER(am335xgpio_handle_speed_coeffs)
{
if (CMD_ARGC == 2) {
@@ -434,104 +327,6 @@ COMMAND_HANDLER(am335xgpio_handle_speed_coeffs)
}
static const struct command_registration am335xgpio_subcommand_handlers[] = {
- {
- .name = "jtag_nums",
- .handler = am335xgpio_handle_jtag_gpionums,
- .mode = COMMAND_CONFIG,
- .help = "gpio numbers for tck, tms, tdi, tdo (in that order).",
- .usage = "[tck tms tdi tdo]",
- },
- {
- .name = "tck_num",
- .handler = am335xgpio_handle_jtag_gpionum_tck,
- .mode = COMMAND_CONFIG,
- .help = "gpio number for tck.",
- .usage = "[tck]",
- },
- {
- .name = "tms_num",
- .handler = am335xgpio_handle_jtag_gpionum_tms,
- .mode = COMMAND_CONFIG,
- .help = "gpio number for tms.",
- .usage = "[tms]",
- },
- {
- .name = "tdo_num",
- .handler = am335xgpio_handle_jtag_gpionum_tdo,
- .mode = COMMAND_CONFIG,
- .help = "gpio number for tdo.",
- .usage = "[tdo]",
- },
- {
- .name = "tdi_num",
- .handler = am335xgpio_handle_jtag_gpionum_tdi,
- .mode = COMMAND_CONFIG,
- .help = "gpio number for tdi.",
- .usage = "[tdi]",
- },
- {
- .name = "swd_nums",
- .handler = am335xgpio_handle_swd_gpionums,
- .mode = COMMAND_CONFIG,
- .help = "gpio numbers for swclk, swdio (in that order).",
- .usage = "[swclk swdio]",
- },
- {
- .name = "swclk_num",
- .handler = am335xgpio_handle_swd_gpionum_swclk,
- .mode = COMMAND_CONFIG,
- .help = "gpio number for swclk.",
- .usage = "[swclk]",
- },
- {
- .name = "swdio_num",
- .handler = am335xgpio_handle_swd_gpionum_swdio,
- .mode = COMMAND_CONFIG,
- .help = "gpio number for swdio.",
- .usage = "[swdio]",
- },
- {
- .name = "swdio_dir_num",
- .handler = am335xgpio_handle_swd_gpionum_swdio_dir,
- .mode = COMMAND_CONFIG,
- .help = "gpio number for swdio direction control pin.",
- .usage = "[swdio_dir]",
- },
- {
- .name = "swdio_dir_output_state",
- .handler = am335xgpio_handle_swd_dir_output_state,
- .mode = COMMAND_CONFIG,
- .help = "required state for swdio_dir pin to select SWDIO buffer to be output.",
- .usage = "['off'|'on']",
- },
- {
- .name = "srst_num",
- .handler = am335xgpio_handle_jtag_gpionum_srst,
- .mode = COMMAND_CONFIG,
- .help = "gpio number for srst.",
- .usage = "[srst]",
- },
- {
- .name = "trst_num",
- .handler = am335xgpio_handle_jtag_gpionum_trst,
- .mode = COMMAND_CONFIG,
- .help = "gpio number for trst.",
- .usage = "[trst]",
- },
- {
- .name = "led_num",
- .handler = am335xgpio_handle_gpionum_led,
- .mode = COMMAND_CONFIG,
- .help = "gpio number for led.",
- .usage = "[led]",
- },
- {
- .name = "led_on_state",
- .handler = am335xgpio_handle_led_on_state,
- .mode = COMMAND_CONFIG,
- .help = "required state for led pin to turn on LED.",
- .usage = "['off'|'on']",
- },
{
.name = "speed_coeffs",
.handler = am335xgpio_handle_speed_coeffs,
@@ -562,32 +357,33 @@ static struct jtag_interface am335xgpio_interface = {
static bool am335xgpio_jtag_mode_possible(void)
{
- if (!is_gpio_valid(tck_gpio))
+ if (!is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_TCK]))
return false;
- if (!is_gpio_valid(tms_gpio))
+ if (!is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_TMS]))
return false;
- if (!is_gpio_valid(tdi_gpio))
+ if (!is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_TDI]))
return false;
- if (!is_gpio_valid(tdo_gpio))
+ if (!is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_TDO]))
return false;
return true;
}
static bool am335xgpio_swd_mode_possible(void)
{
- if (!is_gpio_valid(swclk_gpio))
+ if (!is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK]))
return false;
- if (!is_gpio_valid(swdio_gpio))
+ if (!is_gpio_config_valid(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO]))
return false;
return true;
}
static int am335xgpio_init(void)
{
- bitbang_interface = &am335xgpio_bitbang;
-
LOG_INFO("AM335x GPIO JTAG/SWD bitbang driver");
+ bitbang_interface = &am335xgpio_bitbang;
+ adapter_gpio_config = adapter_gpio_get_config();
+
if (transport_is_jtag() && !am335xgpio_jtag_mode_possible()) {
LOG_ERROR("Require tck, tms, tdi and tdo gpios for JTAG mode");
return ERROR_JTAG_INIT_FAILED;
@@ -608,99 +404,77 @@ static int am335xgpio_init(void)
return ERROR_JTAG_INIT_FAILED;
}
- for (unsigned int i = 0; i < AM335XGPIO_NUM_GPIO_PORTS; ++i) {
- am335xgpio_gpio_port_mmap_addr[i] = mmap(NULL, sysconf(_SC_PAGE_SIZE), PROT_READ | PROT_WRITE,
- MAP_SHARED, dev_mem_fd, am335xgpio_gpio_port_hw_addr[i]);
+ for (unsigned int i = 0; i < AM335XGPIO_NUM_GPIO_CHIPS; ++i) {
+ am335xgpio_gpio_chip_mmap_addr[i] = mmap(NULL, sysconf(_SC_PAGE_SIZE), PROT_READ | PROT_WRITE,
+ MAP_SHARED, dev_mem_fd, am335xgpio_gpio_chip_hw_addr[i]);
- if (am335xgpio_gpio_port_mmap_addr[i] == MAP_FAILED) {
+ if (am335xgpio_gpio_chip_mmap_addr[i] == MAP_FAILED) {
LOG_ERROR("mmap: %s", strerror(errno));
close(dev_mem_fd);
return ERROR_JTAG_INIT_FAILED;
}
}
- /*
- * Configure TDO as an input, and TDI, TCK, TMS, TRST, SRST as outputs.
- * Drive TDI and TCK low, and TMS high.
+ /* Configure JTAG/SWD signals. Default directions and initial states are handled
+ * by adapter.c and "adapter gpio" command.
*/
if (transport_is_jtag()) {
- tdo_gpio_mode = get_gpio_mode(tdo_gpio);
- tdi_gpio_mode = get_gpio_mode(tdi_gpio);
- tck_gpio_mode = get_gpio_mode(tck_gpio);
- tms_gpio_mode = get_gpio_mode(tms_gpio);
- LOG_DEBUG("saved GPIO mode for tdo (GPIO #%d): %s", tdo_gpio, get_gpio_mode_name(tdo_gpio_mode));
- LOG_DEBUG("saved GPIO mode for tdi (GPIO #%d): %s", tdi_gpio, get_gpio_mode_name(tdi_gpio_mode));
- LOG_DEBUG("saved GPIO mode for tck (GPIO #%d): %s", tck_gpio, get_gpio_mode_name(tck_gpio_mode));
- LOG_DEBUG("saved GPIO mode for tms (GPIO #%d): %s", tms_gpio, get_gpio_mode_name(tms_gpio_mode));
-
- set_gpio_mode(tdo_gpio, AM335XGPIO_GPIO_MODE_INPUT);
- set_gpio_mode(tdi_gpio, AM335XGPIO_GPIO_MODE_OUTPUT_LOW);
- set_gpio_mode(tms_gpio, AM335XGPIO_GPIO_MODE_OUTPUT_HIGH);
- set_gpio_mode(tck_gpio, AM335XGPIO_GPIO_MODE_OUTPUT_LOW);
-
- if (is_gpio_valid(trst_gpio)) {
- trst_gpio_mode = get_gpio_mode(trst_gpio);
- LOG_DEBUG("saved GPIO mode for trst (GPIO #%d): %s", trst_gpio, get_gpio_mode_name(trst_gpio_mode));
- }
+ initialize_gpio(ADAPTER_GPIO_IDX_TDO);
+ initialize_gpio(ADAPTER_GPIO_IDX_TDI);
+ initialize_gpio(ADAPTER_GPIO_IDX_TMS);
+ initialize_gpio(ADAPTER_GPIO_IDX_TCK);
+ initialize_gpio(ADAPTER_GPIO_IDX_TRST);
}
if (transport_is_swd()) {
- swclk_gpio_mode = get_gpio_mode(swclk_gpio);
- swdio_gpio_mode = get_gpio_mode(swdio_gpio);
- LOG_DEBUG("saved GPIO mode for swclk (GPIO #%d): %s", swclk_gpio, get_gpio_mode_name(swclk_gpio_mode));
- LOG_DEBUG("saved GPIO mode for swdio (GPIO #%d): %s", swdio_gpio, get_gpio_mode_name(swdio_gpio_mode));
- if (is_gpio_valid(swdio_dir_gpio)) {
- swdio_dir_gpio_mode = get_gpio_mode(swdio_dir_gpio);
- LOG_DEBUG("saved GPIO mode for swdio_dir (GPIO #%d): %s",
- swdio_dir_gpio, get_gpio_mode_name(swdio_dir_gpio_mode));
- set_gpio_mode(swdio_dir_gpio,
- swdio_dir_is_active_high ? AM335XGPIO_GPIO_MODE_OUTPUT_HIGH : AM335XGPIO_GPIO_MODE_OUTPUT_LOW);
-
+ /* swdio and its buffer should be initialized in the order that prevents
+ * two outputs from being connected together. This will occur if the
+ * swdio GPIO of the AM335x is configured as an output while its
+ * external buffer is configured to send the swdio signal from the
+ * target to the AM335x.
+ */
+ if (adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].init_state == ADAPTER_GPIO_INIT_STATE_INPUT) {
+ initialize_gpio(ADAPTER_GPIO_IDX_SWDIO);
+ initialize_gpio(ADAPTER_GPIO_IDX_SWDIO_DIR);
+ } else {
+ initialize_gpio(ADAPTER_GPIO_IDX_SWDIO_DIR);
+ initialize_gpio(ADAPTER_GPIO_IDX_SWDIO);
}
- set_gpio_mode(swdio_gpio, AM335XGPIO_GPIO_MODE_OUTPUT_LOW);
- set_gpio_mode(swclk_gpio, AM335XGPIO_GPIO_MODE_OUTPUT_LOW);
- }
- if (is_gpio_valid(srst_gpio)) {
- srst_gpio_mode = get_gpio_mode(srst_gpio);
- LOG_DEBUG("saved GPIO mode for srst (GPIO #%d): %s", srst_gpio, get_gpio_mode_name(srst_gpio_mode));
+ initialize_gpio(ADAPTER_GPIO_IDX_SWCLK);
}
- if (is_gpio_valid(led_gpio)) {
- led_gpio_mode = get_gpio_mode(led_gpio);
- LOG_DEBUG("saved GPIO mode for led (GPIO #%d): %s", led_gpio, get_gpio_mode_name(led_gpio_mode));
- set_gpio_mode(led_gpio,
- led_is_active_high ? AM335XGPIO_GPIO_MODE_OUTPUT_LOW : AM335XGPIO_GPIO_MODE_OUTPUT_HIGH);
- }
+ initialize_gpio(ADAPTER_GPIO_IDX_SRST);
+ initialize_gpio(ADAPTER_GPIO_IDX_LED);
- /* Set GPIO modes for TRST and SRST and make both inactive */
- am335xgpio_reset(0, 0);
return ERROR_OK;
}
static int am335xgpio_quit(void)
{
if (transport_is_jtag()) {
- set_gpio_mode(tdo_gpio, tdo_gpio_mode);
- set_gpio_mode(tdi_gpio, tdi_gpio_mode);
- set_gpio_mode(tck_gpio, tck_gpio_mode);
- set_gpio_mode(tms_gpio, tms_gpio_mode);
- if (is_gpio_valid(trst_gpio))
- set_gpio_mode(trst_gpio, trst_gpio_mode);
+ restore_gpio(ADAPTER_GPIO_IDX_TDO);
+ restore_gpio(ADAPTER_GPIO_IDX_TDI);
+ restore_gpio(ADAPTER_GPIO_IDX_TMS);
+ restore_gpio(ADAPTER_GPIO_IDX_TCK);
+ restore_gpio(ADAPTER_GPIO_IDX_TRST);
}
if (transport_is_swd()) {
- set_gpio_mode(swclk_gpio, swclk_gpio_mode);
- set_gpio_mode(swdio_gpio, swdio_gpio_mode);
- if (is_gpio_valid(swdio_dir_gpio))
- set_gpio_mode(swdio_dir_gpio, swdio_dir_gpio_mode);
+ /* Restore swdio/swdio_dir to their initial modes, even if that means
+ * connecting two outputs. Begin by making swdio an input so that the
+ * current and final states of swdio and swdio_dir do not have to be
+ * considered to calculate the safe restoration order.
+ */
+ AM335XGPIO_SET_INPUT(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO]);
+ restore_gpio(ADAPTER_GPIO_IDX_SWDIO_DIR);
+ restore_gpio(ADAPTER_GPIO_IDX_SWDIO);
+
+ restore_gpio(ADAPTER_GPIO_IDX_SWCLK);
}
- if (is_gpio_valid(srst_gpio))
- set_gpio_mode(srst_gpio, srst_gpio_mode);
-
- if (is_gpio_valid(led_gpio))
- set_gpio_mode(led_gpio, led_gpio_mode);
+ restore_gpio(ADAPTER_GPIO_IDX_SRST);
+ restore_gpio(ADAPTER_GPIO_IDX_LED);
return ERROR_OK;
}
diff --git a/src/jtag/startup.tcl b/src/jtag/startup.tcl
index 8791611e0..a72775e66 100644
--- a/src/jtag/startup.tcl
+++ b/src/jtag/startup.tcl
@@ -863,4 +863,106 @@ proc "xds110 serial" {args} {
eval adapter serial $args
}
+lappend _telnet_autocomplete_skip "am335xgpio jtag_nums"
+proc "am335xgpio jtag_nums" {tck_num tms_num tdi_num tdo_num} {
+ echo "DEPRECATED! use 'adapter gpio tck; adapter gpio tms; adapter gpio tdi; adapter gpio tdo' not 'am335xgpio jtag_nums'"
+ eval adapter gpio tck [expr {$tck_num % 32}] -chip [expr {$tck_num / 32}]
+ eval adapter gpio tms [expr {$tms_num % 32}] -chip [expr {$tms_num / 32}]
+ eval adapter gpio tdi [expr {$tdi_num % 32}] -chip [expr {$tdi_num / 32}]
+ eval adapter gpio tdo [expr {$tdo_num % 32}] -chip [expr {$tdo_num / 32}]
+}
+
+lappend _telnet_autocomplete_skip "am335xgpio tck_num"
+proc "am335xgpio tck_num" {num} {
+ echo "DEPRECATED! use 'adapter gpio tck' not 'am335xgpio tck_num'"
+ eval adapter gpio tck [expr {$num % 32}] -chip [expr {$num / 32}]
+}
+
+lappend _telnet_autocomplete_skip "am335xgpio tms_num"
+proc "am335xgpio tms_num" {num} {
+ echo "DEPRECATED! use 'adapter gpio tms' not 'am335xgpio tms_num'"
+ eval adapter gpio tms [expr {$num % 32}] -chip [expr {$num / 32}]
+}
+
+lappend _telnet_autocomplete_skip "am335xgpio tdi_num"
+proc "am335xgpio tdi_num" {num} {
+ echo "DEPRECATED! use 'adapter gpio tdi' not 'am335xgpio tdi_num'"
+ eval adapter gpio tdi [expr {$num % 32}] -chip [expr {$num / 32}]
+}
+
+lappend _telnet_autocomplete_skip "am335xgpio tdo_num"
+proc "am335xgpio tdo_num" {num} {
+ echo "DEPRECATED! use 'adapter gpio tdo' not 'am335xgpio tdo_num'"
+ eval adapter gpio tdo [expr {$num % 32}] -chip [expr {$num / 32}]
+}
+
+lappend _telnet_autocomplete_skip "am335xgpio swd_nums"
+proc "am335xgpio swd_nums" {swclk swdio} {
+ echo "DEPRECATED! use 'adapter gpio swclk; adapter gpio swdio' not 'am335xgpio jtag_nums'"
+ eval adapter gpio swclk [expr {$swclk % 32}] -chip [expr {$swclk / 32}]
+ eval adapter gpio swdio [expr {$swdio % 32}] -chip [expr {$swdio / 32}]
+}
+
+lappend _telnet_autocomplete_skip "am335xgpio swclk_num"
+proc "am335xgpio swclk_num" {num} {
+ echo "DEPRECATED! use 'adapter gpio swclk' not 'am335xgpio swclk_num'"
+ eval adapter gpio swclk [expr {$num % 32}] -chip [expr {$num / 32}]
+}
+
+lappend _telnet_autocomplete_skip "am335xgpio swdio_num"
+proc "am335xgpio swdio_num" {num} {
+ echo "DEPRECATED! use 'adapter gpio swdio' not 'am335xgpio swdio_num'"
+ eval adapter gpio swdio [expr {$num % 32}] -chip [expr {$num / 32}]
+}
+
+lappend _telnet_autocomplete_skip "am335xgpio swdio_dir_num"
+proc "am335xgpio swdio_dir_num" {num} {
+ echo "DEPRECATED! use 'adapter gpio swdio_dir' not 'am335xgpio swdio_dir_num'"
+ eval adapter gpio swdio_dir [expr {$num % 32}] -chip [expr {$num / 32}]
+}
+
+lappend _telnet_autocomplete_skip "am335xgpio swdio_dir_output_state"
+proc "am335xgpio swdio_dir_output_state" {state} {
+ echo "DEPRECATED! use 'adapter gpio swdio_dir -active-high' or 'adapter gpio swdio_dir -active-low', not 'am335xgpio swdio_dir_output_state'"
+ switch $state {
+ "high"
+ {eval adapter gpio swdio_dir -active-high}
+ "low"
+ {eval adapter gpio swdio_dir -active-low}
+ default
+ {return -code 1 -level 1 "am335xgpio swdio_dir_output_state: syntax error"}
+ }
+}
+
+lappend _telnet_autocomplete_skip "am335xgpio srst_num"
+proc "am335xgpio srst_num" {num} {
+ echo "DEPRECATED! use 'adapter gpio srst' not 'am335xgpio srst_num'"
+ eval adapter gpio srst [expr {$num % 32}] -chip [expr {$num / 32}]
+}
+
+lappend _telnet_autocomplete_skip "am335xgpio trst_num"
+proc "am335xgpio trst_num" {num} {
+ echo "DEPRECATED! use 'adapter gpio trst' not 'am335xgpio trst_num'"
+ eval adapter gpio trst [expr {$num % 32}] -chip [expr {$num / 32}]
+}
+
+lappend _telnet_autocomplete_skip "am335xgpio led_num"
+proc "am335xgpio led_num" {num} {
+ echo "DEPRECATED! use 'adapter gpio led' not 'am335xgpio led_num'"
+ eval adapter gpio led [expr {$num % 32}] -chip [expr {$num / 32}]
+}
+
+lappend _telnet_autocomplete_skip "am335xgpio led_on_state"
+proc "am335xgpio led_on_state" {state} {
+ echo "DEPRECATED! use 'adapter gpio led -active-high' or 'adapter gpio led -active-low', not 'am335xgpio led_on_state'"
+ switch $state {
+ "high"
+ {eval adapter gpio led -active-high}
+ "low"
+ {eval adapter gpio led -active-low}
+ default
+ {return -code 1 -level 1 "am335xgpio led_on_state: syntax error"}
+ }
+}
+
# END MIGRATION AIDS
diff --git a/tcl/interface/beaglebone-jtag-native.cfg b/tcl/interface/beaglebone-jtag-native.cfg
index cd32ca49b..0240e5d8b 100644
--- a/tcl/interface/beaglebone-jtag-native.cfg
+++ b/tcl/interface/beaglebone-jtag-native.cfg
@@ -16,13 +16,21 @@ adapter driver am335xgpio
# am335xgpio speed SPEED_COEFF SPEED_OFFSET
am335xgpio speed_coeffs 600000 575
-am335xgpio tdo_num 20
-am335xgpio tdi_num 60
-am335xgpio tms_num 4
-am335xgpio tck_num 2
+# BeagleBone pin P9_41
+adapter gpio tdo 20 -chip 0
-am335xgpio led_num 51
-am335xgpio led_on_state on
+# BeagleBone pin P9_12
+adapter gpio tdi 28 -chip 1
-am335xgpio srst_num 65
+# BeagleBone pin P9_18
+adapter gpio tms 4 -chip 0
+
+# BeagleBone pin P9_22
+adapter gpio tck 2 -chip 0
+
+# BeagleBone pin P9_16
+adapter gpio led 19 -chip 1
+
+# BeagleBone pin P8_18
+adapter gpio srst 1 -chip 2
reset_config srst_only srst_push_pull
diff --git a/tcl/interface/beaglebone-swd-native.cfg b/tcl/interface/beaglebone-swd-native.cfg
index f7bff6e57..6c4084979 100644
--- a/tcl/interface/beaglebone-swd-native.cfg
+++ b/tcl/interface/beaglebone-swd-native.cfg
@@ -16,14 +16,18 @@ adapter driver am335xgpio
# am335xgpio speed SPEED_COEFF SPEED_OFFSET
am335xgpio speed_coeffs 600000 575
-am335xgpio swclk_num 2
-am335xgpio swdio_num 4
-am335xgpio swdio_dir_num 60
-am335xgpio swdio_dir_output_state on
+# BeagleBone pin P9_22
+adapter gpio swclk 2 -chip 0
+
+# BeagleBone pin P9_18
+adapter gpio swdio 4 -chip 0
+
+# BeagleBone pin P9_12
+adapter gpio swdio_dir 28 -chip 1
# USR0 LED
-am335xgpio led_num 53
-am335xgpio led_on_state on
+adapter gpio led 21 -chip 1
-am335xgpio srst_num 65
+# BeagleBone pin P8_18
+adapter gpio srst 1 -chip 2
reset_config srst_only srst_push_pull
diff --git a/testing/test-am335xgpio-deprecated-commands.cfg b/testing/test-am335xgpio-deprecated-commands.cfg
new file mode 100644
index 000000000..09b204016
--- /dev/null
+++ b/testing/test-am335xgpio-deprecated-commands.cfg
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# OpenOCD script to test that the deprecated "am335xgpio *" commands produce the
+# expected results. Run this command as:
+#
+# openocd -f <path>/test-linuxgpiod-deprecated-commands.cfg
+
+# Raise an error if the "actual" value does not match the "expected" value. Trim
+# whitespace (including newlines) from strings before comparing.
+proc expected_value {expected actual} {
+ if {[string trim $expected] ne [string trim $actual]} {
+ error [puts "ERROR: '${actual}' != '${expected}'"]
+ }
+}
+
+adapter driver am335xgpio
+
+am335xgpio jtag_nums 1 2 3 4
+expected_value "adapter gpio tck (output): num 1, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tck]
+expected_value "adapter gpio tms (output): num 2, chip 0, active-high, push-pull, pull-none, init-state active" [eval adapter gpio tms]
+expected_value "adapter gpio tdi (output): num 3, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tdi]
+expected_value "adapter gpio tdo (input): num 4, chip 0, active-high, pull-none, init-state input" [eval adapter gpio tdo]
+
+am335xgpio tck_num 5
+expected_value "adapter gpio tck (output): num 5, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tck]
+
+am335xgpio tms_num 6
+expected_value "adapter gpio tms (output): num 6, chip 0, active-high, push-pull, pull-none, init-state active" [eval adapter gpio tms]
+
+am335xgpio tdi_num 7
+expected_value "adapter gpio tdi (output): num 7, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio tdi]
+
+am335xgpio tdo_num 8
+expected_value "adapter gpio tdo (input): num 8, chip 0, active-high, pull-none, init-state input" [eval adapter gpio tdo]
+
+am335xgpio swd_nums 9 10
+expected_value "adapter gpio swclk (output): num 9, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swclk]
+expected_value "adapter gpio swdio (bidirectional): num 10, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swdio]
+
+am335xgpio swclk_num 11
+expected_value "adapter gpio swclk (output): num 11, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swclk]
+
+am335xgpio swdio_num 12
+expected_value "adapter gpio swdio (bidirectional): num 12, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio swdio]
+
+am335xgpio swdio_dir_num 13
+expected_value "adapter gpio swdio_dir (output): num 13, chip 0, active-high, push-pull, pull-none" [eval adapter gpio swdio_dir]
+
+am335xgpio swdio_dir_output_state low
+expected_value "adapter gpio swdio_dir (output): num 13, chip 0, active-low, push-pull, pull-none" [eval adapter gpio swdio_dir]
+
+am335xgpio swdio_dir_output_state high
+expected_value "adapter gpio swdio_dir (output): num 13, chip 0, active-high, push-pull, pull-none" [eval adapter gpio swdio_dir]
+
+am335xgpio srst_num 14
+expected_value "adapter gpio srst (output): num 14, chip 0, active-low, pull-none, init-state inactive" [eval adapter gpio srst]
+
+am335xgpio trst_num 15
+expected_value "adapter gpio trst (output): num 15, chip 0, active-low, pull-none, init-state inactive" [eval adapter gpio trst]
+
+am335xgpio led_num 16
+expected_value "adapter gpio led (output): num 16, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio led]
+
+am335xgpio led_on_state low
+expected_value "adapter gpio led (output): num 16, chip 0, active-low, push-pull, pull-none, init-state inactive" [eval adapter gpio led]
+
+am335xgpio led_on_state high
+expected_value "adapter gpio led (output): num 16, chip 0, active-high, push-pull, pull-none, init-state inactive" [eval adapter gpio led]
+
+puts "SUCCESS"
commit 82fd4005427b6774a754b791bdf384f3ef45072d
Author: Steve Marple <ste...@go...>
Date: Wed May 4 22:51:48 2022 +0100
jtag/adapter: Add command 'adapter gpio'
Most adapters define their own commands to obtain the GPIO number and
other GPIO configuration information such as chip number, output drive
type, active high/low.
Define a general command 'adapter gpio' as replacement for the
driver-specific ones.
Change-Id: I1ca9ca94f0c7df5713172e9f62ffb0ad64e9ee97
Signed-off-by: Steve Marple <ste...@go...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6967
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 995861d18..083f946c4 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2412,7 +2412,57 @@ when external configuration (such as jumpering) changes what
the hardware can support.
@end deffn
+@anchor{adapter gpio}
+@deffn {Config Command} {adapter gpio [ @
+ @option{tdo} | @option{tdi} | @option{tms} | @option{tck} | @option{trst} | @
+ @option{swdio} | @option{swdio_dir} | @option{swclk} | @option{srst} | @
+ @option{led} @
+ [ @
+ gpio_number | @option{-chip} chip_number | @
+ @option{-active-high} | @option{-active-low} | @
+ @option{-push-pull} | @option{-open-drain} | @option{-open-source} | @
+ @option{-pull-none} | @option{-pull-up} | @option{-pull-down} | @
+ @option{-init-inactive} | @option{-init-active} | @option{-init-input} @
+ ] ]}
+
+Define the GPIO mapping that the adapter will use. The following signals can be
+defined:
+@itemize @minus
+@item @option{tdo}, @option{tdi}, @option{tms}, @option{tck}, @option{trst}:
+JTAG transport signals
+@item @option{swdio}, @option{swclk}: SWD transport signals
+@item @option{swdio_dir}: optional swdio buffer control signal
+@item @option{srst}: system reset signal
+@item @option{led}: optional activity led
+
+@end itemize
+
+Some adapters require that the GPIO chip number is set in addition to the GPIO
+number. The configuration options enable signals to be defined as active-high or
+active-low. The output drive mode can be set to push-pull, open-drain or
+open-source. Most adapters will have to emulate open-drain or open-source drive
+modes by switching between an input and output. Input and output signals can be
+instructed to use a pull-up or pull-down resistor, assuming it is supported by
+the adaptor driver and hardware. The initial state of outputs may also be set,
+"active" state means 1 for active-high outputs and 0 for active-low outputs.
+Bidirectional signals may also be initialized as an input. If the swdio signal
+is buffered the buffer direction can be controlled with the swdio_dir signal;
+the active state means that the buffer should be set as an output with respect
+to the adapter. The command options are cumulative with later commands able to
+override settings defined by earlier ones. The two commands @command{gpio led 7
+-active-high} and @command{gpio led -chip 1 -active-low} sent sequentially are
+equivalent to issuing the single command @command{gpio led 7 -chip 1
+-active-low}. It is not permissible to set the drive mode or initial state for
+signals which are inputs. The drive mode for the srst and trst signals must be
+set with the @command{adapter reset_config} command. It is not permissible to
+set the initial state of swdio_dir as it is derived from the initial state of
+swdio. The command @command{adapter gpio} prints the current configuration for
+all GPIOs while the command @command{adapter gpio gpio_name} prints the current
+configuration for gpio_name. Not all adapters support this generic GPIO mapping,
+some require their own commands to define the GPIOs used. Adapters that support
+the generic mapping may not support all of the listed options.
+@end deffn
@deffn {Command} {adapter name}
Returns the name of the debug adapter driver being used.
diff --git a/src/jtag/adapter.c b/src/jtag/adapter.c
index 519505dc3..76a2aaba6 100644
--- a/src/jtag/adapter.c
+++ b/src/jtag/adapter.c
@@ -48,13 +48,74 @@ static struct {
enum adapter_clk_mode clock_mode;
int speed_khz;
int rclk_fallback_speed_khz;
+ struct adapter_gpio_config gpios[ADAPTER_GPIO_IDX_NUM];
+ bool gpios_initialized; /* Initialization of GPIOs to their unset values performed at run time */
} adapter_config;
+static const struct gpio_map {
+ const char *name;
+ enum adapter_gpio_direction direction;
+ bool permit_drive_option;
+ bool permit_init_state_option;
+} gpio_map[ADAPTER_GPIO_IDX_NUM] = {
+ [ADAPTER_GPIO_IDX_TDO] = { "tdo", ADAPTER_GPIO_DIRECTION_INPUT, false, true, },
+ [ADAPTER_GPIO_IDX_TDI] = { "tdi", ADAPTER_GPIO_DIRECTION_OUTPUT, true, true, },
+ [ADAPTER_GPIO_IDX_TMS] = { "tms", ADAPTER_GPIO_DIRECTION_OUTPUT, true, true, },
+ [ADAPTER_GPIO_IDX_TCK] = { "tck", ADAPTER_GPIO_DIRECTION_OUTPUT, true, true, },
+ [ADAPTER_GPIO_IDX_SWDIO] = { "swdio", ADAPTER_GPIO_DIRECTION_BIDIRECTIONAL, true, true, },
+ [ADAPTER_GPIO_IDX_SWDIO_DIR] = { "swdio_dir", ADAPTER_GPIO_DIRECTION_OUTPUT, true, false, },
+ [ADAPTER_GPIO_IDX_SWCLK] = { "swclk", ADAPTER_GPIO_DIRECTION_OUTPUT, true, true, },
+ [ADAPTER_GPIO_IDX_TRST] = { "trst", ADAPTER_GPIO_DIRECTION_OUTPUT, false, true, },
+ [ADAPTER_GPIO_IDX_SRST] = { "srst", ADAPTER_GPIO_DIRECTION_OUTPUT, false, true, },
+ [ADAPTER_GPIO_IDX_LED] = { "led", ADAPTER_GPIO_DIRECTION_OUTPUT, true, true, },
+};
+
bool is_adapter_initialized(void)
{
return adapter_config.adapter_initialized;
}
+/* For convenience of the bit-banging drivers keep the gpio_config drive
+ * settings for srst and trst in sync with values set by the "adapter
+ * reset_config" command.
+ */
+static void sync_adapter_reset_with_gpios(void)
+{
+ enum reset_types cfg = jtag_get_reset_config();
+ if (cfg & RESET_SRST_PUSH_PULL)
+ adapter_config.gpios[ADAPTER_GPIO_IDX_SRST].drive = ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL;
+ else
+ adapter_config.gpios[ADAPTER_GPIO_IDX_SRST].drive = ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN;
+ if (cfg & RESET_TRST_OPEN_DRAIN)
+ adapter_config.gpios[ADAPTER_GPIO_IDX_TRST].drive = ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN;
+ else
+ adapter_config.gpios[ADAPTER_GPIO_IDX_TRST].drive = ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL;
+}
+
+static void adapter_driver_gpios_init(void)
+{
+ if (adapter_config.gpios_initialized)
+ return;
+
+ for (int i = 0; i < ADAPTER_GPIO_IDX_NUM; ++i) {
+ adapter_config.gpios[i].gpio_num = -1;
+ adapter_config.gpios[i].chip_num = -1;
+ if (gpio_map[i].direction == ADAPTER_GPIO_DIRECTION_INPUT)
+ adapter_config.gpios[i].init_state = ADAPTER_GPIO_INIT_STATE_INPUT;
+ }
+
+ /* Drivers assume active low, and this is the normal behaviour for reset
+ * lines so should be the default. */
+ adapter_config.gpios[ADAPTER_GPIO_IDX_SRST].active_low = true;
+ adapter_config.gpios[ADAPTER_GPIO_IDX_TRST].active_low = true;
+ sync_adapter_reset_with_gpios();
+
+ /* JTAG GPIOs should be inactive except for tms */
+ adapter_config.gpios[ADAPTER_GPIO_IDX_TMS].init_state = ADAPTER_GPIO_INIT_STATE_ACTIVE;
+
+ adapter_config.gpios_initialized = true;
+}
+
/**
* Do low-level setup like initializing registers, output signals,
* and clocking.
@@ -71,6 +132,8 @@ int adapter_init(struct command_context *cmd_ctx)
return ERROR_JTAG_INVALID_INTERFACE;
}
+ adapter_driver_gpios_init();
+
int retval;
if (adapter_config.clock_mode == CLOCK_MODE_UNSELECTED) {
@@ -540,6 +603,8 @@ next:
old_cfg &= ~mask;
new_cfg |= old_cfg;
jtag_set_reset_config(new_cfg);
+ sync_adapter_reset_with_gpios();
+
} else
new_cfg = jtag_get_reset_config();
@@ -770,6 +835,218 @@ COMMAND_HANDLER(handle_adapter_reset_de_assert)
(srst == VALUE_DEASSERT) ? SRST_DEASSERT : SRST_ASSERT);
}
+static int get_gpio_index(const char *signal_name)
+{
+ for (int i = 0; i < ADAPTER_GPIO_IDX_NUM; ++i) {
+ if (strcmp(gpio_map[i].name, signal_name) == 0)
+ return i;
+ }
+ return -1;
+}
+
+COMMAND_HELPER(helper_adapter_gpio_print_config, enum adapter_gpio_config_index gpio_idx)
+{
+ struct adapter_gpio_config *gpio_config = &adapter_config.gpios[gpio_idx];
+ const char *active_state = gpio_config->active_low ? "low" : "high";
+ const char *dir = "";
+ const char *drive = "";
+ const char *pull = "";
+ const char *init_state = "";
+
+ switch (gpio_map[gpio_idx].direction) {
+ case ADAPTER_GPIO_DIRECTION_INPUT:
+ dir = "input";
+ break;
+ case ADAPTER_GPIO_DIRECTION_OUTPUT:
+ dir = "output";
+ break;
+ case ADAPTER_GPIO_DIRECTION_BIDIRECTIONAL:
+ dir = "bidirectional";
+ break;
+ }
+
+ if (gpio_map[gpio_idx].permit_drive_option) {
+ switch (gpio_config->drive) {
+ case ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL:
+ drive = ", push-pull";
+ break;
+ case ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN:
+ drive = ", open-drain";
+ break;
+ case ADAPTER_GPIO_DRIVE_MODE_OPEN_SOURCE:
+ drive = ", open-source";
+ break;
+ }
+ }
+
+ switch (gpio_config->pull) {
+ case ADAPTER_GPIO_PULL_NONE:
+ pull = ", pull-none";
+ break;
+ case ADAPTER_GPIO_PULL_UP:
+ pull = ", pull-up";
+ break;
+ case ADAPTER_GPIO_PULL_DOWN:
+ pull = ", pull-down";
+ break;
+ }
+
+ if (gpio_map[gpio_idx].permit_init_state_option) {
+ switch (gpio_config->init_state) {
+ case ADAPTER_GPIO_INIT_STATE_INACTIVE:
+ init_state = ", init-state inactive";
+ break;
+ case ADAPTER_GPIO_INIT_STATE_ACTIVE:
+ init_state = ", init-state active";
+ break;
+ case ADAPTER_GPIO_INIT_STATE_INPUT:
+ init_state = ", init-state input";
+ break;
+ }
+ }
+
+ command_print(CMD, "adapter gpio %s (%s): num %d, chip %d, active-%s%s%s%s",
+ gpio_map[gpio_idx].name, dir, gpio_config->gpio_num, gpio_config->chip_num, active_state,
+ drive, pull, init_state);
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(helper_adapter_gpio_print_all_configs)
+{
+ for (int i = 0; i < ADAPTER_GPIO_IDX_NUM; ++i)
+ CALL_COMMAND_HANDLER(helper_adapter_gpio_print_config, i);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(adapter_gpio_config_handler)
+{
+ unsigned int i = 1;
+ struct adapter_gpio_config *gpio_config;
+
+ adapter_driver_gpios_init();
+
+ if (CMD_ARGC == 0) {
+ CALL_COMMAND_HANDLER(helper_adapter_gpio_print_all_configs);
+ return ERROR_OK;
+ }
+
+ int gpio_idx = get_gpio_index(CMD_ARGV[0]);
+ if (gpio_idx == -1) {
+ LOG_ERROR("adapter has no gpio named %s", CMD_ARGV[0]);
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ if (CMD_ARGC == 1) {
+ CALL_COMMAND_HANDLER(helper_adapter_gpio_print_config, gpio_idx);
+ return ERROR_OK;
+ }
+
+ gpio_config = &adapter_config.gpios[gpio_idx];
+ while (i < CMD_ARGC) {
+ LOG_DEBUG("Processing %s", CMD_ARGV[i]);
+
+ if (isdigit(*CMD_ARGV[i])) {
+ int gpio_num; /* Use a meaningful output parameter for more helpful error messages */
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[i], gpio_num);
+ gpio_config->gpio_num = gpio_num;
+ ++i;
+ continue;
+ }
+
+ if (strcmp(CMD_ARGV[i], "-chip") == 0) {
+ if (CMD_ARGC - i < 2) {
+ LOG_ERROR("-chip option requires a parameter");
+ return ERROR_FAIL;
+ }
+ LOG_DEBUG("-chip arg is %s", CMD_ARGV[i + 1]);
+ int chip_num; /* Use a meaningful output parameter for more helpful error messages */
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[i + 1], chip_num);
+ gpio_config->chip_num = chip_num;
+ i += 2;
+ continue;
+ }
+
+ if (strcmp(CMD_ARGV[i], "-active-high") == 0) {
+ ++i;
+ gpio_config->active_low = false;
+ continue;
+ }
+ if (strcmp(CMD_ARGV[i], "-active-low") == 0) {
+ ++i;
+ gpio_config->active_low = true;
+ continue;
+ }
+
+ if (gpio_map[gpio_idx].permit_drive_option) {
+ if (strcmp(CMD_ARGV[i], "-push-pull") == 0) {
+ ++i;
+ gpio_config->drive = ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL;
+ continue;
+ }
+ if (strcmp(CMD_ARGV[i], "-open-drain") == 0) {
+ ++i;
+ gpio_config->drive = ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN;
+ continue;
+ }
+ if (strcmp(CMD_ARGV[i], "-open-source") == 0) {
+ ++i;
+ gpio_config->drive = ADAPTER_GPIO_DRIVE_MODE_OPEN_SOURCE;
+ continue;
+ }
+ }
+
+ if (strcmp(CMD_ARGV[i], "-pull-none") == 0) {
+ ++i;
+ gpio_config->pull = ADAPTER_GPIO_PULL_NONE;
+ continue;
+ }
+ if (strcmp(CMD_ARGV[i], "-pull-up") == 0) {
+ ++i;
+ gpio_config->pull = ADAPTER_GPIO_PULL_UP;
+ continue;
+ }
+ if (strcmp(CMD_ARGV[i], "-pull-down") == 0) {
+ ++i;
+ gpio_config->pull = ADAPTER_GPIO_PULL_DOWN;
+ continue;
+ }
+
+ if (gpio_map[gpio_idx].permit_init_state_option) {
+ if (strcmp(CMD_ARGV[i], "-init-inactive") == 0) {
+ ++i;
+ gpio_config->init_state = ADAPTER_GPIO_INIT_STATE_INACTIVE;
+ continue;
+ }
+ if (strcmp(CMD_ARGV[i], "-init-active") == 0) {
+ ++i;
+ gpio_config->init_state = ADAPTER_GPIO_INIT_STATE_ACTIVE;
+ continue;
+ }
+
+ if (gpio_map[gpio_idx].direction == ADAPTER_GPIO_DIRECTION_BIDIRECTIONAL &&
+ strcmp(CMD_ARGV[i], "-init-input") == 0) {
+ ++i;
+ gpio_config->init_state = ADAPTER_GPIO_INIT_STATE_INPUT;
+ continue;
+ }
+ }
+
+ LOG_ERROR("illegal option for adapter %s %s: %s",
+ CMD_NAME, gpio_map[gpio_idx].name, CMD_ARGV[i]);
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ /* Force swdio_dir init state to be compatible with swdio init state */
+ if (gpio_idx == ADAPTER_GPIO_IDX_SWDIO)
+ adapter_config.gpios[ADAPTER_GPIO_IDX_SWDIO_DIR].init_state =
+ (gpio_config->init_state == ADAPTER_GPIO_INIT_STATE_INPUT) ?
+ ADAPTER_GPIO_INIT_STATE_INACTIVE :
+ ADAPTER_GPIO_INIT_STATE_ACTIVE;
+
+ return ERROR_OK;
+}
+
#ifdef HAVE_LIBUSB_GET_PORT_NUMBERS
COMMAND_HANDLER(handle_usb_location_command)
{
@@ -887,6 +1164,19 @@ static const struct command_registration adapter_command_handlers[] = {
.help = "Controls SRST and TRST lines.",
.usage = "|assert [srst|trst [deassert|assert srst|trst]]",
},
+ {
+ .name = "gpio",
+ .handler = adapter_gpio_config_handler,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio adapter command group",
+ .usage = "[ tdo|tdi|tms|tck|trst|swdio|swdio_dir|swclk|srst|led"
+ "[gpio_number] "
+ "[-chip chip_number] "
+ "[-active-high|-active-low] "
+ "[-push-pull|-open-drain|-open-source] "
+ "[-pull-none|-pull-up|-pull-down]"
+ "[-init-inactive|-init-active|-init-input] ]",
+ },
COMMAND_REGISTRATION_DONE
};
@@ -923,3 +1213,14 @@ int adapter_register_commands(struct command_context *ctx)
{
return register_commands(ctx, NULL, interface_command_handlers);
}
+
+const char *adapter_gpio_get_name(enum adapter_gpio_config_index idx)
+{
+ return gpio_map[idx].name;
+}
+
+/* Allow drivers access to the GPIO configuration */
+const struct adapter_gpio_config *adapter_gpio_get_config(void)
+{
+ return adapter_config.gpios;
+}
diff --git a/src/jtag/adapter.h b/src/jtag/adapter.h
index 300769c22..625a0b269 100644
--- a/src/jtag/adapter.h
+++ b/src/jtag/adapter.h
@@ -11,6 +11,59 @@
#include <stddef.h>
#include <stdint.h>
+/** Supported output drive modes for adaptor GPIO */
+enum adapter_gpio_drive_mode {
+ ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL,
+ ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN,
+ ADAPTER_GPIO_DRIVE_MODE_OPEN_SOURCE,
+};
+
+/** Supported GPIO directions */
+enum adapter_gpio_direction {
+ ADAPTER_GPIO_DIRECTION_INPUT,
+ ADAPTER_GPIO_DIRECTION_OUTPUT,
+ ADAPTER_GPIO_DIRECTION_BIDIRECTIONAL,
+};
+
+/** Supported initial states for GPIO */
+enum adapter_gpio_init_sta...
[truncated message content] |
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-15 13:24:22
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 3adbec9aab95808222071eb09014f28fbb6ad1be (commit)
from 7e8ea96345d58ad4d1f6da1a2c952560fe78fc60 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 3adbec9aab95808222071eb09014f28fbb6ad1be
Author: Tomas Vanek <va...@fb...>
Date: Tue Aug 2 11:44:43 2022 +0200
target/cortex_m: supress historical reset detection
The S_RESET_ST sticky bit is reset after DHCSR read.
It is set at power-on reset and keeps active until the debuger reads DHCSR.
Ignore S_RESET_ST at the very first read after OpenOCD start
and suppress possibly misleading message "external reset detected"
if we cannot guarantee the reset happened recently.
While on it add a TODO comment.
Change-Id: I15217c2ca6f69ac97aff8be86bce67cba94a42cd
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7109
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 9497aa037..aeaeb1829 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -652,6 +652,11 @@ static int cortex_m_endreset_event(struct target *target)
register_cache_invalidate(armv7m->arm.core_cache);
+ /* TODO: invalidate also working areas (needed in the case of detected reset).
+ * Doing so will require flash drivers to test if working area
+ * is still valid in all target algo calling loops.
+ */
+
/* make sure we have latest dhcsr flags */
retval = cortex_m_read_dhcsr_atomic_sticky(target);
if (retval != ERROR_OK)
@@ -2396,6 +2401,20 @@ int cortex_m_examine(struct target *target)
retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
+
+ /* Don't cumulate sticky S_RESET_ST at the very first read of DHCSR
+ * as S_RESET_ST may indicate a reset that happened long time ago
+ * (most probably the power-on reset before OpenOCD was started).
+ * As we are just initializing the debug system we do not need
+ * to call cortex_m_endreset_event() in the following poll.
+ */
+ if (!cortex_m->dcb_dhcsr_sticky_is_recent) {
+ cortex_m->dcb_dhcsr_sticky_is_recent = true;
+ if (cortex_m->dcb_dhcsr & S_RESET_ST) {
+ LOG_TARGET_DEBUG(target, "reset happened some time ago, ignore");
+ cortex_m->dcb_dhcsr &= ~S_RESET_ST;
+ }
+ }
cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 168613590..69368a919 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -206,6 +206,8 @@ struct cortex_m_common {
/* Context information */
uint32_t dcb_dhcsr;
uint32_t dcb_dhcsr_cumulated_sticky;
+ /* DCB DHCSR has been at least once read, so the sticky bits have been reset */
+ bool dcb_dhcsr_sticky_is_recent;
uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_m.c | 19 +++++++++++++++++++
src/target/cortex_m.h | 2 ++
2 files changed, 21 insertions(+)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-08-15 13:23:55
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commit 7e8ea96345d58ad4d1f6da1a2c952560fe78fc60
Author: Erhan Kurubas <erh...@es...>
Date: Tue Aug 2 01:38:09 2022 +0200
loaders/reset/espressif: replace the GPL-2.0-or-later license tag
Replace the FSF boilerplate with the SPDX tag.
Signed-off-by: Erhan Kurubas <erh...@es...>
Change-Id: Iddccae2bd8906a3587a2aa2684124356a340fc74
Reviewed-on: https://review.openocd.org/c/openocd/+/7105
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/contrib/loaders/reset/espressif/common.mk b/contrib/loaders/reset/espressif/common.mk
index 4623583aa..f77efe676 100644
--- a/contrib/loaders/reset/espressif/common.mk
+++ b/contrib/loaders/reset/espressif/common.mk
@@ -1,18 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# ESP32 Makefile to compile the SoC reset program
# Copyright (C) 2022 Espressif Systems Ltd.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>
# Pass V=1 to see the commands being executed by make
ifneq ("$(V)","1")
diff --git a/contrib/loaders/reset/espressif/esp32/Makefile b/contrib/loaders/reset/espressif/esp32/Makefile
index 3551b6a5e..a63178065 100644
--- a/contrib/loaders/reset/espressif/esp32/Makefile
+++ b/contrib/loaders/reset/espressif/esp32/Makefile
@@ -1,18 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# ESP32 Makefile to compile the SoC reset program
# Copyright (C) 2022 Espressif Systems Ltd.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>
# Prefix for ESP32 cross compilers (can include a directory path)
CROSS ?= xtensa-esp32-elf-
diff --git a/contrib/loaders/reset/espressif/esp32/esp32_cpu_reset_handler.S b/contrib/loaders/reset/espressif/esp32/esp32_cpu_reset_handler.S
index 113254556..506d41e85 100644
--- a/contrib/loaders/reset/espressif/esp32/esp32_cpu_reset_handler.S
+++ b/contrib/loaders/reset/espressif/esp32/esp32_cpu_reset_handler.S
@@ -1,19 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Reset stub used by esp32 target *
* Copyright (C) 2017 Espressif Systems Ltd. *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#define RTC_CNTL_RESET_STATE_REG 0x3ff48034
diff --git a/contrib/loaders/reset/espressif/esp32s3/Makefile b/contrib/loaders/reset/espressif/esp32s3/Makefile
index 4dab161fd..37d5f8281 100644
--- a/contrib/loaders/reset/espressif/esp32s3/Makefile
+++ b/contrib/loaders/reset/espressif/esp32s3/Makefile
@@ -1,18 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# ESP32 Makefile to compile the SoC reset program
# Copyright (C) 2022 Espressif Systems Ltd.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>
# Prefix for ESP32 cross compilers (can include a directory path)
CROSS ?= xtensa-esp32s3-elf-
diff --git a/contrib/loaders/reset/espressif/esp32s3/esp32s3_cpu_reset_handler.S b/contrib/loaders/reset/espressif/esp32s3/esp32s3_cpu_reset_handler.S
index e70ac9ca7..5fc635725 100644
--- a/contrib/loaders/reset/espressif/esp32s3/esp32s3_cpu_reset_handler.S
+++ b/contrib/loaders/reset/espressif/esp32s3/esp32s3_cpu_reset_handler.S
@@ -1,19 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Reset stub used by esp32s3 target *
* Copyright (C) 2020 Espressif Systems (Shanghai) Co. Ltd. *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#define RTC_CNTL_RESET_STATE_REG 0x60008038
-----------------------------------------------------------------------
Summary of changes:
contrib/loaders/reset/espressif/common.mk | 15 ++-------------
contrib/loaders/reset/espressif/esp32/Makefile | 15 ++-------------
.../reset/espressif/esp32/esp32_cpu_reset_handler.S | 15 ++-------------
contrib/loaders/reset/espressif/esp32s3/Makefile | 15 ++-------------
.../reset/espressif/esp32s3/esp32s3_cpu_reset_handler.S | 15 ++-------------
5 files changed, 10 insertions(+), 65 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-08-15 13:23:27
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
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from d9b2607ca094898d8d7180085a913e8a5b46ecac (commit)
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- Log -----------------------------------------------------------------
commit 48db36f436fe212fdda8d3fb7f79db43d9a2aa99
Author: Ian Thompson <ia...@ca...>
Date: Sun Jul 10 17:14:10 2022 -0700
gdb_server: custom target-specific GDB queries
Provide a customizable hook for handling target-specific GDB queries
Valgrind-clean, no new Clang analyzer warnings
Signed-off-by: Ian Thompson <ia...@ca...>
Change-Id: I684a259ed29f3651cbce668101cff421e522f79e
Reviewed-on: https://review.openocd.org/c/openocd/+/7082
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 3052d0a0e..1e50b43f3 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -2965,6 +2965,11 @@ static int gdb_query_packet(struct connection *connection,
gdb_connection->noack_mode = 1;
gdb_put_packet(connection, "OK", 2);
return ERROR_OK;
+ } else if (target->type->gdb_query_custom) {
+ char *buffer = NULL;
+ int ret = target->type->gdb_query_custom(target, packet, &buffer);
+ gdb_put_packet(connection, buffer, strlen(buffer));
+ return ret;
}
gdb_put_packet(connection, "", 0);
diff --git a/src/target/target_type.h b/src/target/target_type.h
index 1933e1cc7..947080381 100644
--- a/src/target/target_type.h
+++ b/src/target/target_type.h
@@ -286,6 +286,15 @@ struct target_type {
*/
int (*gdb_fileio_end)(struct target *target, int retcode, int fileio_errno, bool ctrl_c);
+ /* Parse target-specific GDB query commands.
+ * The string pointer "response_p" is always assigned by the called function
+ * to a pointer to a NULL-terminated string, even when the function returns
+ * an error. The string memory is not freed by the caller, so this function
+ * must pay attention for possible memory leaks if the string memory is
+ * dynamically allocated.
+ */
+ int (*gdb_query_custom)(struct target *target, const char *packet, char **response_p);
+
/* do target profiling
*/
int (*profiling)(struct target *target, uint32_t *samples,
-----------------------------------------------------------------------
Summary of changes:
src/server/gdb_server.c | 5 +++++
src/target/target_type.h | 9 +++++++++
2 files changed, 14 insertions(+)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-08-15 13:23:20
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
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- Log -----------------------------------------------------------------
commit d9b2607ca094898d8d7180085a913e8a5b46ecac
Author: Ian Thompson <ia...@ca...>
Date: Mon Aug 1 15:47:52 2022 -0700
gdb_server: support sparse register maps
Add additional error handling for targets where gaps may exist in reg_list[]
Signed-off-by: Ian Thompson <ia...@ca...>
Change-Id: I65232429e2de08f5d54eeca53aea0db8ce2b58af
Reviewed-on: https://review.openocd.org/c/openocd/+/7103
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 28833c9ce..3052d0a0e 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -1323,6 +1323,8 @@ static int gdb_set_registers_packet(struct connection *connection,
packet_p = packet;
for (i = 0; i < reg_list_size; i++) {
uint8_t *bin_buf;
+ if (!reg_list[i] || !reg_list[i]->exist || reg_list[i]->hidden)
+ continue;
int chars = (DIV_ROUND_UP(reg_list[i]->size, 8) * 2);
if (packet_p + chars > packet + packet_size)
@@ -1375,7 +1377,8 @@ static int gdb_get_register_packet(struct connection *connection,
if (retval != ERROR_OK)
return gdb_error(connection, retval);
- if (reg_list_size <= reg_num) {
+ if ((reg_list_size <= reg_num) || !reg_list[reg_num] ||
+ !reg_list[reg_num]->exist || reg_list[reg_num]->hidden) {
LOG_ERROR("gdb requested a non-existing register (reg_num=%d)", reg_num);
return ERROR_SERVER_REMOTE_CLOSED;
}
@@ -1437,7 +1440,8 @@ static int gdb_set_register_packet(struct connection *connection,
return gdb_error(connection, retval);
}
- if (reg_list_size <= reg_num) {
+ if ((reg_list_size <= reg_num) || !reg_list[reg_num] ||
+ !reg_list[reg_num]->exist || reg_list[reg_num]->hidden) {
LOG_ERROR("gdb requested a non-existing register (reg_num=%d)", reg_num);
free(bin_buf);
free(reg_list);
-----------------------------------------------------------------------
Summary of changes:
src/server/gdb_server.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-08-15 13:22:35
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
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via 0d56f379b55b24959c88e705a83e1fbb826b75e7 (commit)
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- Log -----------------------------------------------------------------
commit e282d208321ed1661efa894b583cf8922d67ba3f
Author: Antonio Borneo <bor...@gm...>
Date: Mon May 30 15:32:24 2022 +0200
openocd: prevent target polling during 'init'
The command 'init' causes the execution of few lower level
commands, e.g. 'target init', and switches from command mode
COMMAND_CONFIG to COMMAND_EXEC, with an intermediate switch back
to mode COMMAND_CONFIG.
A timed target polling can occur during the execution of 'init'
and the target's status can trigger the execution of some events.
E.g. if a target has been left halted by a previous execution of
OpenOCD, the first poll will find the target halted, calling the
corresponding 'halted' event.
The event handler can use commands that can only be executed in
mode COMMAND_EXEC. If the poll happens while OpenOCD is in mode
COMMAND_CONFIG, the triggered handler will fail.
Prevent the target polling to operate during the execution of the
'init' command.
Change-Id: Ia435a5d2039be9b247e2336616dab53ed5d983ac
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7007
Reviewed-by: Tomas Vanek <va...@fb...>
Tested-by: jenkins
diff --git a/src/openocd.c b/src/openocd.c
index 43c852305..b65d47152 100644
--- a/src/openocd.c
+++ b/src/openocd.c
@@ -119,6 +119,8 @@ COMMAND_HANDLER(handle_init_command)
initialized = 1;
+ bool save_poll_mask = jtag_poll_mask();
+
retval = command_run_line(CMD_CTX, "target init");
if (retval != ERROR_OK)
return ERROR_FAIL;
@@ -166,6 +168,8 @@ COMMAND_HANDLER(handle_init_command)
if (command_run_line(CMD_CTX, "tpiu init") != ERROR_OK)
return ERROR_FAIL;
+ jtag_poll_unmask(save_poll_mask);
+
/* initialize telnet subsystem */
gdb_target_add_all(all_targets);
commit 0d56f379b55b24959c88e705a83e1fbb826b75e7
Author: Antonio Borneo <bor...@gm...>
Date: Mon May 30 22:49:12 2022 +0200
target: add API to temporarily mask target polling
The same flag 'jtag_poll' is currently used as local data for the
command 'poll' and to temporarily mask the target polling.
This can cause unexpected behavior if the command 'poll' is
executed while polling is temporarily masked.
Add a new flag 'jtag_poll_en' to hold the temporarily mask
condition and keep 'jtag_poll' for the 'poll' command only.
While there, change the initial assignment of 'jtag_poll' using
the proper boolean value.
Change-Id: I18dcf7c65b07aefadf046caaa2fcd2d74fa6fbae
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7009
Reviewed-by: Tomas Vanek <va...@fb...>
Tested-by: jenkins
diff --git a/src/flash/nor/psoc4.c b/src/flash/nor/psoc4.c
index 4b5aa55cf..1bdd64aae 100644
--- a/src/flash/nor/psoc4.c
+++ b/src/flash/nor/psoc4.c
@@ -651,8 +651,8 @@ static int psoc4_write(struct flash_bank *bank, const uint8_t *buffer,
if (row_offset)
memset(row_buffer, bank->default_padded_value, row_offset);
- bool save_poll = jtag_poll_get_enabled();
- jtag_poll_set_enabled(false);
+ /* Mask automatic polling triggered by execution of halted events */
+ bool save_poll_mask = jtag_poll_mask();
while (count) {
uint32_t chunk_size = psoc4_info->row_size - row_offset;
@@ -693,7 +693,7 @@ static int psoc4_write(struct flash_bank *bank, const uint8_t *buffer,
}
cleanup:
- jtag_poll_set_enabled(save_poll);
+ jtag_poll_unmask(save_poll_mask);
free(sysrq_buffer);
return retval;
diff --git a/src/helper/command.c b/src/helper/command.c
index 43fe033f7..52f9eb6bf 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -702,14 +702,12 @@ static int jim_capture(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
* This is necessary in order to avoid accidentally getting a non-empty
* string for tcl fn's.
*/
- bool save_poll = jtag_poll_get_enabled();
-
- jtag_poll_set_enabled(false);
+ bool save_poll_mask = jtag_poll_mask();
const char *str = Jim_GetString(argv[1], NULL);
int retcode = Jim_Eval_Named(interp, str, __THIS__FILE__, __LINE__);
- jtag_poll_set_enabled(save_poll);
+ jtag_poll_unmask(save_poll_mask);
command_log_capture_finish(state);
diff --git a/src/jtag/core.c b/src/jtag/core.c
index 27c7b3de4..806ee8926 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -136,14 +136,19 @@ int jtag_error_clear(void)
/************/
-static bool jtag_poll = 1;
+static bool jtag_poll = true;
+static bool jtag_poll_en = true;
bool is_jtag_poll_safe(void)
{
/* Polling can be disabled explicitly with set_enabled(false).
+ * It can also be masked with mask().
* It is also implicitly disabled while TRST is active and
* while SRST is gating the JTAG clock.
*/
+ if (!jtag_poll_en)
+ return false;
+
if (!transport_is_jtag())
return jtag_poll;
@@ -162,6 +167,18 @@ void jtag_poll_set_enabled(bool value)
jtag_poll = value;
}
+bool jtag_poll_mask(void)
+{
+ bool retval = jtag_poll_en;
+ jtag_poll_en = false;
+ return retval;
+}
+
+void jtag_poll_unmask(bool saved)
+{
+ jtag_poll_en = saved;
+}
+
/************/
struct jtag_tap *jtag_all_taps(void)
diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h
index 18e09ced3..4f94e9913 100644
--- a/src/jtag/jtag.h
+++ b/src/jtag/jtag.h
@@ -587,6 +587,19 @@ bool jtag_poll_get_enabled(void);
*/
void jtag_poll_set_enabled(bool value);
+/**
+ * Mask (disable) polling and return the current mask status that should be
+ * feed to jtag_poll_unmask() to restore it.
+ * Multiple nested calls to jtag_poll_mask() are allowed, each balanced with
+ * its call to jtag_poll_unmask().
+ */
+bool jtag_poll_mask(void);
+
+/**
+ * Restore saved mask for polling.
+ */
+void jtag_poll_unmask(bool saved);
+
#include <jtag/minidriver.h>
int jim_jtag_newtap(Jim_Interp *interp, int argc, Jim_Obj *const *argv);
diff --git a/src/target/target.c b/src/target/target.c
index 553400df6..10a25efde 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -654,10 +654,10 @@ int target_resume(struct target *target, int current, target_addr_t address,
* Disable polling during resume() to guarantee the execution of handlers
* in the correct order.
*/
- bool save_poll = jtag_poll_get_enabled();
- jtag_poll_set_enabled(false);
+ bool save_poll_mask = jtag_poll_mask();
retval = target->type->resume(target, current, address, handle_breakpoints, debug_execution);
- jtag_poll_set_enabled(save_poll);
+ jtag_poll_unmask(save_poll_mask);
+
if (retval != ERROR_OK)
return retval;
@@ -685,14 +685,12 @@ static int target_process_reset(struct command_invocation *cmd, enum target_rese
* more predictable, i.e. dr/irscan & pathmove in events will
* not have JTAG operations injected into the middle of a sequence.
*/
- bool save_poll = jtag_poll_get_enabled();
-
- jtag_poll_set_enabled(false);
+ bool save_poll_mask = jtag_poll_mask();
sprintf(buf, "ocd_process_reset %s", n->name);
retval = Jim_Eval(cmd->ctx->interp, buf);
- jtag_poll_set_enabled(save_poll);
+ jtag_poll_unmask(save_poll_mask);
if (retval != JIM_OK) {
Jim_MakeErrorMessage(cmd->ctx->interp);
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/psoc4.c | 6 +++---
src/helper/command.c | 6 ++----
src/jtag/core.c | 19 ++++++++++++++++++-
src/jtag/jtag.h | 13 +++++++++++++
src/openocd.c | 4 ++++
src/target/target.c | 12 +++++-------
6 files changed, 45 insertions(+), 15 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-08-15 13:22:07
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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commit c3138e2d805b94b81ba10bc7fcec47689704f60e
Author: Ian Thompson <ia...@ca...>
Date: Mon Aug 1 15:22:32 2022 -0700
gdb_server: add "not supported" Z-packet reply
GDB remote serial protocol specifies breakpoint/watchpoint packet
responses can be an empty string to indicate the specified breakpoint
type is not supported. Add support for this response alongside existing
"OK", "E NN" replies.
Signed-off-by: Ian Thompson <ia...@ca...>
Change-Id: Iaf6280e4c936eb95a92bc80cc74d451ebb328dc3
Reviewed-on: https://review.openocd.org/c/openocd/+/7102
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 2e6c7304d..28833c9ce 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -1770,7 +1770,10 @@ static int gdb_breakpoint_watchpoint_packet(struct connection *connection,
case 1:
if (packet[0] == 'Z') {
retval = breakpoint_add(target, address, size, bp_type);
- if (retval != ERROR_OK) {
+ if (retval == ERROR_NOT_IMPLEMENTED) {
+ /* Send empty reply to report that breakpoints of this type are not supported */
+ gdb_put_packet(connection, "", 0);
+ } else if (retval != ERROR_OK) {
retval = gdb_error(connection, retval);
if (retval != ERROR_OK)
return retval;
@@ -1787,7 +1790,10 @@ static int gdb_breakpoint_watchpoint_packet(struct connection *connection,
{
if (packet[0] == 'Z') {
retval = watchpoint_add(target, address, size, wp_type, 0, 0xffffffffu);
- if (retval != ERROR_OK) {
+ if (retval == ERROR_NOT_IMPLEMENTED) {
+ /* Send empty reply to report that watchpoints of this type are not supported */
+ gdb_put_packet(connection, "", 0);
+ } else if (retval != ERROR_OK) {
retval = gdb_error(connection, retval);
if (retval != ERROR_OK)
return retval;
-----------------------------------------------------------------------
Summary of changes:
src/server/gdb_server.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2022-08-15 13:20:15
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 9903203d73c9243c327db9dc0d726491bb625d41
Author: Erhan Kurubas <erh...@es...>
Date: Thu May 26 22:43:41 2022 +0200
adapter: run at default speed when clock speed not specified
Signed-off-by: Erhan Kurubas <erh...@es...>
Change-Id: I8d2db4a1f618790907265a45d28a212551800b6c
Reviewed-on: https://review.openocd.org/c/openocd/+/7004
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/jtag/adapter.c b/src/jtag/adapter.c
index 14452d42f..519505dc3 100644
--- a/src/jtag/adapter.c
+++ b/src/jtag/adapter.c
@@ -36,6 +36,8 @@ enum adapter_clk_mode {
CLOCK_MODE_RCLK
};
+#define DEFAULT_CLOCK_SPEED_KHZ 100U
+
/**
* Adapter configuration
*/
@@ -70,6 +72,18 @@ int adapter_init(struct command_context *cmd_ctx)
}
int retval;
+
+ if (adapter_config.clock_mode == CLOCK_MODE_UNSELECTED) {
+ LOG_WARNING("An adapter speed is not selected in the init scripts."
+ " OpenOCD will try to run the adapter at the low speed (%d kHz)",
+ DEFAULT_CLOCK_SPEED_KHZ);
+ LOG_WARNING("To remove this warnings and achieve reasonable communication speed with the target,"
+ " set \"adapter speed\" or \"jtag_rclk\" in the init scripts.");
+ retval = adapter_config_khz(DEFAULT_CLOCK_SPEED_KHZ);
+ if (retval != ERROR_OK)
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
retval = adapter_driver->init();
if (retval != ERROR_OK)
return retval;
@@ -80,12 +94,6 @@ int adapter_init(struct command_context *cmd_ctx)
return ERROR_OK;
}
- if (adapter_config.clock_mode == CLOCK_MODE_UNSELECTED) {
- LOG_ERROR("An adapter speed is not selected in the init script."
- " Insert a call to \"adapter speed\" or \"jtag_rclk\" to proceed.");
- return ERROR_JTAG_INIT_FAILED;
- }
-
int requested_khz = adapter_get_speed_khz();
int actual_khz = requested_khz;
int speed_var = 0;
-----------------------------------------------------------------------
Summary of changes:
src/jtag/adapter.c | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
hooks/post-receive
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From: OpenOCD-Gerrit <ope...@us...> - 2022-08-15 13:19:48
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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- Log -----------------------------------------------------------------
commit 6d6207a8d3970beac73840a184af79d8dbeb1fbf
Author: Asier Llano <al...@hu...>
Date: Thu Jul 21 12:27:11 2022 +0200
rtos: Support for "none" rtos
After a certain RTOS has been configured there is no mechanism
to go back to no RTOS support. It may be useful for debugging
purposes. With the provided modification, the "none" option
of RTOS is provided as a valid option.
It has been tested in two different board (Cortex M4 and Cortex M33).
Documentation has also been updated.
Signed-off-by: Asier Llano <al...@hu...>
Change-Id: I602210bff31ccadd41c41e9454c52b5fffa1671e
Reviewed-on: https://review.openocd.org/c/openocd/+/7092
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 1d63b20b7..995861d18 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5149,7 +5149,7 @@ The value should normally correspond to a static mapping for the
@anchor{rtostype}
@item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
-@var{rtos_type} can be one of @option{auto}, @option{eCos},
+@var{rtos_type} can be one of @option{auto}, @option{none}, @option{eCos},
@option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
@option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx},
@option{RIOT}, @option{Zephyr}
@@ -11848,6 +11848,11 @@ Currently supported rtos's include:
@item @option{Zephyr}
@end itemize
+At any time, it's possible to drop the selected RTOS using:
+@example
+$_TARGETNAME configure -rtos none
+@end example
+
Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
index 013080bb0..3e43e828d 100644
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@@ -129,6 +129,9 @@ int rtos_create(struct jim_getopt_info *goi, struct target *target)
if (e != JIM_OK)
return e;
+ if (strcmp(cp, "none") == 0)
+ return JIM_OK;
+
if (strcmp(cp, "auto") == 0) {
/* Auto detect tries to look up all symbols for each RTOS,
* and runs the RTOS driver's _detect() function when GDB
@@ -148,7 +151,7 @@ int rtos_create(struct jim_getopt_info *goi, struct target *target)
res = Jim_GetResult(goi->interp);
for (x = 0; rtos_types[x]; x++)
Jim_AppendStrings(goi->interp, res, rtos_types[x]->name, ", ", NULL);
- Jim_AppendStrings(goi->interp, res, " or auto", NULL);
+ Jim_AppendStrings(goi->interp, res, ", auto or none", NULL);
return JIM_ERR;
}
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 7 ++++++-
src/rtos/rtos.c | 5 ++++-
2 files changed, 10 insertions(+), 2 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2022-08-15 13:19:01
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 81aa5fd6b477cb03b718625a48e50099fc2ae0f2
Author: Tim Newsome <ti...@si...>
Date: Mon Jul 18 09:20:22 2022 -0700
target/riscv: Update debug_defines.h.
This one doesn't have the license in there, which means now it's
acceptable to GPLv2 again.
See https://github.com/riscv/riscv-openocd/pull/711
Change-Id: I8ba27801172ffa955470d2627fa656cad282ee99
Signed-off-by: Tim Newsome <ti...@si...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7087
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/riscv/debug_defines.h b/src/target/riscv/debug_defines.h
index 5c9eef4ea..8113d4766 100644
--- a/src/target/riscv/debug_defines.h
+++ b/src/target/riscv/debug_defines.h
@@ -1,22 +1,21 @@
/*
* This file is auto-generated by running 'make debug_defines.h' in
- * https://github.com/riscv/riscv-debug-spec/ (3dfe4f7)
- * License: Creative Commons Attribution 4.0 International Public License (CC BY 4.0)
+ * https://github.com/riscv/riscv-debug-spec/ (d749752)
*/
#define DTM_IDCODE 0x01
/*
* Identifies the release version of this part.
*/
-#define DTM_IDCODE_VERSION_OFFSET 28
+#define DTM_IDCODE_VERSION_OFFSET 0x1c
#define DTM_IDCODE_VERSION_LENGTH 4
-#define DTM_IDCODE_VERSION (0xfU << DTM_IDCODE_VERSION_OFFSET)
+#define DTM_IDCODE_VERSION 0xf0000000U
/*
* Identifies the designer's part number of this part.
*/
-#define DTM_IDCODE_PARTNUMBER_OFFSET 12
-#define DTM_IDCODE_PARTNUMBER_LENGTH 16
-#define DTM_IDCODE_PARTNUMBER (0xffffU << DTM_IDCODE_PARTNUMBER_OFFSET)
+#define DTM_IDCODE_PARTNUMBER_OFFSET 0xc
+#define DTM_IDCODE_PARTNUMBER_LENGTH 0x10
+#define DTM_IDCODE_PARTNUMBER 0xffff000
/*
* Identifies the designer/manufacturer of this part. Bits 6:0 must be
* bits 6:0 of the designer/manufacturer's Identification Code as
@@ -25,11 +24,11 @@
* Identification Code.
*/
#define DTM_IDCODE_MANUFID_OFFSET 1
-#define DTM_IDCODE_MANUFID_LENGTH 11
-#define DTM_IDCODE_MANUFID (0x7ffU << DTM_IDCODE_MANUFID_OFFSET)
+#define DTM_IDCODE_MANUFID_LENGTH 0xb
+#define DTM_IDCODE_MANUFID 0xffe
#define DTM_IDCODE_1_OFFSET 0
#define DTM_IDCODE_1_LENGTH 1
-#define DTM_IDCODE_1 (0x1U << DTM_IDCODE_1_OFFSET)
+#define DTM_IDCODE_1 1
#define DTM_DTMCS 0x10
/*
* Writing 1 to this bit does a hard reset of the DTM,
@@ -40,16 +39,16 @@
* complete (e.g. a reset condition caused an inflight DMI transaction to
* be cancelled).
*/
-#define DTM_DTMCS_DMIHARDRESET_OFFSET 17
+#define DTM_DTMCS_DMIHARDRESET_OFFSET 0x11
#define DTM_DTMCS_DMIHARDRESET_LENGTH 1
-#define DTM_DTMCS_DMIHARDRESET (0x1U << DTM_DTMCS_DMIHARDRESET_OFFSET)
+#define DTM_DTMCS_DMIHARDRESET 0x20000
/*
* Writing 1 to this bit clears the sticky error state, but does
* not affect outstanding DMI transactions.
*/
-#define DTM_DTMCS_DMIRESET_OFFSET 16
+#define DTM_DTMCS_DMIRESET_OFFSET 0x10
#define DTM_DTMCS_DMIRESET_LENGTH 1
-#define DTM_DTMCS_DMIRESET (0x1U << DTM_DTMCS_DMIRESET_OFFSET)
+#define DTM_DTMCS_DMIRESET 0x10000
/*
* This is a hint to the debugger of the minimum number of
* cycles a debugger should spend in
@@ -65,76 +64,89 @@
*
* And so on.
*/
-#define DTM_DTMCS_IDLE_OFFSET 12
+#define DTM_DTMCS_IDLE_OFFSET 0xc
#define DTM_DTMCS_IDLE_LENGTH 3
-#define DTM_DTMCS_IDLE (0x7U << DTM_DTMCS_IDLE_OFFSET)
+#define DTM_DTMCS_IDLE 0x7000
/*
- * 0: No error.
- *
- * 1: Reserved. Interpret the same as 2.
- *
- * 2: An operation failed (resulted in \FdtmDmiOp of 2).
- *
- * 3: An operation was attempted while a DMI access was still in
- * progress (resulted in \FdtmDmiOp of 3).
+ * Read-only alias of \FdtmDmiOp.
*/
-#define DTM_DTMCS_DMISTAT_OFFSET 10
+#define DTM_DTMCS_DMISTAT_OFFSET 0xa
#define DTM_DTMCS_DMISTAT_LENGTH 2
-#define DTM_DTMCS_DMISTAT (0x3U << DTM_DTMCS_DMISTAT_OFFSET)
+#define DTM_DTMCS_DMISTAT 0xc00
/*
* The size of \FdmSbaddressZeroAddress in \RdtmDmi.
*/
#define DTM_DTMCS_ABITS_OFFSET 4
#define DTM_DTMCS_ABITS_LENGTH 6
-#define DTM_DTMCS_ABITS (0x3fU << DTM_DTMCS_ABITS_OFFSET)
-/*
- * 0: Version described in spec version 0.11.
- *
- * 1: Version described in spec versions 0.13 and 1.0.
- *
- * 15: Version not described in any available version of this spec.
- */
+#define DTM_DTMCS_ABITS 0x3f0
#define DTM_DTMCS_VERSION_OFFSET 0
#define DTM_DTMCS_VERSION_LENGTH 4
-#define DTM_DTMCS_VERSION (0xfU << DTM_DTMCS_VERSION_OFFSET)
+#define DTM_DTMCS_VERSION 0xf
+/*
+ * 0.11: Version described in spec version 0.11.
+ */
+#define DTM_DTMCS_VERSION_0_11 0
+/*
+ * 1.0: Version described in spec versions 0.13 and 1.0.
+ */
+#define DTM_DTMCS_VERSION_1_0 1
+/*
+ * custom: Version not described in any available version of this spec.
+ */
+#define DTM_DTMCS_VERSION_CUSTOM 15
#define DTM_DMI 0x11
/*
* Address used for DMI access. In Update-DR this value is used
* to access the DM over the DMI.
*/
-#define DTM_DMI_ADDRESS_OFFSET 34
-#define DTM_DMI_ADDRESS_LENGTH abits
-#define DTM_DMI_ADDRESS (((1L << abits) - 1) << DTM_DMI_ADDRESS_OFFSET)
+#define DTM_DMI_ADDRESS_OFFSET 0x22
+#define DTM_DMI_ADDRESS_LENGTH(abits) abits
+#define DTM_DMI_ADDRESS(abits) ((0x400000000ULL * (1ULL<<abits)) + -0x400000000ULL)
/*
* The data to send to the DM over the DMI during Update-DR, and
* the data returned from the DM as a result of the previous operation.
*/
#define DTM_DMI_DATA_OFFSET 2
-#define DTM_DMI_DATA_LENGTH 32
-#define DTM_DMI_DATA (0xffffffffULL << DTM_DMI_DATA_OFFSET)
+#define DTM_DMI_DATA_LENGTH 0x20
+#define DTM_DMI_DATA 0x3fffffffcULL
/*
* When the debugger writes this field, it has the following meaning:
- *
- * 0: Ignore \FdmSbdataZeroData and \FdmSbaddressZeroAddress. (nop)
+ */
+#define DTM_DMI_OP_OFFSET 0
+#define DTM_DMI_OP_LENGTH 2
+#define DTM_DMI_OP 3
+/*
+ * nop: Ignore \FdmSbdataZeroData and \FdmSbaddressZeroAddress.
*
* Don't send anything over the DMI during Update-DR.
* This operation should never result in a busy or error response.
* The address and data reported in the following Capture-DR
* are undefined.
- *
- * 1: Read from \FdmSbaddressZeroAddress. (read)
- *
- * 2: Write \FdmSbdataZeroData to \FdmSbaddressZeroAddress. (write)
- *
- * 3: Reserved.
- *
+ */
+#define DTM_DMI_OP_NOP 0
+/*
+ * read: Read from \FdmSbaddressZeroAddress.
+ */
+#define DTM_DMI_OP_READ 1
+/*
+ * write: Write \FdmSbdataZeroData to \FdmSbaddressZeroAddress.
+ */
+#define DTM_DMI_OP_WRITE 2
+/*
+ * reserved: Reserved.
+ */
+/*
* When the debugger reads this field, it means the following:
- *
- * 0: The previous operation completed successfully.
- *
- * 1: Reserved.
- *
- * 2: A previous operation failed. The data scanned into \RdtmDmi in
+ */
+/*
+ * success: The previous operation completed successfully.
+ */
+#define DTM_DMI_OP_SUCCESS 0
+/*
+ * reserved: Reserved.
+ */
+/*
+ * failed: A previous operation failed. The data scanned into \RdtmDmi in
* this access will be ignored. This status is sticky and can be
* cleared by writing \FdtmDtmcsDmireset in \RdtmDtmcs.
*
@@ -142,8 +154,10 @@
* There are no specified cases in which the DM would
* respond with an error, and DMI is not required to support
* returning errors.
- *
- * 3: An operation was attempted while a DMI request is still in
+ */
+#define DTM_DMI_OP_FAILED 2
+/*
+ * busy: An operation was attempted while a DMI request is still in
* progress. The data scanned into \RdtmDmi in this access will be
* ignored. This status is sticky and can be cleared by writing
* \FdtmDtmcsDmireset in \RdtmDtmcs. If a debugger sees this status, it
@@ -151,160 +165,212 @@
* Capture-DR. The simplest way to do that is to add extra transitions
* in Run-Test/Idle.
*/
-#define DTM_DMI_OP_OFFSET 0
-#define DTM_DMI_OP_LENGTH 2
-#define DTM_DMI_OP (0x3ULL << DTM_DMI_OP_OFFSET)
+#define DTM_DMI_OP_BUSY 3
#define CSR_DCSR 0x7b0
+#define CSR_DCSR_DEBUGVER_OFFSET 0x1c
+#define CSR_DCSR_DEBUGVER_LENGTH 4
+#define CSR_DCSR_DEBUGVER 0xf0000000U
/*
- * 0: There is no debug support.
- *
- * 4: Debug support exists as it is described in this document.
- *
- * 15: There is debug support, but it does not conform to any
- * available version of this spec.
+ * none: There is no debug support.
*/
-#define CSR_DCSR_DEBUGVER_OFFSET 28
-#define CSR_DCSR_DEBUGVER_LENGTH 4
-#define CSR_DCSR_DEBUGVER (0xfU << CSR_DCSR_DEBUGVER_OFFSET)
+#define CSR_DCSR_DEBUGVER_NONE 0
/*
- * 0: {\tt ebreak} instructions in VS-mode behave as described in the
- * Privileged Spec.
- *
- * 1: {\tt ebreak} instructions in VS-mode enter Debug Mode.
- *
- * This bit is hardwired to 0 if the hart does not support virtualization mode.
+ * 1.0: Debug support exists as it is described in this document.
+ */
+#define CSR_DCSR_DEBUGVER_1_0 4
+/*
+ * custom: There is debug support, but it does not conform to any
+ * available version of this spec.
*/
-#define CSR_DCSR_EBREAKVS_OFFSET 17
+#define CSR_DCSR_DEBUGVER_CUSTOM 15
+#define CSR_DCSR_EBREAKVS_OFFSET 0x11
#define CSR_DCSR_EBREAKVS_LENGTH 1
-#define CSR_DCSR_EBREAKVS (0x1U << CSR_DCSR_EBREAKVS_OFFSET)
+#define CSR_DCSR_EBREAKVS 0x20000
/*
- * 0: {\tt ebreak} instructions in VU-mode behave as described in the
+ * exception: {\tt ebreak} instructions in VS-mode behave as described in the
* Privileged Spec.
- *
- * 1: {\tt ebreak} instructions in VU-mode enter Debug Mode.
- *
+ */
+#define CSR_DCSR_EBREAKVS_EXCEPTION 0
+/*
+ * debug mode: {\tt ebreak} instructions in VS-mode enter Debug Mode.
+ */
+#define CSR_DCSR_EBREAKVS_DEBUG_MODE 1
+/*
* This bit is hardwired to 0 if the hart does not support virtualization mode.
*/
-#define CSR_DCSR_EBREAKVU_OFFSET 16
+#define CSR_DCSR_EBREAKVU_OFFSET 0x10
#define CSR_DCSR_EBREAKVU_LENGTH 1
-#define CSR_DCSR_EBREAKVU (0x1U << CSR_DCSR_EBREAKVU_OFFSET)
+#define CSR_DCSR_EBREAKVU 0x10000
/*
- * 0: {\tt ebreak} instructions in M-mode behave as described in the
+ * exception: {\tt ebreak} instructions in VU-mode behave as described in the
* Privileged Spec.
- *
- * 1: {\tt ebreak} instructions in M-mode enter Debug Mode.
*/
-#define CSR_DCSR_EBREAKM_OFFSET 15
+#define CSR_DCSR_EBREAKVU_EXCEPTION 0
+/*
+ * debug mode: {\tt ebreak} instructions in VU-mode enter Debug Mode.
+ */
+#define CSR_DCSR_EBREAKVU_DEBUG_MODE 1
+/*
+ * This bit is hardwired to 0 if the hart does not support virtualization mode.
+ */
+#define CSR_DCSR_EBREAKM_OFFSET 0xf
#define CSR_DCSR_EBREAKM_LENGTH 1
-#define CSR_DCSR_EBREAKM (0x1U << CSR_DCSR_EBREAKM_OFFSET)
+#define CSR_DCSR_EBREAKM 0x8000
/*
- * 0: {\tt ebreak} instructions in S-mode behave as described in the
+ * exception: {\tt ebreak} instructions in M-mode behave as described in the
* Privileged Spec.
- *
- * 1: {\tt ebreak} instructions in S-mode enter Debug Mode.
- *
- * This bit is hardwired to 0 if the hart does not support S-mode.
*/
-#define CSR_DCSR_EBREAKS_OFFSET 13
+#define CSR_DCSR_EBREAKM_EXCEPTION 0
+/*
+ * debug mode: {\tt ebreak} instructions in M-mode enter Debug Mode.
+ */
+#define CSR_DCSR_EBREAKM_DEBUG_MODE 1
+#define CSR_DCSR_EBREAKS_OFFSET 0xd
#define CSR_DCSR_EBREAKS_LENGTH 1
-#define CSR_DCSR_EBREAKS (0x1U << CSR_DCSR_EBREAKS_OFFSET)
+#define CSR_DCSR_EBREAKS 0x2000
/*
- * 0: {\tt ebreak} instructions in U-mode behave as described in the
+ * exception: {\tt ebreak} instructions in S-mode behave as described in the
* Privileged Spec.
- *
- * 1: {\tt ebreak} instructions in U-mode enter Debug Mode.
- *
- * This bit is hardwired to 0 if the hart does not support U-mode.
*/
-#define CSR_DCSR_EBREAKU_OFFSET 12
+#define CSR_DCSR_EBREAKS_EXCEPTION 0
+/*
+ * debug mode: {\tt ebreak} instructions in S-mode enter Debug Mode.
+ */
+#define CSR_DCSR_EBREAKS_DEBUG_MODE 1
+/*
+ * This bit is hardwired to 0 if the hart does not support S-mode.
+ */
+#define CSR_DCSR_EBREAKU_OFFSET 0xc
#define CSR_DCSR_EBREAKU_LENGTH 1
-#define CSR_DCSR_EBREAKU (0x1U << CSR_DCSR_EBREAKU_OFFSET)
+#define CSR_DCSR_EBREAKU 0x1000
+/*
+ * exception: {\tt ebreak} instructions in U-mode behave as described in the
+ * Privileged Spec.
+ */
+#define CSR_DCSR_EBREAKU_EXCEPTION 0
+/*
+ * debug mode: {\tt ebreak} instructions in U-mode enter Debug Mode.
+ */
+#define CSR_DCSR_EBREAKU_DEBUG_MODE 1
+/*
+ * This bit is hardwired to 0 if the hart does not support U-mode.
+ */
+#define CSR_DCSR_STEPIE_OFFSET 0xb
+#define CSR_DCSR_STEPIE_LENGTH 1
+#define CSR_DCSR_STEPIE 0x800
+/*
+ * interrupts disabled: Interrupts (including NMI) are disabled during single stepping.
+ */
+#define CSR_DCSR_STEPIE_INTERRUPTS_DISABLED 0
+/*
+ * interrupts enabled: Interrupts (including NMI) are enabled during single stepping.
+ */
+#define CSR_DCSR_STEPIE_INTERRUPTS_ENABLED 1
/*
- * 0: Interrupts (including NMI) are disabled during single stepping.
- *
- * 1: Interrupts (including NMI) are enabled during single stepping.
- *
* Implementations may hard wire this bit to 0.
* In that case interrupt behavior can be emulated by the debugger.
*
* The debugger must not change the value of this bit while the hart
* is running.
*/
-#define CSR_DCSR_STEPIE_OFFSET 11
-#define CSR_DCSR_STEPIE_LENGTH 1
-#define CSR_DCSR_STEPIE (0x1U << CSR_DCSR_STEPIE_OFFSET)
+#define CSR_DCSR_STOPCOUNT_OFFSET 0xa
+#define CSR_DCSR_STOPCOUNT_LENGTH 1
+#define CSR_DCSR_STOPCOUNT 0x400
/*
- * 0: Increment counters as usual.
- *
- * 1: Don't increment any hart-local counters while in Debug Mode or
+ * normal: Increment counters as usual.
+ */
+#define CSR_DCSR_STOPCOUNT_NORMAL 0
+/*
+ * freeze: Don't increment any hart-local counters while in Debug Mode or
* on {\tt ebreak} instructions that cause entry into Debug Mode.
* These counters include the {\tt instret} CSR. On single-hart cores
* {\tt cycle} should be stopped, but on multi-hart cores it must keep
* incrementing.
- *
- * An implementation may hardwire this bit to 0 or 1.
*/
-#define CSR_DCSR_STOPCOUNT_OFFSET 10
-#define CSR_DCSR_STOPCOUNT_LENGTH 1
-#define CSR_DCSR_STOPCOUNT (0x1U << CSR_DCSR_STOPCOUNT_OFFSET)
+#define CSR_DCSR_STOPCOUNT_FREEZE 1
/*
- * 0: Increment timers as usual.
- *
- * 1: Don't increment any hart-local timers while in Debug Mode.
- *
* An implementation may hardwire this bit to 0 or 1.
*/
#define CSR_DCSR_STOPTIME_OFFSET 9
#define CSR_DCSR_STOPTIME_LENGTH 1
-#define CSR_DCSR_STOPTIME (0x1U << CSR_DCSR_STOPTIME_OFFSET)
+#define CSR_DCSR_STOPTIME 0x200
+/*
+ * normal: Increment \Rtime as usual.
+ */
+#define CSR_DCSR_STOPTIME_NORMAL 0
+/*
+ * freeze: Don't increment \Rtime while in Debug Mode. If all harts
+ * have \FcsrDcsrStoptime=1 and are in Debug Mode then \Rmtime
+ * is also allowed to stop incrementing.
+ */
+#define CSR_DCSR_STOPTIME_FREEZE 1
+/*
+ * An implementation may hardwire this bit to 0 or 1.
+ */
/*
* Explains why Debug Mode was entered.
*
* When there are multiple reasons to enter Debug Mode in a single
* cycle, hardware should set \FcsrDcsrCause to the cause with the highest
- * priority.
- *
- * 1: An {\tt ebreak} instruction was executed. (priority 3)
- *
- * 2: A Trigger Module trigger fired with action=0. (priority 4)
- *
- * 3: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq.
- * (priority 1)
- *
- * 4: The hart single stepped because \FcsrDcsrStep was set. (priority 0, lowest)
- *
- * 5: The hart halted directly out of reset due to \Fresethaltreq. It
- * is also acceptable to report 3 when this happens. (priority 2)
- *
- * 6: The hart halted because it's part of a halt group. (priority 5,
- * highest) Harts may report 3 for this cause instead.
- *
- * Other values are reserved for future use.
+ * priority. See table~\ref{tab:dcsrcausepriority} for priorities.
*/
#define CSR_DCSR_CAUSE_OFFSET 6
#define CSR_DCSR_CAUSE_LENGTH 3
-#define CSR_DCSR_CAUSE (0x7U << CSR_DCSR_CAUSE_OFFSET)
+#define CSR_DCSR_CAUSE 0x1c0
+/*
+ * ebreak: An {\tt ebreak} instruction was executed.
+ */
+#define CSR_DCSR_CAUSE_EBREAK 1
+/*
+ * trigger: A Trigger Module trigger fired with action=1.
+ */
+#define CSR_DCSR_CAUSE_TRIGGER 2
+/*
+ * haltreq: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq.
+ */
+#define CSR_DCSR_CAUSE_HALTREQ 3
+/*
+ * step: The hart single stepped because \FcsrDcsrStep was set.
+ */
+#define CSR_DCSR_CAUSE_STEP 4
+/*
+ * resethaltreq: The hart halted directly out of reset due to \Fresethaltreq. It
+ * is also acceptable to report 3 when this happens.
+ */
+#define CSR_DCSR_CAUSE_RESETHALTREQ 5
+/*
+ * group: The hart halted because it's part of a halt group.
+ * Harts may report 3 for this cause instead.
+ */
+#define CSR_DCSR_CAUSE_GROUP 6
+/*
+ * Other values are reserved for future use.
+ */
/*
* Extends the prv field with the virtualization mode the hart was operating
* in when Debug Mode was entered. The encoding is described in Table
- * \ref{tab:privlevel}.
+ * \ref{tab:privmode}.
* A debugger can change this value to change the hart's virtualization mode
* when exiting Debug Mode.
* This bit is hardwired to 0 on harts that do not support virtualization mode.
*/
#define CSR_DCSR_V_OFFSET 5
#define CSR_DCSR_V_LENGTH 1
-#define CSR_DCSR_V (0x1U << CSR_DCSR_V_OFFSET)
+#define CSR_DCSR_V 0x20
+#define CSR_DCSR_MPRVEN_OFFSET 4
+#define CSR_DCSR_MPRVEN_LENGTH 1
+#define CSR_DCSR_MPRVEN 0x10
+/*
+ * disabled: \FcsrMstatusMprv in \Rmstatus is ignored in Debug Mode.
+ */
+#define CSR_DCSR_MPRVEN_DISABLED 0
+/*
+ * enabled: \FcsrMstatusMprv in \Rmstatus takes effect in Debug Mode.
+ */
+#define CSR_DCSR_MPRVEN_ENABLED 1
/*
- * 0: \FcsrMstatusMprv in \Rmstatus is ignored in Debug Mode.
- *
- * 1: \FcsrMstatusMprv in \Rmstatus takes effect in Debug Mode.
- *
* Implementing this bit is optional. It may be tied to either 0 or 1.
*/
-#define CSR_DCSR_MPRVEN_OFFSET 4
-#define CSR_DCSR_MPRVEN_LENGTH 1
-#define CSR_DCSR_MPRVEN (0x1U << CSR_DCSR_MPRVEN_OFFSET)
/*
* When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart.
*
@@ -314,7 +380,7 @@
*/
#define CSR_DCSR_NMIP_OFFSET 3
#define CSR_DCSR_NMIP_LENGTH 1
-#define CSR_DCSR_NMIP (0x1U << CSR_DCSR_NMIP_OFFSET)
+#define CSR_DCSR_NMIP 8
/*
* When set and not in Debug Mode, the hart will only execute a single
* instruction and then enter Debug Mode. See Section~\ref{stepBit}
@@ -325,101 +391,130 @@
*/
#define CSR_DCSR_STEP_OFFSET 2
#define CSR_DCSR_STEP_LENGTH 1
-#define CSR_DCSR_STEP (0x1U << CSR_DCSR_STEP_OFFSET)
+#define CSR_DCSR_STEP 4
/*
- * Contains the privilege level the hart was operating in when Debug
+ * Contains the privilege mode the hart was operating in when Debug
* Mode was entered. The encoding is described in Table
- * \ref{tab:privlevel}. A debugger can change this value to change
- * the hart's privilege level when exiting Debug Mode.
+ * \ref{tab:privmode}. A debugger can change this value to change
+ * the hart's privilege mode when exiting Debug Mode.
*
- * Not all privilege levels are supported on all harts. If the
+ * Not all privilege modes are supported on all harts. If the
* encoding written is not supported or the debugger is not allowed to
- * change to it, the hart may change to any supported privilege level.
+ * change to it, the hart may change to any supported privilege mode.
*/
#define CSR_DCSR_PRV_OFFSET 0
#define CSR_DCSR_PRV_LENGTH 2
-#define CSR_DCSR_PRV (0x3U << CSR_DCSR_PRV_OFFSET)
+#define CSR_DCSR_PRV 3
#define CSR_DPC 0x7b1
#define CSR_DPC_DPC_OFFSET 0
-#define CSR_DPC_DPC_LENGTH DXLEN
-#define CSR_DPC_DPC (((1L << DXLEN) - 1) << CSR_DPC_DPC_OFFSET)
+#define CSR_DPC_DPC_LENGTH(DXLEN) DXLEN
+#define CSR_DPC_DPC(DXLEN) ((1ULL<<DXLEN) + -1)
#define CSR_DSCRATCH0 0x7b2
#define CSR_DSCRATCH1 0x7b3
#define CSR_TSELECT 0x7a0
#define CSR_TSELECT_INDEX_OFFSET 0
-#define CSR_TSELECT_INDEX_LENGTH XLEN
-#define CSR_TSELECT_INDEX (((1L << XLEN) - 1) << CSR_TSELECT_INDEX_OFFSET)
+#define CSR_TSELECT_INDEX_LENGTH(XLEN) XLEN
+#define CSR_TSELECT_INDEX(XLEN) ((1ULL<<XLEN) + -1)
#define CSR_TDATA1 0x7a1
+#define CSR_TDATA1_TYPE_OFFSET(XLEN) (XLEN + -4)
+#define CSR_TDATA1_TYPE_LENGTH 4
+#define CSR_TDATA1_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4)))
/*
- * 0: There is no trigger at this \RcsrTselect.
- *
- * 1: The trigger is a legacy SiFive address match trigger. These
+ * none: There is no trigger at this \RcsrTselect.
+ */
+#define CSR_TDATA1_TYPE_NONE 0
+/*
+ * legacy: The trigger is a legacy SiFive address match trigger. These
* should not be implemented and aren't further documented here.
- *
- * 2: The trigger is an address/data match trigger. The remaining bits
+ */
+#define CSR_TDATA1_TYPE_LEGACY 1
+/*
+ * mcontrol: The trigger is an address/data match trigger. The remaining bits
* in this register act as described in \RcsrMcontrol.
- *
- * 3: The trigger is an instruction count trigger. The remaining bits
+ */
+#define CSR_TDATA1_TYPE_MCONTROL 2
+/*
+ * icount: The trigger is an instruction count trigger. The remaining bits
* in this register act as described in \RcsrIcount.
- *
- * 4: The trigger is an interrupt trigger. The remaining bits
+ */
+#define CSR_TDATA1_TYPE_ICOUNT 3
+/*
+ * itrigger: The trigger is an interrupt trigger. The remaining bits
* in this register act as described in \RcsrItrigger.
- *
- * 5: The trigger is an exception trigger. The remaining bits
+ */
+#define CSR_TDATA1_TYPE_ITRIGGER 4
+/*
+ * etrigger: The trigger is an exception trigger. The remaining bits
* in this register act as described in \RcsrEtrigger.
- *
- * 6: The trigger is an address/data match trigger. The remaining bits
+ */
+#define CSR_TDATA1_TYPE_ETRIGGER 5
+/*
+ * mcontrol6: The trigger is an address/data match trigger. The remaining bits
* in this register act as described in \RcsrMcontrolSix. This is similar
* to a type 2 trigger, but provides additional functionality and
* should be used instead of type 2 in newer implementations.
- *
- * 7: The trigger is a trigger source external to the TM. The
+ */
+#define CSR_TDATA1_TYPE_MCONTROL6 6
+/*
+ * tmexttrigger: The trigger is a trigger source external to the TM. The
* remaining bits in this register act as described in \RcsrTmexttrigger.
- *
- * 12--14: These trigger types are available for non-standard use.
- *
- * 15: This trigger exists (so enumeration shouldn't terminate), but
- * is not currently available.
- *
+ */
+#define CSR_TDATA1_TYPE_TMEXTTRIGGER 7
+/*
+ * custom: These trigger types are available for non-standard use.
+ */
+#define CSR_TDATA1_TYPE_CUSTOM_LOW 12
+#define CSR_TDATA1_TYPE_CUSTOM_HIGH 14
+/*
+ * disabled: This trigger is disabled. In this state, \RcsrTdataTwo and
+ * \RcsrTdataThree can be written with any value that is supported for
+ * any of the types this trigger implements. The remaining bits in this
+ * register are ignored.
+ */
+#define CSR_TDATA1_TYPE_DISABLED 15
+/*
* Other values are reserved for future use.
*/
-#define CSR_TDATA1_TYPE_OFFSET (XLEN-4)
-#define CSR_TDATA1_TYPE_LENGTH 4
-#define CSR_TDATA1_TYPE (0xfULL << CSR_TDATA1_TYPE_OFFSET)
/*
* If \FcsrTdataOneType is 0, then this bit is hard-wired to 0.
- *
- * 0: Both Debug and M-mode can write the {\tt tdata} registers at the
+ */
+#define CSR_TDATA1_DMODE_OFFSET(XLEN) (XLEN + -5)
+#define CSR_TDATA1_DMODE_LENGTH 1
+#define CSR_TDATA1_DMODE(XLEN) (1ULL<<(XLEN + -5))
+/*
+ * both: Both Debug and M-mode can write the {\tt tdata} registers at the
* selected \RcsrTselect.
- *
- * 1: Only Debug Mode can write the {\tt tdata} registers at the
+ */
+#define CSR_TDATA1_DMODE_BOTH 0
+/*
+ * dmode: Only Debug Mode can write the {\tt tdata} registers at the
* selected \RcsrTselect. Writes from other modes are ignored.
- *
+ */
+#define CSR_TDATA1_DMODE_DMODE 1
+/*
* This bit is only writable from Debug Mode.
* In ordinary use, external debuggers will always set this bit when
* configuring a trigger.
- * When clearing this bit, debuggers should also clear the action field
- * (whose location depends on \FcsrTdataOneType).
+ * When clearing this bit, debuggers should also set the action field
+ * (whose location depends on \FcsrTdataOneType) to something other
+ * than 1.
*/
-#define CSR_TDATA1_DMODE_OFFSET (XLEN-5)
-#define CSR_TDATA1_DMODE_LENGTH 1
-#define CSR_TDATA1_DMODE (0x1ULL << CSR_TDATA1_DMODE_OFFSET)
/*
* If \FcsrTdataOneType is 0, then this field is hard-wired to 0.
*
* Trigger-specific data.
*/
#define CSR_TDATA1_DATA_OFFSET 0
-#define CSR_TDATA1_DATA_LENGTH (XLEN - 5)
-#define CSR_TDATA1_DATA (((1L << XLEN - 5) - 1) << CSR_TDATA1_DATA_OFFSET)
+#define CSR_TDATA1_DATA_LENGTH(XLEN) (XLEN + -5)
+#define CSR_TDATA1_DATA(XLEN) ((1ULL<<(XLEN + -5)) + -1)
#define CSR_TDATA2 0x7a2
#define CSR_TDATA2_DATA_OFFSET 0
-#define CSR_TDATA2_DATA_LENGTH XLEN
-#define CSR_TDATA2_DATA (((1L << XLEN) - 1) << CSR_TDATA2_DATA_OFFSET)
+#define CSR_TDATA2_DATA_LENGTH(XLEN) XLEN
+#define CSR_TDATA2_DATA(XLEN) ((1ULL<<XLEN) + -1)
#define CSR_TDATA3 0x7a3
#define CSR_TDATA3_DATA_OFFSET 0
-#define CSR_TDATA3_DATA_LENGTH XLEN
-#define CSR_TDATA3_DATA (((1L << XLEN) - 1) << CSR_TDATA3_DATA_OFFSET)
+#define CSR_TDATA3_DATA_LENGTH(XLEN) XLEN
+#define CSR_TDATA3_DATA(XLEN) ((1ULL<<XLEN) + -1)
#define CSR_TINFO 0x7a4
/*
* One bit for each possible \FcsrTdataOneType enumerated in \RcsrTdataOne. Bit N
@@ -430,32 +525,9 @@
* contains 1.
*/
#define CSR_TINFO_INFO_OFFSET 0
-#define CSR_TINFO_INFO_LENGTH 16
-#define CSR_TINFO_INFO (0xffffULL << CSR_TINFO_INFO_OFFSET)
+#define CSR_TINFO_INFO_LENGTH 0x10
+#define CSR_TINFO_INFO 0xffff
#define CSR_TCONTROL 0x7a5
-/*
- * \RcsrHcontext enable.
- *
- * 0: \RcsrHcontext is set to 0 and writes are ignored.
- *
- * 1: \RcsrHcontext may be written and read.
- */
-#define CSR_TCONTROL_HCXE_OFFSET 9
-#define CSR_TCONTROL_HCXE_LENGTH 1
-#define CSR_TCONTROL_HCXE (0x1ULL << CSR_TCONTROL_HCXE_OFFSET)
-/*
- * \RcsrScontext enable.
- *
- * 0: \RcsrScontext is set to 0 and writes are ignored.
- *
- * 1: \RcsrScontext may be written and read.
- *
- * Enabling \RcsrScontext can be a security risk in a
- * virtualized system with a hypervisor that does not swap \RcsrScontext.
- */
-#define CSR_TCONTROL_SCXE_OFFSET 8
-#define CSR_TCONTROL_SCXE_LENGTH 1
-#define CSR_TCONTROL_SCXE (0x1ULL << CSR_TCONTROL_SCXE_OFFSET)
/*
* M-mode previous trigger enable field.
*
@@ -463,25 +535,30 @@
* regarding triggers with action=0 firing in M-mode trap handlers. See
* Section~\ref{sec:nativetrigger} for more details.
*
- * When a trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of
+ * When a breakpoint trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of
* \FcsrTcontrolMte.
*/
#define CSR_TCONTROL_MPTE_OFFSET 7
#define CSR_TCONTROL_MPTE_LENGTH 1
-#define CSR_TCONTROL_MPTE (0x1ULL << CSR_TCONTROL_MPTE_OFFSET)
+#define CSR_TCONTROL_MPTE 0x80
/*
* M-mode trigger enable field.
- *
- * 0: Triggers with action=0 do not match/fire while the hart is in M-mode.
- *
- * 1: Triggers do match/fire while the hart is in M-mode.
- *
- * When a trap into M-mode is taken, \FcsrTcontrolMte is set to 0. When {\tt
- * mret} is executed, \FcsrTcontrolMte is set to the value of \FcsrTcontrolMpte.
*/
#define CSR_TCONTROL_MTE_OFFSET 3
#define CSR_TCONTROL_MTE_LENGTH 1
-#define CSR_TCONTROL_MTE (0x1ULL << CSR_TCONTROL_MTE_OFFSET)
+#define CSR_TCONTROL_MTE 8
+/*
+ * disabled: Triggers with action=0 do not match/fire while the hart is in M-mode.
+ */
+#define CSR_TCONTROL_MTE_DISABLED 0
+/*
+ * enabled: Triggers do match/fire while the hart is in M-mode.
+ */
+#define CSR_TCONTROL_MTE_ENABLED 1
+/*
+ * When a breakpoint trap into M-mode is taken, \FcsrTcontrolMte is set to 0. When {\tt
+ * mret} is executed, \FcsrTcontrolMte is set to the value of \FcsrTcontrolMpte.
+ */
#define CSR_HCONTEXT 0x6a8
/*
* Hypervisor mode software can write a context number to this register,
@@ -496,8 +573,8 @@
* and 14 on RV64.
*/
#define CSR_HCONTEXT_HCONTEXT_OFFSET 0
-#define CSR_HCONTEXT_HCONTEXT_LENGTH XLEN
-#define CSR_HCONTEXT_HCONTEXT (((1L << XLEN) - 1) << CSR_HCONTEXT_HCONTEXT_OFFSET)
+#define CSR_HCONTEXT_HCONTEXT_LENGTH(XLEN) XLEN
+#define CSR_HCONTEXT_HCONTEXT(XLEN) ((1ULL<<XLEN) + -1)
#define CSR_SCONTEXT 0x5a8
/*
* Supervisor mode software can write a context number to this
@@ -509,17 +586,17 @@
* 34 on RV64.
*/
#define CSR_SCONTEXT_DATA_OFFSET 0
-#define CSR_SCONTEXT_DATA_LENGTH XLEN
-#define CSR_SCONTEXT_DATA (((1L << XLEN) - 1) << CSR_SCONTEXT_DATA_OFFSET)
+#define CSR_SCONTEXT_DATA_LENGTH(XLEN) XLEN
+#define CSR_SCONTEXT_DATA(XLEN) ((1ULL<<XLEN) + -1)
#define CSR_MCONTEXT 0x7a8
#define CSR_MSCONTEXT 0x7aa
#define CSR_MCONTROL 0x7a1
-#define CSR_MCONTROL_TYPE_OFFSET (XLEN-4)
+#define CSR_MCONTROL_TYPE_OFFSET(XLEN) (XLEN + -4)
#define CSR_MCONTROL_TYPE_LENGTH 4
-#define CSR_MCONTROL_TYPE (0xfULL << CSR_MCONTROL_TYPE_OFFSET)
-#define CSR_MCONTROL_DMODE_OFFSET (XLEN-5)
+#define CSR_MCONTROL_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4)))
+#define CSR_MCONTROL_DMODE_OFFSET(XLEN) (XLEN + -5)
#define CSR_MCONTROL_DMODE_LENGTH 1
-#define CSR_MCONTROL_DMODE (0x1ULL << CSR_MCONTROL_DMODE_OFFSET)
+#define CSR_MCONTROL_DMODE(XLEN) (1ULL<<(XLEN + -5))
/*
* Specifies the largest naturally aligned powers-of-two (NAPOT) range
* supported by the hardware when \FcsrMcontrolMatch is 1. The value is the
@@ -528,18 +605,18 @@
* A value of 63 corresponds to the maximum NAPOT range, which is
* $2^{63}$ bytes in size.
*/
-#define CSR_MCONTROL_MASKMAX_OFFSET (XLEN-11)
+#define CSR_MCONTROL_MASKMAX_OFFSET(XLEN) (XLEN + -0xb)
#define CSR_MCONTROL_MASKMAX_LENGTH 6
-#define CSR_MCONTROL_MASKMAX (0x3fULL << CSR_MCONTROL_MASKMAX_OFFSET)
+#define CSR_MCONTROL_MASKMAX(XLEN) (0x3f * (1ULL<<(XLEN + -0xb)))
/*
* This field only exists when XLEN is at least 64.
* It contains the 2 high bits of the access size. The low bits
* come from \FcsrMcontrolSizelo. See \FcsrMcontrolSizelo for how this
* is used.
*/
-#define CSR_MCONTROL_SIZEHI_OFFSET 21
+#define CSR_MCONTROL_SIZEHI_OFFSET 0x15
#define CSR_MCONTROL_SIZEHI_LENGTH 2
-#define CSR_MCONTROL_SIZEHI (0x3ULL << CSR_MCONTROL_SIZEHI_OFFSET)
+#define CSR_MCONTROL_SIZEHI 0x600000
/*
* If this bit is implemented then it must become set when this
* trigger fires and may become set when this trigger matches.
@@ -548,28 +625,35 @@
* trigger(s) matched. If the bit is not implemented, it is always 0
* and writing it has no effect.
*/
-#define CSR_MCONTROL_HIT_OFFSET 20
+#define CSR_MCONTROL_HIT_OFFSET 0x14
#define CSR_MCONTROL_HIT_LENGTH 1
-#define CSR_MCONTROL_HIT (0x1ULL << CSR_MCONTROL_HIT_OFFSET)
+#define CSR_MCONTROL_HIT 0x100000
/*
* This bit determines the contents of the XLEN-bit compare values.
- *
- * 0: There is at least one compare value and it contains the lowest
+ */
+#define CSR_MCONTROL_SELECT_OFFSET 0x13
+#define CSR_MCONTROL_SELECT_LENGTH 1
+#define CSR_MCONTROL_SELECT 0x80000
+/*
+ * address: There is at least one compare value and it contains the lowest
* virtual address of the access.
* It is recommended that there are additional compare values for
* the other accessed virtual addresses.
* (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000
* and the other addresses are 0x4001, 0x4002, and 0x4003.)
- *
- * 1: There is exactly one compare value and it contains the data
+ */
+#define CSR_MCONTROL_SELECT_ADDRESS 0
+/*
+ * data: There is exactly one compare value and it contains the data
* value loaded or stored, or the instruction executed.
* Any bits beyond the size of the data access will contain 0.
*/
-#define CSR_MCONTROL_SELECT_OFFSET 19
-#define CSR_MCONTROL_SELECT_LENGTH 1
-#define CSR_MCONTROL_SELECT (0x1ULL << CSR_MCONTROL_SELECT_OFFSET)
+#define CSR_MCONTROL_SELECT_DATA 1
+#define CSR_MCONTROL_TIMING_OFFSET 0x12
+#define CSR_MCONTROL_TIMING_LENGTH 1
+#define CSR_MCONTROL_TIMING 0x40000
/*
- * 0: The action for this trigger will be taken just before the
+ * before: The action for this trigger will be taken just before the
* instruction that triggered it is committed, but after all preceding
* instructions are committed. \Rxepc or \RcsrDpc (depending
* on \FcsrMcontrolAction) must be set to the virtual address of the
@@ -581,15 +665,19 @@
* though the load will not update its destination register. Debuggers
* should consider this when setting such breakpoints on, for example,
* memory-mapped I/O addresses.
- *
- * 1: The action for this trigger will be taken after the instruction
+ */
+#define CSR_MCONTROL_TIMING_BEFORE 0
+/*
+ * after: The action for this trigger will be taken after the instruction
* that triggered it is committed. It should be taken before the next
* instruction is committed, but it is better to implement triggers imprecisely
* than to not implement them at all. \Rxepc or
* \RcsrDpc (depending on \FcsrMcontrolAction) must be set to
* the virtual address of the next instruction that must be executed to
* preserve the program flow.
- *
+ */
+#define CSR_MCONTROL_TIMING_AFTER 1
+/*
* Most hardware will only implement one timing or the other, possibly
* dependent on \FcsrMcontrolSelect, \FcsrMcontrolExecute,
* \FcsrMcontrolLoad, and \FcsrMcontrolStore. This bit
@@ -606,39 +694,60 @@
* implementation-dependent whether that prevents a trigger with
* \FcsrMcontrolTiming of 1 matching as well.
*/
-#define CSR_MCONTROL_TIMING_OFFSET 18
-#define CSR_MCONTROL_TIMING_LENGTH 1
-#define CSR_MCONTROL_TIMING (0x1ULL << CSR_MCONTROL_TIMING_OFFSET)
/*
* This field contains the 2 low bits of the access size. The high bits come
* from \FcsrMcontrolSizehi. The combined value is interpreted as follows:
- *
- * 0: The trigger will attempt to match against an access of any size.
+ */
+#define CSR_MCONTROL_SIZELO_OFFSET 0x10
+#define CSR_MCONTROL_SIZELO_LENGTH 2
+#define CSR_MCONTROL_SIZELO 0x30000
+/*
+ * any: The trigger will attempt to match against an access of any size.
* The behavior is only well-defined if $|select|=0$, or if the access
* size is XLEN.
- *
- * 1: The trigger will only match against 8-bit memory accesses.
- *
- * 2: The trigger will only match against 16-bit memory accesses or
+ */
+#define CSR_MCONTROL_SIZELO_ANY 0
+/*
+ * 8bit: The trigger will only match against 8-bit memory accesses.
+ */
+#define CSR_MCONTROL_SIZELO_8BIT 1
+/*
+ * 16bit: The trigger will only match against 16-bit memory accesses or
* execution of 16-bit instructions.
- *
- * 3: The trigger will only match against 32-bit memory accesses or
+ */
+#define CSR_MCONTROL_SIZELO_16BIT 2
+/*
+ * 32bit: The trigger will only match against 32-bit memory accesses or
* execution of 32-bit instructions.
- *
- * 4: The trigger will only match against execution of 48-bit instructions.
- *
- * 5: The trigger will only match against 64-bit memory accesses or
+ */
+#define CSR_MCONTROL_SIZELO_32BIT 3
+/*
+ * 48bit: The trigger will only match against execution of 48-bit instructions.
+ */
+#define CSR_MCONTROL_SIZELO_48BIT 4
+/*
+ * 64bit: The trigger will only match against 64-bit memory accesses or
* execution of 64-bit instructions.
- *
- * 6: The trigger will only match against execution of 80-bit instructions.
- *
- * 7: The trigger will only match against execution of 96-bit instructions.
- *
- * 8: The trigger will only match against execution of 112-bit instructions.
- *
- * 9: The trigger will only match against 128-bit memory accesses or
+ */
+#define CSR_MCONTROL_SIZELO_64BIT 5
+/*
+ * 80bit: The trigger will only match against execution of 80-bit instructions.
+ */
+#define CSR_MCONTROL_SIZELO_80BIT 6
+/*
+ * 96bit: The trigger will only match against execution of 96-bit instructions.
+ */
+#define CSR_MCONTROL_SIZELO_96BIT 7
+/*
+ * 112bit: The trigger will only match against execution of 112-bit instructions.
+ */
+#define CSR_MCONTROL_SIZELO_112BIT 8
+/*
+ * 128bit: The trigger will only match against 128-bit memory accesses or
* execution of 128-bit instructions.
- *
+ */
+#define CSR_MCONTROL_SIZELO_128BIT 9
+/*
* An implementation must support the value of 0, but all other values
* are optional. When an implementation supports address triggers
* (\FcsrMcontrolSelect=0), it is recommended that those triggers
@@ -656,22 +765,54 @@
* hart supports, as well as for every instruction length up to XLEN
* that the hart supports.
*/
-#define CSR_MCONTROL_SIZELO_OFFSET 16
-#define CSR_MCONTROL_SIZELO_LENGTH 2
-#define CSR_MCONTROL_SIZELO (0x3ULL << CSR_MCONTROL_SIZELO_OFFSET)
/*
* The action to take when the trigger fires. The values are explained
* in Table~\ref{tab:action}.
*/
-#define CSR_MCONTROL_ACTION_OFFSET 12
+#define CSR_MCONTROL_ACTION_OFFSET 0xc
#define CSR_MCONTROL_ACTION_LENGTH 4
-#define CSR_MCONTROL_ACTION (0xfULL << CSR_MCONTROL_ACTION_OFFSET)
+#define CSR_MCONTROL_ACTION 0xf000
/*
- * 0: When this trigger matches, the configured action is taken.
- *
- * 1: While this trigger does not match, it prevents the trigger with
+ * breakpoint:
+ */
+#define CSR_MCONTROL_ACTION_BREAKPOINT 0
+/*
+ * debug mode:
+ */
+#define CSR_MCONTROL_ACTION_DEBUG_MODE 1
+/*
+ * trace on:
+ */
+#define CSR_MCONTROL_ACTION_TRACE_ON 2
+/*
+ * trace off:
+ */
+#define CSR_MCONTROL_ACTION_TRACE_OFF 3
+/*
+ * trace notify:
+ */
+#define CSR_MCONTROL_ACTION_TRACE_NOTIFY 4
+/*
+ * external0:
+ */
+#define CSR_MCONTROL_ACTION_EXTERNAL0 8
+/*
+ * external1:
+ */
+#define CSR_MCONTROL_ACTION_EXTERNAL1 9
+#define CSR_MCONTROL_CHAIN_OFFSET 0xb
+#define CSR_MCONTROL_CHAIN_LENGTH 1
+#define CSR_MCONTROL_CHAIN 0x800
+/*
+ * disabled: When this trigger matches, the configured action is taken.
+ */
+#define CSR_MCONTROL_CHAIN_DISABLED 0
+/*
+ * enabled: While this trigger does not match, it prevents the trigger with
* the next index from matching.
- *
+ */
+#define CSR_MCONTROL_CHAIN_ENABLED 1
+/*
* A trigger chain starts on the first trigger with $|chain|=1$ after
* a trigger with $|chain|=0$, or simply on the first trigger if that
* has $|chain|=1$. It ends on the first trigger after that which has
@@ -695,44 +836,64 @@
* chain (eg. to meet timing requirements) may do so by zeroing
* \FcsrMcontrolChain in writes to \RcsrMcontrol that would make the chain too long.
*/
-#define CSR_MCONTROL_CHAIN_OFFSET 11
-#define CSR_MCONTROL_CHAIN_LENGTH 1
-#define CSR_MCONTROL_CHAIN (0x1ULL << CSR_MCONTROL_CHAIN_OFFSET)
+#define CSR_MCONTROL_MATCH_OFFSET 7
+#define CSR_MCONTROL_MATCH_LENGTH 4
+#define CSR_MCONTROL_MATCH 0x780
/*
- * 0: Matches when any compare value equals \RcsrTdataTwo.
- *
- * 1: Matches when the top $M$ bits of any compare value match the top
+ * equal: Matches when any compare value equals \RcsrTdataTwo.
+ */
+#define CSR_MCONTROL_MATCH_EQUAL 0
+/*
+ * napot: Matches when the top $M$ bits of any compare value match the top
* $M$ bits of \RcsrTdataTwo.
* $M$ is $|XLEN|-1$ minus the index of the least-significant
* bit containing 0 in \RcsrTdataTwo. Debuggers should only write values
* to \RcsrTdataTwo such that $M + $\FcsrMcontrolMaskmax$ \geq |XLEN|$
* and $M\gt0$ , otherwise it's undefined on what conditions the
* trigger will match.
- *
- * 2: Matches when any compare value is greater than (unsigned) or
+ */
+#define CSR_MCONTROL_MATCH_NAPOT 1
+/*
+ * ge: Matches when any compare value is greater than (unsigned) or
* equal to \RcsrTdataTwo.
- *
- * 3: Matches when any compare value is less than (unsigned)
+ */
+#define CSR_MCONTROL_MATCH_GE 2
+/*
+ * lt: Matches when any compare value is less than (unsigned)
* \RcsrTdataTwo.
- *
- * 4: Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value
+ */
+#define CSR_MCONTROL_MATCH_LT 3
+/*
+ * mask low: Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value
* equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after
* $\frac{|XLEN|}{2}-1$:$0$ of the compare value is ANDed with
* $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.
- *
- * 5: Matches when $|XLEN|-1$:$\frac{|XLEN|}{2}$ of any compare
+ */
+#define CSR_MCONTROL_MATCH_MASK_LOW 4
+/*
+ * mask high: Matches when $|XLEN|-1$:$\frac{|XLEN|}{2}$ of any compare
* value equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after
* $|XLEN|-1$:$\frac{|XLEN|}{2}$ of the compare value is ANDed with
* $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.
- *
- * 8: Matches when \FcsrMcontrolMatch$=0$ would not match.
- *
- * 9: Matches when \FcsrMcontrolMatch$=1$ would not match.
- *
- * 12: Matches when \FcsrMcontrolMatch$=4$ would not match.
- *
- * 13: Matches when \FcsrMcontrolMatch$=5$ would not match.
- *
+ */
+#define CSR_MCONTROL_MATCH_MASK_HIGH 5
+/*
+ * not equal: Matches when \FcsrMcontrolMatch$=0$ would not match.
+ */
+#define CSR_MCONTROL_MATCH_NOT_EQUAL 8
+/*
+ * not napot: Matches when \FcsrMcontrolMatch$=1$ would not match.
+ */
+#define CSR_MCONTROL_MATCH_NOT_NAPOT 9
+/*
+ * not mask low: Matches when \FcsrMcontrolMatch$=4$ would not match.
+ */
+#define CSR_MCONTROL_MATCH_NOT_MASK_LOW 12
+/*
+ * not mask high: Matches when \FcsrMcontrolMatch$=5$ would not match.
+ */
+#define CSR_MCONTROL_MATCH_NOT_MASK_HIGH 13
+/*
* Other values are reserved for future use.
*
* All comparisons only look at the lower XLEN (in the current mode)
@@ -741,15 +902,12 @@
* reduced, and comparisons only look at the lower N bits of the
* compare values and of \RcsrTdataTwo.
*/
-#define CSR_MCONTROL_MATCH_OFFSET 7
-#define CSR_MCONTROL_MATCH_LENGTH 4
-#define CSR_MCONTROL_MATCH (0xfULL << CSR_MCONTROL_MATCH_OFFSET)
/*
* When set, enable this trigger in M-mode.
*/
#define CSR_MCONTROL_M_OFFSET 6
#define CSR_MCONTROL_M_LENGTH 1
-#define CSR_MCONTROL_M (0x1ULL << CSR_MCONTROL_M_OFFSET)
+#define CSR_MCONTROL_M 0x40
/*
* When set, enable this trigger in S/HS-mode.
* This bit is hard-wired to 0 if the hart does not support
@@ -757,7 +915,7 @@
*/
#define CSR_MCONTROL_S_OFFSET 4
#define CSR_MCONTROL_S_LENGTH 1
-#define CSR_MCONTROL_S (0x1ULL << CSR_MCONTROL_S_OFFSET)
+#define CSR_MCONTROL_S 0x10
/*
* When set, enable this trigger in U-mode.
* This bit is hard-wired to 0 if the hart does not support
@@ -765,51 +923,51 @@
*/
#define CSR_MCONTROL_U_OFFSET 3
#define CSR_MCONTROL_U_LENGTH 1
-#define CSR_MCONTROL_U (0x1ULL << CSR_MCONTROL_U_OFFSET)
+#define CSR_MCONTROL_U 8
/*
* When set, the trigger fires on the virtual address or opcode of an
* instruction that is executed.
*/
#define CSR_MCONTROL_EXECUTE_OFFSET 2
#define CSR_MCONTROL_EXECUTE_LENGTH 1
-#define CSR_MCONTROL_EXECUTE (0x1ULL << CSR_MCONTROL_EXECUTE_OFFSET)
+#define CSR_MCONTROL_EXECUTE 4
/*
* When set, the trigger fires on the virtual address or data of any
* store.
*/
#define CSR_MCONTROL_STORE_OFFSET 1
#define CSR_MCONTROL_STORE_LENGTH 1
-#define CSR_MCONTROL_STORE (0x1ULL << CSR_MCONTROL_STORE_OFFSET)
+#define CSR_MCONTROL_STORE 2
/*
* When set, the trigger fires on the virtual address or data of any
* load.
*/
#define CSR_MCONTROL_LOAD_OFFSET 0
#define CSR_MCONTROL_LOAD_LENGTH 1
-#define CSR_MCONTROL_LOAD (0x1ULL << CSR_MCONTROL_LOAD_OFFSET)
+#define CSR_MCONTROL_LOAD 1
#define CSR_MCONTROL6 0x7a1
-#define CSR_MCONTROL6_TYPE_OFFSET (XLEN-4)
+#define CSR_MCONTROL6_TYPE_OFFSET(XLEN) (XLEN + -4)
#define CSR_MCONTROL6_TYPE_LENGTH 4
-#define CSR_MCONTROL6_TYPE (0xfULL << CSR_MCONTROL6_TYPE_OFFSET)
-#define CSR_MCONTROL6_DMODE_OFFSET (XLEN-5)
+#define CSR_MCONTROL6_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4)))
+#define CSR_MCONTROL6_DMODE_OFFSET(XLEN) (XLEN + -5)
#define CSR_MCONTROL6_DMODE_LENGTH 1
-#define CSR_MCONTROL6_DMODE (0x1ULL << CSR_MCONTROL6_DMODE_OFFSET)
+#define CSR_MCONTROL6_DMODE(XLEN) (1ULL<<(XLEN + -5))
/*
* When set, enable this trigger in VS-mode.
* This bit is hard-wired to 0 if the hart does not support
* virtualization mode.
*/
-#define CSR_MCONTROL6_VS_OFFSET 24
+#define CSR_MCONTROL6_VS_OFFSET 0x18
#define CSR_MCONTROL6_VS_LENGTH 1
-#define CSR_MCONTROL6_VS (0x1ULL << CSR_MCONTROL6_VS_OFFSET)
+#define CSR_MCONTROL6_VS 0x1000000
/*
* When set, enable this trigger in VU-mode.
* This bit is hard-wired to 0 if the hart does not support
* virtualization mode.
*/
-#define CSR_MCONTROL6_VU_OFFSET 23
+#define CSR_MCONTROL6_VU_OFFSET 0x17
#define CSR_MCONTROL6_VU_LENGTH 1
-#define CSR_MCONTROL6_VU (0x1ULL << CSR_MCONTROL6_VU_OFFSET)
+#define CSR_MCONTROL6_VU 0x800000
/*
* If this bit is implemented then it must become set when this
* trigger fires and may become set when this trigger matches.
@@ -818,28 +976,35 @@
* trigger(s) matched. If the bit is not implemented, it is always 0
* and writing it has no effect.
*/
-#define CSR_MCONTROL6_HIT_OFFSET 22
+#define CSR_MCONTROL6_HIT_OFFSET 0x16
#define CSR_MCONTROL6_HIT_LENGTH 1
-#define CSR_MCONTROL6_HIT (0x1ULL << CSR_MCONTROL6_HIT_OFFSET)
+#define CSR_MCONTROL6_HIT 0x400000
/*
* This bit determines the contents of the XLEN-bit compare values.
- *
- * 0: There is at least one compare value and it contains the lowest
+ */
+#define CSR_MCONTROL6_SELECT_OFFSET 0x15
+#define CSR_MCONTROL6_SELECT_LENGTH 1
+#define CSR_MCONTROL6_SELECT 0x200000
+/*
+ * address: There is at least one compare value and it contains the lowest
* virtual address of the access.
* In addition, it is recommended that there are additional compare
* values for the other accessed virtual addresses match.
* (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000
* and the other addresses are 0x4001, 0x4002, and 0x4003.)
- *
- * 1: There is exactly one compare value and it contains the data
+ */
+#define CSR_MCONTROL6_SELECT_ADDRESS 0
+/*
+ * data: There is exactly one compare value and it contains the data
* value loaded or stored, or the instruction executed.
* Any bits beyond the size of the data access will contain 0.
*/
-#define CSR_MCONTROL6_SELECT_OFFSET 21
-#define CSR_MCONTROL6_SELECT_LENGTH 1
-#define CSR_MCONTROL6_SELECT (0x1ULL << CSR_MCONTROL6_SELECT_OFFSET)
+#define CSR_MCONTROL6_SELECT_DATA 1
+#define CSR_MCONTROL6_TIMING_OFFSET 0x14
+#define CSR_MCONTROL6_TIMING_LENGTH 1
+#define CSR_MCONTROL6_TIMING 0x100000
/*
- * 0: The action for this trigger will be taken just before the
+ * before: The action for this trigger will be taken just before the
* instruction that triggered it is committed, but after all preceding
* instructions are committed. \Rxepc or \RcsrDpc (depending
* on \FcsrMcontrolSixAction) must be set to the virtual address of the
@@ -851,15 +1016,19 @@
* though the load will not update its destination register. Debuggers
* should consider this when setting such breakpoints on, for example,
* memory-mapped I/O addresses.
- *
- * 1: The action for this trigger will be taken after the instruction
+ */
+#define CSR_MCONTROL6_TIMING_BEFORE 0
+/*
+ * after: The action for this trigger will be taken after the instruction
* that triggered it is committed. It should be taken before the next
* instruction is committed, but it is better to implement triggers imprecisely
* than to not implement them at all. \Rxepc or
* \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set to
* the virtual address of the next instruction that must be executed to
* preserve the program flow.
- *
+ */
+#define CSR_MCONTROL6_TIMING_AFTER 1
+/*
* Most hardware will only implement one timing or the other, possibly
* dependent on \FcsrMcontrolSixSelect, \FcsrMcontrolSixExecute,
* \FcsrMcontrolSixLoad, and \FcsrMcontrolSixStore. This bit
@@ -876,36 +1045,56 @@
* implementation-dependent whether that prevents a trigger with
* \FcsrMcontrolSixTiming of 1 matching as well.
*/
-#define CSR_MCONTROL6_TIMING_OFFSET 20
-#define CSR_MCONTROL6_TIMING_LENGTH 1
-#define CSR_MCONTROL6_TIMING (0x1ULL << CSR_MCONTROL6_TIMING_OFFSET)
+#define CSR_MCONTROL6_SIZE_OFFSET 0x10
+#define CSR_MCONTROL6_SIZE_LENGTH 4
+#define CSR_MCONTROL6_SIZE 0xf0000
/*
- * 0: The trigger will attempt to match against an access of any size.
+ * any: The trigger will attempt to match against an access of any size.
* The behavior is only well-defined if $|select|=0$, or if the access
* size is XLEN.
- *
- * 1: The trigger will only match against 8-bit memory accesses.
- *
- * 2: The trigger will only match against 16-bit memory accesses or
+ */
+#define CSR_MCONTROL6_SIZE_ANY 0
+/*
+ * 8bit: The trigger will only match against 8-bit memory accesses.
+ */
+#define CSR_MCONTROL6_SIZE_8BIT 1
+/*
+ * 16bit: The trigger will only match against 16-bit memory accesses or
* execution of 16-bit instructions.
- *
- * 3: The trigger will only match against 32-bit memory accesses or
+ */
+#define CSR_MCONTROL6_SIZE_16BIT 2
+/*
+ * 32bit: The trigger will only match against 32-bit memory accesses or
* execution of 32-bit instructions.
- *
- * 4: The trigger will only match against execution of 48-bit instructions.
- *
- * 5: The trigger will only match against 64-bit memory accesses or
+ */
+#define CSR_MCONTROL6_SIZE_32BIT 3
+/*
+ * 48bit: The trigger will only match against execution of 48-bit instructions.
+ */
+#define CSR_MCONTROL6_SIZE_48BIT 4
+/*
+ * 64bit: The trigger will only match against 64-bit memory accesses or
* execution of 64-bit instructions.
- *
- * 6: The trigger will only match against execution of 80-bit instructions.
- *
- * 7: The trigger will only match against execution of 96-bit instructions.
- *
- * 8: The trigger will only match against execution of 112-bit instructions.
- *
- * 9: The trigger will only match against 128-bit memory accesses or
+ */
+#define CSR_MCONTROL6_SIZE_64BIT 5
+/*
+ * 80bit: The trigger will only match against execution of 80-bit instructions.
+ */
+#define CSR_MCONTROL6_SIZE_80BIT 6
+/*
+ * 96bit: The trigger will only match against execution of 96-bit instructions.
+ */
+#define CSR_MCONTROL6_SIZE_96BIT 7
+/*
+ * 112bit: The trigger will only match against execution of 112-bit instructions.
+ */
+#define CSR_MCONTROL6_SIZE_112BIT 8
+/*
+ * 128bit: The trigger will only match against 128-bit memory accesses or
* execution of 128-bit instructions.
- *
+ */
+#define CSR_MCONTROL6_SIZE_128BIT 9
+/*
* An implementation must support the value of 0, but all other values
* are optional. When an implementation supports address triggers
* (\FcsrMcontrolSixSelect=0), it is recommended that those triggers
@@ -923,22 +1112,54 @@
* hart supports, as well as for every instruction length up to XLEN
* that the hart supports.
*/
-#define CSR_MCONTROL6_SIZE_OFFSET 16
-#define CSR_MCONTROL6_SIZE_LENGTH 4
-#define CSR_MCONTROL6_SIZE (0xfULL << CSR_MCONTROL6_SIZE_OFFSET)
/*
* The action to take when the trigger fires. The values are explained
* in Table~\ref{tab:action}.
*/
-#define CSR_MCONTROL6_ACTION_OFFSET 12
+#define CSR_MCONTROL6_ACTION_OFFSET 0xc
#define CSR_MCONTROL6_ACTION_LENGTH 4
-#define CSR_MCONTROL6_ACTION (0xfULL << CSR_MCONTROL6_ACTION_OFFSET)
+#define CSR_MCONTROL6_ACTION 0xf000
/*
- * 0: When this trigger matches, the configured action is taken.
- *
- * 1: While this trigger does not match, it prevents the trigger with
+ * breakpoint:
+ */
+#define CSR_MCONTROL6_ACTION_BREAKPOINT 0
+/*
+ * debug mode:
+ */
+#define CSR_MCONTROL6_ACTION_DEBUG_MODE 1
+/*
+ * trace on:
+ */
+#define CSR_MCONTROL6_ACTION_TRACE_ON 2
+/*
+ * trace off:
+ */
+#define CSR_MCONTROL6_ACTION_TRACE_OFF 3
+/*
+ * trace notify:
+ */
+#define CSR_MCONTROL6_ACTION_TRACE_NOTIFY 4
+/*
+ * external0:
+ */
+#define CSR_MCONTROL6_ACTION_EXTERNAL0 8
+/*
+ * external1:
+ */
+#define CSR_MCONTROL6_ACTION_EXTERNAL1 9
+#define CSR_MCONTROL6_CHAIN_OFFSET 0xb
+#define CSR_MCONTROL6_CHAIN_LENGTH 1
+#define CSR_MCONTROL6_CHAIN 0x800
+/*
+ * disabled: When this trigger matches, the configured action is taken.
+ */
+#define CSR_MCONTROL6_CHAIN_DISABLED 0
+/*
+ * enabled: While this trigger does not match, it prevents the trigger with
* the next index from matching.
- *
+ */
+#define CSR_MCONTROL6_CHAIN_ENABLED 1
+/*
* A trigger chain starts on the first trigger with $|chain|=1$ after
* a trigger with $|chain|=0$, or simply on the first trigger if that
* has $|chain|=1$. It ends on the first trigger after that which has
@@ -962,45 +1183,66 @@
* chain (eg. to meet timing requirements) may do so by zeroing
* \FcsrMcontrolSixChain in writes to \RcsrMcontrolSix that would make the chain too long.
*/
-#define CSR_MCONTROL6_CHAIN_OFFSET 11
-#define CSR_MCONTROL6_CHAIN_LENGTH 1
-#define CSR_MCONTROL6_CHAIN (0x1ULL << CSR_MCONTROL6_CHAIN_OFFSET)
+#define CSR_MCONTROL6_MATCH_OFFSET 7
+#define CSR_MCONTROL6_MATCH_LENGTH 4
+#define CSR_MCONTROL6_MATCH 0x780
/*
- * 0: Matches when any compare value equals \RcsrTdataTwo.
- *
- * 1: Matches when the top $M$ bits of any compare value match the top
+ * equal: Matches when any compare value equals \RcsrTdataTwo.
+ */
+#define CSR_MCONTROL6_MATCH_EQUAL 0
+/*
+ * napot: Matches when the top $M$ bits of any compare value match the top
* $M$ bits of \RcsrTdataTwo.
* $M$ is $|XLEN|-1$ minus the index of the least-significant bit
* containing 0 in \RcsrTdataTwo.
- * \RcsrTdataTwo is WARL and bit $|maskmax6|-1$ will be set to 0 if no
- * less significant bits are written with 0.
+ * \RcsrTdataTwo is WARL and if bits $|maskmax6|-1$:0 are written with all
+ * ones then bit $|maskmax6|-1$ will be set to 0 while the values of bits $|maskmax6|-2$:0
+ * are \unspecified.
* Legal values for \RcsrTdataTwo require $M + |maskmax6| \geq |XLEN|$ and $M\gt0$.
* See above for how to determine maskmax6.
- *
- * 2: Matches when any compare value is greater than (unsigned) or
+ */
+#define CSR_MCONTROL6_MATCH_NAPOT 1
+/*
+ * ge: Matches when any compare value is greater than (unsigned) or
* equal to \RcsrTdataTwo.
- *
- * 3: Matches when any compare value is less than (unsigned)
+ */
+#define CSR_MCONTROL6_MATCH_GE 2
+/*
+ * lt: Matches when any compare value is less than (unsigned)
* \RcsrTdataTwo.
- *
- * 4: Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value
+ */
+#define CSR_MCONTROL6_MATCH_LT 3
+/*
+ * mask low: Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value
* equals $\frac{|XLEN|}{2}-1$...
[truncated message content] |
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-14 14:46:00
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 0e1fe03f4ba2b313d80c0a2d3c2ecfb7aee85a77 (commit)
from dee7b7d8212dbe94d5afd6bba736de4fcd1a05ac (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 0e1fe03f4ba2b313d80c0a2d3c2ecfb7aee85a77
Author: Tomas Vanek <va...@fb...>
Date: Mon Aug 1 19:28:18 2022 +0200
target/arm: do not expose 'arm reg', 'arm mcr/mrc' commands on Cortex-M
Tcl commands 'arm reg', 'arm mcr/mrc' do not work on M-profile based devices.
Isolate them from 'arm core_state' and 'arm disassemble' and do not chain
them from armv7m_command_handlers.
Change-Id: I2c6befdf82575e95cf05ed158ab5e6faa1a182c3
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7101
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/target/arm.h b/src/target/arm.h
index f262255ab..bcfa85c79 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -273,6 +273,7 @@ void arm_free_reg_cache(struct arm *arm);
struct reg_cache *armv8_build_reg_cache(struct target *target);
extern const struct command_registration arm_command_handlers[];
+extern const struct command_registration arm_all_profiles_command_handlers[];
int arm_arch_state(struct target *target);
const char *arm_get_gdb_arch(struct target *target);
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 09cf143e6..321772699 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1125,20 +1125,6 @@ static const struct command_registration arm_exec_command_handlers[] = {
.help = "display ARM core registers",
.usage = "",
},
- {
- .name = "core_state",
- .handler = handle_arm_core_state_command,
- .mode = COMMAND_EXEC,
- .usage = "['arm'|'thumb']",
- .help = "display/change ARM core state",
- },
- {
- .name = "disassemble",
- .handler = handle_arm_disassemble_command,
- .mode = COMMAND_EXEC,
- .usage = "address [count ['thumb']]",
- .help = "disassemble instructions",
- },
{
.name = "mcr",
.mode = COMMAND_EXEC,
@@ -1153,11 +1139,33 @@ static const struct command_registration arm_exec_command_handlers[] = {
.help = "read coprocessor register",
.usage = "cpnum op1 CRn CRm op2",
},
+ {
+ .chain = arm_all_profiles_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+const struct command_registration arm_all_profiles_command_handlers[] = {
+ {
+ .name = "core_state",
+ .handler = handle_arm_core_state_command,
+ .mode = COMMAND_EXEC,
+ .usage = "['arm'|'thumb']",
+ .help = "display/change ARM core state",
+ },
+ {
+ .name = "disassemble",
+ .handler = handle_arm_disassemble_command,
+ .mode = COMMAND_EXEC,
+ .usage = "address [count ['thumb']]",
+ .help = "disassemble instructions",
+ },
{
.chain = semihosting_common_handlers,
},
COMMAND_REGISTRATION_DONE
};
+
const struct command_registration arm_command_handlers[] = {
{
.name = "arm",
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 790e70e63..be0de509b 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -1085,7 +1085,11 @@ int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
const struct command_registration armv7m_command_handlers[] = {
{
- .chain = arm_command_handlers,
+ .name = "arm",
+ .mode = COMMAND_ANY,
+ .help = "ARM command group",
+ .usage = "",
+ .chain = arm_all_profiles_command_handlers,
},
COMMAND_REGISTRATION_DONE
};
-----------------------------------------------------------------------
Summary of changes:
src/target/arm.h | 1 +
src/target/armv4_5.c | 36 ++++++++++++++++++++++--------------
src/target/armv7m.c | 6 +++++-
3 files changed, 28 insertions(+), 15 deletions(-)
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commit dee7b7d8212dbe94d5afd6bba736de4fcd1a05ac
Author: Tomas Vanek <va...@fb...>
Date: Mon Aug 1 19:06:35 2022 +0200
target/arm: make 'arm core_state' command compatible with Cortex-M
Tcl command 'arm core_state' was exposed even on Cortex-M devices.
However it returned message "Unsupported Command" without error status
on such device.
Set the only possible arm->core_state ARM_STATE_THUMB in armv7m init.
Block setting core_state to arm on Cortex-M.
Change-Id: I9525553ac8863a6cf77bbacbcd57e354b6cfe1ca
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7100
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 2b347924f..09cf143e6 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -905,32 +905,33 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
return ERROR_OK;
}
-COMMAND_HANDLER(handle_armv4_5_core_state_command)
+COMMAND_HANDLER(handle_arm_core_state_command)
{
struct target *target = get_current_target(CMD_CTX);
struct arm *arm = target_to_arm(target);
+ int ret = ERROR_OK;
if (!is_arm(arm)) {
command_print(CMD, "current target isn't an ARM");
return ERROR_FAIL;
}
- if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) {
- /* armv7m not supported */
- command_print(CMD, "Unsupported Command");
- return ERROR_OK;
- }
-
if (CMD_ARGC > 0) {
- if (strcmp(CMD_ARGV[0], "arm") == 0)
- arm->core_state = ARM_STATE_ARM;
+ if (strcmp(CMD_ARGV[0], "arm") == 0) {
+ if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) {
+ command_print(CMD, "arm mode not supported on Cortex-M");
+ ret = ERROR_FAIL;
+ } else {
+ arm->core_state = ARM_STATE_ARM;
+ }
+ }
if (strcmp(CMD_ARGV[0], "thumb") == 0)
arm->core_state = ARM_STATE_THUMB;
}
command_print(CMD, "core state: %s", arm_state_strings[arm->core_state]);
- return ERROR_OK;
+ return ret;
}
COMMAND_HANDLER(handle_arm_disassemble_command)
@@ -1126,7 +1127,7 @@ static const struct command_registration arm_exec_command_handlers[] = {
},
{
.name = "core_state",
- .handler = handle_armv4_5_core_state_command,
+ .handler = handle_arm_core_state_command,
.mode = COMMAND_EXEC,
.usage = "['arm'|'thumb']",
.help = "display/change ARM core state",
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 4c46240f8..790e70e63 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -854,6 +854,7 @@ int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
/* Enable stimulus port #0 by default */
armv7m->trace_config.itm_ter[0] = 1;
+ arm->core_state = ARM_STATE_THUMB;
arm->core_type = ARM_CORE_TYPE_M_PROFILE;
arm->arch_info = armv7m;
arm->setup_semihosting = armv7m_setup_semihosting;
-----------------------------------------------------------------------
Summary of changes:
src/target/armv4_5.c | 23 ++++++++++++-----------
src/target/armv7m.c | 1 +
2 files changed, 13 insertions(+), 11 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-08-14 12:11:50
|
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commit b6dad912b85d6bcd78c12a7a44065fb85dd8485a
Author: Tomas Vanek <va...@fb...>
Date: Tue Aug 2 11:33:07 2022 +0200
target/cortex_m: prevent segmentation fault in cortex_m_poll()
If a Cortex-M MCU become unresponsive during a debug session and
re-examination fails to find MEM-AP, debug_ap pointer is set to NULL.
Eventual call of cortex_m_poll() dereferences debug_ap.
Check debug_ap validity at the begin of cortex_m_poll().
Change-Id: I9519f48760c91a48a9e5e8c34634d247098cb14a
Fixes: 35a503b08d14 (arm_adi_v5: add ap refcount and add get/put around ap use)
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7108
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 1682f5dec..9497aa037 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -868,6 +868,16 @@ static int cortex_m_poll(struct target *target)
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
+ /* Check if debug_ap is available to prevent segmentation fault.
+ * If the re-examination after an error does not find a MEM-AP
+ * (e.g. the target stopped communicating), debug_ap pointer
+ * can suddenly become NULL.
+ */
+ if (!armv7m->debug_ap) {
+ target->state = TARGET_UNKNOWN;
+ return ERROR_TARGET_NOT_EXAMINED;
+ }
+
/* Read from Debug Halting Control and Status Register */
retval = cortex_m_read_dhcsr_atomic_sticky(target);
if (retval != ERROR_OK) {
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_m.c | 10 ++++++++++
1 file changed, 10 insertions(+)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-08-14 12:10:53
|
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commit cae0c8b32b32202f3552860f12f6579e8ad8ce4a
Author: Tomas Vanek <va...@fb...>
Date: Thu May 26 16:25:34 2022 +0200
target: move parent target structs just after common_magic
Just a cosmetic refactoring.
Change-Id: I7fbc05324e346fafc98d1b42691d33d3d8fbd04e
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7003
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/target/aarch64.h b/src/target/aarch64.h
index be7f246b5..2721fe747 100644
--- a/src/target/aarch64.h
+++ b/src/target/aarch64.h
@@ -40,6 +40,8 @@ struct aarch64_brp {
struct aarch64_common {
unsigned int common_magic;
+ struct armv8_common armv8_common;
+
/* Context information */
uint32_t system_control_reg;
uint32_t system_control_reg_curr;
@@ -55,8 +57,6 @@ struct aarch64_common {
int wp_num_available;
struct aarch64_brp *wp_list;
- struct armv8_common armv8_common;
-
enum aarch64_isrmasking_mode isrmasking_mode;
};
diff --git a/src/target/cortex_a.h b/src/target/cortex_a.h
index 656ccea8a..37fba1a88 100644
--- a/src/target/cortex_a.h
+++ b/src/target/cortex_a.h
@@ -69,6 +69,8 @@ struct cortex_a_wrp {
struct cortex_a_common {
unsigned int common_magic;
+ struct armv7a_common armv7a_common;
+
/* Context information */
uint32_t cpudbg_dscr;
@@ -96,9 +98,6 @@ struct cortex_a_common {
enum cortex_a_isrmasking_mode isrmasking_mode;
enum cortex_a_dacrfixup_mode dacrfixup_mode;
-
- struct armv7a_common armv7a_common;
-
};
static inline struct cortex_a_common *
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 54767c5df..168613590 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -201,6 +201,8 @@ enum cortex_m_isrmasking_mode {
struct cortex_m_common {
unsigned int common_magic;
+ struct armv7m_common armv7m;
+
/* Context information */
uint32_t dcb_dhcsr;
uint32_t dcb_dhcsr_cumulated_sticky;
@@ -226,7 +228,6 @@ struct cortex_m_common {
enum cortex_m_isrmasking_mode isrmasking_mode;
const struct cortex_m_part_info *core_info;
- struct armv7m_common armv7m;
bool slow_register_read; /* A register has not been ready, poll S_REGRDY */
diff --git a/src/target/mips_m4k.h b/src/target/mips_m4k.h
index b563ea513..8026de232 100644
--- a/src/target/mips_m4k.h
+++ b/src/target/mips_m4k.h
@@ -20,8 +20,9 @@ struct target;
struct mips_m4k_common {
unsigned int common_magic;
- bool is_pic32mx;
struct mips32_common mips32;
+
+ bool is_pic32mx;
};
static inline struct mips_m4k_common *
-----------------------------------------------------------------------
Summary of changes:
src/target/aarch64.h | 4 ++--
src/target/cortex_a.h | 5 ++---
src/target/cortex_m.h | 3 ++-
src/target/mips_m4k.h | 3 ++-
4 files changed, 8 insertions(+), 7 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-08-14 12:04:04
|
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generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
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commit ea49b2b2a21edf474236e3bdf0c681215c390787
Author: Tomas Vanek <va...@fb...>
Date: Thu May 26 10:18:43 2022 +0200
target/aarch64: fix duplicate common magic
AARCH64_COMMON_MAGIC was same as CORTEX_A_COMMON_MAGIC, probably copy pasta.
Define unique AARCH64_COMMON_MAGIC
Change-Id: Ie30e0028453a1fce5624ecad9bf73d5ac3791281
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6997
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/aarch64.h b/src/target/aarch64.h
index 52b3bafcd..be7f246b5 100644
--- a/src/target/aarch64.h
+++ b/src/target/aarch64.h
@@ -9,7 +9,7 @@
#include "armv8.h"
-#define AARCH64_COMMON_MAGIC 0x411fc082U
+#define AARCH64_COMMON_MAGIC 0x41413634U
#define CPUDBG_CPUID 0xD00
#define CPUDBG_CTYPR 0xD04
-----------------------------------------------------------------------
Summary of changes:
src/target/aarch64.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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commit 8f299c6aec299f7231005a1ba7526ed2758414c3
Author: Tomas Vanek <va...@fb...>
Date: Thu May 26 10:01:45 2022 +0200
target: consolidate existing target/algo common_magic
Unify common_magic type to unsigned int
Move common_magic to be the first member of the struct
Add unsigned specifier to xxx_COMMON_MAGIC #defines
Change-Id: If961d33232698529514ba3720e04418baf6dc6fe
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6996
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/aarch64.h b/src/target/aarch64.h
index 902a508e4..52b3bafcd 100644
--- a/src/target/aarch64.h
+++ b/src/target/aarch64.h
@@ -9,7 +9,7 @@
#include "armv8.h"
-#define AARCH64_COMMON_MAGIC 0x411fc082
+#define AARCH64_COMMON_MAGIC 0x411fc082U
#define CPUDBG_CPUID 0xD00
#define CPUDBG_CTYPR 0xD04
@@ -38,7 +38,7 @@ struct aarch64_brp {
};
struct aarch64_common {
- int common_magic;
+ unsigned int common_magic;
/* Context information */
uint32_t system_control_reg;
diff --git a/src/target/arc.h b/src/target/arc.h
index 86d8d09d5..bb70a598e 100644
--- a/src/target/arc.h
+++ b/src/target/arc.h
@@ -27,7 +27,7 @@
#include "arc_cmd.h"
#include "arc_mem.h"
-#define ARC_COMMON_MAGIC 0xB32EB324 /* just a unique number */
+#define ARC_COMMON_MAGIC 0xB32EB324U /* just a unique number */
#define AUX_DEBUG_REG 0x5
#define AUX_PC_REG 0x6
@@ -183,7 +183,7 @@ struct arc_actionpoint {
};
struct arc_common {
- uint32_t common_magic;
+ unsigned int common_magic;
struct arc_jtag jtag_info;
diff --git a/src/target/arm.h b/src/target/arm.h
index e264293f4..f262255ab 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -155,7 +155,7 @@ enum arm_vfp_version {
ARM_VFP_V3,
};
-#define ARM_COMMON_MAGIC 0x0A450A45
+#define ARM_COMMON_MAGIC 0x0A450A45U
/**
* Represents a generic ARM core, with standard application registers.
@@ -165,7 +165,8 @@ enum arm_vfp_version {
* registers as traditional ARM cores, and only support Thumb2 instructions.
*/
struct arm {
- int common_magic;
+ unsigned int common_magic;
+
struct reg_cache *core_cache;
/** Handle to the PC; valid in all core modes. */
@@ -252,7 +253,7 @@ static inline bool is_arm(struct arm *arm)
}
struct arm_algorithm {
- int common_magic;
+ unsigned int common_magic;
enum arm_mode core_mode;
enum arm_state core_state;
diff --git a/src/target/arm720t.h b/src/target/arm720t.h
index 81c6e1f6a..65bd78ff0 100644
--- a/src/target/arm720t.h
+++ b/src/target/arm720t.h
@@ -11,11 +11,12 @@
#include "arm7tdmi.h"
#include "armv4_5_mmu.h"
-#define ARM720T_COMMON_MAGIC 0xa720a720
+#define ARM720T_COMMON_MAGIC 0xa720a720U
struct arm720t_common {
+ unsigned int common_magic;
+
struct arm7_9_common arm7_9_common;
- uint32_t common_magic;
struct armv4_5_mmu_common armv4_5_mmu;
uint32_t cp15_control_reg;
uint32_t fsr_reg;
diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h
index 805fbc918..92d0fd51a 100644
--- a/src/target/arm7_9_common.h
+++ b/src/target/arm7_9_common.h
@@ -20,14 +20,15 @@
#include "arm.h"
#include "arm_jtag.h"
-#define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
+#define ARM7_9_COMMON_MAGIC 0x0a790a79U /**< */
/**
* Structure for items that are common between both ARM7 and ARM9 targets.
*/
struct arm7_9_common {
+ unsigned int common_magic;
+
struct arm arm;
- uint32_t common_magic;
struct arm_jtag jtag_info; /**< JTAG information for target */
struct reg_cache *eice_cache; /**< Embedded ICE register cache */
diff --git a/src/target/arm920t.h b/src/target/arm920t.h
index 49ec3c000..eba768fff 100644
--- a/src/target/arm920t.h
+++ b/src/target/arm920t.h
@@ -11,11 +11,12 @@
#include "arm9tdmi.h"
#include "armv4_5_mmu.h"
-#define ARM920T_COMMON_MAGIC 0xa920a920
+#define ARM920T_COMMON_MAGIC 0xa920a920U
struct arm920t_common {
+ unsigned int common_magic;
+
struct arm7_9_common arm7_9_common;
- uint32_t common_magic;
struct armv4_5_mmu_common armv4_5_mmu;
uint32_t cp15_control_reg;
uint32_t d_fsr;
diff --git a/src/target/arm926ejs.h b/src/target/arm926ejs.h
index c652a3b09..479128e61 100644
--- a/src/target/arm926ejs.h
+++ b/src/target/arm926ejs.h
@@ -11,11 +11,12 @@
#include "arm9tdmi.h"
#include "armv4_5_mmu.h"
-#define ARM926EJS_COMMON_MAGIC 0xa926a926
+#define ARM926EJS_COMMON_MAGIC 0xa926a926U
struct arm926ejs_common {
+ unsigned int common_magic;
+
struct arm7_9_common arm7_9_common;
- uint32_t common_magic;
struct armv4_5_mmu_common armv4_5_mmu;
int (*read_cp15)(struct target *target, uint32_t op1, uint32_t op2,
uint32_t crn, uint32_t crm, uint32_t *value);
diff --git a/src/target/arm946e.h b/src/target/arm946e.h
index b205534fd..741687869 100644
--- a/src/target/arm946e.h
+++ b/src/target/arm946e.h
@@ -16,11 +16,12 @@
#include "arm9tdmi.h"
-#define ARM946E_COMMON_MAGIC 0x20f920f9
+#define ARM946E_COMMON_MAGIC 0x20f920f9U
struct arm946e_common {
+ unsigned int common_magic;
+
struct arm7_9_common arm7_9_common;
- int common_magic;
uint32_t cp15_control_reg;
uint32_t cp15_cache_info;
};
diff --git a/src/target/arm966e.h b/src/target/arm966e.h
index e41b85037..be2b3391e 100644
--- a/src/target/arm966e.h
+++ b/src/target/arm966e.h
@@ -13,11 +13,12 @@
#include "arm9tdmi.h"
-#define ARM966E_COMMON_MAGIC 0x20f920f9
+#define ARM966E_COMMON_MAGIC 0x20f920f9U
struct arm966e_common {
+ unsigned int common_magic;
+
struct arm7_9_common arm7_9_common;
- int common_magic;
uint32_t cp15_control_reg;
};
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index ebd38f0f6..6b9c2a68f 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -19,7 +19,7 @@ enum {
ARM_CPSR = 16
};
-#define ARMV7_COMMON_MAGIC 0x0A450999
+#define ARMV7_COMMON_MAGIC 0x0A450999U
/* VA to PA translation operations opc2 values*/
#define V2PCWPR 0
@@ -87,8 +87,9 @@ struct armv7a_mmu_common {
};
struct armv7a_common {
+ unsigned int common_magic;
+
struct arm arm;
- int common_magic;
struct reg_cache *core_cache;
/* Core Debug Unit */
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 6d97e4ac5..9ac6b9ec9 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -215,12 +215,13 @@ enum {
#define ARMV7M_NUM_CORE_REGS (ARMV7M_CORE_LAST_REG - ARMV7M_CORE_FIRST_REG + 1)
-#define ARMV7M_COMMON_MAGIC 0x2A452A45
+#define ARMV7M_COMMON_MAGIC 0x2A452A45U
struct armv7m_common {
+ unsigned int common_magic;
+
struct arm arm;
- int common_magic;
int exception_number;
/* AP this processor is connected to in the DAP */
@@ -289,7 +290,7 @@ target_to_armv7m_safe(struct target *target)
}
struct armv7m_algorithm {
- int common_magic;
+ unsigned int common_magic;
enum arm_mode core_mode;
diff --git a/src/target/armv8.h b/src/target/armv8.h
index 912da675c..e06067175 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -108,7 +108,7 @@ enum run_control_op {
ARMV8_RUNCONTROL_STEP = 3,
};
-#define ARMV8_COMMON_MAGIC 0x0A450AAA
+#define ARMV8_COMMON_MAGIC 0x0A450AAAU
/* VA to PA translation operations opc2 values*/
#define V2PCWPR 0
@@ -178,8 +178,9 @@ struct armv8_mmu_common {
};
struct armv8_common {
+ unsigned int common_magic;
+
struct arm arm;
- int common_magic;
struct reg_cache *core_cache;
/* Core Debug Unit */
diff --git a/src/target/avr32_ap7k.h b/src/target/avr32_ap7k.h
index 6984b6101..ac35754f4 100644
--- a/src/target/avr32_ap7k.h
+++ b/src/target/avr32_ap7k.h
@@ -9,9 +9,11 @@
struct target;
-#define AP7K_COMMON_MAGIC 0x4150374b
+#define AP7K_COMMON_MAGIC 0x4150374bU
+
struct avr32_ap7k_common {
- int common_magic;
+ unsigned int common_magic;
+
struct avr32_jtag jtag;
struct reg_cache *core_cache;
uint32_t core_regs[AVR32NUMCOREREGS];
diff --git a/src/target/cortex_a.h b/src/target/cortex_a.h
index 05c3730c2..656ccea8a 100644
--- a/src/target/cortex_a.h
+++ b/src/target/cortex_a.h
@@ -19,7 +19,7 @@
#include "armv7a.h"
-#define CORTEX_A_COMMON_MAGIC 0x411fc082
+#define CORTEX_A_COMMON_MAGIC 0x411fc082U
#define CORTEX_A5_PARTNUM 0xc05
#define CORTEX_A7_PARTNUM 0xc07
@@ -67,7 +67,7 @@ struct cortex_a_wrp {
};
struct cortex_a_common {
- int common_magic;
+ unsigned int common_magic;
/* Context information */
uint32_t cpudbg_dscr;
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 3f0d55c1c..54767c5df 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -17,7 +17,7 @@
#include "armv7m.h"
#include "helper/bits.h"
-#define CORTEX_M_COMMON_MAGIC 0x1A451A45
+#define CORTEX_M_COMMON_MAGIC 0x1A451A45U
#define SYSTEM_CONTROL_BASE 0x400FE000
@@ -199,7 +199,7 @@ enum cortex_m_isrmasking_mode {
};
struct cortex_m_common {
- int common_magic;
+ unsigned int common_magic;
/* Context information */
uint32_t dcb_dhcsr;
diff --git a/src/target/mips32.h b/src/target/mips32.h
index ca02dda45..8837da1d0 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -16,7 +16,7 @@
#include "target.h"
#include "mips32_pracc.h"
-#define MIPS32_COMMON_MAGIC 0xB320B320
+#define MIPS32_COMMON_MAGIC 0xB320B320U
/**
* Memory segments (32bit kernel mode addresses)
@@ -82,7 +82,8 @@ struct mips32_comparator {
};
struct mips32_common {
- uint32_t common_magic;
+ unsigned int common_magic;
+
void *arch_info;
struct reg_cache *core_cache;
struct mips_ejtag ejtag_info;
@@ -119,7 +120,7 @@ struct mips32_core_reg {
};
struct mips32_algorithm {
- int common_magic;
+ unsigned int common_magic;
enum mips32_isa_mode isa_mode;
};
diff --git a/src/target/mips64.h b/src/target/mips64.h
index 3453e4ed1..9079c8013 100644
--- a/src/target/mips64.h
+++ b/src/target/mips64.h
@@ -19,7 +19,7 @@
#include "register.h"
#include "mips64_pracc.h"
-#define MIPS64_COMMON_MAGIC 0xB640B640
+#define MIPS64_COMMON_MAGIC 0xB640B640U
/* MIPS64 CP0 registers */
#define MIPS64_C0_INDEX 0
@@ -81,7 +81,8 @@ struct mips64_comparator {
};
struct mips64_common {
- uint32_t common_magic;
+ unsigned int common_magic;
+
void *arch_info;
struct reg_cache *core_cache;
struct mips_ejtag ejtag_info;
diff --git a/src/target/mips_m4k.h b/src/target/mips_m4k.h
index ae4a0ff72..b563ea513 100644
--- a/src/target/mips_m4k.h
+++ b/src/target/mips_m4k.h
@@ -15,10 +15,11 @@
struct target;
-#define MIPSM4K_COMMON_MAGIC 0xB321B321
+#define MIPSM4K_COMMON_MAGIC 0xB321B321U
struct mips_m4k_common {
- uint32_t common_magic;
+ unsigned int common_magic;
+
bool is_pic32mx;
struct mips32_common mips32;
};
diff --git a/src/target/mips_mips64.h b/src/target/mips_mips64.h
index 69fb2a6f9..9841deb2f 100644
--- a/src/target/mips_mips64.h
+++ b/src/target/mips_mips64.h
@@ -17,7 +17,8 @@
#include "helper/types.h"
struct mips_mips64_common {
- int common_magic;
+ unsigned int common_magic;
+
struct mips64_common mips64_common;
};
diff --git a/src/target/nds32.h b/src/target/nds32.h
index 1c8675e73..d0b680a97 100644
--- a/src/target/nds32.h
+++ b/src/target/nds32.h
@@ -224,7 +224,8 @@ struct nds32_misc_config {
* Represents a generic Andes core.
*/
struct nds32 {
- uint32_t common_magic;
+ unsigned int common_magic;
+
struct reg_cache *core_cache;
/** Handle for the debug module. */
diff --git a/src/target/stm8.h b/src/target/stm8.h
index bbda4feb6..55e1071ab 100644
--- a/src/target/stm8.h
+++ b/src/target/stm8.h
@@ -11,11 +11,12 @@
struct target;
-#define STM8_COMMON_MAGIC 0x53544D38
+#define STM8_COMMON_MAGIC 0x53544D38U
#define STM8_NUM_CORE_REGS 6
struct stm8_common {
- uint32_t common_magic;
+ unsigned int common_magic;
+
void *arch_info;
struct reg_cache *core_cache;
uint32_t core_regs[STM8_NUM_CORE_REGS];
diff --git a/src/target/x86_32_common.h b/src/target/x86_32_common.h
index 4f90ab4e6..7392447a6 100644
--- a/src/target/x86_32_common.h
+++ b/src/target/x86_32_common.h
@@ -148,7 +148,7 @@ enum {
PMCR,
};
-#define X86_32_COMMON_MAGIC 0x86328632
+#define X86_32_COMMON_MAGIC 0x86328632U
enum {
/* memory read/write */
@@ -200,7 +200,8 @@ struct swbp_mem_patch {
#define NUM_PM_REGS 18 /* regs used in save/restore */
struct x86_32_common {
- uint32_t common_magic;
+ unsigned int common_magic;
+
void *arch_info;
enum x86_core_type core_type;
struct reg_cache *cache;
diff --git a/src/target/xscale.h b/src/target/xscale.h
index 0087b8a43..36a69bca3 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -15,7 +15,7 @@
#include "armv4_5_mmu.h"
#include "trace.h"
-#define XSCALE_COMMON_MAGIC 0x58534341
+#define XSCALE_COMMON_MAGIC 0x58534341U
/* These four JTAG instructions are architecturally defined.
* Lengths are core-specific; originally 5 bits, later 7.
@@ -71,11 +71,11 @@ struct xscale_trace {
};
struct xscale_common {
+ unsigned int common_magic;
+
/* armv4/5 common stuff */
struct arm arm;
- int common_magic;
-
/* XScale registers (CP15, DBG) */
struct reg_cache *reg_cache;
-----------------------------------------------------------------------
Summary of changes:
src/target/aarch64.h | 4 ++--
src/target/arc.h | 4 ++--
src/target/arm.h | 7 ++++---
src/target/arm720t.h | 5 +++--
src/target/arm7_9_common.h | 5 +++--
src/target/arm920t.h | 5 +++--
src/target/arm926ejs.h | 5 +++--
src/target/arm946e.h | 5 +++--
src/target/arm966e.h | 5 +++--
src/target/armv7a.h | 5 +++--
src/target/armv7m.h | 7 ++++---
src/target/armv8.h | 5 +++--
src/target/avr32_ap7k.h | 6 ++++--
src/target/cortex_a.h | 4 ++--
src/target/cortex_m.h | 4 ++--
src/target/mips32.h | 7 ++++---
src/target/mips64.h | 5 +++--
src/target/mips_m4k.h | 5 +++--
src/target/mips_mips64.h | 3 ++-
src/target/nds32.h | 3 ++-
src/target/stm8.h | 5 +++--
src/target/x86_32_common.h | 5 +++--
src/target/xscale.h | 6 +++---
23 files changed, 67 insertions(+), 48 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-08-08 20:53:17
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b76a7a82b20fcf265a7b211e6ef97b759a8cb714 (commit)
from 2aaa991a503dc28b087d81b59531c66931ad74d8 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit b76a7a82b20fcf265a7b211e6ef97b759a8cb714
Author: Tomas Vanek <va...@fb...>
Date: Sun Jul 31 08:01:23 2022 +0200
flash/nor: remove useless setting of bus_width and chip_width
The flash/nor subsystem uses bus_width and chip_width for CFI
external flash only. Drop setting these values for internal flash.
Change-Id: I64e79ab38b6e39e845ff96fbf4f60145e3b9690a
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7098
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/at91sam7.c b/src/flash/nor/at91sam7.c
index fac8bb378..e18635b6d 100644
--- a/src/flash/nor/at91sam7.c
+++ b/src/flash/nor/at91sam7.c
@@ -576,8 +576,6 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
t_bank->bank_number = bnk;
t_bank->base = base_address + bnk * bank_size;
t_bank->size = bank_size;
- t_bank->chip_width = 0;
- t_bank->bus_width = 4;
t_bank->num_sectors = sectors_num;
/* allocate sectors */
@@ -691,8 +689,6 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
uint32_t bank_size;
uint32_t ext_freq = 0;
- unsigned int chip_width;
- unsigned int bus_width;
unsigned int banks_num;
unsigned int num_sectors;
@@ -716,9 +712,6 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], base_address);
- COMMAND_PARSE_NUMBER(uint, CMD_ARGV[3], chip_width);
- COMMAND_PARSE_NUMBER(uint, CMD_ARGV[4], bus_width);
-
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[8], banks_num);
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[9], num_sectors);
COMMAND_PARSE_NUMBER(u16, CMD_ARGV[10], pages_per_sector);
@@ -732,7 +725,7 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
at91sam7_info->ext_freq = ext_freq;
}
- if ((bus_width == 0) || (banks_num == 0) || (num_sectors == 0) ||
+ if ((banks_num == 0) || (num_sectors == 0) ||
(pages_per_sector == 0) || (page_size == 0) || (num_nvmbits == 0)) {
at91sam7_info->flash_autodetection = 1;
return ERROR_OK;
@@ -761,8 +754,6 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
t_bank->bank_number = bnk;
t_bank->base = base_address + bnk * bank_size;
t_bank->size = bank_size;
- t_bank->chip_width = chip_width;
- t_bank->bus_width = bus_width;
t_bank->num_sectors = num_sectors;
/* allocate sectors */
diff --git a/src/flash/nor/psoc6.c b/src/flash/nor/psoc6.c
index ce615fc2a..da07d8487 100644
--- a/src/flash/nor/psoc6.c
+++ b/src/flash/nor/psoc6.c
@@ -591,8 +591,7 @@ static int psoc6_probe(struct flash_bank *bank)
unsigned int num_sectors = bank_size / row_sz;
bank->size = bank_size;
- bank->chip_width = 4;
- bank->bus_width = 4;
+
bank->erased_value = 0;
bank->default_padded_value = 0;
diff --git a/src/flash/nor/tms470.c b/src/flash/nor/tms470.c
index 7b24fff1c..9fffae90a 100644
--- a/src/flash/nor/tms470.c
+++ b/src/flash/nor/tms470.c
@@ -248,9 +248,6 @@ static int tms470_read_part_info(struct flash_bank *bank)
target_write_u32(target, 0xFFFFFFE4, 0x00000000);
target_write_u32(target, 0xFFFFFFE0, 0x00000000);
- bank->chip_width = 32;
- bank->bus_width = 32;
-
LOG_INFO("Identified %s, ver=%d, core=%s, nvmem=%s.",
part_name,
(int)(silicon_version),
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/at91sam7.c | 11 +----------
src/flash/nor/psoc6.c | 3 +--
src/flash/nor/tms470.c | 3 ---
3 files changed, 2 insertions(+), 15 deletions(-)
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