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From: OpenOCD-Gerrit <ope...@us...> - 2022-09-13 22:07:03
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a126229dff2ee0b20b0c7dace7e523633cc6607e (commit)
from d8042fbb46e09704c4b613a656fea09bf1b827a7 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit a126229dff2ee0b20b0c7dace7e523633cc6607e
Author: Antonio Borneo <bor...@gm...>
Date: Tue Aug 30 22:18:31 2022 +0200
contrib: replace the GPLv2-or-later license tag
Replace the GPLv2-or-later boilerplate with the SPDX tag.
The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.
Change-Id: I380d552940f1c405309a3346454251c0e80b5a45
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7159
Tested-by: jenkins
diff --git a/contrib/libdcc/dcc_stdio.c b/contrib/libdcc/dcc_stdio.c
index 7da78c647..eab050eaf 100644
--- a/contrib/libdcc/dcc_stdio.c
+++ b/contrib/libdcc/dcc_stdio.c
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2008 by Dominic Rath *
* Dom...@gm... *
@@ -5,19 +7,6 @@
* sp...@sp... *
* Copyright (C) 2008 by Frederik Kriewtz *
* fre...@kr... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#include "dcc_stdio.h"
diff --git a/contrib/libdcc/dcc_stdio.h b/contrib/libdcc/dcc_stdio.h
index f4a5d7e32..3447b8c6b 100644
--- a/contrib/libdcc/dcc_stdio.h
+++ b/contrib/libdcc/dcc_stdio.h
@@ -1,21 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2008 by Dominic Rath *
* Dom...@gm... *
* Copyright (C) 2008 by Spencer Oliver *
* sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifndef DCC_STDIO_H
diff --git a/contrib/libdcc/example.c b/contrib/libdcc/example.c
index 99b7bf602..e8b275a94 100644
--- a/contrib/libdcc/example.c
+++ b/contrib/libdcc/example.c
@@ -1,21 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2008 by Spencer Oliver *
* sp...@sp... *
* Copyright (C) 2008 by Frederik Kriewtz *
* fre...@kr... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#include "dcc_stdio.h"
diff --git a/contrib/loaders/checksum/armv4_5_crc.s b/contrib/loaders/checksum/armv4_5_crc.s
index 8f62dc89f..b3ecb5847 100644
--- a/contrib/loaders/checksum/armv4_5_crc.s
+++ b/contrib/loaders/checksum/armv4_5_crc.s
@@ -1,21 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/*
diff --git a/contrib/loaders/checksum/armv7m_crc.s b/contrib/loaders/checksum/armv7m_crc.s
index 923875a08..8cb7f2dc1 100644
--- a/contrib/loaders/checksum/armv7m_crc.s
+++ b/contrib/loaders/checksum/armv7m_crc.s
@@ -1,21 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/*
diff --git a/contrib/loaders/checksum/mips32.s b/contrib/loaders/checksum/mips32.s
index 3073d87a3..52de547b4 100644
--- a/contrib/loaders/checksum/mips32.s
+++ b/contrib/loaders/checksum/mips32.s
@@ -1,21 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.global main
diff --git a/contrib/loaders/debug/xscale/debug_handler.S b/contrib/loaders/debug/xscale/debug_handler.S
index 0f62d9c14..9e1d65f93 100644
--- a/contrib/loaders/debug/xscale/debug_handler.S
+++ b/contrib/loaders/debug/xscale/debug_handler.S
@@ -1,19 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2006 by Dominic Rath *
* Dom...@gm... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#include "protocol.h"
diff --git a/contrib/loaders/debug/xscale/protocol.h b/contrib/loaders/debug/xscale/protocol.h
index cb01655ee..bd29cf12f 100644
--- a/contrib/loaders/debug/xscale/protocol.h
+++ b/contrib/loaders/debug/xscale/protocol.h
@@ -1,19 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2006 by Dominic Rath *
* Dom...@gm... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#define REG_R0 0
diff --git a/contrib/loaders/erase_check/armv4_5_erase_check.s b/contrib/loaders/erase_check/armv4_5_erase_check.s
index 6c7d27f05..dedadaa5d 100644
--- a/contrib/loaders/erase_check/armv4_5_erase_check.s
+++ b/contrib/loaders/erase_check/armv4_5_erase_check.s
@@ -1,21 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/*
diff --git a/contrib/loaders/erase_check/armv7m_erase_check.s b/contrib/loaders/erase_check/armv7m_erase_check.s
index 3303c8778..429b6939f 100644
--- a/contrib/loaders/erase_check/armv7m_erase_check.s
+++ b/contrib/loaders/erase_check/armv7m_erase_check.s
@@ -1,21 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/*
diff --git a/contrib/loaders/erase_check/stm8_erase_check.s b/contrib/loaders/erase_check/stm8_erase_check.s
index 04cde5b1b..116ac59f1 100644
--- a/contrib/loaders/erase_check/stm8_erase_check.s
+++ b/contrib/loaders/erase_check/stm8_erase_check.s
@@ -1,20 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/*
-* Copyright (C) 2017 Ake Rehnman
-* ake.rehnman(at)gmail.com
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see <http://www.gnu.org/licenses/>.
-*/
+ * Copyright (C) 2017 Ake Rehnman
+ * ake.rehnman(at)gmail.com
+ */
;;
;; erase check memory code
;;
diff --git a/contrib/loaders/flash/armv4_5_cfi_intel_16.s b/contrib/loaders/flash/armv4_5_cfi_intel_16.s
index c35b6515f..0c5611dc5 100644
--- a/contrib/loaders/flash/armv4_5_cfi_intel_16.s
+++ b/contrib/loaders/flash/armv4_5_cfi_intel_16.s
@@ -1,23 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dom...@gm... *
* Copyright (C) 2010 Spencer Oliver *
* sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
diff --git a/contrib/loaders/flash/armv4_5_cfi_intel_32.s b/contrib/loaders/flash/armv4_5_cfi_intel_32.s
index db477178a..473a78234 100644
--- a/contrib/loaders/flash/armv4_5_cfi_intel_32.s
+++ b/contrib/loaders/flash/armv4_5_cfi_intel_32.s
@@ -1,23 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dom...@gm... *
* Copyright (C) 2010 Spencer Oliver *
* sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
diff --git a/contrib/loaders/flash/armv4_5_cfi_intel_8.s b/contrib/loaders/flash/armv4_5_cfi_intel_8.s
index d50acd2ad..18f4bb811 100644
--- a/contrib/loaders/flash/armv4_5_cfi_intel_8.s
+++ b/contrib/loaders/flash/armv4_5_cfi_intel_8.s
@@ -1,23 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dom...@gm... *
* Copyright (C) 2010 Spencer Oliver *
* sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
diff --git a/contrib/loaders/flash/armv4_5_cfi_span_16.s b/contrib/loaders/flash/armv4_5_cfi_span_16.s
index 532727140..da02037f6 100644
--- a/contrib/loaders/flash/armv4_5_cfi_span_16.s
+++ b/contrib/loaders/flash/armv4_5_cfi_span_16.s
@@ -1,23 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dom...@gm... *
* Copyright (C) 2010 Spencer Oliver *
* sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
diff --git a/contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s b/contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s
index 919f6e164..fb7679e4c 100644
--- a/contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s
+++ b/contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s
@@ -1,23 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dom...@gm... *
* Copyright (C) 2010 Spencer Oliver *
* sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
diff --git a/contrib/loaders/flash/armv4_5_cfi_span_32.s b/contrib/loaders/flash/armv4_5_cfi_span_32.s
index c8f87b12b..7e377e25f 100644
--- a/contrib/loaders/flash/armv4_5_cfi_span_32.s
+++ b/contrib/loaders/flash/armv4_5_cfi_span_32.s
@@ -1,23 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dom...@gm... *
* Copyright (C) 2010 Spencer Oliver *
* sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
diff --git a/contrib/loaders/flash/armv4_5_cfi_span_8.s b/contrib/loaders/flash/armv4_5_cfi_span_8.s
index 46018e18b..ad4ee267b 100644
--- a/contrib/loaders/flash/armv4_5_cfi_span_8.s
+++ b/contrib/loaders/flash/armv4_5_cfi_span_8.s
@@ -1,23 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dom...@gm... *
* Copyright (C) 2010 Spencer Oliver *
* sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
diff --git a/contrib/loaders/flash/armv7m_cfi_span_16.s b/contrib/loaders/flash/armv7m_cfi_span_16.s
index d4915a78c..0a5279e3d 100644
--- a/contrib/loaders/flash/armv7m_cfi_span_16.s
+++ b/contrib/loaders/flash/armv7m_cfi_span_16.s
@@ -1,23 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dom...@gm... *
* Copyright (C) 2010 Spencer Oliver *
* sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
diff --git a/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s b/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s
index 5b29a3bda..592c811bc 100644
--- a/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s
+++ b/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s
@@ -1,23 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dom...@gm... *
* Copyright (C) 2010 Spencer Oliver *
* sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
diff --git a/contrib/loaders/flash/armv7m_io.s b/contrib/loaders/flash/armv7m_io.s
index f6dbbe9bf..9d8439e1a 100644
--- a/contrib/loaders/flash/armv7m_io.s
+++ b/contrib/loaders/flash/armv7m_io.s
@@ -1,21 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2013 by Henrik Nilsson *
* hen...@by... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
diff --git a/contrib/loaders/flash/at91sam7x/dcc.c b/contrib/loaders/flash/at91sam7x/dcc.c
index a5c32e7e6..fea88f6a1 100644
--- a/contrib/loaders/flash/at91sam7x/dcc.c
+++ b/contrib/loaders/flash/at91sam7x/dcc.c
@@ -1,19 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* ch...@as... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#include "dcc.h"
diff --git a/contrib/loaders/flash/at91sam7x/dcc.h b/contrib/loaders/flash/at91sam7x/dcc.h
index 428bf49ff..5baca6ca1 100644
--- a/contrib/loaders/flash/at91sam7x/dcc.h
+++ b/contrib/loaders/flash/at91sam7x/dcc.h
@@ -1,19 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* ch...@as... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifndef dccH
#define dccH
diff --git a/contrib/loaders/flash/at91sam7x/main.c b/contrib/loaders/flash/at91sam7x/main.c
index 47c944082..b896d2bf2 100644
--- a/contrib/loaders/flash/at91sam7x/main.c
+++ b/contrib/loaders/flash/at91sam7x/main.c
@@ -1,19 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* ch...@as... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#include "platform.h"
diff --git a/contrib/loaders/flash/at91sam7x/ocl.h b/contrib/loaders/flash/at91sam7x/ocl.h
index bd8a5f7a0..e458b5864 100644
--- a/contrib/loaders/flash/at91sam7x/ocl.h
+++ b/contrib/loaders/flash/at91sam7x/ocl.h
@@ -1,19 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* ch...@as... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifndef OCL_H
#define OCL_H
diff --git a/contrib/loaders/flash/at91sam7x/platform.h b/contrib/loaders/flash/at91sam7x/platform.h
index 3dfa4dc08..538df9b48 100644
--- a/contrib/loaders/flash/at91sam7x/platform.h
+++ b/contrib/loaders/flash/at91sam7x/platform.h
@@ -1,19 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* ch...@as... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifndef platformH
#define platformH
diff --git a/contrib/loaders/flash/at91sam7x/samflash.c b/contrib/loaders/flash/at91sam7x/samflash.c
index 30953942a..6e4c49575 100644
--- a/contrib/loaders/flash/at91sam7x/samflash.c
+++ b/contrib/loaders/flash/at91sam7x/samflash.c
@@ -1,19 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* ch...@as... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#include "samflash.h"
diff --git a/contrib/loaders/flash/at91sam7x/samflash.h b/contrib/loaders/flash/at91sam7x/samflash.h
index 18973a70d..059c2b2ea 100644
--- a/contrib/loaders/flash/at91sam7x/samflash.h
+++ b/contrib/loaders/flash/at91sam7x/samflash.h
@@ -1,19 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* ch...@as... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifndef samflashH
#define samflashH
diff --git a/contrib/loaders/flash/cc3220sf/cc3220sf.s b/contrib/loaders/flash/cc3220sf/cc3220sf.s
index cffcfa053..ea82c85a7 100644
--- a/contrib/loaders/flash/cc3220sf/cc3220sf.s
+++ b/contrib/loaders/flash/cc3220sf/cc3220sf.s
@@ -1,18 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2017 by Texas Instruments, Inc. *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
/* Params:
diff --git a/contrib/loaders/flash/cortex-m0.S b/contrib/loaders/flash/cortex-m0.S
index b4416e783..74b071dca 100644
--- a/contrib/loaders/flash/cortex-m0.S
+++ b/contrib/loaders/flash/cortex-m0.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2014 by Angus Gratton *
* Derived from stm32f1x.S:
@@ -5,19 +7,6 @@
* and...@gm... *
* Copyright (C) 2013 by Roman Dmitrienko *
* me...@ia... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
.text
.syntax unified
diff --git a/contrib/loaders/flash/efm32.S b/contrib/loaders/flash/efm32.S
index c5de55c27..b6938512a 100644
--- a/contrib/loaders/flash/efm32.S
+++ b/contrib/loaders/flash/efm32.S
@@ -1,23 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2011 by Andreas Fritiofson *
* and...@gm... *
* Copyright (C) 2013 by Roman Dmitrienko *
* me...@ia... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
diff --git a/contrib/loaders/flash/fpga/xilinx_bscan_spi.py b/contrib/loaders/flash/fpga/xilinx_bscan_spi.py
index 4246aa2f3..408cfdd79 100755
--- a/contrib/loaders/flash/fpga/xilinx_bscan_spi.py
+++ b/contrib/loaders/flash/fpga/xilinx_bscan_spi.py
@@ -1,17 +1,7 @@
#!/usr/bin/python3
-#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# Copyright (C) 2015 Robert Jordens <jo...@gm...>
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
import unittest
diff --git a/contrib/loaders/flash/k1921vk01t.S b/contrib/loaders/flash/k1921vk01t.S
index b8f0b53d5..d8e3cd6fa 100644
--- a/contrib/loaders/flash/k1921vk01t.S
+++ b/contrib/loaders/flash/k1921vk01t.S
@@ -1,20 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2015 by Bogdan Kolbov *
* ko...@ni... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc. *
***************************************************************************/
.text
diff --git a/contrib/loaders/flash/kinetis/kinetis_flash.s b/contrib/loaders/flash/kinetis/kinetis_flash.s
index c8e6e05a8..5b9d3c69c 100644
--- a/contrib/loaders/flash/kinetis/kinetis_flash.s
+++ b/contrib/loaders/flash/kinetis/kinetis_flash.s
@@ -1,19 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2015 by Ivan Meleca *
* iv...@ar... *
* *
* Copyright (C) 2016 by Tomas Vanek *
* va...@fb... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
***************************************************************************/
/* Params:
diff --git a/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.s b/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.s
index 1fa761336..f082b4649 100644
--- a/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.s
+++ b/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.s
@@ -1,16 +1,8 @@
+...
[truncated message content] |
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-09-13 22:06:19
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via d8042fbb46e09704c4b613a656fea09bf1b827a7 (commit)
via 2d48b8e012cf99f53cdd2a9130167c075717c7d7 (commit)
from 25a374a187d760eddb87cbe639cb885b159b74b4 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit d8042fbb46e09704c4b613a656fea09bf1b827a7
Author: Antonio Borneo <bor...@gm...>
Date: Tue Aug 30 23:21:52 2022 +0200
contrib: replace the BSD-3-Clause license tag
Replace the BSD-3-Clause boilerplate with the SPDX tag.
Add the SPDX tag and the copyright to two makefiles that were
added by TI with the other files in their respective folder.
The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.
Change-Id: I3ad1b2dbdb6054b74dcc26e394c9223ba0427caf
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7158
Tested-by: jenkins
diff --git a/contrib/loaders/flash/at91sam7x/at91sam7x_ram.ld b/contrib/loaders/flash/at91sam7x/at91sam7x_ram.ld
index 8cb21184f..b09352378 100644
--- a/contrib/loaders/flash/at91sam7x/at91sam7x_ram.ld
+++ b/contrib/loaders/flash/at91sam7x/at91sam7x_ram.ld
@@ -1,32 +1,7 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/****************************************************************************
* Copyright (c) 2006 by Michael Fischer. All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* 1. Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* 2. Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* 3. Neither the name of the author nor the names of its contributors may
-* be used to endorse or promote products derived from this software
-* without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
-* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-* SUCH DAMAGE.
-*
****************************************************************************
*
* History:
diff --git a/contrib/loaders/flash/at91sam7x/crt.s b/contrib/loaders/flash/at91sam7x/crt.s
index 94ed66d73..77df43ce2 100644
--- a/contrib/loaders/flash/at91sam7x/crt.s
+++ b/contrib/loaders/flash/at91sam7x/crt.s
@@ -1,32 +1,7 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/****************************************************************************
* Copyright (c) 2006 by Michael Fischer. All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* 1. Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* 2. Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* 3. Neither the name of the author nor the names of its contributors may
-* be used to endorse or promote products derived from this software
-* without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
-* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-* SUCH DAMAGE.
-*
****************************************************************************
*
* History:
diff --git a/contrib/loaders/flash/at91sam7x/samregs.h b/contrib/loaders/flash/at91sam7x/samregs.h
index b206fd28e..3e34a8d6d 100644
--- a/contrib/loaders/flash/at91sam7x/samregs.h
+++ b/contrib/loaders/flash/at91sam7x/samregs.h
@@ -1,32 +1,8 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/*
* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the copyright holders nor the names of
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
- * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
- * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
* For additional information see http://www.ethernut.de/
*/
diff --git a/contrib/loaders/flash/cc26xx/Makefile b/contrib/loaders/flash/cc26xx/Makefile
index 7cc1fb3c4..550e1d098 100644
--- a/contrib/loaders/flash/cc26xx/Makefile
+++ b/contrib/loaders/flash/cc26xx/Makefile
@@ -1,3 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+
BIN2C = ../../../../src/helper/bin2char.sh
CROSS_COMPILE ?= arm-none-eabi-
diff --git a/contrib/loaders/flash/cc26xx/cc26x0/cc26x0r2f.lds b/contrib/loaders/flash/cc26xx/cc26x0/cc26x0r2f.lds
index 9a126fc2b..79cbfc4fc 100644
--- a/contrib/loaders/flash/cc26xx/cc26x0/cc26x0r2f.lds
+++ b/contrib/loaders/flash/cc26xx/cc26x0/cc26x0r2f.lds
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
/* Entry Point */
diff --git a/contrib/loaders/flash/cc26xx/cc26x2/cc26x2r1f.lds b/contrib/loaders/flash/cc26xx/cc26x2/cc26x2r1f.lds
index fb7cc5611..2394c0cc0 100644
--- a/contrib/loaders/flash/cc26xx/cc26x2/cc26x2r1f.lds
+++ b/contrib/loaders/flash/cc26xx/cc26x2/cc26x2r1f.lds
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
/* Entry Point */
diff --git a/contrib/loaders/flash/cc26xx/flash.c b/contrib/loaders/flash/cc26xx/flash.c
index c19cb735d..3aba82cba 100644
--- a/contrib/loaders/flash/cc26xx/flash.c
+++ b/contrib/loaders/flash/cc26xx/flash.c
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#include <stdint.h>
diff --git a/contrib/loaders/flash/cc26xx/flash.h b/contrib/loaders/flash/cc26xx/flash.h
index dd0a3745a..07acf26f2 100644
--- a/contrib/loaders/flash/cc26xx/flash.h
+++ b/contrib/loaders/flash/cc26xx/flash.h
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#ifndef OPENOCD_LOADERS_FLASH_CC26XX_FLASH_H
diff --git a/contrib/loaders/flash/cc26xx/flashloader.c b/contrib/loaders/flash/cc26xx/flashloader.c
index 2eaf61864..ef3a4fccf 100644
--- a/contrib/loaders/flash/cc26xx/flashloader.c
+++ b/contrib/loaders/flash/cc26xx/flashloader.c
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#include <stdint.h>
diff --git a/contrib/loaders/flash/cc26xx/flashloader.h b/contrib/loaders/flash/cc26xx/flashloader.h
index aec74aaa9..a6695576e 100644
--- a/contrib/loaders/flash/cc26xx/flashloader.h
+++ b/contrib/loaders/flash/cc26xx/flashloader.h
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#ifndef OPENOCD_LOADERS_FLASH_CC26XX_FLASHLOADER_H
diff --git a/contrib/loaders/flash/cc26xx/hw_regs.h b/contrib/loaders/flash/cc26xx/hw_regs.h
index 830d3af25..78c81be24 100644
--- a/contrib/loaders/flash/cc26xx/hw_regs.h
+++ b/contrib/loaders/flash/cc26xx/hw_regs.h
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H
diff --git a/contrib/loaders/flash/cc26xx/main.c b/contrib/loaders/flash/cc26xx/main.c
index 13204b458..91fc43ac1 100644
--- a/contrib/loaders/flash/cc26xx/main.c
+++ b/contrib/loaders/flash/cc26xx/main.c
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#include <stdint.h>
diff --git a/contrib/loaders/flash/cc26xx/startup.c b/contrib/loaders/flash/cc26xx/startup.c
index 53d8ea8c7..9eb0df8ef 100644
--- a/contrib/loaders/flash/cc26xx/startup.c
+++ b/contrib/loaders/flash/cc26xx/startup.c
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#include <stdint.h>
diff --git a/contrib/loaders/flash/msp432/MSP432E4_FlashLibIf.h b/contrib/loaders/flash/msp432/MSP432E4_FlashLibIf.h
index d406d6003..aad39896b 100644
--- a/contrib/loaders/flash/msp432/MSP432E4_FlashLibIf.h
+++ b/contrib/loaders/flash/msp432/MSP432E4_FlashLibIf.h
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2014-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432E4_FLASHLIBIF_H
diff --git a/contrib/loaders/flash/msp432/MSP432P4_FlashLibIf.h b/contrib/loaders/flash/msp432/MSP432P4_FlashLibIf.h
index c438097ef..b9334816d 100644
--- a/contrib/loaders/flash/msp432/MSP432P4_FlashLibIf.h
+++ b/contrib/loaders/flash/msp432/MSP432P4_FlashLibIf.h
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2014-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P4_FLASHLIBIF_H
diff --git a/contrib/loaders/flash/msp432/Makefile b/contrib/loaders/flash/msp432/Makefile
index 608333140..cb1092c66 100644
--- a/contrib/loaders/flash/msp432/Makefile
+++ b/contrib/loaders/flash/msp432/Makefile
@@ -1,3 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+
BIN2C = ../../../../src/helper/bin2char.sh
CROSS_COMPILE ?= arm-none-eabi-
diff --git a/contrib/loaders/flash/msp432/driverlib.c b/contrib/loaders/flash/msp432/driverlib.c
index ac6dfd454..e9058793c 100644
--- a/contrib/loaders/flash/msp432/driverlib.c
+++ b/contrib/loaders/flash/msp432/driverlib.c
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#include <stdint.h>
diff --git a/contrib/loaders/flash/msp432/driverlib.h b/contrib/loaders/flash/msp432/driverlib.h
index 23ba7b520..1a087373f 100644
--- a/contrib/loaders/flash/msp432/driverlib.h
+++ b/contrib/loaders/flash/msp432/driverlib.h
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#ifndef OPENOCD_LOADERS_FLASH_MSP432_DRIVERLIB_H
diff --git a/contrib/loaders/flash/msp432/main_msp432e4x.c b/contrib/loaders/flash/msp432/main_msp432e4x.c
index 23540ac60..db9514a9c 100644
--- a/contrib/loaders/flash/msp432/main_msp432e4x.c
+++ b/contrib/loaders/flash/msp432/main_msp432e4x.c
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#include <stdint.h>
diff --git a/contrib/loaders/flash/msp432/main_msp432p401x.c b/contrib/loaders/flash/msp432/main_msp432p401x.c
index 7992f1168..7d959a741 100644
--- a/contrib/loaders/flash/msp432/main_msp432p401x.c
+++ b/contrib/loaders/flash/msp432/main_msp432p401x.c
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#include <stdint.h>
diff --git a/contrib/loaders/flash/msp432/main_msp432p411x.c b/contrib/loaders/flash/msp432/main_msp432p411x.c
index be1f70976..d72efed68 100644
--- a/contrib/loaders/flash/msp432/main_msp432p411x.c
+++ b/contrib/loaders/flash/msp432/main_msp432p411x.c
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#include <stdint.h>
diff --git a/contrib/loaders/flash/msp432/msp432e4x.h b/contrib/loaders/flash/msp432/msp432e4x.h
index 2a9d15511..c0bc7b4fc 100644
--- a/contrib/loaders/flash/msp432/msp432e4x.h
+++ b/contrib/loaders/flash/msp432/msp432e4x.h
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H
diff --git a/contrib/loaders/flash/msp432/msp432e4x/msp432e4x.lds b/contrib/loaders/flash/msp432/msp432e4x/msp432e4x.lds
index af97458e6..278220970 100644
--- a/contrib/loaders/flash/msp432/msp432e4x/msp432e4x.lds
+++ b/contrib/loaders/flash/msp432/msp432e4x/msp432e4x.lds
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
MEMORY {
diff --git a/contrib/loaders/flash/msp432/msp432p401x.h b/contrib/loaders/flash/msp432/msp432p401x.h
index ca219fdd6..b8ccea8d9 100644
--- a/contrib/loaders/flash/msp432/msp432p401x.h
+++ b/contrib/loaders/flash/msp432/msp432p401x.h
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P401X_H
diff --git a/contrib/loaders/flash/msp432/msp432p401x/msp432p401x.lds b/contrib/loaders/flash/msp432/msp432p401x/msp432p401x.lds
index f9d04ed88..178eaf403 100644
--- a/contrib/loaders/flash/msp432/msp432p401x/msp432p401x.lds
+++ b/contrib/loaders/flash/msp432/msp432p401x/msp432p401x.lds
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
MEMORY {
diff --git a/contrib/loaders/flash/msp432/msp432p411x.h b/contrib/loaders/flash/msp432/msp432p411x.h
index 6482dd333..3225fa45f 100644
--- a/contrib/loaders/flash/msp432/msp432p411x.h
+++ b/contrib/loaders/flash/msp432/msp432p411x.h
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H
diff --git a/contrib/loaders/flash/msp432/msp432p411x/msp432p411x.lds b/contrib/loaders/flash/msp432/msp432p411x/msp432p411x.lds
index 0e7aa2dee..cec3c53f4 100644
--- a/contrib/loaders/flash/msp432/msp432p411x/msp432p411x.lds
+++ b/contrib/loaders/flash/msp432/msp432p411x/msp432p411x.lds
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
MEMORY {
diff --git a/contrib/loaders/flash/msp432/startup_msp432e4.c b/contrib/loaders/flash/msp432/startup_msp432e4.c
index 494da46e7..bd8fc2173 100644
--- a/contrib/loaders/flash/msp432/startup_msp432e4.c
+++ b/contrib/loaders/flash/msp432/startup_msp432e4.c
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#include <stdint.h>
diff --git a/contrib/loaders/flash/msp432/startup_msp432p4.c b/contrib/loaders/flash/msp432/startup_msp432p4.c
index 09103b0e4..f8ad811f2 100644
--- a/contrib/loaders/flash/msp432/startup_msp432p4.c
+++ b/contrib/loaders/flash/msp432/startup_msp432p4.c
@@ -1,35 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
/******************************************************************************
*
* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
******************************************************************************/
#include <stdint.h>
commit 2d48b8e012cf99f53cdd2a9130167c075717c7d7
Author: Antonio Borneo <bor...@gm...>
Date: Tue Aug 30 17:25:24 2022 +0200
contrib: replace the GPLv3-or-later license tag
These files are not built in OpenOCD and are not in conflict with
OpenOCD license.
Replace the GPL boilerplate with the SPDX tag.
Add the SPDX tag.
The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.
Change-Id: I934e4add24098f0e8574120b3bc32e9bcf166abd
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7157
Tested-by: jenkins
diff --git a/contrib/itmdump.c b/contrib/itmdump.c
index 88099040a..f31e1ff75 100644
--- a/contrib/itmdump.c
+++ b/contrib/itmdump.c
@@ -1,19 +1,6 @@
-/*
- * Copyright (C) 2010 by David Brownell
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
+/* SPDX-License-Identifier: GPL-3.0-or-later */
+
+/* Copyright (C) 2010 by David Brownell */
/*
* Simple utility to parse and dump ARM Cortex-M3 SWO trace output. Once the
diff --git a...
[truncated message content] |
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-09-13 22:05:38
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 25a374a187d760eddb87cbe639cb885b159b74b4 (commit)
via 0c6e0bb82bef9c93506e2f30fc20918691540e65 (commit)
from de5c32fe2399bc31f69429262e42555a2dbd9095 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 25a374a187d760eddb87cbe639cb885b159b74b4
Author: Antonio Borneo <bor...@gm...>
Date: Tue Aug 30 17:15:32 2022 +0200
openocd: fix syntax of SPDX tags
Put the SPDX tag alone in a comment in the first line of the file.
Replace the obsolete GPL-2.0+ tag
The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.
Change-Id: Ia91b0f7da42c439b6340bbe81983b86b68f6d65c
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7156
Tested-by: jenkins
diff --git a/.travis.yml b/.travis.yml
index da6b94c3f..28d5502c5 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0+
+# SPDX-License-Identifier: GPL-2.0-or-later
# Copyright Marek Vasut <ma...@de...>
# OpenOCD on Travis CI - https://travis-ci.org/
diff --git a/contrib/loaders/checksum/riscv_crc.c b/contrib/loaders/checksum/riscv_crc.c
index e437b6616..70476ad1f 100644
--- a/contrib/loaders/checksum/riscv_crc.c
+++ b/contrib/loaders/checksum/riscv_crc.c
@@ -1,7 +1,6 @@
-/*
- * SPDX-License-Identifier: GPL-2.0-or-later
- * Copyright (C) 2009-2021 Free Software Foundation, Inc.
- */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/* Copyright (C) 2009-2021 Free Software Foundation, Inc. */
/* Copied from https://github.com/gcc-mirror/gcc/blob/master/libiberty/crc32.c
* and then tweaked a little. */
diff --git a/contrib/loaders/flash/sh_qspi/sh_qspi.S b/contrib/loaders/flash/sh_qspi/sh_qspi.S
index 78eb1e818..b46514a48 100644
--- a/contrib/loaders/flash/sh_qspi/sh_qspi.S
+++ b/contrib/loaders/flash/sh_qspi/sh_qspi.S
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* SH QSPI (Quad SPI) driver
* Copyright (C) 2019 Marek Vasut <mar...@gm...>
diff --git a/contrib/loaders/flash/sh_qspi/sh_qspi.ld b/contrib/loaders/flash/sh_qspi/sh_qspi.ld
index 2683c520b..71cc3e380 100644
--- a/contrib/loaders/flash/sh_qspi/sh_qspi.ld
+++ b/contrib/loaders/flash/sh_qspi/sh_qspi.ld
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
diff --git a/contrib/loaders/flash/xmc1xxx/erase.S b/contrib/loaders/flash/xmc1xxx/erase.S
index e5a4808fc..9d3d9925c 100644
--- a/contrib/loaders/flash/xmc1xxx/erase.S
+++ b/contrib/loaders/flash/xmc1xxx/erase.S
@@ -1,11 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/*
* Infineon XMC1000 flash sectors erase
*
* Copyright (c) 2016 Andreas Färber
*
* Based on XMC1100 AA-Step Reference Manual
- *
- * License: GPL-2.0+
*/
#include "xmc1xxx.S"
diff --git a/contrib/loaders/flash/xmc1xxx/erase_check.S b/contrib/loaders/flash/xmc1xxx/erase_check.S
index 6c993443a..311c2044d 100644
--- a/contrib/loaders/flash/xmc1xxx/erase_check.S
+++ b/contrib/loaders/flash/xmc1xxx/erase_check.S
@@ -1,11 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/*
* Infineon XMC1000 flash sector erase check
*
* Copyright (c) 2016 Andreas Färber
*
* Based on XMC1100 AA-Step Reference Manual
- *
- * License: GPL-2.0+
*/
#include "xmc1xxx.S"
diff --git a/contrib/loaders/flash/xmc1xxx/write.S b/contrib/loaders/flash/xmc1xxx/write.S
index 640f6ca96..175425244 100644
--- a/contrib/loaders/flash/xmc1xxx/write.S
+++ b/contrib/loaders/flash/xmc1xxx/write.S
@@ -1,11 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/*
* Infineon XMC1000 flash write
*
* Copyright (c) 2016 Andreas Färber
*
* Based on XMC1100 AA-Step Reference Manual
- *
- * License: GPL-2.0+
*/
#include "xmc1xxx.S"
diff --git a/contrib/loaders/flash/xmc1xxx/xmc1xxx.S b/contrib/loaders/flash/xmc1xxx/xmc1xxx.S
index dfe7d3f41..5be141d6d 100644
--- a/contrib/loaders/flash/xmc1xxx/xmc1xxx.S
+++ b/contrib/loaders/flash/xmc1xxx/xmc1xxx.S
@@ -1,11 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/*
* Infineon XMC1000 flash
*
* Copyright (c) 2016 Andreas Färber
*
* Based on XMC1100 AA-Step Reference Manual
- *
- * License: GPL-2.0+
*/
.text
commit 0c6e0bb82bef9c93506e2f30fc20918691540e65
Author: Antonio Borneo <bor...@gm...>
Date: Tue Aug 30 16:10:19 2022 +0200
openocd: remove CamelCase symbols *xPSR*
We have left the camelcase symbols *xPSR* for some time, to avoid
any conflict with possibly pending patches in gerrit.
With the approaching v0.12.0-rc1, it's time to revisit it.
The patches in gerrit that conflict with this rename are all not
merge-able due to conflicts or due to negative review.
Drop these CamelCase symbols.
Change-Id: Ifbac4c1df9cc55994e024971a2aaebeed2ea4ed3
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7155
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/rtos/nuttx.c b/src/rtos/nuttx.c
index 3afad3d02..6b20ed322 100644
--- a/src/rtos/nuttx.c
+++ b/src/rtos/nuttx.c
@@ -103,7 +103,7 @@ static const struct stack_register_offset nuttx_stack_offsets_cortex_m[] = {
{ ARMV7M_R13, 0, 32 }, /* sp */
{ ARMV7M_R14, 0x3c, 32 }, /* lr */
{ ARMV7M_PC, 0x40, 32 }, /* pc */
- { ARMV7M_xPSR, 0x44, 32 }, /* xPSR */
+ { ARMV7M_XPSR, 0x44, 32 }, /* xPSR */
};
@@ -131,7 +131,7 @@ static const struct stack_register_offset nuttx_stack_offsets_cortex_m_fpu[] = {
{ ARMV7M_R13, 0, 32 }, /* sp */
{ ARMV7M_R14, 0x80, 32 }, /* lr */
{ ARMV7M_PC, 0x84, 32 }, /* pc */
- { ARMV7M_xPSR, 0x88, 32 }, /* xPSR */
+ { ARMV7M_XPSR, 0x88, 32 }, /* xPSR */
};
static const struct rtos_register_stacking nuttx_stacking_cortex_m_fpu = {
diff --git a/src/rtos/rtos_chibios_stackings.c b/src/rtos/rtos_chibios_stackings.c
index bd1717161..38a2889bd 100644
--- a/src/rtos/rtos_chibios_stackings.c
+++ b/src/rtos/rtos_chibios_stackings.c
@@ -32,7 +32,7 @@ static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets[ARM
{ ARMV7M_R13, -2, 32 }, /* sp */
{ ARMV7M_R14, -1, 32 }, /* lr */
{ ARMV7M_PC, 0x20, 32 }, /* pc */
- { ARMV7M_xPSR, -1, 32 }, /* xPSR */
+ { ARMV7M_XPSR, -1, 32 }, /* xPSR */
};
const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking = {
@@ -59,7 +59,7 @@ static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets_w_f
{ ARMV7M_R13, -2, 32 }, /* sp */
{ ARMV7M_R14, -1, 32 }, /* lr */
{ ARMV7M_PC, 0x60, 32 }, /* pc */
- { ARMV7M_xPSR, -1, 32 }, /* xPSR */
+ { ARMV7M_XPSR, -1, 32 }, /* xPSR */
};
const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking_w_fpu = {
diff --git a/src/rtos/rtos_ecos_stackings.c b/src/rtos/rtos_ecos_stackings.c
index f5c08fe73..b15915046 100644
--- a/src/rtos/rtos_ecos_stackings.c
+++ b/src/rtos/rtos_ecos_stackings.c
@@ -25,7 +25,7 @@ static const struct stack_register_offset rtos_ecos_cortex_m3_stack_offsets[ARMV
{ ARMV7M_R13, -2, 32 }, /* sp */
{ ARMV7M_R14, -1, 32 }, /* lr */
{ ARMV7M_PC, 0x40, 32 }, /* pc */
- { ARMV7M_xPSR, -1, 32 }, /* xPSR */
+ { ARMV7M_XPSR, -1, 32 }, /* xPSR */
};
const struct rtos_register_stacking rtos_ecos_cortex_m3_stacking = {
diff --git a/src/rtos/rtos_embkernel_stackings.c b/src/rtos/rtos_embkernel_stackings.c
index 46e13bc2f..bf02cb799 100644
--- a/src/rtos/rtos_embkernel_stackings.c
+++ b/src/rtos/rtos_embkernel_stackings.c
@@ -30,7 +30,7 @@ static const struct stack_register_offset rtos_embkernel_cortex_m_stack_offsets[
{ ARMV7M_R13, -2, 32 }, /* sp */
{ ARMV7M_R14, 0x38, 32 }, /* lr */
{ ARMV7M_PC, 0x3c, 32 }, /* pc */
- { ARMV7M_xPSR, 0x40, 32 }, /* xPSR */
+ { ARMV7M_XPSR, 0x40, 32 }, /* xPSR */
};
const struct rtos_register_stacking rtos_embkernel_cortex_m_stacking = {
diff --git a/src/rtos/rtos_mqx_stackings.c b/src/rtos/rtos_mqx_stackings.c
index 90a2e0161..087591baa 100644
--- a/src/rtos/rtos_mqx_stackings.c
+++ b/src/rtos/rtos_mqx_stackings.c
@@ -56,7 +56,7 @@ static const struct stack_register_offset rtos_mqx_arm_v7m_stack_offsets[ARMV7M_
{ ARMV7M_R13, -2, 32 }, /* sp */
{ ARMV7M_R14, 0x28, 32 }, /* lr */
{ ARMV7M_PC, 0x44, 32 }, /* pc */
- { ARMV7M_xPSR, 0x48, 32 }, /* xPSR */
+ { ARMV7M_XPSR, 0x48, 32 }, /* xPSR */
};
const struct rtos_register_stacking rtos_mqx_arm_v7m_stacking = {
diff --git a/src/rtos/rtos_riot_stackings.c b/src/rtos/rtos_riot_stackings.c
index 30eecd6b7..bcf14e54f 100644
--- a/src/rtos/rtos_riot_stackings.c
+++ b/src/rtos/rtos_riot_stackings.c
@@ -43,7 +43,7 @@ static const struct stack_register_offset rtos_riot_cortex_m0_stack_offsets[ARMV
{ ARMV7M_R13, -2, 32 }, /* sp */
{ ARMV7M_R14, 0x38, 32 }, /* lr */
{ ARMV7M_PC, 0x3c, 32 }, /* pc */
- { ARMV7M_xPSR, 0x40, 32 }, /* xPSR */
+ { ARMV7M_XPSR, 0x40, 32 }, /* xPSR */
};
const struct rtos_register_stacking rtos_riot_cortex_m0_stacking = {
@@ -72,7 +72,7 @@ static const struct stack_register_offset rtos_riot_cortex_m34_stack_offsets[ARM
{ ARMV7M_R13, -2, 32 }, /* sp */
{ ARMV7M_R14, 0x38, 32 }, /* lr */
{ ARMV7M_PC, 0x3c, 32 }, /* pc */
- { ARMV7M_xPSR, 0x40, 32 }, /* xPSR */
+ { ARMV7M_XPSR, 0x40, 32 }, /* xPSR */
};
const struct rtos_register_stacking rtos_riot_cortex_m34_stacking = {
diff --git a/src/rtos/rtos_standard_stackings.c b/src/rtos/rtos_standard_stackings.c
index ebdc64c2a..059bfc5b4 100644
--- a/src/rtos/rtos_standard_stackings.c
+++ b/src/rtos/rtos_standard_stackings.c
@@ -29,7 +29,7 @@ static const struct stack_register_offset rtos_standard_cortex_m3_stack_offsets[
{ ARMV7M_R13, -2, 32 }, /* sp */
{ ARMV7M_R14, 0x34, 32 }, /* lr */
{ ARMV7M_PC, 0x38, 32 }, /* pc */
- { ARMV7M_xPSR, 0x3c, 32 }, /* xPSR */
+ { ARMV7M_XPSR, 0x3c, 32 }, /* xPSR */
};
static const struct stack_register_offset rtos_standard_cortex_m4f_stack_offsets[] = {
@@ -49,7 +49,7 @@ static const struct stack_register_offset rtos_standard_cortex_m4f_stack_offsets
{ ARMV7M_R13, -2, 32 }, /* sp */
{ ARMV7M_R14, 0x38, 32 }, /* lr */
{ ARMV7M_PC, 0x3c, 32 }, /* pc */
- { ARMV7M_xPSR, 0x40, 32 }, /* xPSR */
+ { ARMV7M_XPSR, 0x40, 32 }, /* xPSR */
};
static const struct stack_register_offset rtos_standard_cortex_m4f_fpu_stack_offsets[] = {
@@ -69,7 +69,7 @@ static const struct stack_register_offset rtos_standard_cortex_m4f_fpu_stack_off
{ ARMV7M_R13, -2, 32 }, /* sp */
{ ARMV7M_R14, 0x78, 32 }, /* lr */
{ ARMV7M_PC, 0x7c, 32 }, /* pc */
- { ARMV7M_xPSR, 0x80, 32 }, /* xPSR */
+ { ARMV7M_XPSR, 0x80, 32 }, /* xPSR */
};
diff --git a/src/rtos/rtos_ucos_iii_stackings.c b/src/rtos/rtos_ucos_iii_stackings.c
index 866251820..aa98cc7a9 100644
--- a/src/rtos/rtos_ucos_iii_stackings.c
+++ b/src/rtos/rtos_ucos_iii_stackings.c
@@ -32,7 +32,7 @@ static const struct stack_register_offset rtos_ucos_iii_cortex_m_stack_offsets[]
{ ARMV7M_R13, -2, 32 }, /* sp */
{ ARMV7M_R14, 0x34, 32 }, /* lr */
{ ARMV7M_PC, 0x38, 32 }, /* pc */
- { ARMV7M_xPSR, 0x3c, 32 }, /* xPSR */
+ { ARMV7M_XPSR, 0x3c, 32 }, /* xPSR */
};
static const struct stack_register_offset rtos_ucos_iii_esi_risc_stack_offsets[] = {
diff --git a/src/rtos/zephyr.c b/src/rtos/zephyr.c
index 6276236e2..5f7795337 100644
--- a/src/rtos/zephyr.c
+++ b/src/rtos/zephyr.c
@@ -136,7 +136,7 @@ static const struct stack_register_offset arm_cpu_saved[] = {
{ ARMV7M_R13, -2, 32 },
{ ARMV7M_R14, 20, 32 },
{ ARMV7M_PC, 24, 32 },
- { ARMV7M_xPSR, 28, 32 },
+ { ARMV7M_XPSR, 28, 32 },
};
static struct stack_register_offset arc_cpu_saved[] = {
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index be0de509b..5d67d51f4 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -53,7 +53,7 @@ const int armv7m_psp_reg_map[ARMV7M_NUM_CORE_REGS] = {
ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
- ARMV7M_xPSR,
+ ARMV7M_XPSR,
};
/* MSP is used in handler and some thread modes */
@@ -62,7 +62,7 @@ const int armv7m_msp_reg_map[ARMV7M_NUM_CORE_REGS] = {
ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
- ARMV7M_xPSR,
+ ARMV7M_XPSR,
};
/*
@@ -97,7 +97,7 @@ static const struct {
{ ARMV7M_R13, "sp", 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_R14, "lr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_PC, "pc", 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.m-profile" },
- { ARMV7M_xPSR, "xPSR", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_XPSR, "xPSR", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
{ ARMV7M_MSP, "msp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
{ ARMV7M_PSP, "psp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
@@ -245,7 +245,7 @@ uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
switch (arm_reg_id) {
case ARMV7M_R0 ... ARMV7M_R14:
case ARMV7M_PC:
- case ARMV7M_xPSR:
+ case ARMV7M_XPSR:
case ARMV7M_MSP:
case ARMV7M_PSP:
/* NOTE: we "know" here that the register identifiers
@@ -579,7 +579,7 @@ int armv7m_start_algorithm(struct target *target,
* Because xPSR.T is populated on reset from the vector table,
* it might be 0 if the vector table has "bad" data in it.
*/
- struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR];
+ struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_XPSR];
buf_set_u32(reg->value, 0, 32, 0x01000000);
reg->valid = true;
reg->dirty = true;
@@ -803,7 +803,7 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
LOG_ERROR("unable to allocate reg type list");
}
- arm->cpsr = reg_list + ARMV7M_xPSR;
+ arm->cpsr = reg_list + ARMV7M_XPSR;
arm->pc = reg_list + ARMV7M_PC;
arm->core_cache = cache;
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 9ac6b9ec9..188bd5652 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -46,7 +46,7 @@ enum {
ARMV7M_REGSEL_R14,
ARMV7M_REGSEL_PC = 15,
- ARMV7M_REGSEL_xPSR = 16,
+ ARMV7M_REGSEL_XPSR = 16,
ARMV7M_REGSEL_MSP,
ARMV7M_REGSEL_PSP,
@@ -124,7 +124,7 @@ enum {
ARMV7M_R14 = ARMV7M_REGSEL_R14,
ARMV7M_PC = ARMV7M_REGSEL_PC,
- ARMV7M_xPSR = ARMV7M_REGSEL_xPSR,
+ ARMV7M_XPSR = ARMV7M_REGSEL_XPSR,
ARMV7M_MSP = ARMV7M_REGSEL_MSP,
ARMV7M_PSP = ARMV7M_REGSEL_PSP,
@@ -199,7 +199,7 @@ enum {
/* for convenience add registers' block delimiters */
ARMV7M_LAST_REG,
ARMV7M_CORE_FIRST_REG = ARMV7M_R0,
- ARMV7M_CORE_LAST_REG = ARMV7M_xPSR,
+ ARMV7M_CORE_LAST_REG = ARMV7M_XPSR,
ARMV7M_FPU_FIRST_REG = ARMV7M_D0,
ARMV7M_FPU_LAST_REG = ARMV7M_FPSCR,
ARMV8M_FIRST_REG = ARMV8M_MSP_NS,
diff --git a/src/target/armv8.c b/src/target/armv8.c
index f4ae1f55c..0da6c05a5 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -134,7 +134,7 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
retval = dpm->instr_read_data_r0_64(dpm,
ARMV8_MRS_DLR(0), &value_64);
break;
- case ARMV8_xPSR:
+ case ARMV8_XPSR:
retval = dpm->instr_read_data_r0(dpm,
ARMV8_MRS_DSPSR(0), &value);
value_64 = value;
@@ -249,7 +249,7 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu
ARMV8_MSR_DLR(0),
value_64);
break;
- case ARMV8_xPSR:
+ case ARMV8_XPSR:
value = value_64;
retval = dpm->instr_write_data_r0(dpm,
ARMV8_MSR_DSPSR(0),
@@ -364,7 +364,7 @@ static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *re
ARMV8_MRC_DLR(0),
&value);
break;
- case ARMV8_xPSR:
+ case ARMV8_XPSR:
retval = dpm->instr_read_data_r0(dpm,
ARMV8_MRC_DSPSR(0),
&value);
@@ -399,17 +399,17 @@ static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *re
break;
case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS_xPSR_T1(1, 0),
+ ARMV8_MRS_XPSR_T1(1, 0),
&value);
break;
case ARMV8_SPSR_EL2: /* mapped to SPSR_hyp */
retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS_xPSR_T1(1, 0),
+ ARMV8_MRS_XPSR_T1(1, 0),
&value);
break;
case ARMV8_SPSR_EL3: /* mapped to SPSR_mon */
retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS_xPSR_T1(1, 0),
+ ARMV8_MRS_XPSR_T1(1, 0),
&value);
break;
case ARMV8_FPSR:
@@ -500,7 +500,7 @@ static int armv8_write_reg32(struct armv8_common *armv8, int regnum, uint64_t va
retval = dpm->instr_write_data_r0(dpm,
ARMV8_MCR_DLR(0), value);
break;
- case ARMV8_xPSR: /* CPSR */
+ case ARMV8_XPSR: /* CPSR */
/* read r0 from DCC, then "MCR r0, DSPSR" */
retval = dpm->instr_write_data_r0(dpm,
ARMV8_MCR_DSPSR(0), value);
@@ -535,17 +535,17 @@ static int armv8_write_reg32(struct armv8_common *armv8, int regnum, uint64_t va
break;
case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
+ ARMV8_MSR_GP_XPSR_T1(1, 0, 15),
value);
break;
case ARMV8_SPSR_EL2: /* mapped to SPSR_hyp */
retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
+ ARMV8_MSR_GP_XPSR_T1(1, 0, 15),
value);
break;
case ARMV8_SPSR_EL3: /* mapped to SPSR_mon */
retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
+ ARMV8_MSR_GP_XPSR_T1(1, 0, 15),
value);
break;
case ARMV8_FPSR:
@@ -1364,7 +1364,7 @@ static const struct {
{ ARMV8_SP, "sp", 64, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.aarch64.core", NULL},
{ ARMV8_PC, "pc", 64, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.aarch64.core", NULL},
- { ARMV8_xPSR, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED,
+ { ARMV8_XPSR, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED,
"general", "org.gnu.gdb.aarch64.core", aarch64_flags_cpsr},
{ ARMV8_V0, "v0", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
{ ARMV8_V1, "v1", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
@@ -1449,7 +1449,7 @@ static const struct {
{ ARMV8_R13, 0, "sp", 32, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.core" },
{ ARMV8_R14, 0, "lr", 32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" },
{ ARMV8_PC, 0, "pc", 32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" },
- { ARMV8_xPSR, 0, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_XPSR, 0, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
{ ARMV8_V0, 0, "d0", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARMV8_V0, 8, "d1", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARMV8_V1, 0, "d2", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
@@ -1652,7 +1652,7 @@ struct reg_cache *armv8_build_reg_cache(struct target *target)
LOG_ERROR("unable to allocate reg type list");
}
- arm->cpsr = reg_list + ARMV8_xPSR;
+ arm->cpsr = reg_list + ARMV8_XPSR;
arm->pc = reg_list + ARMV8_PC;
arm->core_cache = cache;
diff --git a/src/target/armv8.h b/src/target/armv8.h
index e06067175..2ed3a65ac 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -49,7 +49,7 @@ enum {
ARMV8_SP = 31,
ARMV8_PC = 32,
- ARMV8_xPSR = 33,
+ ARMV8_XPSR = 33,
ARMV8_V0 = 34,
ARMV8_V1,
diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index 017c175fc..3ea8fa964 100644
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -601,7 +601,7 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
/* load SPSR with the desired mode and execute DRPS */
LOG_DEBUG("SPSR = 0x%08"PRIx32, cpsr);
retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP_xPSR_T1(1, 0, 15), cpsr);
+ ARMV8_MSR_GP_XPSR_T1(1, 0, 15), cpsr);
if (retval == ERROR_OK)
retval = dpm->instr_execute(dpm, armv8_opcode(armv8, ARMV8_OPC_DRPS));
}
@@ -917,7 +917,7 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
if (!cache->reg_list[i].exist)
continue;
/* skip PC and CPSR */
- if (i == ARMV8_PC || i == ARMV8_xPSR)
+ if (i == ARMV8_PC || i == ARMV8_XPSR)
continue;
/* skip invalid */
if (!cache->reg_list[i].valid)
@@ -939,7 +939,7 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
/* flush CPSR and PC */
if (retval == ERROR_OK)
- retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_xPSR], ARMV8_xPSR);
+ retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_XPSR], ARMV8_XPSR);
if (retval == ERROR_OK)
retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_PC], ARMV8_PC);
/* flush R0 -- it's *very* dirty by now */
@@ -1293,9 +1293,9 @@ void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore)
unsigned int el;
static const int clobbered_regs_by_el[3][5] = {
- { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL1, ARMV8_ESR_EL1, ARMV8_SPSR_EL1 },
- { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL2, ARMV8_ESR_EL2, ARMV8_SPSR_EL2 },
- { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL3, ARMV8_ESR_EL3, ARMV8_SPSR_EL3 },
+ { ARMV8_PC, ARMV8_XPSR, ARMV8_ELR_EL1, ARMV8_ESR_EL1, ARMV8_SPSR_EL1 },
+ { ARMV8_PC, ARMV8_XPSR, ARMV8_ELR_EL2, ARMV8_ESR_EL2, ARMV8_SPSR_EL2 },
+ { ARMV8_PC, ARMV8_XPSR, ARMV8_ELR_EL3, ARMV8_ESR_EL3, ARMV8_SPSR_EL3 },
};
el = (dpm->dscr >> 8) & 3;
@@ -1310,7 +1310,7 @@ void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore)
mem_ap_write_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
- armv8->read_reg_u64(armv8, ARMV8_xPSR, &dlr);
+ armv8->read_reg_u64(armv8, ARMV8_XPSR, &dlr);
dspsr = dlr;
armv8->read_reg_u64(armv8, ARMV8_PC, &dlr);
diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h
index c4ecd667c..8c9652bfe 100644
--- a/src/target/armv8_opcodes.h
+++ b/src/target/armv8_opcodes.h
@@ -138,9 +138,9 @@
(0xd500401f | ((op1) << 16) | ((crm) << 8) | ((op2) << 5))
#define ARMV8_MRS_T1(r, m1, rd, m) (0xF3E08020 | (r << 20) | (m1 << 16) | (rd << 8) | (m << 4))
-#define ARMV8_MRS_xPSR_T1(r, rd) (0xF3EF8000 | (r << 20) | (rd << 8))
+#define ARMV8_MRS_XPSR_T1(r, rd) (0xF3EF8000 | (r << 20) | (rd << 8))
#define ARMV8_MSR_GP_T1(r, m1, rd, m) (0xF3808020 | (r << 20) | (m1 << 8) | (rd << 16) | (m << 4))
-#define ARMV8_MSR_GP_xPSR_T1(r, rn, mask) (0xF3808000 | (r << 20) | (rn << 16) | (mask << 8))
+#define ARMV8_MSR_GP_XPSR_T1(r, rn, mask) (0xF3808000 | (r << 20) | (rn << 16) | (mask << 8))
#define ARMV8_BKPT(im) (0xD4200000 | ((im & 0xffff) << 5))
#define ARMV8_HLT(im) (0x0D4400000 | ((im & 0xffff) << 5))
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index c5cb8d47a..2e81d140c 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -807,11 +807,11 @@ static int cortex_a_internal_restore(struct target *target, int current,
armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = true;
/* Make sure we are in Thumb mode */
- buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
- buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0,
+ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_XPSR].value, 0, 32,
+ buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_XPSR].value, 0,
32) | (1 << 24));
- armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = true;
- armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = true;
+ armv7m->core_cache->reg_list[ARMV7M_XPSR].dirty = true;
+ armv7m->core_cache->reg_list[ARMV7M_XPSR].valid = true;
}
#endif
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 727d9ca07..8e9264b79 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -775,7 +775,7 @@ static int cortex_m_examine_exception_reason(struct target *target)
static int cortex_m_debug_entry(struct target *target)
{
- uint32_t xPSR;
+ uint32_t xpsr;
int retval;
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
@@ -826,11 +826,11 @@ static int cortex_m_debug_entry(struct target *target)
return retval;
r = arm->cpsr;
- xPSR = buf_get_u32(r->value, 0, 32);
+ xpsr = buf_get_u32(r->value, 0, 32);
/* Are we in an exception handler */
- if (xPSR & 0x1FF) {
- armv7m->exception_number = (xPSR & 0x1FF);
+ if (xpsr & 0x1FF) {
+ armv7m->exception_number = (xpsr & 0x1FF);
arm->core_mode = ARM_MODE_HANDLER;
arm->map = armv7m_msp_reg_map;
diff --git a/src/target/hla_target.c b/src/target/hla_target.c
index 748905691..d3a16cd9b 100644
--- a/src/target/hla_target.c
+++ b/src/target/hla_target.c
@@ -231,7 +231,7 @@ static int adapter_debug_entry(struct target *target)
struct armv7m_common *armv7m = target_to_armv7m(target);
struct arm *arm = &armv7m->arm;
struct reg *r;
- uint32_t xPSR;
+ uint32_t xpsr;
int retval;
/* preserve the DCRDR across halts */
@@ -249,11 +249,11 @@ static int adapter_debug_entry(struct target *target)
adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA);
r = arm->cpsr;
- xPSR = buf_get_u32(r->value, 0, 32);
+ xpsr = buf_get_u32(r->value, 0, 32);
/* Are we in an exception handler */
- if (xPSR & 0x1FF) {
- armv7m->exception_number = (xPSR & 0x1FF);
+ if (xpsr & 0x1FF) {
+ armv7m->exception_number = (xpsr & 0x1FF);
arm->core_mode = ARM_MODE_HANDLER;
arm->map = armv7m_msp_reg_map;
-----------------------------------------------------------------------
Summary of changes:
.travis.yml | 2 +-
contrib/loaders/checksum/riscv_crc.c | 7 +++----
contrib/loaders/flash/sh_qspi/sh_qspi.S | 2 +-
contrib/loaders/flash/sh_qspi/sh_qspi.ld | 2 +-
contrib/loaders/flash/xmc1xxx/erase.S | 4 ++--
contrib/loaders/flash/xmc1xxx/erase_check.S | 4 ++--
contrib/loaders/flash/xmc1xxx/write.S | 4 ++--
contrib/loaders/flash/xmc1xxx/xmc1xxx.S | 4 ++--
src/rtos/nuttx.c | 4 ++--
src/rtos/rtos_chibios_stackings.c | 4 ++--
src/rtos/rtos_ecos_stackings.c | 2 +-
src/rtos/rtos_embkernel_stackings.c | 2 +-
src/rtos/rtos_mqx_stackings.c | 2 +-
src/rtos/rtos_riot_stackings.c | 4 ++--
src/rtos/rtos_standard_stackings.c | 6 +++---
src/rtos/rtos_ucos_iii_stackings.c | 2 +-
src/rtos/zephyr.c | 2 +-
src/target/armv7m.c | 12 ++++++------
src/target/armv7m.h | 6 +++---
src/target/armv8.c | 26 +++++++++++++-------------
src/target/armv8.h | 2 +-
src/target/armv8_dpm.c | 14 +++++++-------
src/target/armv8_opcodes.h | 4 ++--
src/target/cortex_a.c | 8 ++++----
src/target/cortex_m.c | 8 ++++----
src/target/hla_target.c | 8 ++++----
26 files changed, 72 insertions(+), 73 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-09-13 22:05:11
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via de5c32fe2399bc31f69429262e42555a2dbd9095 (commit)
from de99836cf639b63dc357a34c13825669af841f17 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit de5c32fe2399bc31f69429262e42555a2dbd9095
Author: Antonio Borneo <bor...@gm...>
Date: Tue Aug 30 16:36:07 2022 +0200
openocd: remove recently added CamelCase symbols
Without the help of checkpatch, some CamelCase symbol passed
through the filter of maintainer's review.
Drop them.
Change-Id: If5fb07b2ffb89e853dd2a61f20d4134aa6e20d24
Signed-off-by: Antonio Borneo <bor...@gm...>
Fixes: 48f267d4adea ("flash/stm32l4x: avoid using magic numbers for device ids")
Fixes: 5ab74bde0654 ("semihosting: User defined operation, Tcl command exec on host")
Reviewed-on: https://review.openocd.org/c/openocd/+/7154
Tested-by: jenkins
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index 6cb75884e..a1108b5fd 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -289,7 +289,7 @@ static const struct stm32l4_rev stm32l45_l46xx_revs[] = {
{ 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
};
-static const struct stm32l4_rev stm32l41_L42xx_revs[] = {
+static const struct stm32l4_rev stm32l41_l42xx_revs[] = {
{ 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
};
@@ -420,8 +420,8 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
},
{
.id = DEVID_STM32L41_L42XX,
- .revs = stm32l41_L42xx_revs,
- .num_revs = ARRAY_SIZE(stm32l41_L42xx_revs),
+ .revs = stm32l41_l42xx_revs,
+ .num_revs = ARRAY_SIZE(stm32l41_l42xx_revs),
.device_str = "STM32L41/L42xx",
.max_flash_size_kb = 128,
.flags = F_NONE,
diff --git a/src/target/semihosting_common.c b/src/target/semihosting_common.c
index c449b0539..bdf29a424 100644
--- a/src/target/semihosting_common.c
+++ b/src/target/semihosting_common.c
@@ -1417,7 +1417,7 @@ int semihosting_common(struct target *target)
}
break;
- case SEMIHOSTING_USER_CMD_0x100 ... SEMIHOSTING_USER_CMD_0x107:
+ case SEMIHOSTING_USER_CMD_0X100 ... SEMIHOSTING_USER_CMD_0X107:
/**
* This is a user defined operation (while user cmds 0x100-0x1ff
* are possible, only 0x100-0x107 are currently implemented).
diff --git a/src/target/semihosting_common.h b/src/target/semihosting_common.h
index 8ecf2e526..7c5f748f4 100644
--- a/src/target/semihosting_common.h
+++ b/src/target/semihosting_common.h
@@ -65,9 +65,9 @@ enum semihosting_operation_numbers {
SEMIHOSTING_SYS_WRITE = 0x05,
SEMIHOSTING_SYS_WRITEC = 0x03,
SEMIHOSTING_SYS_WRITE0 = 0x04,
- SEMIHOSTING_USER_CMD_0x100 = 0x100, /* First user cmd op code */
- SEMIHOSTING_USER_CMD_0x107 = 0x107, /* Last supported user cmd op code */
- SEMIHOSTING_USER_CMD_0x1FF = 0x1FF, /* Last user cmd op code */
+ SEMIHOSTING_USER_CMD_0X100 = 0x100, /* First user cmd op code */
+ SEMIHOSTING_USER_CMD_0X107 = 0x107, /* Last supported user cmd op code */
+ SEMIHOSTING_USER_CMD_0X1FF = 0x1FF, /* Last user cmd op code */
};
/** Maximum allowed Tcl command segment length in bytes*/
diff --git a/src/target/target.c b/src/target/target.c
index 9b07dbf61..97ea13dc2 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -236,14 +236,14 @@ static const struct jim_nvp nvp_target_event[] = {
{ .value = TARGET_EVENT_TRACE_CONFIG, .name = "trace-config" },
- { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0x100, .name = "semihosting-user-cmd-0x100" },
- { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0x101, .name = "semihosting-user-cmd-0x101" },
- { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0x102, .name = "semihosting-user-cmd-0x102" },
- { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0x103, .name = "semihosting-user-cmd-0x103" },
- { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0x104, .name = "semihosting-user-cmd-0x104" },
- { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0x105, .name = "semihosting-user-cmd-0x105" },
- { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0x106, .name = "semihosting-user-cmd-0x106" },
- { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0x107, .name = "semihosting-user-cmd-0x107" },
+ { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0X100, .name = "semihosting-user-cmd-0x100" },
+ { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0X101, .name = "semihosting-user-cmd-0x101" },
+ { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0X102, .name = "semihosting-user-cmd-0x102" },
+ { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0X103, .name = "semihosting-user-cmd-0x103" },
+ { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0X104, .name = "semihosting-user-cmd-0x104" },
+ { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0X105, .name = "semihosting-user-cmd-0x105" },
+ { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0X106, .name = "semihosting-user-cmd-0x106" },
+ { .value = TARGET_EVENT_SEMIHOSTING_USER_CMD_0X107, .name = "semihosting-user-cmd-0x107" },
{ .name = NULL, .value = -1 }
};
diff --git a/src/target/target.h b/src/target/target.h
index e221351a8..d445c2975 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -286,14 +286,14 @@ enum target_event {
TARGET_EVENT_TRACE_CONFIG,
- TARGET_EVENT_SEMIHOSTING_USER_CMD_0x100 = 0x100, /* semihosting allows user cmds from 0x100 to 0x1ff */
- TARGET_EVENT_SEMIHOSTING_USER_CMD_0x101 = 0x101,
- TARGET_EVENT_SEMIHOSTING_USER_CMD_0x102 = 0x102,
- TARGET_EVENT_SEMIHOSTING_USER_CMD_0x103 = 0x103,
- TARGET_EVENT_SEMIHOSTING_USER_CMD_0x104 = 0x104,
- TARGET_EVENT_SEMIHOSTING_USER_CMD_0x105 = 0x105,
- TARGET_EVENT_SEMIHOSTING_USER_CMD_0x106 = 0x106,
- TARGET_EVENT_SEMIHOSTING_USER_CMD_0x107 = 0x107,
+ TARGET_EVENT_SEMIHOSTING_USER_CMD_0X100 = 0x100, /* semihosting allows user cmds from 0x100 to 0x1ff */
+ TARGET_EVENT_SEMIHOSTING_USER_CMD_0X101 = 0x101,
+ TARGET_EVENT_SEMIHOSTING_USER_CMD_0X102 = 0x102,
+ TARGET_EVENT_SEMIHOSTING_USER_CMD_0X103 = 0x103,
+ TARGET_EVENT_SEMIHOSTING_USER_CMD_0X104 = 0x104,
+ TARGET_EVENT_SEMIHOSTING_USER_CMD_0X105 = 0x105,
+ TARGET_EVENT_SEMIHOSTING_USER_CMD_0X106 = 0x106,
+ TARGET_EVENT_SEMIHOSTING_USER_CMD_0X107 = 0x107,
};
struct target_event_action {
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32l4x.c | 6 +++---
src/target/semihosting_common.c | 2 +-
src/target/semihosting_common.h | 6 +++---
src/target/target.c | 16 ++++++++--------
src/target/target.h | 16 ++++++++--------
5 files changed, 23 insertions(+), 23 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2022-09-08 09:32:48
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via de99836cf639b63dc357a34c13825669af841f17 (commit)
from ea165d8e897cb5946942f40589efec4f1b5e7c2c (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit de99836cf639b63dc357a34c13825669af841f17
Author: Ian Thompson <ia...@ca...>
Date: Wed Aug 24 06:51:51 2022 -0700
target/xtensa: virtualize XDM registers
Use indirect enum IDs to access XDM registers in preparation for supporting both NAR (JTAG) and APB (DAP). No new clang static analysis warnings.
Signed-off-by: Ian Thompson <ia...@ca...>
Change-Id: I0b742fe4661ff3cf609454b8650493d141a1e1ff
Reviewed-on: https://review.openocd.org/c/openocd/+/7143
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index 2fd2c7ca5..a90cd1468 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -493,7 +493,7 @@ static void xtensa_mark_register_dirty(struct xtensa *xtensa, enum xtensa_reg_id
static void xtensa_queue_exec_ins(struct xtensa *xtensa, uint32_t ins)
{
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DIR0EXEC, ins);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DIR0EXEC, ins);
}
static void xtensa_queue_exec_ins_wide(struct xtensa *xtensa, uint8_t *ops, uint8_t oplen)
@@ -506,9 +506,9 @@ static void xtensa_queue_exec_ins_wide(struct xtensa *xtensa, uint8_t *ops, uint
else
memcpy(opsw, ops, oplen);
for (int32_t i = oplenw - 1; i > 0; i--)
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DIR0 + i, opsw[i]);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DIR0 + i, opsw[i]);
/* Write DIR0EXEC last */
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DIR0EXEC, opsw[0]);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DIR0EXEC, opsw[0]);
}
}
@@ -529,8 +529,8 @@ int xtensa_window_state_save(struct target *target, uint32_t *woe)
/* Save PS (LX) and disable window overflow exceptions prior to AR save */
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_PS, XT_REG_A3));
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3));
- xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR, woe_buf);
- int res = jtag_execute_queue();
+ xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, woe_buf);
+ int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK) {
LOG_ERROR("Failed to read PS (%d)!", res);
return res;
@@ -539,7 +539,7 @@ int xtensa_window_state_save(struct target *target, uint32_t *woe)
*woe = buf_get_u32(woe_buf, 0, 32);
woe_dis = *woe & ~XT_PS_WOE_MSK;
LOG_DEBUG("Clearing PS.WOE (0x%08" PRIx32 " -> 0x%08" PRIx32 ")", *woe, woe_dis);
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, woe_dis);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, woe_dis);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_PS, XT_REG_A3));
}
@@ -552,7 +552,7 @@ void xtensa_window_state_restore(struct target *target, uint32_t woe)
struct xtensa *xtensa = target_to_xtensa(target);
if (xtensa->core_config->windowed) {
/* Restore window overflow exception state */
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, woe);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, woe);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_PS, XT_REG_A3));
LOG_DEBUG("Restored PS.WOE (0x%08" PRIx32 ")", woe);
@@ -614,7 +614,7 @@ static int xtensa_write_dirty_registers(struct target *target)
reg_list[i].name,
rlist[ridx].reg_num,
regval);
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, regval);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, regval);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
if (reg_list[i].exist) {
unsigned int reg_num = rlist[ridx].reg_num;
@@ -641,7 +641,7 @@ static int xtensa_write_dirty_registers(struct target *target)
if (delay_cpenable) {
regval = xtensa_reg_get(target, XT_REG_IDX_CPENABLE);
LOG_TARGET_DEBUG(target, "Writing back reg cpenable (224) val %08" PRIX32, regval);
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, regval);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, regval);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa,
xtensa_regs[XT_REG_IDX_CPENABLE].reg_num,
@@ -653,8 +653,8 @@ static int xtensa_write_dirty_registers(struct target *target)
if (preserve_a3) {
/* Save (windowed) A3 for scratch use */
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3));
- xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR, a3_buf);
- res = jtag_execute_queue();
+ xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, a3_buf);
+ res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK)
return res;
xtensa_core_status_check(target);
@@ -705,7 +705,7 @@ static int xtensa_write_dirty_registers(struct target *target)
xtensa_regs[XT_REG_IDX_A0 + i].name,
regval,
xtensa_regs[XT_REG_IDX_A0 + i].reg_num);
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, regval);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, regval);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, i));
reg_list[XT_REG_IDX_A0 + i].dirty = false;
if (i == 3) {
@@ -733,7 +733,7 @@ static int xtensa_write_dirty_registers(struct target *target)
xtensa_regs[realadr].name,
regval,
xtensa_regs[realadr].reg_num);
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, regval);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, regval);
xtensa_queue_exec_ins(xtensa,
XT_INS_RSR(xtensa, XT_SR_DDR,
xtensa_regs[XT_REG_IDX_AR0 + i].reg_num));
@@ -757,11 +757,11 @@ static int xtensa_write_dirty_registers(struct target *target)
}
if (preserve_a3) {
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, a3);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, a3);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
}
- res = jtag_execute_queue();
+ res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
xtensa_core_status_check(target);
return res;
@@ -785,11 +785,11 @@ int xtensa_examine(struct target *target)
return ERROR_FAIL;
}
- xtensa_queue_pwr_reg_write(xtensa, DMREG_PWRCTL, cmd);
- xtensa_queue_pwr_reg_write(xtensa, DMREG_PWRCTL, cmd | PWRCTL_JTAGDEBUGUSE);
+ xtensa_queue_pwr_reg_write(xtensa, XDMREG_PWRCTL, cmd);
+ xtensa_queue_pwr_reg_write(xtensa, XDMREG_PWRCTL, cmd | PWRCTL_JTAGDEBUGUSE);
xtensa_dm_queue_enable(&xtensa->dbg_mod);
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
- int res = jtag_execute_queue();
+ int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK)
return res;
if (!xtensa_dm_is_online(&xtensa->dbg_mod)) {
@@ -810,11 +810,11 @@ int xtensa_wakeup(struct target *target)
if (xtensa->reset_asserted)
cmd |= PWRCTL_CORERESET;
- xtensa_queue_pwr_reg_write(xtensa, DMREG_PWRCTL, cmd);
+ xtensa_queue_pwr_reg_write(xtensa, XDMREG_PWRCTL, cmd);
/* TODO: can we join this with the write above? */
- xtensa_queue_pwr_reg_write(xtensa, DMREG_PWRCTL, cmd | PWRCTL_JTAGDEBUGUSE);
+ xtensa_queue_pwr_reg_write(xtensa, XDMREG_PWRCTL, cmd | PWRCTL_JTAGDEBUGUSE);
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
- return jtag_execute_queue();
+ return xtensa_dm_queue_execute(&xtensa->dbg_mod);
}
int xtensa_smpbreak_write(struct xtensa *xtensa, uint32_t set)
@@ -825,11 +825,11 @@ int xtensa_smpbreak_write(struct xtensa *xtensa, uint32_t set)
OCDDCR_DEBUGMODEOUTEN | OCDDCR_ENABLEOCD);
LOG_TARGET_DEBUG(xtensa->target, "write smpbreak set=0x%" PRIx32 " clear=0x%" PRIx32, set, clear);
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DCRSET, set | OCDDCR_ENABLEOCD);
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DCRCLR, clear);
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DSR, dsr_data);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DCRSET, set | OCDDCR_ENABLEOCD);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DCRCLR, clear);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DSR, dsr_data);
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
- return jtag_execute_queue();
+ return xtensa_dm_queue_execute(&xtensa->dbg_mod);
}
int xtensa_smpbreak_set(struct target *target, uint32_t set)
@@ -848,9 +848,9 @@ int xtensa_smpbreak_read(struct xtensa *xtensa, uint32_t *val)
{
uint8_t dcr_buf[sizeof(uint32_t)];
- xtensa_queue_dbg_reg_read(xtensa, NARADR_DCRSET, dcr_buf);
+ xtensa_queue_dbg_reg_read(xtensa, XDMREG_DCRSET, dcr_buf);
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
- int res = jtag_execute_queue();
+ int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
*val = buf_get_u32(dcr_buf, 0, 32);
return res;
@@ -958,11 +958,11 @@ int xtensa_assert_reset(struct target *target)
LOG_TARGET_DEBUG(target, "target_number=%i, begin", target->target_number);
target->state = TARGET_RESET;
xtensa_queue_pwr_reg_write(xtensa,
- DMREG_PWRCTL,
- PWRCTL_JTAGDEBUGUSE | PWRCTL_DEBUGWAKEUP | PWRCTL_MEMWAKEUP | PWRCTL_COREWAKEUP |
- PWRCTL_CORERESET);
+ XDMREG_PWRCTL,
+ PWRCTL_JTAGDEBUGUSE | PWRCTL_DEBUGWAKEUP | PWRCTL_MEMWAKEUP |
+ PWRCTL_COREWAKEUP | PWRCTL_CORERESET);
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
- int res = jtag_execute_queue();
+ int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK)
return res;
xtensa->reset_asserted = true;
@@ -976,13 +976,14 @@ int xtensa_deassert_reset(struct target *target)
LOG_TARGET_DEBUG(target, "halt=%d", target->reset_halt);
if (target->reset_halt)
xtensa_queue_dbg_reg_write(xtensa,
- NARADR_DCRSET,
+ XDMREG_DCRSET,
OCDDCR_ENABLEOCD | OCDDCR_DEBUGINTERRUPT);
xtensa_queue_pwr_reg_write(xtensa,
- DMREG_PWRCTL,
- PWRCTL_JTAGDEBUGUSE | PWRCTL_DEBUGWAKEUP | PWRCTL_MEMWAKEUP | PWRCTL_COREWAKEUP);
+ XDMREG_PWRCTL,
+ PWRCTL_JTAGDEBUGUSE | PWRCTL_DEBUGWAKEUP | PWRCTL_MEMWAKEUP |
+ PWRCTL_COREWAKEUP);
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
- int res = jtag_execute_queue();
+ int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK)
return res;
target->state = TARGET_RUNNING;
@@ -1022,7 +1023,7 @@ int xtensa_fetch_all_regs(struct target *target)
/* Save (windowed) A3 so cache matches physical AR3; A3 usable as scratch */
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3));
- xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR, a3_buf);
+ xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, a3_buf);
int res = xtensa_window_state_save(target, &woe);
if (res != ERROR_OK)
goto xtensa_fetch_all_regs_done;
@@ -1038,10 +1039,10 @@ int xtensa_fetch_all_regs(struct target *target)
if (i + j < xtensa->core_config->aregs_num) {
xtensa_queue_exec_ins(xtensa,
XT_INS_WSR(xtensa, XT_SR_DDR, xtensa_regs[XT_REG_IDX_AR0 + i].reg_num));
- xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR,
+ xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR,
regvals[XT_REG_IDX_AR0 + i + j].buf);
if (debug_dsrs)
- xtensa_queue_dbg_reg_read(xtensa, NARADR_DSR,
+ xtensa_queue_dbg_reg_read(xtensa, XDMREG_DSR,
dsrs[XT_REG_IDX_AR0 + i + j].buf);
}
}
@@ -1057,9 +1058,9 @@ int xtensa_fetch_all_regs(struct target *target)
/* As the very first thing after AREGS, go grab CPENABLE */
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, xtensa_regs[XT_REG_IDX_CPENABLE].reg_num, XT_REG_A3));
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3));
- xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR, regvals[XT_REG_IDX_CPENABLE].buf);
+ xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, regvals[XT_REG_IDX_CPENABLE].buf);
}
- res = jtag_execute_queue();
+ res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK) {
LOG_ERROR("Failed to read ARs (%d)!", res);
goto xtensa_fetch_all_regs_done;
@@ -1072,7 +1073,7 @@ int xtensa_fetch_all_regs(struct target *target)
cpenable = buf_get_u32(regvals[XT_REG_IDX_CPENABLE].buf, 0, 32);
/* Enable all coprocessors (by setting all bits in CPENABLE) so we can read FP and user registers. */
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, 0xffffffff);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, 0xffffffff);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, xtensa_regs[XT_REG_IDX_CPENABLE].reg_num, XT_REG_A3));
@@ -1111,14 +1112,14 @@ int xtensa_fetch_all_regs(struct target *target)
}
if (reg_fetched) {
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3));
- xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR, regvals[i].buf);
+ xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, regvals[i].buf);
if (debug_dsrs)
- xtensa_queue_dbg_reg_read(xtensa, NARADR_DSR, dsrs[i].buf);
+ xtensa_queue_dbg_reg_read(xtensa, XDMREG_DSR, dsrs[i].buf);
}
}
}
/* Ok, send the whole mess to the CPU. */
- res = jtag_execute_queue();
+ res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK) {
LOG_ERROR("Failed to fetch AR regs!");
goto xtensa_fetch_all_regs_done;
@@ -1305,9 +1306,9 @@ int xtensa_halt(struct target *target)
}
LOG_TARGET_DEBUG(target, "Core status 0x%" PRIx32, xtensa_dm_core_status_get(&xtensa->dbg_mod));
if (!xtensa_is_stopped(target)) {
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DCRSET, OCDDCR_ENABLEOCD | OCDDCR_DEBUGINTERRUPT);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DCRSET, OCDDCR_ENABLEOCD | OCDDCR_DEBUGINTERRUPT);
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
- res = jtag_execute_queue();
+ res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK)
LOG_TARGET_ERROR(target, "Failed to set OCDDCR_DEBUGINTERRUPT. Can't halt.");
}
@@ -1381,7 +1382,7 @@ int xtensa_do_resume(struct target *target)
LOG_TARGET_DEBUG(target, "start");
xtensa_queue_exec_ins(xtensa, XT_INS_RFDO(xtensa));
- int res = jtag_execute_queue();
+ int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK) {
LOG_TARGET_ERROR(target, "Failed to exec RFDO %d!", res);
return res;
@@ -1741,26 +1742,26 @@ int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t si
/* We're going to use A3 here */
xtensa_mark_register_dirty(xtensa, XT_REG_IDX_A3);
/* Write start address to A3 */
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, addrstart_al);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, addrstart_al);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
/* Now we can safely read data from addrstart_al up to addrend_al into albuff */
if (xtensa->probe_lsddr32p != 0) {
xtensa_queue_exec_ins(xtensa, XT_INS_LDDR32P(xtensa, XT_REG_A3));
for (unsigned int i = 0; adr != addrend_al; i += sizeof(uint32_t), adr += sizeof(uint32_t))
xtensa_queue_dbg_reg_read(xtensa,
- (adr + sizeof(uint32_t) == addrend_al) ? NARADR_DDR : NARADR_DDREXEC,
+ (adr + sizeof(uint32_t) == addrend_al) ? XDMREG_DDR : XDMREG_DDREXEC,
&albuff[i]);
} else {
xtensa_mark_register_dirty(xtensa, XT_REG_IDX_A4);
for (unsigned int i = 0; adr != addrend_al; i += sizeof(uint32_t), adr += sizeof(uint32_t)) {
xtensa_queue_exec_ins(xtensa, XT_INS_L32I(xtensa, XT_REG_A3, XT_REG_A4, 0));
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A4));
- xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR, &albuff[i]);
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, adr + sizeof(uint32_t));
+ xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, &albuff[i]);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, adr + sizeof(uint32_t));
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
}
}
- int res = jtag_execute_queue();
+ int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res == ERROR_OK) {
bool prev_suppress = xtensa->suppress_dsr_errors;
xtensa->suppress_dsr_errors = true;
@@ -1856,7 +1857,7 @@ int xtensa_write_memory(struct target *target,
if (fill_head_tail) {
/* See if we need to read the first and/or last word. */
if (address & 3) {
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, addrstart_al);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, addrstart_al);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
if (xtensa->probe_lsddr32p == 1) {
xtensa_queue_exec_ins(xtensa, XT_INS_LDDR32P(xtensa, XT_REG_A3));
@@ -1864,10 +1865,10 @@ int xtensa_write_memory(struct target *target,
xtensa_queue_exec_ins(xtensa, XT_INS_L32I(xtensa, XT_REG_A3, XT_REG_A3, 0));
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3));
}
- xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR, &albuff[0]);
+ xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, &albuff[0]);
}
if ((address + (size * count)) & 3) {
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, addrend_al - 4);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, addrend_al - 4);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
if (xtensa->probe_lsddr32p == 1) {
xtensa_queue_exec_ins(xtensa, XT_INS_LDDR32P(xtensa, XT_REG_A3));
@@ -1875,11 +1876,11 @@ int xtensa_write_memory(struct target *target,
xtensa_queue_exec_ins(xtensa, XT_INS_L32I(xtensa, XT_REG_A3, XT_REG_A3, 0));
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3));
}
- xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR,
+ xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR,
&albuff[addrend_al - addrstart_al - 4]);
}
/* Grab bytes */
- res = jtag_execute_queue();
+ res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK) {
LOG_ERROR("Error issuing unaligned memory write context instruction(s): %d", res);
if (albuff != buffer)
@@ -1911,30 +1912,30 @@ int xtensa_write_memory(struct target *target,
buf_bswap32(albuff, fill_head_tail ? albuff : buffer, addrend_al - addrstart_al);
/* Write start address to A3 */
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, addrstart_al);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, addrstart_al);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
/* Write the aligned buffer */
if (xtensa->probe_lsddr32p != 0) {
for (unsigned int i = 0; adr != addrend_al; i += sizeof(uint32_t), adr += sizeof(uint32_t)) {
if (i == 0) {
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, buf_get_u32(&albuff[i], 0, 32));
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, buf_get_u32(&albuff[i], 0, 32));
xtensa_queue_exec_ins(xtensa, XT_INS_SDDR32P(xtensa, XT_REG_A3));
} else {
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDREXEC, buf_get_u32(&albuff[i], 0, 32));
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDREXEC, buf_get_u32(&albuff[i], 0, 32));
}
}
} else {
xtensa_mark_register_dirty(xtensa, XT_REG_IDX_A4);
for (unsigned int i = 0; adr != addrend_al; i += sizeof(uint32_t), adr += sizeof(uint32_t)) {
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, buf_get_u32(&albuff[i], 0, 32));
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, buf_get_u32(&albuff[i], 0, 32));
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A4));
xtensa_queue_exec_ins(xtensa, XT_INS_S32I(xtensa, XT_REG_A3, XT_REG_A4, 0));
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, adr + sizeof(uint32_t));
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, adr + sizeof(uint32_t));
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
}
}
- res = jtag_execute_queue();
+ res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res == ERROR_OK) {
bool prev_suppress = xtensa->suppress_dsr_errors;
xtensa->suppress_dsr_errors = true;
@@ -1967,7 +1968,7 @@ int xtensa_write_memory(struct target *target,
while ((adr + off) < addrend_al) {
if (off == 0) {
/* Write start address to A3 */
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, adr);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, adr);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
}
if (issue_ihi)
@@ -1983,7 +1984,7 @@ int xtensa_write_memory(struct target *target,
}
/* Execute cache WB/INV instructions */
- res = jtag_execute_queue();
+ res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
xtensa_core_status_check(target);
if (res != ERROR_OK)
LOG_TARGET_ERROR(target,
@@ -2013,7 +2014,8 @@ int xtensa_poll(struct target *target)
{
struct xtensa *xtensa = target_to_xtensa(target);
- int res = xtensa_dm_power_status_read(&xtensa->dbg_mod, PWRSTAT_DEBUGWASRESET | PWRSTAT_COREWASRESET);
+ int res = xtensa_dm_power_status_read(&xtensa->dbg_mod, PWRSTAT_DEBUGWASRESET |
+ PWRSTAT_COREWASRESET);
if (xtensa->dbg_mod.power_status.stat != xtensa->dbg_mod.power_status.stath)
LOG_TARGET_DEBUG(target, "PWRSTAT: read 0x%08" PRIx32 ", clear 0x%08lx, reread 0x%08" PRIx32,
xtensa->dbg_mod.power_status.stat,
@@ -2141,7 +2143,7 @@ static int xtensa_update_instruction(struct target *target, target_addr_t addres
xtensa_mark_register_dirty(xtensa, XT_REG_IDX_A3);
/* Write start address to A3 and invalidate */
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, address);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, address);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
LOG_TARGET_DEBUG(target, "DHWBI, IHI for address "TARGET_ADDR_FMT, address);
if (issue_dhwbi) {
@@ -2164,7 +2166,7 @@ static int xtensa_update_instruction(struct target *target, target_addr_t addres
}
/* Execute invalidate instructions */
- ret = jtag_execute_queue();
+ ret = xtensa_dm_queue_execute(&xtensa->dbg_mod);
xtensa_core_status_check(target);
if (ret != ERROR_OK) {
LOG_ERROR("Error issuing cache invaldate instruction(s): %d", ret);
@@ -2181,7 +2183,7 @@ static int xtensa_update_instruction(struct target *target, target_addr_t addres
if (issue_dhwbi) {
/* Flush dcache so instruction propagates. A3 may be corrupted during memory write */
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, address);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, address);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
xtensa_queue_exec_ins(xtensa, XT_INS_DHWB(xtensa, XT_REG_A3, 0));
LOG_DEBUG("DHWB dcache line for address "TARGET_ADDR_FMT, address);
@@ -2191,7 +2193,7 @@ static int xtensa_update_instruction(struct target *target, target_addr_t addres
}
/* Execute invalidate instructions */
- ret = jtag_execute_queue();
+ ret = xtensa_dm_queue_execute(&xtensa->dbg_mod);
xtensa_core_status_check(target);
}
@@ -2658,15 +2660,15 @@ static int xtensa_gdbqc_qxtreg(struct target *target, const char *packet, char *
}
}
xtensa_reg_val_t orig_a4 = xtensa_reg_get(target, XT_REG_IDX_A4);
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, xtensa->spill_loc);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, xtensa->spill_loc);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A4));
int32_t tieop_status = xtensa_gdbqc_parse_exec_tie_ops(target, delim);
/* Restore a4 but not yet spill memory. Execute it all... */
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, orig_a4);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, orig_a4);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A4));
- status = jtag_execute_queue();
+ status = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (status != ERROR_OK) {
LOG_TARGET_ERROR(target, "TIE queue execute: %d\n", status);
tieop_status = status;
@@ -2944,13 +2946,13 @@ void xtensa_target_deinit(struct target *target)
LOG_DEBUG("start");
if (target_was_examined(target)) {
- int ret = xtensa_queue_dbg_reg_write(xtensa, NARADR_DCRCLR, OCDDCR_ENABLEOCD);
+ int ret = xtensa_queue_dbg_reg_write(xtensa, XDMREG_DCRCLR, OCDDCR_ENABLEOCD);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to queue OCDDCR_ENABLEOCD clear operation!");
return;
}
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
- ret = jtag_execute_queue();
+ ret = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to clear OCDDCR_ENABLEOCD!");
return;
@@ -3013,17 +3015,17 @@ COMMAND_HELPER(xtensa_cmd_exe_do, struct target *target)
xtensa_reg_val_t exccause = xtensa_reg_get(target, XT_REG_IDX_EXCCAUSE);
xtensa_reg_val_t cpenable = xtensa_reg_get(target, XT_REG_IDX_CPENABLE);
xtensa_reg_val_t a3 = xtensa_reg_get(target, XT_REG_IDX_A3);
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, 0xffffffff);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, 0xffffffff);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa,
xtensa_regs[XT_REG_IDX_CPENABLE].reg_num, XT_REG_A3));
- xtensa_queue_dbg_reg_write(xtensa, NARADR_DDR, a3);
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, a3);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
/* Queue instruction list and execute everything */
LOG_TARGET_DEBUG(target, "execute stub: %s", CMD_ARGV[0]);
xtensa_queue_exec_ins_wide(xtensa, ops, oplen); /* Handles endian-swap */
- status = jtag_execute_queue();
+ status = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (status != ERROR_OK)
LOG_TARGET_ERROR(target, "TIE queue execute: %d\n", status);
status = xtensa_core_status_check(target);
@@ -3346,8 +3348,9 @@ COMMAND_HELPER(xtensa_cmd_xtreg_do, struct xtensa *xtensa)
return ERROR_FAIL;
}
return ERROR_OK;
- } else if (CMD_ARGC != 2)
+ } else if (CMD_ARGC != 2) {
return ERROR_COMMAND_SYNTAX_ERROR;
+ }
/* "xtregfmt contiguous" must be specified prior to the first "xtreg" definition
* if general register (g-packet) requests or contiguous register maps are supported */
@@ -3471,7 +3474,7 @@ COMMAND_HELPER(xtensa_cmd_xtregfmt_do, struct xtensa *xtensa)
unsigned int numgregs = strtoul(CMD_ARGV[1], NULL, 0);
if ((numgregs <= 0) ||
((numgregs > xtensa->total_regs_num) &&
- (xtensa->total_regs_num > 0))) {
+ (xtensa->total_regs_num > 0))) {
LOG_ERROR("xtregfmt: if specified, numgregs (%d) must be <= numregs (%d)",
numgregs, xtensa->total_regs_num);
return ERROR_COMMAND_SYNTAX_ERROR;
diff --git a/src/target/xtensa/xtensa.h b/src/target/xtensa/xtensa.h
index fd03f07f8..4d98f3a36 100644
--- a/src/target/xtensa/xtensa.h
+++ b/src/target/xtensa/xtensa.h
@@ -273,24 +273,24 @@ static inline bool xtensa_data_addr_valid(struct target *target, uint32_t addr)
return false;
}
-static inline int xtensa_queue_dbg_reg_read(struct xtensa *xtensa, unsigned int reg, uint8_t *data)
+static inline int xtensa_queue_dbg_reg_read(struct xtensa *xtensa, enum xtensa_dm_reg reg, uint8_t *data)
{
struct xtensa_debug_module *dm = &xtensa->dbg_mod;
if (!xtensa->core_config->trace.enabled &&
- (reg <= NARADR_MEMADDREND || (reg >= NARADR_PMG && reg <= NARADR_PMSTAT7))) {
+ (reg <= XDMREG_MEMADDREND || (reg >= XDMREG_PMG && reg <= XDMREG_PMSTAT7))) {
LOG_ERROR("Can not access %u reg when Trace Port option disabled!", reg);
return ERROR_FAIL;
}
return dm->dbg_ops->queue_reg_read(dm, reg, data);
}
-static inline int xtensa_queue_dbg_reg_write(struct xtensa *xtensa, unsigned int reg, uint32_t data)
+static inline int xtensa_queue_dbg_reg_write(struct xtensa *xtensa, enum xtensa_dm_reg reg, uint32_t data)
{
struct xtensa_debug_module *dm = &xtensa->dbg_mod;
if (!xtensa->core_config->trace.enabled &&
- (reg <= NARADR_MEMADDREND || (reg >= NARADR_PMG && reg <= NARADR_PMSTAT7))) {
+ (reg <= XDMREG_MEMADDREND || (reg >= XDMREG_PMG && reg <= XDMREG_PMSTAT7))) {
LOG_ERROR("Can not access %u reg when Trace Port option disabled!", reg);
return ERROR_FAIL;
}
diff --git a/src/target/xtensa/xtensa_debug_module.c b/src/target/xtensa/xtensa_debug_module.c
index a7de1ad5c..7f8a75bc6 100644
--- a/src/target/xtensa/xtensa_debug_module.c
+++ b/src/target/xtensa/xtensa_debug_module.c
@@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
- * Generic Xtensa debug module API for OpenOCD *
+ * Xtensa Debug Module (XDM) Support for OpenOCD *
+ * Copyright (C) 2020-2022 Cadence Design Systems, Inc. *
* Copyright (C) 2019 Espressif Systems Ltd. *
***************************************************************************/
@@ -24,11 +25,14 @@
#define TAPINS_IDCODE_LEN 32
#define TAPINS_BYPASS_LEN 1
+/* Table of debug register offsets for Nexus and APB space */
+static const struct xtensa_dm_reg_offsets xdm_regs[XDMREG_NUM] =
+ XTENSA_DM_REG_OFFSETS;
static void xtensa_dm_add_set_ir(struct xtensa_debug_module *dm, uint8_t value)
{
struct scan_field field;
- uint8_t t[4] = { 0 };
+ uint8_t t[4] = { 0, 0, 0, 0 };
memset(&field, 0, sizeof(field));
field.num_bits = dm->tap->ir_length;
@@ -67,76 +71,65 @@ int xtensa_dm_init(struct xtensa_debug_module *dm, const struct xtensa_debug_mod
int xtensa_dm_queue_enable(struct xtensa_debug_module *dm)
{
- return dm->dbg_ops->queue_reg_write(dm, NARADR_DCRSET, OCDDCR_ENABLEOCD);
+ return dm->dbg_ops->queue_reg_write(dm, XDMREG_DCRSET, OCDDCR_ENABLEOCD);
}
-int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, unsigned int reg, uint8_t *value)
+int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value)
{
- uint8_t regdata = (reg << 1) | 0;
- uint8_t dummy[4] = { 0, 0, 0, 0 };
-
- if (reg > NARADR_MAX) {
+ if (reg >= XDMREG_NUM) {
LOG_ERROR("Invalid DBG reg ID %d!", reg);
return ERROR_FAIL;
}
+ uint8_t regdata = (xdm_regs[reg].nar << 1) | 0;
+ uint8_t dummy[4] = { 0, 0, 0, 0 };
xtensa_dm_add_set_ir(dm, TAPINS_NARSEL);
xtensa_dm_add_dr_scan(dm, TAPINS_NARSEL_ADRLEN, ®data, NULL, TAP_IDLE);
xtensa_dm_add_dr_scan(dm, TAPINS_NARSEL_DATALEN, dummy, value, TAP_IDLE);
return ERROR_OK;
}
-int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, unsigned int reg, uint32_t value)
+int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value)
{
- uint8_t regdata = (reg << 1) | 1;
- uint8_t valdata[] = { value, value >> 8, value >> 16, value >> 24 };
-
- if (reg > NARADR_MAX) {
+ if (reg >= XDMREG_NUM) {
LOG_ERROR("Invalid DBG reg ID %d!", reg);
return ERROR_FAIL;
}
+ uint8_t regdata = (xdm_regs[reg].nar << 1) | 1;
+ uint8_t valdata[] = { value, value >> 8, value >> 16, value >> 24 };
xtensa_dm_add_set_ir(dm, TAPINS_NARSEL);
xtensa_dm_add_dr_scan(dm, TAPINS_NARSEL_ADRLEN, ®data, NULL, TAP_IDLE);
xtensa_dm_add_dr_scan(dm, TAPINS_NARSEL_DATALEN, valdata, NULL, TAP_IDLE);
return ERROR_OK;
}
-int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm, unsigned int reg, uint8_t *data, uint8_t clear)
+int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm,
+ enum xtensa_dm_pwr_reg reg,
+ uint8_t *data,
+ uint32_t clear)
{
- uint8_t value_clr = clear;
- uint8_t tap_insn;
- int tap_insn_sz;
-
- if (reg == DMREG_PWRCTL) {
- tap_insn = TAPINS_PWRCTL;
- tap_insn_sz = TAPINS_PWRCTL_LEN;
- } else if (reg == DMREG_PWRSTAT) {
- tap_insn = TAPINS_PWRSTAT;
- tap_insn_sz = TAPINS_PWRSTAT_LEN;
- } else {
+ if (reg >= XDMREG_PWRNUM) {
LOG_ERROR("Invalid PWR reg ID %d!", reg);
return ERROR_FAIL;
}
+ uint8_t value_clr = (uint8_t)clear;
+ uint8_t tap_insn = (reg == XDMREG_PWRCTL) ? TAPINS_PWRCTL : TAPINS_PWRSTAT;
+ int tap_insn_sz = (reg == XDMREG_PWRCTL) ? TAPINS_PWRCTL_LEN : TAPINS_PWRSTAT_LEN;
xtensa_dm_add_set_ir(dm, tap_insn);
xtensa_dm_add_dr_scan(dm, tap_insn_sz, &value_clr, data, TAP_IDLE);
return ERROR_OK;
}
-int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm, unsigned int reg, uint8_t data)
+int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm,
+ enum xtensa_dm_pwr_reg reg,
+ uint32_t data)
{
- uint8_t value = data;
- uint8_t tap_insn;
- int tap_insn_sz;
-
- if (reg == DMREG_PWRCTL) {
- tap_insn = TAPINS_PWRCTL;
- tap_insn_sz = TAPINS_PWRCTL_LEN;
- } else if (reg == DMREG_PWRSTAT) {
- tap_insn = TAPINS_PWRSTAT;
- tap_insn_sz = TAPINS_PWRSTAT_LEN;
- } else {
+ if (reg >= XDMREG_PWRNUM) {
LOG_ERROR("Invalid PWR reg ID %d!", reg);
return ERROR_FAIL;
}
+ uint8_t tap_insn = (reg == XDMREG_PWRCTL) ? TAPINS_PWRCTL : TAPINS_PWRSTAT;
+ int tap_insn_sz = (reg == XDMREG_PWRCTL) ? TAPINS_PWRCTL_LEN : TAPINS_PWRSTAT_LEN;
+ uint8_t value = (uint8_t)data;
xtensa_dm_add_set_ir(dm, tap_insn);
xtensa_dm_add_dr_scan(dm, tap_insn_sz, &value, NULL, TAP_IDLE);
return ERROR_OK;
@@ -146,9 +139,9 @@ int xtensa_dm_device_id_read(struct xtensa_debug_module *dm)
{
uint8_t id_buf[sizeof(uint32_t)];
- dm->dbg_ops->queue_reg_read(dm, NARADR_OCDID, id_buf);
+ dm->dbg_ops->queue_reg_read(dm, XDMREG_OCDID, id_buf);
xtensa_dm_queue_tdi_idle(dm);
- int res = jtag_execute_queue();
+ int res = xtensa_dm_queue_execute(dm);
if (res != ERROR_OK)
return res;
dm->device_id = buf_get_u32(id_buf, 0, 32);
@@ -157,16 +150,22 @@ int xtensa_dm_device_id_read(struct xtensa_debug_module *dm)
int xtensa_dm_power_status_read(struct xtensa_debug_module *dm, uint32_t clear)
{
- /* uint8_t id_buf[sizeof(uint32_t)]; */
+ uint8_t stat_buf[sizeof(uint32_t)];
+ uint8_t stath_buf[sizeof(uint32_t)];
/* TODO: JTAG does not work when PWRCTL_JTAGDEBUGUSE is not set.
- * It is set in xtensa_examine(), need to move reading of NARADR_OCDID out of this function */
- /* dm->dbg_ops->queue_reg_read(dm, NARADR_OCDID, id_buf);
+ * It is set in xtensa_examine(), need to move reading of XDMREG_OCDID out of this function */
+ /* dm->dbg_ops->queue_reg_read(dm, XDMREG_OCDID, id_buf);
*Read reset state */
- dm->pwr_ops->queue_reg_read(dm, DMREG_PWRSTAT, &dm->power_status.stat, clear);
- dm->pwr_ops->queue_reg_read(dm, DMREG_PWRSTAT, &dm->power_status.stath, clear);
+ dm->pwr_ops->queue_reg_read(dm, XDMREG_PWRSTAT, stat_buf, clear);
+ dm->pwr_ops->queue_reg_read(dm, XDMREG_PWRSTAT, stath_buf, clear);
xtensa_dm_queue_tdi_idle(dm);
- return jtag_execute_queue();
+ int res = xtensa_dm_queue_execute(dm);
+ if (res != ERROR_OK)
+ return res;
+ dm->power_status.stat = buf_get_u32(stat_buf, 0, 32);
+ dm->power_status.stath = buf_get_u32(stath_buf, 0, 32);
+ return res;
}
int xtensa_dm_core_status_read(struct xtensa_debug_module *dm)
@@ -174,9 +173,9 @@ int xtensa_dm_core_status_read(struct xtensa_debug_module *dm)
uint8_t dsr_buf[sizeof(uint32_t)];
xtensa_dm_queue_enable(dm);
- dm->dbg_ops->queue_reg_read(dm, NARADR_DSR, dsr_buf);
+ dm->dbg_ops->queue_reg_read(dm, XDMREG_DSR, dsr_buf);
xtensa_dm_queue_tdi_idle(dm);
- int res = jtag_execute_queue();
+ int res = xtensa_dm_queue_execute(dm);
if (res != ERROR_OK)
return res;
dm->core_status.dsr = buf_get_u32(dsr_buf, 0, 32);
@@ -185,37 +184,37 @@ int xtensa_dm_core_status_read(struct xtensa_debug_module *dm)
int xtensa_dm_core_status_clear(struct xtensa_debug_module *dm, xtensa_dsr_t bits)
{
- dm->dbg_ops->queue_reg_write(dm, NARADR_DSR, bits);
+ dm->dbg_ops->queue_reg_write(dm, XDMREG_DSR, bits);
xtensa_dm_queue_tdi_idle(dm);
- return jtag_execute_queue();
+ return xtensa_dm_queue_execute(dm);
}
int xtensa_dm_trace_start(struct xtensa_debug_module *dm, struct xtensa_trace_start_config *cfg)
{
/*Turn off trace unit so we can start a new trace. */
- dm->dbg_ops->queue_reg_write(dm, NARADR_TRAXCTRL, 0);
+ dm->dbg_ops->queue_reg_write(dm, XDMREG_TRAXCTRL, 0);
xtensa_dm_queue_tdi_idle(dm);
- int res = jtag_execute_queue();
+ int res = xtensa_dm_queue_execute(dm);
if (res != ERROR_OK)
return res;
/*Set up parameters */
- dm->dbg_ops->queue_reg_write(dm, NARADR_TRAXADDR, 0);
+ dm->dbg_ops->queue_reg_write(dm, XDMREG_TRAXADDR, 0);
if (cfg->stopmask != XTENSA_STOPMASK_DISABLED) {
- dm->dbg_ops->queue_reg_write(dm, NARADR_PCMATCHCTRL,
+ dm->dbg_ops->queue_reg_write(dm, XDMREG_PCMATCHCTRL,
(cfg->stopmask << PCMATCHCTRL_PCML_SHIFT));
- dm->dbg_ops->queue_reg_write(dm, NARADR_TRIGGERPC, cfg->stoppc);
+ dm->dbg_ops->queue_reg_write(dm, XDMREG_TRIGGERPC, cfg->stoppc);
}
- dm->dbg_ops->queue_reg_write(dm, NARADR_DELAYCNT, cfg->after);
+ dm->dbg_ops->queue_reg_write(dm, XDMREG_DELAYCNT, cfg->after);
/*Options are mostly hardcoded for now. ToDo: make this more configurable. */
dm->dbg_ops->queue_reg_write(
dm,
- NARADR_TRAXCTRL,
+ XDMREG_TRAXCTRL,
TRAXCTRL_TREN |
((cfg->stopmask != XTENSA_STOPMASK_DISABLED) ? TRAXCTRL_PCMEN : 0) | TRAXCTRL_TMEN |
(cfg->after_is_words ? 0 : TRAXCTRL_CNTU) | (0 << TRAXCTRL_SMPER_SHIFT) | TRAXCTRL_PTOWS);
xtensa_dm_queue_tdi_idle(dm);
- return jtag_execute_queue();
+ return xtensa_dm_queue_execute(dm);
}
int xtensa_dm_trace_stop(struct xtensa_debug_module *dm, bool pto_enable)
@@ -224,9 +223,9 @@ int xtensa_dm_trace_stop(struct xtensa_debug_module *dm, bool pto_enable)
uint32_t traxctl;
struct xtensa_trace_status trace_status;
- dm->dbg_ops->queue_reg_read(dm, NARADR_TRAXCTRL, traxctl_buf);
+ dm->dbg_ops->queue_reg_read(dm, XDMREG_TRAXCTRL, traxctl_buf);
xtensa_dm_queue_tdi_idle(dm);
- int res = jtag_execute_queue();
+ int res = xtensa_dm_queue_execute(dm);
if (res != ERROR_OK)
return res;
traxctl = buf_get_u32(traxctl_buf, 0, 32);
@@ -234,9 +233,9 @@ int xtensa_dm_trace_stop(struct xtensa_debug_module *dm, bool pto_enable)
if (!pto_enable)
traxctl &= ~(TRAXCTRL_PTOWS | TRAXCTRL_PTOWT);
- dm->dbg_ops->queue_reg_write(dm, NARADR_TRAXCTRL, traxctl | TRAXCTRL_TRSTP);
+ dm->dbg_ops->queue_reg_write(dm, XDMREG_TRAXCTRL, traxctl | TRAXCTRL_TRSTP);
xtensa_dm_queue_tdi_idle(dm);
- res = jtag_execute_queue();
+ res = xtensa_dm_queue_execute(dm);
if (res != ERROR_OK)
return res;
@@ -256,9 +255,9 @@ int xtensa_dm_trace_status_read(struct xtensa_debug_module *dm, struct xtensa_tr
{
uint8_t traxstat_buf[sizeof(uint32_t)];
- dm->dbg_ops->queue_reg_read(dm, NARADR_TRAXSTAT, traxstat_buf);
+ dm->dbg_ops->queue_reg_read(dm, XDMREG_TRAXSTAT, traxstat_buf);
xtensa_dm_queue_tdi_idle(dm);
- int res = jtag_execute_queue();
+ int res = xtensa_dm_queue_execute(dm);
if (res == ERROR_OK && status)
status->stat = buf_get_u32(traxstat_buf, 0, 32);
return res;
@@ -274,12 +273,12 @@ int xtensa_dm_trace_config_read(struct xtensa_debug_module *dm, struct xtensa_tr
if (!config)
return ERROR_FAIL;
- dm->dbg_ops->queue_reg_read(dm, NARADR_TRAXCTRL, traxctl_buf);
- dm->dbg_ops->queue_reg_read(dm, NARADR_MEMADDRSTART, memadrstart_buf);
- dm->dbg_ops->queue_reg_read(dm, NARADR_MEMADDREND, memadrend_buf);
- dm->dbg_ops->queue_reg_read(dm, NARADR_TRAXADDR, adr_buf);
+ dm->dbg_ops->queue_reg_read(dm, XDMREG_TRAXCTRL, traxctl_buf);
+ dm->dbg_ops->queue_reg_read(dm, XDMREG_MEMADDRSTART, memadrstart_buf);
+ dm->dbg_ops->queue_reg_read(dm, XDMREG_MEMADDREND, memadrend_buf);
+ dm->dbg_ops->queue_reg_read(dm, XDMREG_TRAXADDR, adr_buf);
xtensa_dm_queue_tdi_idle(dm);
- int res = jtag_execute_queue();
+ int res = xtensa_dm_queue_execute(dm);
if (res == ERROR_OK) {
config->ctrl = buf_get_u32(traxctl_buf, 0, 32);
config->memaddr_start = buf_get_u32(memadrstart_buf, 0, 32);
@@ -295,9 +294,9 @@ int xtensa_dm_trace_data_read(struct xtensa_debug_module *dm, uint8_t *dest, uin
return ERROR_FAIL;
for (unsigned int i = 0; i < size / 4; i++)
- dm->dbg_ops->queue_reg_read(dm, NARADR_TRAXDATA, &dest[i * 4]);
+ dm->dbg_ops->queue_reg_read(dm, XDMREG_TRAXDATA, &dest[i * 4]);
xtensa_dm_queue_tdi_idle(dm);
- return jtag_execute_queue();
+ return xtensa_dm_queue_execute(dm);
}
int xtensa_dm_perfmon_enable(struct xtensa_debug_module *dm, int counter_id,
@@ -313,13 +312,13 @@ int xtensa_dm_perfmon_enable(struct xtensa_debug_module *dm, int counter_id,
(config->kernelcnt << 3);
/* enable performance monitor */
- dm->dbg_ops->queue_reg_write(dm, NARADR_PMG, 0x1);
+ dm->dbg_ops->queue_reg_write(dm, XDMREG_PMG, 0x1);
/* reset counter */
- dm->dbg_ops->queue_reg_write(dm, NARADR_PM0 + counter_id, 0);
- dm->dbg_ops->queue_reg_write(dm, NARADR_PMCTRL0 + counter_id, pmctrl);
- dm->dbg_ops->queue_reg_read(dm, NARADR_PMSTAT0 + counter_id, pmstat_buf);
+ dm->dbg_ops->queue_reg_write(dm, XDMREG_PM0 + counter_id, 0);
+ dm->dbg_ops->queue_reg_write(dm, XDMREG_PMCTRL0 + counter_id, pmctrl);
+ dm->dbg_ops->queue_reg_read(dm, XDMREG_PMSTAT0 + counter_id, pmstat_buf);
xtensa_dm_queue_tdi_idle(dm);
- return jtag_execute_queue();
+ return xtensa_dm_queue_execute(dm);
}
int xtensa_dm_perfmon_dump(struct xtensa_debug_module *dm, int counter_id,
@@ -328,10 +327,10 @@ int xtensa_dm_perfmon_dump(struct xtensa_debug_module *dm, int counter_id,
uint8_t pmstat_buf[4];
uint8_t pmcount_buf[4];
- dm->dbg_ops->queue_reg_read(dm, NARADR_PMSTAT0 + counter_id, pmstat_buf);
- dm->dbg_ops->queue_reg_read(dm, NARADR_PM0 + counter_id, pmcount_buf);
+ dm->dbg_ops->queue_reg_read(dm, XDMREG_PMSTAT0 + counter_id, pmstat_buf);
+ dm->dbg_ops->queue_reg_read(dm, XDMREG_PM0 + counter_id, pmcount_buf);
xtensa_dm_queue_tdi_idle(dm);
- int res = jtag_execute_queue();
+ int res = xtensa_dm_queue_execute(dm);
if (res == ERROR_OK) {
uint32_t stat = buf_get_u32(pmstat_buf, 0, 32);
uint64_t result = buf_get_u32(pmcount_buf, 0, 32);
diff --git a/src/target/xtensa/xtensa_debug_module.h b/src/target/xtensa/xtensa_debug_module.h
index 189a6c97a..b4bb88682 100644
--- a/src/target/xtensa/xtensa_debug_module.h
+++ b/src/target/xtensa/xtensa_debug_module.h
@@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
- * Xtensa debug module API *
+ * Xtensa Debug Module (XDM) Support for OpenOCD *
+ * Copyright (C) 2020-2022 Cadence Design Systems, Inc. *
* Copyright (C) 2019 Espressif Systems Ltd. *
* Derived from original ESP8266 target. *
* Author: Angus Gratton gu...@pr... *
@@ -15,8 +16,23 @@
#include <target/target.h>
/* Virtual IDs for using with xtensa_power_ops API */
-#define DMREG_PWRCTL 0x00
-#define DMREG_PWRSTAT 0x01
+enum xtensa_dm_pwr_reg {
+ XDMREG_PWRCTL = 0x00,
+ XDMREG_PWRSTAT,
+ XDMREG_PWRNUM
+};
+
+/* Debug Module Power Register offsets within APB */
+struct xtensa_dm_pwr_reg_offsets {
+ uint16_t apb;
+};
+
+/* Debug Module Power Register offset structure; must include XDMREG_PWRNUM entries */
+#define XTENSA_DM_PWR_REG_OFFSETS { \
+ /* Power/Reset Registers */ \
+ { .apb = 0x3020 }, /* XDMREG_PWRCTL */ \
+ { .apb = 0x3024 }, /* XDMREG_PWRSTAT */ \
+}
/*
From the manual:
@@ -42,68 +58,187 @@
#define PWRSTAT_DEBUGDOMAINON BIT(2)
#define PWRSTAT_MEMDOMAINON BIT(1)
#define PWRSTAT_COREDOMAINON BIT(0)
+/* Virtual IDs for using with xtensa_debug_ops API */
+enum xtensa_dm_reg {
+ /* TRAX Registers */
+ XDMREG_TRAXID = 0x00,
+ XDMREG_TRAXCTRL,
+ XDMREG_TRAXSTAT,
+ XDMREG_TRAXDATA,
+ XDMREG_TRAXADDR,
+ XDMREG_TRIGGERPC,
+ XDMREG_PCMATCHCTRL,
+ XDMREG_DELAYCNT,
+ XDMREG_MEMADDRSTART,
+ XDMREG_MEMADDREND,
+
+ /* Performance Monitor Registers */
+ XDMREG_PMG,
+ XDMREG_INTPC,
+ XDMREG_PM0,
+ XDMREG_PM1,
+ XDMREG_PM2,
+ XDMREG_PM3,
+ XDMREG_PM4,
+ XDMREG_PM5,
+ XDMREG_PM6,
+ XDMREG_PM7,
+ XDMREG_PMCTRL0,
+ XDMREG_PMCTRL1,
+ XDMREG_PMCTRL2,
+ XDMREG_PMCTRL3,
+ XDMREG_PMCTRL4,
+ XDMREG_PMCTRL5,
+ XDMREG_PMCTRL6,
+ XDMREG_PMCTRL7,
+ XDMREG_PMSTAT0,
+ XDMREG_PMSTAT1,
+ XDMREG_PMSTAT2,
+ XDMREG_PMSTAT3,
+ XDMREG_PMSTAT4,
+ XDMREG_PMSTAT5,
+ XDMREG_PMSTAT6,
+ XDMREG_PMSTAT7,
+
+ /* OCD Registers */
+ XDMREG_OCDID,
+ XDMREG_DCRCLR,
+ XDMREG_DCRSET,
+ XDMREG_DSR,
+ XDMREG_DDR,
+ XDMREG_DDREXEC,
+ XDMREG_DIR0EXEC,
+ XDMREG_DIR0,
+ XDMREG_DIR1,
+ XDMREG_DIR2,
+ XDMREG_DIR3,
+ XDMREG_DIR4,
+ XDMREG_DIR5,
+ XDMREG_DIR6,
+ XDMREG_DIR7,
+
+ /* Misc Registers */
+ XDMREG_ERISTAT,
+
+ /* CoreSight Registers */
+ XDMREG_ITCTRL,
+ XDMREG_CLAIMSET,
+ XDMREG_CLAIMCLR,
+ XDMREG_LOCKACCESS,
+ XDMREG_LOCKSTATUS,
+ XDMREG_AUTHSTATUS,
+ XDMREG_DEVID,
+ XDMREG_DEVTYPE,
+ XDMREG_PERID4,
+ XDMREG_PERID5,
+ XDMREG_PERID6,
+ XDMREG_PERID7,
+ XDMREG_PERID0,
+ XDMREG_PERID1,
+ XDMREG_PERID2,
+ XDMREG_PERID3,
+ XDMREG_COMPID0,
+ XDMREG_COMPID1,
+ XDMREG_COMPID2,
+ XDMREG_COMPID3,
+
+ XDMREG_NUM
+};
-/* *** NAR addresses (also used as IDs for debug registers in xtensa_debug_ops API) ***
- *TRAX registers */
-#define NARADR_TRAXID 0x00
-#define NARADR_TRAXCTRL 0x01
-#define NARADR_TRAXSTAT 0x02
-#define NARADR_TRAXDATA 0x03
-#define NARADR_TRAXADDR 0x04
-#define NARADR_TRIGGERPC 0x05
-#define NARADR_PCMATCHCTRL 0x06
-#define NARADR_DELAYCNT 0x07
-#define NARADR_MEMADDRSTART 0x08
-#define NARADR_MEMADDREND 0x09
-/*Performance monitor registers */
-#define NARADR_PMG 0x20
-#define NARADR_INTPC 0x24
-#define NARADR_PM0 0x28
-/*... */
-#define NARADR_PM7 0x2F
-#define NARADR_PMCTRL0 0x30
-/*... */
-#define NARADR_PMCTRL7 0x37
-#define NARADR_PMSTAT0 0x38
-/*... */
-#define NARADR_PMSTAT7 0x3F
-/*OCD registers */
-#define NARADR_OCDID 0x40
-#define NARADR_DCRCLR 0x42
-#define NARADR_DCRSET 0x43
-#define NARADR_DSR 0x44
-#define NARADR_DDR 0x45
-#define NARADR_DDREXEC 0x46
-#define NARADR_DIR0EXEC 0x47
-#define NARADR_DIR0 0x48
-#define NARADR_DIR1 0x49
-/*... */
-#define NARADR_DIR7 0x4F
-/*Misc registers */
-#define NARADR_PWRCTL 0x58
-#define NARADR_PWRSTAT 0x59
-#define NARADR_ERISTAT 0x5A
-/*CoreSight registers */
-#define NARADR_ITCTRL 0x60
-#define NARADR_CLAIMSET 0x68
-#define NARADR_CLAIMCLR 0x69
-#define NARADR_LOCKACCESS 0x6c
-#define NARADR_LOCKSTATUS 0x6d
-#define NARADR_AUTHSTATUS 0x6e
-#define NARADR_DEVID 0x72
-#define NARADR_DEVTYPE 0x73
-#define NARADR_PERID4 0x74
-/*... */
-#define NARADR_PERID7 0x77
-#define NARADR_PERID0 0x78
-/*... */
-#define NARADR_PERID3 0x7b
-#define NARADR_COMPID0 0x7c
-/*... */
-#define NARADR_COMPID3 0x7f
-#define NARADR_MAX NARADR_COMPID3
-
-/*OCD registers, bit definitions */
+/* Debug Module Register offsets within Nexus (NAR) or APB */
+struct xtensa_dm_reg_offsets {
+ uint8_t nar;
+ uint16_t apb;
+};
+
+/* Debug Module Register offset structure; must include XDMREG_NUM entries */
+#define XTENSA_DM_REG_OFFSETS { \
+ /* TRAX Registers */ \
+ { .nar = 0x00, .apb = 0x0000 }, /* XDMREG_TRAXID */ \
+ { .nar = 0x01, .apb = 0x0004 }, /* XDMREG_TRAXCTRL */ \
+ { .nar = 0x02, .apb = 0x0008 }, /* XDMREG_TRAXSTAT */ \
+ { .nar = 0x03, .apb = 0x000c }, /* XDMREG_TRAXDATA */ \
+ { .nar = 0x04, .apb = 0x0010 }, /* XDMREG_TRAXADDR */ \
+ { .nar = 0x05, .apb = 0x0014 }, /* XDMREG_TRIGGERPC */ \
+ { .nar = 0x06, .apb = 0x0018 }, /* XDMREG_PCMATCHCTRL */ \
+ { .nar = 0x07, .apb = 0x001c }, /* XDMREG_DELAYCNT */ \
+ { .nar = 0x08, .apb = 0x0020 }, /* XDMREG_MEMADDRSTART */ \
+ { .nar = 0x09, .apb = 0x0024 }, /* XDMREG_MEMADDREND */ \
+ \
+ /* Performance Monitor Registers */ \
+ { .nar = 0x20, .apb = 0x1000 }, /* XDMREG_PMG */ \
+ { .nar = 0x24, .apb = 0x1010 }, /* XDMREG_INTPC */ \
+ { .nar = 0x28, .apb = 0x1080 }, /* XDMREG_PM0 */ \
+ { .nar = 0x29, .apb = 0x1084 }, /* XDMREG_PM1 */ \
+ { .nar = 0x2a, .apb = 0x1088 }, /* XDMREG_PM2 */ \
+ { .nar = 0x2b, .apb = 0x108c }, /* XDMREG_PM3 */ \
+ { .nar = 0x2c, .apb = 0x1090 }, /* XDMREG_PM4 */ \
+ { .nar = 0x2d, .apb = 0x1094 }, /* XDMREG_PM5 */ \
+ { .nar = 0x2e, .apb = 0x1098 }, /* XDMREG_PM6 */ \
+ { .nar = 0x2f, .apb = 0x109c }, /* XDMREG_PM7 */ \
+ { .nar = 0x30, .apb = 0x1100 }, /* XDMREG_PMCTRL0 */ \
+ { .nar = 0x31, .apb = 0x1104 }, /* XDMREG_PMCTRL1 */ \
+ { .nar = 0x32, .apb = 0x1108 }, /* XDMREG_PMCTRL2 */ \
+ { .nar = 0x33, .apb = 0x110c }, /* XDMREG_PMCTRL3 */ \
+ { .nar = 0x34, .apb = 0x1110 }, /* XDMREG_PMCTRL4 */ \
+ { .nar = 0x35, .apb = 0x1114 }, /* XDMREG_PMCTRL5 */ \
+ { .nar = 0x36, .apb = 0x1118 }, /* XDMREG_PMCTRL6 */ \
+ { .nar = 0x37, .apb = 0x111c }, /* XDMREG_PMCTRL7 */ \
+ { .nar = 0x38, .apb = 0x1180 }, /* XDMREG_PMSTAT0 */ \
+ { .nar = 0x39, .apb = 0x1184 }, /* XDMREG_PMSTAT1 */ \
+ { .nar = 0x3a, .apb = 0x1188 }, /* XDMREG_PMSTAT2 */ \
+ { .nar = 0x3b, .apb = 0x118c }, /* XDMREG_PMSTAT3 */ \
+ { .nar = 0x3c, .apb = 0x1190 }, /* XDMREG_PMSTAT4 */ \
+ { .nar = 0x3d, .apb = 0x1194 }, /* XDMREG_PMSTAT5 */ \
+ { .nar = 0x3e, .apb = 0x1198 }, /* XDMREG_PMSTAT6 */ \
+ { .nar = 0x3f, .apb = 0x119c }, /* XDMREG_PMSTAT7 */ \
+ \
+ /* OCD Registers */ \
+ { .nar = 0x40, .apb = 0x2000 }, /* XDMREG_OCDID */ \
+ { .nar = 0x42, .apb = 0x2008 }, /* XDMREG_DCRCLR */ \
+ { .nar = 0x43, .apb = 0x200c }, /* XDMREG_DCRSET */ \
+ { .nar = 0x44, .apb = 0x2010 }, /* XDMREG_DSR */ \
+ { .nar = 0x45, .apb = 0x2014 }, /* XDMREG_DDR */ \
+ { .nar = 0x46, .apb = 0x2018 }, /* XDMREG_DDREXEC */ \
+ { .nar = 0x47, .apb = 0x201c }, /* XDMREG_DIR0EXEC */ \
+ { .nar = 0x48, .apb = 0x2020 }, /* XDMREG_DIR0 */ \
+ { .nar = 0x49, .apb = 0x2024 }, /* XDMREG_DIR1 */ \
+ { .nar = 0x4a, .apb = 0x2028 }, /* XDMREG_DIR2 */ \
+ { .nar = 0x4b, .apb = 0x202c }, /* XDMREG_DIR3 */ \
+ { .nar = 0x4c, .apb = 0x2030 }, /* XDMREG_DIR4 */ \
+ { .nar = 0x4d, .apb = 0x2034 }, /* XDMREG_DIR5 */ \
+ { .nar = 0x4e, .apb = 0x2038 }, /* XDMREG_DIR6 */ \
+ { .nar = 0x4f, .apb = 0x203c }, /* XDMREG_DIR7 */ \
+ \
+ /* Misc Registers */ \
+ { .nar = 0x5a, .apb = 0x3028 }, /* XDMREG_ERISTAT */ \
+ \
+ /* CoreSight Registers */ \
+ { .nar = 0x60, .apb = 0x3f00 }, /* XDMREG_ITCTRL */ \
+ { .nar = 0x68, .apb = 0x3fa0 }, /* XDMREG_CLAIMSET */ \
+ { .nar = 0x69, .apb = 0x3fa4 }, /* XDMREG_CLAIMCLR */ \
+ { .nar = 0x6c, .apb = 0x3fb0 }, /* XDMREG_LOCKACCESS */ \
+ { .nar = 0x6d, .apb = 0x3fb4 }, /* XDMREG_LOCKSTATUS */ \
+ { .nar = 0x6e, .apb = 0x3fb8 }, /* XDMREG_AUTHSTATUS */ \
+ { .nar = 0x72, .apb = 0x3fc8 }, /* XDMREG_DEVID */ \
+ { .nar = 0x73, .apb = 0x3fcc }, /* XDMREG_DEVTYPE */ \
+ { .nar = 0x74, .apb = 0x3fd0 }, /* XDMREG_PERID4 */ \
+ { .nar = 0x75, .apb = 0x3fd4 }, /* XDMREG_PERID5 */ \
+ { .nar = 0x76, .apb = 0x3fd8 }, /* XDMREG_PERID6 */ \
+ { .nar = 0x77, .apb = 0x3fdc }, /* XDMREG_PERID7 */ \
+ { .nar = 0x78, .apb = 0x3fe0 }, /* XDMREG_PERID0 */ \
+ { .nar = 0x79, .apb = 0x3fe4 }, /* XDMREG_PERID1 */ \
+ { .nar = 0x7a, .apb = 0x3fe8 }, /* XDMREG_PERID2 */ \
+ { .nar = 0x7b, .apb = 0x3fec }, /* XDMREG_PERID3 */ \
+ { .nar = 0x7c, .apb = 0x3ff0 }, /* XDMREG_COMPID0 */ \
+ { .nar = 0x7d, .apb = 0x3ff4 }, /* XDMREG_COMPID1 */ \
+ { .nar = 0x7e, .apb = 0x3ff8 }, /* XDMREG_COMPID2 */ \
+ { .nar = 0x7f, .apb = 0x3ffc }, /* XDMREG_COMPID3 */ \
+}
+
+#define XTENSA_DM_APB_MASK (0x3fff)
+
+/* OCD registers, bit definitions */
#define OCDDCR_ENABLEOCD BIT(0)
#define OCDDCR_DEBUGINTERRUPT BIT(1)
#define OCDDCR_INTERRUPTALLCONDS BIT(2)
@@ -150,7 +285,7 @@
#define TRAXCTRL_CTIEN BIT(5) /* Cross-trigger enable */
#define TRAXCTRL_TMEN BIT(7) /* Tracemem Enable. Always set. */
#define TRAXCTRL_CNTU BIT(9) /* Post-stop-trigger countdown units; selects when DelayCount-- happens.
- *0 - every 32-bit word written to tracemem, 1 - every cpu instruction */
+ * 0 - every 32-bit word written to tracemem, 1 - every cpu instruction */
#define TRAXCTRL_TSEN BIT(11) /* Undocumented/deprecated? */
#define TRAXCTRL_SMPER_SHIFT 12 /* Send sync every 2^(9-smper) messages. 7=reserved, 0=no sync msg */
#define TRAXCTRL_SMPER_MASK 0x07 /* Synchronization message period */
@@ -188,7 +323,7 @@
#define PCMATCHCTRL_PCML_SHIFT 0 /* Amount of lower bits to ignore in pc trigger register */
#define PCMATCHCTRL_PCML_MASK 0x1F
#define PCMATCHCTRL_PCMS BIT(31) /* PC Match Sense, 0-match when procs PC is in-range, 1-match when
- *out-of-range */
+ * out-of-range */
#define XTENSA_MAX_PERF_COUNTERS 2
#define XTENSA_MAX_PERF_SELECT 32
@@ -202,20 +337,24 @@ struct xtensa_debug_ops {
/** enable operation */
int (*queue_enable)(struct xtensa_debug_module *dm);
/** register read. */
- int (*queue_reg_read)(struct xtensa_debug_module *dm, unsigned int reg, uint8_t *data);
+ int (*queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *data);
/** register write. */
- int (*queue_reg_write)(struct xtensa_debug_module *dm, unsigned int reg, uint32_t data);
+ int (*queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t data);
};
+/* Xtensa power registers are 8 bits wide on JTAG interfaces but 32 bits wide
+ * when accessed via APB/DAP. In order to use DAP queuing APIs (for optimal
+ * performance), the XDM power register APIs take 32-bit register params.
+ */
struct xtensa_power_ops {
/** register read. */
- int (*queue_reg_read)(struct xtensa_debug_module *dm, unsigned int reg, uint8_t *data,
- uint8_t clear);
+ int (*queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data,
+ uint32_t clear);
/** register write. */
- int (*queue_reg_write)(struct xtensa_debug_module *dm, unsigned int reg, uint8_t data);
+ int (*queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data);
};
-typedef uint8_t xtensa_pwrstat_t;
+typedef uint32_t xtensa_pwrstat_t;
typedef uint32_t xtensa_ocdid_t;
typedef uint32_t xtensa_dsr_t;
typedef uint32_t xtensa_traxstat_t;
@@ -288,10 +427,20 @@ struct xtensa_debug_module {
int xtensa_dm_init(struct xtensa_debug_module *dm, const struct xtensa_debug_module_config *cfg);
int xtensa_dm_queue_enable(struct xtensa_debug_module *dm);
-int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, unsigned int reg, uint8_t *value);
-int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, unsigned int reg, uint32_t value);
-int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm, unsigned int reg, uint8_t *data, uint8_t clear);
-int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm, unsigned int reg, uint8_t data);
+int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value);
+int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value);
+int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm,
+ enum xtensa_dm_pwr_reg reg,
+ uint8_t *data,
+ uint32_t clear);
+int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm,
+ enum xtensa_dm_pwr_reg reg,
+ uint32_t data);
+
+static inline int xtensa_dm_queue_execute(struct xtensa_debug_module *dm)
+{
+ return jtag_execute_queue();
+}
static inline void xtensa_dm_queue_tdi_idle(struct xtensa_debug_module *dm)
{
@@ -338,7 +487,7 @@ static inline bool xtensa_dm_is_online(struct xtensa_debug_module *dm)
int res = xtensa_dm_device_id_read(dm);
if (res != ERROR_OK)
return false;
- return (dm->device_id != 0xffffffff && dm->device_id != 0);
+ return dm->device_id != 0xffffffff && dm->device_id != 0;
}
static inline bool xtensa_dm_tap_was_reset(struct xtensa_debug_module *dm)
-----------------------------------------------------------------------
Summary of changes:
src/target/xtensa/xtensa.c | 163 ++++++++---------
src/target/xtensa/xtensa.h | 8 +-
src/target/xtensa/xtensa_debug_module.c | 155 ++++++++--------
src/target/xtensa/xtensa_debug_module.h | 303 ++++++++++++++++++++++++--------
4 files changed, 390 insertions(+), 239 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2022-09-08 09:32:34
|
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The branch, master has been updated
via ea165d8e897cb5946942f40589efec4f1b5e7c2c (commit)
via 3cd7c40c3c7c7cc82824b41f5e2be8ff118ce41f (commit)
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- Log -----------------------------------------------------------------
commit ea165d8e897cb5946942f40589efec4f1b5e7c2c
Author: Antonio Borneo <ant...@st...>
Date: Sat Aug 27 19:29:55 2022 +0200
jep106: update to revision JEP106BE Jan 2022
Change-Id: I687c653517133c114a66f628cce58178ce6707cd
Signed-off-by: Antonio Borneo <ant...@st...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7148
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/helper/jep106.inc b/src/helper/jep106.inc
index 850a3c5c5..01c3aac07 100644
--- a/src/helper/jep106.inc
+++ b/src/helper/jep106.inc
@@ -8,7 +8,7 @@
* identification code list, please visit the JEDEC website at www.jedec.org .
*/
-/* This file is aligned to revision JEP106BC February 2021. */
+/* This file is aligned to revision JEP106BE January 2022. */
[0][0x01 - 1] = "AMD",
[0][0x02 - 1] = "AMI",
@@ -1559,7 +1559,7 @@
[12][0x23 - 1] = "Tangem AG",
[12][0x24 - 1] = "FuturePath Technology (Shenzhen) Co",
[12][0x25 - 1] = "RC Module",
-[12][0x26 - 1] = "Team Research Inc",
+[12][0x26 - 1] = "Timetec International Inc",
[12][0x27 - 1] = "ICMAX Technologies Co Limited",
[12][0x28 - 1] = "Lynxi Technologies Ltd Co",
[12][0x29 - 1] = "Guangzhou Taisupanke Computer Equipment",
@@ -1577,7 +1577,7 @@
[12][0x35 - 1] = "Shenzhen Xinxinshun Technology Co",
[12][0x36 - 1] = "Galois Inc",
[12][0x37 - 1] = "Ubilite Inc",
-[12][0x38 - 1] = "Shenzhen Quanzing Technology Co Ltd",
+[12][0x38 - 1] = "Shenzhen Quanxing Technology Co Ltd",
[12][0x39 - 1] = "Group RZX Technology LTDA",
[12][0x3a - 1] = "Yottac Technology (XI'AN) Cooperation",
[12][0x3b - 1] = "Shenzhen RuiRen Technology Co Ltd",
@@ -1617,4 +1617,92 @@
[12][0x5d - 1] = "OLOy Technology",
[12][0x5e - 1] = "Wuhan P&S Semiconductor Co Ltd",
[12][0x5f - 1] = "Sitrus Technology",
+[12][0x60 - 1] = "AnHui Conner Storage Co Ltd",
+[12][0x61 - 1] = "Rochester Electronics",
+[12][0x62 - 1] = "Wuxi Petabyte Technologies Co Ltd",
+[12][0x63 - 1] = "Star Memory",
+[12][0x64 - 1] = "Agile Memory Technology Co Ltd",
+[12][0x65 - 1] = "MEJEC",
+[12][0x66 - 1] = "Rockchip Electronics Co Ltd",
+[12][0x67 - 1] = "Dongguan Guanma e-commerce Co Ltd",
+[12][0x68 - 1] = "Rayson Hi-Tech (SZ) Limited",
+[12][0x69 - 1] = "MINRES Technologies GmbH",
+[12][0x6a - 1] = "Himax Technologies Inc",
+[12][0x6b - 1] = "Shenzhen Cwinner Technology Co Ltd",
+[12][0x6c - 1] = "Tecmiyo",
+[12][0x6d - 1] = "Shenzhen Suhuicun Technology Co Ltd",
+[12][0x6e - 1] = "Vickter Electronics Co. Ltd.",
+[12][0x6f - 1] = "lowRISC",
+[12][0x70 - 1] = "EXEGate FZE",
+[12][0x71 - 1] = "Shenzhen 9 Chapter Technologies Co",
+[12][0x72 - 1] = "Addlink",
+[12][0x73 - 1] = "Starsway",
+[12][0x74 - 1] = "Pensando Systems Inc.",
+[12][0x75 - 1] = "AirDisk",
+[12][0x76 - 1] = "Shenzhen Speedmobile Technology Co",
+[12][0x77 - 1] = "PEZY Computing",
+[12][0x78 - 1] = "Extreme Engineering Solutions Inc",
+[12][0x79 - 1] = "Shangxin Technology Co Ltd",
+[12][0x7a - 1] = "Shanghai Zhaoxin Semiconductor Co",
+[12][0x7b - 1] = "Xsight Labs Ltd",
+[12][0x7c - 1] = "Hangzhou Hikstorage Technology Co",
+[12][0x7d - 1] = "Dell Technologies",
+[12][0x7e - 1] = "Guangdong StarFive Technology Co",
+[13][0x01 - 1] = "TECOTON",
+[13][0x02 - 1] = "Abko Co Ltd",
+[13][0x03 - 1] = "Shenzhen Feisrike Technology Co Ltd",
+[13][0x04 - 1] = "Shenzhen Sunhome Electronics Co Ltd",
+[13][0x05 - 1] = "Global Mixed-mode Technology Inc",
+[13][0x06 - 1] = "Shenzhen Weien Electronics Co. Ltd.",
+[13][0x07 - 1] = "Shenzhen Cooyes Technology Co Ltd",
+[13][0x08 - 1] = "Keymos Electronics Co., Limited",
+[13][0x09 - 1] = "E-Rockic Technology Company Limited",
+[13][0x0a - 1] = "Aerospace Science Memory Shenzhen",
+[13][0x0b - 1] = "Shenzhen Quanji Technology Co Ltd",
+[13][0x0c - 1] = "Dukosi",
+[13][0x0d - 1] = "Maxell Corporation of America",
+[13][0x0e - 1] = "Shenshen Xinxintao Electronics Co Ltd",
+[13][0x0f - 1] = "Zhuhai Sanxia Semiconductor Co Ltd",
+[13][0x10 - 1] = "Groq Inc",
+[13][0x11 - 1] = "AstraTek",
+[13][0x12 - 1] = "Shenzhen Xinyuze Technology Co Ltd",
+[13][0x13 - 1] = "All Bit Semiconductor",
+[13][0x14 - 1] = "ACFlow",
+[13][0x15 - 1] = "Shenzhen Sipeed Technology Co Ltd",
+[13][0x16 - 1] = "Linzhi Hong Kong Co Limited",
+[13][0x17 - 1] = "Supreme Wise Limited",
+[13][0x18 - 1] = "Blue Cheetah Analog Design Inc",
+[13][0x19 - 1] = "Hefei Laiku Technology Co Ltd",
+[13][0x1a - 1] = "Zord",
+[13][0x1b - 1] = "SBO Hearing A/S",
+[13][0x1c - 1] = "Regent Sharp International Limited",
+[13][0x1d - 1] = "Permanent Potential Limited",
+[13][0x1e - 1] = "Creative World International Limited",
+[13][0x1f - 1] = "Base Creation International Limited",
+[13][0x20 - 1] = "Shenzhen Zhixin Chuanglian Technology",
+[13][0x21 - 1] = "Protected Logic Corporation",
+[13][0x22 - 1] = "Sabrent",
+[13][0x23 - 1] = "Union Memory",
+[13][0x24 - 1] = "NEUCHIPS Corporation",
+[13][0x25 - 1] = "Ingenic Semiconductor Co Ltd",
+[13][0x26 - 1] = "SiPearl",
+[13][0x27 - 1] = "Shenzhen Actseno Information Technology",
+[13][0x28 - 1] = "RIVAI Technologies (Shenzhen) Co Ltd",
+[13][0x29 - 1] = "Shenzhen Sunny Technology Co Ltd",
+[13][0x2a - 1] = "Cott Electronics Ltd",
+[13][0x2b - 1] = "Shanghai Synsense Technologies Co Ltd",
+[13][0x2c - 1] = "Shenzhen Jintang Fuming Optoelectronics",
+[13][0x2d - 1] = "CloudBEAR LLC",
+[13][0x2e - 1] = "Emzior, LLC",
+[13][0x2f - 1] = "Ehiway Microelectronic Science Tech Co",
+[13][0x30 - 1] = "UNIM Innovation Technology (Wu XI)",
+[13][0x31 - 1] = "GDRAMARS",
+[13][0x32 - 1] = "Meminsights Technology",
+[13][0x33 - 1] = "Zhuzhou Hongda Electronics Corp Ltd",
+[13][0x34 - 1] = "Luminous Computing Inc",
+[13][0x35 - 1] = "PROXMEM",
+[13][0x36 - 1] = "Draper Labs",
+[13][0x37 - 1] = "ORICO Technologies Co. Ltd.",
+[13][0x38 - 1] = "Space Exploration Technologies Corp",
+[13][0x39 - 1] = "AONDEVICES Inc",
/* EOF */
commit 3cd7c40c3c7c7cc82824b41f5e2be8ff118ce41f
Author: Antonio Borneo <ant...@st...>
Date: Sat Aug 27 18:58:42 2022 +0200
jep106: add SPDX tag and JEDEC copyright
As a follow-up of talks between JEDEC and STMicroelectronics,
JEDEC agrees to let OpenOCD project including the manufacturer's
identification code list extracted from JEDEC JEP106 document and
to let OpenOCD being updated regularly using the future JEDEC
JEP106 document versions. JEDEC requires OpenOCD to report the
origin of the JEDEC JEP106 manufacturer's identification code list
together with the JEDEC copyright.
As agreed with JEDEC, add in the file jep106.inc:
- the SPDX tag with the GPL license of the OpenOCD project;
- the JEDEC copyright;
- the text provided by JEDEC reporting the origin of the JEDEC
JEP106 manufacturer's identification code list.
While there:
- add a line reporting the version of the JEP106 document that was
used for the current code list extraction;
- remove the obsolete comment, as the script for extraction is not
working anymore; keep the script as example.
Change-Id: Iaa76716db14e15ffca04fcf7d8c27bb85a27ba10
Signed-off-by: Antonio Borneo <ant...@st...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7147
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/helper/jep106.inc b/src/helper/jep106.inc
index 41afdb845..850a3c5c5 100644
--- a/src/helper/jep106.inc
+++ b/src/helper/jep106.inc
@@ -1,9 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/*
- * Should be autogenerated with update_jep106.pl but latest
- * file from JEDEC is only available in PDF form. The PDF
- * also breaks the pdftotext flow due to embedded watermarks.
- * Created with a mix of scripts and manual editing.
+ * The manufacturer's standard identification code list appears in JEP106.
+ * Copyright (c) 2022 JEDEC. All rights reserved.
+ *
+ * JEP106 is regularly updated. For the current manufacturer's standard
+ * identification code list, please visit the JEDEC website at www.jedec.org .
*/
+
+/* This file is aligned to revision JEP106BC February 2021. */
+
[0][0x01 - 1] = "AMD",
[0][0x02 - 1] = "AMI",
[0][0x03 - 1] = "Fairchild",
-----------------------------------------------------------------------
Summary of changes:
src/helper/jep106.inc | 106 +++++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 100 insertions(+), 6 deletions(-)
hooks/post-receive
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From: OpenOCD-Gerrit <ope...@us...> - 2022-09-08 09:31:52
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
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- Log -----------------------------------------------------------------
commit c47f05cb06c5a9036c55f59d83d7cb807c7494e8
Author: Antonio Borneo <bor...@gm...>
Date: Mon Aug 22 19:47:05 2022 +0200
jtag/vdebug: remove BSD-2-Clause boilerplate
The full text of the license is already available in the file
LICENSES/preferred/BSD-2-Clause
and there is no need to replicate it in the source code.
Remove the BSD-2-Clause boilerplate but, preserved the copyright
notice because it provides the info on the copyright holder.
Change-Id: I162aa4ad06b551f1a71a28d049cb797ee8ab5a01
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7146
Tested-by: jenkins
Reviewed-by: Jacek Wuwer <jac...@gm...>
diff --git a/src/jtag/drivers/vdebug.c b/src/jtag/drivers/vdebug.c
index 035c1bee2..b641c03ae 100644
--- a/src/jtag/drivers/vdebug.c
+++ b/src/jtag/drivers/vdebug.c
@@ -1,27 +1,6 @@
/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
-/*----------------------------------------------------------------------------
- * Copyright 2020-2022 Cadence Design Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *----------------------------------------------------------------------------
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *----------------------------------------------------------------------------
-*/
+
+/* Copyright 2020-2022 Cadence Design Systems, Inc. */
/*!
* @file
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/vdebug.c | 25 ++-----------------------
1 file changed, 2 insertions(+), 23 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-09-08 09:31:19
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from 7fcbac1bdf5848fb5f80545126ca61473dc59721 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 68f12b87ef8623d6b9536f5fda45465377907d8e
Author: Marc Schink <de...@za...>
Date: Tue Aug 16 10:39:14 2022 +0200
libjaylink: Update to 0.3.1 release
Change-Id: If4c13767de033a221e80fc26ee38f67c6c3d746c
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7119
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/libjaylink b/src/jtag/drivers/libjaylink
index 9aa7a5957..0d23921a0 160000
--- a/src/jtag/drivers/libjaylink
+++ b/src/jtag/drivers/libjaylink
@@ -1 +1 @@
-Subproject commit 9aa7a5957c07bb6e862fc1a6d3153d109c7407e4
+Subproject commit 0d23921a05d5d427332a142d154c213d0c306eb1
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/libjaylink | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-09-03 21:32:19
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 7fcbac1bdf5848fb5f80545126ca61473dc59721 (commit)
from bea4d6590356f4a9ef0bcb6b270943e565852f0e (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 7fcbac1bdf5848fb5f80545126ca61473dc59721
Author: Erhan Kurubas <erh...@es...>
Date: Thu Aug 25 17:06:40 2022 +0300
server: add function to get openocd shutdown status
In the app-trace module we are polling the target in the while loops
outside of the server.c
In that loops, we need to catch ctrl+c signal by checking shutdown_openocd
status
Signed-off-by: Erhan Kurubas <erh...@es...>
Change-Id: Id87c709a01470bf6d3642078b160a68ca85f4406
Reviewed-on: https://review.openocd.org/c/openocd/+/7142
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/server/server.c b/src/server/server.c
index 6542200d2..43540d6d3 100644
--- a/src/server/server.c
+++ b/src/server/server.c
@@ -747,6 +747,11 @@ int connection_read(struct connection *connection, void *data, int len)
return read(connection->fd, data, len);
}
+bool openocd_is_shutdown_pending(void)
+{
+ return shutdown_openocd != CONTINUE_MAIN_LOOP;
+}
+
/* tell the server we want to shut down */
COMMAND_HANDLER(handle_shutdown_command)
{
diff --git a/src/server/server.h b/src/server/server.h
index f09988a8a..c9d4698af 100644
--- a/src/server/server.h
+++ b/src/server/server.h
@@ -104,6 +104,8 @@ int server_register_commands(struct command_context *context);
int connection_write(struct connection *connection, const void *data, int len);
int connection_read(struct connection *connection, void *data, int len);
+bool openocd_is_shutdown_pending(void);
+
/**
* Defines an extended command handler function declaration to enable
* access to (and manipulation of) the server port number.
-----------------------------------------------------------------------
Summary of changes:
src/server/server.c | 5 +++++
src/server/server.h | 2 ++
2 files changed, 7 insertions(+)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-09-03 21:28:12
|
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commit bea4d6590356f4a9ef0bcb6b270943e565852f0e
Author: Erhan Kurubas <erh...@es...>
Date: Thu Jun 30 13:14:27 2022 +0300
target/espressif: add semihosting support
ARM semihosting + some custom syscalls implemented for
Espressif chips (ESP32, ESP32-S2, ESP32-S3)
Signed-off-by: Erhan Kurubas <erh...@es...>
Change-Id: Ic8174cf1cd344fa16d619b7b8405c9650e869443
Reviewed-on: https://review.openocd.org/c/openocd/+/7074
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/espressif/Makefile.am b/src/target/espressif/Makefile.am
index 1b4f8062e..8367a3881 100644
--- a/src/target/espressif/Makefile.am
+++ b/src/target/espressif/Makefile.am
@@ -6,6 +6,10 @@ noinst_LTLIBRARIES += %D%/libespressif.la
%D%/esp_xtensa.h \
%D%/esp_xtensa_smp.c \
%D%/esp_xtensa_smp.h \
+ %D%/esp_xtensa_semihosting.c \
+ %D%/esp_xtensa_semihosting.h \
%D%/esp32.c \
%D%/esp32s2.c \
- %D%/esp32s3.c
+ %D%/esp32s3.c \
+ %D%/esp_semihosting.c \
+ %D%/esp_semihosting.h
diff --git a/src/target/espressif/esp32.c b/src/target/espressif/esp32.c
index a083627fb..8ad8bad83 100644
--- a/src/target/espressif/esp32.c
+++ b/src/target/espressif/esp32.c
@@ -13,6 +13,7 @@
#include <target/target.h>
#include <target/target_type.h>
#include <target/smp.h>
+#include <target/semihosting_common.h>
#include "assert.h"
#include "esp_xtensa_smp.h"
@@ -329,6 +330,10 @@ static const struct esp_xtensa_smp_chip_ops esp32_chip_ops = {
.on_halt = esp32_on_halt
};
+static const struct esp_semihost_ops esp32_semihost_ops = {
+ .prepare = esp32_disable_wdts
+};
+
static int esp32_target_create(struct target *target, Jim_Interp *interp)
{
struct xtensa_debug_module_config esp32_dm_cfg = {
@@ -346,7 +351,7 @@ static int esp32_target_create(struct target *target, Jim_Interp *interp)
}
int ret = esp_xtensa_smp_init_arch_info(target, &esp32->esp_xtensa_smp,
- &esp32_dm_cfg, &esp32_chip_ops);
+ &esp32_dm_cfg, &esp32_chip_ops, &esp32_semihost_ops);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to init arch info!");
free(esp32);
@@ -445,6 +450,13 @@ static const struct command_registration esp32_command_handlers[] = {
.usage = "",
.chain = esp32_any_command_handlers,
},
+ {
+ .name = "arm",
+ .mode = COMMAND_ANY,
+ .help = "ARM Command Group",
+ .usage = "",
+ .chain = semihosting_common_handlers
+ },
COMMAND_REGISTRATION_DONE
};
diff --git a/src/target/espressif/esp32s2.c b/src/target/espressif/esp32s2.c
index 0bcd20f2d..4aef3791b 100644
--- a/src/target/espressif/esp32s2.c
+++ b/src/target/espressif/esp32s2.c
@@ -13,7 +13,9 @@
#include "assert.h"
#include <target/target.h>
#include <target/target_type.h>
+#include <target/semihosting_common.h>
#include "esp_xtensa.h"
+#include "esp_xtensa_semihosting.h"
/* Overall memory map
* TODO: read memory configuration from target registers */
@@ -406,6 +408,19 @@ static int esp32s2_poll(struct target *target)
if (old_state == TARGET_DEBUG_RUNNING) {
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
} else {
+ if (esp_xtensa_semihosting(target, &ret) == SEMIHOSTING_HANDLED) {
+ struct esp_xtensa_common *esp_xtensa = target_to_esp_xtensa(target);
+ if (ret == ERROR_OK && esp_xtensa->semihost.need_resume) {
+ esp_xtensa->semihost.need_resume = false;
+ /* Resume xtensa_resume will handle BREAK instruction. */
+ ret = target_resume(target, 1, 0, 1, 0);
+ if (ret != ERROR_OK) {
+ LOG_ERROR("Failed to resume target");
+ return ret;
+ }
+ }
+ return ret;
+ }
esp32s2_on_halt(target);
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
}
@@ -423,7 +438,11 @@ static int esp32s2_virt2phys(struct target *target,
static int esp32s2_target_init(struct command_context *cmd_ctx, struct target *target)
{
- return esp_xtensa_target_init(cmd_ctx, target);
+ int ret = esp_xtensa_target_init(cmd_ctx, target);
+ if (ret != ERROR_OK)
+ return ret;
+
+ return esp_xtensa_semihosting_init(target);
}
static const struct xtensa_debug_ops esp32s2_dbg_ops = {
@@ -437,6 +456,10 @@ static const struct xtensa_power_ops esp32s2_pwr_ops = {
.queue_reg_write = xtensa_dm_queue_pwr_reg_write
};
+static const struct esp_semihost_ops esp32s2_semihost_ops = {
+ .prepare = esp32s2_disable_wdts
+};
+
static int esp32s2_target_create(struct target *target, Jim_Interp *interp)
{
struct xtensa_debug_module_config esp32s2_dm_cfg = {
@@ -454,7 +477,7 @@ static int esp32s2_target_create(struct target *target, Jim_Interp *interp)
return ERROR_FAIL;
}
- int ret = esp_xtensa_init_arch_info(target, &esp32->esp_xtensa, &esp32s2_dm_cfg);
+ int ret = esp_xtensa_init_arch_info(target, &esp32->esp_xtensa, &esp32s2_dm_cfg, &esp32s2_semihost_ops);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to init arch info!");
free(esp32);
@@ -471,6 +494,13 @@ static const struct command_registration esp32s2_command_handlers[] = {
{
.chain = xtensa_command_handlers,
},
+ {
+ .name = "arm",
+ .mode = COMMAND_ANY,
+ .help = "ARM Command Group",
+ .usage = "",
+ .chain = semihosting_common_handlers
+ },
COMMAND_REGISTRATION_DONE
};
diff --git a/src/target/espressif/esp32s3.c b/src/target/espressif/esp32s3.c
index b87005901..0da8552a3 100644
--- a/src/target/espressif/esp32s3.c
+++ b/src/target/espressif/esp32s3.c
@@ -13,6 +13,7 @@
#include <target/target.h>
#include <target/target_type.h>
#include <target/smp.h>
+#include <target/semihosting_common.h>
#include "assert.h"
#include "esp_xtensa_smp.h"
@@ -302,7 +303,7 @@ static int esp32s3_virt2phys(struct target *target,
static int esp32s3_target_init(struct command_context *cmd_ctx, struct target *target)
{
- return esp_xtensa_target_init(cmd_ctx, target);
+ return esp_xtensa_smp_target_init(cmd_ctx, target);
}
static const struct xtensa_debug_ops esp32s3_dbg_ops = {
@@ -321,6 +322,10 @@ static const struct esp_xtensa_smp_chip_ops esp32s3_chip_ops = {
.on_halt = esp32s3_on_halt
};
+static const struct esp_semihost_ops esp32s3_semihost_ops = {
+ .prepare = esp32s3_disable_wdts
+};
+
static int esp32s3_target_create(struct target *target, Jim_Interp *interp)
{
struct xtensa_debug_module_config esp32s3_dm_cfg = {
@@ -340,7 +345,8 @@ static int esp32s3_target_create(struct target *target, Jim_Interp *interp)
int ret = esp_xtensa_smp_init_arch_info(target,
&esp32s3->esp_xtensa_smp,
&esp32s3_dm_cfg,
- &esp32s3_chip_ops);
+ &esp32s3_chip_ops,
+ &esp32s3_semihost_ops);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to init arch info!");
free(esp32s3);
@@ -363,6 +369,13 @@ static const struct command_registration esp32s3_command_handlers[] = {
.usage = "",
.chain = smp_command_handlers,
},
+ {
+ .name = "arm",
+ .mode = COMMAND_ANY,
+ .help = "ARM Command Group",
+ .usage = "",
+ .chain = semihosting_common_handlers
+ },
COMMAND_REGISTRATION_DONE
};
diff --git a/src/target/espressif/esp_semihosting.c b/src/target/espressif/esp_semihosting.c
new file mode 100644
index 000000000..b1edef31d
--- /dev/null
+++ b/src/target/espressif/esp_semihosting.c
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ * Semihosting API for Espressif chips *
+ * Copyright (C) 2022 Espressif Systems Ltd. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <helper/log.h>
+#include <target/target.h>
+#include <target/semihosting_common.h>
+#include "esp_semihosting.h"
+#include "esp_xtensa.h"
+
+struct esp_semihost_data *target_to_esp_semihost_data(struct target *target)
+{
+ const char *arch = target_get_gdb_arch(target);
+ if (arch) {
+ if (strncmp(arch, "xtensa", 6) == 0)
+ return &target_to_esp_xtensa(target)->semihost;
+ /* TODO: add riscv */
+ }
+ LOG_ERROR("Unknown target arch!");
+ return NULL;
+}
+
+int esp_semihosting_sys_seek(struct target *target, uint64_t fd, uint32_t pos, size_t whence)
+{
+ struct semihosting *semihosting = target->semihosting;
+
+ semihosting->result = lseek(fd, pos, whence);
+ semihosting->sys_errno = errno;
+ LOG_TARGET_DEBUG(target, "lseek(%" PRIx64 ", %" PRIu32 " %" PRId64 ")=%d", fd, pos, semihosting->result, errno);
+ return ERROR_OK;
+}
+
+int esp_semihosting_common(struct target *target)
+{
+ struct semihosting *semihosting = target->semihosting;
+ if (!semihosting)
+ /* Silently ignore if the semihosting field was not set. */
+ return ERROR_OK;
+
+ int retval = ERROR_NOT_IMPLEMENTED;
+
+ /* Enough space to hold 4 long words. */
+ uint8_t fields[4 * 8];
+
+ /*
+ * By default return an error.
+ * The actual result must be set by each function
+ */
+ semihosting->result = -1;
+ semihosting->sys_errno = EIO;
+
+ LOG_TARGET_DEBUG(target, "op=0x%x, param=0x%" PRIx64, semihosting->op, semihosting->param);
+
+ switch (semihosting->op) {
+ case ESP_SEMIHOSTING_SYS_DRV_INFO:
+ /* Return success to make esp-idf application happy */
+ retval = ERROR_OK;
+ semihosting->result = 0;
+ semihosting->sys_errno = 0;
+ break;
+
+ case ESP_SEMIHOSTING_SYS_SEEK:
+ retval = semihosting_read_fields(target, 3, fields);
+ if (retval == ERROR_OK) {
+ uint64_t fd = semihosting_get_field(target, 0, fields);
+ uint32_t pos = semihosting_get_field(target, 1, fields);
+ size_t whence = semihosting_get_field(target, 2, fields);
+ retval = esp_semihosting_sys_seek(target, fd, pos, whence);
+ }
+ break;
+
+ case ESP_SEMIHOSTING_SYS_APPTRACE_INIT:
+ case ESP_SEMIHOSTING_SYS_DEBUG_STUBS_INIT:
+ case ESP_SEMIHOSTING_SYS_BREAKPOINT_SET:
+ case ESP_SEMIHOSTING_SYS_WATCHPOINT_SET:
+ /* For the time being only riscv chips support these commands
+ * TODO: invoke riscv custom command handler */
+ break;
+ }
+
+ return retval;
+}
+
+int esp_semihosting_basedir_command(struct command_invocation *cmd)
+{
+ struct target *target = get_current_target(CMD_CTX);
+
+ if (!target) {
+ LOG_ERROR("No target selected");
+ return ERROR_FAIL;
+ }
+
+ struct semihosting *semihosting = target->semihosting;
+ if (!semihosting) {
+ command_print(CMD, "semihosting not supported for current target");
+ return ERROR_FAIL;
+ }
+
+ if (!semihosting->is_active) {
+ if (semihosting->setup(target, true) != ERROR_OK) {
+ LOG_ERROR("Failed to Configure semihosting");
+ return ERROR_FAIL;
+ }
+ semihosting->is_active = true;
+ }
+
+ if (CMD_ARGC > 0) {
+ free(semihosting->basedir);
+ semihosting->basedir = strdup(CMD_ARGV[0]);
+ if (!semihosting->basedir) {
+ command_print(CMD, "semihosting failed to allocate memory for basedir!");
+ return ERROR_FAIL;
+ }
+ }
+
+ command_print(CMD, "DEPRECATED! semihosting base dir: %s",
+ semihosting->basedir ? semihosting->basedir : "");
+
+ return ERROR_OK;
+}
diff --git a/src/target/espressif/esp_semihosting.h b/src/target/espressif/esp_semihosting.h
new file mode 100644
index 000000000..bd2c0799e
--- /dev/null
+++ b/src/target/espressif/esp_semihosting.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ * Semihosting API for Espressif chips *
+ * Copyright (C) 2022 Espressif Systems Ltd. *
+ ***************************************************************************/
+
+#ifndef OPENOCD_TARGET_ESP_SEMIHOSTING_H
+#define OPENOCD_TARGET_ESP_SEMIHOSTING_H
+
+/* Legacy syscalls */
+#define ESP_SYS_DRV_INFO_LEGACY 0xE0
+
+/* syscalls compatible to ARM standard */
+#define ESP_SEMIHOSTING_SYS_DRV_INFO 0x100
+#define ESP_SEMIHOSTING_SYS_APPTRACE_INIT 0x101
+#define ESP_SEMIHOSTING_SYS_DEBUG_STUBS_INIT 0x102
+#define ESP_SEMIHOSTING_SYS_BREAKPOINT_SET 0x103
+#define ESP_SEMIHOSTING_SYS_WATCHPOINT_SET 0x104
+#define ESP_SEMIHOSTING_SYS_SEEK 0x105 /* custom lseek with whence */
+/* not implemented yet */
+#define ESP_SEMIHOSTING_SYS_MKDIR 0x106
+#define ESP_SEMIHOSTING_SYS_OPENDIR 0x107
+#define ESP_SEMIHOSTING_SYS_READDIR 0x108
+#define ESP_SEMIHOSTING_SYS_READDIR_R 0x109
+#define ESP_SEMIHOSTING_SYS_SEEKDIR 0x10A
+#define ESP_SEMIHOSTING_SYS_TELLDIR 0x10B
+#define ESP_SEMIHOSTING_SYS_CLOSEDIR 0x10C
+#define ESP_SEMIHOSTING_SYS_RMDIR 0x10D
+#define ESP_SEMIHOSTING_SYS_ACCESS 0x10E
+#define ESP_SEMIHOSTING_SYS_TRUNCATE 0x10F
+#define ESP_SEMIHOSTING_SYS_UTIME 0x110
+#define ESP_SEMIHOSTING_SYS_FSTAT 0x111
+#define ESP_SEMIHOSTING_SYS_STAT 0x112
+#define ESP_SEMIHOSTING_SYS_FSYNC 0x113
+#define ESP_SEMIHOSTING_SYS_LINK 0x114
+#define ESP_SEMIHOSTING_SYS_UNLINK 0x115
+
+/**
+ * Semihost calls handling operations.
+ */
+struct esp_semihost_ops {
+ /** Callback called before handling semihost call */
+ int (*prepare)(struct target *target);
+};
+
+struct esp_semihost_data {
+ bool need_resume;
+ struct esp_semihost_ops *ops;
+};
+
+int esp_semihosting_common(struct target *target);
+int esp_semihosting_basedir_command(struct command_invocation *cmd);
+
+#endif /* OPENOCD_TARGET_ESP_SEMIHOSTING_H */
diff --git a/src/target/espressif/esp_xtensa.c b/src/target/espressif/esp_xtensa.c
index fcd42eac3..6a1b72ec4 100644
--- a/src/target/espressif/esp_xtensa.c
+++ b/src/target/espressif/esp_xtensa.c
@@ -12,14 +12,20 @@
#include <stdbool.h>
#include <stdint.h>
#include <target/smp.h>
-#include "esp_xtensa.h"
#include <target/register.h>
+#include "esp_xtensa.h"
+#include "esp_semihosting.h"
int esp_xtensa_init_arch_info(struct target *target,
struct esp_xtensa_common *esp_xtensa,
- struct xtensa_debug_module_config *dm_cfg)
+ struct xtensa_debug_module_config *dm_cfg,
+ const struct esp_semihost_ops *semihost_ops)
{
- return xtensa_init_arch_info(target, &esp_xtensa->xtensa, dm_cfg);
+ int ret = xtensa_init_arch_info(target, &esp_xtensa->xtensa, dm_cfg);
+ if (ret != ERROR_OK)
+ return ret;
+ esp_xtensa->semihost.ops = (struct esp_semihost_ops *)semihost_ops;
+ return ERROR_OK;
}
int esp_xtensa_target_init(struct command_context *cmd_ctx, struct target *target)
diff --git a/src/target/espressif/esp_xtensa.h b/src/target/espressif/esp_xtensa.h
index 61e87c086..1ad6c377f 100644
--- a/src/target/espressif/esp_xtensa.h
+++ b/src/target/espressif/esp_xtensa.h
@@ -8,12 +8,14 @@
#ifndef OPENOCD_TARGET_ESP_XTENSA_H
#define OPENOCD_TARGET_ESP_XTENSA_H
-#include <helper/command.h>
#include <target/target.h>
#include <target/xtensa/xtensa.h>
+#include "esp_xtensa.h"
+#include "esp_semihosting.h"
struct esp_xtensa_common {
struct xtensa xtensa; /* must be the first element */
+ struct esp_semihost_data semihost;
};
static inline struct esp_xtensa_common *target_to_esp_xtensa(struct target *target)
@@ -23,7 +25,8 @@ static inline struct esp_xtensa_common *target_to_esp_xtensa(struct target *targ
int esp_xtensa_init_arch_info(struct target *target,
struct esp_xtensa_common *esp_xtensa,
- struct xtensa_debug_module_config *dm_cfg);
+ struct xtensa_debug_module_config *dm_cfg,
+ const struct esp_semihost_ops *semihost_ops);
int esp_xtensa_target_init(struct command_context *cmd_ctx, struct target *target);
void esp_xtensa_target_deinit(struct target *target);
int esp_xtensa_arch_state(struct target *target);
diff --git a/src/target/espressif/esp_xtensa_semihosting.c b/src/target/espressif/esp_xtensa_semihosting.c
new file mode 100644
index 000000000..9ea8e4df5
--- /dev/null
+++ b/src/target/espressif/esp_xtensa_semihosting.c
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ * Copyright (c) 2020 Espressif Systems (Shanghai) Co. Ltd. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <target/semihosting_common.h>
+#include <target/xtensa/xtensa_regs.h>
+#include <target/xtensa/xtensa.h>
+#include "esp_xtensa.h"
+#include "esp_xtensa_semihosting.h"
+
+#define ESP_XTENSA_SYSCALL 0x41E0 /* XT_INS_BREAK(1, 14) */
+#define ESP_XTENSA_SYSCALL_SZ 3
+
+#define XTENSA_SYSCALL_OP_REG XT_REG_IDX_A2
+#define XTENSA_SYSCALL_RETVAL_REG XT_REG_IDX_A2
+#define XTENSA_SYSCALL_ERRNO_REG XT_REG_IDX_A3
+
+static int esp_xtensa_semihosting_setup(struct target *target, int enable)
+{
+ LOG_TARGET_DEBUG(target, "semihosting enable=%d", enable);
+
+ return ERROR_OK;
+}
+
+static int esp_xtensa_semihosting_post_result(struct target *target)
+{
+ /* Even with the v2 and later, errno will not retrieved from A3 reg, it is safe to set */
+ xtensa_reg_set(target, XTENSA_SYSCALL_RETVAL_REG, target->semihosting->result);
+ xtensa_reg_set(target, XTENSA_SYSCALL_ERRNO_REG, target->semihosting->sys_errno);
+ return ERROR_OK;
+}
+
+/**
+ * Checks and processes an ESP Xtensa semihosting request. This is meant
+ * to be called when the target is stopped due to a debug mode entry.
+ * If the value 0 is returned then there was nothing to process. A non-zero
+ * return value signifies that a request was processed and the target resumed,
+ * or an error was encountered, in which case the caller must return immediately.
+ *
+ * @param target Pointer to the ESP Xtensa target to process.
+ * @param retval Pointer to a location where the return code will be stored
+ * @return SEMIHOSTING_HANDLED if a request was processed or SEMIHOSTING_NONE with the proper retval
+ */
+int esp_xtensa_semihosting(struct target *target, int *retval)
+{
+ struct esp_xtensa_common *esp_xtensa = target_to_esp_xtensa(target);
+
+ xtensa_reg_val_t dbg_cause = xtensa_reg_get(target, XT_REG_IDX_DEBUGCAUSE);
+ if ((dbg_cause & (DEBUGCAUSE_BI | DEBUGCAUSE_BN)) == 0)
+ return SEMIHOSTING_NONE;
+
+ uint8_t brk_insn_buf[sizeof(uint32_t)] = { 0 };
+ xtensa_reg_val_t pc = xtensa_reg_get(target, XT_REG_IDX_PC);
+ *retval = target_read_memory(target, pc, ESP_XTENSA_SYSCALL_SZ, 1, brk_insn_buf);
+ if (*retval != ERROR_OK) {
+ LOG_TARGET_ERROR(target, "Failed to read break instruction!");
+ return SEMIHOSTING_NONE;
+ }
+
+ uint32_t syscall_ins = buf_get_u32(brk_insn_buf, 0, 32);
+ if (syscall_ins != ESP_XTENSA_SYSCALL) {
+ *retval = ERROR_OK;
+ return SEMIHOSTING_NONE;
+ }
+
+ if (esp_xtensa->semihost.ops && esp_xtensa->semihost.ops->prepare)
+ esp_xtensa->semihost.ops->prepare(target);
+
+ xtensa_reg_val_t a2 = xtensa_reg_get(target, XT_REG_IDX_A2);
+ xtensa_reg_val_t a3 = xtensa_reg_get(target, XT_REG_IDX_A3);
+ LOG_TARGET_DEBUG(target, "Semihosting call 0x%" PRIx32 " 0x%" PRIx32 " Base dir '%s'",
+ a2,
+ a3,
+ target->semihosting->basedir ? target->semihosting->basedir : "");
+
+ target->semihosting->op = a2;
+ target->semihosting->param = a3;
+
+ *retval = semihosting_common(target);
+
+ /* Most operations are resumable, except the two exit calls. */
+ if (*retval != ERROR_OK) {
+ LOG_TARGET_ERROR(target, "Semihosting operation (op: 0x%x) error! Code: %d",
+ target->semihosting->op,
+ *retval);
+ }
+
+ /* Resume if target it is resumable and we are not waiting on a fileio operation to complete. */
+ if (target->semihosting->is_resumable && !target->semihosting->hit_fileio)
+ target_to_esp_xtensa(target)->semihost.need_resume = true;
+
+ return SEMIHOSTING_HANDLED;
+}
+
+static int xtensa_semihosting_init(struct target *target)
+{
+ return semihosting_common_init(target, esp_xtensa_semihosting_setup, esp_xtensa_semihosting_post_result);
+}
+
+int esp_xtensa_semihosting_init(struct target *target)
+{
+ int retval = xtensa_semihosting_init(target);
+ if (retval != ERROR_OK)
+ return retval;
+ target->semihosting->word_size_bytes = 4; /* 32 bits */
+ target->semihosting->user_command_extension = esp_semihosting_common;
+ return ERROR_OK;
+}
diff --git a/src/target/espressif/esp_xtensa_semihosting.h b/src/target/espressif/esp_xtensa_semihosting.h
new file mode 100644
index 000000000..1da311579
--- /dev/null
+++ b/src/target/espressif/esp_xtensa_semihosting.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ * Copyright (c) 2020 Espressif Systems (Shanghai) Co. Ltd. *
+ ***************************************************************************/
+
+#ifndef OPENOCD_TARGET_ESP_XTENSA_SEMIHOSTING_H
+#define OPENOCD_TARGET_ESP_XTENSA_SEMIHOSTING_H
+
+#include <target/target.h>
+
+int esp_xtensa_semihosting_init(struct target *target);
+int esp_xtensa_semihosting(struct target *target, int *retval);
+
+#endif /* OPENOCD_TARGET_ESP_XTENSA_SEMIHOSTING_H */
diff --git a/src/target/espressif/esp_xtensa_smp.c b/src/target/espressif/esp_xtensa_smp.c
index b109f3c5e..235a86eb9 100644
--- a/src/target/espressif/esp_xtensa_smp.c
+++ b/src/target/espressif/esp_xtensa_smp.c
@@ -13,7 +13,9 @@
#include <target/target.h>
#include <target/target_type.h>
#include <target/smp.h>
+#include <target/semihosting_common.h>
#include "esp_xtensa_smp.h"
+#include "esp_xtensa_semihosting.h"
/*
Multiprocessor stuff common:
@@ -128,6 +130,7 @@ int esp_xtensa_smp_poll(struct target *target)
{
enum target_state old_state = target->state;
struct esp_xtensa_smp_common *esp_xtensa_smp = target_to_esp_xtensa_smp(target);
+ struct esp_xtensa_common *esp_xtensa = target_to_esp_xtensa(target);
struct target_list *head;
struct target *curr;
bool other_core_resume_req = false;
@@ -180,6 +183,19 @@ int esp_xtensa_smp_poll(struct target *target)
if (old_state == TARGET_DEBUG_RUNNING) {
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
} else {
+ if (esp_xtensa_semihosting(target, &ret) == SEMIHOSTING_HANDLED) {
+ if (ret == ERROR_OK && esp_xtensa->semihost.need_resume &&
+ !esp_xtensa_smp->other_core_does_resume) {
+ esp_xtensa->semihost.need_resume = false;
+ /* Resume xtensa_resume will handle BREAK instruction. */
+ ret = target_resume(target, 1, 0, 1, 0);
+ if (ret != ERROR_OK) {
+ LOG_ERROR("Failed to resume target");
+ return ret;
+ }
+ }
+ return ret;
+ }
/* check whether any core polled by esp_xtensa_smp_update_halt_gdb() requested resume */
if (target->smp && other_core_resume_req) {
/* Resume xtensa_resume will handle BREAK instruction. */
@@ -253,6 +269,11 @@ static int esp_xtensa_smp_update_halt_gdb(struct target *target, bool *need_resu
if (ret != ERROR_OK)
return ret;
esp_xtensa_smp->other_core_does_resume = false;
+ struct esp_xtensa_common *curr_esp_xtensa = target_to_esp_xtensa(curr);
+ if (curr_esp_xtensa->semihost.need_resume) {
+ curr_esp_xtensa->semihost.need_resume = false;
+ *need_resume = true;
+ }
}
/* after all targets were updated, poll the gdb serving target */
@@ -451,9 +472,10 @@ int esp_xtensa_smp_watchpoint_remove(struct target *target, struct watchpoint *w
int esp_xtensa_smp_init_arch_info(struct target *target,
struct esp_xtensa_smp_common *esp_xtensa_smp,
struct xtensa_debug_module_config *dm_cfg,
- const struct esp_xtensa_smp_chip_ops *chip_ops)
+ const struct esp_xtensa_smp_chip_ops *chip_ops,
+ const struct esp_semihost_ops *semihost_ops)
{
- int ret = esp_xtensa_init_arch_info(target, &esp_xtensa_smp->esp_xtensa, dm_cfg);
+ int ret = esp_xtensa_init_arch_info(target, &esp_xtensa_smp->esp_xtensa, dm_cfg, semihost_ops);
if (ret != ERROR_OK)
return ret;
esp_xtensa_smp->chip_ops = chip_ops;
@@ -463,7 +485,24 @@ int esp_xtensa_smp_init_arch_info(struct target *target,
int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *target)
{
- return esp_xtensa_target_init(cmd_ctx, target);
+ int ret = esp_xtensa_target_init(cmd_ctx, target);
+ if (ret != ERROR_OK)
+ return ret;
+
+ if (target->smp) {
+ struct target_list *head;
+ foreach_smp_target(head, target->smp_targets) {
+ struct target *curr = head->target;
+ ret = esp_xtensa_semihosting_init(curr);
+ if (ret != ERROR_OK)
+ return ret;
+ }
+ } else {
+ ret = esp_xtensa_semihosting_init(target);
+ if (ret != ERROR_OK)
+ return ret;
+ }
+ return ERROR_OK;
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_xtdef)
diff --git a/src/target/espressif/esp_xtensa_smp.h b/src/target/espressif/esp_xtensa_smp.h
index bafd42066..aeb1d61f5 100644
--- a/src/target/espressif/esp_xtensa_smp.h
+++ b/src/target/espressif/esp_xtensa_smp.h
@@ -44,7 +44,8 @@ int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *t
int esp_xtensa_smp_init_arch_info(struct target *target,
struct esp_xtensa_smp_common *esp_xtensa_smp,
struct xtensa_debug_module_config *dm_cfg,
- const struct esp_xtensa_smp_chip_ops *chip_ops);
+ const struct esp_xtensa_smp_chip_ops *chip_ops,
+ const struct esp_semihost_ops *semihost_ops);
extern const struct command_registration esp_xtensa_smp_command_handlers[];
extern const struct command_registration esp_xtensa_smp_xtensa_command_handlers[];
diff --git a/tcl/target/esp32.cfg b/tcl/target/esp32.cfg
index 4206080ac..f4c13aa5b 100644
--- a/tcl/target/esp32.cfg
+++ b/tcl/target/esp32.cfg
@@ -3,6 +3,9 @@
# The ESP32 only supports JTAG.
transport select jtag
+# Source the ESP common configuration file
+source [find target/esp_common.cfg]
+
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
@@ -67,6 +70,30 @@ if { $_ONLYCPU != 1 } {
$_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt }
}
+$_TARGETNAME_0 configure -event examine-end {
+ # Need to enable to set 'semihosting_basedir'
+ arm semihosting enable
+ arm semihosting_resexit enable
+ if { [info exists _SEMIHOST_BASEDIR] } {
+ if { $_SEMIHOST_BASEDIR != "" } {
+ arm semihosting_basedir $_SEMIHOST_BASEDIR
+ }
+ }
+}
+
+if { $_ONLYCPU != 1 } {
+ $_TARGETNAME_1 configure -event examine-end {
+ # Need to enable to set 'semihosting_basedir'
+ arm semihosting enable
+ arm semihosting_resexit enable
+ if { [info exists _SEMIHOST_BASEDIR] } {
+ if { $_SEMIHOST_BASEDIR != "" } {
+ arm semihosting_basedir $_SEMIHOST_BASEDIR
+ }
+ }
+ }
+}
+
gdb_breakpoint_override hard
source [find target/xtensa-core-esp32.cfg]
diff --git a/tcl/target/esp32s2.cfg b/tcl/target/esp32s2.cfg
index 23ada5e9b..e478a6d39 100644
--- a/tcl/target/esp32s2.cfg
+++ b/tcl/target/esp32s2.cfg
@@ -7,6 +7,8 @@ set CPU_MAX_ADDRESS 0xFFFFFFFF
source [find bitsbytes.tcl]
source [find memory.tcl]
source [find mmr_helpers.tcl]
+# Source the ESP common configuration file
+source [find target/esp_common.cfg]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
@@ -60,6 +62,17 @@ $_TARGETNAME configure -event gdb-attach {
xtensa maskisr on
+$_TARGETNAME configure -event examine-end {
+ # Need to enable to set 'semihosting_basedir'
+ arm semihosting enable
+ arm semihosting_resexit enable
+ if { [info exists _SEMIHOST_BASEDIR] } {
+ if { $_SEMIHOST_BASEDIR != "" } {
+ arm semihosting_basedir $_SEMIHOST_BASEDIR
+ }
+ }
+}
+
$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
gdb_breakpoint_override hard
diff --git a/tcl/target/esp32s3.cfg b/tcl/target/esp32s3.cfg
index a25dc145c..42b219963 100644
--- a/tcl/target/esp32s3.cfg
+++ b/tcl/target/esp32s3.cfg
@@ -7,6 +7,9 @@ set CPU_MAX_ADDRESS 0xFFFFFFFF
source [find bitsbytes.tcl]
source [find memory.tcl]
source [find mmr_helpers.tcl]
+# Source the ESP common configuration file
+source [find target/esp_common.cfg]
+
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
@@ -96,6 +99,29 @@ if { $_ONLYCPU != 1 } {
$_TARGETNAME_0 xtensa maskisr on
$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
+$_TARGETNAME_0 configure -event examine-end {
+ # Need to enable to set 'semihosting_basedir'
+ arm semihosting enable
+ arm semihosting_resexit enable
+ if { [info exists _SEMIHOST_BASEDIR] } {
+ if { $_SEMIHOST_BASEDIR != "" } {
+ arm semihosting_basedir $_SEMIHOST_BASEDIR
+ }
+ }
+}
+
+if { $_ONLYCPU != 1 } {
+ $_TARGETNAME_1 configure -event examine-end {
+ # Need to enable to set 'semihosting_basedir'
+ arm semihosting enable
+ arm semihosting_resexit enable
+ if { [info exists _SEMIHOST_BASEDIR] } {
+ if { $_SEMIHOST_BASEDIR != "" } {
+ arm semihosting_basedir $_SEMIHOST_BASEDIR
+ }
+ }
+ }
+}
$_TARGETNAME_0 configure -event gdb-attach {
$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
diff --git a/tcl/target/esp_common.cfg b/tcl/target/esp_common.cfg
new file mode 100644
index 000000000..424c0cdff
--- /dev/null
+++ b/tcl/target/esp_common.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Common ESP chips definitions
+
+if { [info exists ESP_SEMIHOST_BASEDIR] } {
+ set _SEMIHOST_BASEDIR $ESP_SEMIHOST_BASEDIR
+} else {
+ # by default current dir (when OOCD has been started)
+ set _SEMIHOST_BASEDIR "."
+}
-----------------------------------------------------------------------
Summary of changes:
src/target/espressif/Makefile.am | 6 +-
src/target/espressif/esp32.c | 14 ++-
src/target/espressif/esp32s2.c | 34 ++++++-
src/target/espressif/esp32s3.c | 17 +++-
src/target/espressif/esp_semihosting.c | 127 ++++++++++++++++++++++++++
src/target/espressif/esp_semihosting.h | 55 +++++++++++
src/target/espressif/esp_xtensa.c | 12 ++-
src/target/espressif/esp_xtensa.h | 7 +-
src/target/espressif/esp_xtensa_semihosting.c | 114 +++++++++++++++++++++++
src/target/espressif/esp_xtensa_semihosting.h | 15 +++
src/target/espressif/esp_xtensa_smp.c | 45 ++++++++-
src/target/espressif/esp_xtensa_smp.h | 3 +-
tcl/target/esp32.cfg | 27 ++++++
tcl/target/esp32s2.cfg | 13 +++
tcl/target/esp32s3.cfg | 26 ++++++
tcl/target/esp_common.cfg | 10 ++
16 files changed, 510 insertions(+), 15 deletions(-)
create mode 100644 src/target/espressif/esp_semihosting.c
create mode 100644 src/target/espressif/esp_semihosting.h
create mode 100644 src/target/espressif/esp_xtensa_semihosting.c
create mode 100644 src/target/espressif/esp_xtensa_semihosting.h
create mode 100644 tcl/target/esp_common.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-09-03 21:27:51
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 7dc4be3157d666ef05905151b7b4d0f05778b08a (commit)
from 6db57051d070fc8d6bb54d21413e5e8610972651 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 7dc4be3157d666ef05905151b7b4d0f05778b08a
Author: iysheng <iyy...@gm...>
Date: Sat Aug 20 08:30:59 2022 +0800
target/arm: Add support with identify STAR-MC1
Tested with an PLUS-F5270 board which uses the MM32F5277E9PV.
Signed-off-by: iysheng <iyy...@gm...>
Change-Id: Icb75ae8337fdc6fa60e39d3d74dd8bc163707bdd
Reviewed-on: https://review.openocd.org/c/openocd/+/7136
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index aeaeb1829..727d9ca07 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -103,6 +103,12 @@ static const struct cortex_m_part_info cortex_m_parts[] = {
.arch = ARM_ARCH_V8M,
.flags = CORTEX_M_F_HAS_FPV5,
},
+ {
+ .partno = STAR_MC1_PARTNO,
+ .name = "STAR-MC1",
+ .arch = ARM_ARCH_V8M,
+ .flags = CORTEX_M_F_HAS_FPV5,
+ },
};
/* forward declarations */
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 69368a919..b1de26ebc 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -36,6 +36,7 @@
enum cortex_m_partno {
CORTEX_M_PARTNO_INVALID,
+ STAR_MC1_PARTNO = 0x132,
CORTEX_M0_PARTNO = 0xC20,
CORTEX_M1_PARTNO = 0xC21,
CORTEX_M3_PARTNO = 0xC23,
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_m.c | 6 ++++++
src/target/cortex_m.h | 1 +
2 files changed, 7 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-09-01 10:23:38
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 6db57051d070fc8d6bb54d21413e5e8610972651 (commit)
from a527112dae0e8b3a31589c27d01a97174f24e1df (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 6db57051d070fc8d6bb54d21413e5e8610972651
Author: Erhan Kurubas <erh...@es...>
Date: Sun Aug 21 21:57:32 2022 +0300
flash/nor/kinetis: fix clang scan-build error format-truncation
kinetis.c:994:61: error: '%u' directive output may be truncated
writing between 1 and 10 bytes into a region of size 4
[-Werror=format-truncation=]
tested with scan-build-14
Signed-off-by: Erhan Kurubas <erh...@es...>
Change-Id: I72d141a3f8e19ca3596beee2be8434fc8492946f
Reviewed-on: https://review.openocd.org/c/openocd/+/7140
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c
index 61e7b17ab..239cf4164 100644
--- a/src/flash/nor/kinetis.c
+++ b/src/flash/nor/kinetis.c
@@ -948,7 +948,7 @@ static int kinetis_create_missing_banks(struct kinetis_chip *k_chip)
unsigned num_blocks;
struct kinetis_flash_bank *k_bank;
struct flash_bank *bank;
- char base_name[69], name[80], num[4];
+ char base_name[69], name[87], num[11];
char *class, *p;
num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/kinetis.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-27 16:21:41
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a527112dae0e8b3a31589c27d01a97174f24e1df (commit)
from d93ac5482afc97a0c712ec16716a8f6ecc10fdfa (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit a527112dae0e8b3a31589c27d01a97174f24e1df
Author: Tim Newsome <ti...@si...>
Date: Fri Jul 8 13:02:13 2022 -0700
target/riscv: Update with latest encoding from riscv-opcodes
This gets us a clearly labeled BSD-3-Clause header, which should be
compatible with OpenOCD and Fedora, and also make it clear what the
license actually is.
See https://github.com/riscv/riscv-openocd/pull/710,
https://github.com/riscv/riscv-openocd/pull/713, and
https://github.com/riscv/riscv-openocd/pull/717.
Change-Id: I992b4f3bb230edb9f281e2278dd41c712098ed4c
Signed-off-by: Tim Newsome <ti...@si...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7084
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/riscv/encoding.h b/src/target/riscv/encoding.h
index 4445f0bd2..c2da4e676 100644
--- a/src/target/riscv/encoding.h
+++ b/src/target/riscv/encoding.h
@@ -1,10 +1,12 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/* Copyright (c) 2022 RISC-V International */
+
/*
- * This file is auto-generated by running 'make ../riscv-openocd/src/target/riscv/encoding.h' in
- * https://github.com/riscv/riscv-opcodes (6c34f60)
+ * This file is auto-generated by running 'make' in
+ * https://github.com/riscv/riscv-opcodes (dcdf8d3)
*/
-/* See LICENSE for license details. */
-
#ifndef RISCV_CSR_ENCODING_H
#define RISCV_CSR_ENCODING_H
@@ -139,6 +141,7 @@
#define MIP_VSEIP (1 << IRQ_VS_EXT)
#define MIP_MEIP (1 << IRQ_M_EXT)
#define MIP_SGEIP (1 << IRQ_S_GEXT)
+#define MIP_LCOFIP (1 << IRQ_LCOF)
#define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP)
#define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
@@ -149,6 +152,74 @@
#define SIP_SSIP MIP_SSIP
#define SIP_STIP MIP_STIP
+#define MENVCFG_FIOM 0x00000001
+#define MENVCFG_CBIE 0x00000030
+#define MENVCFG_CBCFE 0x00000040
+#define MENVCFG_CBZE 0x00000080
+#define MENVCFG_PBMTE 0x4000000000000000
+#define MENVCFG_STCE 0x8000000000000000
+
+#define MENVCFGH_PBMTE 0x40000000
+#define MENVCFGH_STCE 0x80000000
+
+#define MSTATEEN0_CS 0x00000001
+#define MSTATEEN0_FCSR 0x00000002
+#define MSTATEEN0_HCONTEXT 0x0200000000000000
+#define MSTATEEN0_HENVCFG 0x4000000000000000
+#define MSTATEEN_HSTATEEN 0x8000000000000000
+
+#define MSTATEEN0H_HCONTEXT 0x02000000
+#define MSTATEEN0H_HENVCFG 0x40000000
+#define MSTATEENH_HSTATEEN 0x80000000
+
+#define MHPMEVENT_VUINH 0x0400000000000000
+#define MHPMEVENT_VSINH 0x0800000000000000
+#define MHPMEVENT_UINH 0x1000000000000000
+#define MHPMEVENT_SINH 0x2000000000000000
+#define MHPMEVENT_MINH 0x4000000000000000
+#define MHPMEVENT_OF 0x8000000000000000
+
+#define MHPMEVENTH_VUINH 0x04000000
+#define MHPMEVENTH_VSINH 0x08000000
+#define MHPMEVENTH_UINH 0x10000000
+#define MHPMEVENTH_SINH 0x20000000
+#define MHPMEVENTH_MINH 0x40000000
+#define MHPMEVENTH_OF 0x80000000
+
+#define HENVCFG_FIOM 0x00000001
+#define HENVCFG_CBIE 0x00000030
+#define HENVCFG_CBCFE 0x00000040
+#define HENVCFG_CBZE 0x00000080
+#define HENVCFG_PBMTE 0x4000000000000000
+#define HENVCFG_STCE 0x8000000000000000
+
+#define HENVCFGH_PBMTE 0x40000000
+#define HENVCFGH_STCE 0x80000000
+
+#define HSTATEEN0_CS 0x00000001
+#define HSTATEEN0_FCSR 0x00000002
+#define HSTATEEN0_SCONTEXT 0x0200000000000000
+#define HSTATEEN0_SENVCFG 0x4000000000000000
+#define HSTATEEN_SSTATEEN 0x8000000000000000
+
+#define HSTATEEN0H_SCONTEXT 0x02000000
+#define HSTATEEN0H_SENVCFG 0x40000000
+#define HSTATEENH_SSTATEEN 0x80000000
+
+#define SENVCFG_FIOM 0x00000001
+#define SENVCFG_CBIE 0x00000030
+#define SENVCFG_CBCFE 0x00000040
+#define SENVCFG_CBZE 0x00000080
+
+#define SSTATEEN0_CS 0x00000001
+#define SSTATEEN0_FCSR 0x00000002
+
+#define MSECCFG_MML 0x00000001
+#define MSECCFG_MMWP 0x00000002
+#define MSECCFG_RLB 0x00000004
+#define MSECCFG_USEED 0x00000100
+#define MSECCFG_SSEED 0x00000200
+
#define PRV_U 0
#define PRV_S 1
#define PRV_M 3
@@ -181,6 +252,7 @@
#define HGATP_MODE_SV32X4 1
#define HGATP_MODE_SV39X4 8
#define HGATP_MODE_SV48X4 9
+#define HGATP_MODE_SV57X4 10
#define PMP_R 0x01
#define PMP_W 0x02
@@ -207,7 +279,7 @@
#define IRQ_M_EXT 11
#define IRQ_S_GEXT 12
#define IRQ_COP 12
-#define IRQ_HOST 13
+#define IRQ_LCOF 13
/* page table entry (PTE) fields */
#define PTE_V 0x001 /* Valid */
@@ -278,3797 +350,3344 @@
#endif
#endif
-/* Automatically generated by parse_opcodes. */
+
+/* Automatically generated by parse_opcodes. */
#ifndef RISCV_ENCODING_H
#define RISCV_ENCODING_H
-#define MATCH_SLLI_RV32 0x1013
-#define MASK_SLLI_RV32 0xfe00707f
-#define MATCH_SRLI_RV32 0x5013
-#define MASK_SRLI_RV32 0xfe00707f
-#define MATCH_SRAI_RV32 0x40005013
-#define MASK_SRAI_RV32 0xfe00707f
-#define MATCH_FRFLAGS 0x102073
-#define MASK_FRFLAGS 0xfffff07f
-#define MATCH_FSFLAGS 0x101073
-#define MASK_FSFLAGS 0xfff0707f
-#define MATCH_FSFLAGSI 0x105073
-#define MASK_FSFLAGSI 0xfff0707f
-#define MATCH_FRRM 0x202073
-#define MASK_FRRM 0xfffff07f
-#define MATCH_FSRM 0x201073
-#define MASK_FSRM 0xfff0707f
-#define MATCH_FSRMI 0x205073
-#define MASK_FSRMI 0xfff0707f
-#define MATCH_FSCSR 0x301073
-#define MASK_FSCSR 0xfff0707f
-#define MATCH_FRCSR 0x302073
-#define MASK_FRCSR 0xfffff07f
-#define MATCH_RDCYCLE 0xc0002073
-#define MASK_RDCYCLE 0xfffff07f
-#define MATCH_RDTIME 0xc0102073
-#define MASK_RDTIME 0xfffff07f
-#define MATCH_RDINSTRET 0xc0202073
-#define MASK_RDINSTRET 0xfffff07f
-#define MATCH_RDCYCLEH 0xc8002073
-#define MASK_RDCYCLEH 0xfffff07f
-#define MATCH_RDTIMEH 0xc8102073
-#define MASK_RDTIMEH 0xfffff07f
-#define MATCH_RDINSTRETH 0xc8202073
-#define MASK_RDINSTRETH 0xfffff07f
-#define MATCH_SCALL 0x73
-#define MASK_SCALL 0xffffffff
-#define MATCH_SBREAK 0x100073
-#define MASK_SBREAK 0xffffffff
-#define MATCH_FMV_X_S 0xe0000053
-#define MASK_FMV_X_S 0xfff0707f
-#define MATCH_FMV_S_X 0xf0000053
-#define MASK_FMV_S_X 0xfff0707f
-#define MATCH_FENCE_TSO 0x8330000f
-#define MASK_FENCE_TSO 0xfff0707f
-#define MATCH_PAUSE 0x100000f
-#define MASK_PAUSE 0xffffffff
-#define MATCH_BEQ 0x63
-#define MASK_BEQ 0x707f
-#define MATCH_BNE 0x1063
-#define MASK_BNE 0x707f
-#define MATCH_BLT 0x4063
-#define MASK_BLT 0x707f
-#define MATCH_BGE 0x5063
-#define MASK_BGE 0x707f
-#define MATCH_BLTU 0x6063
-#define MASK_BLTU 0x707f
-#define MATCH_BGEU 0x7063
-#define MASK_BGEU 0x707f
-#define MATCH_JALR 0x67
-#define MASK_JALR 0x707f
-#define MATCH_JAL 0x6f
-#define MASK_JAL 0x7f
-#define MATCH_LUI 0x37
-#define MASK_LUI 0x7f
-#define MATCH_AUIPC 0x17
-#define MASK_AUIPC 0x7f
-#define MATCH_ADDI 0x13
-#define MASK_ADDI 0x707f
-#define MATCH_SLTI 0x2013
-#define MASK_SLTI 0x707f
-#define MATCH_SLTIU 0x3013
-#define MASK_SLTIU 0x707f
-#define MATCH_XORI 0x4013
-#define MASK_XORI 0x707f
-#define MATCH_ORI 0x6013
-#define MASK_ORI 0x707f
-#define MATCH_ANDI 0x7013
-#define MASK_ANDI 0x707f
#define MATCH_ADD 0x33
-#define MASK_ADD 0xfe00707f
-#define MATCH_SUB 0x40000033
-#define MASK_SUB 0xfe00707f
-#define MATCH_SLL 0x1033
-#define MASK_SLL 0xfe00707f
-#define MATCH_SLT 0x2033
-#define MASK_SLT 0xfe00707f
-#define MATCH_SLTU 0x3033
-#define MASK_SLTU 0xfe00707f
-#define MATCH_XOR 0x4033
-#define MASK_XOR 0xfe00707f
-#define MATCH_SRL 0x5033
-#define MASK_SRL 0xfe00707f
-#define MATCH_SRA 0x40005033
-#define MASK_SRA 0xfe00707f
-#define MATCH_OR 0x6033
-#define MASK_OR 0xfe00707f
-#define MATCH_AND 0x7033
-#define MASK_AND 0xfe00707f
-#define MATCH_LB 0x3
-#define MASK_LB 0x707f
-#define MATCH_LH 0x1003
-#define MASK_LH 0x707f
-#define MATCH_LW 0x2003
-#define MASK_LW 0x707f
-#define MATCH_LBU 0x4003
-#define MASK_LBU 0x707f
-#define MATCH_LHU 0x5003
-#define MASK_LHU 0x707f
-#define MATCH_SB 0x23
-#define MASK_SB 0x707f
-#define MATCH_SH 0x1023
-#define MASK_SH 0x707f
-#define MATCH_SW 0x2023
-#define MASK_SW 0x707f
-#define MATCH_FENCE 0xf
-#define MASK_FENCE 0x707f
-#define MATCH_FENCE_I 0x100f
-#define MASK_FENCE_I 0x707f
+#define MASK_ADD 0xfe00707f
+#define MATCH_ADD16 0x40000077
+#define MASK_ADD16 0xfe00707f
+#define MATCH_ADD32 0x40002077
+#define MASK_ADD32 0xfe00707f
+#define MATCH_ADD64 0xc0001077
+#define MASK_ADD64 0xfe00707f
+#define MATCH_ADD8 0x48000077
+#define MASK_ADD8 0xfe00707f
+#define MATCH_ADD_UW 0x800003b
+#define MASK_ADD_UW 0xfe00707f
+#define MATCH_ADDD 0x7b
+#define MASK_ADDD 0xfe00707f
+#define MATCH_ADDI 0x13
+#define MASK_ADDI 0x707f
+#define MATCH_ADDID 0x5b
+#define MASK_ADDID 0x707f
#define MATCH_ADDIW 0x1b
-#define MASK_ADDIW 0x707f
-#define MATCH_SLLIW 0x101b
-#define MASK_SLLIW 0xfe00707f
-#define MATCH_SRLIW 0x501b
-#define MASK_SRLIW 0xfe00707f
-#define MATCH_SRAIW 0x4000501b
-#define MASK_SRAIW 0xfe00707f
+#define MASK_ADDIW 0x707f
#define MATCH_ADDW 0x3b
-#define MASK_ADDW 0xfe00707f
-#define MATCH_SUBW 0x4000003b
-#define MASK_SUBW 0xfe00707f
-#define MATCH_SLLW 0x103b
-#define MASK_SLLW 0xfe00707f
-#define MATCH_SRLW 0x503b
-#define MASK_SRLW 0xfe00707f
-#define MATCH_SRAW 0x4000503b
-#define MASK_SRAW 0xfe00707f
-#define MATCH_LD 0x3003
-#define MASK_LD 0x707f
-#define MATCH_LWU 0x6003
-#define MASK_LWU 0x707f
-#define MATCH_SD 0x3023
-#define MASK_SD 0x707f
-#define MATCH_SLLI 0x1013
-#define MASK_SLLI 0xfc00707f
-#define MATCH_SRLI 0x5013
-#define MASK_SRLI 0xfc00707f
-#define MATCH_SRAI 0x40005013
-#define MASK_SRAI 0xfc00707f
-#define MATCH_MUL 0x2000033
-#define MASK_MUL 0xfe00707f
-#define MATCH_MULH 0x2001033
-#define MASK_MULH 0xfe00707f
-#define MATCH_MULHSU 0x2002033
-#define MASK_MULHSU 0xfe00707f
-#define MATCH_MULHU 0x2003033
-#define MASK_MULHU 0xfe00707f
-#define MATCH_DIV 0x2004033
-#define MASK_DIV 0xfe00707f
-#define MATCH_DIVU 0x2005033
-#define MASK_DIVU 0xfe00707f
-#define MATCH_REM 0x2006033
-#define MASK_REM 0xfe00707f
-#define MATCH_REMU 0x2007033
-#define MASK_REMU 0xfe00707f
-#define MATCH_MULW 0x200003b
-#define MASK_MULW 0xfe00707f
-#define MATCH_DIVW 0x200403b
-#define MASK_DIVW 0xfe00707f
-#define MATCH_DIVUW 0x200503b
-#define MASK_DIVUW 0xfe00707f
-#define MATCH_REMW 0x200603b
-#define MASK_REMW 0xfe00707f
-#define MATCH_REMUW 0x200703b
-#define MASK_REMUW 0xfe00707f
+#define MASK_ADDW 0xfe00707f
+#define MATCH_AES32DSI 0x2a000033
+#define MASK_AES32DSI 0x3e00707f
+#define MATCH_AES32DSMI 0x2e000033
+#define MASK_AES32DSMI 0x3e00707f
+#define MATCH_AES32ESI 0x22000033
+#define MASK_AES32ESI 0x3e00707f
+#define MATCH_AES32ESMI 0x26000033
+#define MASK_AES32ESMI 0x3e00707f
+#define MATCH_AES64DS 0x3a000033
+#define MASK_AES64DS 0xfe00707f
+#define MATCH_AES64DSM 0x3e000033
+#define MASK_AES64DSM 0xfe00707f
+#define MATCH_AES64ES 0x32000033
+#define MASK_AES64ES 0xfe00707f
+#define MATCH_AES64ESM 0x36000033
+#define MASK_AES64ESM 0xfe00707f
+#define MATCH_AES64IM 0x30001013
+#define MASK_AES64IM 0xfff0707f
+#define MATCH_AES64KS1I 0x31001013
+#define MASK_AES64KS1I 0xff00707f
+#define MATCH_AES64KS2 0x7e000033
+#define MASK_AES64KS2 0xfe00707f
+#define MATCH_AMOADD_D 0x302f
+#define MASK_AMOADD_D 0xf800707f
#define MATCH_AMOADD_W 0x202f
-#define MASK_AMOADD_W 0xf800707f
-#define MATCH_AMOXOR_W 0x2000202f
-#define MASK_AMOXOR_W 0xf800707f
-#define MATCH_AMOOR_W 0x4000202f
-#define MASK_AMOOR_W 0xf800707f
+#define MASK_AMOADD_W 0xf800707f
+#define MATCH_AMOAND_D 0x6000302f
+#define MASK_AMOAND_D 0xf800707f
#define MATCH_AMOAND_W 0x6000202f
-#define MASK_AMOAND_W 0xf800707f
-#define MATCH_AMOMIN_W 0x8000202f
-#define MASK_AMOMIN_W 0xf800707f
+#define MASK_AMOAND_W 0xf800707f
+#define MATCH_AMOMAX_D 0xa000302f
+#define MASK_AMOMAX_D 0xf800707f
#define MATCH_AMOMAX_W 0xa000202f
-#define MASK_AMOMAX_W 0xf800707f
-#define MATCH_AMOMINU_W 0xc000202f
-#define MASK_AMOMINU_W 0xf800707f
+#define MASK_AMOMAX_W 0xf800707f
+#define MATCH_AMOMAXU_D 0xe000302f
+#define MASK_AMOMAXU_D 0xf800707f
#define MATCH_AMOMAXU_W 0xe000202f
-#define MASK_AMOMAXU_W 0xf800707f
-#define MATCH_AMOSWAP_W 0x800202f
-#define MASK_AMOSWAP_W 0xf800707f
-#define MATCH_LR_W 0x1000202f
-#define MASK_LR_W 0xf9f0707f
-#define MATCH_SC_W 0x1800202f
-#define MASK_SC_W 0xf800707f
-#define MATCH_AMOADD_D 0x302f
-#define MASK_AMOADD_D 0xf800707f
-#define MATCH_AMOXOR_D 0x2000302f
-#define MASK_AMOXOR_D 0xf800707f
-#define MATCH_AMOOR_D 0x4000302f
-#define MASK_AMOOR_D 0xf800707f
-#define MATCH_AMOAND_D 0x6000302f
-#define MASK_AMOAND_D 0xf800707f
+#define MASK_AMOMAXU_W 0xf800707f
#define MATCH_AMOMIN_D 0x8000302f
-#define MASK_AMOMIN_D 0xf800707f
-#define MATCH_AMOMAX_D 0xa000302f
-#define MASK_AMOMAX_D 0xf800707f
+#define MASK_AMOMIN_D 0xf800707f
+#define MATCH_AMOMIN_W 0x8000202f
+#define MASK_AMOMIN_W 0xf800707f
#define MATCH_AMOMINU_D 0xc000302f
-#define MASK_AMOMINU_D 0xf800707f
-#define MATCH_AMOMAXU_D 0xe000302f
-#define MASK_AMOMAXU_D 0xf800707f
+#define MASK_AMOMINU_D 0xf800707f
+#define MATCH_AMOMINU_W 0xc000202f
+#define MASK_AMOMINU_W 0xf800707f
+#define MATCH_AMOOR_D 0x4000302f
+#define MASK_AMOOR_D 0xf800707f
+#define MATCH_AMOOR_W 0x4000202f
+#define MASK_AMOOR_W 0xf800707f
#define MATCH_AMOSWAP_D 0x800302f
-#define MASK_AMOSWAP_D 0xf800707f
-#define MATCH_LR_D 0x1000302f
-#define MASK_LR_D 0xf9f0707f
-#define MATCH_SC_D 0x1800302f
-#define MASK_SC_D 0xf800707f
-#define MATCH_HFENCE_VVMA 0x22000073
-#define MASK_HFENCE_VVMA 0xfe007fff
-#define MATCH_HFENCE_GVMA 0x62000073
-#define MASK_HFENCE_GVMA 0xfe007fff
-#define MATCH_HLV_B 0x60004073
-#define MASK_HLV_B 0xfff0707f
-#define MATCH_HLV_BU 0x60104073
-#define MASK_HLV_BU 0xfff0707f
-#define MATCH_HLV_H 0x64004073
-#define MASK_HLV_H 0xfff0707f
-#define MATCH_HLV_HU 0x64104073
-#define MASK_HLV_HU 0xfff0707f
-#define MATCH_HLVX_HU 0x64304073
-#define MASK_HLVX_HU 0xfff0707f
-#define MATCH_HLV_W 0x68004073
-#define MASK_HLV_W 0xfff0707f
-#define MATCH_HLVX_WU 0x68304073
-#define MASK_HLVX_WU 0xfff0707f
-#define MATCH_HSV_B 0x62004073
-#define MASK_HSV_B 0xfe007fff
-#define MATCH_HSV_H 0x66004073
-#define MASK_HSV_H 0xfe007fff
-#define MATCH_HSV_W 0x6a004073
-#define MASK_HSV_W 0xfe007fff
-#define MATCH_HLV_WU 0x68104073
-#define MASK_HLV_WU 0xfff0707f
-#define MATCH_HLV_D 0x6c004073
-#define MASK_HLV_D 0xfff0707f
-#define MATCH_HSV_D 0x6e004073
-#define MASK_HSV_D 0xfe007fff
-#define MATCH_FADD_S 0x53
-#define MASK_FADD_S 0xfe00007f
-#define MATCH_FSUB_S 0x8000053
-#define MASK_FSUB_S 0xfe00007f
-#define MATCH_FMUL_S 0x10000053
-#define MASK_FMUL_S 0xfe00007f
-#define MATCH_FDIV_S 0x18000053
-#define MASK_FDIV_S 0xfe00007f
-#define MATCH_FSGNJ_S 0x20000053
-#define MASK_FSGNJ_S 0xfe00707f
-#define MATCH_FSGNJN_S 0x20001053
-#define MASK_FSGNJN_S 0xfe00707f
-#define MATCH_FSGNJX_S 0x20002053
-#define MASK_FSGNJX_S 0xfe00707f
-#define MATCH_FMIN_S 0x28000053
-#define MASK_FMIN_S 0xfe00707f
-#define MATCH_FMAX_S 0x28001053
-#define MASK_FMAX_S 0xfe00707f
-#define MATCH_FSQRT_S 0x58000053
-#define MASK_FSQRT_S 0xfff0007f
-#define MATCH_FLE_S 0xa0000053
-#define MASK_FLE_S 0xfe00707f
-#define MATCH_FLT_S 0xa0001053
-#define MASK_FLT_S 0xfe00707f
-#define MATCH_FEQ_S 0xa0002053
-#define MASK_FEQ_S 0xfe00707f
-#define MATCH_FCVT_W_S 0xc0000053
-#define MASK_FCVT_W_S 0xfff0007f
-#define MATCH_FCVT_WU_S 0xc0100053
-#define MASK_FCVT_WU_S 0xfff0007f
-#define MATCH_FMV_X_W 0xe0000053
-#define MASK_FMV_X_W 0xfff0707f
-#define MATCH_FCLASS_S 0xe0001053
-#define MASK_FCLASS_S 0xfff0707f
-#define MATCH_FCVT_S_W 0xd0000053
-#define MASK_FCVT_S_W 0xfff0007f
-#define MATCH_FCVT_S_WU 0xd0100053
-#define MASK_FCVT_S_WU 0xfff0007f
-#define MATCH_FMV_W_X 0xf0000053
-#define MASK_FMV_W_X 0xfff0707f
-#define MATCH_FLW 0x2007
-#define MASK_FLW 0x707f
-#define MATCH_FSW 0x2027
-#define MASK_FSW 0x707f
-#define MATCH_FMADD_S 0x43
-#define MASK_FMADD_S 0x600007f
-#define MATCH_FMSUB_S 0x47
-#define MASK_FMSUB_S 0x600007f
-#define MATCH_FNMSUB_S 0x4b
-#define MASK_FNMSUB_S 0x600007f
-#define MATCH_FNMADD_S 0x4f
-#define MASK_FNMADD_S 0x600007f
-#define MATCH_FCVT_L_S 0xc0200053
-#define MASK_FCVT_L_S 0xfff0007f
-#define MATCH_FCVT_LU_S 0xc0300053
-#define MASK_FCVT_LU_S 0xfff0007f
-#define MATCH_FCVT_S_L 0xd0200053
-#define MASK_FCVT_S_L 0xfff0007f
-#define MATCH_FCVT_S_LU 0xd0300053
-#define MASK_FCVT_S_LU 0xfff0007f
-#define MATCH_FADD_D 0x2000053
-#define MASK_FADD_D 0xfe00007f
-#define MATCH_FSUB_D 0xa000053
-#define MASK_FSUB_D 0xfe00007f
-#define MATCH_FMUL_D 0x12000053
-#define MASK_FMUL_D 0xfe00007f
-#define MATCH_FDIV_D 0x1a000053
-#define MASK_FDIV_D 0xfe00007f
-#define MATCH_FSGNJ_D 0x22000053
-#define MASK_FSGNJ_D 0xfe00707f
-#define MATCH_FSGNJN_D 0x22001053
-#define MASK_FSGNJN_D 0xfe00707f
-#define MATCH_FSGNJX_D 0x22002053
-#define MASK_FSGNJX_D 0xfe00707f
-#define MATCH_FMIN_D 0x2a000053
-#define MASK_FMIN_D 0xfe00707f
-#define MATCH_FMAX_D 0x2a001053
-#define MASK_FMAX_D 0xfe00707f
-#define MATCH_FCVT_S_D 0x40100053
-#define MASK_FCVT_S_D 0xfff0007f
-#define MATCH_FCVT_D_S 0x42000053
-#define MASK_FCVT_D_S 0xfff0007f
-#define MATCH_FSQRT_D 0x5a000053
-#define MASK_FSQRT_D 0xfff0007f
-#define MATCH_FLE_D 0xa2000053
-#define MASK_FLE_D 0xfe00707f
-#define MATCH_FLT_D 0xa2001053
-#define MASK_FLT_D 0xfe00707f
-#define MATCH_FEQ_D 0xa2002053
-#define MASK_FEQ_D 0xfe00707f
-#define MATCH_FCVT_W_D 0xc2000053
-#define MASK_FCVT_W_D 0xfff0007f
-#define MATCH_FCVT_WU_D 0xc2100053
-#define MASK_FCVT_WU_D 0xfff0007f
-#define MATCH_FCLASS_D 0xe2001053
-#define MASK_FCLASS_D 0xfff0707f
-#define MATCH_FCVT_D_W 0xd2000053
-#define MASK_FCVT_D_W 0xfff0007f
-#define MATCH_FCVT_D_WU 0xd2100053
-#define MASK_FCVT_D_WU 0xfff0007f
-#define MATCH_FLD 0x3007
-#define MASK_FLD 0x707f
-#define MATCH_FSD 0x3027
-#define MASK_FSD 0x707f
-#define MATCH_FMADD_D 0x2000043
-#define MASK_FMADD_D 0x600007f
-#define MATCH_FMSUB_D 0x2000047
-#define MASK_FMSUB_D 0x600007f
-#define MATCH_FNMSUB_D 0x200004b
-#define MASK_FNMSUB_D 0x600007f
-#define MATCH_FNMADD_D 0x200004f
-#define MASK_FNMADD_D 0x600007f
-#define MATCH_FCVT_L_D 0xc2200053
-#define MASK_FCVT_L_D 0xfff0007f
-#define MATCH_FCVT_LU_D 0xc2300053
-#define MASK_FCVT_LU_D 0xfff0007f
-#define MATCH_FMV_X_D 0xe2000053
-#define MASK_FMV_X_D 0xfff0707f
-#define MATCH_FCVT_D_L 0xd2200053
-#define MASK_FCVT_D_L 0xfff0007f
-#define MATCH_FCVT_D_LU 0xd2300053
-#define MASK_FCVT_D_LU 0xfff0007f
-#define MATCH_FMV_D_X 0xf2000053
-#define MASK_FMV_D_X 0xfff0707f
-#define MATCH_FADD_Q 0x6000053
-#define MASK_FADD_Q 0xfe00007f
-#define MATCH_FSUB_Q 0xe000053
-#define MASK_FSUB_Q 0xfe00007f
-#define MATCH_FMUL_Q 0x16000053
-#define MASK_FMUL_Q 0xfe00007f
-#define MATCH_FDIV_Q 0x1e000053
-#define MASK_FDIV_Q 0xfe00007f
-#define MATCH_FSGNJ_Q 0x26000053
-#define MASK_FSGNJ_Q 0xfe00707f
-#define MATCH_FSGNJN_Q 0x26001053
-#define MASK_FSGNJN_Q 0xfe00707f
-#define MATCH_FSGNJX_Q 0x26002053
-#define MASK_FSGNJX_Q 0xfe00707f
-#define MATCH_FMIN_Q 0x2e000053
-#define MASK_FMIN_Q 0xfe00707f
-#define MATCH_FMAX_Q 0x2e001053
-#define MASK_FMAX_Q 0xfe00707f
-#define MATCH_FCVT_S_Q 0x40300053
-#define MASK_FCVT_S_Q 0xfff0007f
-#define MATCH_FCVT_Q_S 0x46000053
-#define MASK_FCVT_Q_S 0xfff0007f
-#define MATCH_FCVT_D_Q 0x42300053
-#define MASK_FCVT_D_Q 0xfff0007f
-#define MATCH_FCVT_Q_D 0x46100053
-#define MASK_FCVT_Q_D 0xfff0007f
-#define MATCH_FSQRT_Q 0x5e000053
-#define MASK_FSQRT_Q 0xfff0007f
-#define MATCH_FLE_Q 0xa6000053
-#define MASK_FLE_Q 0xfe00707f
-#define MATCH_FLT_Q 0xa6001053
-#define MASK_FLT_Q 0xfe00707f
-#define MATCH_FEQ_Q 0xa6002053
-#define MASK_FEQ_Q 0xfe00707f
-#define MATCH_FCVT_W_Q 0xc6000053
-#define MASK_FCVT_W_Q 0xfff0007f
-#define MATCH_FCVT_WU_Q 0xc6100053
-#define MASK_FCVT_WU_Q 0xfff0007f
-#define MATCH_FCLASS_Q 0xe6001053
-#define MASK_FCLASS_Q 0xfff0707f
-#define MATCH_FCVT_Q_W 0xd6000053
-#define MASK_FCVT_Q_W 0xfff0007f
-#define MATCH_FCVT_Q_WU 0xd6100053
-#define MASK_FCVT_Q_WU 0xfff0007f
-#define MATCH_FLQ 0x4007
-#define MASK_FLQ 0x707f
-#define MATCH_FSQ 0x4027
-#define MASK_FSQ 0x707f
-#define MATCH_FMADD_Q 0x6000043
-#define MASK_FMADD_Q 0x600007f
-#define MATCH_FMSUB_Q 0x6000047
-#define MASK_FMSUB_Q 0x600007f
-#define MATCH_FNMSUB_Q 0x600004b
-#define MASK_FNMSUB_Q 0x600007f
-#define MATCH_FNMADD_Q 0x600004f
-#define MASK_FNMADD_Q 0x600007f
-#define MATCH_FCVT_L_Q 0xc6200053
-#define MASK_FCVT_L_Q 0xfff0007f
-#define MATCH_FCVT_LU_Q 0xc6300053
-#define MASK_FCVT_LU_Q 0xfff0007f
-#define MATCH_FCVT_Q_L 0xd6200053
-#define MASK_FCVT_Q_L 0xfff0007f
-#define MATCH_FCVT_Q_LU 0xd6300053
-#define MASK_FCVT_Q_LU 0xfff0007f
+#define MASK_AMOSWAP_D 0xf800707f
+#define MATCH_AMOSWAP_W 0x800202f
+#define MASK_AMOSWAP_W 0xf800707f
+#define MATCH_AMOXOR_D 0x2000302f
+#define MASK_AMOXOR_D 0xf800707f
+#define MATCH_AMOXOR_W 0x2000202f
+#define MASK_AMOXOR_W 0xf800707f
+#define MATCH_AND 0x7033
+#define MASK_AND 0xfe00707f
+#define MATCH_ANDI 0x7013
+#define MASK_ANDI 0x707f
#define MATCH_ANDN 0x40007033
-#define MASK_ANDN 0xfe00707f
-#define MATCH_ORN 0x40006033
-#define MASK_ORN 0xfe00707f
-#define MATCH_XNOR 0x40004033
-#define MASK_XNOR 0xfe00707f
-#define MATCH_SLO 0x20001033
-#define MASK_SLO 0xfe00707f
-#define MATCH_SRO 0x20005033
-#define MASK_SRO 0xfe00707f
-#define MATCH_ROL 0x60001033
-#define MASK_ROL 0xfe00707f
-#define MATCH_ROR 0x60005033
-#define MASK_ROR 0xfe00707f
+#define MASK_ANDN 0xfe00707f
+#define MATCH_AUIPC 0x17
+#define MASK_AUIPC 0x7f
+#define MATCH_AVE 0xe0000077
+#define MASK_AVE 0xfe00707f
#define MATCH_BCLR 0x48001033
-#define MASK_BCLR 0xfe00707f
-#define MATCH_BSET 0x28001033
-#define MASK_BSET 0xfe00707f
-#define MATCH_BINV 0x68001033
-#define MASK_BINV 0xfe00707f
-#define MATCH_BEXT 0x48005033
-#define MASK_BEXT 0xfe00707f
-#define MATCH_GORC 0x28005033
-#define MASK_GORC 0xfe00707f
-#define MATCH_GREV 0x68005033
-#define MASK_GREV 0xfe00707f
-#define MATCH_SLOI 0x20001013
-#define MASK_SLOI 0xfc00707f
-#define MATCH_SROI 0x20005013
-#define MASK_SROI 0xfc00707f
-#define MATCH_RORI 0x60005013
-#define MASK_RORI 0xfc00707f
+#define MASK_BCLR 0xfe00707f
#define MATCH_BCLRI 0x48001013
-#define MASK_BCLRI 0xfc00707f
-#define MATCH_BSETI 0x28001013
-#define MASK_BSETI 0xfc00707f
-#define MATCH_BINVI 0x68001013
-#define MASK_BINVI 0xfc00707f
-#define MATCH_BEXTI 0x48005013
-#define MASK_BEXTI 0xfc00707f
-#define MATCH_GORCI 0x28005013
-#define MASK_GORCI 0xfc00707f
-#define MATCH_GREVI 0x68005013
-#define MASK_GREVI 0xfc00707f
-#define MATCH_CMIX 0x6001033
-#define MASK_CMIX 0x600707f
-#define MATCH_CMOV 0x6005033
-#define MASK_CMOV 0x600707f
-#define MATCH_FSL 0x4001033
-#define MASK_FSL 0x600707f
-#define MATCH_FSR 0x4005033
-#define MASK_FSR 0x600707f
-#define MATCH_FSRI 0x4005013
-#define MASK_FSRI 0x400707f
-#define MATCH_CLZ 0x60001013
-#define MASK_CLZ 0xfff0707f
-#define MATCH_CTZ 0x60101013
-#define MASK_CTZ 0xfff0707f
-#define MATCH_CPOP 0x60201013
-#define MASK_CPOP 0xfff0707f
-#define MATCH_SEXT_B 0x60401013
-#define MASK_SEXT_B 0xfff0707f
-#define MATCH_SEXT_H 0x60501013
-#define MASK_SEXT_H 0xfff0707f
-#define MATCH_CRC32_B 0x61001013
-#define MASK_CRC32_B 0xfff0707f
-#define MATCH_CRC32_H 0x61101013
-#define MASK_CRC32_H 0xfff0707f
-#define MATCH_CRC32_W 0x61201013
-#define MASK_CRC32_W 0xfff0707f
-#define MATCH_CRC32C_B 0x61801013
-#define MASK_CRC32C_B 0xfff0707f
-#define MATCH_CRC32C_H 0x61901013
-#define MASK_CRC32C_H 0xfff0707f
-#define MATCH_CRC32C_W 0x61a01013
-#define MASK_CRC32C_W 0xfff0707f
-#define MATCH_SH1ADD 0x20002033
-#define MASK_SH1ADD 0xfe00707f
-#define MATCH_SH2ADD 0x20004033
-#define MASK_SH2ADD 0xfe00707f
-#define MATCH_SH3ADD 0x20006033
-#define MASK_SH3ADD 0xfe00707f
-#define MATCH_CLMUL 0xa001033
-#define MASK_CLMUL 0xfe00707f
-#define MATCH_CLMULR 0xa002033
-#define MASK_CLMULR 0xfe00707f
-#define MATCH_CLMULH 0xa003033
-#define MASK_CLMULH 0xfe00707f
-#define MATCH_MIN 0xa004033
-#define MASK_MIN 0xfe00707f
-#define MATCH_MINU 0xa005033
-#define MASK_MINU 0xfe00707f
-#define MATCH_MAX 0xa006033
-#define MASK_MAX 0xfe00707f
-#define MATCH_MAXU 0xa007033
-#define MASK_MAXU 0xfe00707f
-#define MATCH_SHFL 0x8001033
-#define MASK_SHFL 0xfe00707f
-#define MATCH_UNSHFL 0x8005033
-#define MASK_UNSHFL 0xfe00707f
+#define MASK_BCLRI 0xfc00707f
#define MATCH_BCOMPRESS 0x8006033
-#define MASK_BCOMPRESS 0xfe00707f
+#define MASK_BCOMPRESS 0xfe00707f
+#define MATCH_BCOMPRESSW 0x800603b
+#define MASK_BCOMPRESSW 0xfe00707f
#define MATCH_BDECOMPRESS 0x48006033
-#define MASK_BDECOMPRESS 0xfe00707f
-#define MATCH_PACK 0x8004033
-#define MASK_PACK 0xfe00707f
-#define MATCH_PACKU 0x48004033
-#define MASK_PACKU 0xfe00707f
-#define MATCH_PACKH 0x8007033
-#define MASK_PACKH 0xfe00707f
+#define MASK_BDECOMPRESS 0xfe00707f
+#define MATCH_BDECOMPRESSW 0x4800603b
+#define MASK_BDECOMPRESSW 0xfe00707f
+#define MATCH_BEQ 0x63
+#define MASK_BEQ 0x707f
+#define MATCH_BEXT 0x48005033
+#define MASK_BEXT 0xfe00707f
+#define MATCH_BEXTI 0x48005013
+#define MASK_BEXTI 0xfc00707f
#define MATCH_BFP 0x48007033
-#define MASK_BFP 0xfe00707f
-#define MATCH_SHFLI 0x8001013
-#define MASK_SHFLI 0xfe00707f
-#define MATCH_UNSHFLI 0x8005013
-#define MASK_UNSHFLI 0xfe00707f
-#define MATCH_XPERM4 0x28002033
-#define MASK_XPERM4 0xfe00707f
-#define MATCH_XPERM8 0x28004033
-#define MASK_XPERM8 0xfe00707f
-#define MATCH_XPERM16 0x28006033
-#define MASK_XPERM16 0xfe00707f
+#define MASK_BFP 0xfe00707f
+#define MATCH_BFPW 0x4800703b
+#define MASK_BFPW 0xfe00707f
+#define MATCH_BGE 0x5063
+#define MASK_BGE 0x707f
+#define MATCH_BGEU 0x7063
+#define MASK_BGEU 0x707f
+#define MATCH_BINV 0x68001033
+#define MASK_BINV 0xfe00707f
+#define MATCH_BINVI 0x68001013
+#define MASK_BINVI 0xfc00707f
+#define MATCH_BITREV 0xe6000077
+#define MASK_BITREV 0xfe00707f
+#define MATCH_BITREVI 0xe8000077
+#define MASK_BITREVI 0xfc00707f
+#define MATCH_BLT 0x4063
+#define MASK_BLT 0x707f
+#define MATCH_BLTU 0x6063
+#define MASK_BLTU 0x707f
#define MATCH_BMATFLIP 0x60301013
-#define MASK_BMATFLIP 0xfff0707f
-#define MATCH_CRC32_D 0x61301013
-#define MASK_CRC32_D 0xfff0707f
-#define MATCH_CRC32C_D 0x61b01013
-#define MASK_CRC32C_D 0xfff0707f
+#define MASK_BMATFLIP 0xfff0707f
#define MATCH_BMATOR 0x8003033
-#define MASK_BMATOR 0xfe00707f
+#define MASK_BMATOR 0xfe00707f
#define MATCH_BMATXOR 0x48003033
-#define MASK_BMATXOR 0xfe00707f
-#define MATCH_SLLI_UW 0x800101b
-#define MASK_SLLI_UW 0xfc00707f
-#define MATCH_ADD_UW 0x800003b
-#define MASK_ADD_UW 0xfe00707f
-#define MATCH_SLOW 0x2000103b
-#define MASK_SLOW 0xfe00707f
-#define MATCH_SROW 0x2000503b
-#define MASK_SROW 0xfe00707f
-#define MATCH_ROLW 0x6000103b
-#define MASK_ROLW 0xfe00707f
-#define MATCH_RORW 0x6000503b
-#define MASK_RORW 0xfe00707f
-#define MATCH_SBCLRW 0x4800103b
-#define MASK_SBCLRW 0xfe00707f
-#define MATCH_SBSETW 0x2800103b
-#define MASK_SBSETW 0xfe00707f
-#define MATCH_SBINVW 0x6800103b
-#define MASK_SBINVW 0xfe00707f
-#define MATCH_SBEXTW 0x4800503b
-#define MASK_SBEXTW 0xfe00707f
-#define MATCH_GORCW 0x2800503b
-#define MASK_GORCW 0xfe00707f
-#define MATCH_GREVW 0x6800503b
-#define MASK_GREVW 0xfe00707f
-#define MATCH_SLOIW 0x2000101b
-#define MASK_SLOIW 0xfe00707f
-#define MATCH_SROIW 0x2000501b
-#define MASK_SROIW 0xfe00707f
-#define MATCH_RORIW 0x6000501b
-#define MASK_RORIW 0xfe00707f
-#define MATCH_SBCLRIW 0x4800101b
-#define MASK_SBCLRIW 0xfe00707f
-#define MATCH_SBSETIW 0x2800101b
-#define MASK_SBSETIW 0xfe00707f
-#define MATCH_SBINVIW 0x6800101b
-#define MASK_SBINVIW 0xfe00707f
-#define MATCH_GORCIW 0x2800501b
-#define MASK_GORCIW 0xfe00707f
-#define MATCH_GREVIW 0x6800501b
-#define MASK_GREVIW 0xfe00707f
-#define MATCH_FSLW 0x400103b
-#define MASK_FSLW 0x600707f
-#define MATCH_FSRW 0x400503b
-#define MASK_FSRW 0x600707f
-#define MATCH_FSRIW 0x400501b
-#define MASK_FSRIW 0x600707f
-#define MATCH_CLZW 0x6000101b
-#define MASK_CLZW 0xfff0707f
-#define MATCH_CTZW 0x6010101b
-#define MASK_CTZW 0xfff0707f
-#define MATCH_CPOPW 0x6020101b
-#define MASK_CPOPW 0xfff0707f
-#define MATCH_SH1ADD_UW 0x2000203b
-#define MASK_SH1ADD_UW 0xfe00707f
-#define MATCH_SH2ADD_UW 0x2000403b
-#define MASK_SH2ADD_UW 0xfe00707f
-#define MATCH_SH3ADD_UW 0x2000603b
-#define MASK_SH3ADD_UW 0xfe00707f
-#define MATCH_SHFLW 0x800103b
-#define MASK_SHFLW 0xfe00707f
-#define MATCH_UNSHFLW 0x800503b
-#define MASK_UNSHFLW 0xfe00707f
-#define MATCH_BCOMPRESSW 0x800603b
-#define MASK_BCOMPRESSW 0xfe00707f
-#define MATCH_BDECOMPRESSW 0x4800603b
-#define MASK_BDECOMPRESSW 0xfe00707f
-#define MATCH_PACKW 0x800403b
-#define MASK_PACKW 0xfe00707f
-#define MATCH_PACKUW 0x4800403b
-#define MASK_PACKUW 0xfe00707f
-#define MATCH_BFPW 0x4800703b
-#define MASK_BFPW 0xfe00707f
-#define MATCH_XPERM32 0x28000033
-#define MASK_XPERM32 0xfe00707f
-#define MATCH_ECALL 0x73
-#define MASK_ECALL 0xffffffff
-#define MATCH_EBREAK 0x100073
-#define MASK_EBREAK 0xffffffff
-#define MATCH_SRET 0x10200073
-#define MASK_SRET 0xffffffff
-#define MATCH_MRET 0x30200073
-#define MASK_MRET 0xffffffff
-#define MATCH_DRET 0x7b200073
-#define MASK_DRET 0xffffffff
-#define MATCH_SFENCE_VMA 0x12000073
-#define MASK_SFENCE_VMA 0xfe007fff
-#define MATCH_WFI 0x10500073
-#define MASK_WFI 0xffffffff
-#define MATCH_CSRRW 0x1073
-#define MASK_CSRRW 0x707f
-#define MATCH_CSRRS 0x2073
-#define MASK_CSRRS 0x707f
-#define MATCH_CSRRC 0x3073
-#define MASK_CSRRC 0x707f
-#define MATCH_CSRRWI 0x5073
-#define MASK_CSRRWI 0x707f
-#define MATCH_CSRRSI 0x6073
-#define MASK_CSRRSI 0x707f
-#define MATCH_CSRRCI 0x7073
-#define MASK_CSRRCI 0x707f
-#define MATCH_SINVAL_VMA 0x16000073
-#define MASK_SINVAL_VMA 0xfe007fff
-#define MATCH_SFENCE_W_INVAL 0x18000073
-#define MASK_SFENCE_W_INVAL 0xffffffff
-#define MATCH_SFENCE_INVAL_IR 0x18100073
-#define MASK_SFENCE_INVAL_IR 0xffffffff
-#define MATCH_HINVAL_VVMA 0x36000073
-#define MASK_HINVAL_VVMA 0xfe007fff
-#define MATCH_HINVAL_GVMA 0x76000073
-#define MASK_HINVAL_GVMA 0xfe007fff
-#define MATCH_FADD_H 0x4000053
-#define MASK_FADD_H 0xfe00007f
-#define MATCH_FSUB_H 0xc000053
-#define MASK_FSUB_H 0xfe00007f
-#define MATCH_FMUL_H 0x14000053
-#define MASK_FMUL_H 0xfe00007f
-#define MATCH_FDIV_H 0x1c000053
-#define MASK_FDIV_H 0xfe00007f
-#define MATCH_FSGNJ_H 0x24000053
-#define MASK_FSGNJ_H 0xfe00707f
-#define MATCH_FSGNJN_H 0x24001053
-#define MASK_FSGNJN_H 0xfe00707f
-#define MATCH_FSGNJX_H 0x24002053
-#define MASK_FSGNJX_H 0xfe00707f
-#define MATCH_FMIN_H 0x2c000053
-#define MASK_FMIN_H 0xfe00707f
-#define MATCH_FMAX_H 0x2c001053
-#define MASK_FMAX_H 0xfe00707f
-#define MATCH_FCVT_H_S 0x44000053
-#define MASK_FCVT_H_S 0xfff0007f
-#define MATCH_FCVT_S_H 0x40200053
-#define MASK_FCVT_S_H 0xfff0007f
-#define MATCH_FSQRT_H 0x5c000053
-#define MASK_FSQRT_H 0xfff0007f
-#define MATCH_FLE_H 0xa4000053
-#define MASK_FLE_H 0xfe00707f
-#define MATCH_FLT_H 0xa4001053
-#define MASK_FLT_H 0xfe00707f
-#define MATCH_FEQ_H 0xa4002053
-#define MASK_FEQ_H 0xfe00707f
-#define MATCH_FCVT_W_H 0xc4000053
-#define MASK_FCVT_W_H 0xfff0007f
-#define MATCH_FCVT_WU_H 0xc4100053
-#define MASK_FCVT_WU_H 0xfff0007f
-#define MATCH_FMV_X_H 0xe4000053
-#define MASK_FMV_X_H 0xfff0707f
-#define MATCH_FCLASS_H 0xe4001053
-#define MASK_FCLASS_H 0xfff0707f
-#define MATCH_FCVT_H_W 0xd4000053
-#define MASK_FCVT_H_W 0xfff0007f
-#define MATCH_FCVT_H_WU 0xd4100053
-#define MASK_FCVT_H_WU 0xfff0007f
-#define MATCH_FMV_H_X 0xf4000053
-#define MASK_FMV_H_X 0xfff0707f
-#define MATCH_FLH 0x1007
-#define MASK_FLH 0x707f
-#define MATCH_FSH 0x1027
-#define MASK_FSH 0x707f
-#define MATCH_FMADD_H 0x4000043
-#define MASK_FMADD_H 0x600007f
-#define MATCH_FMSUB_H 0x4000047
-#define MASK_FMSUB_H 0x600007f
-#define MATCH_FNMSUB_H 0x400004b
-#define MASK_FNMSUB_H 0x600007f
-#define MATCH_FNMADD_H 0x400004f
-#define MASK_FNMADD_H 0x600007f
-#define MATCH_FCVT_H_D 0x44100053
-#define MASK_FCVT_H_D 0xfff0007f
-#define MATCH_FCVT_D_H 0x42200053
-#define MASK_FCVT_D_H 0xfff0007f
-#define MATCH_FCVT_H_Q 0x44300053
-#define MASK_FCVT_H_Q 0xfff0007f
-#define MATCH_FCVT_Q_H 0x46200053
-#define MASK_FCVT_Q_H 0xfff0007f
-#define MATCH_FCVT_L_H 0xc4200053
-#define MASK_FCVT_L_H 0xfff0007f
-#define MATCH_FCVT_LU_H 0xc4300053
-#define MASK_FCVT_LU_H 0xfff0007f
-#define MATCH_FCVT_H_L 0xd4200053
-#define MASK_FCVT_H_L 0xfff0007f
-#define MATCH_FCVT_H_LU 0xd4300053
-#define MASK_FCVT_H_LU 0xfff0007f
-#define MATCH_SM4ED 0x30000033
-#define MASK_SM4ED 0x3e00707f
-#define MATCH_SM4KS 0x34000033
-#define MASK_SM4KS 0x3e00707f
-#define MATCH_SM3P0 0x10801013
-#define MASK_SM3P0 0xfff0707f
-#define MATCH_SM3P1 0x10901013
-#define MASK_SM3P1 0xfff0707f
-#define MATCH_SHA256SUM0 0x10001013
-#define MASK_SHA256SUM0 0xfff0707f
-#define MATCH_SHA256SUM1 0x10101013
-#define MASK_SHA256SUM1 0xfff0707f
-#define MATCH_SHA256SIG0 0x10201013
-#define MASK_SHA256SIG0 0xfff0707f
-#define MATCH_SHA256SIG1 0x10301013
-#define MASK_SHA256SIG1 0xfff0707f
-#define MATCH_AES32ESMI 0x26000033
-#define MASK_AES32ESMI 0x3e00707f
-#define MATCH_AES32ESI 0x22000033
-#define MASK_AES32ESI 0x3e00707f
-#define MATCH_AES32DSMI 0x2e000033
-#define MASK_AES32DSMI 0x3e00707f
-#define MATCH_AES32DSI 0x2a000033
-#define MASK_AES32DSI 0x3e00707f
-#define MATCH_SHA512SUM0R 0x50000033
-#define MASK_SHA512SUM0R 0xfe00707f
-#define MATCH_SHA512SUM1R 0x52000033
-#define MASK_SHA512SUM1R 0xfe00707f
-#define MATCH_SHA512SIG0L 0x54000033
-#define MASK_SHA512SIG0L 0xfe00707f
-#define MATCH_SHA512SIG0H 0x5c000033
-#define MASK_SHA512SIG0H 0xfe00707f
-#define MATCH_SHA512SIG1L 0x56000033
-#define MASK_SHA512SIG1L 0xfe00707f
-#define MATCH_SHA512SIG1H 0x5e000033
-#define MASK_SHA512SIG1H 0xfe00707f
-#define MATCH_AES64KS1I 0x31001013
-#define MASK_AES64KS1I 0xff00707f
-#define MATCH_AES64IM 0x30001013
-#define MASK_AES64IM 0xfff0707f
-#define MATCH_AES64KS2 0x7e000033
-#define MASK_AES64KS2 0xfe00707f
-#define MATCH_AES64ESM 0x36000033
-#define MASK_AES64ESM 0xfe00707f
-#define MATCH_AES64ES 0x32000033
-#define MASK_AES64ES 0xfe00707f
-#define MATCH_AES64DSM 0x3e000033
-#define MASK_AES64DSM 0xfe00707f
-#define MATCH_AES64DS 0x3a000033
-#define MASK_AES64DS 0xfe00707f
-#define MATCH_SHA512SUM0 0x10401013
-#define MASK_SHA512SUM0 0xfff0707f
-#define MATCH_SHA512SUM1 0x10501013
-#define MASK_SHA512SUM1 0xfff0707f
-#define MATCH_SHA512SIG0 0x10601013
-#define MASK_SHA512SIG0 0xfff0707f
-#define MATCH_SHA512SIG1 0x10701013
-#define MASK_SHA512SIG1 0xfff0707f
-#define MATCH_C_NOP 0x1
-#define MASK_C_NOP 0xffff
+#define MASK_BMATXOR 0xfe00707f
+#define MATCH_BNE 0x1063
+#define MASK_BNE 0x707f
+#define MATCH_BPICK 0x3077
+#define MASK_BPICK 0x600707f
+#define MATCH_BSET 0x28001033
+#define MASK_BSET 0xfe00707f
+#define MATCH_BSETI 0x28001013
+#define MASK_BSETI 0xfc00707f
+#define MATCH_C_ADD 0x9002
+#define MASK_C_ADD 0xf003
+#define MATCH_C_ADDI 0x1
+#define MASK_C_ADDI 0xe003
#define MATCH_C_ADDI16SP 0x6101
-#define MASK_C_ADDI16SP 0xef83
-#define MATCH_C_JR 0x8002
-#define MASK_C_JR 0xf07f
-#define MATCH_C_JALR 0x9002
-#define MASK_C_JALR 0xf07f
-#define MATCH_C_EBREAK 0x9002
-#define MASK_C_EBREAK 0xffff
+#define MASK_C_ADDI16SP 0xef83
#define MATCH_C_ADDI4SPN 0x0
-#define MASK_C_ADDI4SPN 0xe003
+#define MASK_C_ADDI4SPN 0xe003
+#define MATCH_C_ADDIW 0x2001
+#define MASK_C_ADDIW 0xe003
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW 0xfc63
+#define MATCH_C_AND 0x8c61
+#define MASK_C_AND 0xfc63
+#define MATCH_C_ANDI 0x8801
+#define MASK_C_ANDI 0xec03
+#define MATCH_C_BEQZ 0xc001
+#define MASK_C_BEQZ 0xe003
+#define MATCH_C_BNEZ 0xe001
+#define MASK_C_BNEZ 0xe003
+#define MATCH_C_EBREAK 0x9002
+#define MASK_C_EBREAK 0xffff
#define MATCH_C_FLD 0x2000
-#define MASK_C_FLD 0xe003
-#define MATCH_C_LW 0x4000
-#define MASK_C_LW 0xe003
+#define MASK_C_FLD 0xe003
+#define MATCH_C_FLDSP 0x2002
+#define MASK_C_FLDSP 0xe003
#define MATCH_C_FLW 0x6000
-#define MASK_C_FLW 0xe003
+#define MASK_C_FLW 0xe003
+#define MATCH_C_FLWSP 0x6002
+#define MASK_C_FLWSP 0xe003
#define MATCH_C_FSD 0xa000
-#define MASK_C_FSD 0xe003
-#define MATCH_C_SW 0xc000
-#define MASK_C_SW 0xe003
+#define MASK_C_FSD 0xe003
+#define MATCH_C_FSDSP 0xa002
+#define MASK_C_FSDSP 0xe003
#define MATCH_C_FSW 0xe000
-#define MASK_C_FSW 0xe003
-#define MATCH_C_ADDI 0x1
-#define MASK_C_ADDI 0xe003
+#define MASK_C_FSW 0xe003
+#define MATCH_C_FSWSP 0xe002
+#define MASK_C_FSWSP 0xe003
+#define MATCH_C_J 0xa001
+#define MASK_C_J 0xe003
#define MATCH_C_JAL 0x2001
-#define MASK_C_JAL 0xe003
+#define MASK_C_JAL 0xe003
+#define MATCH_C_JALR 0x9002
+#define MASK_C_JALR 0xf07f
+#define MATCH_C_JR 0x8002
+#define MASK_C_JR 0xf07f
+#define MATCH_C_LD 0x6000
+#define MASK_C_LD 0xe003
+#define MATCH_C_LDSP 0x6002
+#define MASK_C_LDSP 0xe003
#define MATCH_C_LI 0x4001
-#define MASK_C_LI 0xe003
+#define MASK_C_LI 0xe003
+#define MATCH_C_LQ 0x2000
+#define MASK_C_LQ 0xe003
+#define MATCH_C_LQSP 0x2002
+#define MASK_C_LQSP 0xe003
#define MATCH_C_LUI 0x6001
-#define MASK_C_LUI 0xe003
-#define MATCH_C_SRLI 0x8001
-#define MASK_C_SRLI 0xec03
-#define MATCH_C_SRAI 0x8401
-#define MASK_C_SRAI 0xec03
-#define MATCH_C_ANDI 0x8801
-#define MASK_C_ANDI 0xec03
-#define MATCH_C_SUB 0x8c01
-#define MASK_C_SUB 0xfc63
-#define MATCH_C_XOR 0x8c21
-#define MASK_C_XOR 0xfc63
-#define MATCH_C_OR 0x8c41
-#define MASK_C_OR 0xfc63
-#define MATCH_C_AND 0x8c61
-#define MASK_C_AND 0xfc63
-#define MATCH_C_J 0xa001
-#define MASK_C_J 0xe003
-#define MATCH_C_BEQZ 0xc001
-#define MASK_C_BEQZ 0xe003
-#define MATCH_C_BNEZ 0xe001
-#define MASK_C_BNEZ 0xe003
-#define MATCH_C_SLLI 0x2
-#define MASK_C_SLLI 0xe003
-#define MATCH_C_FLDSP 0x2002
-#define MASK_C_FLDSP 0xe003
+#define MASK_C_LUI 0xe003
+#define MATCH_C_LW 0x4000
+#define MASK_C_LW 0xe003
#define MATCH_C_LWSP 0x4002
-#define MASK_C_LWSP 0xe003
-#define MATCH_C_FLWSP 0x6002
-#define MASK_C_FLWSP 0xe003
+#define MASK_C_LWSP 0xe003
#define MATCH_C_MV 0x8002
-#define MASK_C_MV 0xf003
-#define MATCH_C_ADD 0x9002
-#define MASK_C_ADD 0xf003
-#define MATCH_C_FSDSP 0xa002
-#define MASK_C_FSDSP 0xe003
-#define MATCH_C_SWSP 0xc002
-#define MASK_C_SWSP 0xe003
-#define MATCH_C_FSWSP 0xe002
-#define MASK_C_FSWSP 0xe003
-#define MATCH_C_SRLI_RV32 0x8001
-#define MASK_C_SRLI_RV32 0xfc03
-#define MATCH_C_SRAI_RV32 0x8401
-#define MASK_C_SRAI_RV32 0xfc03
-#define MATCH_C_SLLI_RV32 0x2
-#define MASK_C_SLLI_RV32 0xf003
-#define MATCH_C_LD 0x6000
-#define MASK_C_LD 0xe003
+#define MASK_C_MV 0xf003
+#define MATCH_C_NOP 0x1
+#define MASK_C_NOP 0xef83
+#define MATCH_C_OR 0x8c41
+#define MASK_C_OR 0xfc63
#define MATCH_C_SD 0xe000
-#define MASK_C_SD 0xe003
-#define MATCH_C_SUBW 0x9c01
-#define MASK_C_SUBW 0xfc63
-#define MATCH_C_ADDW 0x9c21
-#define MASK_C_ADDW 0xfc63
-#define MATCH_C_ADDIW 0x2001
-#define MASK_C_ADDIW 0xe003
-#define MATCH_C_LDSP 0x6002
-#define MASK_C_LDSP 0xe003
+#define MASK_C_SD 0xe003
#define MATCH_C_SDSP 0xe002
-#define MASK_C_SDSP 0xe003
-#define MATCH_CUSTOM0 0xb
-#define MASK_CUSTOM0 0x707f
-#define MATCH_CUSTOM0_RS1 0x200b
-#define MASK_CUSTOM0_RS1 0x707f
-#define MATCH_CUSTOM0_RS1_RS2 0x300b
-#define MASK_CUSTOM0_RS1_RS2 0x707f
-#define MATCH_CUSTOM0_RD 0x400b
-#define MASK_CUSTOM0_RD 0x707f
-#define MATCH_CUSTOM0_RD_RS1 0x600b
-#define MASK_CUSTOM0_RD_RS1 0x707f
-#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
-#define MASK_CUSTOM0_RD_RS1_RS2 0x707f
-#define MATCH_CUSTOM1 0x2b
-#define MASK_CUSTOM1 0x707f
-#define MATCH_CUSTOM1_RS1 0x202b
-#define MASK_CUSTOM1_RS1 0x707f
-#define MATCH_CUSTOM1_RS1_RS2 0x302b
-#define MASK_CUSTOM1_RS1_RS2 0x707f
-#define MATCH_CUSTOM1_RD 0x402b
-#define MASK_CUSTOM1_RD 0x707f
-#define MATCH_CUSTOM1_RD_RS1 0x602b
-#define MASK_CUSTOM1_RD_RS1 0x707f
-#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
-#define MASK_CUSTOM1_RD_RS1_RS2 0x707f
-#define MATCH_CUSTOM2 0x5b
-#define MASK_CUSTOM2 0x707f
-#define MATCH_CUSTOM2_RS1 0x205b
-#define MASK_CUSTOM2_RS1 0x707f
-#define MATCH_CUSTOM2_RS1_RS2 0x305b
-#define MASK_CUSTOM2_RS1_RS2 0x707f
-#define MATCH_CUSTOM2_RD 0x405b
-#define MASK_CUSTOM2_RD 0x707f
-#define MATCH_CUSTOM2_RD_RS1 0x605b
-#define MASK_CUSTOM2_RD_RS1 0x707f
-#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
-#define MASK_CUSTOM2_RD_RS1_RS2 0x707f
-#define MATCH_CUSTOM3 0x7b
-#define MASK_CUSTOM3 0x707f
-#define MATCH_CUSTOM3_RS1 0x207b
-#define MASK_CUSTOM3_RS1 0x707f
-#define MATCH_CUSTOM3_RS1_RS2 0x307b
-#define MASK_CUSTOM3_RS1_RS2 0x707f
-#define MATCH_CUSTOM3_RD 0x407b
-#define MASK_CUSTOM3_RD 0x707f
-#define MATCH_CUSTOM3_RD_RS1 0x607b
-#define MASK_CUSTOM3_RD_RS1 0x707f
-#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
-#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
-#define MATCH_VSETIVLI 0xc0007057
-#define MASK_VSETIVLI 0xc000707f
-#define MATCH_VSETVLI 0x7057
-#define MASK_VSETVLI 0x8000707f
-#define MATCH_VSETVL 0x80007057
-#define MASK_VSETVL 0xfe00707f
-#define MATCH_VLM_V 0x2b00007
-#define MASK_VLM_V 0xfff0707f
-#define MATCH_VSM_V 0x2b00027
-#define MASK_VSM_V 0xfff0707f
-#define MATCH_VLE8_V 0x7
-#define MASK_VLE8_V 0x1df0707f
-#define MATCH_VLE16_V 0x5007
-#define MASK_VLE16_V 0x1df0707f
-#define MATCH_VLE32_V 0x6007
-#define MASK_VLE32_V 0x1df0707f
-#define MATCH_VLE64_V 0x7007
-#define MASK_VLE64_V 0x1df0707f
-#define MATCH_VLE128_V 0x10000007
-#define MASK_VLE128_V 0x1df0707f
-#define MATCH_VLE256_V 0x10005007
-#define MASK_VLE256_V 0x1df0707f
-#define MATCH_VLE512_V 0x10006007
-#define MASK_VLE512_V 0x1df0707f
-#define MATCH_VLE1024_V 0x10007007
-#define MASK_VLE1024_V 0x1df0707f
-#define MATCH_VSE8_V 0x27
-#define MASK_VSE8_V 0x1df0707f
-#define MATCH_VSE16_V 0x5027
-#define MASK_VSE16_V 0x1df0707f
-#define MATCH_VSE32_V 0x6027
-#define MASK_VSE32_V 0x1df0707f
-#define MATCH_VSE64_V 0x7027
-#define MASK_VSE64_V 0x1df0707f
-#define MATCH_VSE128_V 0x10000027
-#define MASK_VSE128_V 0x1df0707f
-#define MATCH_VSE256_V 0x10005027
-#define MASK_VSE256_V 0x1df0707f
-#define MATCH_VSE512_V 0x10006027
-#define MASK_VSE512_V 0x1df0707f
-#define MATCH_VSE1024_V 0x10007027
-#define MASK_VSE1024_V 0x1df0707f
-#define MATCH_VLUXEI8_V 0x4000007
-#define MASK_VLUXEI8_V 0x1c00707f
-#define MATCH_VLUXEI16_V 0x4005007
-#define MASK_VLUXEI16_V 0x1c00707f
-#define MATCH_VLUXEI32_V 0x4006007
-#define MASK_VLUXEI32_V 0x1c00707f
-#define MATCH_VLUXEI64_V 0x4007007
-#define MASK_VLUXEI64_V 0x1c00707f
-#define MATCH_VLUXEI128_V 0x14000007
-#define MASK_VLUXEI128_V 0x1c00707f
-#define MATCH_VLUXEI256_V 0x14005007
-#define MASK_VLUXEI256_V 0x1c00707f
-#define MATCH_VLUXEI512_V 0x14006007
-#define MASK_VLUXEI512_V 0x1c00707f
-#define MATCH_VLUXEI1024_V 0x14007007
-#define MASK_VLUXEI1024_V 0x1c00707f
-#define MATCH_VSUXEI8_V 0x4000027
-#define MASK_VSUXEI8_V 0x1c00707f
-#define MATCH_VSUXEI16_V 0x4005027
-#define MASK_VSUXEI16_V 0x1c00707f
-#define MATCH_VSUXEI32_V 0x4006027
-#define MASK_VSUXEI32_V 0x1c00707f
-#define MATCH_VSUXEI64_V 0x4007027
-#define MASK_VSUXEI64_V 0x1c00707f
-#define MATCH_VSUXEI128_V 0x14000027
-#define MASK_VSUXEI128_V 0x1c00707f
-#define MATCH_VSUXEI256_V 0x14005027
-#define MASK_VSUXEI256_V 0x1c00707f
-#define MATCH_VSUXEI512_V 0x14006027
-#define MASK_VSUXEI512_V 0x1c00707f
-#define MATCH_VSUXEI1024_V 0x14007027
-#define MASK_VSUXEI1024_V 0x1c00707f
-#define MATCH_VLSE8_V 0x8000007
-#define MASK_VLSE8_V 0x1c00707f
-#define MATCH_VLSE16_V 0x8005007
-#define MASK_VLSE16_V 0x1c00707f
-#define MATCH_VLSE32_V 0x8006007
-#define MASK_VLSE32_V 0x1c00707f
-#define MATCH_VLSE64_V 0x8007007
-#define MASK_VLSE64_V 0x1c00707f
-#define MATCH_VLSE128_V 0x18000007
-#define MASK_VLSE128_V 0x1c00707f
-#define MATCH_VLSE256_V 0x18005007
-#define MASK_VLSE256_V 0x1c00707f
-#define MATCH_VLSE512_V 0x18006007
-#define MASK_VLSE512_V 0x1c00707f
-#define MATCH_VLSE1024_V 0x18007007
-#define MASK_VLSE1024_V 0x1c00707f
-#define MATCH_VSSE8_V 0x8000027
-#define MASK_VSSE8_V 0x1c00707f
-#define MATCH_VSSE16_V 0x8005027
-#define MASK_VSSE16_V 0x1c00707f
-#define MATCH_VSSE32_V 0x8006027
-#define MASK_VSSE32_V 0x1c00707f
-#define MATCH_VSSE64_V 0x8007027
-#define MASK_VSSE64_V 0x1c00707f
-#define MATCH_VSSE128_V 0x18000027
-#define MASK_VSSE128_V 0x1c00707f
-#define MATCH_VSSE256_V 0x18005027
-#define MASK_VSSE256_V 0x1c00707f
-#define MATCH_VSSE512_V 0x18006027
-#define MASK_VSSE512_V 0x1c00707f
-#define MATCH_VSSE1024_V 0x18007027
-#define MASK_VSSE1024_V 0x1c00707f
-#define MATCH_VLOXEI8_V 0xc000007
-#define MASK_VLOXEI8_V 0x1c00707f
-#define MATCH_VLOXEI16_V 0xc005007
-#define MASK_VLOXEI16_V 0x1c00707f
-#define MATCH_VLOXEI32_V 0xc006007
-#define MASK_VLOXEI32_V 0x1c00707f
-#define MATCH_VLOXEI64_V 0xc007007
-#define MASK_VLOXEI64_V 0x1c00707f
-#define MATCH_VLOXEI128_V 0x1c000007
-#define MASK_VLOXEI128_V 0x1c00707f
-#define MATCH_VLOXEI256_V 0x1c005007
-#define MASK_VLOXEI256_V 0x1c00707f
-#define MATCH_VLOXEI512_V 0x1c006007
-#define MASK_VLOXEI512_V 0x1c00707f
-#define MATCH_VLOXEI1024_V 0x1c007007
-#define MASK_VLOXEI1024_V 0x1c00707f
-#define MATCH_VSOXEI8_V 0xc000027
-#define MASK_VSOXEI8_V 0x1c00707f
-#define MATCH_VSOXEI16_V 0xc005027
-#define MASK_VSOXEI16_V 0x1c00707f
-#define MATCH_VSOXEI32_V 0xc006027
-#define MASK_VSOXEI32_V 0x1c00707f
-#define MATCH_VSOXEI64_V 0xc007027
-#define MASK_VSOXEI64_V 0x1c00707f
-#define MATCH_VSOXEI128_V 0x1c000027
-#define MASK_VSOXEI128_V 0x1c00707f
-#define MATCH_VSOXEI256_V 0x1c005027
-#define MASK_VSOXEI256_V 0x1c00707f
-#define MATCH_VSOXEI512_V 0x1c006027
-#define MASK_VSOXEI512_V 0x1c00707f
-#define MATCH_VSOXEI1024_V 0x1c007027
-#define MASK_VSOXEI1024_V 0x1c00707f
-#define MATCH_VLE8FF_V 0x1000007
-#define MASK_VLE8FF_V 0x1df0707f
-#define MATCH_VLE16FF_V 0x1005007
-#define MASK_VLE16FF_V 0x1df0707f
-#define MATCH_VLE32FF_V 0x1006007
-#define MASK_VLE32FF_V 0x1df0707f
-#define MATCH_VLE64FF_V 0x1007007
-#define MASK_VLE64FF_V 0x1df0707f
-#define MATCH_VLE128FF_V 0x11000007
-#define MASK_VLE128FF_V 0x1df0707f
-#define MATCH_VLE256FF_V 0x11005007
-#define MASK_VLE256FF_V 0x1df0707f
-#define MATCH_VLE512FF_V 0x11006007
-#define MASK_VLE512FF_V 0x1df0707f
-#define MATCH_VLE1024FF_V 0x11007007
-#define MASK_VLE1024FF_V 0x1df0707f
-#define MATCH_VL1RE8_V 0x2800007
-#define MASK_VL1RE8_V 0xfff0707f
-#define MATCH_VL1RE16_V 0x2805007
-#define MASK_VL1RE16_V 0xfff0707f
-#define MATCH_VL1RE32_V 0x2806007
-#define MASK_VL1RE32_V 0xfff0707f
-#define MATCH_VL1RE64_V 0x2807007
-#define MASK_VL1RE64_V 0xfff0707f
-#define MATCH_VL2RE8_V 0x22800007
-#define MASK_VL2RE8_V 0xfff0707f
-#define MATCH_VL2RE16_V 0x22805007
-#define MASK_VL2RE16_V 0xfff0707f
-#define MATCH_VL2RE32_V 0x22806007
-#define MASK_VL2RE32_V 0xfff0707f
-#define MATCH_VL2RE64_V 0x22807007
-#define MASK_VL2RE64_V 0xfff0707f
-#define MATCH_VL4RE8_V 0x62800007
-#define MASK_VL4RE8_V 0xfff0707f
-#define MATCH_VL4RE16_V 0x62805007
-#define MASK_VL4RE16_V 0xfff0707f
-#define MATCH_VL4RE32_V 0x62806007
-#define MASK_VL4RE32_V 0xfff0707f
-#define MATCH_VL4RE64_V 0x62807007
-#define MASK_VL4RE64_V 0xfff0707f
-#define MATCH_VL8RE8_V 0xe2800007
-#define MASK_VL8RE8_V 0xfff0707f
-#define MATCH_VL8RE16_V 0xe2805007
-#define MASK_VL8RE16_V 0xfff0707f
-#define MATCH_VL8RE32_V 0xe2806007
-#define MASK_VL8RE32_V 0xfff0707f
-#define MATCH_VL8RE64_V 0xe2807007
-#define MASK_VL8RE64_V 0xfff0707f
-#define MATCH_VS1R_V 0x2800027
-#define MASK_VS1R_V 0xfff0707f
-#define MATCH_VS2R_V 0x22800027
-#define MASK_VS2R_V 0xfff0707f
-#define MATCH_VS4R_V 0x62800027
-#define MASK_VS4R_V 0xfff0707f
-#define MATCH_VS8R_V 0xe2800027
-#define MASK_VS8R_V 0xfff0707f
-#define MATCH_VFADD_VF 0x5057
-#define MASK_VFADD_VF 0xfc00707f
-#define MATCH_VFSUB_VF 0x8005057
-#define MASK_VFSUB_VF 0xfc00707f
-#define MATCH_VFMIN_VF 0x10005057
-#define MASK_VFMIN_VF 0xfc00707f
-#define MATCH_VFMAX_VF 0x18005057
-#define MASK_VFMAX_VF 0xfc00707f
-#define MATCH_VFSGNJ_VF 0x20005057
-#define MASK_VFSGNJ_VF 0xfc00707f
-#define MATCH_VFSGNJN_VF 0x24005057
-#define MASK_VFSGNJN_VF 0xfc00707f
-#define MATCH_VFSGNJX_VF 0x28005057
-#define MASK_VFSGNJX_VF 0xfc00707f
-#define MATCH_VFSLIDE1UP_VF 0x38005057
-#define MASK_VFSLIDE1UP_VF 0xfc00707f
-#define MATCH_VFSLIDE1DOWN_VF 0x3c005057
-#define MASK_VFSLIDE1DOWN_VF 0xfc00707f
-#define MATCH_VFMV_S_F 0x42005057
-#define MASK_VFMV_S_F 0xfff0707f
-#define MATCH_VFMERGE_VFM 0x5c005057
-#define MASK_VFMERGE_VFM 0xfe00707f
-#define MATCH_VFMV_V_F 0x5e005057
-#define MASK_VFMV_V_F 0xfff0707f
-#define MATCH_VMFEQ_VF 0x60005057
-#define MASK_VMFEQ_VF 0xfc00707f
-#define MATCH_VMFLE_VF 0x64005057
-#define MASK_VMFLE_VF 0xfc00707f
-#define MATCH_VMFLT_VF 0x6c005057
-#define MASK_VMFLT_VF 0xfc00707f
-#define MATCH_VMFNE_VF 0x70005057
-#define MASK_VMFNE_VF 0xfc00707f
-#define MATCH_VMFGT_VF 0x74005057
-#define MASK_VMFGT_VF 0xfc00707f
-#define MATCH_VMFGE_VF 0x7c005057
-#define MASK_VMFGE_VF 0xfc00707f
-#define MATCH_VFDIV_VF 0x80005057
-#define MASK_VFDIV_VF 0xfc00707f
-#define MATCH_VFRDIV_VF 0x84005057
-#define MASK_VFRDIV_VF 0xfc00707f
-#define MATCH_VFMUL_VF 0x90005057
-#define MASK_VFMUL_VF 0xfc00707f
-#define MATCH_VFRSUB_VF 0x9c005057
-#define MASK_VFRSUB_VF 0xfc00707f
-#define MATCH_VFMADD_VF 0xa0005057
-#define MASK_VFMADD_VF 0xfc00707f
-#define MATCH_VFNMADD_VF 0xa4005057
-#define MASK_VFNMADD_VF 0xfc00707f
-#define MATCH_VFMSUB_VF 0xa8005057
-#define MASK_VFMSUB_VF 0xfc00707f
-#define MATCH_VFNMSUB_VF 0xac005057
-#define MASK_VFNMSUB_VF 0xfc00707f
-#define MATCH_VFMACC_VF 0xb0005057
-#define MASK_VFMACC_VF 0xfc00707f
-#define MATCH_VFNMACC_VF 0xb4005057
-#define MASK_VFNMACC_VF 0xfc00707f
-#define MATCH_VFMSAC_VF 0xb8005057
-#define MASK_VFMSAC_VF 0xfc00707f
-#define MATCH_VFNMSAC_VF 0xbc005057
-#define MASK_VFNMSAC_VF 0xfc00707f
-#define MATCH_VFWADD_VF 0xc0005057
-#define MASK_VFWADD_VF 0xfc00707f
-#define MATCH_VFWSUB_VF 0xc8005057
-#define MASK_VFWSUB_VF 0xfc00707f
-#define MATCH_VFWADD_WF 0xd0005057
-#define MASK_VFWADD_WF 0xfc00707f
-#define MATCH_VFWSUB_WF 0xd8005057
-#define MASK_VFWSUB_WF 0xfc00707f
-#define MATCH_VFWMUL_VF 0xe0005057
-#define MASK_VFWMUL_VF 0xfc00707f
-#define MATCH_VFWMACC_VF 0xf0005057
-#define MASK_VFWMACC_VF 0xfc00707f
-#define MATCH_VFWNMACC_VF 0xf4005057
-#define MASK_VFWNMACC_VF 0xfc00707f
-#define MATCH_VFWMSAC_VF 0xf8005057
-#define MASK_VFWMSAC_VF 0xfc00707f
-#define MATCH_VFWNMSAC_VF 0xfc005057
-#define MASK_VFWNMSAC_VF 0xfc00707f
-#define MATCH_VFADD_VV 0x1057
-#define MASK_VFADD_VV 0xfc00707f
-#define MATCH_VFREDUSUM_VS 0x4001057
-#define MASK_VFREDUSUM_VS 0xfc00707f
-#define MATCH_VFSUB_VV 0x8001057
-#define MASK_VFSUB_VV 0xfc00707f
-#define MATCH_VFREDOSUM_VS 0xc001057
-#define MASK_VFREDOSUM_VS 0xfc00707f
-#define MATCH_VFMIN_VV 0x10001057
-#define MASK_VFMIN_VV 0xfc00707f
-#define MATCH_VFREDMIN_VS 0x14001057
-#define MASK_VFREDMIN_VS 0xfc00707f
-#define MATCH_VFMAX_VV 0x18001057
-#define MASK_VFMAX_VV 0xfc00707f
-#define MATCH_VFREDMAX_VS 0x1c001057
-#define MASK_VFREDMAX_VS 0xfc00707f
-#define MATCH_VFSGNJ_VV 0x20001057
-#define MASK_VFSGNJ_VV 0xfc00707f
-#define MATCH_VFSGNJN_VV 0x24001057
-#define MASK_VFSGNJN_VV 0xfc00707f
-#define MATCH_VFSGNJX_VV 0x28001057
-#define MASK_VFSGNJX_VV 0xfc00707f
-#define MATCH_VFMV_F_S 0x42001057
-#define MASK_VFMV_F_S 0xfe0ff07f
-#define MATCH_VMFEQ_VV 0x60001057
-#define MASK_VMFEQ_VV 0xfc00707f
-#define MATCH_VMFLE_VV 0x64001057
-#define MASK_VMFLE_VV 0xfc00707f
-#define MATCH_VMFLT_VV 0x6c001057
-#define MASK_VMFLT_VV 0xfc00707f
-#define MATCH_VMFNE_VV 0x70001057
-#define MASK_VMFNE_VV 0xfc00707f
-#define MATCH_VFDIV_VV 0x80001057
-#define MASK_VFDIV_VV 0xfc00707f
-#define MATCH_VFMUL_VV 0x90001057
-#define MASK_VFMUL_VV 0xfc00707f
-#define MATCH_VFMADD_VV 0xa0001057
-#define MASK_VFMADD_VV 0xfc00707f
-#define MATCH_VFNMADD_VV 0xa4001057
-#define MASK_VFNMADD_VV 0xfc00707f
-#define MATCH_VFMSUB_VV 0xa8001057
-#define MASK_VFMSUB_VV 0xfc00707f
-#define MATCH_VFNMSUB_VV 0xac001057
-#define MASK_VFNMSUB_VV 0xfc00707f
-#define MATCH_VFMACC_VV 0xb0001057
-#define MASK_VFMACC_VV 0xfc00707f
-#define MATCH_VFNMACC_VV 0xb4001057
-#define MASK_VFNMACC_VV 0xfc00707f
-#define MATCH_VFMSAC_VV 0xb8001057
-#define MASK_VFMSAC_VV 0xfc00707f
-#define MATCH_VFNMSAC_VV 0xbc001057
-#define MASK_VFNMSAC_VV 0xfc00707f
-#define MATCH_VFCVT_XU_F_V 0x48001057
-#define MASK_VFCVT_XU_F_V 0xfc0ff07f
-#define MATCH_VFCVT_X_F_V 0x48009057
-#define MASK_VFCVT_X_F_V 0xfc0ff07f
-#define MATCH_VFCVT_F_XU_V 0x48011057
-#define MASK_VFCVT_F_XU_V 0xfc0ff07f
-#define MATCH_VFCVT_F_X_V 0x48019057
-#define MASK_VFCVT_F_X_V 0xfc0ff07f
-#define MATCH_VFCVT_RTZ_XU_F_V 0x48031057
-#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f
-#define MATCH_VFCVT_RTZ_X_F_V 0x48039057
-#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f
-#define MATCH_VFWCVT_XU_F_V 0x48041057
-#define MASK_VFWCVT_XU_F_V 0xfc0ff07f
-#define MATCH_VFWCVT_X_F_V 0x48049057
-#define MASK_VFWCVT_X_F_V 0xfc0ff07f
-#define MATCH_VFWCVT_F_XU_V 0x48051057
-#define MASK_VFWCVT_F_XU_V 0xfc0ff07f
-#define MATCH_VFWCVT_F_X_V 0x48059057
-#define MASK_VFWCVT_F_X_V 0xfc0ff07f
-#define MATCH_VFWCVT_F_F_V 0x48061057
-#define MASK_VFWCVT_F_F_V 0xfc0ff07f
-#define MATCH_VFWCVT_RTZ_XU_F_V 0x48071057
-#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f
-#define MATCH_VFWCVT_RTZ_X_F_V 0x48079057
-#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f
-#define MATCH_VFNCVT_XU_F_W 0x48081057
-#define MASK_VFNCVT_XU_F_W 0xfc0ff07f
-#define MATCH_VFNCVT_X_F_W 0x48089057
-#define MASK_VFNCVT_X_F_W 0xfc0ff07f
-#define MATCH_VFNCVT_F_XU_W 0x48091057
-#define MASK_VFNCVT_F_XU_W 0xfc0ff07f
-#define MATCH_VFNCVT_F_X_W 0x48099057
-#define MASK_VFNCVT_F_X_W 0xfc0ff07f
-#define MATCH_VFNCVT_F_F_W 0x480a1057
-#define MASK_VFNCVT_F_F_W 0xfc0ff07f
-#define MATCH_VFNCVT_ROD_F_F_W 0x480a9057
-#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f
-#define MATCH_VFNCVT_RTZ_XU_F_W 0x480b1057
-#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f
-#define MATCH_VFNCVT_RTZ_X_F_W 0x480b9057
-#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f
-#define MATCH_VFSQRT_V 0x4c001057
-#define MASK_VFSQRT_V 0xfc0ff07f
-#define MATCH_VFRSQRT7_V 0x4c021057
-#define MASK_VFRSQRT7_V 0xfc0ff07f
-#define MATCH_VFREC7_V 0x4c029057
-#define MASK_VFREC7_V 0xfc0ff07f
-#define MATCH_VFCLASS_V 0x4c081057
-#define MASK_VFCLASS_V 0xfc0ff07f
-#define MATCH_VFWADD_VV 0xc0001057
-#define MASK_VFWADD_VV 0xfc00707f
-#define MATCH_VFWREDUSUM_VS 0xc4001057
-#define MASK_VFWREDUSUM_VS 0xfc00707f
-#define MATCH_VFWSUB_VV 0xc8001057
-#define MASK_VFWSUB_VV 0xfc00707f
-#define MATCH_VFWREDOSUM_VS 0xcc001057
-#define MASK_VFWREDOSUM_VS 0xfc00707f
-#define MATCH_VFWADD_WV 0xd0001057
-#define MASK_VFWADD_WV 0xfc00707f
-#define MATCH_VFWSUB_WV 0xd8001057
-#define MASK_VFWSUB_WV 0xfc00707f
-#define MATCH_VFWMUL_VV 0xe0001057
-#define MASK_VFWMUL_VV 0xfc00707f
-#define MATCH_VFWMACC_VV 0xf0001057
-#define MASK_VFWMACC_VV 0xfc00707f
-#define MATCH_VFWNMACC_VV 0xf4001057
-#define MASK_VFWNMACC_VV 0xfc00707f
-#define MATCH_VFWMSAC_VV 0xf8001057
-#define MASK_VFWMSAC_VV 0xfc00707f
-#define MATCH_VFWNMSAC_VV 0xfc001057
-#define MASK_VFWNMSAC_VV 0xfc00707f
-#define MATCH_VADD_VX 0x4057
-#define MASK_VADD_VX 0xfc00707f
-#define MATCH_VSUB_VX 0x8004057
-#define MASK_VSUB_VX 0xfc00707f
-#define MATCH_VRSUB_VX 0xc004057
-#define MASK_VRSUB_VX 0xfc00707f
-#define MATCH_VMINU_VX 0x10004057
-#define MASK_VMINU_VX 0xfc00707f
-#define MATCH_VMIN_VX 0x14004057
-#define MASK_VMIN_VX 0xfc00707f
-#define MATCH_VMAXU_VX 0x18004057
-#define MASK_VMAXU_VX 0xfc00707f
-#define MATCH_VMAX_VX 0x1c004057
-#define MASK_VMAX_VX 0xfc00707f
-#define MATCH_VAND_VX 0x24004057
-#define MASK_VAND_VX 0xfc00707f
-#define MATCH_VOR_VX 0x28004057
-#define MASK_VOR_VX 0xfc00707f
-#define MATCH_VXOR_VX 0x2c004057
-#define MASK_VXOR_VX 0xfc00707f
-#define MATCH_VRGATHER_VX 0x30004057
-#define MASK_VRGATHER_VX 0xfc00707f
-#define MATCH_VSLIDEUP_VX 0x38004057
-#define MASK_VSLIDEUP_VX 0xfc00707f
-#define MATCH_VSLIDEDOWN_VX 0x3c004057
-#define MASK_VSLIDEDOWN_VX 0xfc00707f
-#define MATCH_VADC_VXM 0x40004057
-#define MASK_VADC_VXM 0xfe00707f
-#define MATCH_VMADC_VXM 0x44004057
-#define MASK_VMADC_VXM 0xfe00707f
-#define MATCH_VMADC_VX 0x46004057
-#define MASK_VMADC_VX 0xfe00707f
-#define MATCH_VSBC_VXM 0x48004057
-#define MASK_VSBC_VXM 0xfe00707f
-#define MATCH_VMSBC_VXM 0x4c004057
-#define MASK_VMSBC_VXM 0xfe00707f
-#define MATCH_VMSBC_VX 0x4e004057
-#define MASK_VMSBC_VX 0xfe00707f
-#define MATCH_VMERGE_VXM 0x5c004057
-#define MASK_VMERGE_VXM 0xfe00707f
-#define MATCH_VMV_V_X 0x5e004057
-#define MASK_VMV_V_X 0xfff0707f
-#define MATCH_VMSEQ_VX 0x60004057
-#define MASK_VMSEQ_VX 0xfc00707f
-#define MATCH_VMSNE_VX 0x64004057
-#define MASK_VMSNE_VX 0xfc00707f
-#define MATCH_VMSLTU_VX 0x68004057
-#define MASK_VMSLTU_VX 0xfc00707f
-#define MATCH_VMSLT_VX 0x6c004057
-#define MASK_VMSLT_VX 0xfc00707f
-#define MATCH_VMSLEU_VX 0x70004057
-#define MASK_VMSLEU_VX 0xfc00707f
-#define MATCH_VMSLE_VX 0x74004057
-#define MASK_VMSLE_VX 0xfc00707f
-#define MATCH_VMSGTU_VX 0x78004057
-#define MASK_VMSGTU_VX 0xfc00707f
-#define MATCH_VMSGT_VX 0x7c004057
-#define MASK_VMSGT_VX 0xfc00707f
-#define MATCH_VSADDU_VX 0x80004057
-#define MASK_VSADDU_VX 0xfc00707f
-#define MATCH_VSADD_VX 0x84004057
-#define MASK_VSADD_VX 0xfc00707f
-#define MATCH_VSSUBU_VX 0x88004057
-#define MASK_VSSUBU_VX 0xfc00707f
-#define MATCH_VSSUB_VX 0x8c004057
-#define MASK_VSSUB_VX 0xfc00707f
-#define MATCH_VSLL_VX 0x94004057
-#define MASK_VSLL_VX 0xfc00707f
-#define MATCH_VSMUL_VX 0x9c004057
-#define MASK_VSMUL_VX 0xfc00707f
-#define MATCH_VSRL_VX 0xa0004057
-#define MASK_VSRL_VX 0xfc00707f
-#define MATCH_VSRA_VX 0xa4004057
-#define MASK_VSRA_VX 0xfc00707f
-#define MATCH_VSSRL_VX 0xa8004057
-#define MASK_VSSRL_VX 0xfc00707f
-#define MATCH_VSSRA_VX 0xac004057
-#define MASK_VSSRA_VX 0xfc00707f
-#define MATCH_VNSRL_WX 0xb0004057
-#define MASK_VNSRL_WX 0xfc00707f
-#define MATCH_VNSRA_WX 0xb4004057
-#define MASK_VNSRA_WX 0xfc00707f
-#define MATCH_VNCLIPU_WX 0xb8004057
-#define MASK_VNCLIPU_WX 0xfc00707f
-#define MATCH_VNCLIP_WX 0xbc004057
-#define MASK_VNCLIP_WX 0xfc00707f
-#define MATCH_VADD_VV 0x57
-#define MASK_VADD_VV 0xfc00707f
-#define MATCH_VSUB_VV 0x8000057
-#define MASK_VSUB_VV 0xfc00707f
-#define MATCH_VMINU_VV 0x10000057
-#define MASK_VMINU_VV 0xfc00707f
-#define MATCH_VMIN_VV 0x14000057
-#define MASK_VMIN_VV 0xfc00707f
-#define MATCH_VMAXU_VV 0x18000057
-#define MASK_VMAXU_VV 0xfc00707f
-#define MATCH_VMAX_VV 0x1c000057
-#define MASK_VMAX_VV 0xfc00707f
-#define MATCH_VAND_VV 0x24000057
-#define MASK_VAND_VV 0xfc00707f
-#define MATCH_VOR_VV 0x28000057
-#define MASK_VOR_VV 0xfc00707f
-#define MATCH_VXOR_VV 0x2c000057
-#define MASK_VXOR_VV 0xfc00707f
-#define MATCH_VRGATHER_VV 0x30000057
-#define MASK_VRGATHER_VV 0xfc00707f
-#define MATCH_VRGATHEREI16_VV 0x38000057
-#define MASK_VRGATHEREI16_VV 0xfc00707f
-#define MATCH_VADC_VVM 0x40000057
-#define MASK_VADC_VVM 0xfe00707f
-#define MATCH_VMADC_VVM 0x44000057
-#define MASK_VMADC_VVM 0xfe00707f
-#define MATCH_VMADC_VV 0x46000057
-#define MASK_VMADC_VV 0xfe00707f
-#define MATCH_VSBC_VVM 0x48000057
-#define MASK_VSBC_VVM 0xfe00707f
-#define MATCH_VMSBC_VVM 0x4c000057
-#define MASK_VMSBC_VVM 0xfe00707f
-#define MATCH_VMSBC_VV 0x4e000057
-#define MASK_VMSBC_VV 0xfe00707f
-#define MATCH_VMERGE_VVM 0x5c000057
-#define MASK_VMERGE_VVM 0xfe00707f
-#define MATCH_VMV_V_V 0x5e000057
-#define MASK_VMV_V_V 0xfff0707f
-#define MATCH_VMSEQ_VV 0x60000057
-#define MASK_VMSEQ_VV 0xfc00707f
-#define MATCH_VMSNE_VV 0x64000057
-#define MASK_VMSNE_VV 0xfc00707f
-#define MATCH_VMSLTU_VV 0x68000057
-#define MASK_VMSLTU_VV 0xfc00707f
-#define MATCH_VMSLT_VV 0x6c000057
-#define MASK_VMSLT_VV 0xfc00707f
-#define MATCH_VMSLEU_VV 0x70000057
-#define MASK_VMSLEU_VV 0xfc00707f
-#define MATCH_VMSLE_VV 0x74000057
-#define MASK_VMSLE_VV 0xfc00707f
-#define MATCH_VSADDU_VV 0x80000057
-#define MASK_VSADDU_VV 0xfc00707f
-#define MATCH_VSADD_VV 0x84000057
-#define MASK_VSADD_VV 0xfc00707f
-#define MATCH_VSSUBU_VV 0x88000057
-#define MASK_VSSUBU_VV 0xfc00707f
-#define MATCH_VSSUB_VV 0x8c000057
-#define MASK_VSSUB_VV 0xfc00707f
-#de...
[truncated message content] |
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-27 16:21:20
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via d93ac5482afc97a0c712ec16716a8f6ecc10fdfa (commit)
from d8307ed46037f4c7b5f4ce99991485bf08edce4e (commit)
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- Log -----------------------------------------------------------------
commit d93ac5482afc97a0c712ec16716a8f6ecc10fdfa
Author: Ian Thompson <ia...@ca...>
Date: Sun Aug 21 15:56:41 2022 -0700
target/xtensa: fix clang analyzer warnings
Scan-build of target/xtensa/ has no clang analyzer warnings from xtensa source files.
Signed-off-by: Ian Thompson <ia...@ca...>
Change-Id: I11a125c923ece9a6fd0d9ee1698f742f88ee5cab
Reviewed-on: https://review.openocd.org/c/openocd/+/7141
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index 4e18e3eb4..2fd2c7ca5 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -2608,6 +2608,7 @@ static int xtensa_gdbqc_qxtreg(struct target *target, const char *packet, char *
goto xtensa_gdbqc_qxtreg_fail;
}
uint8_t regbuf[XT_QUERYPKT_RESP_MAX];
+ memset(regbuf, 0, XT_QUERYPKT_RESP_MAX);
LOG_DEBUG("TIE reg 0x%08" PRIx32 " %s (%d bytes)", regnum, iswrite ? "write" : "read", reglen);
if (reglen * 2 + 1 > XT_QUERYPKT_RESP_MAX) {
LOG_ERROR("TIE register too large");
@@ -2990,6 +2991,7 @@ COMMAND_HELPER(xtensa_cmd_exe_do, struct target *target)
}
uint8_t ops[32];
+ memset(ops, 0, 32);
unsigned int oplen = parm_len / 2;
char encoded_byte[3] = { 0, 0, 0 };
for (unsigned int i = 0; i < oplen; i++) {
-----------------------------------------------------------------------
Summary of changes:
src/target/xtensa/xtensa.c | 2 ++
1 file changed, 2 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-27 16:20:39
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via d8307ed46037f4c7b5f4ce99991485bf08edce4e (commit)
from 50f80530c55a044be88bb90a574959e920e7be82 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit d8307ed46037f4c7b5f4ce99991485bf08edce4e
Author: Tomas Vanek <va...@fb...>
Date: Wed Aug 17 12:24:41 2022 +0200
flash/nor/bluenrg-x: clarify target algo stack usage
While on it rename misleading write_algorithm_sp to write_algorithm_stack
and change messages referring 'stack pointer' instead of stack.
No functional change.
Change-Id: Ibb9897d3f01734812ed0f8bc8cd43b935a573f8a
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7132
Tested-by: jenkins
Reviewed-by: Salvatore Giorgio Pecorino <sal...@st...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/bluenrg-x.c b/src/flash/nor/bluenrg-x.c
index d4fb5e972..ec5cae76e 100644
--- a/src/flash/nor/bluenrg-x.c
+++ b/src/flash/nor/bluenrg-x.c
@@ -236,7 +236,7 @@ static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer,
struct target *target = bank->target;
uint32_t buffer_size = 16384 + 8;
struct working_area *write_algorithm;
- struct working_area *write_algorithm_sp;
+ struct working_area *write_algorithm_stack;
struct working_area *source;
uint32_t address = bank->base + offset;
struct reg_param reg_params[5];
@@ -285,10 +285,10 @@ static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer,
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
- /* Stack pointer area */
+ /* Stack area */
if (target_alloc_working_area(target, 128,
- &write_algorithm_sp) != ERROR_OK) {
- LOG_DEBUG("no working area for write code stack pointer");
+ &write_algorithm_stack) != ERROR_OK) {
+ LOG_DEBUG("no working area for target algorithm stack");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@@ -300,8 +300,19 @@ static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer,
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
init_reg_param(®_params[4], "sp", 32, PARAM_OUT);
- /* Put the parameter at the first available stack location */
- init_mem_param(&mem_params[0], write_algorithm_sp->address + 80, 32, PARAM_OUT);
+ /* Put the 4th parameter at the location in the stack frame of target write() function.
+ * See contrib/loaders/flash/bluenrg-x/bluenrg-x_write.lst
+ * 34 ldr r6, [sp, #80]
+ * ^^^ offset
+ */
+ init_mem_param(&mem_params[0], write_algorithm_stack->address + 80, 32, PARAM_OUT);
+ /* Stack for target write algorithm - target write() function has
+ * __attribute__((naked)) so it does not setup the new stack frame.
+ * Therefore the stack frame uses the area from SP upwards!
+ * Interrupts are disabled and no subroutines are called from write()
+ * so no need to allocate stack below SP.
+ * TODO: remove __attribute__((naked)) and use similar parameter passing as stm32l4x */
+ buf_set_u32(reg_params[4].value, 0, 32, write_algorithm_stack->address);
/* FIFO start address (first two words used for write and read pointers) */
buf_set_u32(reg_params[0].value, 0, 32, source->address);
@@ -311,14 +322,12 @@ static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer,
buf_set_u32(reg_params[2].value, 0, 32, address);
/* Number of bytes */
buf_set_u32(reg_params[3].value, 0, 32, count);
- /* Stack pointer for program working area */
- buf_set_u32(reg_params[4].value, 0, 32, write_algorithm_sp->address);
/* Flash register base address */
buf_set_u32(mem_params[0].value, 0, 32, bluenrgx_info->flash_ptr->flash_regs_base);
LOG_DEBUG("source->address = " TARGET_ADDR_FMT, source->address);
LOG_DEBUG("source->address+ source->size = " TARGET_ADDR_FMT, source->address+source->size);
- LOG_DEBUG("write_algorithm_sp->address = " TARGET_ADDR_FMT, write_algorithm_sp->address);
+ LOG_DEBUG("write_algorithm_stack->address = " TARGET_ADDR_FMT, write_algorithm_stack->address);
LOG_DEBUG("address = %08" PRIx32, address);
LOG_DEBUG("count = %08" PRIx32, count);
@@ -357,7 +366,7 @@ static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer,
}
target_free_working_area(target, source);
target_free_working_area(target, write_algorithm);
- target_free_working_area(target, write_algorithm_sp);
+ target_free_working_area(target, write_algorithm_stack);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/bluenrg-x.c | 29 +++++++++++++++++++----------
1 file changed, 19 insertions(+), 10 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-27 16:20:13
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 50f80530c55a044be88bb90a574959e920e7be82 (commit)
from 60396be0b6a7b5ad45e0724b860dabc2b7c6f378 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 50f80530c55a044be88bb90a574959e920e7be82
Author: Tomas Vanek <va...@fb...>
Date: Wed Aug 17 10:42:47 2022 +0200
flash/nor/nrf5: don't misuse uint32_t for refcount
Change-Id: I016fc9ae037fae75528850d35da059d1db5a4d45
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7131
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index 23b221cb3..9d2565b01 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -136,7 +136,7 @@ struct nrf5_device_spec {
};
struct nrf5_info {
- uint32_t refcount;
+ unsigned int refcount;
struct nrf5_bank {
struct nrf5_info *chip;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/nrf5.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-27 16:19:49
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 60396be0b6a7b5ad45e0724b860dabc2b7c6f378 (commit)
from 7bc4e67d65367d214fbdef6514eb2fa29c541475 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 60396be0b6a7b5ad45e0724b860dabc2b7c6f378
Author: Tomas Vanek <va...@fb...>
Date: Tue Aug 16 14:10:26 2022 +0200
flash/nor/core: remove unused define
FLASH_MAX_ERROR_STR is not used since commit 815c3b353307
(merged in ~2008)
Change-Id: Ic117a2e3d22235c31dc14533b6564ebf5a13ae58
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7121
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/core.h b/src/flash/nor/core.h
index 0c09e9875..8c26ba012 100644
--- a/src/flash/nor/core.h
+++ b/src/flash/nor/core.h
@@ -20,8 +20,6 @@
struct image;
-#define FLASH_MAX_ERROR_STR (128)
-
/**
* Describes the geometry and status of a single flash sector
* within a flash bank. A single bank typically consists of multiple
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/core.h | 2 --
1 file changed, 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-27 16:19:13
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 7bc4e67d65367d214fbdef6514eb2fa29c541475 (commit)
from 424f9f67964b01ce39c3cedfc2e189770c11a8bc (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 7bc4e67d65367d214fbdef6514eb2fa29c541475
Author: Antonio Borneo <bor...@gm...>
Date: Tue Aug 16 11:42:32 2022 +0200
flash/nor: remove empty command definitions
The value of struct flash_driver::command can be NULL when the
flash driver does not need to add any new command.
Remove empty command definitions.
Change-Id: I5413967d4069030234469822d24e9825425ae012
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7120
Reviewed-by: Tomas Vanek <va...@fb...>
Tested-by: jenkins
diff --git a/src/flash/nor/fm4.c b/src/flash/nor/fm4.c
index 2881f1201..3a362d888 100644
--- a/src/flash/nor/fm4.c
+++ b/src/flash/nor/fm4.c
@@ -688,24 +688,8 @@ FLASH_BANK_COMMAND_HANDLER(fm4_flash_bank_command)
return ret;
}
-static const struct command_registration fm4_exec_command_handlers[] = {
- COMMAND_REGISTRATION_DONE
-};
-
-static const struct command_registration fm4_command_handlers[] = {
- {
- .name = "fm4",
- .mode = COMMAND_ANY,
- .help = "fm4 flash command group",
- .usage = "",
- .chain = fm4_exec_command_handlers,
- },
- COMMAND_REGISTRATION_DONE
-};
-
const struct flash_driver fm4_flash = {
.name = "fm4",
- .commands = fm4_command_handlers,
.flash_bank_command = fm4_flash_bank_command,
.info = fm4_get_info_command,
.probe = fm4_probe,
diff --git a/src/flash/nor/psoc5lp.c b/src/flash/nor/psoc5lp.c
index a8265bc23..b546b0aa0 100644
--- a/src/flash/nor/psoc5lp.c
+++ b/src/flash/nor/psoc5lp.c
@@ -811,24 +811,8 @@ FLASH_BANK_COMMAND_HANDLER(psoc5lp_nvl_flash_bank_command)
return ERROR_OK;
}
-static const struct command_registration psoc5lp_nvl_exec_command_handlers[] = {
- COMMAND_REGISTRATION_DONE
-};
-
-static const struct command_registration psoc5lp_nvl_command_handlers[] = {
- {
- .name = "psoc5lp_nvl",
- .mode = COMMAND_ANY,
- .help = "PSoC 5LP NV Latch command group",
- .usage = "",
- .chain = psoc5lp_nvl_exec_command_handlers,
- },
- COMMAND_REGISTRATION_DONE
-};
-
const struct flash_driver psoc5lp_nvl_flash = {
.name = "psoc5lp_nvl",
- .commands = psoc5lp_nvl_command_handlers,
.flash_bank_command = psoc5lp_nvl_flash_bank_command,
.info = psoc5lp_nvl_get_info_command,
.probe = psoc5lp_nvl_probe,
@@ -1010,24 +994,8 @@ FLASH_BANK_COMMAND_HANDLER(psoc5lp_eeprom_flash_bank_command)
return ERROR_OK;
}
-static const struct command_registration psoc5lp_eeprom_exec_command_handlers[] = {
- COMMAND_REGISTRATION_DONE
-};
-
-static const struct command_registration psoc5lp_eeprom_command_handlers[] = {
- {
- .name = "psoc5lp_eeprom",
- .mode = COMMAND_ANY,
- .help = "PSoC 5LP EEPROM command group",
- .usage = "",
- .chain = psoc5lp_eeprom_exec_command_handlers,
- },
- COMMAND_REGISTRATION_DONE
-};
-
const struct flash_driver psoc5lp_eeprom_flash = {
.name = "psoc5lp_eeprom",
- .commands = psoc5lp_eeprom_command_handlers,
.flash_bank_command = psoc5lp_eeprom_flash_bank_command,
.info = psoc5lp_eeprom_get_info_command,
.probe = psoc5lp_eeprom_probe,
diff --git a/src/flash/nor/xmc1xxx.c b/src/flash/nor/xmc1xxx.c
index 70e07fcfa..04a39f36e 100644
--- a/src/flash/nor/xmc1xxx.c
+++ b/src/flash/nor/xmc1xxx.c
@@ -520,24 +520,8 @@ FLASH_BANK_COMMAND_HANDLER(xmc1xxx_flash_bank_command)
return ERROR_OK;
}
-static const struct command_registration xmc1xxx_exec_command_handlers[] = {
- COMMAND_REGISTRATION_DONE
-};
-
-static const struct command_registration xmc1xxx_command_handlers[] = {
- {
- .name = "xmc1xxx",
- .mode = COMMAND_ANY,
- .help = "xmc1xxx flash command group",
- .usage = "",
- .chain = xmc1xxx_exec_command_handlers,
- },
- COMMAND_REGISTRATION_DONE
-};
-
const struct flash_driver xmc1xxx_flash = {
.name = "xmc1xxx",
- .commands = xmc1xxx_command_handlers,
.flash_bank_command = xmc1xxx_flash_bank_command,
.info = xmc1xxx_get_info_command,
.probe = xmc1xxx_probe,
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/fm4.c | 16 ----------------
src/flash/nor/psoc5lp.c | 32 --------------------------------
src/flash/nor/xmc1xxx.c | 16 ----------------
3 files changed, 64 deletions(-)
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2022-08-27 16:18:43
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 424f9f67964b01ce39c3cedfc2e189770c11a8bc
Author: Antonio Borneo <bor...@gm...>
Date: Thu May 5 17:23:49 2022 +0200
doc: how to use QEMU to test big-endian build
Document the process of using buildroot to build a big-endian
binary of OpenOCD and using QEMU User Mode Emulation for running
the big-endian binary on a little-endian host PC.
Change-Id: Ic5fe26e353a4cf69e57af3c23ae7fa4b25347b2b
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6968
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/contrib/buildroot/openocd_be_defconfig b/contrib/buildroot/openocd_be_defconfig
new file mode 100644
index 000000000..9752da50e
--- /dev/null
+++ b/contrib/buildroot/openocd_be_defconfig
@@ -0,0 +1,27 @@
+BR2_armeb=y
+BR2_cortex_a7=y
+BR2_TOOLCHAIN_EXTERNAL=y
+BR2_PACKAGE_OPENOCD=y
+BR2_PACKAGE_OPENOCD_FTDI=y
+BR2_PACKAGE_OPENOCD_STLINK=y
+BR2_PACKAGE_OPENOCD_TI_ICDI=y
+BR2_PACKAGE_OPENOCD_ULINK=y
+BR2_PACKAGE_OPENOCD_UBLASTER2=y
+BR2_PACKAGE_OPENOCD_JLINK=y
+BR2_PACKAGE_OPENOCD_OSDBM=y
+BR2_PACKAGE_OPENOCD_OPENDOUS=y
+BR2_PACKAGE_OPENOCD_AICE=y
+BR2_PACKAGE_OPENOCD_VSLLINK=y
+BR2_PACKAGE_OPENOCD_USBPROG=y
+BR2_PACKAGE_OPENOCD_RLINK=y
+BR2_PACKAGE_OPENOCD_ARMEW=y
+BR2_PACKAGE_OPENOCD_XDS110=y
+BR2_PACKAGE_OPENOCD_PARPORT=y
+BR2_PACKAGE_OPENOCD_VPI=y
+BR2_PACKAGE_OPENOCD_UBLASTER=y
+BR2_PACKAGE_OPENOCD_AMTJT=y
+BR2_PACKAGE_OPENOCD_GW16012=y
+BR2_PACKAGE_OPENOCD_PRESTO=y
+BR2_PACKAGE_OPENOCD_OPENJTAG=y
+BR2_PACKAGE_OPENOCD_BUSPIRATE=y
+BR2_PACKAGE_OPENOCD_SYSFS=y
diff --git a/doc/manual/endianness.txt b/doc/manual/endianness.txt
new file mode 100644
index 000000000..bba2116b5
--- /dev/null
+++ b/doc/manual/endianness.txt
@@ -0,0 +1,197 @@
+/** @page endianness About endianness
+
+OpenOCD has to potentially deal with different endianness between:
+- the host PC endianness;
+- the data endianness during communication between host and adapter;
+- the target CPU endianness.
+
+The whole OpenOCD code should be written to handle any endianness
+mismatch and should run on either little and big endian hosts.
+
+Big-endian host PC are becoming less and less common since Apple™ has
+switched away from big-endian PowerPC™ in favor of little-endian intel
+X86™.
+
+The lack of commercial big-endian hosts makes hard testing OpenOCD correctness
+on big-endian hosts. Running OpenOCD on low-cost commercial routers based on
+big-endian MIPS is possible, but it's tricky to properly setup the system and
+the cross-compiling environment.
+
+In next sections there are two example on how to compile and test OpenOCD in an
+emulated big-endian environment.
+
+
+@section endianness_helpers OpenOCD API for handling endianness
+
+Use the following OpenOCD API to handle endianness conversions:
+- host endianness to/from little endian:
+ - le_to_h_u64(), le_to_h_u32(), le_to_h_u16();
+ - h_u64_to_le(), h_u32_to_le(), h_u16_to_le();
+ - buf_get_u32(), buf_get_u64();
+ - buf_set_u32(), buf_set_u64();
+- host endianness to/from big endian:
+ - be_to_h_u64(), be_to_h_u32(), be_to_h_u16();
+ - h_u64_to_be(), h_u32_to_be(), h_u16_to_be();
+- host endianness to/from target endianness:
+ - target_read_u64(), target_read_u32(), target_read_u16();
+ - target_write_u64(), target_write_u32(), target_write_u16();
+ - target_write_phys_u64(), target_write_phys_u32(), target_write_phys_u16();
+ - target_buffer_get_u64(), target_buffer_get_u32(), target_buffer_get_u24(), target_buffer_get_u16();
+ - target_buffer_set_u64(), target_buffer_set_u32(), target_buffer_set_u24(), target_buffer_set_u16();
+- byte swap:
+ - buf_bswap32(), buf_bswap16().
+
+
+@section endianness_docker Use dockers to run different endianness
+
+
+Docker can run a full Linux image that includes the toolchain through QEMU
+emulator.
+By selecting a big-endian image, it's possible to compile and execute OpenOCD
+in big-endian.
+There are, so far, not many options for big-endian images; s390x is one of the
+few available.
+
+To be expanded.
+
+User should:
+- install docker;
+- download the big-endian image;
+- run the image in docker;
+- download, in the image, the OpenOCD code to test;
+- recompile OpenOCD code in the image;
+- run OpenOCD binary in the image.
+
+From https://github.com/multiarch/qemu-user-static
+
+ @code{.unparsed}
+ docker run --rm -t s390x/ubuntu bash
+ @endcode
+
+
+@section endianness_qemu Use buildroot and QEMU to run different endianness
+
+QEMU User Mode Emulation is an efficient method to launch, on host's CPU,
+applications compiled for another CPU and/or for different endianness.
+It works either on Linux and BSD. More info available on
+https://www.qemu.org/docs/master/user/index.html
+
+With QEMU User Mode Emulation is thus possible running, on a commonly available
+little-endian X86 Linux host, OpenOCD compiled for a big-endian host.
+
+The following example will show how to use buildroot to:
+- build big-endian toolchain and libraries;
+- compile OpenOCD for big-endian;
+- run the big-endian OpenOCD on little-endian Linux PC.
+
+The example will use ARM Cortex-A7 big-endian only because I personally feel
+comfortable reading ARM assembly during debug. User can select other CPU
+architectures, as this does not impact the result.
+
+A similar method can be used to test OpenOCD compiled for 32 vs 64 bit host.
+
+@note
+- the version of autotools locally installer in your Linux host can be
+ incompatible with the version of autotools used by buildroot. This can cause
+ the build to fail if buildroot has to run its autotools on a partially
+ configured OpenOCD folder. Use either a clean copy of OpenOCD code in 2., or
+ run "./bootstrap" in OpenOCD folder to prevent buildroot from using its own
+ autotools;
+- the configuration tool in 4. and 5. matches the version of OpenOCD used by
+ buildroot. Some new driver could be not listed in. OpenOCD will build every
+ driver that is not disabled and with satisfied dependencies. If the driver
+ you plan to use is not listed, try a first build and check OpenOCD with
+ command "adapter list", then try to hack the buildroot files Config.in and
+ openocd.mk in folder package/openocd/ and use "make openocd-reconfigure" to
+ rerun the build starting with configuration;
+- using pre-built toolchains, you need 2GB of disk space for buildroot build.
+ To also rebuild the toolchains you will need ~5GB and much longer time for
+ the first build (it takes ~2 hour on my crap 10+ years old laptop);
+- you need to install few tools for buildroot dependency, listed in
+ https://buildroot.org/downloads/manual/manual.html#requirement ;
+- you need to install qemu-armeb. On Arch Linux it's in package qemu-arch-extra;
+ on Ubuntu/debian it's packaged in qemu-user.
+ Buildroot can also be configured to build qemu for the host, if you prefer,
+ by enabling BR2_PACKAGE_HOST_QEMU_LINUX_USER_MODE, but this takes longer
+ compile time;
+- don't use qemu-system-arm, as it emulates a complete system and requires a
+ fully bootable ARM image;
+- while QEMU User Mode Emulation is available for both Linux and BSD, buildroot
+ only builds binaries for Linux target. This example can only be used with
+ Linux hosts emulating the Linux target.
+
+
+Steps to run big-endian OpenOCD on little-endian host Linux PC:
+
+1. Get buildroot source. Today's latest version is "2022.02":
+ @code{.unparsed}
+ wget https://buildroot.org/downloads/buildroot-2022.02.tar.xz
+ tar xf buildroot-2022.02.tar.xz
+ cd buildroot-2022.02
+ @endcode
+
+2. Override the source repo for OpenOCD in order to build your own code version
+ in place of the default OpenOCD release version:
+ @code{.unparsed}
+ echo OPENOCD_OVERRIDE_SRCDIR=/home/me/openocd.git >> local.mk
+ @endcode
+
+3. Copy default config for OpenOCD big-endian. This used:
+ - ARM Cortex-A7 big-endian target,
+ - external Linaro armeb toolchain (to speed up first build),
+ - OpenOCD all configure options enabled.
+
+ @code{.unparsed}
+ cp $OPENOCD_OVERRIDE_SRCDIR/contrib/buildroot/openocd_be_defconfig configs/
+ @endcode
+
+4. Configure buildroot with default config for OpenOCD big-endian:
+ @code{.unparsed}
+ make openocd_be_defconfig
+ @endcode
+
+5. Optional, change buildroot configuration:
+ @code{.unparsed}
+ make menuconfig
+ @endcode
+ These are the options selected with default config for OpenOCD big-endian:
+ @code{.unparsed}
+ Target options --->
+ Target Architecture --->
+ ARM (big endian)
+ Target Architecture Variant --->
+ cortex-A7
+ Toolchain --->
+ Toolchain type --->
+ External toolchain
+ Toolchain --->
+ Linaro armeb 2018.05
+ Toolchain origin --->
+ Toolchain to be downloaded and installed
+ Target packages --->
+ Hardware handling --->
+ openocd
+ All adapters selected
+ @endcode
+ Save and exit
+
+6. Build (and take a long coffee break ...):
+ @code{.unparsed}
+ make openocd
+ @endcode
+
+7. Execute big-endian OpenOCD:
+ @code{.unparsed}
+ cd output/target
+ qemu-armeb -cpu cortex-a7 -L . usr/bin/openocd -s usr/share/openocd/scripts/ -f board/st_nucleo_f4.cfg
+ @endcode
+
+8. Optional, to rebuild after any source code modification in ${OPENOCD_OVERRIDE_SRCDIR}:
+ @code{.unparsed}
+ make openocd-rebuild
+ @endcode
+
+ */
+/** @file
+This file contains the @ref endianness page.
+ */
diff --git a/doc/manual/main.txt b/doc/manual/main.txt
index 14c64c2e7..c28fbe228 100644
--- a/doc/manual/main.txt
+++ b/doc/manual/main.txt
@@ -19,6 +19,8 @@ check the mailing list archives to find the status of your feature (or bug).
- The @subpage bugs page contains the content of the BUGS file, which
provides instructions for submitting bug reports to the maintainers.
- The @subpage releases page describes the project's release process.
+- The @subpage endianness provides hints about writing and testing
+ endianness independent code for OpenOCD.
@ref primer provide introductory materials for new developers on various
specific topics.
-----------------------------------------------------------------------
Summary of changes:
contrib/buildroot/openocd_be_defconfig | 27 +++++
doc/manual/endianness.txt | 197 +++++++++++++++++++++++++++++++++
doc/manual/main.txt | 2 +
3 files changed, 226 insertions(+)
create mode 100644 contrib/buildroot/openocd_be_defconfig
create mode 100644 doc/manual/endianness.txt
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-27 16:18:25
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 63cc08f6a2a50f78a51075991537fa9fa34f378d (commit)
from 386155419bfd9a47d896dfe23dbda19f8a4cf2d0 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 63cc08f6a2a50f78a51075991537fa9fa34f378d
Author: Tomas Vanek <va...@fb...>
Date: Mon Aug 15 19:18:18 2022 +0200
server/server: fix target timer timing
The change 6363: Call poll at a fixed interval
switched from target_call_timer_callbacks() to target_call_timer_callbacks_now().
It breaks the timing as all timers callbacks are called every time
one timer expires.
Revert this part of change and use target_call_timer_callbacks().
Fixes: db16b3dc5b06 (Call poll at a fixed interval.)
Change-Id: Ib5b7774de9694d40c55d2a4109d0d1582fc5008b
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7118
Tested-by: jenkins
Reviewed-by: Tim Newsome <ti...@si...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/server/server.c b/src/server/server.c
index eeaa3d750..6542200d2 100644
--- a/src/server/server.c
+++ b/src/server/server.c
@@ -473,7 +473,7 @@ int server_loop(struct command_context *command_context)
tv.tv_usec = 0;
retval = socket_select(fd_max + 1, &read_fds, NULL, NULL, &tv);
} else {
- /* Every 100ms, can be changed with "poll_period" command */
+ /* Timeout socket_select() when a target timer expires or every polling_period */
int timeout_ms = next_event - timeval_ms();
if (timeout_ms < 0)
timeout_ms = 0;
@@ -507,9 +507,12 @@ int server_loop(struct command_context *command_context)
}
if (retval == 0) {
- /* We only execute these callbacks when there was nothing to do or we timed
- *out */
- target_call_timer_callbacks_now();
+ /* Execute callbacks of expired timers when
+ * - there was nothing to do if poll_ok was true
+ * - socket_select() timed out if poll_ok was false, now one or more
+ * timers expired or the polling period elapsed
+ */
+ target_call_timer_callbacks();
next_event = target_timer_next_event();
process_jim_events(command_context);
-----------------------------------------------------------------------
Summary of changes:
src/server/server.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-27 16:16:57
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from 09ca11066b568497cc2a191e9fedbf08673c15c6 (commit)
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- Log -----------------------------------------------------------------
commit 386155419bfd9a47d896dfe23dbda19f8a4cf2d0
Author: Antonio Borneo <bor...@gm...>
Date: Sat Apr 23 16:14:15 2022 +0200
tcl/target: stm32[fl]4x: document the settings for trace
While reviewing on gerrit the change
https://review.openocd.org/6932/
it get clear that the missing documentation on stm32f4x's code
was triggering errors in the new change.
OpenOCD is currently unable to read traces, but these can be
hopefully be read with some other tool.
Document the settings for enabling trace on stm32[fl]4x.
Change-Id: Ibae77a53de16375d3d500e728678740095547009
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6945
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index befd28863..35d8275b5 100644
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -100,18 +100,21 @@ proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
if { [$_chipname.tpiu cget -protocol] eq "sync" } {
switch [$_chipname.tpiu cget -port-width] {
1 {
+ # Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0
mmw 0xE0042004 0x00000060 0x000000c0
mmw 0x40021020 0x00000000 0x0000ff00
mmw 0x40021000 0x000000a0 0x000000f0
mmw 0x40021008 0x000000f0 0x00000000
}
2 {
+ # Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0
mmw 0xE0042004 0x000000a0 0x000000c0
mmw 0x40021020 0x00000000 0x000fff00
mmw 0x40021000 0x000002a0 0x000003f0
mmw 0x40021008 0x000003f0 0x00000000
}
4 {
+ # Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0
mmw 0xE0042004 0x000000e0 0x000000c0
mmw 0x40021020 0x00000000 0x0fffff00
mmw 0x40021000 0x00002aa0 0x00003ff0
@@ -119,6 +122,7 @@ proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
}
}
} else {
+ # Set TRACE_IOEN; TRACE_MODE to async
mmw 0xE0042004 0x00000020 0x000000c0
}
}
diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg
index 61d25b7c3..9a696736c 100644
--- a/tcl/target/stm32l4x.cfg
+++ b/tcl/target/stm32l4x.cfg
@@ -110,18 +110,21 @@ proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
if { [$_chipname.tpiu cget -protocol] eq "sync" } {
switch [$_chipname.tpiu cget -port-width] {
1 {
+ # Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0
mmw 0xE0042004 0x00000060 0x000000c0
mmw 0x48001020 0x00000000 0x0000ff00
mmw 0x48001000 0x000000a0 0x000000f0
mmw 0x48001008 0x000000f0 0x00000000
}
2 {
+ # Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0
mmw 0xE0042004 0x000000a0 0x000000c0
mmw 0x48001020 0x00000000 0x000fff00
mmw 0x48001000 0x000002a0 0x000003f0
mmw 0x48001008 0x000003f0 0x00000000
}
4 {
+ # Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0
mmw 0xE0042004 0x000000e0 0x000000c0
mmw 0x48001020 0x00000000 0x0fffff00
mmw 0x48001000 0x00002aa0 0x00003ff0
@@ -129,6 +132,7 @@ proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
}
}
} else {
+ # Set TRACE_IOEN; TRACE_MODE to async
mmw 0xE0042004 0x00000020 0x000000c0
}
}
-----------------------------------------------------------------------
Summary of changes:
tcl/target/stm32f4x.cfg | 4 ++++
tcl/target/stm32l4x.cfg | 4 ++++
2 files changed, 8 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-27 16:16:09
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 09ca11066b568497cc2a191e9fedbf08673c15c6 (commit)
from 65de7c95f41e78746dc41e6173bbee4106a758f9 (commit)
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- Log -----------------------------------------------------------------
commit 09ca11066b568497cc2a191e9fedbf08673c15c6
Author: Antonio Borneo <bor...@gm...>
Date: Mon Nov 8 20:14:46 2021 +0100
tcl/target: replace event trace-config
With commit dc7b32ea4a00 ("armv7m_trace: get rid of the old tpiu
code") the target's event "trace-config" has been deprecated.
Create the TPIU device.
Replace the target's event "trace-config" with tpiu's event
"pre-enable" in the STM32 devices that require enabling the trace
clock _before_ programming the TPIU.
Make the script multi-instance-able in case it's used for JTAG
chained devices.
Uniform the code in STM32F4x with the other scripts.
Remove the empty event from STM32WLx.
Change-Id: Ifda219c3c5f37e03072a88168611cf505eb630b7
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6681
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg
index 4c4ff25f2..53e81a59f 100644
--- a/tcl/target/stm32f1x.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -83,9 +83,16 @@ $_TARGETNAME configure -event examine-end {
mmw 0xE0042004 0x00000307 0
}
-$_TARGETNAME configure -event trace-config {
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+ targets $_targetname
+
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0
}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg
index a20941d12..f47582648 100644
--- a/tcl/target/stm32f2x.cfg
+++ b/tcl/target/stm32f2x.cfg
@@ -83,9 +83,16 @@ $_TARGETNAME configure -event examine-end {
mmw 0xE0042008 0x00001800 0
}
-$_TARGETNAME configure -event trace-config {
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+ targets $_targetname
+
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0
}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index ebec04f85..4ecc7eda3 100644
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -103,9 +103,16 @@ $_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
$_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
$_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }
-$_TARGETNAME configure -event trace-config {
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+ targets $_targetname
+
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xe0042004 0x00000020 0
}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index 5be0cf505..befd28863 100644
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -40,8 +40,6 @@ if { [info exists CPUTAPID] } {
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
-
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5
}
@@ -93,7 +91,10 @@ $_TARGETNAME configure -event examine-end {
mmw 0xE0042008 0x00001800 0
}
-proc proc_post_enable {_chipname} {
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
targets $_chipname.cpu
if { [$_chipname.tpiu cget -protocol] eq "sync" } {
@@ -122,7 +123,7 @@ proc proc_post_enable {_chipname} {
}
}
-$_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME"
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME"
$_TARGETNAME configure -event reset-init {
# Configure PLL to boost clock to HSI x 4 (64 MHz)
diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg
index 92cf30e0b..3782b9a9c 100644
--- a/tcl/target/stm32f7x.cfg
+++ b/tcl/target/stm32f7x.cfg
@@ -109,13 +109,20 @@ $_TARGETNAME configure -event examine-end {
mmw 0xE0042008 0x00001800 0
}
-$_TARGETNAME configure -event trace-config {
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+ targets $_targetname
+
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0
}
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
+
$_TARGETNAME configure -event reset-init {
# If the HSE was previously enabled and the external clock source
# disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be
diff --git a/tcl/target/stm32g4x.cfg b/tcl/target/stm32g4x.cfg
index 04cc9447c..39ed1e381 100644
--- a/tcl/target/stm32g4x.cfg
+++ b/tcl/target/stm32g4x.cfg
@@ -97,9 +97,16 @@ $_TARGETNAME configure -event examine-end {
mmw 0xE0042008 0x00001800 0
}
-$_TARGETNAME configure -event trace-config {
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+ targets $_targetname
+
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0
}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/tcl/target/stm32l1.cfg b/tcl/target/stm32l1.cfg
index 91360d829..53d9076e1 100644
--- a/tcl/target/stm32l1.cfg
+++ b/tcl/target/stm32l1.cfg
@@ -101,9 +101,16 @@ $_TARGETNAME configure -event examine-end {
mmw 0xE0042008 0x00001800 0
}
-$_TARGETNAME configure -event trace-config {
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+ targets $_targetname
+
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0
}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg
index dabdacd41..61d25b7c3 100644
--- a/tcl/target/stm32l4x.cfg
+++ b/tcl/target/stm32l4x.cfg
@@ -40,8 +40,6 @@ if { [info exists CPUTAPID] } {
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
-
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5
}
@@ -103,7 +101,10 @@ $_TARGETNAME configure -event examine-end {
mmw 0xE0042008 0x00001800 0
}
-proc proc_post_enable {_chipname} {
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
targets $_chipname.cpu
if { [$_chipname.tpiu cget -protocol] eq "sync" } {
@@ -132,7 +133,7 @@ proc proc_post_enable {_chipname} {
}
}
-$_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME"
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME"
$_TARGETNAME configure -event reset-init {
# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
diff --git a/tcl/target/stm32wbx.cfg b/tcl/target/stm32wbx.cfg
index 0c5b76148..737b1447c 100644
--- a/tcl/target/stm32wbx.cfg
+++ b/tcl/target/stm32wbx.cfg
@@ -97,9 +97,16 @@ $_TARGETNAME configure -event examine-end {
mmw 0xE004203C 0x00001800 0
}
-$_TARGETNAME configure -event trace-config {
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+ targets $_targetname
+
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0
}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/tcl/target/stm32wlx.cfg b/tcl/target/stm32wlx.cfg
index 81e590f25..39c897fc5 100644
--- a/tcl/target/stm32wlx.cfg
+++ b/tcl/target/stm32wlx.cfg
@@ -119,9 +119,7 @@ $_CHIPNAME.cpu0 configure -event examine-end {
}
}
-$_CHIPNAME.cpu0 configure -event trace-config {
- # nothing to do
-}
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
if {[set $_CHIPNAME.DUAL_CORE]} {
target create $_CHIPNAME.cpu1 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
diff --git a/tcl/target/stm32x5x_common.cfg b/tcl/target/stm32x5x_common.cfg
index 276d0cca0..c506e224b 100644
--- a/tcl/target/stm32x5x_common.cfg
+++ b/tcl/target/stm32x5x_common.cfg
@@ -146,9 +146,16 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
$_TARGETNAME configure -work-area-phys $workarea_addr
}
-$_TARGETNAME configure -event trace-config {
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+ targets $_targetname
+
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0044004 0x00000020 0
}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
-----------------------------------------------------------------------
Summary of changes:
tcl/target/stm32f1x.cfg | 9 ++++++++-
tcl/target/stm32f2x.cfg | 9 ++++++++-
tcl/target/stm32f3x.cfg | 9 ++++++++-
tcl/target/stm32f4x.cfg | 9 +++++----
tcl/target/stm32f7x.cfg | 9 ++++++++-
tcl/target/stm32g4x.cfg | 9 ++++++++-
tcl/target/stm32l1.cfg | 9 ++++++++-
tcl/target/stm32l4x.cfg | 9 +++++----
tcl/target/stm32wbx.cfg | 9 ++++++++-
tcl/target/stm32wlx.cfg | 4 +---
tcl/target/stm32x5x_common.cfg | 9 ++++++++-
11 files changed, 75 insertions(+), 19 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-27 16:15:22
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 65de7c95f41e78746dc41e6173bbee4106a758f9 (commit)
via 1a9d9916193ee7884d942b6119163557edc8dad2 (commit)
from 66d6f9a1e7c977faed71cf7fef977124a5edee7e (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 65de7c95f41e78746dc41e6173bbee4106a758f9
Author: Tomas Vanek <va...@fb...>
Date: Tue Aug 2 09:16:21 2022 +0200
jtag/drivers/kitprog: workaround serious firmware problem
Since commit 88f429ead019fd6df96ec15f0d897385f3cef0d0
5321: target/cortex_m: faster reading of all CPU registers
debugging with a kitprog adapter freezes at debug entry.
How to replicate:
openocd -f interface/kitprog.cfg -f target/psoc4.cfg
Connect to telnet server.
Make sure the target is running:
resume
Halt the target:
halt
Without this patch OpenOCD freezes in kitprog_hid_command()
in library call hid_write().
Reduce the number of SWD transactions sent in one USB bulk write
as a workaround, simply use shorter buffer.
For details see the comment in src/jtag/drivers/kitprog.c
Change-Id: I0116894d5ebf1655f6011f0d35acdbbc178cd48c
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7107
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/kitprog.c b/src/jtag/drivers/kitprog.c
index 7122d5757..f800b7b92 100644
--- a/src/jtag/drivers/kitprog.c
+++ b/src/jtag/drivers/kitprog.c
@@ -79,8 +79,24 @@
#define HID_COMMAND_CONFIGURE 0x8f
#define HID_COMMAND_BOOTLOADER 0xa0
-/* 512 bytes seems to work reliably */
-#define SWD_MAX_BUFFER_LENGTH 512
+/* 512 bytes seemed to work reliably.
+ * It works with both full queue of mostly reads or mostly writes.
+ *
+ * Unfortunately the commit 88f429ead019fd6df96ec15f0d897385f3cef0d0
+ * 5321: target/cortex_m: faster reading of all CPU registers
+ * revealed a serious Kitprog firmware problem:
+ * If the queue contains more than 63 transactions in the repeated pattern
+ * one write, two reads, the firmware fails badly.
+ * Sending 64 transactions makes the adapter to loose the connection with the
+ * device. Sending 65 or more transactions causes the adapter to stop
+ * receiving USB HID commands, next kitprog_hid_command() stops in hid_write().
+ *
+ * The problem was detected with KitProg v2.12 and v2.16.
+ * We can guess the problem is something like a buffer or stack overflow.
+ *
+ * Use shorter buffer as a workaround. 300 bytes (= 60 transactions) works.
+ */
+#define SWD_MAX_BUFFER_LENGTH 300
struct kitprog {
hid_device *hid_handle;
commit 1a9d9916193ee7884d942b6119163557edc8dad2
Author: Tomas Vanek <va...@fb...>
Date: Mon Aug 1 23:16:47 2022 +0200
jtag/drivers/kitprog: use HID read timeout
Use hid_read_timeout() instead of hid_read().
Improve error messages.
Change-Id: Ia75b4fcd610442ab926bc454341f928d59843fcf
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7106
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/kitprog.c b/src/jtag/drivers/kitprog.c
index 0956d3aa6..7122d5757 100644
--- a/src/jtag/drivers/kitprog.c
+++ b/src/jtag/drivers/kitprog.c
@@ -321,9 +321,13 @@ static int kitprog_hid_command(uint8_t *command, size_t command_length,
return ERROR_FAIL;
}
- ret = hid_read(kitprog_handle->hid_handle, data, data_length);
- if (ret < 0) {
- LOG_DEBUG("HID read returned %i", ret);
+ ret = hid_read_timeout(kitprog_handle->hid_handle,
+ data, data_length, LIBUSB_TIMEOUT_MS);
+ if (ret == 0) {
+ LOG_ERROR("HID read timed out");
+ return ERROR_TIMEOUT_REACHED;
+ } else if (ret < 0) {
+ LOG_ERROR("HID read error %ls", hid_error(kitprog_handle->hid_handle));
return ERROR_FAIL;
}
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/kitprog.c | 30 +++++++++++++++++++++++++-----
1 file changed, 25 insertions(+), 5 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-27 16:13:34
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 66d6f9a1e7c977faed71cf7fef977124a5edee7e (commit)
from f77c919cf4dd25d3540bdef7d0bf60f5b84d5dd6 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 66d6f9a1e7c977faed71cf7fef977124a5edee7e
Author: Paul Fertser <fer...@gm...>
Date: Sat Aug 7 21:55:30 2021 +0300
flash: nor: use binary prefixes consistently
When printing memory sizes standard ISO 80000-1 prefixes should be used.
Also a space should be added between any number and its unit according
to papers publication rules.
Change-Id: Id1d35e210766b55c201de4e80ac165d8d0414d0a
Signed-off-by: Paul Fertser <fer...@gm...>
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6416
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 54fdbd8cb..04b03c7d9 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -1075,8 +1075,8 @@ static int efm32x_probe(struct flash_bank *bank)
LOG_INFO("detected part: %s Gecko, rev %d",
efm32_mcu_info->family_data->name, efm32_mcu_info->prod_rev);
- LOG_INFO("flash size = %dkbytes", efm32_mcu_info->flash_sz_kib);
- LOG_INFO("flash page size = %dbytes", efm32_mcu_info->page_size);
+ LOG_INFO("flash size = %d KiB", efm32_mcu_info->flash_sz_kib);
+ LOG_INFO("flash page size = %d B", efm32_mcu_info->page_size);
assert(efm32_mcu_info->page_size != 0);
diff --git a/src/flash/nor/em357.c b/src/flash/nor/em357.c
index d73194bc6..63302f68a 100644
--- a/src/flash/nor/em357.c
+++ b/src/flash/nor/em357.c
@@ -709,7 +709,7 @@ static int em357_probe(struct flash_bank *bank)
em357_info->ppage_size = 4;
- LOG_INFO("flash size = %dkbytes", num_pages*page_size/1024);
+ LOG_INFO("flash size = %d KiB", num_pages*page_size/1024);
free(bank->sectors);
diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c
index 12e3f5fb9..61e7b17ab 100644
--- a/src/flash/nor/kinetis.c
+++ b/src/flash/nor/kinetis.c
@@ -2662,12 +2662,12 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip)
snprintf(k_chip->name, sizeof(k_chip->name), name, flash_marking);
LOG_INFO("Kinetis %s detected: %u flash blocks", k_chip->name, num_blocks);
- LOG_INFO("%u PFlash banks: %" PRIu32 "k total", k_chip->num_pflash_blocks, pflash_size_k);
+ LOG_INFO("%u PFlash banks: %" PRIu32 " KiB total", k_chip->num_pflash_blocks, pflash_size_k);
if (k_chip->num_nvm_blocks) {
nvm_size_k = k_chip->nvm_size / 1024;
dflash_size_k = k_chip->dflash_size / 1024;
- LOG_INFO("%u FlexNVM banks: %" PRIu32 "k total, %" PRIu32 "k available as data flash, %" PRIu32 "bytes FlexRAM",
- k_chip->num_nvm_blocks, nvm_size_k, dflash_size_k, ee_size);
+ LOG_INFO("%u FlexNVM banks: %" PRIu32 " KiB total, %" PRIu32 " KiB available as data flash, %"
+ PRIu32 " bytes FlexRAM", k_chip->num_nvm_blocks, nvm_size_k, dflash_size_k, ee_size);
}
k_chip->probed = true;
diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c
index 960fb8d25..aacafa123 100644
--- a/src/flash/nor/pic32mx.c
+++ b/src/flash/nor/pic32mx.c
@@ -759,7 +759,7 @@ static int pic32mx_probe(struct flash_bank *bank)
}
}
- LOG_INFO("flash size = %" PRIu32 "kbytes", num_pages / 1024);
+ LOG_INFO("flash size = %" PRIu32 " KiB", num_pages / 1024);
free(bank->sectors);
diff --git a/src/flash/nor/psoc4.c b/src/flash/nor/psoc4.c
index 1bdd64aae..8ca1a7cfa 100644
--- a/src/flash/nor/psoc4.c
+++ b/src/flash/nor/psoc4.c
@@ -774,7 +774,7 @@ static int psoc4_probe(struct flash_bank *bank)
num_macros++;
}
- LOG_DEBUG("SPCIF geometry: %" PRIu32 " kb flash, row %" PRIu32 " bytes.",
+ LOG_DEBUG("SPCIF geometry: %" PRIu32 " KiB flash, row %" PRIu32 " bytes.",
flash_size_in_kb, row_size);
/* if the user sets the size manually then ignore the probed value
@@ -788,7 +788,7 @@ static int psoc4_probe(struct flash_bank *bank)
if (num_macros > 1)
snprintf(macros_txt, sizeof(macros_txt), " in %" PRIu32 " macros", num_macros);
- LOG_INFO("flash size = %" PRIu32 " kbytes%s", flash_size_in_kb, macros_txt);
+ LOG_INFO("flash size = %" PRIu32 " KiB%s", flash_size_in_kb, macros_txt);
/* calculate number of pages */
uint32_t num_rows = flash_size_in_kb * 1024 / row_size;
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index 455a06a9b..b00b70ac2 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -1006,7 +1006,7 @@ static int stm32x_probe(struct flash_bank *bank)
flash_size_in_kb = stm32x_info->user_bank_size / 1024;
}
- LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
+ LOG_INFO("flash size = %d KiB", flash_size_in_kb);
/* did we assign flash size? */
assert(flash_size_in_kb != 0xffff);
diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c
index 5e95b9b6b..7b3f9305d 100644
--- a/src/flash/nor/stm32f2x.c
+++ b/src/flash/nor/stm32f2x.c
@@ -1125,7 +1125,7 @@ static int stm32x_probe(struct flash_bank *bank)
flash_size_in_kb = stm32x_info->user_bank_size / 1024;
}
- LOG_INFO("flash size = %" PRIu16 " kbytes", flash_size_in_kb);
+ LOG_INFO("flash size = %" PRIu16 " KiB", flash_size_in_kb);
/* did we assign flash size? */
assert(flash_size_in_kb != 0xffff);
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index 2b428f032..6cb75884e 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -1816,7 +1816,7 @@ static int stm32l4_probe(struct flash_bank *bank)
flash_size_kb = stm32l4_info->user_bank_size / 1024;
}
- LOG_INFO("flash size = %dkbytes", flash_size_kb);
+ LOG_INFO("flash size = %d KiB", flash_size_kb);
/* did we assign a flash size? */
assert((flash_size_kb != 0xffff) && flash_size_kb);
diff --git a/src/flash/nor/stmqspi.c b/src/flash/nor/stmqspi.c
index a5332482f..ca4d51338 100644
--- a/src/flash/nor/stmqspi.c
+++ b/src/flash/nor/stmqspi.c
@@ -754,13 +754,13 @@ COMMAND_HANDLER(stmqspi_handle_set)
bank->sectors = sectors;
stmqspi_info->dev.name = stmqspi_info->devname;
if (stmqspi_info->dev.size_in_bytes / 4096)
- LOG_INFO("flash \'%s\' id = unknown\nchip size = %" PRIu32 "kbytes,"
- " bank size = %" PRIu32 "kbytes", stmqspi_info->dev.name,
+ LOG_INFO("flash \'%s\' id = unknown\nchip size = %" PRIu32 " KiB,"
+ " bank size = %" PRIu32 " KiB", stmqspi_info->dev.name,
stmqspi_info->dev.size_in_bytes / 1024,
(stmqspi_info->dev.size_in_bytes / 1024) << dual);
else
- LOG_INFO("flash \'%s\' id = unknown\nchip size = %" PRIu32 "bytes,"
- " bank size = %" PRIu32 "bytes", stmqspi_info->dev.name,
+ LOG_INFO("flash \'%s\' id = unknown\nchip size = %" PRIu32 " B,"
+ " bank size = %" PRIu32 " B", stmqspi_info->dev.name,
stmqspi_info->dev.size_in_bytes,
stmqspi_info->dev.size_in_bytes << dual);
@@ -2206,10 +2206,10 @@ static int stmqspi_probe(struct flash_bank *bank)
memcpy(&stmqspi_info->dev, p, sizeof(stmqspi_info->dev));
if (p->size_in_bytes / 4096)
LOG_INFO("flash1 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
- "kbytes", p->name, id1, p->size_in_bytes / 1024);
+ " KiB", p->name, id1, p->size_in_bytes / 1024);
else
LOG_INFO("flash1 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
- "bytes", p->name, id1, p->size_in_bytes);
+ " B", p->name, id1, p->size_in_bytes);
break;
}
}
@@ -2228,7 +2228,7 @@ static int stmqspi_probe(struct flash_bank *bank)
if (retval == ERROR_OK) {
LOG_INFO("flash1 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
- "kbytes", temp.name, id1, temp.size_in_bytes / 1024);
+ " KiB", temp.name, id1, temp.size_in_bytes / 1024);
/* save info and retrieved *good* id as spi_sfdp clears all info */
memcpy(&stmqspi_info->dev, &temp, sizeof(stmqspi_info->dev));
stmqspi_info->dev.device_id = id1;
@@ -2246,10 +2246,10 @@ static int stmqspi_probe(struct flash_bank *bank)
if (p->device_id == id2) {
if (p->size_in_bytes / 4096)
LOG_INFO("flash2 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
- "kbytes", p->name, id2, p->size_in_bytes / 1024);
+ " KiB", p->name, id2, p->size_in_bytes / 1024);
else
LOG_INFO("flash2 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
- "bytes", p->name, id2, p->size_in_bytes);
+ " B", p->name, id2, p->size_in_bytes);
if (!id1)
memcpy(&stmqspi_info->dev, p, sizeof(stmqspi_info->dev));
@@ -2286,7 +2286,7 @@ static int stmqspi_probe(struct flash_bank *bank)
if (retval == ERROR_OK)
LOG_INFO("flash2 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
- "kbytes", temp.name, id2, temp.size_in_bytes / 1024);
+ " KiB", temp.name, id2, temp.size_in_bytes / 1024);
else {
/* even not identified by SFDP, then give up */
LOG_WARNING("Unknown flash2 device id = 0x%06" PRIx32
@@ -2392,22 +2392,22 @@ static int get_stmqspi_info(struct flash_bank *bank, struct command_invocation *
}
command_print_sameline(cmd, "flash%s%s \'%s\', device id = 0x%06" PRIx32
- ", flash size = %" PRIu32 "%sbytes\n(page size = %" PRIu32
+ ", flash size = %" PRIu32 "%s B\n(page size = %" PRIu32
", read = 0x%02" PRIx8 ", qread = 0x%02" PRIx8
", pprog = 0x%02" PRIx8 ", mass_erase = 0x%02" PRIx8
- ", sector size = %" PRIu32 "%sbytes, sector_erase = 0x%02" PRIx8 ")",
+ ", sector size = %" PRIu32 " %sB, sector_erase = 0x%02" PRIx8 ")",
((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
BIT(SPI_FSEL_FLASH))) != BIT(SPI_FSEL_FLASH)) ? "1" : "",
((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
BIT(SPI_FSEL_FLASH))) != 0) ? "2" : "",
stmqspi_info->dev.name, stmqspi_info->dev.device_id,
bank->size / 4096 ? bank->size / 1024 : bank->size,
- bank->size / 4096 ? "k" : "", stmqspi_info->dev.pagesize,
+ bank->size / 4096 ? "Ki" : "", stmqspi_info->dev.pagesize,
stmqspi_info->dev.read_cmd, stmqspi_info->dev.qread_cmd,
stmqspi_info->dev.pprog_cmd, stmqspi_info->dev.chip_erase_cmd,
stmqspi_info->dev.sectorsize / 4096 ?
stmqspi_info->dev.sectorsize / 1024 : stmqspi_info->dev.sectorsize,
- stmqspi_info->dev.sectorsize / 4096 ? "k" : "",
+ stmqspi_info->dev.sectorsize / 4096 ? "Ki" : "",
stmqspi_info->dev.erase_cmd);
return ERROR_OK;
diff --git a/src/flash/nor/w600.c b/src/flash/nor/w600.c
index 52105bd6d..98c0f46e5 100644
--- a/src/flash/nor/w600.c
+++ b/src/flash/nor/w600.c
@@ -312,7 +312,7 @@ static int w600_probe(struct flash_bank *bank)
flash_size = 1 << flash_size;
}
- LOG_INFO("flash size = %" PRIu32 "kbytes", flash_size / 1024);
+ LOG_INFO("flash size = %" PRIu32 " KiB", flash_size / 1024);
/* calculate numbers of pages */
size_t num_pages = flash_size / W600_FLASH_SECSIZE;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/efm32.c | 4 ++--
src/flash/nor/em357.c | 2 +-
src/flash/nor/kinetis.c | 6 +++---
src/flash/nor/pic32mx.c | 2 +-
src/flash/nor/psoc4.c | 4 ++--
src/flash/nor/stm32f1x.c | 2 +-
src/flash/nor/stm32f2x.c | 2 +-
src/flash/nor/stm32l4x.c | 2 +-
src/flash/nor/stmqspi.c | 28 ++++++++++++++--------------
src/flash/nor/w600.c | 2 +-
10 files changed, 27 insertions(+), 27 deletions(-)
hooks/post-receive
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From: OpenOCD-Gerrit <ope...@us...> - 2022-08-21 22:04:40
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via f77c919cf4dd25d3540bdef7d0bf60f5b84d5dd6 (commit)
from 44e21b41df593d3349c07c2de5e088ea82a37042 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit f77c919cf4dd25d3540bdef7d0bf60f5b84d5dd6
Author: Erhan Kurubas <erh...@es...>
Date: Sat Aug 20 23:22:47 2022 +0300
target/xtensa: fix clang analyzer warnings and gcc12 build errors
Fix Unused code Dead assignment at line 657
Fix Memory error Double free at line 2851
Fix Memory error Memory leak at line 2530
Fix error: 'a3' may be used uninitialized at line 758
Fix error: '%04x' directive writing between 4 and 8 bytes
into a region of size 5 at line 2471
Signed-off-by: Erhan Kurubas <erh...@es...>
Change-Id: I0382a622bc7c4108a335fd741816577e79240397
Reviewed-on: https://review.openocd.org/c/openocd/+/7137
Tested-by: jenkins
Reviewed-by: Ian Thompson <ia...@ca...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index fe0f43882..4e18e3eb4 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -591,7 +591,7 @@ static int xtensa_write_dirty_registers(struct target *target)
unsigned int reg_list_size = xtensa->core_cache->num_regs;
bool preserve_a3 = false;
uint8_t a3_buf[4];
- xtensa_reg_val_t a3, woe;
+ xtensa_reg_val_t a3 = 0, woe;
LOG_TARGET_DEBUG(target, "start");
@@ -655,6 +655,8 @@ static int xtensa_write_dirty_registers(struct target *target)
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3));
xtensa_queue_dbg_reg_read(xtensa, NARADR_DDR, a3_buf);
res = jtag_execute_queue();
+ if (res != ERROR_OK)
+ return res;
xtensa_core_status_check(target);
a3 = buf_get_u32(a3_buf, 0, 32);
}
@@ -2468,7 +2470,7 @@ static int xtensa_build_reg_cache(struct target *target)
LOG_TARGET_ERROR(target, "ERROR: Out of memory");
goto fail;
}
- sprintf((char *)xtensa->empty_regs[i].name, "?0x%04x", i);
+ sprintf((char *)xtensa->empty_regs[i].name, "?0x%04x", i & 0x0000FFFF);
xtensa->empty_regs[i].size = 32;
xtensa->empty_regs[i].type = &xtensa_reg_type;
xtensa->empty_regs[i].value = calloc(1, 4 /*XT_REG_LEN*/); /* make Clang Static Analyzer happy */
@@ -2526,6 +2528,7 @@ fail:
if (reg_list) {
for (unsigned int i = 0; i < reg_list_size; i++)
free(reg_list[i].value);
+ free(reg_list);
}
if (xtensa->empty_regs) {
for (unsigned int i = 0; i < xtensa->dbregs_num; i++) {
@@ -2847,7 +2850,7 @@ int xtensa_init_arch_info(struct target *target, struct xtensa *xtensa,
for (enum xtensa_ar_scratch_set_e s = 0; s < XT_AR_SCRATCH_NUM; s++) {
xtensa->scratch_ars[s].chrval = calloc(8, sizeof(char));
if (!xtensa->scratch_ars[s].chrval) {
- for (enum xtensa_ar_scratch_set_e f = s - 1; s >= 0; s--)
+ for (enum xtensa_ar_scratch_set_e f = 0; f < s; f++)
free(xtensa->scratch_ars[f].chrval);
free(xtensa->core_config);
LOG_ERROR("Xtensa scratch AR alloc failed\n");
-----------------------------------------------------------------------
Summary of changes:
src/target/xtensa/xtensa.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
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