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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-13-g8af4d4462

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- Log -----------------------------------------------------------------
commit 8af4d4462fb1954ab4f5d97bc0513e3082a6bb52
Author: Tomas Vanek <va...@fb...>
Date:   Sun Oct 2 14:46:11 2022 +0200

    tcl/target: add SMP mode to rp2040.cfg
    
    Add the variable selected configuration for SMP debug with rtos hwthread.
    
    Use SMP by default.
    
    Change-Id: I1c37d91688a3ab58d65c15686737892965711adc
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7242
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/rp2040.cfg b/tcl/target/rp2040.cfg
index ee455420b..0593e03ba 100644
--- a/tcl/target/rp2040.cfg
+++ b/tcl/target/rp2040.cfg
@@ -26,12 +26,12 @@ if { [info exists CPUTAPID] } {
 	set _CPUTAPID 0x01002927
 }
 
-# Set to '0' or '1' for single core configuration,
-# anything else for isolated debugging of both cores
+# Set to '0' or '1' for single core configuration, 'SMP' for -rtos hwthread
+# handling of both cores, anything else for isolated debugging of both cores
 if { [info exists USE_CORE] } {
 	set _USE_CORE $USE_CORE
 } else {
-	set _USE_CORE { 0 1 }
+	set _USE_CORE SMP
 }
 set _BOTH_CORES [expr { $_USE_CORE != 0 && $_USE_CORE != 1 }]
 
@@ -54,6 +54,12 @@ if { $_USE_CORE != 0 } {
 	$_TARGETNAME_1 cortex_m reset_config sysresetreq
 }
 
+if {[string compare $_USE_CORE SMP] == 0} {
+	$_TARGETNAME_0 configure  -rtos hwthread
+	$_TARGETNAME_1 configure  -rtos hwthread
+	target smp $_TARGETNAME_0 $_TARGETNAME_1
+}
+
 if { $_USE_CORE == 1 } {
 	set _FLASH_TARGET $_TARGETNAME_1
 } else {

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/rp2040.cfg | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)


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- Log -----------------------------------------------------------------
commit 0979cbc5bcf0688d10815aaa1b938a6086e75f0e
Author: Tomas Vanek <va...@fb...>
Date:   Sun Oct 2 11:21:42 2022 +0200

    flash/nor/rp2040: make SPI flash ID detection optional
    
    Do not read ID from SPI flash and suppress autodetection
    if non-zero flash bank size is configured.
    
    Change-Id: Idcf9ee6ca17f9fa89964a60da7bf11e47b4af5e7
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7241
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/flash/nor/rp2040.c b/src/flash/nor/rp2040.c
index feff9a6f9..b0d118bdb 100644
--- a/src/flash/nor/rp2040.c
+++ b/src/flash/nor/rp2040.c
@@ -50,6 +50,10 @@ struct rp2040_flash_bank {
 	const struct flash_device *dev;
 };
 
+/* guessed SPI flash description if autodetection disabled (same as win w25q16jv) */
+static const struct flash_device rp2040_default_spi_device =
+	FLASH_ID("autodetect disabled", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0, 0x100, 0x10000, 0);
+
 static uint32_t rp2040_lookup_symbol(struct target *target, uint32_t tag, uint16_t *symbol)
 {
 	uint32_t magic;
@@ -432,41 +436,48 @@ static int rp2040_flash_probe(struct flash_bank *bank)
 		return err;
 	}
 
-	err = rp2040_stack_grab_and_prep(bank);
+	if (bank->size) {
+		/* size overridden, suppress reading SPI flash ID */
+		priv->dev = &rp2040_default_spi_device;
+		LOG_DEBUG("SPI flash autodetection disabled, using configured size");
 
-	uint32_t device_id = 0;
-	if (err == ERROR_OK)
-		err = rp2040_spi_read_flash_id(target, &device_id);
+	} else {
+		/* zero bank size in cfg, read SPI flash ID and autodetect */
+		err = rp2040_stack_grab_and_prep(bank);
 
-	rp2040_finalize_stack_free(bank);
+		uint32_t device_id = 0;
+		if (err == ERROR_OK)
+			err = rp2040_spi_read_flash_id(target, &device_id);
 
-	if (err != ERROR_OK)
-		return err;
+		rp2040_finalize_stack_free(bank);
 
-	/* search for a SPI flash Device ID match */
-	priv->dev = NULL;
-	for (const struct flash_device *p = flash_devices; p->name ; p++)
-		if (p->device_id == device_id) {
-			priv->dev = p;
-			break;
+		if (err != ERROR_OK)
+			return err;
+
+		/* search for a SPI flash Device ID match */
+		priv->dev = NULL;
+		for (const struct flash_device *p = flash_devices; p->name ; p++)
+			if (p->device_id == device_id) {
+				priv->dev = p;
+				break;
+			}
+
+		if (!priv->dev) {
+			LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", device_id);
+			return ERROR_FAIL;
 		}
+		LOG_INFO("Found flash device '%s' (ID 0x%08" PRIx32 ")",
+			priv->dev->name, priv->dev->device_id);
 
-	if (!priv->dev) {
-		LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", device_id);
-		return ERROR_FAIL;
+		bank->size = priv->dev->size_in_bytes;
 	}
 
-	LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
-		priv->dev->name, priv->dev->device_id);
-
 	/* the Boot ROM flash_range_program() routine requires page alignment */
 	bank->write_start_alignment = priv->dev->pagesize;
 	bank->write_end_alignment = priv->dev->pagesize;
 
-	bank->size = priv->dev->size_in_bytes;
-
 	bank->num_sectors = bank->size / priv->dev->sectorsize;
-	LOG_INFO("RP2040 B0 Flash Probe: %d bytes @" TARGET_ADDR_FMT ", in %d sectors\n",
+	LOG_INFO("RP2040 B0 Flash Probe: %" PRIu32 " bytes @" TARGET_ADDR_FMT ", in %u sectors\n",
 		bank->size, bank->base, bank->num_sectors);
 	bank->sectors = alloc_block_array(0, priv->dev->sectorsize, bank->num_sectors);
 	if (!bank->sectors)

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/rp2040.c | 55 ++++++++++++++++++++++++++++++--------------------
 1 file changed, 33 insertions(+), 22 deletions(-)


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- Log -----------------------------------------------------------------
commit 59763653c631625f195bf652f226f8537fe66832
Author: Tomas Vanek <va...@fb...>
Date:   Sat Oct 1 17:10:31 2022 +0200

    target/cortex_m: add SMP support for Cortex-M
    
    Cortex-M support for SMP multicore targets.
    
    This SMP implementation unlike older ones does not act
    on the first halted target found. It polls targets
    until a SMP group is finished and stores eventual
    'halted' events instead of emitting them. As soon as polling
    of a group is done, poll proceeds with SMP related tasks.
    This approach improves detection of a reason why debug
    stopped - a correct reason is detected for all targets,
    not only for the first found.
    Drawback: SMP target group should be defined in the same
    order as the targets were defined.
    
    Obsolete gdb 'J' packet/smp_gdb command core switching is not implemented,
    use with rtos hwthread.
    
    Only one core is resumed if debug_execution is requested.
    
    Some ideas taken from Graham Sanderson's [4936]
    and src/target/aarch64.c
    
    Added error checking of armv7m_restore_context().
    
    Change-Id: I60f5b79e74b624dc2b5835ff10e38ac2ccb23792
    Link: [4936]: target/cortex_m: Add smp support for Cortex M | https://review.openocd.org/c/openocd/+/4936
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7239
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 017a6d3a1..88e9bb299 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -28,6 +28,7 @@
 #include "register.h"
 #include "arm_opcodes.h"
 #include "arm_semihosting.h"
+#include "smp.h"
 #include <helper/time_support.h>
 #include <rtt/rtt.h>
 
@@ -871,7 +872,7 @@ static int cortex_m_debug_entry(struct target *target)
 	return ERROR_OK;
 }
 
-static int cortex_m_poll(struct target *target)
+static int cortex_m_poll_one(struct target *target)
 {
 	int detected_failure = ERROR_OK;
 	int retval = ERROR_OK;
@@ -934,21 +935,26 @@ static int cortex_m_poll(struct target *target)
 
 		if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
 			retval = cortex_m_debug_entry(target);
-			if (retval != ERROR_OK)
-				return retval;
 
-			if (arm_semihosting(target, &retval) != 0)
+			/* arm_semihosting needs to know registers, don't run if debug entry returned error */
+			if (retval == ERROR_OK && arm_semihosting(target, &retval) != 0)
 				return retval;
 
-			target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+			if (target->smp) {
+				LOG_TARGET_DEBUG(target, "postpone target event 'halted'");
+				target->smp_halt_event_postponed = true;
+			} else {
+				/* regardless of errors returned in previous code update state */
+				target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+			}
 		}
 		if (prev_target_state == TARGET_DEBUG_RUNNING) {
 			retval = cortex_m_debug_entry(target);
-			if (retval != ERROR_OK)
-				return retval;
 
 			target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 		}
+		if (retval != ERROR_OK)
+			return retval;
 	}
 
 	if (target->state == TARGET_UNKNOWN) {
@@ -981,7 +987,104 @@ static int cortex_m_poll(struct target *target)
 	return retval;
 }
 
-static int cortex_m_halt(struct target *target)
+static int cortex_m_halt_one(struct target *target);
+
+static int cortex_m_smp_halt_all(struct list_head *smp_targets)
+{
+	int retval = ERROR_OK;
+	struct target_list *head;
+
+	foreach_smp_target(head, smp_targets) {
+		struct target *curr = head->target;
+		if (!target_was_examined(curr))
+			continue;
+		if (curr->state == TARGET_HALTED)
+			continue;
+
+		int ret2 = cortex_m_halt_one(curr);
+		if (retval == ERROR_OK)
+			retval = ret2;	/* store the first error code ignore others */
+	}
+	return retval;
+}
+
+static int cortex_m_smp_post_halt_poll(struct list_head *smp_targets)
+{
+	int retval = ERROR_OK;
+	struct target_list *head;
+
+	foreach_smp_target(head, smp_targets) {
+		struct target *curr = head->target;
+		if (!target_was_examined(curr))
+			continue;
+		/* skip targets that were already halted */
+		if (curr->state == TARGET_HALTED)
+			continue;
+
+		int ret2 = cortex_m_poll_one(curr);
+		if (retval == ERROR_OK)
+			retval = ret2;	/* store the first error code ignore others */
+	}
+	return retval;
+}
+
+static int cortex_m_poll_smp(struct list_head *smp_targets)
+{
+	int retval = ERROR_OK;
+	struct target_list *head;
+	bool halted = false;
+
+	foreach_smp_target(head, smp_targets) {
+		struct target *curr = head->target;
+		if (curr->smp_halt_event_postponed) {
+			halted = true;
+			break;
+		}
+	}
+
+	if (halted) {
+		retval = cortex_m_smp_halt_all(smp_targets);
+
+		int ret2 = cortex_m_smp_post_halt_poll(smp_targets);
+		if (retval == ERROR_OK)
+			retval = ret2;	/* store the first error code ignore others */
+
+		foreach_smp_target(head, smp_targets) {
+			struct target *curr = head->target;
+			if (!curr->smp_halt_event_postponed)
+				continue;
+
+			curr->smp_halt_event_postponed = false;
+			if (curr->state == TARGET_HALTED) {
+				LOG_TARGET_DEBUG(curr, "sending postponed target event 'halted'");
+				target_call_event_callbacks(curr, TARGET_EVENT_HALTED);
+			}
+		}
+		/* There is no need to set gdb_service->target
+		 * as hwthread_update_threads() selects an interesting thread
+		 * by its own
+		 */
+	}
+	return retval;
+}
+
+static int cortex_m_poll(struct target *target)
+{
+	int retval = cortex_m_poll_one(target);
+
+	if (target->smp) {
+		struct target_list *last;
+		last = list_last_entry(target->smp_targets, struct target_list, lh);
+		if (target == last->target)
+			/* After the last target in SMP group has been polled
+			 * check for postponed halted events and eventually halt and re-poll
+			 * other targets */
+			cortex_m_poll_smp(target->smp_targets);
+	}
+	return retval;
+}
+
+static int cortex_m_halt_one(struct target *target)
 {
 	LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target));
 
@@ -1019,6 +1122,14 @@ static int cortex_m_halt(struct target *target)
 	return ERROR_OK;
 }
 
+static int cortex_m_halt(struct target *target)
+{
+	if (target->smp)
+		return cortex_m_smp_halt_all(target->smp_targets);
+	else
+		return cortex_m_halt_one(target);
+}
+
 static int cortex_m_soft_reset_halt(struct target *target)
 {
 	struct cortex_m_common *cortex_m = target_to_cm(target);
@@ -1096,8 +1207,8 @@ void cortex_m_enable_breakpoints(struct target *target)
 	}
 }
 
-static int cortex_m_resume(struct target *target, int current,
-	target_addr_t address, int handle_breakpoints, int debug_execution)
+static int cortex_m_restore_one(struct target *target, bool current,
+	target_addr_t *address, bool handle_breakpoints, bool debug_execution)
 {
 	struct armv7m_common *armv7m = target_to_armv7m(target);
 	struct breakpoint *breakpoint = NULL;
@@ -1105,7 +1216,7 @@ static int cortex_m_resume(struct target *target, int current,
 	struct reg *r;
 
 	if (target->state != TARGET_HALTED) {
-		LOG_TARGET_WARNING(target, "target not halted");
+		LOG_TARGET_ERROR(target, "target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
@@ -1147,7 +1258,7 @@ static int cortex_m_resume(struct target *target, int current,
 	/* current = 1: continue on current pc, otherwise continue at <address> */
 	r = armv7m->arm.pc;
 	if (!current) {
-		buf_set_u32(r->value, 0, 32, address);
+		buf_set_u32(r->value, 0, 32, *address);
 		r->dirty = true;
 		r->valid = true;
 	}
@@ -1161,8 +1272,12 @@ static int cortex_m_resume(struct target *target, int current,
 		armv7m_maybe_skip_bkpt_inst(target, NULL);
 
 	resume_pc = buf_get_u32(r->value, 0, 32);
+	if (current)
+		*address = resume_pc;
 
-	armv7m_restore_context(target);
+	int retval = armv7m_restore_context(target);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* the front-end may request us not to handle breakpoints */
 	if (handle_breakpoints) {
@@ -1172,34 +1287,99 @@ static int cortex_m_resume(struct target *target, int current,
 			LOG_TARGET_DEBUG(target, "unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
 				breakpoint->address,
 				breakpoint->unique_id);
-			cortex_m_unset_breakpoint(target, breakpoint);
-			cortex_m_single_step_core(target);
-			cortex_m_set_breakpoint(target, breakpoint);
+			retval = cortex_m_unset_breakpoint(target, breakpoint);
+			if (retval == ERROR_OK)
+				retval = cortex_m_single_step_core(target);
+			int ret2 = cortex_m_set_breakpoint(target, breakpoint);
+			if (retval != ERROR_OK)
+				return retval;
+			if (ret2 != ERROR_OK)
+				return ret2;
 		}
 	}
 
+	return ERROR_OK;
+}
+
+static int cortex_m_restart_one(struct target *target, bool debug_execution)
+{
+	struct armv7m_common *armv7m = target_to_armv7m(target);
+
 	/* Restart core */
 	cortex_m_set_maskints_for_run(target);
 	cortex_m_write_debug_halt_mask(target, 0, C_HALT);
 
 	target->debug_reason = DBG_REASON_NOTHALTED;
-
 	/* registers are now invalid */
 	register_cache_invalidate(armv7m->arm.core_cache);
 
 	if (!debug_execution) {
 		target->state = TARGET_RUNNING;
 		target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
-		LOG_TARGET_DEBUG(target, "target resumed at 0x%" PRIx32 "", resume_pc);
 	} else {
 		target->state = TARGET_DEBUG_RUNNING;
 		target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
-		LOG_TARGET_DEBUG(target, "target debug resumed at 0x%" PRIx32 "", resume_pc);
 	}
 
 	return ERROR_OK;
 }
 
+static int cortex_m_restore_smp(struct target *target, bool handle_breakpoints)
+{
+	struct target_list *head;
+	target_addr_t address;
+	foreach_smp_target(head, target->smp_targets) {
+		struct target *curr = head->target;
+		/* skip calling target */
+		if (curr == target)
+			continue;
+		if (!target_was_examined(curr))
+			continue;
+		/* skip running targets */
+		if (curr->state == TARGET_RUNNING)
+			continue;
+
+		int retval = cortex_m_restore_one(curr, true, &address,
+										handle_breakpoints, false);
+		if (retval != ERROR_OK)
+			return retval;
+
+		retval = cortex_m_restart_one(curr, false);
+		if (retval != ERROR_OK)
+			return retval;
+
+		LOG_TARGET_DEBUG(curr, "SMP resumed at " TARGET_ADDR_FMT, address);
+	}
+	return ERROR_OK;
+}
+
+static int cortex_m_resume(struct target *target, int current,
+						   target_addr_t address, int handle_breakpoints, int debug_execution)
+{
+	int retval = cortex_m_restore_one(target, !!current, &address, !!handle_breakpoints, !!debug_execution);
+	if (retval != ERROR_OK) {
+		LOG_TARGET_ERROR(target, "context restore failed, aborting resume");
+		return retval;
+	}
+
+	if (target->smp && !debug_execution) {
+		retval = cortex_m_restore_smp(target, !!handle_breakpoints);
+		if (retval != ERROR_OK)
+			LOG_WARNING("resume of a SMP target failed, trying to resume current one");
+	}
+
+	cortex_m_restart_one(target, !!debug_execution);
+	if (retval != ERROR_OK) {
+		LOG_TARGET_ERROR(target, "resume failed");
+		return retval;
+	}
+
+	LOG_TARGET_DEBUG(target, "%sresumed at " TARGET_ADDR_FMT,
+					debug_execution ? "debug " : "", address);
+
+	return ERROR_OK;
+}
+
 /* int irqstepcount = 0; */
 static int cortex_m_step(struct target *target, int current,
 	target_addr_t address, int handle_breakpoints)
@@ -1217,6 +1397,11 @@ static int cortex_m_step(struct target *target, int current,
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
+	/* Just one of SMP cores will step. Set the gdb control
+	 * target to current one or gdb miss gdb-end event */
+	if (target->smp && target->gdb_service)
+		target->gdb_service->target = target;
+
 	/* current = 1: continue on current pc, otherwise continue at <address> */
 	if (!current) {
 		buf_set_u32(pc->value, 0, 32, address);
@@ -2850,6 +3035,9 @@ static const struct command_registration cortex_m_exec_command_handlers[] = {
 		.help = "configure software reset handling",
 		.usage = "['sysresetreq'|'vectreset']",
 	},
+	{
+		.chain = smp_command_handlers,
+	},
 	COMMAND_REGISTRATION_DONE
 };
 static const struct command_registration cortex_m_command_handlers[] = {
diff --git a/src/target/target.h b/src/target/target.h
index d445c2975..ef9ba1062 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -193,6 +193,10 @@ struct target {
 	struct list_head *smp_targets;		/* list all targets in this smp group/cluster
 										 * The head of the list is shared between the
 										 * cluster, thus here there is a pointer */
+	bool smp_halt_event_postponed;		/* Some SMP implementations (currently Cortex-M) stores
+										 * 'halted' events and emits them after all targets of
+										 * the SMP group has been polled */
+
 	/* the gdb service is there in case of smp, we have only one gdb server
 	 * for all smp target
 	 * the target attached to the gdb is changing dynamically by changing

-----------------------------------------------------------------------

Summary of changes:
 src/target/cortex_m.c | 226 +++++++++++++++++++++++++++++++++++++++++++++-----
 src/target/target.h   |   4 +
 2 files changed, 211 insertions(+), 19 deletions(-)


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- Log -----------------------------------------------------------------
commit 083100fca3c5fd019517e38028d26a6c8e33a364
Author: Tomas Vanek <va...@fb...>
Date:   Sat Oct 1 17:00:51 2022 +0200

    target/armv7m: check error in armv7m_restore_context()
    
    Return error if arm.write_core_reg() fails.
    
    Change-Id: Ide8f5aa5958532b202dc9f5e13d3250a706d832d
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7238
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 93df5877e..1b85315de 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -182,8 +182,11 @@ int armv7m_restore_context(struct target *target)
 	for (i = cache->num_regs - 1; i >= 0; i--) {
 		struct reg *r = &cache->reg_list[i];
 
-		if (r->exist && r->dirty)
-			armv7m->arm.write_core_reg(target, r, i, ARM_MODE_ANY, r->value);
+		if (r->exist && r->dirty) {
+			int retval = armv7m->arm.write_core_reg(target, r, i, ARM_MODE_ANY, r->value);
+			if (retval != ERROR_OK)
+				return retval;
+		}
 	}
 
 	return ERROR_OK;

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv7m.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)


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- Log -----------------------------------------------------------------
commit d0436b0cdabb2106701222628d78932c973a1e62
Author: Koudai Iwahori <ko...@go...>
Date:   Tue Oct 4 04:21:35 2022 -0700

    armv8: Add support of pointer authentication
    
    When pointer authentication is enabled, some upper bits of the link
    register (LR[63:VA_SIZE]) are used to store a signature. Therefore, GDB
    need to remove the signature to get backtraces.
    GDB has support of pointer authentication. When pointer authenticaion is
    enabled, GDB requests 8-bytes mask to the target to remove the
    signature. mask[63:VA_SIZE] should be all set and mask[VA_SIZE-1:0]
    should be all cleared. GDB removes the signature by addr&~mask or
    addr|mask.
    I added a feature to provide the mask for pointer authentication.
    
    Signed-off-by: Koudai Iwahori <ko...@go...>
    Change-Id: I56fbbf9cc23619b6536ecd326f350c8bf137f322
    Reviewed-on: https://review.openocd.org/c/openocd/+/7248
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index c7fee3e71..aa1707b7d 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -10297,6 +10297,16 @@ the target, the exception catch must be disabled again with @command{$target_nam
 Issuing the command without options prints the current configuration.
 @end deffn
 
+@deffn {Command} {$target_name pauth} [@option{off}|@option{on}]
+Enable or disable pointer authentication features.
+When pointer authentication is used on ARM cores, GDB asks GDB servers for an 8-bytes mask to remove signature bits added by pointer authentication.
+If this feature is enabled, OpenOCD provides GDB with an 8-bytes mask.
+Pointer authentication feature is broken until gdb 12.1, going to be fixed.
+Consider using a newer version of gdb if you want to enable pauth feature.
+The default configuration is @option{off}.
+@end deffn
+
+
 @section EnSilica eSi-RISC Architecture
 
 eSi-RISC is a highly configurable microprocessor architecture for embedded systems
diff --git a/src/target/armv8.c b/src/target/armv8.c
index de0bddb3e..ff71a8e63 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -114,6 +114,166 @@ const char *armv8_mode_name(unsigned psr_mode)
 	return "UNRECOGNIZED";
 }
 
+static uint8_t armv8_pa_size(uint32_t ps)
+{
+	uint8_t ret = 0;
+	switch (ps) {
+		case 0:
+			ret = 32;
+			break;
+		case 1:
+			ret = 36;
+			break;
+		case 2:
+			ret = 40;
+			break;
+		case 3:
+			ret = 42;
+			break;
+		case 4:
+			ret = 44;
+			break;
+		case 5:
+			ret = 48;
+			break;
+		default:
+			LOG_INFO("Unknown physical address size");
+			break;
+	}
+	return ret;
+}
+
+static __attribute__((unused)) int armv8_read_ttbcr32(struct target *target)
+{
+	struct armv8_common *armv8 = target_to_armv8(target);
+	struct arm_dpm *dpm = armv8->arm.dpm;
+	uint32_t ttbcr, ttbcr_n;
+	int retval = dpm->prepare(dpm);
+	if (retval != ERROR_OK)
+		goto done;
+	/*  MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
+	retval = dpm->instr_read_data_r0(dpm,
+			ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
+			&ttbcr);
+	if (retval != ERROR_OK)
+		goto done;
+
+	LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
+
+	ttbcr_n = ttbcr & 0x7;
+	armv8->armv8_mmu.ttbcr = ttbcr;
+
+	/*
+	 * ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
+	 * document # ARM DDI 0406C
+	 */
+	armv8->armv8_mmu.ttbr_range[0]  = 0xffffffff >> ttbcr_n;
+	armv8->armv8_mmu.ttbr_range[1] = 0xffffffff;
+	armv8->armv8_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n);
+	armv8->armv8_mmu.ttbr_mask[1] = 0xffffffff << 14;
+
+	LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
+		  (ttbcr_n != 0) ? "used" : "not used",
+		  armv8->armv8_mmu.ttbr_mask[0],
+		  armv8->armv8_mmu.ttbr_mask[1]);
+
+done:
+	dpm->finish(dpm);
+	return retval;
+}
+
+static int armv8_read_ttbcr(struct target *target)
+{
+	struct armv8_common *armv8 = target_to_armv8(target);
+	struct arm_dpm *dpm = armv8->arm.dpm;
+	struct arm *arm = &armv8->arm;
+	uint32_t ttbcr;
+	uint64_t ttbcr_64;
+
+	int retval = dpm->prepare(dpm);
+	if (retval != ERROR_OK)
+		goto done;
+
+	/* clear ttrr1_used and ttbr0_mask */
+	memset(&armv8->armv8_mmu.ttbr1_used, 0, sizeof(armv8->armv8_mmu.ttbr1_used));
+	memset(&armv8->armv8_mmu.ttbr0_mask, 0, sizeof(armv8->armv8_mmu.ttbr0_mask));
+
+	switch (armv8_curel_from_core_mode(arm->core_mode)) {
+	case SYSTEM_CUREL_EL3:
+		retval = dpm->instr_read_data_r0(dpm,
+				ARMV8_MRS(SYSTEM_TCR_EL3, 0),
+				&ttbcr);
+		retval += dpm->instr_read_data_r0_64(dpm,
+				ARMV8_MRS(SYSTEM_TTBR0_EL3, 0),
+				&armv8->ttbr_base);
+		if (retval != ERROR_OK)
+			goto done;
+		armv8->va_size = 64 - (ttbcr & 0x3F);
+		armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
+		armv8->page_size = (ttbcr >> 14) & 3;
+		break;
+	case SYSTEM_CUREL_EL2:
+		retval = dpm->instr_read_data_r0(dpm,
+				ARMV8_MRS(SYSTEM_TCR_EL2, 0),
+				&ttbcr);
+		retval += dpm->instr_read_data_r0_64(dpm,
+				ARMV8_MRS(SYSTEM_TTBR0_EL2, 0),
+				&armv8->ttbr_base);
+		if (retval != ERROR_OK)
+			goto done;
+		armv8->va_size = 64 - (ttbcr & 0x3F);
+		armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
+		armv8->page_size = (ttbcr >> 14) & 3;
+		break;
+	case SYSTEM_CUREL_EL0:
+		armv8_dpm_modeswitch(dpm, ARMV8_64_EL1H);
+		/* fall through */
+	case SYSTEM_CUREL_EL1:
+		retval = dpm->instr_read_data_r0_64(dpm,
+				ARMV8_MRS(SYSTEM_TCR_EL1, 0),
+				&ttbcr_64);
+		armv8->va_size = 64 - (ttbcr_64 & 0x3F);
+		armv8->pa_size = armv8_pa_size((ttbcr_64 >> 32) & 7);
+		armv8->page_size = (ttbcr_64 >> 14) & 3;
+		armv8->armv8_mmu.ttbr1_used = (((ttbcr_64 >> 16) & 0x3F) != 0) ? 1 : 0;
+		armv8->armv8_mmu.ttbr0_mask  = 0x0000FFFFFFFFFFFF;
+		retval += dpm->instr_read_data_r0_64(dpm,
+				ARMV8_MRS(SYSTEM_TTBR0_EL1 | (armv8->armv8_mmu.ttbr1_used), 0),
+				&armv8->ttbr_base);
+		if (retval != ERROR_OK)
+			goto done;
+		break;
+	default:
+		LOG_ERROR("unknown core state");
+		retval = ERROR_FAIL;
+		break;
+	}
+	if (retval != ERROR_OK)
+		goto done;
+
+	if (armv8->armv8_mmu.ttbr1_used == 1)
+		LOG_INFO("TTBR0 access above %" PRIx64, (uint64_t)(armv8->armv8_mmu.ttbr0_mask));
+
+done:
+	armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
+	dpm->finish(dpm);
+	return retval;
+}
+
+static int armv8_get_pauth_mask(struct armv8_common *armv8, uint64_t *mask)
+{
+	struct arm *arm = &armv8->arm;
+	int retval = ERROR_OK;
+	if (armv8->va_size == 0)
+		retval = armv8_read_ttbcr(arm->target);
+	if (retval != ERROR_OK)
+		return retval;
+
+	*mask = ~(((uint64_t)1 << armv8->va_size) - 1);
+
+	return retval;
+}
+
 static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regval)
 {
 	struct arm_dpm *dpm = &armv8->dpm;
@@ -191,6 +351,10 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
 				ARMV8_MRS(SYSTEM_SPSR_EL3, 0), &value);
 		value_64 = value;
 		break;
+	case ARMV8_PAUTH_CMASK:
+	case ARMV8_PAUTH_DMASK:
+		retval = armv8_get_pauth_mask(armv8, &value_64);
+		break;
 	default:
 		retval = ERROR_FAIL;
 		break;
@@ -772,152 +936,6 @@ static __attribute__((unused)) void armv8_show_fault_registers(struct target *ta
 		armv8_show_fault_registers32(armv8);
 }
 
-static uint8_t armv8_pa_size(uint32_t ps)
-{
-	uint8_t ret = 0;
-	switch (ps) {
-		case 0:
-			ret = 32;
-			break;
-		case 1:
-			ret = 36;
-			break;
-		case 2:
-			ret = 40;
-			break;
-		case 3:
-			ret = 42;
-			break;
-		case 4:
-			ret = 44;
-			break;
-		case 5:
-			ret = 48;
-			break;
-		default:
-			LOG_INFO("Unknown physical address size");
-			break;
-	}
-	return ret;
-}
-
-static __attribute__((unused)) int armv8_read_ttbcr32(struct target *target)
-{
-	struct armv8_common *armv8 = target_to_armv8(target);
-	struct arm_dpm *dpm = armv8->arm.dpm;
-	uint32_t ttbcr, ttbcr_n;
-	int retval = dpm->prepare(dpm);
-	if (retval != ERROR_OK)
-		goto done;
-	/*  MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
-	retval = dpm->instr_read_data_r0(dpm,
-			ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
-			&ttbcr);
-	if (retval != ERROR_OK)
-		goto done;
-
-	LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
-
-	ttbcr_n = ttbcr & 0x7;
-	armv8->armv8_mmu.ttbcr = ttbcr;
-
-	/*
-	 * ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
-	 * document # ARM DDI 0406C
-	 */
-	armv8->armv8_mmu.ttbr_range[0]  = 0xffffffff >> ttbcr_n;
-	armv8->armv8_mmu.ttbr_range[1] = 0xffffffff;
-	armv8->armv8_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n);
-	armv8->armv8_mmu.ttbr_mask[1] = 0xffffffff << 14;
-
-	LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
-		  (ttbcr_n != 0) ? "used" : "not used",
-		  armv8->armv8_mmu.ttbr_mask[0],
-		  armv8->armv8_mmu.ttbr_mask[1]);
-
-done:
-	dpm->finish(dpm);
-	return retval;
-}
-
-static __attribute__((unused)) int armv8_read_ttbcr(struct target *target)
-{
-	struct armv8_common *armv8 = target_to_armv8(target);
-	struct arm_dpm *dpm = armv8->arm.dpm;
-	struct arm *arm = &armv8->arm;
-	uint32_t ttbcr;
-	uint64_t ttbcr_64;
-
-	int retval = dpm->prepare(dpm);
-	if (retval != ERROR_OK)
-		goto done;
-
-	/* clear ttrr1_used and ttbr0_mask */
-	memset(&armv8->armv8_mmu.ttbr1_used, 0, sizeof(armv8->armv8_mmu.ttbr1_used));
-	memset(&armv8->armv8_mmu.ttbr0_mask, 0, sizeof(armv8->armv8_mmu.ttbr0_mask));
-
-	switch (armv8_curel_from_core_mode(arm->core_mode)) {
-	case SYSTEM_CUREL_EL3:
-		retval = dpm->instr_read_data_r0(dpm,
-				ARMV8_MRS(SYSTEM_TCR_EL3, 0),
-				&ttbcr);
-		retval += dpm->instr_read_data_r0_64(dpm,
-				ARMV8_MRS(SYSTEM_TTBR0_EL3, 0),
-				&armv8->ttbr_base);
-		if (retval != ERROR_OK)
-			goto done;
-		armv8->va_size = 64 - (ttbcr & 0x3F);
-		armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
-		armv8->page_size = (ttbcr >> 14) & 3;
-		break;
-	case SYSTEM_CUREL_EL2:
-		retval = dpm->instr_read_data_r0(dpm,
-				ARMV8_MRS(SYSTEM_TCR_EL2, 0),
-				&ttbcr);
-		retval += dpm->instr_read_data_r0_64(dpm,
-				ARMV8_MRS(SYSTEM_TTBR0_EL2, 0),
-				&armv8->ttbr_base);
-		if (retval != ERROR_OK)
-			goto done;
-		armv8->va_size = 64 - (ttbcr & 0x3F);
-		armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
-		armv8->page_size = (ttbcr >> 14) & 3;
-		break;
-	case SYSTEM_CUREL_EL0:
-		armv8_dpm_modeswitch(dpm, ARMV8_64_EL1H);
-		/* fall through */
-	case SYSTEM_CUREL_EL1:
-		retval = dpm->instr_read_data_r0_64(dpm,
-				ARMV8_MRS(SYSTEM_TCR_EL1, 0),
-				&ttbcr_64);
-		armv8->va_size = 64 - (ttbcr_64 & 0x3F);
-		armv8->pa_size = armv8_pa_size((ttbcr_64 >> 32) & 7);
-		armv8->page_size = (ttbcr_64 >> 14) & 3;
-		armv8->armv8_mmu.ttbr1_used = (((ttbcr_64 >> 16) & 0x3F) != 0) ? 1 : 0;
-		armv8->armv8_mmu.ttbr0_mask  = 0x0000FFFFFFFFFFFF;
-		retval += dpm->instr_read_data_r0_64(dpm,
-				ARMV8_MRS(SYSTEM_TTBR0_EL1 | (armv8->armv8_mmu.ttbr1_used), 0),
-				&armv8->ttbr_base);
-		if (retval != ERROR_OK)
-			goto done;
-		break;
-	default:
-		LOG_ERROR("unknown core state");
-		retval = ERROR_FAIL;
-		break;
-	}
-	if (retval != ERROR_OK)
-		goto done;
-
-	if (armv8->armv8_mmu.ttbr1_used == 1)
-		LOG_INFO("TTBR0 access above %" PRIx64, (uint64_t)(armv8->armv8_mmu.ttbr0_mask));
-
-done:
-	armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
-	dpm->finish(dpm);
-	return retval;
-}
-
 /*  method adapted to cortex A : reused arm v4 v5 method*/
 int armv8_mmu_translate_va(struct target *target,  target_addr_t va, target_addr_t *val)
 {
@@ -1083,6 +1101,15 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command)
 	return ERROR_OK;
 }
 
+COMMAND_HANDLER(armv8_pauth_command)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	struct armv8_common *armv8 = target_to_armv8(target);
+	return CALL_COMMAND_HANDLER(handle_command_parse_bool,
+				    &armv8->enable_pauth,
+				    "pauth feature");
+}
+
 int armv8_handle_cache_info_command(struct command_invocation *cmd,
 	struct armv8_cache_common *armv8_cache)
 {
@@ -1421,6 +1448,8 @@ static const struct {
 														NULL},
 	{ ARMV8_SPSR_EL3, "SPSR_EL3", 32, ARMV8_64_EL3H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
 														NULL},
+	{ ARMV8_PAUTH_DMASK, "pauth_dmask", 64, ARM_MODE_ANY, REG_TYPE_UINT64, NULL, "org.gnu.gdb.aarch64.pauth", NULL},
+	{ ARMV8_PAUTH_CMASK, "pauth_cmask", 64, ARM_MODE_ANY, REG_TYPE_UINT64, NULL, "org.gnu.gdb.aarch64.pauth", NULL},
 };
 
 static const struct {
@@ -1650,6 +1679,9 @@ struct reg_cache *armv8_build_reg_cache(struct target *target)
 				*reg_list[i].reg_data_type = *armv8_regs[i].data_type;
 		} else
 			LOG_ERROR("unable to allocate reg type list");
+
+		if (i == ARMV8_PAUTH_CMASK || i == ARMV8_PAUTH_DMASK)
+			reg_list[i].hidden = !armv8->enable_pauth;
 	}
 
 	arm->cpsr = reg_list + ARMV8_XPSR;
@@ -1745,6 +1777,17 @@ const struct command_registration armv8_command_handlers[] = {
 		.help = "configure exception catch",
 		.usage = "[(nsec_el1,nsec_el2,sec_el1,sec_el3)+,off]",
 	},
+	{
+		.name = "pauth",
+		.handler = armv8_pauth_command,
+		.mode = COMMAND_CONFIG,
+		.help = "enable or disable providing GDB with an 8-bytes mask to "
+			"remove signature bits added by pointer authentication."
+			"Pointer authentication feature is broken until gdb 12.1, going to be fixed. "
+			"Consider using a newer version of gdb if you want enable "
+			"pauth feature.",
+		.usage = "[on|off]",
+	},
 	COMMAND_REGISTRATION_DONE
 };
 
diff --git a/src/target/armv8.h b/src/target/armv8.h
index 2ed3a65ac..54aa08634 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -98,6 +98,10 @@ enum {
 	ARMV8_ESR_EL3 = 75,
 	ARMV8_SPSR_EL3 = 76,
 
+	/* Pseudo registers defined by GDB to remove the pauth signature. */
+	ARMV8_PAUTH_DMASK = 77,
+	ARMV8_PAUTH_CMASK = 78,
+
 	ARMV8_LAST_REG,
 };
 
@@ -205,6 +209,9 @@ struct armv8_common {
 
 	struct arm_cti *cti;
 
+	/* True if OpenOCD provides pointer auth related info to GDB */
+	bool enable_pauth;
+
 	/* last run-control command issued to this target (resume, halt, step) */
 	enum run_control_op last_run_control_op;
 

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi   |  10 ++
 src/target/armv8.c | 335 ++++++++++++++++++++++++++++++-----------------------
 src/target/armv8.h |   7 ++
 3 files changed, 206 insertions(+), 146 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-8-gd96dc47ef

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  d96dc47ef67e427cd64a07d9825fd297e3a81633 (commit)
      from  9a7781ff8c9dea6ef5998238b1932094b8a226da (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit d96dc47ef67e427cd64a07d9825fd297e3a81633
Author: James G. Smith <js...@ra...>
Date:   Wed May 26 10:08:26 2021 +0100

    src/rtos/eCos : Support per-build configuration specific structure layouts
    
    Extended feature. This is a large patch, but is self-contained to the
    eCos support and does not affect any other openocd functionality. It
    does NOT affect existing eCos RTOS plugin users where their
    applications do not provide the extended symbolic helper
    information. If the helper symbols are not available the rtos support
    code will behave as before. This "dynamic" functionality is *required*
    because eCos does NOT have a fixed/hardwired, known, layout for the
    thread descriptor structure. The per-application build eCos
    configuration can affect the shape of the thread descriptor structure
    (field presence, and hence offsets of subsequent fields) such that
    constant values cannot be used to consistently interpret all possible
    eCos application configurations. For historical reasons, there is not
    yet a consistent namespace for the helper symbols across eCos HALs
    hence the support is currently limited to specific architectures
    (Cortex-M and ARM/Cortex-A). No new Clang analyser warnings are raised
    by this changeset.
    
    Change-Id: Ib3a36877326eeb56595cbca55e21b9e59a59c98a
    Signed-off-by: James G. Smith <js...@ra...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/6275
    Reviewed-by: Alex Schuilenburg <ale...@gm...>
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/rtos/eCos.c b/src/rtos/eCos.c
index 3f813ac38..963bb61cf 100644
--- a/src/rtos/eCos.c
+++ b/src/rtos/eCos.c
@@ -11,66 +11,446 @@
 #include <jtag/jtag.h>
 #include "target/target.h"
 #include "target/target_type.h"
+#include "target/armv7m.h"
 #include "rtos.h"
 #include "helper/log.h"
 #include "helper/types.h"
+#include "helper/bits.h"
+#include "rtos_standard_stackings.h"
 #include "rtos_ecos_stackings.h"
+#include "server/gdb_server.h"
+
+/* Unfortunately for the moment we are limited to returning the hardwired
+ * register count (ARMV7M_NUM_CORE_REGS for Cortex-M) since the openocd RTOS
+ * support does not yet support accessing all per-thread "stacked"
+ * registers. e.g. For Cortex-M under eCos we have a per-thread BASEPRI, and for
+ * all eCos targets we may have per-thread VFP/FPU register state.
+ *
+ * So, for the moment, we continue to use the hardwired limit for the depth of
+ * the returned register description vector. The current openocd
+ * rtos_standard_stackings.c just provides the main core regs for the Cortex_M*
+ * targets regardless of whether FPU is present/enabled.
+ *
+ * However, this code is written with the expectation that we may eventually be
+ * able to provide more register information ("m-system" and "vfp" for example)
+ * and also with the expectation of supporting different register sets being
+ * returned depending on the per-thread Cortex-M eCos contex_m for
+ * example. Hence the fact that the eCos_stack_layout_*() functions below allow
+ * for the stack context descriptor vector to be returned by those calls
+ * allowing for eventual support where this code will potentially cache
+ * different sets of register descriptors for the different shapes of contexts
+ * in a *single* application/binary run-time.
+ *
+ * TODO: Extend openocd generic RTOS support to allow thread-specific system and
+ * FPU register state to be returned. */
+
+struct ecos_params;
 
 static bool ecos_detect_rtos(struct target *target);
 static int ecos_create(struct target *target);
 static int ecos_update_threads(struct rtos *rtos);
 static int ecos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs);
 static int ecos_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]);
+static int ecos_stack_layout_cortexm(struct rtos *rtos, struct ecos_params *param,
+				int64_t stack_ptr, const struct rtos_register_stacking **si);
+static int ecos_stack_layout_arm(struct rtos *rtos, struct ecos_params *param,
+				int64_t stack_ptr, const struct rtos_register_stacking **si);
+
+/* The current eCos thread IDentifier uses 0 as an unused (not a valid thread
+ * ID) value. Currently the unique_id field is 16-bits, but the eCos SMP support
+ * convention is that only 12-bits of the ID will be used. This
+ * ECOS_MAX_THREAD_COUNT manifest is provided to limit the potential for
+ * interpreting stale/inconsistent thread list state when the debug host scans
+ * the thread list before the target RTOS has completed its initialisation. This
+ * support will need to revisited when eCos is re-engineered to support more
+ * than 16 CPU SMP setups. */
+#define ECOS_MAX_THREAD_COUNT (4095)
 
 struct ecos_thread_state {
 	int value;
 	const char *desc;
 };
 
-static const struct ecos_thread_state ecos_thread_states[] = {
-	{ 0, "Ready" },
-	{ 1, "Sleeping" },
-	{ 2, "Countsleep" },
-	{ 4, "Suspended" },
-	{ 8, "Creating" },
-	{ 16, "Exited" }
+/* The status is actually a logical-OR bitmask of states: */
+enum ecos_thread_state_flags {
+	RUNNING    = 0, /* explicit no-bits-set value */
+	SLEEPING   = BIT(0),
+	COUNTSLEEP = BIT(1),
+	SUSPENDED  = BIT(2),
+	CREATING   = BIT(3),
+	EXITED     = BIT(4),
+	SLEEPSET   = (SLEEPING | COUNTSLEEP)
+};
+
+/* Cyg_Thread:: reason codes for wake and sleep fields: */
+static const struct ecos_thread_state ecos_thread_reasons[] = {
+	{ 0, "NONE" }, /* normally indicates "not yet started" */
+	{ 1, "WAIT" }, /* wait with no timeout */
+	{ 2, "DELAY" }, /* simple time delay */
+	{ 3, "TIMEOUT" }, /* wait with timeout *or* timeout expired */
+	{ 4, "BREAK" }, /* forced break out of sleep */
+	{ 5, "DESTRUCT" }, /* wait on object being destroyed */
+	{ 6, "EXIT" }, /* forced termination */
+	{ 7, "DONE" } /* wait/delay completed */
+};
+
+static const char * const target_cortex_m[] = {
+	"cortex_m",
+	"hla_target",
+	NULL
+};
+
+static const char * const target_arm[] = {
+	"cortex_a",
+	"arm7tdmi",
+	"arm720t",
+	"arm9tdmi",
+	"arm920t",
+	"arm926ejs",
+	"arm946e",
+	"arm966e",
+	"arm11",
+	NULL
 };
 
-#define ECOS_NUM_STATES ARRAY_SIZE(ecos_thread_states)
+/* Since individual eCos application configurations may have different thread
+ * object structure layouts depending on the actual build-time enabled features
+ * we provide support for applications built containing the relevant symbolic
+ * support to match the actual application binary being debugged, rather than
+ * relying on a set of default/fixed (and potentially incorrect)
+ * offsets. However, for backwards compatibility, we do *NOT* enforce the
+ * requirement for the common extra helper symbols to be present to allow the
+ * fallback to the simple fixed CM3 model to avoid affecting existing users of
+ * older eCos worlds. Similarly we need to provide support for per-thread
+ * register context offsets, as well as for per-application-configurations,
+ * since some targets can have different stacked state on a per-thread basis
+ * (e.g. "cortex_m"). This is why the stacking_info is now set at run-time
+ * rather than being fixed. */
 
 struct ecos_params {
-	const char *target_name;
+	const char * const *target_names; /* NULL terminated list of targets */
+	int (*target_stack_layout)(struct rtos *rtos, struct ecos_params *param,
+		int64_t stack_ptr, const struct rtos_register_stacking **si);
+	bool flush_common;
 	unsigned char pointer_width;
-	unsigned char thread_stack_offset;
-	unsigned char thread_name_offset;
-	unsigned char thread_state_offset;
-	unsigned char thread_next_offset;
-	unsigned char thread_uniqueid_offset;
+	unsigned char uid_width;
+	unsigned char state_width;
+	unsigned int thread_stack_offset;
+	unsigned int thread_name_offset;
+	unsigned int thread_state_offset;
+	unsigned int thread_next_offset;
+	unsigned int thread_uniqueid_offset;
 	const struct rtos_register_stacking *stacking_info;
 };
 
-static const struct ecos_params ecos_params_list[] = {
+/* As mentioned above we provide default offset values for the "cortex_m"
+ * targets for backwards compatibility with older eCos application builds and
+ * previous users of this RTOS specific support that do not have the
+ * configuration specific offsets provided in the symbol table. The support for
+ * other targets (e.g. "cortex_a") we do expect the application to provide the
+ * required symbolic information. We do not populate the stacking_info reference
+ * until we have had a chance to interrogate the symbol table. */
+
+static struct ecos_params ecos_params_list[] = {
+	{
+	.target_names = target_cortex_m,
+	.pointer_width = 4,
+	.uid_width = 2,
+	.state_width = 4,
+	.thread_stack_offset = 0x0c,
+	.thread_name_offset = 0x9c,
+	.thread_state_offset = 0x3c,
+	.thread_next_offset = 0xa0,
+	.thread_uniqueid_offset = 0x4c,
+	.target_stack_layout = ecos_stack_layout_cortexm,
+	.stacking_info = NULL
+	},
 	{
-	"cortex_m",			/* target_name */
-	4,						/* pointer_width; */
-	0x0c,					/* thread_stack_offset; */
-	0x9c,					/* thread_name_offset; */
-	0x3c,					/* thread_state_offset; */
-	0xa0,					/* thread_next_offset */
-	0x4c,					/* thread_uniqueid_offset */
-	&rtos_ecos_cortex_m3_stacking	/* stacking_info */
+	.target_names = target_arm,
+	.pointer_width = 0,
+	.uid_width = 0,
+	.state_width = 0,
+	.thread_stack_offset = 0,
+	.thread_name_offset = 0,
+	.thread_state_offset = 0,
+	.thread_next_offset = 0,
+	.thread_uniqueid_offset = 0,
+	.target_stack_layout = ecos_stack_layout_arm,
+	.stacking_info = NULL
 	}
 };
 
+#define ECOS_NUM_PARAMS ARRAY_SIZE(ecos_params_list)
+
+/* To eventually allow for more than just the ARMV7M_NUM_CORE_REGS to be
+ * returned by the Cortex-M support, and to avoid run-time lookups we manually
+ * maintain our own mapping for the supplied stack register vector entries. This
+ * enum needs to match the rtos_ecos_regoff_cortexm[] vector. Admittedly the
+ * initial indices just match the corresponding ARMV7M_R* definitions, but after
+ * the base registers the ARMV7M_* number space does not match the vector we
+ * wish to populate in this eCos support code. */
+enum ecos_reglist_cortexm {
+	ECOS_REGLIST_R0 = 0,
+	ECOS_REGLIST_R1,
+	ECOS_REGLIST_R2,
+	ECOS_REGLIST_R3,
+	ECOS_REGLIST_R4,
+	ECOS_REGLIST_R5,
+	ECOS_REGLIST_R6,
+	ECOS_REGLIST_R7,
+	ECOS_REGLIST_R8,
+	ECOS_REGLIST_R9,
+	ECOS_REGLIST_R10,
+	ECOS_REGLIST_R11,
+	ECOS_REGLIST_R12,
+	ECOS_REGLIST_R13,
+	ECOS_REGLIST_R14,
+	ECOS_REGLIST_PC,
+	ECOS_REGLIST_XPSR,	/* ARMV7M_NUM_CORE_REGS */
+	ECOS_REGLIST_BASEPRI,
+	ECOS_REGLIST_FPSCR,	/* Following for FPU contexts */
+	ECOS_REGLIST_D0,
+	ECOS_REGLIST_D1,
+	ECOS_REGLIST_D2,
+	ECOS_REGLIST_D3,
+	ECOS_REGLIST_D4,
+	ECOS_REGLIST_D5,
+	ECOS_REGLIST_D6,
+	ECOS_REGLIST_D7,
+	ECOS_REGLIST_D8,
+	ECOS_REGLIST_D9,
+	ECOS_REGLIST_D10,
+	ECOS_REGLIST_D11,
+	ECOS_REGLIST_D12,
+	ECOS_REGLIST_D13,
+	ECOS_REGLIST_D14,
+	ECOS_REGLIST_D15
+};
+
+#define ECOS_CORTEXM_BASE_NUMREGS (ARMV7M_NUM_CORE_REGS)
+
+/* NOTE: The offsets in this vector are overwritten by the architecture specific
+ * layout functions depending on the specific application configuration. The
+ * ordering of this vector MUST match eCos_reglist. */
+static struct stack_register_offset rtos_ecos_regoff_cortexm[] = {
+	{ ARMV7M_R0,      -1, 32 },	/* r0            */
+	{ ARMV7M_R1,      -1, 32 },	/* r1            */
+	{ ARMV7M_R2,      -1, 32 },	/* r2            */
+	{ ARMV7M_R3,      -1, 32 },	/* r3            */
+	{ ARMV7M_R4,      -1, 32 },	/* r4            */
+	{ ARMV7M_R5,      -1, 32 },	/* r5            */
+	{ ARMV7M_R6,      -1, 32 },	/* r6            */
+	{ ARMV7M_R7,      -1, 32 },	/* r7            */
+	{ ARMV7M_R8,      -1, 32 },	/* r8            */
+	{ ARMV7M_R9,      -1, 32 },	/* r9            */
+	{ ARMV7M_R10,     -1, 32 },	/* r10           */
+	{ ARMV7M_R11,     -1, 32 },	/* r11           */
+	{ ARMV7M_R12,     -1, 32 },	/* r12           */
+	{ ARMV7M_R13,     -1, 32 },	/* sp            */
+	{ ARMV7M_R14,     -1, 32 },	/* lr            */
+	{ ARMV7M_PC,      -1, 32 },	/* pc            */
+	{ ARMV7M_XPSR,    -1, 32 },	/* xPSR          */
+	{ ARMV7M_BASEPRI, -1, 32 },     /* BASEPRI       */
+	{ ARMV7M_FPSCR,   -1, 32 },     /* FPSCR         */
+	{ ARMV7M_D0,      -1, 64 },     /* D0  (S0/S1)   */
+	{ ARMV7M_D1,      -1, 64 },     /* D1  (S2/S3)   */
+	{ ARMV7M_D2,      -1, 64 },     /* D2  (S4/S5)   */
+	{ ARMV7M_D3,      -1, 64 },     /* D3  (S6/S7)   */
+	{ ARMV7M_D4,      -1, 64 },     /* D4  (S8/S9)   */
+	{ ARMV7M_D5,      -1, 64 },     /* D5  (S10/S11) */
+	{ ARMV7M_D6,      -1, 64 },     /* D6  (S12/S13) */
+	{ ARMV7M_D7,      -1, 64 },     /* D7  (S14/S15) */
+	{ ARMV7M_D8,      -1, 64 },     /* D8  (S16/S17) */
+	{ ARMV7M_D9,      -1, 64 },     /* D9  (S18/S19) */
+	{ ARMV7M_D10,     -1, 64 },     /* D10 (S20/S21) */
+	{ ARMV7M_D11,     -1, 64 },     /* D11 (S22/S23) */
+	{ ARMV7M_D12,     -1, 64 },     /* D12 (S24/S25) */
+	{ ARMV7M_D13,     -1, 64 },     /* D13 (S26/S27) */
+	{ ARMV7M_D14,     -1, 64 },     /* D14 (S28/S29) */
+	{ ARMV7M_D15,     -1, 64 },     /* D15 (S30/S31) */
+};
+
+static struct stack_register_offset rtos_ecos_regoff_arm[] = {
+	{ 0,  -1, 32 },		/* r0       */
+	{ 1,  -1, 32 },		/* r1       */
+	{ 2,  -1, 32 },		/* r2       */
+	{ 3,  -1, 32 },		/* r3       */
+	{ 4,  -1, 32 },		/* r4       */
+	{ 5,  -1, 32 },		/* r5       */
+	{ 6,  -1, 32 },		/* r6       */
+	{ 7,  -1, 32 },		/* r7       */
+	{ 8,  -1, 32 },		/* r8       */
+	{ 9,  -1, 32 },		/* r9       */
+	{ 10, -1, 32 },		/* r10      */
+	{ 11, -1, 32 },		/* r11 (fp) */
+	{ 12, -1, 32 },		/* r12 (ip) */
+	{ 13, -1, 32 },		/* sp (r13) */
+	{ 14, -1, 32 },		/* lr (r14) */
+	{ 15, -1, 32 },		/* pc (r15) */
+	{ 16, -1, 32 },		/* xPSR     */
+};
+
+static struct rtos_register_stacking rtos_ecos_stacking = {
+	.stack_registers_size = 0,
+	.stack_growth_direction = -1,
+	.num_output_registers = 0,
+	.calculate_process_stack = NULL,	/* stack_alignment */
+	.register_offsets = NULL
+};
+
+/* To avoid the run-time cost of matching explicit symbol names we push the
+ * lookup offsets to this *manually* maintained enumeration which must match the
+ * ecos_symbol_list[] order below. */
 enum ecos_symbol_values {
 	ECOS_VAL_THREAD_LIST = 0,
-	ECOS_VAL_CURRENT_THREAD_PTR = 1
+	ECOS_VAL_CURRENT_THREAD_PTR,
+	ECOS_VAL_COMMON_THREAD_NEXT_OFF,
+	ECOS_VAL_COMMON_THREAD_NEXT_SIZE,
+	ECOS_VAL_COMMON_THREAD_STATE_OFF,
+	ECOS_VAL_COMMON_THREAD_STATE_SIZE,
+	ECOS_VAL_COMMON_THREAD_SLEEP_OFF,
+	ECOS_VAL_COMMON_THREAD_SLEEP_SIZE,
+	ECOS_VAL_COMMON_THREAD_WAKE_OFF,
+	ECOS_VAL_COMMON_THREAD_WAKE_SIZE,
+	ECOS_VAL_COMMON_THREAD_ID_OFF,
+	ECOS_VAL_COMMON_THREAD_ID_SIZE,
+	ECOS_VAL_COMMON_THREAD_NAME_OFF,
+	ECOS_VAL_COMMON_THREAD_NAME_SIZE,
+	ECOS_VAL_COMMON_THREAD_PRI_OFF,
+	ECOS_VAL_COMMON_THREAD_PRI_SIZE,
+	ECOS_VAL_COMMON_THREAD_STACK_OFF,
+	ECOS_VAL_COMMON_THREAD_STACK_SIZE,
+	ECOS_VAL_CORTEXM_THREAD_SAVED,
+	ECOS_VAL_CORTEXM_CTX_THREAD_SIZE,
+	ECOS_VAL_CORTEXM_CTX_TYPE_OFF,
+	ECOS_VAL_CORTEXM_CTX_TYPE_SIZE,
+	ECOS_VAL_CORTEXM_CTX_BASEPRI_OFF,
+	ECOS_VAL_CORTEXM_CTX_BASEPRI_SIZE,
+	ECOS_VAL_CORTEXM_CTX_SP_OFF,
+	ECOS_VAL_CORTEXM_CTX_SP_SIZE,
+	ECOS_VAL_CORTEXM_CTX_REG_OFF,
+	ECOS_VAL_CORTEXM_CTX_REG_SIZE,
+	ECOS_VAL_CORTEXM_CTX_PC_OFF,
+	ECOS_VAL_CORTEXM_CTX_PC_SIZE,
+	ECOS_VAL_CORTEXM_VAL_EXCEPTION,
+	ECOS_VAL_CORTEXM_VAL_THREAD,
+	ECOS_VAL_CORTEXM_VAL_INTERRUPT,
+	ECOS_VAL_CORTEXM_VAL_FPU,
+	ECOS_VAL_CORTEXM_CTX_FPSCR_OFF,
+	ECOS_VAL_CORTEXM_CTX_FPSCR_SIZE,
+	ECOS_VAL_CORTEXM_CTX_S_OFF,
+	ECOS_VAL_CORTEXM_CTX_S_SIZE,
+	ECOS_VAL_ARM_REGSIZE,
+	ECOS_VAL_ARM_CTX_R0_OFF,
+	ECOS_VAL_ARM_CTX_R1_OFF,
+	ECOS_VAL_ARM_CTX_R2_OFF,
+	ECOS_VAL_ARM_CTX_R3_OFF,
+	ECOS_VAL_ARM_CTX_R4_OFF,
+	ECOS_VAL_ARM_CTX_R5_OFF,
+	ECOS_VAL_ARM_CTX_R6_OFF,
+	ECOS_VAL_ARM_CTX_R7_OFF,
+	ECOS_VAL_ARM_CTX_R8_OFF,
+	ECOS_VAL_ARM_CTX_R9_OFF,
+	ECOS_VAL_ARM_CTX_R10_OFF,
+	ECOS_VAL_ARM_CTX_FP_OFF,
+	ECOS_VAL_ARM_CTX_IP_OFF,
+	ECOS_VAL_ARM_CTX_SP_OFF,
+	ECOS_VAL_ARM_CTX_LR_OFF,
+	ECOS_VAL_ARM_CTX_PC_OFF,
+	ECOS_VAL_ARM_CTX_CPSR_OFF,
+	ECOS_VAL_ARM_FPUSIZE,
+	ECOS_VAL_ARM_CTX_FPSCR_OFF,
+	ECOS_VAL_ARM_SCOUNT,
+	ECOS_VAL_ARM_CTX_SVEC_OFF,
+	ECOS_VAL_ARM_VFPCOUNT,
+	ECOS_VAL_ARM_CTX_VFPVEC_OFF
 };
 
-static const char * const ecos_symbol_list[] = {
-	"Cyg_Thread::thread_list",
-	"Cyg_Scheduler_Base::current_thread",
-	NULL
+struct symbols {
+	const char *name;
+	const char * const *target_names; /* non-NULL when for a specific architecture */
+	bool optional;
+};
+
+#define ECOSSYM(_n, _o, _t) { .name = _n, .optional = (_o), .target_names = _t }
+
+/* Some of offset/size helper symbols are common to all eCos
+ * targets. Unfortunately, for historical reasons, some information is in
+ * architecture specific namespaces leading to some duplication and a larger
+ * vector below. */
+static const struct symbols ecos_symbol_list[] = {
+	ECOSSYM("Cyg_Thread::thread_list", false, NULL),
+	ECOSSYM("Cyg_Scheduler_Base::current_thread", false, NULL),
+	/* Following symbols *are* required for generic application-specific
+	 * configuration support, but we mark as optional for backwards
+	 * compatibility with the previous fixed Cortex-M3 only RTOS plugin
+	 * implementation. */
+	ECOSSYM("__ecospro_syminfo.off.cyg_thread.list_next", true, NULL),
+	ECOSSYM("__ecospro_syminfo.size.cyg_thread.list_next", true, NULL),
+	ECOSSYM("__ecospro_syminfo.off.cyg_thread.state", true, NULL),
+	ECOSSYM("__ecospro_syminfo.size.cyg_thread.state", true, NULL),
+	ECOSSYM("__ecospro_syminfo.off.cyg_thread.sleep_reason", true, NULL),
+	ECOSSYM("__ecospro_syminfo.size.cyg_thread.sleep_reason", true, NULL),
+	ECOSSYM("__ecospro_syminfo.off.cyg_thread.wake_reason", true, NULL),
+	ECOSSYM("__ecospro_syminfo.size.cyg_thread.wake_reason", true, NULL),
+	ECOSSYM("__ecospro_syminfo.off.cyg_thread.unique_id", true, NULL),
+	ECOSSYM("__ecospro_syminfo.size.cyg_thread.unique_id", true, NULL),
+	ECOSSYM("__ecospro_syminfo.off.cyg_thread.name", true, NULL),
+	ECOSSYM("__ecospro_syminfo.size.cyg_thread.name", true, NULL),
+	ECOSSYM("__ecospro_syminfo.off.cyg_thread.priority", true, NULL),
+	ECOSSYM("__ecospro_syminfo.size.cyg_thread.priority", true, NULL),
+	ECOSSYM("__ecospro_syminfo.off.cyg_thread.stack_ptr", true, NULL),
+	ECOSSYM("__ecospro_syminfo.size.cyg_thread.stack_ptr", true, NULL),
+	/* optional Cortex-M: */
+	ECOSSYM("__ecospro_syminfo.cortexm.thread.saved", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.Thread", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.type", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.type", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.basepri", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.basepri", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.sp", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.sp", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.r", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.r", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.pc", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.pc", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.value.HAL_SAVEDREGISTERS.EXCEPTION", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.value.HAL_SAVEDREGISTERS.THREAD", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.value.HAL_SAVEDREGISTERS.INTERRUPT", true, target_cortex_m),
+	/* optional Cortex-M with H/W FPU configured: */
+	ECOSSYM("__ecospro_syminfo.value.HAL_SAVEDREGISTERS.WITH_FPU", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.fpscr", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.fpscr", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.s", true, target_cortex_m),
+	ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.s", true, target_cortex_m),
+	/* optional ARM: */
+	ECOSSYM("ARMREG_SIZE", true, target_arm),
+	ECOSSYM("armreg_r0", true, target_arm),
+	ECOSSYM("armreg_r1", true, target_arm),
+	ECOSSYM("armreg_r2", true, target_arm),
+	ECOSSYM("armreg_r3", true, target_arm),
+	ECOSSYM("armreg_r4", true, target_arm),
+	ECOSSYM("armreg_r5", true, target_arm),
+	ECOSSYM("armreg_r6", true, target_arm),
+	ECOSSYM("armreg_r7", true, target_arm),
+	ECOSSYM("armreg_r8", true, target_arm),
+	ECOSSYM("armreg_r9", true, target_arm),
+	ECOSSYM("armreg_r10", true, target_arm),
+	ECOSSYM("armreg_fp", true, target_arm),
+	ECOSSYM("armreg_ip", true, target_arm),
+	ECOSSYM("armreg_sp", true, target_arm),
+	ECOSSYM("armreg_lr", true, target_arm),
+	ECOSSYM("armreg_pc", true, target_arm),
+	ECOSSYM("armreg_cpsr", true, target_arm),
+	/* optional ARM FPU common: */
+	ECOSSYM("ARMREG_FPUCONTEXT_SIZE", true, target_arm),
+	ECOSSYM("armreg_fpscr", true, target_arm),
+	/* optional ARM FPU single-precision: */
+	ECOSSYM("ARMREG_S_COUNT", true, target_arm),
+	ECOSSYM("armreg_s_vec", true, target_arm),
+	/* optional ARM FPU double-precision: */
+	ECOSSYM("ARMREG_VFP_COUNT", true, target_arm),
+	ECOSSYM("armreg_vfp_vec", true, target_arm),
 };
 
 const struct rtos_type ecos_rtos = {
@@ -84,34 +464,280 @@ const struct rtos_type ecos_rtos = {
 
 };
 
+static symbol_address_t ecos_value(struct rtos *rtos, unsigned int idx)
+{
+	if (idx < ARRAY_SIZE(ecos_symbol_list))
+		return rtos->symbols[idx].address;
+
+	/* We do not terminate, just return 0 in this case. */
+	LOG_ERROR("eCos: Invalid symbol index %u", idx);
+	return 0;
+}
+
+#define XMLENTRY(_c, _s) { .xc = (_c), .rs = (_s), .rlen = (sizeof(_s) - 1) }
+
+static const struct {
+	char xc;
+	const char *rs;
+	size_t rlen;
+} xmlchars[] = {
+	XMLENTRY('<', "&lt;"),
+	XMLENTRY('&', "&amp;"),
+	XMLENTRY('>', "&gt;"),
+	XMLENTRY('\'', "&apos;"),
+	XMLENTRY('"', "&quot;")
+};
+
+/** Escape any XML reserved characters in a string. */
+static bool ecos_escape_string(const char *raw, char *out, size_t limit)
+{
+	static const char *tokens = "<&>\'\"";
+	bool escaped = false;
+
+	if (!out || !limit)
+		return false;
+
+	(void)memset(out, '\0', limit);
+
+	while (raw && *raw && limit) {
+		size_t lok = strcspn(raw, tokens);
+		if (lok) {
+			size_t tocopy;
+			tocopy = ((limit < lok) ? limit : lok);
+			(void)memcpy(out, raw, tocopy);
+			limit -= tocopy;
+			out += tocopy;
+			raw += lok;
+			continue;
+		}
+
+		char *fidx = strchr(tokens, *raw);
+		if (!fidx) {
+			/* Should never happen assuming xmlchars
+			 * vector and tokens string match. */
+			LOG_ERROR("eCos: Unexpected XML char %c", *raw);
+			continue;
+		}
+
+		uint32_t cidx = (fidx - tokens);
+		size_t tocopy = xmlchars[cidx].rlen;
+		if (limit < tocopy)
+			break;
+
+		escaped = true;
+		(void)memcpy(out, xmlchars[cidx].rs, tocopy);
+		limit -= tocopy;
+		out += tocopy;
+		raw++;
+	}
+
+	return escaped;
+}
+
+static int ecos_check_app_info(struct rtos *rtos, struct ecos_params *param)
+{
+	if (!rtos || !param)
+		return -1;
+
+	if (param->flush_common) {
+		if (debug_level >= LOG_LVL_DEBUG) {
+			for (unsigned int idx = 0; idx < ARRAY_SIZE(ecos_symbol_list); idx++) {
+				LOG_DEBUG("eCos: %s 0x%016" PRIX64 " %s",
+					rtos->symbols[idx].optional ? "OPTIONAL" : "        ",
+					rtos->symbols[idx].address, rtos->symbols[idx].symbol_name);
+			}
+		}
+
+		/* If "__ecospro_syminfo.size.cyg_thread.list_next" is non-zero then we
+		 * expect all of the generic thread structure symbols to have been
+		 * provided. */
+		symbol_address_t thread_next_size = ecos_value(rtos, ECOS_VAL_COMMON_THREAD_NEXT_SIZE);
+		if (thread_next_size != 0) {
+			param->pointer_width = thread_next_size;
+			param->uid_width = ecos_value(rtos, ECOS_VAL_COMMON_THREAD_ID_SIZE);
+			param->state_width = ecos_value(rtos, ECOS_VAL_COMMON_THREAD_STATE_SIZE);
+			param->thread_stack_offset = ecos_value(rtos, ECOS_VAL_COMMON_THREAD_STACK_OFF);
+			param->thread_name_offset = ecos_value(rtos, ECOS_VAL_COMMON_THREAD_NAME_OFF);
+			param->thread_state_offset = ecos_value(rtos, ECOS_VAL_COMMON_THREAD_STATE_OFF);
+			param->thread_next_offset = ecos_value(rtos, ECOS_VAL_COMMON_THREAD_NEXT_OFF);
+			param->thread_uniqueid_offset = ecos_value(rtos, ECOS_VAL_COMMON_THREAD_ID_OFF);
+		}
+
+		if (param->uid_width != sizeof(uint16_t)) {
+			/* Currently all eCos configurations use a 16-bit field to hold the
+			 * unique thread ID. */
+			LOG_WARNING("eCos: Unexpected unique_id width %" PRIu8, param->uid_width);
+			param->uid_width = (unsigned char)sizeof(uint16_t);
+		}
+
+		param->stacking_info = NULL;
+		param->flush_common = false;
+	}
+
+	return ERROR_OK;
+}
+
+/* The Cortex-M eCosPro "thread" contexts have a "type" indicator, which tracks
+ * the context state of (THREAD | EXCEPTION | INTERRUPT) and whether FPU
+ * registers are saved.
+ *
+ * For thread-aware debugging from GDB we are only interested in THREAD states
+ * and so do not need to implement support for INTERRUPT or EXCEPTION thread
+ * contexts since this code does not expose those stack contexts via the
+ * constructed thread list support. */
+static int ecos_stack_layout_cortexm(struct rtos *rtos,
+		struct ecos_params *param, int64_t stack_ptr,
+		const struct rtos_register_stacking **si)
+{
+	int retval = ERROR_OK;
+
+	/* CONSIDER: We could return
+	 * ecos_value(rtos, ECOS_VAL_CORTEXM_THREAD_SAVED) as the actual PC
+	 * address of a context switch, with the LR being set to the context PC
+	 * field to give a true representation of where the thread switch
+	 * occurs. However that would require extending the common
+	 * rtos_generic_stack_read() code with suitable support for applying a
+	 * supplied value, or just implementing our own version of that code that
+	 * can inject data into what is passed onwards to GDB. */
+
+	/* UPDATE: When we can return VFP register state then we will NOT be
+	 * basing the cached state on the single param->stacking_info value,
+	 * since we will need a different stacking_info structure returned for
+	 * each thread type when FPU support is enabled. The use of the single
+	 * param->stacking_info is a holder whilst we are limited to the fixed
+	 * ARMV7M_NUM_CORE_REGS set of descriptors. */
+
+	if (!param->stacking_info &&
+		ecos_value(rtos, ECOS_VAL_CORTEXM_THREAD_SAVED) &&
+		ecos_value(rtos, ECOS_VAL_CORTEXM_VAL_THREAD)) {
+		unsigned char numoutreg = ECOS_CORTEXM_BASE_NUMREGS;
+
+		rtos_ecos_stacking.stack_registers_size = ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_THREAD_SIZE);
+		rtos_ecos_stacking.calculate_process_stack = rtos_generic_stack_align8;
+		rtos_ecos_stacking.register_offsets = rtos_ecos_regoff_cortexm;
+
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_R0].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x00);
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_R1].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x04);
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_R2].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x08);
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_R3].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x0C);
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_R4].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x10);
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_R5].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x14);
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_R6].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x18);
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_R7].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x1C);
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_R8].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x20);
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_R9].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x24);
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_R10].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x28);
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_R11].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x2C);
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_R12].offset = (ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_REG_OFF) + 0x30);
+		/* Rather than using the stacked ECOS_VAL_CORTEXM_CTX_SP_OFF
+		 * value we force the reported sp to be after the stacked
+		 * register context. */
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_R13].offset = -2;
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_R14].offset = -1;
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_PC].offset = ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_PC_OFF);
+		rtos_ecos_regoff_cortexm[ECOS_REGLIST_XPSR].offset = -1;
+
+		param->stacking_info = &rtos_ecos_stacking;
+
+		/* Common Cortex-M thread register offsets for the current
+		 * symbol table: */
+		if (retval == ERROR_OK && param->stacking_info) {
+			if (numoutreg > ECOS_REGLIST_BASEPRI) {
+				rtos_ecos_regoff_cortexm[ECOS_REGLIST_BASEPRI].offset =
+					ecos_value(rtos, ECOS_VAL_CORTEXM_CTX_BASEPRI_OFF);
+			}
+
+			rtos_ecos_stacking.num_output_registers = numoutreg;
+		}
+	}
+
+	if (si)
+		*si = param->stacking_info;
+
+	return retval;
+}
+
+static int ecos_stack_layout_arm(struct rtos *rtos, struct ecos_params *param,
+		int64_t stack_ptr, const struct rtos_register_stacking **si)
+{
+	int retval = ERROR_OK;
+
+	if (!param->stacking_info && ecos_value(rtos, ECOS_VAL_ARM_REGSIZE)) {
+		/* When OpenOCD is extended to allow FPU registers to be returned from a
+		 * stacked thread context we can check:
+		 *		if (0 != ecos_value(rtos, ECOS_VAL_ARM_FPUSIZE)) { FPU }
+		 * for presence of FPU registers in the context. */
+
+		rtos_ecos_stacking.stack_registers_size = ecos_value(rtos, ECOS_VAL_ARM_REGSIZE);
+		rtos_ecos_stacking.num_output_registers = ARRAY_SIZE(rtos_ecos_regoff_arm);
+		rtos_ecos_stacking.register_offsets = rtos_ecos_regoff_arm;
+
+		rtos_ecos_regoff_arm[0].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R0_OFF);
+		rtos_ecos_regoff_arm[1].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R1_OFF);
+		rtos_ecos_regoff_arm[2].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R2_OFF);
+		rtos_ecos_regoff_arm[3].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R3_OFF);
+		rtos_ecos_regoff_arm[4].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R4_OFF);
+		rtos_ecos_regoff_arm[5].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R5_OFF);
+		rtos_ecos_regoff_arm[6].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R6_OFF);
+		rtos_ecos_regoff_arm[7].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R7_OFF);
+		rtos_ecos_regoff_arm[8].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R8_OFF);
+		rtos_ecos_regoff_arm[9].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R9_OFF);
+		rtos_ecos_regoff_arm[10].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_R10_OFF);
+		rtos_ecos_regoff_arm[11].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_FP_OFF);
+		rtos_ecos_regoff_arm[12].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_IP_OFF);
+		rtos_ecos_regoff_arm[13].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_SP_OFF);
+		rtos_ecos_regoff_arm[14].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_LR_OFF);
+		rtos_ecos_regoff_arm[15].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_PC_OFF);
+		rtos_ecos_regoff_arm[16].offset = ecos_value(rtos, ECOS_VAL_ARM_CTX_CPSR_OFF);
+
+		param->stacking_info = &rtos_ecos_stacking;
+	}
+
+	if (si)
+		*si = param->stacking_info;
+
+	return retval;
+}
+
+/* We see this function called on a new connection, it looks like before and
+ * after the "tar rem"/"tar extended-remote". It might be the only point we can
+ * decide to cache information (to check if the symbol table has changed). */
 static int ecos_update_threads(struct rtos *rtos)
 {
 	int retval;
 	int tasks_found = 0;
 	int thread_list_size = 0;
-	const struct ecos_params *param;
+	struct ecos_params *param;
 
 	if (!rtos)
 		return -1;
 
+	/* wipe out previous thread details if any */
+	rtos_free_threadlist(rtos);
+
 	if (!rtos->rtos_specific_params)
 		return -3;
 
-	param = (const struct ecos_params *) rtos->rtos_specific_params;
+	param = rtos->rtos_specific_params;
 
 	if (!rtos->symbols) {
+		/* NOTE: We only see this when connecting from GDB the first
+		 * time before the application image is loaded. So it is not a
+		 * hook for detecting an application change. */
+		param->flush_common = true;
 		LOG_ERROR("No symbols for eCos");
 		return -4;
 	}
 
+	retval = ecos_check_app_info(rtos, param);
+	if (retval != ERROR_OK)
+		return retval;
+
 	if (rtos->symbols[ECOS_VAL_THREAD_LIST].address == 0) {
 		LOG_ERROR("Don't have the thread list head");
 		return -2;
 	}
 
-	/* wipe out previous thread details if any */
-	rtos_free_threadlist(rtos);
-
 	/* determine the number of current threads */
 	uint32_t thread_list_head = rtos->symbols[ECOS_VAL_THREAD_LIST].address;
 	uint32_t thread_index;
@@ -120,50 +746,82 @@ static int ecos_update_threads(struct rtos *rtos)
 		param->pointer_width,
 		(uint8_t *) &thread_index);
 	uint32_t first_thread = thread_index;
-	do {
-		thread_list_size++;
-		retval = target_read_buffer(rtos->target,
-				thread_index + param->thread_next_offset,
-				param->pointer_width,
-				(uint8_t *) &thread_index);
-		if (retval != ERROR_OK)
-			return retval;
-	} while (thread_index != first_thread);
+
+	/* Even if 0==first_thread indicates a system with no defined eCos
+	 * threads, instead of early exiting here we fall through the code to
+	 * allow the creation of a faked "Current Execution" descriptor as
+	 * needed. */
+
+	if (first_thread) {
+		/* Since the OpenOCD RTOS support can attempt to obtain thread
+		 * information on initial connection when the system *may* have
+		 * undefined memory state it is possible for a simple thread count scan
+		 * to produce invalid results. To avoid blocking indefinitely when
+		 * encountering an invalid closed loop we limit the number of threads to
+		 * the maximum possible, and if we pass that limit then something is
+		 * wrong so treat the system as having no threads defined. */
+		do {
+			thread_list_size++;
+			if (thread_list_size > ECOS_MAX_THREAD_COUNT) {
+				/* Treat as "no threads" case: */
+				first_thread = 0;
+				thread_list_size = 0;
+				break;
+			}
+			retval = target_read_buffer(rtos->target,
+					thread_index + param->thread_next_offset,
+					param->pointer_width,
+					(uint8_t *)&thread_index);
+			if (retval != ERROR_OK)
+				return retval;
+		} while (thread_index != first_thread);
+	}
 
 	/* read the current thread id */
+	rtos->current_thread = 0;
+
 	uint32_t current_thread_addr;
 	retval = target_read_buffer(rtos->target,
 			rtos->symbols[ECOS_VAL_CURRENT_THREAD_PTR].address,
-			4,
+			param->pointer_width,
 			(uint8_t *)&current_thread_addr);
-	if (retval != ERROR_OK)
-		return retval;
-	rtos->current_thread = 0;
-	retval = target_read_buffer(rtos->target,
-			current_thread_addr + param->thread_uniqueid_offset,
-			2,
-			(uint8_t *)&rtos->current_thread);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("Could not read eCos current thread from target");
+		LOG_ERROR("Reading active thread address");
 		return retval;
 	}
 
-	if ((thread_list_size  == 0) || (rtos->current_thread == 0)) {
+	if (current_thread_addr) {
+		uint16_t id = 0;
+		retval = target_read_buffer(rtos->target,
+				current_thread_addr + param->thread_uniqueid_offset,
+				param->uid_width,
+				(uint8_t *)&id);
+		if (retval != ERROR_OK) {
+			LOG_ERROR("Could not read eCos current thread from target");
+			return retval;
+		}
+		rtos->current_thread = (threadid_t)id;
+	}
+
+	if (thread_list_size == 0 || rtos->current_thread == 0) {
 		/* Either : No RTOS threads - there is always at least the current execution though */
 		/* OR     : No current thread - all threads suspended - show the current execution
 		 * of idling */
-		char tmp_str[] = "Current Execution";
+		static const char tmp_str[] = "Current Execution";
 		thread_list_size++;
 		tasks_found++;
 		rtos->thread_details = malloc(
 				sizeof(struct thread_detail) * thread_list_size);
-		rtos->thread_details->threadid = 1;
+		/* 1 is a valid eCos thread id, so we return 0 for this faked
+		 * "current" CPU state: */
+		rtos->thread_details->threadid = 0;
 		rtos->thread_details->exists = true;
 		rtos->thread_details->extra_info_str = NULL;
 		rtos->thread_details->thread_name_str = malloc(sizeof(tmp_str));
 		strcpy(rtos->thread_details->thread_name_str, tmp_str);
 
-		if (thread_list_size == 0) {
+		/* Early exit if current CPU state our only "thread": */
+		if (thread_list_size == 1) {
 			rtos->thread_count = 1;
 			return ERROR_OK;
 		}
@@ -176,18 +834,18 @@ static int ecos_update_threads(struct rtos *rtos)
 	/* loop over all threads */
 	thread_index = first_thread;
 	do {
-
 		#define ECOS_THREAD_NAME_STR_SIZE (200)
 		char tmp_str[ECOS_THREAD_NAME_STR_SIZE];
-		unsigned int i = 0;
 		uint32_t name_ptr = 0;
 		uint32_t prev_thread_ptr;
 
-		/* Save the thread pointer */
-		uint16_t thread_id;
+		/* Save the thread ID. For eCos the thread has a unique ID distinct from
+		 * the thread_index descriptor pointer. We present this scheduler ID
+		 * instead of the descriptor memory address. */
+		uint16_t thread_id = 0;
 		retval = target_read_buffer(rtos->target,
 				thread_index + param->thread_uniqueid_offset,
-				2,
+				param->uid_width,
 				(uint8_t *)&thread_id);
 		if (retval != ERROR_OK) {
 			LOG_ERROR("Could not read eCos thread id from target");
@@ -195,7 +853,7 @@ static int ecos_update_threads(struct rtos *rtos)
 		}
 		rtos->thread_details[tasks_found].threadid = thread_id;
 
-		/* read the name pointer */
+		/* Read the name pointer */
 		retval = target_read_buffer(rtos->target,
 				thread_index + param->thread_name_offset,
 				param->pointer_width,
@@ -217,8 +875,26 @@ static int ecos_update_threads(struct rtos *rtos)
 		}
 		tmp_str[ECOS_THREAD_NAME_STR_SIZE-1] = '\x00';
 
-		if (tmp_str[0] == '\x00')
-			strcpy(tmp_str, "No Name");
+		/* Since eCos can have arbitrary C string names we can sometimes
+		 * get an internal warning from GDB about "not well-formed
+		 * (invalid token)" since the XML post-processing done by GDB on
+		 * the OpenOCD returned response containing the thread strings
+		 * is not escaped. For example the eCos kernel testsuite
+		 * application tm_basic uses the thread name "<<NULL>>" which
+		 * will trigger this failure unless escaped. */
+		if (tmp_str[0] == '\x00') {
+			snprintf(tmp_str, ECOS_THREAD_NAME_STR_SIZE, "NoName:[0x%08" PRIX32 "]", thread_index);
+		} else {
+			/* The following is a workaround to avoid any issues
+			 * from arbitrary eCos thread names causing GDB/OpenOCD
+			 * issues. We limit the escaped thread name passed to
+			 * GDB to the same length as the un-escaped just to
+			 * avoid overly long strings. */
+			char esc_str[ECOS_THREAD_NAME_STR_SIZE];
+			bool escaped = ecos_escape_string(tmp_str, esc_str, sizeof(esc_str));
+			if (escaped)
+				strcpy(tmp_str, esc_str);
+		}
 
 		rtos->thread_details[tasks_found].thread_name_str =
 			malloc(strlen(tmp_str)+1);
@@ -228,28 +904,109 @@ static int ecos_update_threads(struct rtos *rtos)
 		int64_t thread_status = 0;
 		retval = target_read_buffer(rtos->target,
 				thread_index + param->thread_state_offset,
-				4,
+				param->state_width,
 				(uint8_t *)&thread_status);
 		if (retval != ERROR_OK) {
 			LOG_ERROR("Error reading thread state from eCos target");
 			return retval;
 		}
 
-		for (i = 0; (i < ECOS_NUM_STATES) && (ecos_thread_states[i].value != thread_status); i++) {
-			/*
-			 * empty
-			 */
-		}
+		/* The thread_status is a BITMASK */
+		char state_desc[21];		/* Enough for "suspended+countsleep\0" maximum */
 
-		const char *state_desc;
-		if  (i < ECOS_NUM_STATES)
-			state_desc = ecos_thread_states[i].desc;
+		if (thread_status & SUSPENDED)
+			strcpy(state_desc, "suspended+");
 		else
-			state_desc = "Unknown state";
+			state_desc[0] = '\0';
+
+		switch (thread_status & ~SUSPENDED) {
+		case RUNNING:
+			if (thread_index == current_thread_addr)
+				strcat(state_desc, "running");
+			else if (thread_status & SUSPENDED)
+				state_desc[9] = '\0';	/* Drop '+' from "suspended+" */
+			else
+				strcat(state_desc, "ready");
+			break;
+		case SLEEPING:
+			strcat(state_desc, "sleeping");
+			break;
+		case SLEEPSET:
+		case COUNTSLEEP:
+			strcat(state_desc, "counted sleep");
+			break;
+		case CREATING:
+			strcpy(state_desc, "creating");
+			break;
+		case EXITED:
+			strcpy(state_desc, "exited");
+			break;
+		default:
+			strcpy(state_desc, "unknown state");
+			break;
+		}
+
+		/* For the moment we do not bother decoding the wake reason for the
+		 * active "running" thread, but it is useful providing the sleep reason
+		 * for stacked threads. */
+		int64_t sleep_reason = 0; /* sleep reason */
+
+		if (thread_index != current_thread_addr &&
+			ecos_value(rtos, ECOS_VAL_COMMON_THREAD_SLEEP_SIZE)) {
+			retval = target_read_buffer(rtos->target,
+				(thread_index + ecos_value(rtos, ECOS_VAL_COMMON_THREAD_SLEEP_OFF)),
+				ecos_value(rtos, ECOS_VAL_COMMON_THREAD_SLEEP_SIZE),
+				(uint8_t *)&sleep_reason);
+			if (retval != ERROR_OK) {
+				LOG_ERROR("Error reading thread sleep reason from eCos target");
+				return retval;
+			}
+			if (sleep_reason < 0 ||
+				sleep_reason > (int64_t)ARRAY_SIZE(ecos_thread_reasons)) {
+				sleep_reason = 0;
+			}
+		}
+
+		/* We do not display anything for the Cyg_Thread::NONE reason */
+		size_t tr_extra = 0;
+		const char *reason_desc = NULL;
+		if (sleep_reason)
+			reason_desc = ecos_thread_reasons[sleep_reason].desc;
+		if (reason_desc)
+			tr_extra = 2 + strlen(reason_desc) + 1;
 
-		rtos->thread_details[tasks_found].extra_info_str = malloc(strlen(
-					state_desc)+8);
-		sprintf(rtos->thread_details[tasks_found].extra_info_str, "State: %s", state_desc);
+		/* Display thread priority if available: */
+		int64_t priority = 0;
+		size_t pri_extra = 0;
+		if (ecos_value(rtos, ECOS_VAL_COMMON_THREAD_PRI_SIZE)) {
+			retval = target_read_buffer(rtos->target,
+				(thread_index + ecos_value(rtos, ECOS_VAL_COMMON_THREAD_PRI_OFF)),
+				ecos_value(rtos, ECOS_VAL_COMMON_THREAD_PRI_SIZE),
+				(uint8_t *)&priority);
+			if (retval != ERROR_OK) {
+				LOG_ERROR("Error reading thread priority from eCos target");
+				return retval;
+			}
+			pri_extra = (12 + 20); /* worst-case ", Priority: " */
+		}
+
+		size_t eilen = (8 + strlen(state_desc) + tr_extra + pri_extra);
+		char *eistr = malloc(eilen);
+		/* We do not need to treat a malloc failure as a fatal error here since
+		 * the code below will just not report extra thread information if NULL,
+		 * thus allowing all of the threads to be enumerated even with reduced
+		 * information when the host is low on memory. However... */
+		if (!eistr) {
+			LOG_ERROR("OOM allocating extra information buffer");
+			return ERROR_FAIL;
+		}
+
+		int soff = snprintf(eistr, eilen, "State: %s", state_desc);
+		if (tr_extra && reason_desc)
+			soff += snprintf(&eistr[soff], (eilen - soff), " (%s)", reason_desc);
+		if (pri_extra)
+			(void)snprintf(&eistr[soff], (eilen - soff), ", Priority: %" PRId64 "", priority);
+		rtos->thread_details[tasks_found].extra_info_str = eistr;
 
 		rtos->thread_details[tasks_found].exists = true;
 
@@ -269,14 +1026,14 @@ static int ecos_update_threads(struct rtos *rtos)
 	} while (thread_index != first_thread);
 
 	rtos->thread_count = tasks_found;
-	return 0;
+	return ERROR_OK;
 }
 
 static int ecos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
 		struct rtos_reg **reg_list, int *num_regs)
 {
 	int retval;
-	const struct ecos_params *param;
+	struct ecos_params *param;
 
 	if (!rtos)
 		return -1;
@@ -287,7 +1044,22 @@ static int ecos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
 	if (!rtos->rtos_specific_params)
 		return -3;
 
-	param = (const struct ecos_params *) rtos->rtos_specific_params;
+	param = rtos->rtos_specific_params;
+
+	retval = ecos_check_app_info(rtos, param);
+	if (retval != ERROR_OK)
+		return retval;
+
+	/* We can get memory access errors reported by this function on
+	 * re-connecting to a board with stale thread information in memory. The
+	 * initial ecos_update_threads() is called twice and may read
+	 * stale/invalid information depending on the memory state. This happens
+	 * as part of the "target remote" connection so cannot be avoided by GDB
+	 * scripting. It is not critical and allowing the application to run and
+	 * initialise its BSS etc. will allow correct thread and register
+	 * information to be obtained. This really only affects debug sessions
+	 * where "info thr" is used before the initial run-time initialisation
+	 * has occurred. */
 
 	/* Find the thread with that thread id */
 	uint16_t id = 0;
@@ -299,10 +1071,10 @@ static int ecos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
 	while (!done) {
 		retval = target_read_buffer(rtos->target,
 				thread_index + param->thread_uniqueid_offset,
-				2,
+				param->uid_width,
 				(uint8_t *)&id);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("Error reading unique id from eCos thread");
+			LOG_ERROR("Error reading unique id from eCos thread 0x%08" PRIX32 "", thread_index);
 			return retval;
 		}
 
@@ -328,8 +1100,24 @@ static int ecos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
 			return retval;
 		}
 
+		if (!stack_ptr) {
+			LOG_ERROR("NULL stack pointer in thread %" PRIu64, thread_id);
+			return -5;
+		}
+
+		const struct rtos_register_stacking *stacking_info = NULL;
+		if (param->target_stack_layout) {
+			retval = param->target_stack_layout(rtos, param, stack_ptr, &stacking_info);
+			if (retval != ERROR_OK) {
+				LOG_ERROR("Error reading stack layout for eCos thread");
+				return retval;
+			}
+		}
+		if (!stacking_info)
+			stacking_info = &rtos_ecos_cortex_m3_stacking;
+
 		return rtos_generic_stack_read(rtos->target,
-			param->stacking_info,
+			stacking_info,
 			stack_ptr,
 			reg_list,
 			num_regs);
@@ -338,18 +1126,31 @@ static int ecos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
 	return -1;
 }
 
+/* NOTE: This is only called once when the first GDB connection is made to
+ * OpenOCD and not on subsequent connections (when the application symbol table
+ * may have changed, affecting the offsets of critical fields and the stacked
+ * context shape). */
 static int ecos_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[])
 {
 	unsigned int i;
 	*symbol_list = calloc(
 			ARRAY_SIZE(ecos_symbol_list), sizeof(struct symbol_table_elem));
 
-	for (i = 0; i < ARRAY_SIZE(ecos_symbol_list); i++)
-		(*symbol_list)[i].symbol_name = ecos_symbol_list[i];
+	/* If the target reference was passed into this function we could limit
+	 * the symbols we need to lookup to the target->type->name based
+	 * range. For the moment we need to provide a single vector with all of
+	 * the symbols across all of the supported architectures. */
+	for (i = 0; i < ARRAY_SIZE(ecos_symbol_list); i++) {
+		(*symbol_list)[i].symbol_name = ecos_symbol_list[i].name;
+		(*symbol_list)[i].optional = ecos_symbol_list[i].optional;
+	}
 
 	return 0;
 }
 
+/* NOTE: Only called by rtos.c:rtos_qsymbol() when auto-detecting the RTOS. If
+ * the target configuration uses the explicit "-rtos" config option then this
+ * detection routine is NOT called. */
 static bool ecos_detect_rtos(struct target *target)
 {
 	if ((target->rtos->symbols) &&
@@ -360,15 +1161,67 @@ static bool ecos_detect_rtos(struct target *target)
 	return false;
 }
 
+extern int rtos_thread_packet(struct connection *connection,
+		const char *packet, int packet_size);
+
+/* Since we should never have 0 as a valid eCos thread ID we use $Hg0 as the
+ * indicator of a new session as regards flushing any cached state. */
+static int ecos_packet_hook(struct connection *connection,
+		const char *packet, int packet_size)
+{
+	int64_t current_threadid;
+
+	if (packet[0] == 'H' && packet[1] == 'g') {
+		int numscan = sscanf(packet, "Hg%16" SCNx64, &current_threadid);
+		if (numscan == 1 && current_threadid == 0) {
+			struct target *target = get_target_from_connection(connection);
+			if (target && target->rtos && target->rtos->rtos_specific_params) {
+				struct ecos_params *param;
+				param = target->rtos->rtos_specific_params;
+				param->flush_common = true;
+			}
+		}
+	}
+
+	return rtos_thread_packet(connection, packet, packet_size);
+}
+
+/* Called at start of day when eCos detected or specified in config file. */
 static int ecos_create(struct target *target)
 {
-	for (unsigned int i = 0; i < ARRAY_SIZE(ecos_params_list); i++)
-		if (strcmp(ecos_params_list[i].target_name, target->type->name) == 0) {
-			target->rtos->rtos_specific_params = (void *)&ecos_params_list[i];
-			target->rtos->current_thread = 0;
-			target->rtos->thread_details = NULL;
-			return 0;
+	for (unsigned int i = 0; i < ARRAY_SIZE(ecos_params_list); i++) {
+		const char * const *tnames = ecos_params_list[i].target_names;
+		while (*tnames) {
+			if (strcmp(*tnames, target->type->name) == 0) {
+				/* LOG_DEBUG("eCos: matched target \"%s\"", target->type->name); */
+				target->rtos->rtos_specific_params = (void *)&ecos_params_list[i];
+				ecos_params_list[i].flush_common = true;
+				ecos_params_list[i].stacking_info = NULL;
+				target->rtos->current_thread = 0;
+				target->rtos->thread_details = NULL;
+
+				/* We use the $Hg0 packet as a new GDB connection "start-of-day" hook to
+				 * force a re-cache of information. It is possible for a single OpenOCD
+				 * session to be connected to a target with multiple GDB debug sessions
+				 * started/stopped. With eCos it is possible for those GDB sessions to
+				 * present applications with different offsets within a thread
+				 * descriptor for fields used by this module, and for the stacked
+				 * context within the connected target architecture to differ between
+				 * applications and even between threads in a single application. So we
+				 * need to ensure any information we cache is flushed on an application
+				 * change, and GDB referencing an invalid eCos thread ID (0) is a good
+				 * enough point, since we can accept the re-cache hit if that packet
+				 * appears during an established session, whilst benefiting from not
+				 * re-loading information on every update_threads or get_thread_reg_list
+				 * call. */
+				target->rtos->gdb_thread_packet = ecos_packet_hook;
+				/* We do not currently use the target->rtos->gdb_target_for_threadid
+				 * hook. */
+				return 0;
+			}
+			tnames++;
 		}
+	}
 
 	LOG_ERROR("Could not find target in eCos compatibility list");
 	return -1;
diff --git a/src/rtos/rtos_ecos_stackings.c b/src/rtos/rtos_ecos_stackings.c
index 0f54e86f7..86e176507 100644
--- a/src/rtos/rtos_ecos_stackings.c
+++ b/src/rtos/rtos_ecos_stackings.c
@@ -8,6 +8,13 @@
 #include "rtos_standard_stackings.h"
 #include "target/armv7m.h"
 
+/* For Cortex-M eCos applications the actual thread context register layout can
+ * be different between active threads of an application depending on whether
+ * the FPU is in use, configured for lazy FPU context saving, etc. */
+
+/* Default fixed thread register context description used for older eCos
+ * application builds without the necessary symbolic information describing the
+ * actual configuration-dependent offsets. */
 static const struct stack_register_offset rtos_ecos_cortex_m3_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
 	{ ARMV7M_R0,   0x0c, 32 },		/* r0   */
 	{ ARMV7M_R1,   0x10, 32 },		/* r1   */

-----------------------------------------------------------------------

Summary of changes:
 src/rtos/eCos.c                | 1033 ++++++++++++++++++++++++++++++++++++----
 src/rtos/rtos_ecos_stackings.c |    7 +
 2 files changed, 950 insertions(+), 90 deletions(-)


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- Log -----------------------------------------------------------------
commit 9a7781ff8c9dea6ef5998238b1932094b8a226da
Author: Fawaz Tirmizi <fa...@ri...>
Date:   Fri Aug 19 14:22:06 2022 -0700

    flash/nor/spi: Add issi is25lq040b to device list
    
    The HiFive Inventor uses this flash chip, so adding it will allow for
    openocd to be used to program it. These values were taken from the
    chip's documentation.
    
    Signed-off-by: Fawaz Tirmizi <fa...@ri...>
    Change-Id: I15c9d35f99d4500f73134cdc2d1b9ab6279b491c
    Reviewed-on: https://review.openocd.org/c/openocd/+/7135
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/flash/nor/spi.c b/src/flash/nor/spi.c
index eed747b58..373a9a144 100644
--- a/src/flash/nor/spi.c
+++ b/src/flash/nor/spi.c
@@ -112,6 +112,7 @@ const struct flash_device flash_devices[] = {
 	FLASH_ID("gd gd25q128c",        0x03, 0xeb, 0x02, 0xd8, 0xc7, 0x001840c8, 0x100, 0x10000, 0x1000000),
 	FLASH_ID("gd gd25q256c",        0x13, 0x00, 0x12, 0xdc, 0xc7, 0x001940c8, 0x100, 0x10000, 0x2000000),
 	FLASH_ID("gd gd25q512mc",       0x13, 0x00, 0x12, 0xdc, 0xc7, 0x002040c8, 0x100, 0x10000, 0x4000000),
+	FLASH_ID("issi is25lq040b",     0x03, 0xeb, 0x02, 0x20, 0xc7, 0x0013409d, 0x100, 0x1000,  0x80000),
 	FLASH_ID("issi is25lp032",      0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0016609d, 0x100, 0x10000, 0x400000),
 	FLASH_ID("issi is25lp064",      0x03, 0x00, 0x02, 0xd8, 0xc7, 0x0017609d, 0x100, 0x10000, 0x800000),
 	FLASH_ID("issi is25lp128d",     0x03, 0xeb, 0x02, 0xd8, 0xc7, 0x0018609d, 0x100, 0x10000, 0x1000000),

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/spi.c | 1 +
 1 file changed, 1 insertion(+)


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- Log -----------------------------------------------------------------
commit 0708ccead4fbce07e3d78bb7380aca0aae8cb14d
Author: Erhan Kurubas <erh...@es...>
Date:   Thu Sep 29 00:22:00 2022 +0200

    target/xtensa: remove needless target_was_examined check
    
    In any case flag will be set as examined.
    
    Signed-off-by: Erhan Kurubas <erh...@es...>
    Change-Id: I5177ee656f726a807269e2f4725223f50e49e855
    Reviewed-on: https://review.openocd.org/c/openocd/+/7231
    Tested-by: jenkins
    Reviewed-by: Ian Thompson <ia...@ca...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index c2c047edb..b57e2d660 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -801,8 +801,7 @@ int xtensa_examine(struct target *target)
 		return ERROR_TARGET_FAILURE;
 	}
 	LOG_DEBUG("OCD_ID = %08" PRIx32, xtensa->dbg_mod.device_id);
-	if (!target_was_examined(target))
-		target_set_examined(target);
+	target_set_examined(target);
 	xtensa_smpbreak_write(xtensa, xtensa->smp_break);
 	return ERROR_OK;
 }

-----------------------------------------------------------------------

Summary of changes:
 src/target/xtensa/xtensa.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)


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- Log -----------------------------------------------------------------
commit 0c28006cf2cf2d98ba2d73a73bf629e781f4ffb8
Author: Kyle Schwarz <ze...@gm...>
Date:   Sun Jul 10 15:58:14 2022 -0400

    flash/nor/avrf: add ATmega32U4 support
    
    Add new chip info and tcl target
    
    Change-Id: Ib9d33d1b145a8659857b7a6cc9c5acba047f41d1
    Signed-off-by: Kyle Schwarz <ze...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7081
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/flash/nor/avrf.c b/src/flash/nor/avrf.c
index 0e2e263ce..1d317a10c 100644
--- a/src/flash/nor/avrf.c
+++ b/src/flash/nor/avrf.c
@@ -64,6 +64,7 @@ static const struct avrf_type avft_chips_info[] = {
 	{"atmega324pa", 0x9511, 128, 256, 4, 256},
 	{"atmega644p", 0x960a, 256, 256, 8, 256},
 	{"atmega1284p", 0x9705, 256, 512, 8, 512},
+	{"atmega32u4", 0x9587, 128, 256, 4, 256},
 };
 
 /* avr program functions */
diff --git a/tcl/target/atmega32u4.cfg b/tcl/target/atmega32u4.cfg
new file mode 100644
index 000000000..9199c741e
--- /dev/null
+++ b/tcl/target/atmega32u4.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# ATmega32U4
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME avr
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4958703f
+}
+
+adapter speed 4500
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/avrf.c                             |  1 +
 tcl/target/{atmega128rfa1.cfg => atmega32u4.cfg} | 26 +++++++++++++++---------
 2 files changed, 17 insertions(+), 10 deletions(-)
 copy tcl/target/{atmega128rfa1.cfg => atmega32u4.cfg} (53%)


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- Log -----------------------------------------------------------------
commit 95603fae18f81eebdafc5b318e70f9e2cdefab9e
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Dec 18 19:15:57 2022 +0100

    openocd: revert workarounds for 'expr' syntax change
    
    With OpenOCD v0.12.0 released, drop the workarounds for 'expr'
    syntax change by reverting:
    - commit 320043c054dc ("openocd: fix for polling during "expr"
      computation");
    - commit c7eaaf620488 ("openocd: prepare for jimtcl 0.81 'expr'
      syntax change").
    
    Replace the call to target_call_timer_callbacks_now() with call
    to target_call_timer_callbacks().
    
    Change-Id: Iae5afc50e3f688e11176a52648efc9a6577a9a11
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7405
    Tested-by: jenkins

diff --git a/src/helper/command.c b/src/helper/command.c
index 6898e2d7c..ca66cf7dd 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -936,19 +936,7 @@ static int jim_command_dispatch(Jim_Interp *interp, int argc, Jim_Obj * const *a
 	if (!command_can_run(cmd_ctx, c, Jim_GetString(argv[0], NULL)))
 		return JIM_ERR;
 
-	/*
-	 * TODO: to be removed after v0.12.0
-	 * workaround for https://sourceforge.net/p/openocd/tickets/362/
-	 * After syntax change of "expr" in jimtcl 0.81
-	 * the replacement of jimtcl "expr" with openocd version in
-	 * https://review.openocd.org/6510/
-	 * introduces too many target polling during math expressions with
-	 * "expr" commands.
-	 * After v0.12.0 replace the following two lines with
-	 * target_call_timer_callbacks();
-	 */
-	if (strcmp(c->name, "expr"))
-		target_call_timer_callbacks_now();
+	target_call_timer_callbacks();
 
 	/*
 	 * Black magic of overridden current target:
diff --git a/src/openocd.c b/src/openocd.c
index bef084f98..875da5a62 100644
--- a/src/openocd.c
+++ b/src/openocd.c
@@ -230,65 +230,6 @@ static int openocd_register_commands(struct command_context *cmd_ctx)
 	return register_commands(cmd_ctx, NULL, openocd_command_handlers);
 }
 
-/*
- * TODO: to be removed after v0.12.0
- * workaround for syntax change of "expr" in jimtcl 0.81
- * replace "expr" with openocd version that prints the deprecated msg
- */
-struct jim_scriptobj {
-	void *token;
-	Jim_Obj *filename_obj;
-	int len;
-	int subst_flags;
-	int in_use;
-	int firstline;
-	int linenr;
-	int missing;
-};
-
-static int jim_expr_command(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
-{
-	if (argc == 2)
-		return Jim_EvalExpression(interp, argv[1]);
-
-	if (argc > 2) {
-		Jim_Obj *obj = Jim_ConcatObj(interp, argc - 1, argv + 1);
-		Jim_IncrRefCount(obj);
-		const char *s = Jim_String(obj);
-		struct jim_scriptobj *script = Jim_GetIntRepPtr(interp->currentScriptObj);
-		if (interp->currentScriptObj == interp->emptyObj ||
-				strcmp(interp->currentScriptObj->typePtr->name, "script") ||
-				script->subst_flags ||
-				script->filename_obj == interp->emptyObj)
-			LOG_WARNING("DEPRECATED! use 'expr { %s }' not 'expr %s'", s, s);
-		else
-			LOG_WARNING("DEPRECATED! (%s:%d) use 'expr { %s }' not 'expr %s'",
-						Jim_String(script->filename_obj), script->linenr, s, s);
-		int retcode = Jim_EvalExpression(interp, obj);
-		Jim_DecrRefCount(interp, obj);
-		return retcode;
-	}
-
-	Jim_WrongNumArgs(interp, 1, argv, "expression ?...?");
-	return JIM_ERR;
-}
-
-static const struct command_registration expr_handler[] = {
-	{
-		.name = "expr",
-		.jim_handler = jim_expr_command,
-		.mode = COMMAND_ANY,
-		.help = "",
-		.usage = "",
-	},
-	COMMAND_REGISTRATION_DONE
-};
-
-static int workaround_for_jimtcl_expr(struct command_context *cmd_ctx)
-{
-	return register_commands(cmd_ctx, NULL, expr_handler);
-}
-
 struct command_context *global_cmd_ctx;
 
 static struct command_context *setup_command_handler(Jim_Interp *interp)
@@ -301,7 +242,6 @@ static struct command_context *setup_command_handler(Jim_Interp *interp)
 	/* register subsystem commands */
 	typedef int (*command_registrant_t)(struct command_context *cmd_ctx_value);
 	static const command_registrant_t command_registrants[] = {
-		&workaround_for_jimtcl_expr,
 		&openocd_register_commands,
 		&server_register_commands,
 		&gdb_register_commands,

-----------------------------------------------------------------------

Summary of changes:
 src/helper/command.c | 14 +-----------
 src/openocd.c        | 60 ----------------------------------------------------
 2 files changed, 1 insertion(+), 73 deletions(-)


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- Log -----------------------------------------------------------------
commit da34e36cdb542eac9370957b10853184f870e495
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Sep 19 23:14:41 2022 +0200

    nds32: drop it, together with aice adapter driver
    
    The target nds32 and its companion adapter aice have not received
    any real improvement since 2013.
    It has been hard to keep them aligned during the evolution of
    OpenOCD code, with no way for maintainers to really check if they
    are still working.
    No real documentation is present for them in OpenOCD.
    The nds32 code triggers ~50 errors/warnings with scan-build.
    
    The arch nds32 has been dropped from Linux kernel v5.18-rc1.
    
    For all the reasons above, this code has been deprecated with
    commit 2e5df83de7f2 ("nds32: deprecate it, together with aice
    adapter driver") and tagged to be dropped before v0.13.0.
    
    Let it r.i.p. in OpenOCD git history.
    
    While there, drop from checkpatch list the camelcase symbols that
    where only used in this code.
    
    Change-Id: Ide52a217f2228e9da2f1cc5036c48f3536f26952
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7382
    Tested-by: jenkins

diff --git a/README b/README
index 08b8117db..2f71cfc6a 100644
--- a/README
+++ b/README
@@ -101,7 +101,7 @@ Supported hardware
 JTAG adapters
 -------------
 
-AICE, AM335x, ARM-JTAG-EW, ARM-USB-OCD, ARM-USB-TINY, AT91RM9200, axm0432, BCM2835,
+AM335x, ARM-JTAG-EW, ARM-USB-OCD, ARM-USB-TINY, AT91RM9200, axm0432, BCM2835,
 Bus Blaster, Buspirate, Cadence DPI, Cadence vdebug, Chameleon, CMSIS-DAP,
 Cortino, Cypress KitProg, DENX, Digilent JTAG-SMT2, DLC 5, DLP-USB1232H,
 embedded projects, Espressif USB JTAG Programmer,
@@ -122,7 +122,7 @@ Debug targets
 ARM: AArch64, ARM11, ARM7, ARM9, Cortex-A/R (v7-A/R), Cortex-M (ARMv{6/7/8}-M),
 FA526, Feroceon/Dragonite, XScale.
 ARCv2, AVR32, DSP563xx, DSP5680xx, EnSilica eSi-RISC, EJTAG (MIPS32, MIPS64),
-ESP32, ESP32-S2, ESP32-S3, Intel Quark, LS102x-SAP, NDS32, RISC-V, ST STM8,
+ESP32, ESP32-S2, ESP32-S3, Intel Quark, LS102x-SAP, RISC-V, ST STM8,
 Xtensa.
 
 Flash drivers
diff --git a/configure.ac b/configure.ac
index 4fcc91528..cc7139c7c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -130,9 +130,6 @@ m4_define([USB1_ADAPTERS],
 	[[usbprog], [USBProg JTAG Programmer], [USBPROG]],
 	[[esp_usb_jtag], [Espressif JTAG Programmer], [ESP_USB_JTAG]]])
 
-m4_define([DEPRECATED_USB1_ADAPTERS],
-	[[[aice], [Andes JTAG Programmer (deprecated)], [AICE]]])
-
 m4_define([HIDAPI_ADAPTERS],
 	[[[cmsis_dap], [CMSIS-DAP Compliant Debugger], [CMSIS_DAP_HID]],
 	[[nulink], [Nu-Link Programmer], [HLADAPTER_NULINK]]])
@@ -264,8 +261,6 @@ AC_ARG_ADAPTERS([
   LIBJAYLINK_ADAPTERS
   ],[auto])
 
-AC_ARG_ADAPTERS([DEPRECATED_USB1_ADAPTERS],[no])
-
 AC_ARG_ENABLE([parport],
   AS_HELP_STRING([--enable-parport], [Enable building the pc parallel port driver]),
   [build_parport=$enableval], [build_parport=no])
@@ -684,7 +679,6 @@ m4_define([PROCESS_ADAPTERS], [
 ])
 
 PROCESS_ADAPTERS([USB1_ADAPTERS], ["x$use_libusb1" = "xyes"], [libusb-1.x])
-PROCESS_ADAPTERS([DEPRECATED_USB1_ADAPTERS], ["x$use_libusb1" = "xyes"], [libusb-1.x])
 PROCESS_ADAPTERS([HIDAPI_ADAPTERS], ["x$use_hidapi" = "xyes"], [hidapi])
 PROCESS_ADAPTERS([HIDAPI_USB1_ADAPTERS], ["x$use_hidapi" = "xyes" -a "x$use_libusb1" = "xyes"], [hidapi and libusb-1.x])
 PROCESS_ADAPTERS([LIBFTDI_ADAPTERS], ["x$use_libftdi" = "xyes"], [libftdi])
@@ -834,7 +828,6 @@ echo
 echo OpenOCD configuration summary
 echo --------------------------------------------------
 m4_foreach([adapter], [USB1_ADAPTERS,
-	DEPRECATED_USB1_ADAPTERS,
 	HIDAPI_ADAPTERS, HIDAPI_USB1_ADAPTERS, LIBFTDI_ADAPTERS,
 	LIBFTDI_USB1_ADAPTERS,
 	LIBGPIOD_ADAPTERS,
diff --git a/contrib/buildroot/openocd_be_defconfig b/contrib/buildroot/openocd_be_defconfig
index 2fe28f647..49a6ec2ac 100644
--- a/contrib/buildroot/openocd_be_defconfig
+++ b/contrib/buildroot/openocd_be_defconfig
@@ -12,7 +12,6 @@ BR2_PACKAGE_OPENOCD_UBLASTER2=y
 BR2_PACKAGE_OPENOCD_JLINK=y
 BR2_PACKAGE_OPENOCD_OSDBM=y
 BR2_PACKAGE_OPENOCD_OPENDOUS=y
-BR2_PACKAGE_OPENOCD_AICE=y
 BR2_PACKAGE_OPENOCD_VSLLINK=y
 BR2_PACKAGE_OPENOCD_USBPROG=y
 BR2_PACKAGE_OPENOCD_RLINK=y
diff --git a/doc/openocd.texi b/doc/openocd.texi
index d8a5e86b4..c7fee3e71 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2480,7 +2480,7 @@ This command is only available if your libusb1 is at least version 1.0.16.
 Specifies the @var{serial_string} of the adapter to use.
 If this command is not specified, serial strings are not checked.
 Only the following adapter drivers use the serial string from this command:
-aice (aice_usb), arm-jtag-ew, cmsis_dap, ft232r, ftdi, hla (stlink, ti-icdi), jlink, kitprog, opendus,
+arm-jtag-ew, cmsis_dap, ft232r, ftdi, hla (stlink, ti-icdi), jlink, kitprog, opendus,
 openjtag, osbdm, presto, rlink, st-link, usb_blaster (ublast2), usbprog, vsllink, xds110.
 @end deffn
 
@@ -4825,9 +4825,6 @@ specified, @xref{gdbportoverride,,option -gdb-port}.), and a fake ARM core will
 be emulated to comply to GDB remote protocol.
 @item @code{mips_m4k} -- a MIPS core.
 @item @code{mips_mips64} -- a MIPS64 core.
-@item @code{nds32_v2} -- this is an Andes NDS32 v2 core (deprecated; would be removed in v0.13.0).
-@item @code{nds32_v3} -- this is an Andes NDS32 v3 core (deprecated; would be removed in v0.13.0).
-@item @code{nds32_v3m} -- this is an Andes NDS32 v3m core (deprecated; would be removed in v0.13.0).
 @item @code{or1k} -- this is an OpenRISC 1000 core.
 The current implementation supports three JTAG TAP cores:
 @itemize @minus
diff --git a/src/jtag/Makefile.am b/src/jtag/Makefile.am
index 43c6f8b27..7ce4adc29 100644
--- a/src/jtag/Makefile.am
+++ b/src/jtag/Makefile.am
@@ -9,11 +9,6 @@ include %D%/hla/Makefile.am
 %C%_libjtag_la_LIBADD += $(top_builddir)/%D%/hla/libocdhla.la
 endif
 
-if AICE
-include %D%/aice/Makefile.am
-%C%_libjtag_la_LIBADD += $(top_builddir)/%D%/aice/libocdaice.la
-endif
-
 include %D%/drivers/Makefile.am
 %C%_libjtag_la_LIBADD += $(top_builddir)/%D%/drivers/libocdjtagdrivers.la
 
diff --git a/src/jtag/aice/Makefile.am b/src/jtag/aice/Makefile.am
deleted file mode 100644
index bc5dac1e2..000000000
--- a/src/jtag/aice/Makefile.am
+++ /dev/null
@@ -1,16 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-
-noinst_LTLIBRARIES += %D%/libocdaice.la
-
-%C%_libocdaice_la_CPPFLAGS = -I$(top_srcdir)/src/jtag/drivers $(AM_CPPFLAGS) $(LIBUSB1_CFLAGS)
-%C%_libocdaice_la_SOURCES = \
-	%D%/aice_transport.c \
-	%D%/aice_interface.c \
-	%D%/aice_port.c \
-	%D%/aice_usb.c \
-	%D%/aice_pipe.c \
-	%D%/aice_transport.h \
-	%D%/aice_interface.h \
-	%D%/aice_port.h \
-	%D%/aice_usb.h \
-	%D%/aice_pipe.h
diff --git a/src/jtag/aice/aice_interface.c b/src/jtag/aice/aice_interface.c
deleted file mode 100644
index 89f82a0ae..000000000
--- a/src/jtag/aice/aice_interface.c
+++ /dev/null
@@ -1,507 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/***************************************************************************
- *   Copyright (C) 2013 by Andes Technology                                *
- *   Hsiangkai Wang <hk...@an...>                                 *
- ***************************************************************************/
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <jtag/adapter.h>
-#include <jtag/interface.h>
-#include <jtag/commands.h>
-#include <transport/transport.h>
-#include <target/target.h>
-#include <jtag/aice/aice_transport.h>
-#include "aice_usb.h"
-
-#define AICE_KHZ_TO_SPEED_MAP_SIZE	16
-static const int aice_khz_to_speed_map[AICE_KHZ_TO_SPEED_MAP_SIZE] = {
-	30000,
-	15000,
-	7500,
-	3750,
-	1875,
-	937,
-	468,
-	234,
-	48000,
-	24000,
-	12000,
-	6000,
-	3000,
-	1500,
-	750,
-	375,
-};
-
-static const struct aice_port *aice_port;
-static struct aice_port_param_s param;
-static uint32_t retry_times;
-static uint32_t count_to_check_dbger;
-
-/***************************************************************************/
-/* External interface implementation */
-static uint32_t aice_target_id_codes[AICE_MAX_NUM_CORE];
-static uint8_t aice_num_of_target_id_codes;
-
-/***************************************************************************/
-/* AICE operations */
-int aice_init_targets(void)
-{
-	int res;
-	struct target *target;
-	struct aice_port_s *aice;
-
-	LOG_DEBUG("aice_init_targets");
-
-	if (aice_num_of_target_id_codes == 0) {
-		res = aice_port->api->idcode(aice_target_id_codes, &aice_num_of_target_id_codes);
-		if (res != ERROR_OK) {
-			LOG_ERROR("<-- TARGET ERROR! Failed to identify AndesCore "
-					"JTAG Manufacture ID in the JTAG scan chain. "
-					"Failed to access EDM registers. -->");
-			return res;
-		}
-	}
-
-	for (target = all_targets; target; target = target->next) {
-		target->tap->idcode = aice_target_id_codes[target->tap->abs_chain_position];
-
-		unsigned ii, limit = target->tap->expected_ids_cnt;
-		int found = 0;
-
-		for (ii = 0; ii < limit; ii++) {
-			uint32_t expected = target->tap->expected_ids[ii];
-
-			/* treat "-expected-id 0" as a "don't-warn" wildcard */
-			if (!expected || (target->tap->idcode == expected)) {
-				found = 1;
-				break;
-			}
-		}
-
-		if (found == 0) {
-			LOG_ERROR
-				("aice_init_targets: target not found: idcode: %" PRIx32,
-				 target->tap->idcode);
-			return ERROR_FAIL;
-		}
-
-		aice = calloc(1, sizeof(struct aice_port_s));
-		aice->port = aice_port;
-		aice->coreid = target->tap->abs_chain_position;
-
-		target->tap->priv = aice;
-		target->tap->hasidcode = 1;
-	}
-
-	return ERROR_OK;
-}
-
-/***************************************************************************/
-/* End of External interface implementation */
-
-/* initial aice
- * 1. open usb
- * 2. get/show version number
- * 3. reset
- */
-static int aice_init(void)
-{
-	if (aice_port->api->open(&param) != ERROR_OK) {
-		LOG_ERROR("Cannot find AICE Interface! Please check "
-				"connection and permissions.");
-		return ERROR_JTAG_INIT_FAILED;
-	}
-
-	aice_port->api->set_retry_times(retry_times);
-	aice_port->api->set_count_to_check_dbger(count_to_check_dbger);
-
-	LOG_INFO("AICE JTAG Interface ready");
-
-	return ERROR_OK;
-}
-
-/* cleanup aice resource
- * close usb
- */
-static int aice_quit(void)
-{
-	aice_port->api->close();
-	return ERROR_OK;
-}
-
-static int aice_execute_reset(struct jtag_command *cmd)
-{
-	static int last_trst;
-	int retval = ERROR_OK;
-
-	LOG_DEBUG_IO("reset trst: %d", cmd->cmd.reset->trst);
-
-	if (cmd->cmd.reset->trst != last_trst) {
-		if (cmd->cmd.reset->trst)
-			retval = aice_port->api->reset();
-
-		last_trst = cmd->cmd.reset->trst;
-	}
-
-	return retval;
-}
-
-static int aice_execute_command(struct jtag_command *cmd)
-{
-	int retval;
-
-	switch (cmd->type) {
-		case JTAG_RESET:
-			retval = aice_execute_reset(cmd);
-			break;
-		default:
-			retval = ERROR_OK;
-			break;
-	}
-	return retval;
-}
-
-/* aice has no need to implement jtag execution model
-*/
-static int aice_execute_queue(void)
-{
-	struct jtag_command *cmd = jtag_command_queue;	/* currently processed command */
-	int retval;
-
-	retval = ERROR_OK;
-
-	while (cmd) {
-		if (aice_execute_command(cmd) != ERROR_OK)
-			retval = ERROR_JTAG_QUEUE_FAILED;
-
-		cmd = cmd->next;
-	}
-
-	return retval;
-}
-
-/* set jtag frequency(base frequency/frequency divider) to your jtag adapter */
-static int aice_speed(int speed)
-{
-	return aice_port->api->set_jtag_clock(speed);
-}
-
-/* convert jtag adapter frequency(base frequency/frequency divider) to
- * human readable KHz value */
-static int aice_speed_div(int speed, int *khz)
-{
-	*khz = aice_khz_to_speed_map[speed];
-
-	return ERROR_OK;
-}
-
-/* convert human readable KHz value to jtag adapter frequency
- * (base frequency/frequency divider) */
-static int aice_khz(int khz, int *jtag_speed)
-{
-	int i;
-	for (i = 0 ; i < AICE_KHZ_TO_SPEED_MAP_SIZE ; i++) {
-		if (khz == aice_khz_to_speed_map[i]) {
-			if (i >= 8)
-				*jtag_speed = i | AICE_TCK_CONTROL_TCK3048;
-			else
-				*jtag_speed = i;
-			break;
-		}
-	}
-
-	if (i == AICE_KHZ_TO_SPEED_MAP_SIZE) {
-		LOG_INFO("No support the jtag clock: %d", khz);
-		LOG_INFO("Supported jtag clocks are:");
-
-		for (i = 0 ; i < AICE_KHZ_TO_SPEED_MAP_SIZE ; i++)
-			LOG_INFO("* %d", aice_khz_to_speed_map[i]);
-
-		return ERROR_FAIL;
-	}
-
-	return ERROR_OK;
-}
-
-int aice_scan_jtag_chain(void)
-{
-	LOG_DEBUG("=== %s ===", __func__);
-	uint8_t num_of_idcode = 0;
-	struct target *target;
-
-	int res = aice_port->api->idcode(aice_target_id_codes, &num_of_idcode);
-	if (res != ERROR_OK) {
-		LOG_ERROR("<-- TARGET ERROR! Failed to identify AndesCore "
-					"JTAG Manufacture ID in the JTAG scan chain. "
-					"Failed to access EDM registers. -->");
-		return res;
-	}
-
-	for (unsigned int i = 0; i < num_of_idcode; i++)
-		LOG_DEBUG("id_codes[%u] = 0x%" PRIx32, i, aice_target_id_codes[i]);
-
-	/* Update tap idcode */
-	for (target = all_targets; target; target = target->next)
-		target->tap->idcode = aice_target_id_codes[target->tap->abs_chain_position];
-
-	return ERROR_OK;
-}
-
-/***************************************************************************/
-/* Command handlers */
-COMMAND_HANDLER(aice_handle_aice_info_command)
-{
-	LOG_DEBUG("aice_handle_aice_info_command");
-
-	command_print(CMD, "Description: %s", param.device_desc);
-	command_print(CMD, "Serial number: %s", adapter_get_required_serial());
-	if (strncmp(aice_port->name, "aice_pipe", 9) == 0)
-		command_print(CMD, "Adapter: %s", param.adapter_name);
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(aice_handle_aice_port_command)
-{
-	LOG_DEBUG("aice_handle_aice_port_command");
-
-	if (CMD_ARGC != 1) {
-		LOG_ERROR("Need exactly one argument to 'aice port'");
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	for (const struct aice_port *l = aice_port_get_list(); l->name; l++) {
-		if (strcmp(l->name, CMD_ARGV[0]) == 0) {
-			aice_port = l;
-			return ERROR_OK;
-		}
-	}
-
-	LOG_ERROR("No AICE port '%s' found", CMD_ARGV[0]);
-	return ERROR_FAIL;
-}
-
-COMMAND_HANDLER(aice_handle_aice_desc_command)
-{
-	LOG_DEBUG("aice_handle_aice_desc_command");
-
-	if (CMD_ARGC == 1)
-		param.device_desc = strdup(CMD_ARGV[0]);
-	else
-		LOG_ERROR("expected exactly one argument to aice desc <description>");
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(aice_handle_aice_vid_pid_command)
-{
-	LOG_DEBUG("aice_handle_aice_vid_pid_command");
-
-	if (CMD_ARGC != 2) {
-		LOG_WARNING("ignoring extra IDs in aice vid_pid (maximum is 1 pair)");
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	COMMAND_PARSE_NUMBER(u16, CMD_ARGV[0], param.vid);
-	COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], param.pid);
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(aice_handle_aice_adapter_command)
-{
-	LOG_DEBUG("aice_handle_aice_adapter_command");
-
-	if (CMD_ARGC == 1)
-		param.adapter_name = strdup(CMD_ARGV[0]);
-	else
-		LOG_ERROR("expected exactly one argument to aice adapter <adapter-name>");
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(aice_handle_aice_retry_times_command)
-{
-	LOG_DEBUG("aice_handle_aice_retry_times_command");
-
-	if (CMD_ARGC == 1)
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], retry_times);
-	else
-		LOG_ERROR("expected exactly one argument to aice retry_times <num_of_retry>");
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(aice_handle_aice_count_to_check_dbger_command)
-{
-	LOG_DEBUG("aice_handle_aice_count_to_check_dbger_command");
-
-	if (CMD_ARGC == 1)
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], count_to_check_dbger);
-	else
-		LOG_ERROR("expected exactly one argument to aice count_to_check_dbger "
-				"<count_of_checking>");
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(aice_handle_aice_custom_srst_script_command)
-{
-	LOG_DEBUG("aice_handle_aice_custom_srst_script_command");
-
-	if (CMD_ARGC > 0) {
-		aice_port->api->set_custom_srst_script(CMD_ARGV[0]);
-		return ERROR_OK;
-	}
-
-	return ERROR_FAIL;
-}
-
-COMMAND_HANDLER(aice_handle_aice_custom_trst_script_command)
-{
-	LOG_DEBUG("aice_handle_aice_custom_trst_script_command");
-
-	if (CMD_ARGC > 0) {
-		aice_port->api->set_custom_trst_script(CMD_ARGV[0]);
-		return ERROR_OK;
-	}
-
-	return ERROR_FAIL;
-}
-
-COMMAND_HANDLER(aice_handle_aice_custom_restart_script_command)
-{
-	LOG_DEBUG("aice_handle_aice_custom_restart_script_command");
-
-	if (CMD_ARGC > 0) {
-		aice_port->api->set_custom_restart_script(CMD_ARGV[0]);
-		return ERROR_OK;
-	}
-
-	return ERROR_FAIL;
-}
-
-COMMAND_HANDLER(aice_handle_aice_reset_command)
-{
-	LOG_DEBUG("aice_handle_aice_reset_command");
-
-	return aice_port->api->reset();
-}
-
-
-static const struct command_registration aice_subcommand_handlers[] = {
-	{
-		.name = "info",
-		.handler = &aice_handle_aice_info_command,
-		.mode = COMMAND_EXEC,
-		.help = "show aice info",
-		.usage = "",
-	},
-	{
-		.name = "port",
-		.handler = &aice_handle_aice_port_command,
-		.mode = COMMAND_CONFIG,
-		.help = "set the port of the AICE",
-		.usage = "['aice_pipe'|'aice_usb']",
-	},
-	{
-		.name = "desc",
-		.handler = &aice_handle_aice_desc_command,
-		.mode = COMMAND_CONFIG,
-		.help = "set the aice device description",
-		.usage = "[description string]",
-	},
-	{
-		.name = "vid_pid",
-		.handler = &aice_handle_aice_vid_pid_command,
-		.mode = COMMAND_CONFIG,
-		.help = "the vendor and product ID of the AICE device",
-		.usage = "(vid pid)*",
-	},
-	{
-		.name = "adapter",
-		.handler = &aice_handle_aice_adapter_command,
-		.mode = COMMAND_CONFIG,
-		.help = "set the file name of adapter",
-		.usage = "[adapter name]",
-	},
-	{
-		.name = "retry_times",
-		.handler = &aice_handle_aice_retry_times_command,
-		.mode = COMMAND_CONFIG,
-		.help = "set retry times as AICE timeout",
-		.usage = "num_of_retry",
-	},
-	{
-		.name = "count_to_check_dbger",
-		.handler = &aice_handle_aice_count_to_check_dbger_command,
-		.mode = COMMAND_CONFIG,
-		.help = "set retry times as checking $DBGER status",
-		.usage = "count_of_checking",
-	},
-	{
-		.name = "custom_srst_script",
-		.handler = &aice_handle_aice_custom_srst_script_command,
-		.mode = COMMAND_CONFIG,
-		.usage = "script_file_name",
-		.help = "set custom srst script",
-	},
-	{
-		.name = "custom_trst_script",
-		.handler = &aice_handle_aice_custom_trst_script_command,
-		.mode = COMMAND_CONFIG,
-		.usage = "script_file_name",
-		.help = "set custom trst script",
-	},
-	{
-		.name = "custom_restart_script",
-		.handler = &aice_handle_aice_custom_restart_script_command,
-		.mode = COMMAND_CONFIG,
-		.usage = "script_file_name",
-		.help = "set custom restart script",
-	},
-	{
-		.name = "reset",
-		.handler = &aice_handle_aice_reset_command,
-		.mode = COMMAND_EXEC,
-		.usage = "",
-		.help = "reset AICE",
-	},
-	COMMAND_REGISTRATION_DONE
-};
-
-static const struct command_registration aice_command_handlers[] = {
-	{
-		.name = "aice",
-		.mode = COMMAND_ANY,
-		.help = "perform aice management",
-		.usage = "[subcommand]",
-		.chain = aice_subcommand_handlers,
-	},
-	COMMAND_REGISTRATION_DONE
-};
-/***************************************************************************/
-/* End of Command handlers */
-
-static struct jtag_interface aice_interface = {
-	.execute_queue = aice_execute_queue,
-};
-
-struct adapter_driver aice_adapter_driver = {
-	.name = "aice",
-	.transports = aice_transports,
-	.commands = aice_command_handlers,
-
-	.init = aice_init,
-	.quit = aice_quit,
-	.speed = aice_speed,		/* set interface speed */
-	.khz = aice_khz,		/* convert khz to interface speed value */
-	.speed_div = aice_speed_div,	/* return readable value */
-
-	.jtag_ops = &aice_interface,
-};
diff --git a/src/jtag/aice/aice_interface.h b/src/jtag/aice/aice_interface.h
deleted file mode 100644
index 615e90f2e..000000000
--- a/src/jtag/aice/aice_interface.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/***************************************************************************
- *   Copyright (C) 2013 by Andes Technology                                *
- *   Hsiangkai Wang <hk...@an...>                                 *
- ***************************************************************************/
-
-#ifndef OPENOCD_JTAG_AICE_AICE_INTERFACE_H
-#define OPENOCD_JTAG_AICE_AICE_INTERFACE_H
-
-int aice_init_targets(void);
-int aice_scan_jtag_chain(void);
-
-#endif /* OPENOCD_JTAG_AICE_AICE_INTERFACE_H */
diff --git a/src/jtag/aice/aice_pipe.c b/src/jtag/aice/aice_pipe.c
deleted file mode 100644
index 1ee2d88b4..000000000
--- a/src/jtag/aice/aice_pipe.c
+++ /dev/null
@@ -1,884 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/***************************************************************************
- *   Copyright (C) 2013 by Andes Technology                                *
- *   Hsiangkai Wang <hk...@an...>                                 *
- ***************************************************************************/
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <helper/system.h>
-
-#ifdef _WIN32
-#include <windows.h>
-#else
-#include <signal.h>
-#endif
-
-#include <helper/log.h>
-#include <helper/time_support.h>
-#include "aice_port.h"
-#include "aice_pipe.h"
-
-#define AICE_PIPE_MAXLINE 8192
-
-#ifdef _WIN32
-PROCESS_INFORMATION proc_info;
-
-static HANDLE aice_pipe_output[2];
-static HANDLE aice_pipe_input[2];
-
-static int aice_pipe_write(const void *buffer, int count)
-{
-	BOOL success;
-	DWORD written;
-
-	success = WriteFile(aice_pipe_output[1], buffer, count, &written, NULL);
-	if (!success) {
-		LOG_ERROR("(WIN32) write to pipe failed, error code: 0x%08l" PRIx32, GetLastError());
-		return -1;
-	}
-
-	return written;
-}
-
-static int aice_pipe_read(void *buffer, int count)
-{
-	BOOL success;
-	DWORD has_read;
-
-	success = ReadFile(aice_pipe_input[0], buffer, count, &has_read, NULL);
-	if (!success || (has_read == 0)) {
-		LOG_ERROR("(WIN32) read from pipe failed, error code: 0x%08l" PRIx32, GetLastError());
-		return -1;
-	}
-
-	return has_read;
-}
-
-static int aice_pipe_child_init(struct aice_port_param_s *param)
-{
-	STARTUPINFO start_info;
-	BOOL success;
-
-	ZeroMemory(&proc_info, sizeof(PROCESS_INFORMATION));
-	ZeroMemory(&start_info, sizeof(STARTUPINFO));
-	start_info.cb = sizeof(STARTUPINFO);
-	start_info.hStdError = aice_pipe_input[1];
-	start_info.hStdOutput = aice_pipe_input[1];
-	start_info.hStdInput = aice_pipe_output[0];
-	start_info.dwFlags |= STARTF_USESTDHANDLES;
-
-	success = CreateProcess(NULL,
-			param->adapter_name,
-			NULL,
-			NULL,
-			TRUE,
-			0,
-			NULL,
-			NULL,
-			&start_info,
-			&proc_info);
-
-	if (!success) {
-		LOG_ERROR("Create new process failed");
-		return ERROR_FAIL;
-	}
-
-	return ERROR_OK;
-}
-
-static int aice_pipe_parent_init(struct aice_port_param_s *param)
-{
-	/* send open to adapter */
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_OPEN;
-	set_u16(command + 1, param->vid);
-	set_u16(command + 3, param->pid);
-
-	if (aice_pipe_write(command, 5) != 5) {
-		LOG_ERROR("write failed\n");
-		return ERROR_FAIL;
-	}
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) {
-		LOG_ERROR("read failed\n");
-		return ERROR_FAIL;
-	}
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_open(struct aice_port_param_s *param)
-{
-	SECURITY_ATTRIBUTES attribute;
-
-	attribute.nLength = sizeof(SECURITY_ATTRIBUTES);
-	attribute.bInheritHandle = TRUE;
-	attribute.lpSecurityDescriptor = NULL;
-
-	if (!CreatePipe(&aice_pipe_output[0], &aice_pipe_output[1],
-				&attribute, AICE_PIPE_MAXLINE)) {
-		LOG_ERROR("Create pipes failed");
-		return ERROR_FAIL;
-	}
-	if (!CreatePipe(&aice_pipe_input[0], &aice_pipe_input[1],
-				&attribute, AICE_PIPE_MAXLINE)) {
-		LOG_ERROR("Create pipes failed");
-		return ERROR_FAIL;
-	}
-
-	/* do not inherit aice_pipe_output[1] & aice_pipe_input[0] to child process */
-	if (!SetHandleInformation(aice_pipe_output[1], HANDLE_FLAG_INHERIT, 0))
-		return ERROR_FAIL;
-	if (!SetHandleInformation(aice_pipe_input[0], HANDLE_FLAG_INHERIT, 0))
-		return ERROR_FAIL;
-
-	aice_pipe_child_init(param);
-
-	aice_pipe_parent_init(param);
-
-	return ERROR_OK;
-}
-
-#else
-
-static int aice_pipe_output[2];
-static int aice_pipe_input[2];
-
-static int aice_pipe_write(const void *buffer, int count)
-{
-	if (write(aice_pipe_output[1], buffer, count) != count) {
-		LOG_ERROR("write to pipe failed");
-		return -1;
-	}
-
-	return count;
-}
-
-static int aice_pipe_read(void *buffer, int count)
-{
-	int n;
-	int64_t then, cur;
-
-	then = timeval_ms();
-
-	while (1) {
-		n = read(aice_pipe_input[0], buffer, count);
-
-		if ((n == -1) && (errno == EAGAIN)) {
-			cur = timeval_ms();
-			if (cur - then > 500)
-				keep_alive();
-			continue;
-		} else if (n > 0)
-			break;
-		else {
-			LOG_ERROR("read from pipe failed");
-			break;
-		}
-	}
-
-	return n;
-}
-
-static int aice_pipe_child_init(struct aice_port_param_s *param)
-{
-	close(aice_pipe_output[1]);
-	close(aice_pipe_input[0]);
-
-	if (aice_pipe_output[0] != STDIN_FILENO) {
-		if (dup2(aice_pipe_output[0], STDIN_FILENO) != STDIN_FILENO) {
-			LOG_ERROR("Map aice_pipe to STDIN failed");
-			return ERROR_FAIL;
-		}
-		close(aice_pipe_output[0]);
-	}
-
-	if (aice_pipe_input[1] != STDOUT_FILENO) {
-		if (dup2(aice_pipe_input[1], STDOUT_FILENO) != STDOUT_FILENO) {
-			LOG_ERROR("Map aice_pipe to STDOUT failed");
-			return ERROR_FAIL;
-		}
-		close(aice_pipe_input[1]);
-	}
-
-	if (execl(param->adapter_name, param->adapter_name, (char *)0) < 0) {
-		LOG_ERROR("Execute aice_pipe failed");
-		return ERROR_FAIL;
-	}
-
-	return ERROR_OK;
-}
-
-static int aice_pipe_parent_init(struct aice_port_param_s *param)
-{
-	close(aice_pipe_output[0]);
-	close(aice_pipe_input[1]);
-
-	/* set read end of pipe as non-blocking */
-	if (fcntl(aice_pipe_input[0], F_SETFL, O_NONBLOCK))
-		return ERROR_FAIL;
-
-	/* send open to adapter */
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_OPEN;
-	set_u16(command + 1, param->vid);
-	set_u16(command + 3, param->pid);
-
-	if (aice_pipe_write(command, 5) != 5) {
-		LOG_ERROR("write failed\n");
-		return ERROR_FAIL;
-	}
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0) {
-		LOG_ERROR("read failed\n");
-		return ERROR_FAIL;
-	}
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-}
-
-static void sig_pipe(int signo)
-{
-	exit(1);
-}
-
-static int aice_pipe_open(struct aice_port_param_s *param)
-{
-	pid_t pid;
-
-	if (signal(SIGPIPE, sig_pipe) == SIG_ERR) {
-		LOG_ERROR("Register SIGPIPE handler failed");
-		return ERROR_FAIL;
-	}
-
-	if (pipe(aice_pipe_output) < 0 || pipe(aice_pipe_input) < 0) {
-		LOG_ERROR("Create pipes failed");
-		return ERROR_FAIL;
-	}
-
-	pid = fork();
-	if (pid < 0) {
-		LOG_ERROR("Fork new process failed");
-		return ERROR_FAIL;
-	} else if (pid == 0) {
-		if (aice_pipe_child_init(param) != ERROR_OK) {
-			LOG_ERROR("AICE_PIPE child process initial error");
-			return ERROR_FAIL;
-		} else {
-			if (aice_pipe_parent_init(param) != ERROR_OK) {
-				LOG_ERROR("AICE_PIPE parent process initial error");
-				return ERROR_FAIL;
-			}
-		}
-	}
-
-	return ERROR_OK;
-}
-#endif
-
-static int aice_pipe_close(void)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_CLOSE;
-
-	if (aice_pipe_write(command, 1) != 1)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_OK) {
-#ifdef _WIN32
-		WaitForSingleObject(proc_info.hProcess, INFINITE);
-		CloseHandle(proc_info.hProcess);
-		CloseHandle(proc_info.hThread);
-#endif
-		return ERROR_OK;
-	} else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_idcode(uint32_t *idcode, uint8_t *num_of_idcode)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_IDCODE;
-
-	if (aice_pipe_write(command, 1) != 1)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	*num_of_idcode = line[0];
-
-	if ((*num_of_idcode == 0) || (*num_of_idcode >= 16))
-		return ERROR_FAIL;
-
-	for (int i = 0 ; i < *num_of_idcode ; i++)
-		idcode[i] = get_u32(line + i * 4 + 1);
-
-	return ERROR_OK;
-}
-
-static int aice_pipe_state(uint32_t coreid, enum aice_target_state_s *state)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_STATE;
-
-	if (aice_pipe_write(command, 1) != 1)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	*state = (enum aice_target_state_s)line[0];
-
-	return ERROR_OK;
-}
-
-static int aice_pipe_reset(void)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_RESET;
-
-	if (aice_pipe_write(command, 1) != 1)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_assert_srst(uint32_t coreid, enum aice_srst_type_s srst)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_ASSERT_SRST;
-	command[1] = srst;
-
-	if (aice_pipe_write(command, 2) != 2)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_run(uint32_t coreid)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_RUN;
-
-	if (aice_pipe_write(command, 1) != 1)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_halt(uint32_t coreid)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_HALT;
-
-	if (aice_pipe_write(command, 1) != 1)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_read_reg(uint32_t coreid, uint32_t num, uint32_t *val)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_READ_REG;
-	set_u32(command + 1, num);
-
-	if (aice_pipe_write(command, 5) != 5)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	*val = get_u32(line);
-
-	return ERROR_OK;
-}
-
-static int aice_pipe_write_reg(uint32_t coreid, uint32_t num, uint32_t val)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_WRITE_REG;
-	set_u32(command + 1, num);
-	set_u32(command + 5, val);
-
-	if (aice_pipe_write(command, 9) != 9)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_read_reg_64(uint32_t coreid, uint32_t num, uint64_t *val)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_READ_REG_64;
-	set_u32(command + 1, num);
-
-	if (aice_pipe_write(command, 5) != 5)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	*val = (((uint64_t)get_u32(line + 4)) << 32) | get_u32(line);
-
-	return ERROR_OK;
-}
-
-static int aice_pipe_write_reg_64(uint32_t coreid, uint32_t num, uint64_t val)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_WRITE_REG_64;
-	set_u32(command + 1, num);
-	set_u32(command + 5, val & 0xFFFFFFFF);
-	set_u32(command + 9, (val >> 32) & 0xFFFFFFFF);
-
-	if (aice_pipe_write(command, 13) != 9)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_step(uint32_t coreid)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_STEP;
-
-	if (aice_pipe_write(command, 1) != 1)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_read_mem_unit(uint32_t coreid, uint32_t addr, uint32_t size,
-		uint32_t count, uint8_t *buffer)
-{
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_READ_MEM_UNIT;
-	set_u32(command + 1, addr);
-	set_u32(command + 5, size);
-	set_u32(command + 9, count);
-
-	if (aice_pipe_write(command, 13) != 13)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(buffer, size * count) < 0)
-		return ERROR_FAIL;
-
-	return ERROR_OK;
-}
-
-static int aice_pipe_write_mem_unit(uint32_t coreid, uint32_t addr, uint32_t size,
-		uint32_t count, const uint8_t *buffer)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_WRITE_MEM_UNIT;
-	set_u32(command + 1, addr);
-	set_u32(command + 5, size);
-	set_u32(command + 9, count);
-
-	/* WRITE_MEM_UNIT|addr|size|count|data */
-	memcpy(command + 13, buffer, size * count);
-
-	if (aice_pipe_write(command, 13 + size * count) < 0)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-
-	return ERROR_OK;
-}
-
-static int aice_pipe_read_mem_bulk(uint32_t coreid, uint32_t addr,
-		uint32_t length, uint8_t *buffer)
-{
-	char line[AICE_PIPE_MAXLINE + 1];
-	char command[AICE_PIPE_MAXLINE];
-	uint32_t remain_len = length;
-	uint32_t prepare_len;
-	char *received_line;
-	uint32_t received_len;
-	int read_len;
-
-	command[0] = AICE_READ_MEM_BULK;
-	set_u32(command + 1, addr);
-	set_u32(command + 5, length);
-
-	if (aice_pipe_write(command, 9) < 0)
-		return ERROR_FAIL;
-
-	while (remain_len > 0) {
-		if (remain_len > AICE_PIPE_MAXLINE)
-			prepare_len = AICE_PIPE_MAXLINE;
-		else
-			prepare_len = remain_len;
-
-		prepare_len++;
-		received_len = 0;
-		received_line = line;
-		do {
-			read_len = aice_pipe_read(received_line, prepare_len - received_len);
-			if (read_len < 0)
-				return ERROR_FAIL;
-			received_line += read_len;
-			received_len += read_len;
-		} while (received_len < prepare_len);
-
-		if (line[0] != AICE_OK)
-			return ERROR_FAIL;
-
-		prepare_len--;
-		memcpy(buffer, line + 1, prepare_len);
-		remain_len -= prepare_len;
-		buffer += prepare_len;
-	}
-
-	return ERROR_OK;
-}
-
-static int aice_pipe_write_mem_bulk(uint32_t coreid, uint32_t addr,
-		uint32_t length, const uint8_t *buffer)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE + 4];
-	uint32_t remain_len = length;
-	uint32_t written_len = 0;
-	uint32_t write_len;
-
-	command[0] = AICE_WRITE_MEM_BULK;
-	set_u32(command + 1, addr);
-	set_u32(command + 5, length);
-
-	/* Send command first */
-	if (aice_pipe_write(command, 9) < 0)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_ERROR)
-		return ERROR_FAIL;
-
-	while (remain_len > 0) {
-		if (remain_len > AICE_PIPE_MAXLINE)
-			write_len = AICE_PIPE_MAXLINE;
-		else
-			write_len = remain_len;
-
-		set_u32(command, write_len);
-		memcpy(command + 4, buffer + written_len, write_len); /* data only */
-
-		if (aice_pipe_write(command, write_len + 4) < 0)
-			return ERROR_FAIL;
-
-		if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-			return ERROR_FAIL;
-
-		if (line[0] == AICE_ERROR)
-			return ERROR_FAIL;
-
-		remain_len -= write_len;
-		written_len += write_len;
-	}
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_read_debug_reg(uint32_t coreid, uint32_t addr, uint32_t *val)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_READ_DEBUG_REG;
-	set_u32(command + 1, addr);
-
-	if (aice_pipe_write(command, 5) != 5)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	*val = get_u32(line);
-
-	return ERROR_OK;
-}
-
-static int aice_pipe_write_debug_reg(uint32_t coreid, uint32_t addr, const uint32_t val)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_WRITE_DEBUG_REG;
-	set_u32(command + 1, addr);
-	set_u32(command + 5, val);
-
-	if (aice_pipe_write(command, 9) != 9)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_set_jtag_clock(uint32_t a_clock)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_SET_JTAG_CLOCK;
-	set_u32(command + 1, a_clock);
-
-	if (aice_pipe_write(command, 5) != 5)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_memory_access(uint32_t coreid, enum nds_memory_access access_channel)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_MEMORY_ACCESS;
-	set_u32(command + 1, access_channel);
-
-	if (aice_pipe_write(command, 5) != 5)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_memory_mode(uint32_t coreid, enum nds_memory_select mem_select)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_MEMORY_MODE;
-	set_u32(command + 1, mem_select);
-
-	if (aice_pipe_write(command, 5) != 5)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_read_tlb(uint32_t coreid, target_addr_t virtual_address,
-		target_addr_t *physical_address)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_READ_TLB;
-	set_u32(command + 1, virtual_address);
-
-	if (aice_pipe_write(command, 5) != 5)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_OK) {
-		*physical_address = get_u32(line + 1);
-		return ERROR_OK;
-	} else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_cache_ctl(uint32_t coreid, uint32_t subtype, uint32_t address)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_CACHE_CTL;
-	set_u32(command + 1, subtype);
-	set_u32(command + 5, address);
-
-	if (aice_pipe_write(command, 9) != 9)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_set_retry_times(uint32_t a_retry_times)
-{
-	return ERROR_OK;
-}
-
-/** */
-struct aice_port_api_s aice_pipe = {
-	/** */
-	.open = aice_pipe_open,
-	/** */
-	.close = aice_pipe_close,
-	/** */
-	.idcode = aice_pipe_idcode,
-	/** */
-	.set_jtag_clock = aice_pipe_set_jtag_clock,
-	/** */
-	.state = aice_pipe_state,
-	/** */
-	.reset = aice_pipe_reset,
-	/** */
-	.assert_srst = aice_pipe_assert_srst,
-	/** */
-	.run = aice_pipe_run,
-	/** */
-	.halt = aice_pipe_halt,
-	/** */
-	.step = aice_pipe_step,
-	/** */
-	.read_reg = aice_pipe_read_reg,
-	/** */
-	.write_reg = aice_pipe_write_reg,
-	/** */
-	.read_reg_64 = aice_pipe_read_reg_64,
-	/** */
-	.write_reg_64 = aice_pipe_write_reg_64,
-	/** */
-	.read_mem_unit = aice_pipe_read_mem_unit,
-	/** */
-	.write_mem_unit = aice_pipe_write_mem_unit,
-	/** */
-	.read_mem_bulk = aice_pipe_read_mem_bulk,
-	/** */
-	.write_mem_bulk = aice_pipe_write_mem_bulk,
-	/** */
-	.read_debug_reg = aice_pipe_read_debug_reg,
-	/** */
-	.write_debug_reg = aice_pipe_write_debug_reg,
-
-	/** */
-	.memory_access = aice_pipe_memory_access,
-	/** */
-	.memory_mode = aice_pipe_memory_mode,
-
-	/** */
-	.read_tlb = aice_pipe_read_tlb,
-
-	/** */
-	.cache_ctl = aice_pipe_cache_ctl,
-
-	/** */
-	.set_retry_times = aice_pipe_set_retry_times,
-};
diff --git a/src/jtag/aice/aice_pipe.h b/src/jtag/aice/aice_pipe.h
deleted file mode 100644
index 5a1f4107f..000000000
--- a/src/jtag/aice/aice_pipe.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/***************************************************************************
- *   Copyright (C) 2013 by Andes Technology                                *
- *   Hsiangkai Wang <hk...@an...>                                 *
- ***************************************************************************/
-
-#ifndef OPENOCD_JTAG_AICE_AICE_PIPE_H
-#define OPENOCD_JTAG_AICE_AICE_PIPE_H
-
-#include <helper/types.h>
-
-#define set_u32(buffer, value) h_u32_to_le((uint8_t *)buffer, value)
-#define set_u16(buffer, value) h_u16_to_le((uint8_t *)buffer, value)
-#define get_u32(buffer) le_to_h_u32((const uint8_t *)buffer)
-#define get_u16(buffer) le_to_h_u16((const uint8_t *)buffer)
-
-extern struct aice_port_api_s aice_pipe;
-
-#endif /* OPENOCD_JTAG_AICE_AICE_PIPE_H */
diff --git a/src/jtag/aice/aice_port.c b/src/jtag/aice/aice_port.c
deleted file mode 100644
index ac38cec3a..000000000
--- a/src/jtag/aice/aice_port.c
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/***************************************************************************
- *   Copyright (C) 2013 by Andes Technology                                *
- *   Hsiangkai Wang <hk...@an...>                                 *
- ***************************************************************************/
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <helper/log.h>
-#include "aice_usb.h"
-#include "aice_pipe.h"
-#include "aice_port.h"
-
-static const struct aice_port aice_ports[] = {
-	{
-		.name = "aice_usb",
-		.type = AICE_PORT_AICE_USB,
-		.api = &aice_usb_api,
-	},
-	{
-		.name = "aice_pipe",
-		.type = AICE_PORT_AICE_PIPE,
-		.api = &aice_pipe,
-	},
-	{.name = NULL, /* END OF TABLE */ },
-};
-
-/** */
-const struct aice_port *aice_port_get_list(void)
-{
-	return aice_ports;
-}
diff --git a/src/jtag/aice/aice_port.h b/src/jtag/aice/aice_port.h
deleted file mode 100644
index fb914d853..000000000
--- a/src/jtag/aice/aice_port.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/***************************************************************************
- *   Copyright (C) 2013 by Andes Technology                                *
- *   Hsiangkai Wang <hk...@an...>                                 *
- ***************************************************************************/
-
-#ifndef OPENOCD_JTAG_AICE_AICE_PORT_H
-#define OPENOCD_JTAG_AICE_AICE_PORT_H
-
-#include <target/nds32_edm.h>
-
-#define AICE_MAX_NUM_CORE      (0x10)
-
-#define ERROR_AICE_DISCONNECT  (-200)
-#define ERROR_AICE_TIMEOUT     (-201)
-
-enum aice_target_state_s {
-	AICE_DISCONNECT = 0,
-	AICE_TARGET_DETACH,
-	AICE_TARGET_UNKNOWN,
-	AICE_TARGET_RUNNING,
-	AICE_TARGET_HALTED,
-	AICE_TARGET_RESET,
-	AICE_TARGET_DEBUG_RUNNING,
-};
-
-enum aice_srst_type_s {
-	AICE_SRST = 0x1,
-	AICE_RESET_HOLD = 0x8,
-};
-
-enum aice_target_endian {
-	AICE_LITTLE_ENDIAN = 0,
-	AICE_BIG_ENDIAN,
-};
-
-enum aice_api_s {
-	AICE_OPEN = 0x0,
-	AICE_CLOSE,
-	AICE_RESET,
-	AICE_IDCODE,
-	AICE_SET_JTAG_CLOCK,
-	AICE_ASSERT_SRST,
-	AICE_RUN,
-	AICE_HALT,
-	AICE_STEP,
-	AICE_READ_REG,
-	AICE_WRITE_REG,
-	AICE_READ_REG_64,
-	AICE_WRITE_REG_64,
-	AICE_READ_MEM_UNIT,
-	AICE_WRITE_MEM_UNIT,
-	AICE_READ_MEM_BULK,
-	AICE_WRITE_MEM_BULK,
-	AICE_READ_DEBUG_REG,
-	AICE_WRITE_DEBUG_REG,
-	AICE_STATE,
-	AICE_MEMORY_ACCESS,
-	AICE_MEMORY_MODE,
-	AICE_READ_TLB,
-	AICE_CACHE_CTL,
-	AICE_SET_RETRY_TIMES,
-	AICE_PROGRAM_EDM,
-	AICE_SET_COMMAND_MODE,
-	AICE_EXECUTE,
-	AICE_SET_CUSTOM_SRST_SCRIPT,
-	AICE_SET_CUSTOM_TRST_SCRIPT,
-	AICE_SET_CUSTOM_RESTART_SCRIPT,
-	AICE_SET_COUNT_TO_CHECK_DBGER,
-	AICE_SET_DATA_ENDIAN,
-};
-
-enum aice_error_s {
-	AICE_OK,
-	AICE_ACK,
-	AICE_ERROR,
-};
-
-enum aice_cache_ctl_type {
-	AICE_CACHE_CTL_L1D_INVALALL = 0,
-	AICE_CACHE_CTL_L1D_VA_INVAL,
-	AICE_CACHE_CTL_L1D_WBALL,
-	AICE_CACHE_CTL_L1D_VA_WB,
-	AICE_CACHE_CTL_L1I_INVALALL,
-	AICE_CACHE_CTL_L1I_VA_INVAL,
-};
-
-enum aice_command_mode {
-	AICE_COMMAND_MODE_NORMAL,
-	AICE_COMMAND_MODE_PACK,
-	AICE_COMMAND_MODE_BATCH,
-};
-
-struct aice_port_param_s {
-	/** */
-	const char *device_desc;
-	/** */
-	uint16_t vid;
-	/** */
-	uint16_t pid;
-	/** */
-	char *adapter_name;
-};
-
-struct aice_port_s {
-	/** */
-	uint32_t coreid;
-	/** */
-	const struct aice_port *port;
-};
-
-/** */
-extern struct aice_port_api_s aice_usb_layout_api;
-
-/** */
-struct aice_port_api_s {
-	/** */
-	int (*open)(struct aice_port_param_s *param);
-	/** */
-	int (*close)(void);
-	/** */
-	int (*reset)(void);
-	/** */
-	int (*idcode)(uint32_t *idcode, uint8_t *num_of_idcode);
-	/** */
-	int (*set_jtag_clock)(uint32_t a_clock);
-	/** */
-	int (*assert_srst)(uint32_t coreid, enum aice_srst_type_s srst);
-	/** */
-	int (*run)(uint32_t coreid);
-	/** */
-	int (*halt)(uint32_t coreid);
-	/** */
-	int (*step)(uint32_t coreid);
-	/** */
-	int (*read_reg)(uint32_t coreid, uint32_t num, uint32_t *val);
-	/** */
-	int (*write_reg)(uint32_t coreid, uint32_t num, uint32_t val);
-	/** */
-	int (*read_reg_64)(uint32_t coreid, uint32_t num, uint64_t *val);
-	/** */
-	int (*write_reg_64)(uint32_t coreid, uint32_t num, uint64_t val);
-	/** */
-	int (*read_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
-			uint32_t count, uint8_t *buffer);
-	/** */
-	int (*write_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
-			uint32_t count, const uint8_t *buffer);
-	/** */
-	int (*read_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
-			uint8_t *buffer);
-	/** */
-	int (*write_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
-			const uint8_t *buffer);
-	/** */
-	int (*read_debug_reg)(uint32_t coreid, uint32_t addr, uint32_t *val);
-	/** */
-	int (*write_debug_reg)(uint32_t coreid, uint32_t addr, const uint32_t val);
-
-	/** */
-	int (*state)(uint32_t coreid, enum aice_target_state_s *state);
-
-	/** */
-	int (*memory_access)(uint32_t coreid, enum nds_memory_access a_access);
-	/** */
-	int (*memory_mode)(uint32_t coreid, enum nds_memory_select mem_select);
-
-	/** */
-	int (*read_tlb)(uint32_t coreid, target_addr_t virtual_address, target_addr_t *physical_address);
-
-	/** */
-	int (*cache_ctl)(uint32_t coreid, uint32_t subtype, uint32_t address);
-
-	/** */
-	int (*set_retry_times)(uint32_t a_retry_times);
-
-	/** */
-	int (*program_edm)(uint32_t coreid, char *command_sequence);
-
-	/** */
-	int (*set_command_mode)(enum aice_command_mode command_mode);
-
-	/** */
-	int (*execute)(uint32_t coreid, uint32_t *instructions, uint32_t instruction_num);
-
-	/** */
-	int (*set_custom_srst_script)(const char *script);
-
-	/** */
-	int (*set_custom_trst_script)(const char *script);
-
-	/** */
-	int (*set_custom_restart_script)(const char *script);
-
-	/** */
-	int (*set_count_to_check_dbger)(uint32_t count_to_check);
-
-	/** */
-	int (*set_data_endian)(uint32_t coreid, enum aice_target_endian target_data_endian);
-
-	/** */
-	int (*profiling)(uint32_t coreid, uint32_t interval, uint32_t iteration,
-		uint32_t reg_no, uint32_t *samples, uint32_t *num_samples);
-};
-
-#define AICE_PORT_UNKNOWN	0
-#define AICE_PORT_AICE_USB	1
-#define AICE_PORT_AICE_PIPE	2
-
-/** */
-struct aice_port {
-	/** */
-	const char *name;
-	/** */
-	int type;
-	/** */
-	struct aice_port_api_s *const api;
-};
-
-/** */
-const struct aice_port *aice_port_get_list(void);
-
-#endif /* OPENOCD_JTAG_AICE_AICE_PORT_H */
diff --git a/src/jtag/aice/aice_transport.c b/src/jtag/aice/aice_transport.c
deleted file mode 100644
index 49f899ddc..000000000
--- a/src/jtag/aice/aice_transport.c
+++ /dev/null
@@ -1,432 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/***************************************************************************
- *   Copyright (C) 2013 by Andes Technology                                *
- *   Hsiangkai Wang <hk...@an...>                                 *
- ***************************************************************************/
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-/* project specific includes */
-#include <jtag/interface.h>
-#include <jtag/tcl.h>
-#include <transport/transport.h>
-#include <target/target.h>
-#include <jtag/aice/aice_interface.h>
-#include <jtag/aice/aice_transport.h>
-#include <string.h>
-
-/* */
-static int jim_newtap_expected_id(struct jim_nvp *n, struct jim_getopt_info *goi,
-		struct jtag_tap *tap)
-{
-	jim_wide w;
-	int e = jim_getopt_wide(goi, &w);
-	if (e != JIM_OK) {
-		Jim_SetResultFormatted(goi->interp, "option: %s bad parameter",
-				n->name);
-		return e;
-	}
-
-	unsigned expected_len = sizeof(uint32_t) * tap->expected_ids_cnt;
-	uint32_t *new_expected_ids = malloc(expected_len + sizeof(uint32_t));
-	if (!new_expected_ids) {
-		Jim_SetResultFormatted(goi->interp, "no memory");
-		return JIM_ERR;
-	}
-
-	assert(tap->expected_ids);
-	memcpy(new_expected_ids, tap->expected_ids, expected_len);
-
-	new_expected_ids[tap->expected_ids_cnt] = w;
-
-	free(tap->expected_ids);
-	tap->expected_ids = new_expected_ids;
-	tap->expected_ids_cnt++;
-
-	return JIM_OK;
-}
-
-#define NTAP_OPT_EXPECTED_ID 0
-
-/* */
-static int jim_aice_newtap_cmd(struct jim_getopt_info *goi)
-{
-	struct jtag_tap *tap;
-	int x;
-	int e;
-	struct jim_nvp *n;
-	char *cp;
-	const struct jim_nvp opts[] = {
-		{.name = "-expected-id", .value = NTAP_OPT_EXPECTED_ID},
-		{.name = NULL, .value = -1},
-	};
-
-	tap = calloc(1, sizeof(struct jtag_tap));
-	if (!tap) {
-		Jim_SetResultFormatted(goi->interp, "no memory");
-		return JIM_ERR;
-	}
-
-	/*
-	 * we expect CHIP + TAP + OPTIONS
-	 * */
-	if (goi->argc < 3) {
-		Jim_SetResultFormatted(goi->interp,
-				"Missing CHIP TAP OPTIONS ....");
-		free(tap);
-		return JIM_ERR;
-	}
-
-	const char *tmp;
-	jim_getopt_string(goi, &tmp, NULL);
-	tap->chip = strdup(tmp);
-
-	jim_getopt_string(goi, &tmp, NULL);
-	tap->tapname = strdup(tmp);
-
-	/* name + dot + name + null */
-	x = strlen(tap->chip) + 1 + strlen(tap->tapname) + 1;
-	cp = malloc(x);
-	sprintf(cp, "%s.%s", tap->chip, tap->tapname);
-	tap->dotted_name = cp;
-
-	LOG_DEBUG("Creating New Tap, Chip: %s, Tap: %s, Dotted: %s, %d params",
-			tap->chip, tap->tapname, tap->dotted_name, goi->argc);
-
-	while (goi->argc) {
-		e = jim_getopt_nvp(goi, opts, &n);
-		if (e != JIM_OK) {
-			jim_getopt_nvp_unknown(goi, opts, 0);
-			free(cp);
-			free(tap);
-			return e;
-		}
-		LOG_DEBUG("Processing option: %s", n->name);
-		switch (n->value) {
-			case NTAP_OPT_EXPECTED_ID:
-				e = jim_newtap_expected_id(n, goi, tap);
-				if (e != JIM_OK) {
-					free(cp);
-					free(tap);
-					return e;
-				}
-				break;
-		}		/* switch (n->value) */
-	}			/* while (goi->argc) */
-
-	/* default is enabled-after-reset */
-	tap->enabled = !tap->disabled_after_reset;
-
-	jtag_tap_init(tap);
-	return JIM_OK;
-}
-
-/* */
-static int jim_aice_newtap(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
-{
-	struct jim_getopt_info goi;
-	jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
-	return jim_aice_newtap_cmd(&goi);
-}
-
-/* */
-COMMAND_HANDLER(handle_aice_init_command)
-{
-	if (CMD_ARGC != 0)
-		return ERROR_COMMAND_SYNTAX_ERROR;
-
-	static bool jtag_initialized;
-	if (jtag_initialized) {
-		LOG_INFO("'jtag init' has already been called");
-		return ERROR_OK;
-	}
-	jtag_initialized = true;
-
-	LOG_DEBUG("Initializing jtag devices...");
-	return jtag_init(CMD_CTX);
-}
-
-COMMAND_HANDLER(handle_scan_chain_command)
-{
-	struct jtag_tap *tap;
-	char expected_id[12];
-
-	aice_scan_jtag_chain();
-	tap = jtag_all_taps();
-	command_print(CMD,
-		"   TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask");
-	command_print(CMD,
-		"-- ------------------- -------- ---------- ---------- ----- ----- ------");
-
-	while (tap) {
-		uint32_t expected, expected_mask, ii;
-
-		snprintf(expected_id, sizeof(expected_id), "0x%08x",
-			(unsigned)((tap->expected_ids_cnt > 0)
-				   ? tap->expected_ids[0]
-				   : 0));
-		if (tap->ignore_version)
-			expected_id[2] = '*';
-
-		expected = buf_get_u32(tap->expected, 0, tap->ir_length);
-		expected_mask = buf_get_u32(tap->expected_mask, 0, tap->ir_length);
-
-		command_print(CMD,
-			"%2d %-18s     %c     0x%08x %s %5d 0x%02x  0x%02x",
-			tap->abs_chain_position,
-			tap->dotted_name,
-			tap->enabled ? 'Y' : 'n',
-			(unsigned int)(tap->idcode),
-			expected_id,
-			(unsigned int)(tap->ir_length),
-			(unsigned int)(expected),
-			(unsigned int)(expected_mask));
-
-		for (ii = 1; ii < tap->expected_ids_cnt; ii++) {
-			snprintf(expected_id, sizeof(expected_id), "0x%08x",
-				(unsigned) tap->expected_ids[ii]);
-			if (tap->ignore_version)
-				expected_id[2] = '*';
-
-			command_print(CMD,
-				"                                           %s",
-				expected_id);
-		}
-
-		tap = tap->next_tap;
-	}
-
-	return ERROR_OK;
-}
-
-static int jim_aice_arp_init(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
-{
-	LOG_DEBUG("No implement: jim_aice_arp_init");
-
-	return JIM_OK;
-}
-
-/* */
-static int aice_init_reset(struct command_context *cmd_ctx)
-{
-	LOG_DEBUG("Initializing with hard TRST+SRST reset");
-
-	int retval;
-	enum reset_types jtag_reset_config = jtag_get_reset_config();
-
-	jtag_add_reset(1, 0);	/* TAP_RESET */
-	if (jtag_reset_config & RESET_HAS_SRST) {
-		jtag_add_reset(1, 1);
-		if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
-			jtag_add_reset(0, 1);
-	}
-	jtag_add_reset(0, 0);
-	retval = jtag_execute_queue();
-	if (retval != ERROR_OK)
-		return retval;
-
-	return ERROR_OK;
-}
-
-/* */
-static int jim_aice_arp_init_reset(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
-{
-	int e = ERROR_OK;
-	struct jim_getopt_info goi;
-	jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
-	if (goi.argc != 0) {
-		Jim_WrongNumArgs(goi.interp, 1, goi.argv - 1, "(no params)");
-		return JIM_ERR;
-	}
-	struct command_context *context = current_command_context(interp);
-	e = aice_init_reset(context);
-
-	if (e != ERROR_OK) {
-		Jim_Obj *obj = Jim_NewIntObj(goi.interp, e);
-		Jim_SetResultFormatted(goi.interp, "error: %#s", obj);
-		return JIM_ERR;
-	}
-	return JIM_OK;
-}
-
-static int jim_aice_names(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
-{
-	struct jim_getopt_info goi;
-	jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
-	if (goi.argc != 0) {
-		Jim_WrongNumArgs(goi.interp, 1, goi.argv, "Too many parameters");
-		return JIM_ERR;
-	}
-	Jim_SetResult(goi.interp, Jim_NewListObj(goi.interp, NULL, 0));
-	struct jtag_tap *tap;
-
-	for (tap = jtag_all_taps(); tap; tap = tap->next_tap)
-		Jim_ListAppendElement(goi.interp,
-				Jim_GetResult(goi.interp),
-				Jim_NewStringObj(goi.interp,
-					tap->dotted_name, -1));
-
-	return JIM_OK;
-}
-
-/* */
-static const struct command_registration aice_transport_jtag_subcommand_handlers[] = {
-	{
-		.name = "init",
-		.mode = COMMAND_ANY,
-		.handler = handle_aice_init_command,
-		.help = "initialize jtag scan chain",
-		.usage = ""
-	},
-	{
-		.name = "arp_init",
-		.mode = COMMAND_ANY,
-		.jim_handler = jim_aice_arp_init,
-		.help = "Validates JTAG scan chain against the list of "
-			"declared TAPs.",
-	},
-	{
-		.name = "arp_init-reset",
-		.mode = COMMAND_ANY,
-		.jim_handler = jim_aice_arp_init_reset,
-		.help = "Uses TRST and SRST to try resetting everything on "
-			"the JTAG scan chain, then performs 'jtag arp_init'."
-	},
-	{
-		.name = "newtap",
-		.mode = COMMAND_CONFIG,
-		.jim_handler = jim_aice_newtap,
-		.help = "Create a new TAP instance named basename.tap_type, "
-			"and appends it to the scan chain.",
-		.usage = "basename tap_type ['-expected_id' number]"
-	},
-	{
-		.name = "tapisenabled",
-		.mode = COMMAND_EXEC,
-		.jim_handler = jim_jtag_tap_enabler,
-		.help = "Returns a Tcl boolean (0/1) indicating whether "
-			"the TAP is enabled (1) or not (0).",
-		.usage = "tap_name",
-	},
-	{
-		.name = "tapenable",
-		.mode = COMMAND_EXEC,
-		.jim_handler = jim_jtag_tap_enabler,
-		.help = "Try to enable the specified TAP using the "
-			"'tap-enable' TAP event.",
-		.usage = "tap_name",
-	},
-	{
-		.name = "tapdisable",
-		.mode = COMMAND_EXEC,
-		.jim_handler = jim_jtag_tap_enabler,
-		.help = "Try to disable the specified TAP using the "
-			"'tap-disable' TAP event.",
-		.usage = "tap_name",
-	},
-	{
-		.name = "configure",
-		.mode = COMMAND_ANY,
-		.jim_handler = jim_jtag_configure,
-		.help = "Provide a Tcl handler for the specified "
-			"TAP event.",
-		.usage = "tap_name '-event' event_name handler",
-	},
-	{
-		.name = "cget",
-		.mode = COMMAND_EXEC,
-		.jim_handler = jim_jtag_configure,
-		.help = "Return any Tcl handler for the specified "
-			"TAP event.",
-		.usage = "tap_name '-event' event_name",
-	},
-	{
-		.name = "names",
-		.mode = COMMAND_ANY,
-		.jim_handler = jim_aice_names,
-		.help = "Returns list of all JTAG tap names.",
-	},
-	{
-		.name = "scan_chain",
-		.handler = handle_scan_chain_command,
-		.mode = COMMAND_ANY,
-		.help = "print current scan chain configuration",
-		.usage = ""
-	},
-
-	COMMAND_REGISTRATION_DONE
-};
-
-/* */
-static const struct command_registration aice_transport_command_handlers[] = {
-	{
-		.name = "jtag",
-		.mode = COMMAND_ANY,
-		.usage = "",
-		.chain = aice_transport_jtag_subcommand_handlers,
-	},
-	COMMAND_REGISTRATION_DONE
-
-};
-
-/* */
-static int aice_transport_register_commands(struct command_context *cmd_ctx)
-{
-	return register_commands(cmd_ctx, NULL, aice_transport_command_handlers);
-}
-
-/* */
-static int aice_transport_init(struct command_context *cmd_ctx)
-{
-	LOG_DEBUG("aice_transport_init");
-	struct target *t = get_current_target(cmd_ctx);
-	struct transport *transport;
-
-	if (!t) {
-		LOG_ERROR("no current target");
-		return ERROR_FAIL;
-	}
-
-	transport = get_current_transport();
-
-	if (!transport) {
-		LOG_ERROR("no transport selected");
-		return ERROR_FAIL;
-	}
-
-	LOG_DEBUG("current transport %s", transport->name);
-
-	return aice_init_targets();
-}
-
-/* */
-static int aice_transport_select(struct command_context *ctx)
-{
-	LOG_DEBUG("aice_transport_select");
-
-	int retval;
-
-	retval = aice_transport_register_commands(ctx);
-
-	if (retval != ERROR_OK)
-		return retval;
-
-	return ERROR_OK;
-}
-
-static struct transport aice_jtag_transport = {
-	.name = "aice_jtag",
-	.select = aice_transport_select,
-	.init = aice_transport_init,
-};
-
-const char *aice_transports[] = { "aice_jtag", NULL };
-
-static void aice_constructor(void) __attribute__((constructor));
-static void aice_constructor(void)
-{
-	transport_register(&aice_jtag_transport);
-}
diff --git a/src/jtag/aice/aice_transport.h b/src/jtag/aice/aice_transport.h
deleted file mode 100644
index b00003198..000000000
--- a/src/jtag/aice/aice_transport.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/***************************************************************************
- *   Copyright (C) 2013 by Andes Technology                                *
- *   Hsiangkai Wang <hk...@an...>                                 *
- ***************************************************************************/
-
-#ifndef OPENOCD_JTAG_AICE_AICE_TRANSPORT_H
-#define OPENOCD_JTAG_AICE_AICE_TRANSPORT_H
-
-extern const char *aice_transports[];
-
-#endif /* OPENOCD_JTAG_AICE_AICE_TRANSPORT_H */
diff --git a/src/jtag/aice/aice_usb.c b/src/jtag/aice/aice_usb.c
deleted file mode 100644
index b5d0f0b6e..000000000
--- a/src/jtag/aice/aice_usb.c
+++ /dev/null
@@ -1,4099 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/***************************************************************************
- *   Copyright (C) 2013 by Andes Technology                                *
- *   Hsiangkai Wang <hk...@an...>                                 *
- ***************************************************************************/
-#ifdef HAVE_CONFIG_H
-#include ...
 
[truncated message content]

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-2-g8bb926eb0

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  8bb926eb01022998ceefe666f8df102e59404015 (commit)
      from  f8a6553e82919bcfd37436dd6b95e99bb261d04c (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 8bb926eb01022998ceefe666f8df102e59404015
Author: Marc Schink <de...@za...>
Date:   Sun May 22 16:15:00 2022 +0200

    Deprecate libjaylink Git submodule
    
    libjaylink was integrated into OpenOCD as a Git submodule, because at
    that time there was no official release and no packages for it.
    Today there are libjaylink packages for most popular distributions [1].
    
    Removing libjaylink from OpenOCD reduces build complexity in both
    projects and makes them more flexible with respect to the build system,
    for example.
    
    Disable the libjaylink submodule by default and announce it as
    deprecated feature that will be removed in the future. This gives
    package maintainers time to package libjaylink if not already done.
    
    [1] https://repology.org/project/libjaylink/versions
    
    Change-Id: I6166ba4757aee5c89a0506de867072f58fa5ec4b
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7129
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/configure.ac b/configure.ac
index 7f0955f13..4fcc91528 100644
--- a/configure.ac
+++ b/configure.ac
@@ -373,9 +373,9 @@ AC_ARG_ENABLE([jimtcl-maintainer],
   [use_internal_jimtcl_maintainer=$enableval], [use_internal_jimtcl_maintainer=no])
 
 AC_ARG_ENABLE([internal-libjaylink],
-  AS_HELP_STRING([--disable-internal-libjaylink],
-  [Disable building internal libjaylink]),
-  [use_internal_libjaylink=$enableval], [use_internal_libjaylink=yes])
+  AS_HELP_STRING([--enable-internal-libjaylink],
+  [Enable building internal libjaylink]),
+  [use_internal_libjaylink=$enableval], [use_internal_libjaylink=no])
 
 AC_ARG_ENABLE([remote-bitbang],
   AS_HELP_STRING([--enable-remote-bitbang], [Enable building support for the Remote Bitbang jtag driver]),
@@ -713,7 +713,7 @@ AS_IF([test "x$enable_jlink" != "xno"], [
       AX_CONFIG_SUBDIR_OPTION([src/jtag/drivers/libjaylink],
 		[--enable-subproject-build])
     ], [
-      AC_MSG_ERROR([Internal libjaylink not found, run either 'git submodule init' and 'git submodule update' or disable internal libjaylink with --disable-internal-libjaylink.])
+      AC_MSG_ERROR([Internal libjaylink not found, run 'git submodule init' and 'git submodule update'.])
     ])
   ])
 ])
@@ -823,6 +823,12 @@ AC_CONFIG_FILES([
 ])
 AC_OUTPUT
 
+AS_IF([test "x$enable_jlink" != "xno"], [
+  AS_IF([test "x$use_internal_libjaylink" = "xyes"], [
+    AC_MSG_WARN([Using the internal libjaylink is deprecated and will not be possible in the future.])
+  ]])
+)
+
 echo
 echo
 echo OpenOCD configuration summary

-----------------------------------------------------------------------

Summary of changes:
 configure.ac | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1-gf8a6553e8

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  f8a6553e82919bcfd37436dd6b95e99bb261d04c (commit)
       via  9ea7f3d647c8ecf6b0f1424002dfc3f4504a162c (commit)
      from  f71b5f5a37fde4b22cd8eb379c2bc8454c636145 (commit)

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- Log -----------------------------------------------------------------
commit f8a6553e82919bcfd37436dd6b95e99bb261d04c
Author: Paul Fertser <fer...@gm...>
Date:   Sun Jan 15 02:33:06 2023 +0300

    Restore normal development cycle
    
    Signed-off-by: Paul Fertser <fer...@gm...>

diff --git a/NEWS b/NEWS
index 208146a46..9db6c5fee 100644
--- a/NEWS
+++ b/NEWS
@@ -2,126 +2,29 @@ This file includes highlights of the changes made in the OpenOCD
 source archive release.
 
 JTAG Layer:
-	* add default to adapter speed when unspecified (100 kHz)
-	* AM335X gpio (BeagleBones) adapter driver
-	* BCM2835 support for SWD
-	* Cadence Virtual Debug (vdebug) adapter driver
-	* CMSIS-DAP support for SWO and SWD multidrop
-	* Espressif USB JTAG Programmer adapter driver
-	* Remote bitbang support for Windows host
-	* ST-LINK add TCP server support to adapter driver
-	* SWD multidrop support
 
 Boundary Scan:
 
 Target Layer:
-	* aarch64: support watchpoints
-	* arm: support independent TPIU and SWO for trace
-	* arm adi v5: support Large Physical Address Extension
-	* arm adi v6: support added, for jtag and swd transport
-	* cortex_a: support watchpoints
-	* elf 64bit load support
-	* Espressif: support ESP32, ESP32-S2 and ESP32-S3 cores
-	* semihosting: support user defined operations
-	* Xtensa: support Xtensa LX architecture via JTAG and ADIv5 DAP
 
 Flash Layer:
-	* Atmel/Microchip SAM E51G18A, E51G19A, R35J18B, LAN9255 support
-	* GigaDevice GD32E23x, GD32F1x0/3x0, GD32VF103 support
-	* Nuvoton NPCX series support
-	* onsemi RSL10 support
-	* Raspberry Pi Pico RP2040 support
-	* ST BlueNRG-LPS support
-	* ST STM32 G05x, G06x, G0Bx, G0Cx, U57x, U58x, WB1x, WL5x support
-	* ST STM32 G0, G4, L4, L4+, L5, WB, WL OTP support
 
 Board, Target, and Interface Configuration Scripts:
-	* Ampere Computing eMAG8180, Altra ("Quicksilver") and Altra Max ("Mystique") board config
-	* Cadence KC705 FPGA (Xtensa Development Platform) via JTAG and ADIv5 DAP board config
-	* Digilent Nexys Video board config
-	* Espressif ESP32 ETHERNET-KIT and WROVER-KIT board config
-	* Espressif ESP32 via ESP USB Bridge generic board config
-	* Espressif ESP32-S2 Kaluga 1 board config
-	* Espressif ESP32-S2 with ESP USB Bridge board config
-	* Espressif ESP32-S3 example board config
-	* Kontron SMARC-sAL28 board config
-	* LambdaConcept ECPIX-5 board config
-	* Microchip ATSAMA5D27-SOM1-EK1 board config
-	* Microchip EVB-LAN9255 board config
-	* Microchip SAME51 Curiosity Nano board config
-	* NXP FRDM-K64F, LS1046ARDB and LS1088ARDB board config
-	* NXP RT6XX board config
-	* Olimex H405 board config
-	* Radiona ULX3S board config
-	* Raspberry Pi 3 and Raspberry Pi 4 model B board config
-	* Raspberry Pi Pico-Debug board config
-	* Renesas R-Car V3U Falcon board config
-	* ST BlueNRG-LPS steval-idb012v1 board config
-	* ST NUCLEO-8S208RB board config
-	* ST NUCLEO-G031K8, NUCLEO-G070RB, NUCLEO-G071RB board config
-	* ST NUCLEO-G431KB, NUCLEO-G431RB, NUCLEO-G474RE board config
-	* ST STM32MP13x-DK board config
-	* TI AM625 EVM, AM642 EVM and AM654 EVM board config
-	* TI J721E EVM, J721S2 EVM and J7200 EVM board config
-	* Ampere Computing eMAG, Altra ("Quicksilver") and Altra Max ("Mystique") target config
-	* Cadence Xtensa generic and Xtensa VDebug target config
-	* Broadcom BCM2711, BCM2835, BCM2836 and BCM2837 target config
-	* Espressif ESP32, ESP32-S2 and ESP32-S3 target config
-	* Microchip ATSAMA5D2 series target config
-	* NanoXplore NG-Ultra SoC target config
-	* NXP IMX8QM target config
-	* NXP LS1028A, LS1046A and LS1088A target config
-	* NXP RT600 (Xtensa HiFi DSP) target config
-	* onsemi RSL10 target config
-	* Raspberry Pi Pico RP2040 target config
-	* Renesas R8A779A0 V3U target config
-	* Renesas RZ/Five target config
-	* Renesas RZ/G2 MPU family target config
-	* Rockchip RK3399 target config
-	* ST BlueNRG-LPS target config
-	* ST STM32MP13x target config
-	* TI AM625, AM654, J721E and J721S2 target config
-	* Ashling Opella-LD interface config
-	* Aspeed AST2600 linuxgpiod based interface config
-	* Blinkinlabs JTAG_Hat interface config
-	* Cadence Virtual Debug (vdebug) interface config
-	* Espressif ESP32-S2 Kaluga 1 board's interface config
-	* Espressif USB Bridge jtag interface config
-	* Infineon DAP miniWiggler V3 interface config
-	* PLS SPC5 interface config
-	* Tigard interface config
-	* Lattice MachXO3 family FPGA config
 
 Server Layer:
-	* GDB: add per-target remote protocol extensions
-	* GDB: more 'Z' packets support
-	* IPDBG JtagHost server functionality
-	* semihosting: I/O redirection to TCP server
-	* telnet: support for command's autocomplete
 
 RTOS:
-	* 'none' rtos support
-	* Zephyr rtos support
 
 Documentation:
 
 Build and Release:
-	* Add json extension to jimtcl build
-	* Drop dependency from libusb0
-	* Drop repository repo.or.cz for submodules
-	* Move gerrit to https://review.openocd.org/
-	* Require autoconf 2.69 or newer
-	* Update jep106 to revision JEP106BF.01
-	* Update jimtcl to version 0.81
-	* Update libjaylink to version 0.3.1
-	* New configure flag '--enable-jimtcl-maintainer' for jimtcl build
 
 
 This release also contains a number of other important functional and
 cosmetic bugfixes. For more details about what has changed since the
 last release, see the git repository history:
 
-http://sourceforge.net/p/openocd/code/ci/v0.12.0/log/?path=
+http://sourceforge.net/p/openocd/code/ci/v0.x.0/log/?path=
 
 
 For older NEWS, see the NEWS files associated with each release
diff --git a/NEWS b/NEWS-0.12.0
similarity index 100%
copy from NEWS
copy to NEWS-0.12.0
diff --git a/configure.ac b/configure.ac
index eee42d424..7f0955f13 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 AC_PREREQ([2.69])
-AC_INIT([openocd], [0.12.0],
+AC_INIT([openocd], [0.12.0+dev],
   [OpenOCD Mailing List <ope...@li...>])
 AC_CONFIG_SRCDIR([src/openocd.c])
 AC_CONFIG_AUX_DIR([build-aux])

commit 9ea7f3d647c8ecf6b0f1424002dfc3f4504a162c
Author: Paul Fertser <fer...@gm...>
Date:   Sat Jan 14 23:14:31 2023 +0300

    The openocd-0.12.0 release
    
    Signed-off-by: Paul Fertser <fer...@gm...>

diff --git a/NEWS b/NEWS
index 4ebb831ce..208146a46 100644
--- a/NEWS
+++ b/NEWS
@@ -121,7 +121,7 @@ This release also contains a number of other important functional and
 cosmetic bugfixes. For more details about what has changed since the
 last release, see the git repository history:
 
-http://sourceforge.net/p/openocd/code/ci/v0.12.0-rc3/log/?path=
+http://sourceforge.net/p/openocd/code/ci/v0.12.0/log/?path=
 
 
 For older NEWS, see the NEWS files associated with each release
diff --git a/configure.ac b/configure.ac
index a8535213d..eee42d424 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 AC_PREREQ([2.69])
-AC_INIT([openocd], [0.12.0-rc3+dev],
+AC_INIT([openocd], [0.12.0],
   [OpenOCD Mailing List <ope...@li...>])
 AC_CONFIG_SRCDIR([src/openocd.c])
 AC_CONFIG_AUX_DIR([build-aux])

-----------------------------------------------------------------------

Summary of changes:
 NEWS                | 99 +----------------------------------------------------
 NEWS => NEWS-0.12.0 |  2 +-
 configure.ac        |  2 +-
 3 files changed, 3 insertions(+), 100 deletions(-)
 copy NEWS => NEWS-0.12.0 (98%)


hooks/post-receive
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[OpenOCD-commit] Main OpenOCD repository annotated tag, v0.12.0, created. v0.12.0

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The annotated tag, v0.12.0 has been created
        at  5cc204e035530d806f308be5ac22552fdb298a02 (tag)
   tagging  9ea7f3d647c8ecf6b0f1424002dfc3f4504a162c (commit)
  replaces  v0.12.0-rc3
 tagged by  Paul Fertser
        on  Sat Jan 14 23:14:42 2023 +0300

- Log -----------------------------------------------------------------
The openocd-0.12.0 release.

Antonio Borneo (2):
      jtag: esp_usb_jtag: remove macro __packed
      configure.ac: fix check for jimtcl submodule

Marcin Niestroj (1):
      rtt: fix corner-cases of finding control block

Paul Fertser (2):
      Restore +dev suffix
      The openocd-0.12.0 release

-----------------------------------------------------------------------


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-rc3-4-gf71b5f5a3

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  f71b5f5a37fde4b22cd8eb379c2bc8454c636145 (commit)
      from  d92ebb5ab43f6c6a900c6beb0bc426573058c359 (commit)

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- Log -----------------------------------------------------------------
commit f71b5f5a37fde4b22cd8eb379c2bc8454c636145
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jan 14 15:18:02 2023 +0100

    configure.ac: fix check for jimtcl submodule
    
    The file configure.ac checks if jimtcl submodule is present by
    looking for the file jimtcl/configure.ac .
    But jimtcl has switched to its own build system in 2011 and thus
    dropped configure.ac . This cause a build issue on OpenOCD that
    was incorrectly fixed by adding a dummy configure.ac in jimtcl.
    
    Fix OpenOCD configure.ac to look for the correct file
    jimtcl/configure .
    After this fix, another fix would be proposed to jimtcl to drop
    its useless dummy file configure.ac .
    
    Change-Id: I705f72d83e374c8dd700baaa0c0bbe041f153605
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reported-by: Paul Fertser <fer...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7437
    Tested-by: jenkins
    Reviewed-by: Paul Fertser <fer...@gm...>

diff --git a/configure.ac b/configure.ac
index bcacfb240..a8535213d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -574,7 +574,7 @@ AS_IF([test "x$enable_buspirate" != "xno"], [
 ])
 
 AS_IF([test "x$use_internal_jimtcl" = "xyes"], [
-  AS_IF([test -f "$srcdir/jimtcl/configure.ac"], [
+  AS_IF([test -f "$srcdir/jimtcl/configure"], [
     AS_IF([test "x$use_internal_jimtcl_maintainer" = "xyes"], [
       jimtcl_config_options="--disable-install-jim --with-ext=json --maintainer"
     ], [

-----------------------------------------------------------------------

Summary of changes:
 configure.ac | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-rc3-3-gd92ebb5ab

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  d92ebb5ab43f6c6a900c6beb0bc426573058c359 (commit)
       via  7dd5b6a4645cf0ce9c635a7fc8b140575385c827 (commit)
      from  dfe57baa16cdbc0dc2ae7182b5b3831028637223 (commit)

Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit d92ebb5ab43f6c6a900c6beb0bc426573058c359
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Jan 6 12:40:01 2023 +0100

    jtag: esp_usb_jtag: remove macro __packed
    
    In FreeBSB 13.0 the build fails due to redefined macro __packed.
    
            src/jtag/drivers/esp_usb_jtag.c:19:9: error: '__packed' macro
                redefined [-Werror,-Wmacro-redefined]
            #define __packed __attribute__((packed))
                    ^
            /usr/include/sys/cdefs.h:223:9: note: previous definition is here
            #define __packed        __attribute__((__packed__))
                    ^
            1 error generated.
    
    Drop the macro and align the code with the other files in OpenOCD
    project, where the attribute is directly applied without using a
    macro.
    
    Change-Id: I89ae943e77036206d40d4d54172cd4a73e76e5c5
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reported-by: Wojciech Puchar <wo...@pu...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7435
    Tested-by: jenkins
    Reviewed-by: Erhan Kurubas <erh...@es...>

diff --git a/src/jtag/drivers/esp_usb_jtag.c b/src/jtag/drivers/esp_usb_jtag.c
index 65293ee37..dd96f4b39 100644
--- a/src/jtag/drivers/esp_usb_jtag.c
+++ b/src/jtag/drivers/esp_usb_jtag.c
@@ -16,8 +16,6 @@
 #include "bitq.h"
 #include "libusb_helper.h"
 
-#define __packed __attribute__((packed))
-
 /*
 Holy Crap, it's protocol documentation, and it's even vendor-provided!
 
@@ -110,7 +108,7 @@ descriptor.
 struct jtag_proto_caps_hdr {
 	uint8_t proto_ver;	/* Protocol version. Expects JTAG_PROTO_CAPS_VER for now. */
 	uint8_t length;	/* of this plus any following descriptors */
-} __packed;
+} __attribute__((packed));
 
 /* start of the descriptor headers */
 #define JTAG_BUILTIN_DESCR_START_OFF            0	/* Devices with builtin usb jtag */
@@ -133,7 +131,7 @@ of caps header to assume this. If no such caps exist, assume a minimum (in) buff
 struct jtag_gen_hdr {
 	uint8_t type;
 	uint8_t length;
-} __packed;
+} __attribute__((packed));
 
 struct jtag_proto_caps_speed_apb {
 	uint8_t type;					/* Type, always JTAG_PROTO_CAPS_SPEED_APB_TYPE */
@@ -141,7 +139,7 @@ struct jtag_proto_caps_speed_apb {
 	uint8_t apb_speed_10khz[2];		/* ABP bus speed, in 10KHz increments. Base speed is half this. */
 	uint8_t div_min[2];				/* minimum divisor (to base speed), inclusive */
 	uint8_t div_max[2];				/* maximum divisor (to base speed), inclusive */
-} __packed;
+} __attribute__((packed));
 
 #define JTAG_PROTO_CAPS_DATA_LEN                255
 #define JTAG_PROTO_CAPS_SPEED_APB_TYPE          1

commit 7dd5b6a4645cf0ce9c635a7fc8b140575385c827
Author: Marcin Niestroj <m.n...@em...>
Date:   Mon Jan 2 08:04:06 2023 +0100

    rtt: fix corner-cases of finding control block
    
    This patch fixes two corner-cases of finding RTT control block.
    
    The first one is when there was a partial match (even single byte) at
    the end of loaded buffer (uint8_t buf[1024]), but this was not part of
    full match. In that case `cb_offset` was not updated correctly and the
    returned `*address` was lower by the legth of the partial match. In case
    of searched 'SEGGER RTT' (the default control block ID) string, it was
    enough to match `buf[1023] == 'S'`, which is quite likely to happen, and
    the `*address` was offset by 1 (e.g. it was 0x20000fff instead of
    0x20010000).
    
    Updating (or even maintaining) `cb_offset` is not needed, as start
    address of control block can be calculated based on memory address that
    was loaded into `uint8_t buf[1024]`, the offset within this buffer and
    the length of expected string.
    
    The second issue is when control block is prepended with a byte that
    matches first ID character, e.g. there is `SEGGER RTT` control block ID
    is prepended by another `S`, making memory contents be `SSEGGER RTT`. In
    that case there was no match found.
    
    Fix that issue by making sure that tested byte is always compared with
    first byte of expected control block ID.
    
    While at it, change names of local variables to better describe their
    meaning.
    
    Signed-off-by: Marcin Niestroj <m.n...@em...>
    Change-Id: I12aa6e202bf12bedcbb888ab595751a2a2518a24
    Reviewed-on: https://review.openocd.org/c/openocd/+/7429
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/rtt.c b/src/target/rtt.c
index ef2c45d69..b14c42f91 100644
--- a/src/target/rtt.c
+++ b/src/target/rtt.c
@@ -241,43 +241,37 @@ int target_rtt_find_control_block(struct target *target,
 		target_addr_t *address, size_t size, const char *id, bool *found,
 		void *user_data)
 {
+	target_addr_t address_end = *address + size;
 	uint8_t buf[1024];
 
 	*found = false;
 
-	size_t j = 0;
-	size_t cb_offset = 0;
+	size_t id_matched_length = 0;
 	const size_t id_length = strlen(id);
 
 	LOG_INFO("rtt: Searching for control block '%s'", id);
 
-	for (target_addr_t addr = 0; addr < size; addr = addr + sizeof(buf)) {
+	for (target_addr_t addr = *address; addr < address_end; addr += sizeof(buf)) {
 		int ret;
 
-		const size_t buf_size = MIN(sizeof(buf), size - addr);
-		ret = target_read_buffer(target, *address + addr, buf_size, buf);
+		const size_t buf_size = MIN(sizeof(buf), address_end - addr);
+		ret = target_read_buffer(target, addr, buf_size, buf);
 
 		if (ret != ERROR_OK)
 			return ret;
 
-		size_t start = 0;
-		size_t i = 0;
-
-		while (i < buf_size) {
-			if (buf[i] != id[j]) {
-				start++;
-				cb_offset++;
-				i = start;
-				j = 0;
-
-				continue;
+		for (size_t buf_off = 0; buf_off < buf_size; buf_off++) {
+			if (id_matched_length > 0 &&
+			    buf[buf_off] != id[id_matched_length]) {
+				/* Start from beginning */
+				id_matched_length = 0;
 			}
 
-			i++;
-			j++;
+			if (buf[buf_off] == id[id_matched_length])
+				id_matched_length++;
 
-			if (j == id_length) {
-				*address = *address + cb_offset;
+			if (id_matched_length == id_length) {
+				*address = addr + buf_off + 1 - id_length;
 				*found = true;
 				return ERROR_OK;
 			}

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/esp_usb_jtag.c |  8 +++-----
 src/target/rtt.c                | 34 ++++++++++++++--------------------
 2 files changed, 17 insertions(+), 25 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-rc3-1-gdfe57baa1

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  dfe57baa16cdbc0dc2ae7182b5b3831028637223 (commit)
       via  fcb40f49b10fef01debf4ccf1d0faca71a1108fa (commit)
      from  77c281d2df25621782b48d0a45846b93fba3860d (commit)

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- Log -----------------------------------------------------------------
commit dfe57baa16cdbc0dc2ae7182b5b3831028637223
Author: Paul Fertser <fer...@gm...>
Date:   Tue Dec 20 15:49:44 2022 +0300

    Restore +dev suffix
    
    Signed-off-by: Paul Fertser <fer...@gm...>

diff --git a/configure.ac b/configure.ac
index 23c524359..bcacfb240 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 AC_PREREQ([2.69])
-AC_INIT([openocd], [0.12.0-rc3],
+AC_INIT([openocd], [0.12.0-rc3+dev],
   [OpenOCD Mailing List <ope...@li...>])
 AC_CONFIG_SRCDIR([src/openocd.c])
 AC_CONFIG_AUX_DIR([build-aux])

commit fcb40f49b10fef01debf4ccf1d0faca71a1108fa
Author: Antonio Borneo <bor...@gm...>
Date:   Tue Nov 15 22:46:27 2022 +0100

    The openocd-0.12.0-rc3 release candidate
    
    Change-Id: Id7ddf232593e1aa7cb36f2b30fe832ebf79c1535
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/NEWS b/NEWS
index 5bb6e5e7b..4ebb831ce 100644
--- a/NEWS
+++ b/NEWS
@@ -111,7 +111,7 @@ Build and Release:
 	* Drop repository repo.or.cz for submodules
 	* Move gerrit to https://review.openocd.org/
 	* Require autoconf 2.69 or newer
-	* Update jep106 to revision JEP106BE
+	* Update jep106 to revision JEP106BF.01
 	* Update jimtcl to version 0.81
 	* Update libjaylink to version 0.3.1
 	* New configure flag '--enable-jimtcl-maintainer' for jimtcl build
@@ -121,7 +121,7 @@ This release also contains a number of other important functional and
 cosmetic bugfixes. For more details about what has changed since the
 last release, see the git repository history:
 
-http://sourceforge.net/p/openocd/code/ci/v0.12.0-rc2/log/?path=
+http://sourceforge.net/p/openocd/code/ci/v0.12.0-rc3/log/?path=
 
 
 For older NEWS, see the NEWS files associated with each release
diff --git a/configure.ac b/configure.ac
index 503e79169..23c524359 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 AC_PREREQ([2.69])
-AC_INIT([openocd], [0.12.0-rc2+dev],
+AC_INIT([openocd], [0.12.0-rc3],
   [OpenOCD Mailing List <ope...@li...>])
 AC_CONFIG_SRCDIR([src/openocd.c])
 AC_CONFIG_AUX_DIR([build-aux])

-----------------------------------------------------------------------

Summary of changes:
 NEWS         | 4 ++--
 configure.ac | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository annotated tag, v0.12.0-rc3, created. v0.12.0-rc3

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The annotated tag, v0.12.0-rc3 has been created
        at  e758ddc77236c03e9759115dcafacb7f6d776728 (tag)
   tagging  fcb40f49b10fef01debf4ccf1d0faca71a1108fa (commit)
  replaces  v0.12.0-rc2
 tagged by  Paul Fertser
        on  Tue Dec 20 13:52:22 2022 +0300

- Log -----------------------------------------------------------------
The openocd-0.12.0-rc3 release.

Andreas Bolsch (1):
      Fix for segfault and some clang reported problems in stmqspi

Antonio Borneo (17):
      helper/types: use unsigned type for all h_u64_to_le() and similar
      openrisc: fix clang error core.CallAndMessage
      esirisc_jtag: fix clang error core.VLASize
      dsp5680xx: fix clang error core.UndefinedBinaryOperatorResult
      flash: stmqspi: fix clang error 'dead assignment'
      rtos: hwthread: fix clang error core.NullDereference
      jep106: update to revision JEP106BF.01 Oct 2022
      flash: lpc2900: fix clang error 'dead assignment'
      jtag: xds110: fix clang error core.StackAddressEscape
      arm_adi_v5: fix SIGSEGV due to failing re-examine
      target: cortex_a: fix clang error core.CallAndMessage
      target: fix unsigned computation in 'monitor profile'
      target: fix assert in 'monitor profile' on constant PC
      driver: vdebug: fix mode of cmd 'vdebug mem_path'
      jtag: fix build with configure --enable-verbose
      cortex_m: handle armv8m cores without security extension
      The openocd-0.12.0-rc3 release candidate

Ben McMorran (1):
      ThreadX: set current_thread for kernel execution

Dan Stahlke (1):
      at91samd: wait for nvm ready

Daniel Anselmi (1):
      pld/virtex2: small doc extension

Evgeniy Naydanov (1):
      Fix jim_target_smp for smp rtos target

George Voicu (1):
      tcl/cpld/xilinx-xcu: fix typo

Giulio Fieramosca (1):
      rtos/ThreadX: added check for NULL-named tasks

Karl Palsson (1):
      doc: describe tcl port consistently.

Koudai Iwahori (2):
      hwthread: Add register validity check in get_thread_reg_list
      hwthread: Restore current_threadid in hwthread_update_threads

Marc Schink (1):
      flash/nor/stm32lx: Add revision '1, X' for Cat.2 devices

Nick Kraus (1):
      jtag/drivers/cmsis_dap.c: Fix Length of SWO Baudrate Command

Nima Palizban (1):
      src/target/mips_m4k.c: set missing flag in set_watchpoint

Paul Fertser (1):
      Restore +dev suffix

Rocco Marco Guglielmi (1):
      tcl: max326xx: fix target scripts for latest version of OpenOCD

Simon Smiganovski (1):
      flash/nor/stm32f1x: adjust size of the flash loader buffer

Tomas Vanek (5):
      jtag/drivers/cmsis_dap: prevent CDC missdetect as CMSIS-DAP bulk
      Revert "Remove duplicate of a counter in hwthread_update_threads"
      tcl/interface: fix raspberrypi2-native.cfg speed coefficient
      target/armv7m: prevent saving and restoring non existent regs
      target/armv7m: fix feature name of ARMv8M security extension regs

-----------------------------------------------------------------------


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commit 77c281d2df25621782b48d0a45846b93fba3860d
Author: Antonio Borneo <bor...@gm...>
Date:   Wed Dec 14 15:54:53 2022 +0100

    cortex_m: handle armv8m cores without security extension
    
    Cores armv8m, e.g. Cortex-M33, can be instantiated without the
    optional Security Extension.
    In this case, the secure registers are not present and when GDB
    try accessing them it triggers a set of errors.
    
    For armv8m cores without security extension, don't provide to GDB
    the description of the secure registers.
    
    Change-Id: I254478a4cf883e85b786df3f62c726b2f40d88d9
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reported-by: Torbjörn SVENSSON <tor...@fo...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7402
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 2472e38e2..017a6d3a1 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2270,6 +2270,22 @@ static void cortex_m_dwt_free(struct target *target)
 	cm->dwt_cache = NULL;
 }
 
+static bool cortex_m_has_tz(struct target *target)
+{
+	struct armv7m_common *armv7m = target_to_armv7m(target);
+	uint32_t dauthstatus;
+
+	if (armv7m->arm.arch != ARM_ARCH_V8M)
+		return false;
+
+	int retval = target_read_u32(target, DAUTHSTATUS, &dauthstatus);
+	if (retval != ERROR_OK) {
+		LOG_WARNING("Error reading DAUTHSTATUS register");
+		return false;
+	}
+	return (dauthstatus & DAUTHSTATUS_SID_MASK) != 0;
+}
+
 #define MVFR0 0xe000ef40
 #define MVFR1 0xe000ef44
 
@@ -2398,7 +2414,7 @@ int cortex_m_examine(struct target *target)
 			for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++)
 				armv7m->arm.core_cache->reg_list[idx].exist = false;
 
-		if (armv7m->arm.arch != ARM_ARCH_V8M)
+		if (!cortex_m_has_tz(target))
 			for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++)
 				armv7m->arm.core_cache->reg_list[idx].exist = false;
 
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index b1de26ebc..a1c43b56d 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -68,6 +68,9 @@ struct cortex_m_part_info {
 #define DCB_DEMCR	0xE000EDFC
 #define DCB_DSCSR	0xE000EE08
 
+#define DAUTHSTATUS	0xE000EFB8
+#define DAUTHSTATUS_SID_MASK	0x00000030
+
 #define DCRSR_WNR	BIT(16)
 
 #define DWT_CTRL	0xE0001000

-----------------------------------------------------------------------

Summary of changes:
 src/target/cortex_m.c | 18 +++++++++++++++++-
 src/target/cortex_m.h |  3 +++
 2 files changed, 20 insertions(+), 1 deletion(-)


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commit c913e4d5a6cafab9a19735c440be8d0c111b2088
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Dec 17 23:05:23 2022 +0100

    jtag: fix build with configure --enable-verbose
    
    With flag --enable-verbose, configure enables compiling some
    conditional code that with new gcc triggers an error:
            error: '%04x' directive output may be truncated writing
            between 4 and 8 bytes into a region of size 5
            [-Werror=format-truncation=]
    
    Extend the buffer to contain the full 8 bytes of %04x on a 'int'
    and change the limit in snprintf.
    Skip the intermediate buffer 's[4]'.
    Align the code to the coding style.
    
    Change-Id: Ifc8a6e4686555578a7355a1f6049471fd5e31913
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reported-by: Karl Hammar <ka...@as...>
    Reported-by: Tommy Murphy <tom...@ho...>
    Fixes: https://sourceforge.net/p/openocd/tickets/376/
    Reviewed-on: https://review.openocd.org/c/openocd/+/7403
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/jtag/drivers/arm-jtag-ew.c b/src/jtag/drivers/arm-jtag-ew.c
index a3e9e1712..7db3c7b15 100644
--- a/src/jtag/drivers/arm-jtag-ew.c
+++ b/src/jtag/drivers/arm-jtag-ew.c
@@ -776,17 +776,12 @@ static int armjtagew_usb_read(struct armjtagew *armjtagew, int exp_in_length)
 
 static void armjtagew_debug_buffer(uint8_t *buffer, int length)
 {
-	char line[81];
-	char s[4];
-	int i;
-	int j;
+	char line[8 + 3 * BYTES_PER_LINE + 1];
 
-	for (i = 0; i < length; i += BYTES_PER_LINE) {
-		snprintf(line, 5, "%04x", i);
-		for (j = i; j < i + BYTES_PER_LINE && j < length; j++) {
-			snprintf(s, 4, " %02x", buffer[j]);
-			strcat(line, s);
-		}
+	for (int i = 0; i < length; i += BYTES_PER_LINE) {
+		int n = snprintf(line, 9, "%04x", i);
+		for (int j = i; j < i + BYTES_PER_LINE && j < length; j++)
+			n += snprintf(line + n, 4, " %02x", buffer[j]);
 		LOG_DEBUG("%s", line);
 
 		/* Prevent GDB timeout (writing to log might take some time) */
diff --git a/src/jtag/drivers/opendous.c b/src/jtag/drivers/opendous.c
index d0c527788..c353aef40 100644
--- a/src/jtag/drivers/opendous.c
+++ b/src/jtag/drivers/opendous.c
@@ -796,17 +796,12 @@ int opendous_usb_read(struct opendous_jtag *opendous_jtag)
 
 void opendous_debug_buffer(uint8_t *buffer, int length)
 {
-	char line[81];
-	char s[4];
-	int i;
-	int j;
+	char line[8 + 3 * BYTES_PER_LINE + 1];
 
-	for (i = 0; i < length; i += BYTES_PER_LINE) {
-		snprintf(line, 5, "%04x", i);
-		for (j = i; j < i + BYTES_PER_LINE && j < length; j++) {
-			snprintf(s, 4, " %02x", buffer[j]);
-			strcat(line, s);
-		}
+	for (int i = 0; i < length; i += BYTES_PER_LINE) {
+		int n = snprintf(line, 9, "%04x", i);
+		for (int j = i; j < i + BYTES_PER_LINE && j < length; j++)
+			n += snprintf(line + n, 4, " %02x", buffer[j]);
 		LOG_DEBUG("%s", line);
 	}
 }

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/arm-jtag-ew.c | 15 +++++----------
 src/jtag/drivers/opendous.c    | 15 +++++----------
 2 files changed, 10 insertions(+), 20 deletions(-)


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- Log -----------------------------------------------------------------
commit 77c7abe4e7569ca8bb23dad6110c7209c8c55558
Author: Dan Stahlke <da...@st...>
Date:   Sun Dec 4 18:12:16 2022 -0800

    at91samd: wait for nvm ready
    
    Flashing a SAMD21J17D was failing during NVM erase.  The samd21
    datasheet specifies that one cause of error conditions is executing an
    NVM command while the previous command is still running.  The solution
    is to wait for INTFLAG.READY after a command is issued.
    
    SAMD21J17A was not exhibiting this problem.  Perhaps the later silicon
    revision has slower NVM erase times.
    
    Signed-off-by: Dan Stahlke <da...@st...>
    Change-Id: I19745dae4d3fc6e3a7611dcac628e067cb41e0f0
    Reviewed-on: https://review.openocd.org/c/openocd/+/7391
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/at91samd.c b/src/flash/nor/at91samd.c
index f213444d1..33e86c76e 100644
--- a/src/flash/nor/at91samd.c
+++ b/src/flash/nor/at91samd.c
@@ -12,6 +12,7 @@
 #include "imp.h"
 #include "helper/binarybuffer.h"
 
+#include <helper/time_support.h>
 #include <jtag/jtag.h>
 #include <target/cortex_m.h>
 
@@ -31,7 +32,7 @@
 #define SAMD_NVMCTRL_CTRLA		0x00	/* NVM control A register */
 #define SAMD_NVMCTRL_CTRLB		0x04	/* NVM control B register */
 #define SAMD_NVMCTRL_PARAM		0x08	/* NVM parameters register */
-#define SAMD_NVMCTRL_INTFLAG	0x18	/* NVM Interrupt Flag Status & Clear */
+#define SAMD_NVMCTRL_INTFLAG	0x14	/* NVM Interrupt Flag Status & Clear */
 #define SAMD_NVMCTRL_STATUS		0x18	/* NVM status register */
 #define SAMD_NVMCTRL_ADDR		0x1C	/* NVM address register */
 #define SAMD_NVMCTRL_LOCK		0x20	/* NVM Lock section register */
@@ -55,6 +56,9 @@
 /* NVMCTRL bits */
 #define SAMD_NVM_CTRLB_MANW 0x80
 
+/* NVMCTRL_INTFLAG bits */
+#define SAMD_NVM_INTFLAG_READY 0x01
+
 /* Known identifiers */
 #define SAMD_PROCESSOR_M0	0x01
 #define SAMD_FAMILY_D		0x00
@@ -497,7 +501,27 @@ static int samd_probe(struct flash_bank *bank)
 static int samd_check_error(struct target *target)
 {
 	int ret, ret2;
+	uint8_t intflag;
 	uint16_t status;
+	int timeout_ms = 1000;
+	int64_t ts_start = timeval_ms();
+
+	do {
+		ret = target_read_u8(target,
+			SAMD_NVMCTRL + SAMD_NVMCTRL_INTFLAG, &intflag);
+		if (ret != ERROR_OK) {
+			LOG_ERROR("Can't read NVM intflag");
+			return ret;
+		}
+		if (intflag & SAMD_NVM_INTFLAG_READY)
+			break;
+		keep_alive();
+	} while (timeval_ms() - ts_start < timeout_ms);
+
+	if (!(intflag & SAMD_NVM_INTFLAG_READY)) {
+		LOG_ERROR("SAMD: NVM programming timed out");
+		return ERROR_FLASH_OPERATION_FAILED;
+	}
 
 	ret = target_read_u16(target,
 			SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);

commit 0a829efda5c254ceca2371edb38e9b0e4a998706
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Dec 11 11:08:32 2022 +0100

    driver: vdebug: fix mode of cmd 'vdebug mem_path'
    
    The command 'vdebug mem_path' is reported in the documentation as
    '{Config Command}', but the code sets mode = COMMAND_ANY.
    The code of the commands sets some value that is only used during
    the init phase, so the documentation is correct.
    
    Change mode of command 'vdebug mem_path' to COMMAND_CONFIG.
    
    Change-Id: Icb940fe382cbc75015273b35dcc8a88fc2a7d0ac
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7395
    Tested-by: jenkins
    Reviewed-by: Jacek Wuwer <jac...@gm...>

diff --git a/src/jtag/drivers/vdebug.c b/src/jtag/drivers/vdebug.c
index ef7a49332..7898e9d9b 100644
--- a/src/jtag/drivers/vdebug.c
+++ b/src/jtag/drivers/vdebug.c
@@ -1246,7 +1246,7 @@ static const struct command_registration vdebug_command_handlers[] = {
 	{
 		.name = "mem_path",
 		.handler = &vdebug_set_mem,
-		.mode = COMMAND_ANY,
+		.mode = COMMAND_CONFIG,
 		.help = "set the design memory for the code load",
 		.usage = "<path> <base_address> <size>",
 	},

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/at91samd.c  | 26 +++++++++++++++++++++++++-
 src/jtag/drivers/vdebug.c |  2 +-
 2 files changed, 26 insertions(+), 2 deletions(-)


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- Log -----------------------------------------------------------------
commit 2b6fe8f1ab739798309b47f7b3a664894ba43a19
Author: Antonio Borneo <bor...@gm...>
Date:   Wed Dec 14 15:21:43 2022 +0100

    target: fix assert in 'monitor profile' on constant PC
    
    When target is stopped in WFI/WFE or is in an infinite loop, the
    sampled PC will always return the same value.
    Command 'profile' requires that distance between min and max PC
    should be at least 2, which is not the case for constant PC, and
    incorrectly enforces the check through as assert().
    
    Move the code that reads the optional parameters 'start' and 'end'
    and check the gap 'end - start' before running the profile.
    For self-computed min and max, increase max (or decrease min) to
    match the required constraint.
    Drop the assert().
    
    Change-Id: I2be8df8568ce8c889923888c492e4f7ce354b16b
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Fixes: https://sourceforge.net/p/openocd/tickets/370/
    Reviewed-on: https://review.openocd.org/c/openocd/+/7400
    Tested-by: jenkins

diff --git a/src/target/target.c b/src/target/target.c
index 755a8e283..e3a6f955e 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -4253,10 +4253,17 @@ static void write_gmon(uint32_t *samples, uint32_t sample_num, const char *filen
 		 * Refer to binutils/gprof/hist.c (find_histogram_for_pc) */
 		if (max < UINT32_MAX)
 			max++;
+
+		/* gprof requires (max - min) >= 2 */
+		while ((max - min) < 2) {
+			if (max < UINT32_MAX)
+				max++;
+			else
+				min--;
+		}
 	}
 
 	uint32_t address_space = max - min;
-	assert(address_space >= 2);
 
 	/* FIXME: What is the reasonable number of buckets?
 	 * The profiling result will be more accurate if there are enough buckets. */
@@ -4332,6 +4339,19 @@ COMMAND_HANDLER(handle_profile_command)
 
 	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], offset);
 
+	uint32_t start_address = 0;
+	uint32_t end_address = 0;
+	bool with_range = false;
+	if (CMD_ARGC == 4) {
+		with_range = true;
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], start_address);
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], end_address);
+		if (start_address > end_address || (end_address - start_address) < 2) {
+			command_print(CMD, "Error: end - start < 2");
+			return ERROR_COMMAND_ARGUMENT_INVALID;
+		}
+	}
+
 	uint32_t *samples = malloc(sizeof(uint32_t) * MAX_PROFILE_SAMPLE_NUM);
 	if (!samples) {
 		LOG_ERROR("No memory to store samples.");
@@ -4384,15 +4404,6 @@ COMMAND_HANDLER(handle_profile_command)
 		return retval;
 	}
 
-	uint32_t start_address = 0;
-	uint32_t end_address = 0;
-	bool with_range = false;
-	if (CMD_ARGC == 4) {
-		with_range = true;
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], start_address);
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], end_address);
-	}
-
 	write_gmon(samples, num_of_samples, CMD_ARGV[1],
 		   with_range, start_address, end_address, target, duration_ms);
 	command_print(CMD, "Wrote %s", CMD_ARGV[1]);

-----------------------------------------------------------------------

Summary of changes:
 src/target/target.c | 31 +++++++++++++++++++++----------
 1 file changed, 21 insertions(+), 10 deletions(-)


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- Log -----------------------------------------------------------------
commit a51ac964c6160646f2c28db854aa8faf096eb314
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Dec 11 10:11:58 2022 +0100

    target: fix unsigned computation in 'monitor profile'
    
    The implementation of command 'monitor profile' has few
    issues:
    - the address_space is a signed int, so cannot wrap-around on
      space over INT_MAX;
    - max address is incremented without check for overflow;
    - assert() used on errors instead of returning error codes;
    - only handles 32 bits PC;
    - output file created and left empty on error.
    
    This patch fixes the first two issues, as a wider fix would be too
    invasive and should be postponed in a following series.
    
    Change-Id: Id8ead3f6db0fd5730682a0d1638f11836d06a632
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Fixes: https://sourceforge.net/p/openocd/tickets/370/
    Reviewed-on: https://review.openocd.org/c/openocd/+/7394
    Tested-by: jenkins

diff --git a/src/target/target.c b/src/target/target.c
index e4fe20f72..755a8e283 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -4251,10 +4251,11 @@ static void write_gmon(uint32_t *samples, uint32_t sample_num, const char *filen
 
 		/* max should be (largest sample + 1)
 		 * Refer to binutils/gprof/hist.c (find_histogram_for_pc) */
-		max++;
+		if (max < UINT32_MAX)
+			max++;
 	}
 
-	int address_space = max - min;
+	uint32_t address_space = max - min;
 	assert(address_space >= 2);
 
 	/* FIXME: What is the reasonable number of buckets?

-----------------------------------------------------------------------

Summary of changes:
 src/target/target.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)


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commit a6b02219529d1d48d130e4bed9c8d55395662ff6
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Dec 10 22:15:44 2022 +0100

    target: cortex_a: fix clang error core.CallAndMessage
    
    Clang complains about the variable 'orig_dfsr' that can be used
    uninitialized both in cortex_a_read_cpu_memory() and in
    cortex_a_write_cpu_memory().
    
    The issue is caused by an incorrect error path that used to jump
    through 'goto out'. The code after the label 'out' is specific to
    handle the case of an error during memory R/W; it is incorrect to
    jump there to handle an error during the initialization that
    precedes the memory R/W.
    
    Replace the 'goto out' with 'return retval'.
    Remove the label 'out' that is now unused.
    
    Change-Id: Ib4b140221d1c1b63419de109579bde8b63fc2e8c
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7393
    Tested-by: jenkins

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 07796d57c..3db9c62a5 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2246,7 +2246,7 @@ static int cortex_a_write_cpu_memory(struct target *target,
 	/* Switch to non-blocking mode if not already in that mode. */
 	retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, &dscr);
 	if (retval != ERROR_OK)
-		goto out;
+		return retval;
 
 	/* Mark R0 as dirty. */
 	arm_reg_current(arm, 0)->dirty = true;
@@ -2254,16 +2254,16 @@ static int cortex_a_write_cpu_memory(struct target *target,
 	/* Read DFAR and DFSR, as they will be modified in the event of a fault. */
 	retval = cortex_a_read_dfar_dfsr(target, &orig_dfar, &orig_dfsr, &dscr);
 	if (retval != ERROR_OK)
-		goto out;
+		return retval;
 
 	/* Get the memory address into R0. */
 	retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
 			armv7a->debug_base + CPUDBG_DTRRX, address);
 	if (retval != ERROR_OK)
-		goto out;
+		return retval;
 	retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
 	if (retval != ERROR_OK)
-		goto out;
+		return retval;
 
 	if (size == 4 && (address % 4) == 0) {
 		/* We are doing a word-aligned transfer, so use fast mode. */
@@ -2288,7 +2288,6 @@ static int cortex_a_write_cpu_memory(struct target *target,
 		retval = cortex_a_write_cpu_memory_slow(target, size, count, buffer, &dscr);
 	}
 
-out:
 	final_retval = retval;
 
 	/* Switch to non-blocking mode if not already in that mode. */
@@ -2564,7 +2563,7 @@ static int cortex_a_read_cpu_memory(struct target *target,
 	/* Switch to non-blocking mode if not already in that mode. */
 	retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, &dscr);
 	if (retval != ERROR_OK)
-		goto out;
+		return retval;
 
 	/* Mark R0 as dirty. */
 	arm_reg_current(arm, 0)->dirty = true;
@@ -2572,16 +2571,16 @@ static int cortex_a_read_cpu_memory(struct target *target,
 	/* Read DFAR and DFSR, as they will be modified in the event of a fault. */
 	retval = cortex_a_read_dfar_dfsr(target, &orig_dfar, &orig_dfsr, &dscr);
 	if (retval != ERROR_OK)
-		goto out;
+		return retval;
 
 	/* Get the memory address into R0. */
 	retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
 			armv7a->debug_base + CPUDBG_DTRRX, address);
 	if (retval != ERROR_OK)
-		goto out;
+		return retval;
 	retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
 	if (retval != ERROR_OK)
-		goto out;
+		return retval;
 
 	if (size == 4 && (address % 4) == 0) {
 		/* We are doing a word-aligned transfer, so use fast mode. */
@@ -2607,7 +2606,6 @@ static int cortex_a_read_cpu_memory(struct target *target,
 		retval = cortex_a_read_cpu_memory_slow(target, size, count, buffer, &dscr);
 	}
 
-out:
 	final_retval = retval;
 
 	/* Switch to non-blocking mode if not already in that mode. */

-----------------------------------------------------------------------

Summary of changes:
 src/target/cortex_a.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)


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- Log -----------------------------------------------------------------
commit c6fe10de75763623dfdaaf2fe3fff7e78a4ca146
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Dec 10 18:19:54 2022 +0100

    arm_adi_v5: fix SIGSEGV due to failing re-examine
    
    Commit 35a503b08d14 ("arm_adi_v5: add ap refcount and add get/put
    around ap use") modifies the examine functions of mem_ap, cortex_m,
    cortex_a and aarch64 by calling dap_put_ap() and then looking again
    for the mem-ap and calling dap_get_ap().
    This causes an issue if the system is irresponsive and the examine
    fails and left the AP pointer to NULL. If the system was already
    examined the NULL pointer will cause a SIGSEGV.
    
    Commit b6dad912b85d ("target/cortex_m: prevent segmentation fault
    in cortex_m_poll()") proposes a fix for one specific case and only
    on cortex_m.
    
    Modify all the examine functions by skipping look-up for the AP if
    it was already set in a previous examine; the target's AP is not
    supposed to change during runtime.
    
    Remove the partial fix for cortex_m as it is not needed anymore.
    
    Change-Id: I806ec3b1b02fcc76e141c8dd3a65044febbf0a8c
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Fixes: 35a503b08d14 ("arm_adi_v5: add ap refcount and add get/put around ap use")
    Reviewed-on: https://review.openocd.org/c/openocd/+/7392
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 8592daa16..8e90e6400 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -2546,23 +2546,20 @@ static int aarch64_examine_first(struct target *target)
 	if (!pc)
 		return ERROR_FAIL;
 
-	if (armv8->debug_ap) {
-		dap_put_ap(armv8->debug_ap);
-		armv8->debug_ap = NULL;
-	}
-
-	if (pc->adiv5_config.ap_num == DP_APSEL_INVALID) {
-		/* Search for the APB-AB */
-		retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &armv8->debug_ap);
-		if (retval != ERROR_OK) {
-			LOG_ERROR("Could not find APB-AP for debug access");
-			return retval;
-		}
-	} else {
-		armv8->debug_ap = dap_get_ap(swjdp, pc->adiv5_config.ap_num);
-		if (!armv8->debug_ap) {
-			LOG_ERROR("Cannot get AP");
-			return ERROR_FAIL;
+	if (!armv8->debug_ap) {
+		if (pc->adiv5_config.ap_num == DP_APSEL_INVALID) {
+			/* Search for the APB-AB */
+			retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &armv8->debug_ap);
+			if (retval != ERROR_OK) {
+				LOG_ERROR("Could not find APB-AP for debug access");
+				return retval;
+			}
+		} else {
+			armv8->debug_ap = dap_get_ap(swjdp, pc->adiv5_config.ap_num);
+			if (!armv8->debug_ap) {
+				LOG_ERROR("Cannot get AP");
+				return ERROR_FAIL;
+			}
 		}
 	}
 
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 7286a305b..07796d57c 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2874,23 +2874,20 @@ static int cortex_a_examine_first(struct target *target)
 	int retval = ERROR_OK;
 	uint32_t didr, cpuid, dbg_osreg, dbg_idpfr1;
 
-	if (armv7a->debug_ap) {
-		dap_put_ap(armv7a->debug_ap);
-		armv7a->debug_ap = NULL;
-	}
-
-	if (pc->ap_num == DP_APSEL_INVALID) {
-		/* Search for the APB-AP - it is needed for access to debug registers */
-		retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
-		if (retval != ERROR_OK) {
-			LOG_ERROR("Could not find APB-AP for debug access");
-			return retval;
-		}
-	} else {
-		armv7a->debug_ap = dap_get_ap(swjdp, pc->ap_num);
-		if (!armv7a->debug_ap) {
-			LOG_ERROR("Cannot get AP");
-			return ERROR_FAIL;
+	if (!armv7a->debug_ap) {
+		if (pc->ap_num == DP_APSEL_INVALID) {
+			/* Search for the APB-AP - it is needed for access to debug registers */
+			retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
+			if (retval != ERROR_OK) {
+				LOG_ERROR("Could not find APB-AP for debug access");
+				return retval;
+			}
+		} else {
+			armv7a->debug_ap = dap_get_ap(swjdp, pc->ap_num);
+			if (!armv7a->debug_ap) {
+				LOG_ERROR("Cannot get AP");
+				return ERROR_FAIL;
+			}
 		}
 	}
 
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 186344167..2472e38e2 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -879,16 +879,6 @@ static int cortex_m_poll(struct target *target)
 	struct cortex_m_common *cortex_m = target_to_cm(target);
 	struct armv7m_common *armv7m = &cortex_m->armv7m;
 
-	/* Check if debug_ap is available to prevent segmentation fault.
-	 * If the re-examination after an error does not find a MEM-AP
-	 * (e.g. the target stopped communicating), debug_ap pointer
-	 * can suddenly become NULL.
-	 */
-	if (!armv7m->debug_ap) {
-		target->state = TARGET_UNKNOWN;
-		return ERROR_TARGET_NOT_EXAMINED;
-	}
-
 	/* Read from Debug Halting Control and Status Register */
 	retval = cortex_m_read_dhcsr_atomic_sticky(target);
 	if (retval != ERROR_OK) {
@@ -2311,23 +2301,20 @@ int cortex_m_examine(struct target *target)
 	/* hla_target shares the examine handler but does not support
 	 * all its calls */
 	if (!armv7m->is_hla_target) {
-		if (armv7m->debug_ap) {
-			dap_put_ap(armv7m->debug_ap);
-			armv7m->debug_ap = NULL;
-		}
-
-		if (cortex_m->apsel == DP_APSEL_INVALID) {
-			/* Search for the MEM-AP */
-			retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
-			if (retval != ERROR_OK) {
-				LOG_TARGET_ERROR(target, "Could not find MEM-AP to control the core");
-				return retval;
-			}
-		} else {
-			armv7m->debug_ap = dap_get_ap(swjdp, cortex_m->apsel);
-			if (!armv7m->debug_ap) {
-				LOG_ERROR("Cannot get AP");
-				return ERROR_FAIL;
+		if (!armv7m->debug_ap) {
+			if (cortex_m->apsel == DP_APSEL_INVALID) {
+				/* Search for the MEM-AP */
+				retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
+				if (retval != ERROR_OK) {
+					LOG_TARGET_ERROR(target, "Could not find MEM-AP to control the core");
+					return retval;
+				}
+			} else {
+				armv7m->debug_ap = dap_get_ap(swjdp, cortex_m->apsel);
+				if (!armv7m->debug_ap) {
+					LOG_ERROR("Cannot get AP");
+					return ERROR_FAIL;
+				}
 			}
 		}
 
diff --git a/src/target/mem_ap.c b/src/target/mem_ap.c
index a66250693..50dc91c7b 100644
--- a/src/target/mem_ap.c
+++ b/src/target/mem_ap.c
@@ -136,15 +136,12 @@ static int mem_ap_examine(struct target *target)
 	struct mem_ap *mem_ap = target->arch_info;
 
 	if (!target_was_examined(target)) {
-		if (mem_ap->ap) {
-			dap_put_ap(mem_ap->ap);
-			mem_ap->ap = NULL;
-		}
-
-		mem_ap->ap = dap_get_ap(mem_ap->dap, mem_ap->ap_num);
 		if (!mem_ap->ap) {
-			LOG_ERROR("Cannot get AP");
-			return ERROR_FAIL;
+			mem_ap->ap = dap_get_ap(mem_ap->dap, mem_ap->ap_num);
+			if (!mem_ap->ap) {
+				LOG_ERROR("Cannot get AP");
+				return ERROR_FAIL;
+			}
 		}
 		target_set_examined(target);
 		target->state = TARGET_UNKNOWN;

-----------------------------------------------------------------------

Summary of changes:
 src/target/aarch64.c  | 31 ++++++++++++++-----------------
 src/target/cortex_a.c | 31 ++++++++++++++-----------------
 src/target/cortex_m.c | 41 ++++++++++++++---------------------------
 src/target/mem_ap.c   | 13 +++++--------
 4 files changed, 47 insertions(+), 69 deletions(-)


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