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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-758-gdb0d4dbc3

From: OpenOCD-Gerrit <ope...@us...> - 2022-07-23 13:14:06

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  db0d4dbc3f1edbaae0057ff356f501b2aa31f69d (commit)
      from  dba88e0238716f2fe0ff861d493cbace88a6bec3 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit db0d4dbc3f1edbaae0057ff356f501b2aa31f69d
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jun 26 11:07:45 2022 +0200

    openocd: src: add GPL license tag on files that miss it
    
    Some file miss completely the license tag.
    
    Add the SPDX tag, using the same GPL-2.0-or-later license of the
    OpenOCD project.
    
    The SPDX tag on files *.c is incorrect, as it should use the C99
    single line comment using '//'. But current checkpatch doesn't
    allow C99 comments, so keep using standard C comments, by now.
    
    Change-Id: I1fb51e722232d14f050458a820c3041de3dc9138
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7058
    Tested-by: jenkins

diff --git a/src/flash/nor/fm4.c b/src/flash/nor/fm4.c
index 09865d2ab..2881f1201 100644
--- a/src/flash/nor/fm4.c
+++ b/src/flash/nor/fm4.c
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 /*
  * Spansion FM4 flash
  *
diff --git a/src/jtag/drivers/cmsis_dap.h b/src/jtag/drivers/cmsis_dap.h
index 7c64d492c..cf929b069 100644
--- a/src/jtag/drivers/cmsis_dap.h
+++ b/src/jtag/drivers/cmsis_dap.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 #ifndef OPENOCD_JTAG_DRIVERS_CMSIS_DAP_H
 #define OPENOCD_JTAG_DRIVERS_CMSIS_DAP_H
 
diff --git a/src/rtos/linux_header.h b/src/rtos/linux_header.h
index a2b408efd..79199643c 100644
--- a/src/rtos/linux_header.h
+++ b/src/rtos/linux_header.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 #ifndef OPENOCD_RTOS_LINUX_HEADER_H
 #define OPENOCD_RTOS_LINUX_HEADER_H
 
diff --git a/src/target/openrisc/jsp_server.h b/src/target/openrisc/jsp_server.h
index e5cfaa8b4..a522fa8da 100644
--- a/src/target/openrisc/jsp_server.h
+++ b/src/target/openrisc/jsp_server.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 #ifndef OPENOCD_TARGET_OPENRISC_JSP_SERVER_H
 #define OPENOCD_TARGET_OPENRISC_JSP_SERVER_H
 

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/fm4.c              | 2 ++
 src/jtag/drivers/cmsis_dap.h     | 2 ++
 src/rtos/linux_header.h          | 2 ++
 src/target/openrisc/jsp_server.h | 2 ++
 4 files changed, 8 insertions(+)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-757-gdba88e023

From: OpenOCD-Gerrit <ope...@us...> - 2022-07-23 13:13:45

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  dba88e0238716f2fe0ff861d493cbace88a6bec3 (commit)
       via  96202cda1906be3b698614a6a7977cc5e6407cf6 (commit)
      from  5e96b012af91c4dc6eae680b67a594e9a22b3ead (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit dba88e0238716f2fe0ff861d493cbace88a6bec3
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jun 26 10:54:00 2022 +0200

    openocd: src: remove duplicated GPL license tag
    
    SPDX tag is replacing the FSF boilerplate.
    For files that have both, remove the FSF boilerplate and keep only
    the SPDX tag.
    
    Change-Id: I04c4764d13d4ca92453f30ed16aeae53cd4c3fc8
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7057
    Tested-by: jenkins

diff --git a/src/target/riscv/riscv_semihosting.c b/src/target/riscv/riscv_semihosting.c
index c337a740d..03de97c45 100644
--- a/src/target/riscv/riscv_semihosting.c
+++ b/src/target/riscv/riscv_semihosting.c
@@ -12,19 +12,6 @@
  *                                                                         *
  *   Copyright (C) 2016 by Square, Inc.                                    *
  *   Steven Stallion <sta...@sq...>                               *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 /**

commit 96202cda1906be3b698614a6a7977cc5e6407cf6
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 25 18:19:46 2022 +0200

    openocd: build: add SPDX tag
    
    Add the SPDX tag to makefiles, configuration scripts and tcl files
    present in the folders under src/
    
    Change-Id: I1e4552aafe46ef4893d510da9d732c5f181784a4
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7051
    Tested-by: jenkins

diff --git a/Makefile.am b/Makefile.am
index a18c572fb..89ca8380f 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # not a GNU package. You can remove this line, if
 # have all needed files, that a GNU package needs
 AUTOMAKE_OPTIONS = gnu 1.6
diff --git a/bootstrap b/bootstrap
index e81ba4d02..cf6167fff 100755
--- a/bootstrap
+++ b/bootstrap
@@ -1,4 +1,6 @@
 #!/bin/sh
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Run the autotools bootstrap sequence to create the configure script
 
 # Abort execution on error
diff --git a/configure.ac b/configure.ac
index 66b07b179..9959777d9 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 AC_PREREQ([2.69])
 AC_INIT([openocd], [0.11.0+dev],
   [OpenOCD Mailing List <ope...@li...>])
diff --git a/src/Makefile.am b/src/Makefile.am
index 432c31e14..6d79cd631 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libopenocd.la
 bin_PROGRAMS += %D%/openocd
 
diff --git a/src/flash/Makefile.am b/src/flash/Makefile.am
index 4c70702b5..c5eb2482b 100644
--- a/src/flash/Makefile.am
+++ b/src/flash/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libflash.la
 %C%_libflash_la_SOURCES = \
 	%D%/common.c %D%/common.h
diff --git a/src/flash/nand/Makefile.am b/src/flash/nand/Makefile.am
index abe90f8bb..6a1a9b193 100644
--- a/src/flash/nand/Makefile.am
+++ b/src/flash/nand/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libocdflashnand.la
 
 %C%_libocdflashnand_la_SOURCES = \
diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am
index a5ef42210..e3afc0ddf 100644
--- a/src/flash/nor/Makefile.am
+++ b/src/flash/nor/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libocdflashnor.la
 %C%_libocdflashnor_la_SOURCES = \
 	%D%/core.c \
diff --git a/src/flash/startup.tcl b/src/flash/startup.tcl
index 16cbe1950..654f201a4 100644
--- a/src/flash/startup.tcl
+++ b/src/flash/startup.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Defines basic Tcl procs for OpenOCD flash module
 
 #
diff --git a/src/helper/Makefile.am b/src/helper/Makefile.am
index c1aeebf00..7354f5422 100644
--- a/src/helper/Makefile.am
+++ b/src/helper/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libhelper.la
 
 %C%_libhelper_la_SOURCES = \
diff --git a/src/helper/startup.tcl b/src/helper/startup.tcl
index 6389262a3..5a0d479f5 100644
--- a/src/helper/startup.tcl
+++ b/src/helper/startup.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Defines basic Tcl procs that must exist for OpenOCD scripts to work.
 #
 # Embedded into OpenOCD executable
diff --git a/src/jtag/Makefile.am b/src/jtag/Makefile.am
index 23424f5a2..43c6f8b27 100644
--- a/src/jtag/Makefile.am
+++ b/src/jtag/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libjtag.la
 
 %C%_libjtag_la_LIBADD =
diff --git a/src/jtag/aice/Makefile.am b/src/jtag/aice/Makefile.am
index b6a7ba922..bc5dac1e2 100644
--- a/src/jtag/aice/Makefile.am
+++ b/src/jtag/aice/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libocdaice.la
 
 %C%_libocdaice_la_CPPFLAGS = -I$(top_srcdir)/src/jtag/drivers $(AM_CPPFLAGS) $(LIBUSB1_CFLAGS)
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index 1440eb5a6..6410f3754 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libocdjtagdrivers.la
 %C%_libocdjtagdrivers_la_LIBADD =
 
diff --git a/src/jtag/drivers/usb_blaster/Makefile.am b/src/jtag/drivers/usb_blaster/Makefile.am
index a6694c543..0fb8a07f1 100644
--- a/src/jtag/drivers/usb_blaster/Makefile.am
+++ b/src/jtag/drivers/usb_blaster/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libocdusbblaster.la
 %C%_libocdusbblaster_la_SOURCES = $(USB_BLASTER_SRC)
 %C%_libocdusbblaster_la_CPPFLAGS = -I$(top_srcdir)/src/jtag/drivers $(AM_CPPFLAGS) $(LIBUSB1_CFLAGS) $(LIBFTDI_CFLAGS)
diff --git a/src/jtag/hla/Makefile.am b/src/jtag/hla/Makefile.am
index 6bb2960eb..41117868a 100644
--- a/src/jtag/hla/Makefile.am
+++ b/src/jtag/hla/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libocdhla.la
 
 %C%_libocdhla_la_SOURCES = \
diff --git a/src/jtag/startup.tcl b/src/jtag/startup.tcl
index ee116269e..238342061 100644
--- a/src/jtag/startup.tcl
+++ b/src/jtag/startup.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Defines basic Tcl procs for OpenOCD JTAG module
 
 # Executed during "init". Can be overridden
diff --git a/src/pld/Makefile.am b/src/pld/Makefile.am
index 7f3a55423..14786afbf 100644
--- a/src/pld/Makefile.am
+++ b/src/pld/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libpld.la
 %C%_libpld_la_SOURCES = \
 	%D%/pld.c \
diff --git a/src/rtos/Makefile.am b/src/rtos/Makefile.am
index f09ac21a2..f00d7194e 100644
--- a/src/rtos/Makefile.am
+++ b/src/rtos/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/librtos.la
 %C%_librtos_la_SOURCES = \
 	%D%/rtos.c \
diff --git a/src/rtt/Makefile.am b/src/rtt/Makefile.am
index e3fcefdbf..99685547a 100644
--- a/src/rtt/Makefile.am
+++ b/src/rtt/Makefile.am
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/librtt.la
 %C%_librtt_la_SOURCES = %D%/rtt.c %D%/rtt.h %D%/tcl.c
diff --git a/src/server/Makefile.am b/src/server/Makefile.am
index e3699f181..13a591409 100644
--- a/src/server/Makefile.am
+++ b/src/server/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libserver.la
 %C%_libserver_la_SOURCES = \
 	%D%/server.c \
diff --git a/src/server/startup.tcl b/src/server/startup.tcl
index 447b57cc3..1d30b1dd3 100644
--- a/src/server/startup.tcl
+++ b/src/server/startup.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Defines basic Tcl procs for OpenOCD server modules
 
 # Handle GDB 'R' packet. Can be overridden by configuration script,
diff --git a/src/svf/Makefile.am b/src/svf/Makefile.am
index 5603d53b5..5fcb02c3f 100644
--- a/src/svf/Makefile.am
+++ b/src/svf/Makefile.am
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libsvf.la
 %C%_libsvf_la_SOURCES = %D%/svf.c %D%/svf.h
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 799c3dd07..46870922a 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 %C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
 	%D%/riscv/libriscv.la \
 	%D%/xtensa/libxtensa.la \
diff --git a/src/target/espressif/Makefile.am b/src/target/espressif/Makefile.am
index 2ea31d82c..df002b33b 100644
--- a/src/target/espressif/Makefile.am
+++ b/src/target/espressif/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libespressif.la
 %C%_libespressif_la_SOURCES = \
        %D%/esp_xtensa.c \
diff --git a/src/target/openrisc/Makefile.am b/src/target/openrisc/Makefile.am
index 5a2549a51..b9c0f83ea 100644
--- a/src/target/openrisc/Makefile.am
+++ b/src/target/openrisc/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libopenrisc.la
 %C%_libopenrisc_la_SOURCES = \
 	%D%/or1k.c \
diff --git a/src/target/riscv/Makefile.am b/src/target/riscv/Makefile.am
index 83f1a8ca3..4b6a74f0b 100644
--- a/src/target/riscv/Makefile.am
+++ b/src/target/riscv/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libriscv.la
 %C%_libriscv_la_SOURCES = \
        %D%/asm.h \
diff --git a/src/target/startup.tcl b/src/target/startup.tcl
index 0e46992b7..290e79d1e 100644
--- a/src/target/startup.tcl
+++ b/src/target/startup.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Defines basic Tcl procs for OpenOCD target module
 
 proc new_target_name { } {
diff --git a/src/target/xtensa/Makefile.am b/src/target/xtensa/Makefile.am
index f6cee99c2..a11e58530 100644
--- a/src/target/xtensa/Makefile.am
+++ b/src/target/xtensa/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libxtensa.la
 %C%_libxtensa_la_SOURCES = \
        %D%/xtensa.c \
diff --git a/src/transport/Makefile.am b/src/transport/Makefile.am
index 9076d9b68..cb4f48f66 100644
--- a/src/transport/Makefile.am
+++ b/src/transport/Makefile.am
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libtransport.la
 %C%_libtransport_la_SOURCES = \
 	%D%/transport.c \
diff --git a/src/xsvf/Makefile.am b/src/xsvf/Makefile.am
index 61e6fb920..08f1cc1d8 100644
--- a/src/xsvf/Makefile.am
+++ b/src/xsvf/Makefile.am
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 noinst_LTLIBRARIES += %D%/libxsvf.la
 %C%_libxsvf_la_SOURCES = %D%/xsvf.c %D%/xsvf.h

-----------------------------------------------------------------------

Summary of changes:
 Makefile.am                              |  2 ++
 bootstrap                                |  2 ++
 configure.ac                             |  2 ++
 src/Makefile.am                          |  2 ++
 src/flash/Makefile.am                    |  2 ++
 src/flash/nand/Makefile.am               |  2 ++
 src/flash/nor/Makefile.am                |  2 ++
 src/flash/startup.tcl                    |  2 ++
 src/helper/Makefile.am                   |  2 ++
 src/helper/startup.tcl                   |  2 ++
 src/jtag/Makefile.am                     |  2 ++
 src/jtag/aice/Makefile.am                |  2 ++
 src/jtag/drivers/Makefile.am             |  2 ++
 src/jtag/drivers/usb_blaster/Makefile.am |  2 ++
 src/jtag/hla/Makefile.am                 |  2 ++
 src/jtag/startup.tcl                     |  2 ++
 src/pld/Makefile.am                      |  2 ++
 src/rtos/Makefile.am                     |  2 ++
 src/rtt/Makefile.am                      |  2 ++
 src/server/Makefile.am                   |  2 ++
 src/server/startup.tcl                   |  2 ++
 src/svf/Makefile.am                      |  2 ++
 src/target/Makefile.am                   |  2 ++
 src/target/espressif/Makefile.am         |  2 ++
 src/target/openrisc/Makefile.am          |  2 ++
 src/target/riscv/Makefile.am             |  2 ++
 src/target/riscv/riscv_semihosting.c     | 13 -------------
 src/target/startup.tcl                   |  2 ++
 src/target/xtensa/Makefile.am            |  2 ++
 src/transport/Makefile.am                |  2 ++
 src/xsvf/Makefile.am                     |  2 ++
 31 files changed, 60 insertions(+), 13 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-748-ga70bab9e5

From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:55:09

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  a70bab9e5185c8853882748737ceebabde7c4781 (commit)
      from  573a39b36cf133bb7403b12337301a5616112f1a (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit a70bab9e5185c8853882748737ceebabde7c4781
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jun 19 22:10:47 2022 +0200

    helper: fix build with mingw gcc 12.1.0
    
    New mingw compiler correctly complains for using a freed memory
    area:
    
            src/helper/configuration.c: In function 'get_home_dir':
            src/helper/configuration.c:182:29: error: dangling pointer 'home'
                    to 'homepath' may be used [-Werror=dangling-pointer=]
            182 | home_path = alloc_printf("%s/%s", home, append_path);
                |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    
    In fact the variable 'homepath' is declared inside an 'if' branch
    and is not available outside.
    
    Move the declaration of 'homepath' to have it available in a wider
    context.
    
    Change-Id: I4a43a03c007c9f0d5c4cee962a9f7cc83ca49637
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reported-by: Dietmar May <die...@ou...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7038
    Tested-by: jenkins
    Reviewed-by: Dietmar May <die...@ou...>

diff --git a/src/helper/configuration.c b/src/helper/configuration.c
index 7e791d084..614892c8a 100644
--- a/src/helper/configuration.c
+++ b/src/helper/configuration.c
@@ -148,6 +148,10 @@ int parse_config_file(struct command_context *cmd_ctx)
 
 char *get_home_dir(const char *append_path)
 {
+#ifdef _WIN32
+	char homepath[MAX_PATH];
+#endif
+
 	char *home = getenv("HOME");
 
 	if (!home) {
@@ -156,8 +160,6 @@ char *get_home_dir(const char *append_path)
 		home = getenv("USERPROFILE");
 
 		if (!home) {
-
-			char homepath[MAX_PATH];
 			char *drive = getenv("HOMEDRIVE");
 			char *path = getenv("HOMEPATH");
 			if (drive && path) {

-----------------------------------------------------------------------

Summary of changes:
 src/helper/configuration.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-747-g573a39b36

From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:54:27

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  573a39b36cf133bb7403b12337301a5616112f1a (commit)
       via  3bccc77999175494ceb534c172475e509ff99189 (commit)
      from  4157732bd84c4e9e4b55357e1dc9a96078a35ee1 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 573a39b36cf133bb7403b12337301a5616112f1a
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jun 12 23:51:51 2022 +0200

    tcl: add SPDX tag
    
    For historical reasons, no license information was added to the
    tcl files. This makes trivial adding the SPDX tag through script:
            fgrep -rL SPDX tcl | while read a;do \
            sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
            }' $a;done
    
    With no specific license information from the author, let's extend
    the OpenOCD project license GPL-2.0-or-later to the files.
    
    Change-Id: Ief3da306a6e1978de7dfb8f552f9ff23151f9944
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7030
    Tested-by: jenkins

diff --git a/tcl/bitsbytes.tcl b/tcl/bitsbytes.tcl
index 756c725df..03d758e7c 100644
--- a/tcl/bitsbytes.tcl
+++ b/tcl/bitsbytes.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #----------------------------------------
 # Purpose - Create some $BIT variables
 #           Create $K and $M variables
diff --git a/tcl/chip/atmel/at91/aic.tcl b/tcl/chip/atmel/at91/aic.tcl
index 8b8a48f3b..6657b601a 100644
--- a/tcl/chip/atmel/at91/aic.tcl
+++ b/tcl/chip/atmel/at91/aic.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 set AIC_SMR      	[expr {$AT91C_BASE_AIC + 0x00000000} ]
 global AIC_SMR
 set AIC_SVR      	[expr {$AT91C_BASE_AIC + 0x00000080} ]
diff --git a/tcl/chip/atmel/at91/at91_pio.cfg b/tcl/chip/atmel/at91/at91_pio.cfg
index 2373c19fe..10a1d48c6 100644
--- a/tcl/chip/atmel/at91/at91_pio.cfg
+++ b/tcl/chip/atmel/at91/at91_pio.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 set PIO_PER	0x00	;# Enable Register
 set PIO_PDR	0x04	;# Disable Register
 set PIO_PSR	0x08	;# Status Register
diff --git a/tcl/chip/atmel/at91/at91_pmc.cfg b/tcl/chip/atmel/at91/at91_pmc.cfg
index dd554ce81..a75cecd6a 100644
--- a/tcl/chip/atmel/at91/at91_pmc.cfg
+++ b/tcl/chip/atmel/at91/at91_pmc.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 set	AT91_PMC_SCER		[expr {$AT91_PMC + 0x00}]	;# System Clock Enable Register
 set	AT91_PMC_SCDR		[expr {$AT91_PMC + 0x04}]	;# System Clock Disable Register
 
diff --git a/tcl/chip/atmel/at91/at91_rstc.cfg b/tcl/chip/atmel/at91/at91_rstc.cfg
index 6673fe645..fd174380a 100644
--- a/tcl/chip/atmel/at91/at91_rstc.cfg
+++ b/tcl/chip/atmel/at91/at91_rstc.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 set AT91_RSTC_CR		[expr {$AT91_RSTC + 0x00}]	;# Reset Controller Control Register
 set		AT91_RSTC_PROCRST	[expr {1 << 0}]		;# Processor Reset
 set		AT91_RSTC_PERRST	[expr {1 << 2}]		;# Peripheral Reset
diff --git a/tcl/chip/atmel/at91/at91_wdt.cfg b/tcl/chip/atmel/at91/at91_wdt.cfg
index 9b4e817e2..8bba62e16 100644
--- a/tcl/chip/atmel/at91/at91_wdt.cfg
+++ b/tcl/chip/atmel/at91/at91_wdt.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 set AT91_WDT_CR		[expr {$AT91_WDT + 0x00}]	;# Watchdog Control Register
 set		AT91_WDT_WDRSTT		[expr {1    << 0}]	;# Restart
 set		AT91_WDT_KEY		[expr {0xa5 << 24}]	;# KEY Password
diff --git a/tcl/chip/atmel/at91/at91sam7x128.tcl b/tcl/chip/atmel/at91/at91sam7x128.tcl
index ce33cf009..8f468275b 100644
--- a/tcl/chip/atmel/at91/at91sam7x128.tcl
+++ b/tcl/chip/atmel/at91/at91sam7x128.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 source [find bitsbytes.tcl]
 source [find cpu/arm/arm7tdmi.tcl]
 source [find memory.tcl]
diff --git a/tcl/chip/atmel/at91/at91sam7x256.tcl b/tcl/chip/atmel/at91/at91sam7x256.tcl
index dc4918ab1..49d5244cc 100644
--- a/tcl/chip/atmel/at91/at91sam7x256.tcl
+++ b/tcl/chip/atmel/at91/at91sam7x256.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 source [find bitsbytes.tcl]
 source [find cpu/arm/arm7tdmi.tcl]
 source [find memory.tcl]
diff --git a/tcl/chip/atmel/at91/at91sam9261.cfg b/tcl/chip/atmel/at91/at91sam9261.cfg
index 61b0c0bf3..51e7101b5 100644
--- a/tcl/chip/atmel/at91/at91sam9261.cfg
+++ b/tcl/chip/atmel/at91/at91sam9261.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Peripheral identifiers/interrupts.
 #
diff --git a/tcl/chip/atmel/at91/at91sam9261_matrix.cfg b/tcl/chip/atmel/at91/at91sam9261_matrix.cfg
index 238e65841..c3656bd41 100644
--- a/tcl/chip/atmel/at91/at91sam9261_matrix.cfg
+++ b/tcl/chip/atmel/at91/at91sam9261_matrix.cfg
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
 
 set AT91_MATRIX_MCFG	[expr {$AT91_MATRIX + 0x00}]	;# Master Configuration Register #
 set		AT91_MATRIX_RCB0	[expr {1 << 0}]		;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
diff --git a/tcl/chip/atmel/at91/at91sam9263.cfg b/tcl/chip/atmel/at91/at91sam9263.cfg
index 8e22eb2db..600c54861 100644
--- a/tcl/chip/atmel/at91/at91sam9263.cfg
+++ b/tcl/chip/atmel/at91/at91sam9263.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Peripheral identifiers/interrupts.
 #
diff --git a/tcl/chip/atmel/at91/at91sam9263_matrix.cfg b/tcl/chip/atmel/at91/at91sam9263_matrix.cfg
index b4a07d32d..20a31079a 100644
--- a/tcl/chip/atmel/at91/at91sam9263_matrix.cfg
+++ b/tcl/chip/atmel/at91/at91sam9263_matrix.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 set AT91_MATRIX_MCFG0	[expr {$AT91_MATRIX + 0x00}]	;# Master Configuration Register 0
 set AT91_MATRIX_MCFG1	[expr {$AT91_MATRIX + 0x04}]	;# Master Configuration Register 1
 set AT91_MATRIX_MCFG2	[expr {$AT91_MATRIX + 0x08}]	;# Master Configuration Register 2
diff --git a/tcl/chip/atmel/at91/at91sam9_init.cfg b/tcl/chip/atmel/at91/at91sam9_init.cfg
index 27611eb5e..a64d6eaef 100644
--- a/tcl/chip/atmel/at91/at91sam9_init.cfg
+++ b/tcl/chip/atmel/at91/at91sam9_init.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 uplevel #0 [list source [find chip/atmel/at91/at91sam9_sdramc.cfg]]
 uplevel #0 [list source [find chip/atmel/at91/at91_pmc.cfg]]
 uplevel #0 [list source [find chip/atmel/at91/at91_pio.cfg]]
diff --git a/tcl/chip/atmel/at91/at91sam9_sdramc.cfg b/tcl/chip/atmel/at91/at91sam9_sdramc.cfg
index 7b09369de..658b6c361 100644
--- a/tcl/chip/atmel/at91/at91sam9_sdramc.cfg
+++ b/tcl/chip/atmel/at91/at91sam9_sdramc.cfg
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
 
 # SDRAM Controller (SDRAMC) registers
 set AT91_SDRAMC_MR		[expr {$AT91_SDRAMC + 0x00}]	;# SDRAM Controller Mode Register
diff --git a/tcl/chip/atmel/at91/at91sam9_smc.cfg b/tcl/chip/atmel/at91/at91sam9_smc.cfg
index 3a76d147b..c096c4a2c 100644
--- a/tcl/chip/atmel/at91/at91sam9_smc.cfg
+++ b/tcl/chip/atmel/at91/at91sam9_smc.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 set		AT91_SMC_READMODE	[expr {1 <<  0}]		;# Read Mode
 set		AT91_SMC_WRITEMODE	[expr {1 <<  1}]		;# Write Mode
 set		AT91_SMC_EXNWMODE	[expr {3 <<  4}]		;# NWAIT Mode
diff --git a/tcl/chip/atmel/at91/hardware.cfg b/tcl/chip/atmel/at91/hardware.cfg
index a25eab975..069d4b78c 100644
--- a/tcl/chip/atmel/at91/hardware.cfg
+++ b/tcl/chip/atmel/at91/hardware.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # External Memory Map
 set AT91_CHIPSELECT_0	0x10000000
 set AT91_CHIPSELECT_1	0x20000000
diff --git a/tcl/chip/atmel/at91/pmc.tcl b/tcl/chip/atmel/at91/pmc.tcl
index 7cb1d093e..0f997cad5 100644
--- a/tcl/chip/atmel/at91/pmc.tcl
+++ b/tcl/chip/atmel/at91/pmc.tcl
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
 
 if [info exists AT91C_MAINOSC_FREQ] {
     # user set this... let it be.
diff --git a/tcl/chip/atmel/at91/rtt.tcl b/tcl/chip/atmel/at91/rtt.tcl
index d49ce7114..1ef83733b 100644
--- a/tcl/chip/atmel/at91/rtt.tcl
+++ b/tcl/chip/atmel/at91/rtt.tcl
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
 
 set RTTC_RTMR [expr {$AT91C_BASE_RTTC + 0x00}]
 set RTTC_RTAR [expr {$AT91C_BASE_RTTC + 0x04}]
diff --git a/tcl/chip/atmel/at91/sam9_smc.cfg b/tcl/chip/atmel/at91/sam9_smc.cfg
index 0628d4d18..87880c769 100644
--- a/tcl/chip/atmel/at91/sam9_smc.cfg
+++ b/tcl/chip/atmel/at91/sam9_smc.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Setup register
 #
 # ncs_read_setup
diff --git a/tcl/chip/atmel/at91/usarts.tcl b/tcl/chip/atmel/at91/usarts.tcl
index 253b7fbfc..62a651bbd 100644
--- a/tcl/chip/atmel/at91/usarts.tcl
+++ b/tcl/chip/atmel/at91/usarts.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # the DBGU and USARTs are 'almost' indentical'
 set DBGU_CR         [expr {$AT91C_BASE_DBGU + 0x00000000}]
 set DBGU_MR         [expr {$AT91C_BASE_DBGU + 0x00000004}]
diff --git a/tcl/chip/st/spear/quirk_no_srst.tcl b/tcl/chip/st/spear/quirk_no_srst.tcl
index 551df061d..e8640f46b 100644
--- a/tcl/chip/st/spear/quirk_no_srst.tcl
+++ b/tcl/chip/st/spear/quirk_no_srst.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Quirks to bypass missing SRST on JTAG connector
 # EVALSPEAr310 Rev. 2.0
 # http://www.st.com/spear
diff --git a/tcl/chip/st/spear/spear3xx.tcl b/tcl/chip/st/spear/spear3xx.tcl
index 86f2a1d24..474ebe316 100644
--- a/tcl/chip/st/spear/spear3xx.tcl
+++ b/tcl/chip/st/spear/spear3xx.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Generic init scripts for all ST SPEAr3xx family
 # http://www.st.com/spear
 #
diff --git a/tcl/chip/st/spear/spear3xx_ddr.tcl b/tcl/chip/st/spear/spear3xx_ddr.tcl
index 22fe06eaf..59925672d 100644
--- a/tcl/chip/st/spear/spear3xx_ddr.tcl
+++ b/tcl/chip/st/spear/spear3xx_ddr.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Init scripts to configure DDR controller of SPEAr3xx
 # http://www.st.com/spear
 # Original values taken from XLoader source code
diff --git a/tcl/chip/st/stm32/stm32.tcl b/tcl/chip/st/stm32/stm32.tcl
index 94b1935dd..3826a57af 100644
--- a/tcl/chip/st/stm32/stm32.tcl
+++ b/tcl/chip/st/stm32/stm32.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 source [find bitsbytes.tcl]
 source [find cpu/arm/cortex_m3.tcl]
 source [find memory.tcl]
diff --git a/tcl/chip/st/stm32/stm32_rcc.tcl b/tcl/chip/st/stm32/stm32_rcc.tcl
index fa652a2e6..afa4cbfd6 100644
--- a/tcl/chip/st/stm32/stm32_rcc.tcl
+++ b/tcl/chip/st/stm32/stm32_rcc.tcl
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
 
 set RCC_CR            [expr {$RCC_BASE + 0x00}]
 set RCC_CFGR          [expr {$RCC_BASE + 0x04}]
diff --git a/tcl/chip/st/stm32/stm32_regs.tcl b/tcl/chip/st/stm32/stm32_regs.tcl
index 6ae2f63f6..07ff1aa29 100644
--- a/tcl/chip/st/stm32/stm32_regs.tcl
+++ b/tcl/chip/st/stm32/stm32_regs.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # /* Peripheral and SRAM base address in the alias region */
 set PERIPH_BB_BASE        0x42000000
 set SRAM_BB_BASE          0x22000000
diff --git a/tcl/chip/ti/lm3s/lm3s.tcl b/tcl/chip/ti/lm3s/lm3s.tcl
index 42da8c668..324aad065 100644
--- a/tcl/chip/ti/lm3s/lm3s.tcl
+++ b/tcl/chip/ti/lm3s/lm3s.tcl
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 source [find chip/ti/lm3s/lm3s_regs.tcl]
diff --git a/tcl/chip/ti/lm3s/lm3s_regs.tcl b/tcl/chip/ti/lm3s/lm3s_regs.tcl
index cb20812db..1e86e29e8 100644
--- a/tcl/chip/ti/lm3s/lm3s_regs.tcl
+++ b/tcl/chip/ti/lm3s/lm3s_regs.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #*****************************************************************************
 #
 # The following are defines for the System Control register addresses.
diff --git a/tcl/cpld/altera-5m570z-cpld.cfg b/tcl/cpld/altera-5m570z-cpld.cfg
index 22a422c48..5dbd0deee 100644
--- a/tcl/cpld/altera-5m570z-cpld.cfg
+++ b/tcl/cpld/altera-5m570z-cpld.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Altera MAXV 5M24OZ/5M570Z CPLD
 # see MAX V Device Handbook
 # Table 6-3: 32-Bit MAX V Device IDCODE
diff --git a/tcl/cpld/altera-epm240.cfg b/tcl/cpld/altera-epm240.cfg
index ece02bbef..39c409bc3 100644
--- a/tcl/cpld/altera-epm240.cfg
+++ b/tcl/cpld/altera-epm240.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Altera MAXII EPM240T100C CPLD
 
 if { [info exists CHIPNAME] } {
diff --git a/tcl/cpld/jtagspi.cfg b/tcl/cpld/jtagspi.cfg
index e720c3959..7071e5e34 100644
--- a/tcl/cpld/jtagspi.cfg
+++ b/tcl/cpld/jtagspi.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 set _USER1 0x02
 
 if { [info exists JTAGSPI_IR] } {
diff --git a/tcl/cpld/lattice-lc4032ze.cfg b/tcl/cpld/lattice-lc4032ze.cfg
index d4a85eb79..479180f28 100644
--- a/tcl/cpld/lattice-lc4032ze.cfg
+++ b/tcl/cpld/lattice-lc4032ze.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Lattice ispMACH 4000ZE family, device LC4032ZE
 # just configure a tap
 jtag newtap LC4032ZE tap -irlen 8 -expected-id  0x01806043
diff --git a/tcl/cpld/xilinx-xc6s.cfg b/tcl/cpld/xilinx-xc6s.cfg
index 9ce7ad491..82b87fb41 100644
--- a/tcl/cpld/xilinx-xc6s.cfg
+++ b/tcl/cpld/xilinx-xc6s.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # xilinx spartan6
 # http://www.xilinx.com/support/documentation/user_guides/ug380.pdf
 
diff --git a/tcl/cpld/xilinx-xc7.cfg b/tcl/cpld/xilinx-xc7.cfg
index 4c0502c5d..22e0aea7f 100644
--- a/tcl/cpld/xilinx-xc7.cfg
+++ b/tcl/cpld/xilinx-xc7.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # xilinx series 7 (artix, kintex, virtex)
 # http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
 
diff --git a/tcl/cpld/xilinx-xcf-p.cfg b/tcl/cpld/xilinx-xcf-p.cfg
index 8e0a26c6f..7b6d384a7 100644
--- a/tcl/cpld/xilinx-xcf-p.cfg
+++ b/tcl/cpld/xilinx-xcf-p.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
 } else {
diff --git a/tcl/cpld/xilinx-xcf-s.cfg b/tcl/cpld/xilinx-xcf-s.cfg
index a3c79a385..417ecff69 100644
--- a/tcl/cpld/xilinx-xcf-s.cfg
+++ b/tcl/cpld/xilinx-xcf-s.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
 } else {
diff --git a/tcl/cpld/xilinx-xcr3256.cfg b/tcl/cpld/xilinx-xcr3256.cfg
index e5611f1ec..4668e5478 100644
--- a/tcl/cpld/xilinx-xcr3256.cfg
+++ b/tcl/cpld/xilinx-xcr3256.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #xilinx coolrunner xcr3256
 #simple device - just configure a tap
 jtag newtap xcr tap -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id  0x0494c093
diff --git a/tcl/cpld/xilinx-xcu.cfg b/tcl/cpld/xilinx-xcu.cfg
index 327059711..57a59f59a 100644
--- a/tcl/cpld/xilinx-xcu.cfg
+++ b/tcl/cpld/xilinx-xcu.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Xilinx Ultrascale (Kintex, Virtex, Zynq)
 # https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
 
diff --git a/tcl/cpu/arm/arm7tdmi.tcl b/tcl/cpu/arm/arm7tdmi.tcl
index a1d4a1f46..e407a2396 100644
--- a/tcl/cpu/arm/arm7tdmi.tcl
+++ b/tcl/cpu/arm/arm7tdmi.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 set CPU_TYPE   arm
 set CPU_NAME   arm7tdmi
 set CPU_ARCH   armv4t
diff --git a/tcl/cpu/arm/arm920.tcl b/tcl/cpu/arm/arm920.tcl
index c01f602f2..1c5a8ad8a 100644
--- a/tcl/cpu/arm/arm920.tcl
+++ b/tcl/cpu/arm/arm920.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 set CPU_TYPE   arm
 set CPU_NAME   arm920
 set CPU_ARCH   armv4t
diff --git a/tcl/cpu/arm/arm946.tcl b/tcl/cpu/arm/arm946.tcl
index a6110a53f..602d4d700 100644
--- a/tcl/cpu/arm/arm946.tcl
+++ b/tcl/cpu/arm/arm946.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 set CPU_TYPE   arm
 set CPU_NAME   arm946
 set CPU_ARCH   armv5te
diff --git a/tcl/cpu/arm/arm966.tcl b/tcl/cpu/arm/arm966.tcl
index 1fffbc092..0e64312e0 100644
--- a/tcl/cpu/arm/arm966.tcl
+++ b/tcl/cpu/arm/arm966.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 set CPU_TYPE   arm
 set CPU_NAME   arm966
 set CPU_ARCH   armv5te
diff --git a/tcl/cpu/arm/cortex_m3.tcl b/tcl/cpu/arm/cortex_m3.tcl
index c9950261f..0791664bb 100644
--- a/tcl/cpu/arm/cortex_m3.tcl
+++ b/tcl/cpu/arm/cortex_m3.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 set CPU_TYPE   arm
 set CPU_NAME   cortex_m3
 set CPU_ARCH   armv7
diff --git a/tcl/fpga/altera-10m50.cfg b/tcl/fpga/altera-10m50.cfg
index d5af71059..1937cb4b6 100644
--- a/tcl/fpga/altera-10m50.cfg
+++ b/tcl/fpga/altera-10m50.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # see MAX 10 FPGA Device Architecture
 # Table 3-1: IDCODE Information for MAX 10 Devices
 # Intel MAX 10M02 0x31810dd
diff --git a/tcl/fpga/altera-ep3c10.cfg b/tcl/fpga/altera-ep3c10.cfg
index 6e8962a53..7c231f942 100644
--- a/tcl/fpga/altera-ep3c10.cfg
+++ b/tcl/fpga/altera-ep3c10.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Altera Cyclone III EP3C10
 # see Cyclone III Device Handbook, Volume 1;
 # Table 14â5. 32-Bit Cyclone III Device IDCODE
diff --git a/tcl/fpga/xilinx-dna.cfg b/tcl/fpga/xilinx-dna.cfg
index a8056735b..56f8c1411 100644
--- a/tcl/fpga/xilinx-dna.cfg
+++ b/tcl/fpga/xilinx-dna.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 proc xilinx_dna_addr {chip} {
 	array set addrs {
 		Spartan6 0x30
diff --git a/tcl/fpga/xilinx-xadc.cfg b/tcl/fpga/xilinx-xadc.cfg
index 250879ec9..fdaf3a961 100644
--- a/tcl/fpga/xilinx-xadc.cfg
+++ b/tcl/fpga/xilinx-xadc.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Xilinx XADC support for 7 Series FPGAs
 #
 # The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die
diff --git a/tcl/mem_helper.tcl b/tcl/mem_helper.tcl
index 1c860119a..0229d54b7 100644
--- a/tcl/mem_helper.tcl
+++ b/tcl/mem_helper.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Helper for common memory read/modify/write procedures
 
 # mrw: "memory read word", returns value of $reg
diff --git a/tcl/memory.tcl b/tcl/memory.tcl
index ac273451d..b11174995 100644
--- a/tcl/memory.tcl
+++ b/tcl/memory.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # MEMORY
 #
 # All Memory regions have two components.
diff --git a/tcl/mmr_helpers.tcl b/tcl/mmr_helpers.tcl
index 61c58e7ca..5c37fcfdc 100644
--- a/tcl/mmr_helpers.tcl
+++ b/tcl/mmr_helpers.tcl
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
 
 proc proc_exists { NAME } {
     set n [info commands $NAME]
diff --git a/tcl/test/selftest.cfg b/tcl/test/selftest.cfg
index 0331b482f..10efb0c6d 100644
--- a/tcl/test/selftest.cfg
+++ b/tcl/test/selftest.cfg
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
 
 add_help_text selftest "run selftest using working ram <tmpfile> <address> <size>"
 
diff --git a/tcl/test/syntax1.cfg b/tcl/test/syntax1.cfg
index 2e6618895..7735ee98c 100644
--- a/tcl/test/syntax1.cfg
+++ b/tcl/test/syntax1.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 adapter srst delay 200
 jtag_ntrst_delay 200
 
diff --git a/tcl/tools/firmware-recovery.tcl b/tcl/tools/firmware-recovery.tcl
index 9d7e0fce8..6a328cd2e 100644
--- a/tcl/tools/firmware-recovery.tcl
+++ b/tcl/tools/firmware-recovery.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 echo "\n\nFirmware recovery helpers"
 echo "Use -c firmware_help to get help\n"
 
diff --git a/tcl/tools/memtest.tcl b/tcl/tools/memtest.tcl
index c7fa591f3..f70f950d7 100644
--- a/tcl/tools/memtest.tcl
+++ b/tcl/tools/memtest.tcl
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Algorithms by Michael Barr, released into public domain
 # Ported to OpenOCD by Shane Volpe, additional fixes by Paul Fertser
 

commit 3bccc77999175494ceb534c172475e509ff99189
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jun 12 23:50:59 2022 +0200

    tcl/interface: add SPDX tag
    
    For historical reasons, no license information was added to the
    tcl files. This makes trivial adding the SPDX tag through script:
            fgrep -rL SPDX tcl/interface | while read a;do \
            sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
            }' $a;done
    
    With no specific license information from the author, let's extend
    the OpenOCD project license GPL-2.0-or-later to the files.
    
    Change-Id: I7bd6a628e9e153fc477cddf9b97087a39ec48aa7
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7029
    Tested-by: jenkins

diff --git a/tcl/interface/altera-usb-blaster.cfg b/tcl/interface/altera-usb-blaster.cfg
index cb4ca9a78..cc6057b51 100644
--- a/tcl/interface/altera-usb-blaster.cfg
+++ b/tcl/interface/altera-usb-blaster.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Altera USB-Blaster
 #
diff --git a/tcl/interface/altera-usb-blaster2.cfg b/tcl/interface/altera-usb-blaster2.cfg
index 05b0519b8..93f9809b0 100644
--- a/tcl/interface/altera-usb-blaster2.cfg
+++ b/tcl/interface/altera-usb-blaster2.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Altera USB-Blaster II
 #
diff --git a/tcl/interface/arm-jtag-ew.cfg b/tcl/interface/arm-jtag-ew.cfg
index 797bb7121..a064a428e 100644
--- a/tcl/interface/arm-jtag-ew.cfg
+++ b/tcl/interface/arm-jtag-ew.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Olimex ARM-JTAG-EW
 #
diff --git a/tcl/interface/at91rm9200.cfg b/tcl/interface/at91rm9200.cfg
index b66e060d1..caef9975d 100644
--- a/tcl/interface/at91rm9200.cfg
+++ b/tcl/interface/at91rm9200.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Various Atmel AT91RM9200 boards
 #
diff --git a/tcl/interface/buspirate.cfg b/tcl/interface/buspirate.cfg
index 20761d152..8f613a764 100644
--- a/tcl/interface/buspirate.cfg
+++ b/tcl/interface/buspirate.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Buspirate with OpenOCD support
 #
diff --git a/tcl/interface/calao-usb-a9260.cfg b/tcl/interface/calao-usb-a9260.cfg
index 01b426b89..ff652ef8f 100644
--- a/tcl/interface/calao-usb-a9260.cfg
+++ b/tcl/interface/calao-usb-a9260.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # CALAO Systems USB-A9260 common -C01 -C02 setup
 #
diff --git a/tcl/interface/chameleon.cfg b/tcl/interface/chameleon.cfg
index 97bf98d27..b73d129f0 100644
--- a/tcl/interface/chameleon.cfg
+++ b/tcl/interface/chameleon.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Amontec Chameleon POD
 #
diff --git a/tcl/interface/cmsis-dap.cfg b/tcl/interface/cmsis-dap.cfg
index 1bc91a527..15efe8060 100644
--- a/tcl/interface/cmsis-dap.cfg
+++ b/tcl/interface/cmsis-dap.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # ARM CMSIS-DAP compliant adapter
 #
diff --git a/tcl/interface/dummy.cfg b/tcl/interface/dummy.cfg
index 154c872cf..34e6558cc 100644
--- a/tcl/interface/dummy.cfg
+++ b/tcl/interface/dummy.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Dummy interface (for testing purposes)
 #
diff --git a/tcl/interface/estick.cfg b/tcl/interface/estick.cfg
index 75e6ea8e5..1daaf7c2e 100644
--- a/tcl/interface/estick.cfg
+++ b/tcl/interface/estick.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # eStick
 #
diff --git a/tcl/interface/flashlink.cfg b/tcl/interface/flashlink.cfg
index b7ec0bb24..d552c50a6 100644
--- a/tcl/interface/flashlink.cfg
+++ b/tcl/interface/flashlink.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # ST FlashLINK JTAG parallel cable
 #
diff --git a/tcl/interface/ft232r.cfg b/tcl/interface/ft232r.cfg
index 2c705c335..94eed0235 100644
--- a/tcl/interface/ft232r.cfg
+++ b/tcl/interface/ft232r.cfg
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 adapter driver ft232r
 adapter speed 1000
diff --git a/tcl/interface/ftdi/100ask-openjtag.cfg b/tcl/interface/ftdi/100ask-openjtag.cfg
index a12df97af..5ab9252c6 100644
--- a/tcl/interface/ftdi/100ask-openjtag.cfg
+++ b/tcl/interface/ftdi/100ask-openjtag.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # www.100ask.org OpenJTAG
 #
diff --git a/tcl/interface/ftdi/axm0432.cfg b/tcl/interface/ftdi/axm0432.cfg
index 84b77a69a..50083996c 100644
--- a/tcl/interface/ftdi/axm0432.cfg
+++ b/tcl/interface/ftdi/axm0432.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Axiom axm0432
 #
diff --git a/tcl/interface/ftdi/c232hm.cfg b/tcl/interface/ftdi/c232hm.cfg
index 25fcae1b0..23c8f3af2 100644
--- a/tcl/interface/ftdi/c232hm.cfg
+++ b/tcl/interface/ftdi/c232hm.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # FTDI USB Hi-Speed to MPSSE Cable
 #
 # http://www.ftdichip.com/Products/Cables/USBMPSSE.htm
diff --git a/tcl/interface/ftdi/calao-usb-a9260-c01.cfg b/tcl/interface/ftdi/calao-usb-a9260-c01.cfg
index 41e597391..c84e77874 100644
--- a/tcl/interface/ftdi/calao-usb-a9260-c01.cfg
+++ b/tcl/interface/ftdi/calao-usb-a9260-c01.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # CALAO Systems USB-A9260-C01
 #
diff --git a/tcl/interface/ftdi/calao-usb-a9260-c02.cfg b/tcl/interface/ftdi/calao-usb-a9260-c02.cfg
index 001aef59c..9d79b2600 100644
--- a/tcl/interface/ftdi/calao-usb-a9260-c02.cfg
+++ b/tcl/interface/ftdi/calao-usb-a9260-c02.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # CALAO Systems USB-A9260-C02
 #
diff --git a/tcl/interface/ftdi/cortino.cfg b/tcl/interface/ftdi/cortino.cfg
index c0eae3105..8bc8d6e4c 100644
--- a/tcl/interface/ftdi/cortino.cfg
+++ b/tcl/interface/ftdi/cortino.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Hitex Cortino
 #
diff --git a/tcl/interface/ftdi/digilent-hs1.cfg b/tcl/interface/ftdi/digilent-hs1.cfg
index 55391b9d3..6a632ed26 100644
--- a/tcl/interface/ftdi/digilent-hs1.cfg
+++ b/tcl/interface/ftdi/digilent-hs1.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # this supports JTAG-HS1 and JTAG-SMT1
 # (the later being the OEM on-board version)
 
diff --git a/tcl/interface/ftdi/digilent-hs2.cfg b/tcl/interface/ftdi/digilent-hs2.cfg
index 269eca0f3..e9fe94eb6 100644
--- a/tcl/interface/ftdi/digilent-hs2.cfg
+++ b/tcl/interface/ftdi/digilent-hs2.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # this supports JTAG-HS2 (and apparently Nexys4 as well)
 
 adapter driver ftdi
diff --git a/tcl/interface/ftdi/digilent_jtag_hs3.cfg b/tcl/interface/ftdi/digilent_jtag_hs3.cfg
index ca2807f80..78a233feb 100644
--- a/tcl/interface/ftdi/digilent_jtag_hs3.cfg
+++ b/tcl/interface/ftdi/digilent_jtag_hs3.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Digilent JTAG-HS3
 #
diff --git a/tcl/interface/ftdi/digilent_jtag_smt2.cfg b/tcl/interface/ftdi/digilent_jtag_smt2.cfg
index f4ba27bef..ac623a796 100644
--- a/tcl/interface/ftdi/digilent_jtag_smt2.cfg
+++ b/tcl/interface/ftdi/digilent_jtag_smt2.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Digilent JTAG-SMT2
 #
diff --git a/tcl/interface/ftdi/digilent_jtag_smt2_nc.cfg b/tcl/interface/ftdi/digilent_jtag_smt2_nc.cfg
index a143cd772..38236bc10 100644
--- a/tcl/interface/ftdi/digilent_jtag_smt2_nc.cfg
+++ b/tcl/interface/ftdi/digilent_jtag_smt2_nc.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Digilent JTAG-SMT2-NC
 #
diff --git a/tcl/interface/ftdi/dlp-usb1232h.cfg b/tcl/interface/ftdi/dlp-usb1232h.cfg
index e9651dd99..67fee6b0f 100644
--- a/tcl/interface/ftdi/dlp-usb1232h.cfg
+++ b/tcl/interface/ftdi/dlp-usb1232h.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # DLP Design DLP-USB1232H USB-to-UART/FIFO interface module
 #
diff --git a/tcl/interface/ftdi/dp_busblaster.cfg b/tcl/interface/ftdi/dp_busblaster.cfg
index 420f788d2..373e122c4 100644
--- a/tcl/interface/ftdi/dp_busblaster.cfg
+++ b/tcl/interface/ftdi/dp_busblaster.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Dangerous Prototypes - Bus Blaster
 #
diff --git a/tcl/interface/ftdi/dp_busblaster_kt-link.cfg b/tcl/interface/ftdi/dp_busblaster_kt-link.cfg
index 4924d2619..222ca3810 100644
--- a/tcl/interface/ftdi/dp_busblaster_kt-link.cfg
+++ b/tcl/interface/ftdi/dp_busblaster_kt-link.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Dangerous Prototypes - Bus Blaster (with KT-Link buffer)
 #
diff --git a/tcl/interface/ftdi/flossjtag-noeeprom.cfg b/tcl/interface/ftdi/flossjtag-noeeprom.cfg
index 7083e6388..1008e1ae6 100644
--- a/tcl/interface/ftdi/flossjtag-noeeprom.cfg
+++ b/tcl/interface/ftdi/flossjtag-noeeprom.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # FlossJTAG
 #
diff --git a/tcl/interface/ftdi/flossjtag.cfg b/tcl/interface/ftdi/flossjtag.cfg
index c1506a2e9..90ba63a4c 100644
--- a/tcl/interface/ftdi/flossjtag.cfg
+++ b/tcl/interface/ftdi/flossjtag.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # FlossJTAG
 #
diff --git a/tcl/interface/ftdi/flyswatter.cfg b/tcl/interface/ftdi/flyswatter.cfg
index bfa015b2c..8bce00dbb 100644
--- a/tcl/interface/ftdi/flyswatter.cfg
+++ b/tcl/interface/ftdi/flyswatter.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # TinCanTools Flyswatter
 #
diff --git a/tcl/interface/ftdi/flyswatter2.cfg b/tcl/interface/ftdi/flyswatter2.cfg
index 0b4a8ef9f..ebc00fe60 100644
--- a/tcl/interface/ftdi/flyswatter2.cfg
+++ b/tcl/interface/ftdi/flyswatter2.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # TinCanTools Flyswatter2
 #
diff --git a/tcl/interface/ftdi/ft232h-module-swd.cfg b/tcl/interface/ftdi/ft232h-module-swd.cfg
index 7fa428359..d09ccf16d 100644
--- a/tcl/interface/ftdi/ft232h-module-swd.cfg
+++ b/tcl/interface/ftdi/ft232h-module-swd.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # ADAFRUIT FTDI FT232H as a SWD direct connect interface
 # Any FT232H based board may work
diff --git a/tcl/interface/ftdi/gw16042.cfg b/tcl/interface/ftdi/gw16042.cfg
index ef3182938..326a88fa0 100644
--- a/tcl/interface/ftdi/gw16042.cfg
+++ b/tcl/interface/ftdi/gw16042.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Gateworks GW16042 JTAG Dongle
 #
diff --git a/tcl/interface/ftdi/hilscher_nxhx10_etm.cfg b/tcl/interface/ftdi/hilscher_nxhx10_etm.cfg
index d55f636de..d5d24e5fc 100644
--- a/tcl/interface/ftdi/hilscher_nxhx10_etm.cfg
+++ b/tcl/interface/ftdi/hilscher_nxhx10_etm.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Hilscher NXHX 10-ETM
 #
diff --git a/tcl/interface/ftdi/hilscher_nxhx500_etm.cfg b/tcl/interface/ftdi/hilscher_nxhx500_etm.cfg
index 8c7981561..003b9df6b 100644
--- a/tcl/interface/ftdi/hilscher_nxhx500_etm.cfg
+++ b/tcl/interface/ftdi/hilscher_nxhx500_etm.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Hilscher NXHX 500-ETM
 #
diff --git a/tcl/interface/ftdi/hilscher_nxhx500_re.cfg b/tcl/interface/ftdi/hilscher_nxhx500_re.cfg
index 9aa2cd516..97ad38075 100644
--- a/tcl/interface/ftdi/hilscher_nxhx500_re.cfg
+++ b/tcl/interface/ftdi/hilscher_nxhx500_re.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Hilscher NXHX 500-RE
 #
diff --git a/tcl/interface/ftdi/hilscher_nxhx50_etm.cfg b/tcl/interface/ftdi/hilscher_nxhx50_etm.cfg
index a64d0e8a4..06280c1ff 100644
--- a/tcl/interface/ftdi/hilscher_nxhx50_etm.cfg
+++ b/tcl/interface/ftdi/hilscher_nxhx50_etm.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Hilscher NXHX 50-ETM
 #
diff --git a/tcl/interface/ftdi/hilscher_nxhx50_re.cfg b/tcl/interface/ftdi/hilscher_nxhx50_re.cfg
index 277883675..f14be626b 100644
--- a/tcl/interface/ftdi/hilscher_nxhx50_re.cfg
+++ b/tcl/interface/ftdi/hilscher_nxhx50_re.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Hilscher NXHX 50-RE
 #
diff --git a/tcl/interface/ftdi/hitex_lpc1768stick.cfg b/tcl/interface/ftdi/hitex_lpc1768stick.cfg
index 87affe84a..91bd5a842 100644
--- a/tcl/interface/ftdi/hitex_lpc1768stick.cfg
+++ b/tcl/interface/ftdi/hitex_lpc1768stick.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Hitex LPC1768-Stick
 #
diff --git a/tcl/interface/ftdi/hitex_str9-comstick.cfg b/tcl/interface/ftdi/hitex_str9-comstick.cfg
index 6490d65f4..f698677a6 100644
--- a/tcl/interface/ftdi/hitex_str9-comstick.cfg
+++ b/tcl/interface/ftdi/hitex_str9-comstick.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Hitex STR9-comStick
 #
diff --git a/tcl/interface/ftdi/icebear.cfg b/tcl/interface/ftdi/icebear.cfg
index 76b2102a5..4a763994b 100644
--- a/tcl/interface/ftdi/icebear.cfg
+++ b/tcl/interface/ftdi/icebear.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Section5 ICEBear
 #
diff --git a/tcl/interface/ftdi/imx8mp-evk.cfg b/tcl/interface/ftdi/imx8mp-evk.cfg
index 64f3f3db0..02564dc99 100644
--- a/tcl/interface/ftdi/imx8mp-evk.cfg
+++ b/tcl/interface/ftdi/imx8mp-evk.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Configuration file for NXP MC-IMX8MP-EVK on-board internal JTAG
 #
diff --git a/tcl/interface/ftdi/incircuit-icprog.cfg b/tcl/interface/ftdi/incircuit-icprog.cfg
index a20095446..81f287220 100644
--- a/tcl/interface/ftdi/incircuit-icprog.cfg
+++ b/tcl/interface/ftdi/incircuit-icprog.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # In-Circuit's ICprog OpenOCD JTAG Adapter
 # https://shop.in-circuit.de/product_info.php?products_id=112
diff --git a/tcl/interface/ftdi/iotlab-usb.cfg b/tcl/interface/ftdi/iotlab-usb.cfg
index 92ffa840b..b7a004e84 100644
--- a/tcl/interface/ftdi/iotlab-usb.cfg
+++ b/tcl/interface/ftdi/iotlab-usb.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # This is the integrated adapter as found on the IoT-LAB boards
 # https://github.com/iot-lab/iot-lab/wiki
diff --git a/tcl/interface/ftdi/isodebug.cfg b/tcl/interface/ftdi/isodebug.cfg
index 018998963..0a6e0807e 100644
--- a/tcl/interface/ftdi/isodebug.cfg
+++ b/tcl/interface/ftdi/isodebug.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # isodebug v1
 # 5 kV isolated JTAG/SWD + UART adapter by Unjo AB
 
diff --git a/tcl/interface/ftdi/jtag-lock-pick_tiny_2.cfg b/tcl/interface/ftdi/jtag-lock-pick_tiny_2.cfg
index 3eefecf83..ea60dcfc3 100644
--- a/tcl/interface/ftdi/jtag-lock-pick_tiny_2.cfg
+++ b/tcl/interface/ftdi/jtag-lock-pick_tiny_2.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # DISTORTEC JTAG-lock-pick Tiny 2
 #
diff --git a/tcl/interface/ftdi/jtagkey.cfg b/tcl/interface/ftdi/jtagkey.cfg
index 511244b3f..1c1c09d3f 100644
--- a/tcl/interface/ftdi/jtagkey.cfg
+++ b/tcl/interface/ftdi/jtagkey.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Amontec JTAGkey
 #
diff --git a/tcl/interface/ftdi/jtagkey2.cfg b/tcl/interface/ftdi/jtagkey2.cfg
index aa33a7528..80df347c3 100644
--- a/tcl/interface/ftdi/jtagkey2.cfg
+++ b/tcl/interface/ftdi/jtagkey2.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Amontec JTAGkey2
 #
diff --git a/tcl/interface/ftdi/jtagkey2p.cfg b/tcl/interface/ftdi/jtagkey2p.cfg
index dbfca66c4..3a76bd085 100644
--- a/tcl/interface/ftdi/jtagkey2p.cfg
+++ b/tcl/interface/ftdi/jtagkey2p.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Amontec JTAGkey2P
 #
diff --git a/tcl/interface/ftdi/kt-link.cfg b/tcl/interface/ftdi/kt-link.cfg
index 112ecf154..61c6b831b 100644
--- a/tcl/interface/ftdi/kt-link.cfg
+++ b/tcl/interface/ftdi/kt-link.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Kristech KT-Link
 #
diff --git a/tcl/interface/ftdi/lisa-l.cfg b/tcl/interface/ftdi/lisa-l.cfg
index 3da64a00e..75c5cbe7f 100644
--- a/tcl/interface/ftdi/lisa-l.cfg
+++ b/tcl/interface/ftdi/lisa-l.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Lisa/L
 #
diff --git a/tcl/interface/ftdi/luminary-icdi.cfg b/tcl/interface/ftdi/luminary-icdi.cfg
index 08676a348..9142503dd 100644
--- a/tcl/interface/ftdi/luminary-icdi.cfg
+++ b/tcl/interface/ftdi/luminary-icdi.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Luminary Micro Stellaris LM3S9B9x Evaluation Kits
 # In-Circuit Debug Interface (ICDI) Board
diff --git a/tcl/interface/ftdi/luminary-lm3s811.cfg b/tcl/interface/ftdi/luminary-lm3s811.cfg
index 90f454ef0..98be166fd 100644
--- a/tcl/interface/ftdi/luminary-lm3s811.cfg
+++ b/tcl/interface/ftdi/luminary-lm3s811.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Luminary Micro Stellaris LM3S811 Evaluation Kit
 #
diff --git a/tcl/interface/ftdi/luminary.cfg b/tcl/interface/ftdi/luminary.cfg
index 3258b214c..27d9a9da0 100644
--- a/tcl/interface/ftdi/luminary.cfg
+++ b/tcl/interface/ftdi/luminary.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Luminary Micro Stellaris Evaluation Kits
 #
diff --git a/tcl/interface/ftdi/m53evk.cfg b/tcl/interface/ftdi/m53evk.cfg
index 2b7c43445..2d9c30448 100644
--- a/tcl/interface/ftdi/m53evk.cfg
+++ b/tcl/interface/ftdi/m53evk.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # DENX M53EVK
 #
diff --git a/tcl/interface/ftdi/mbftdi.cfg b/tcl/interface/ftdi/mbftdi.cfg
index a34390ba7..09cec9ffb 100644
--- a/tcl/interface/ftdi/mbftdi.cfg
+++ b/tcl/interface/ftdi/mbftdi.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # MBFTDI
 #
diff --git a/tcl/interface/ftdi/minimodule-swd.cfg b/tcl/interface/ftdi/minimodule-swd.cfg
index 15b007afb..3eb2f5327 100644
--- a/tcl/interface/ftdi/minimodule-swd.cfg
+++ b/tcl/interface/ftdi/minimodule-swd.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Supports SWD using the FT2232H or FT4232H minimodule.
 # Each can support 2 SWD interfaces.
diff --git a/tcl/interface/ftdi/minimodule.cfg b/tcl/interface/ftdi/minimodule.cfg
index 6b2d60c07..825d7c1dc 100644
--- a/tcl/interface/ftdi/minimodule.cfg
+++ b/tcl/interface/ftdi/minimodule.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # FTDI MiniModule
 #
diff --git a/tcl/interface/ftdi/minispartan6.cfg b/tcl/interface/ftdi/minispartan6.cfg
index faf820d7a..f12bae621 100644
--- a/tcl/interface/ftdi/minispartan6.cfg
+++ b/tcl/interface/ftdi/minispartan6.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # https://www.scarabhardware.com/minispartan6/
 # https://github.com/scarabhardware/miniSpartan6-plus/raw/master/miniSpartan6%2B_Rev_B.pdf
 adapter driver ftdi
diff --git a/tcl/interface/ftdi/neodb.cfg b/tcl/interface/ftdi/neodb.cfg
index 426f5c4c7..d3b35412f 100644
--- a/tcl/interface/ftdi/neodb.cfg
+++ b/tcl/interface/ftdi/neodb.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Openmoko USB JTAG/RS232 adapter
 #
diff --git a/tcl/interface/ftdi/ngxtech.cfg b/tcl/interface/ftdi/ngxtech.cfg
index 962f25baa..635333fb9 100644
--- a/tcl/interface/ftdi/ngxtech.cfg
+++ b/tcl/interface/ftdi/ngxtech.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # NGX ARM USB JTAG
 #
diff --git a/tcl/interface/ftdi/olimex-arm-jtag-swd.cfg b/tcl/interface/ftdi/olimex-arm-jtag-swd.cfg
index ace0df98d..6aa13af74 100644
--- a/tcl/interface/ftdi/olimex-arm-jtag-swd.cfg
+++ b/tcl/interface/ftdi/olimex-arm-jtag-swd.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Olimex ARM JTAG SWD adapter
 # https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG-SWD/
diff --git a/tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg b/tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg
index ca014a4d4..cd11ad8e1 100644
--- a/tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg
+++ b/tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Olimex ARM-USB-OCD-H
 #
diff --git a/tcl/interface/ftdi/olimex-arm-usb-ocd.cfg b/tcl/interface/ftdi/olimex-arm-usb-ocd.cfg
index 6b9257583..d2261e2b7 100644
--- a/tcl/interface/ftdi/olimex-arm-usb-ocd.cfg
+++ b/tcl/interface/ftdi/olimex-arm-usb-ocd.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Olimex ARM-USB-OCD
 #
diff --git a/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg b/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg
index 98fe36784..a2b3e3edf 100644
--- a/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg
+++ b/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Olimex ARM-USB-TINY-H
 #
diff --git a/tcl/interface/ftdi/olimex-jtag-tiny.cfg b/tcl/interface/ftdi/olimex-jtag-tiny.cfg
index ebca496d2..7d8e81da3 100644
--- a/tcl/interface/ftdi/olimex-jtag-tiny.cfg
+++ b/tcl/interface/ftdi/olimex-jtag-tiny.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Olimex ARM-USB-TINY
 #
diff --git a/tcl/interface/ftdi/oocdlink.cfg b/tcl/interface/ftdi/oocdlink.cfg
index 367112a6c..0e99b67a4 100644
--- a/tcl/interface/ftdi/oocdlink.cfg
+++ b/tcl/interface/ftdi/oocdlink.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Joern Kaipf's OOCDLink
 #
diff --git a/tcl/interface/ftdi/opendous_ftdi.cfg b/tcl/interface/ftdi/opendous_ftdi.cfg
index f212bf561..5d6f5aee1 100644
--- a/tcl/interface/ftdi/opendous_ftdi.cfg
+++ b/tcl/interface/ftdi/opendous_ftdi.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Opendous
 #
diff --git a/tcl/interface/ftdi/openocd-usb-hs.cfg b/tcl/interface/ftdi/openocd-usb-hs.cfg
index d1a3ff0a2..af1f61c33 100644
--- a/tcl/interface/ftdi/openocd-usb-hs.cfg
+++ b/tcl/interface/ftdi/openocd-usb-hs.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # embedded projects openocd usb adapter v3
 #
diff --git a/tcl/interface/ftdi/openocd-usb.cfg b/tcl/interface/ftdi/openocd-usb.cfg
index 620d20436..c333d65ca 100644
--- a/tcl/interface/ftdi/openocd-usb.cfg
+++ b/tcl/interface/ftdi/openocd-usb.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Hubert Hoegl's USB to JTAG
 #
diff --git a/tcl/interface/ftdi/openrd.cfg b/tcl/interface/ftdi/openrd.cfg
index 88b2a6e51..b6b2d1d93 100644
--- a/tcl/interface/ftdi/openrd.cfg
+++ b/tcl/interface/ftdi/openrd.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Marvell OpenRD
 #
diff --git a/tcl/interface/ftdi/pipistrello.cfg b/tcl/interface/ftdi/pipistrello.cfg
index 11fcf077c..29ecd1229 100644
--- a/tcl/interface/ftdi/pipistrello.cfg
+++ b/tcl/interface/ftdi/pipistrello.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # http://pipistrello.saanlima.com/
 # http://www.saanlima.com/download/pipistrello-v2.0/pipistrello_v2_schematic.pdf
 adapter driver ftdi
diff --git a/tcl/interface/ftdi/redbee-econotag.cfg b/tcl/interface/ftdi/redbee-econotag.cfg
index 35bedfa7e..d0d3d833e 100644
--- a/tcl/interface/ftdi/redbee-econotag.cfg
+++ b/tcl/interface/ftdi/redbee-econotag.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Redwire Redbee-Econotag
 #
diff --git a/tcl/interface/ftdi/redbee-usb.cfg b/tcl/interface/ftdi/redbee-usb.cfg
index a57176610..98805536d 100644
--- a/tcl/interface/ftdi/redbee-usb.cfg
+++ b/tcl/interface/ftdi/redbee-usb.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Redwire Redbee-USB
 #
diff --git a/tcl/interface/ftdi/rowley-cc-arm-swd.cfg b/tcl/interface/ftdi/rowley-cc-arm-swd.cfg
index fb416db56..585d589c8 100644
--- a/tcl/interface/ftdi/rowley-cc-arm-swd.cfg
+++ b/tcl/interface/ftdi/rowley-cc-arm-swd.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Rowley ARM SWD Adapter
 # http://sites.fastspring.com/rowley/product/armswdadapter
diff --git a/tcl/interface/ftdi/sheevaplug.cfg b/tcl/interface/ftdi/sheevaplug.cfg
index 5929453c1..29c868809 100644
--- a/tcl/interface/ftdi/sheevaplug.cfg
+++ b/tcl/interface/ftdi/sheevaplug.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Marvel SheevaPlug Development Kit
 #
diff --git a/tcl/interface/ftdi/signalyzer-lite.cfg b/tcl/interface/ftdi/signalyzer-lite.cfg
index 9e010d394..e6c3839c9 100644
--- a/tcl/interface/ftdi/signalyzer-lite.cfg
+++ b/tcl/interface/ftdi/signalyzer-lite.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Xverve Signalyzer LITE (DT-USB-SLITE)
 #
diff --git a/tcl/interface/ftdi/signalyzer.cfg b/tcl/interface/ftdi/signalyzer.cfg
index d94c6bc7f..fa7a7edc1 100644
--- a/tcl/interface/ftdi/signalyzer.cfg
+++ b/tcl/interface/ftdi/signalyzer.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Xverve Signalyzer Tool (DT-USB-ST)
 #
diff --git a/tcl/interface/ftdi/stm32-stick.cfg b/tcl/interface/ftdi/stm32-stick.cfg
index fd877ec77..1d72d20e3 100644
--- a/tcl/interface/ftdi/stm32-stick.cfg
+++ b/tcl/interface/ftdi/stm32-stick.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Hitex STM32-PerformanceStick
 #
diff --git a/tcl/interface/ftdi/swd-resistor-hack.cfg b/tcl/interface/ftdi/swd-resistor-hack.cfg
index 5bdb87c18..d9e715871 100644
--- a/tcl/interface/ftdi/swd-resistor-hack.cfg
+++ b/tcl/interface/ftdi/swd-resistor-hack.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Connect TDI to SWDIO via a suitable series resistor (220-470 Ohm or
 # so depending on the drive capability of the target and adapter);
diff --git a/tcl/interface/ftdi/ti-icdi.cfg b/tcl/interface/ftdi/ti-icdi.cfg
index f6e16be84..964de76e6 100644
--- a/tcl/interface/ftdi/ti-icdi.cfg
+++ b/tcl/interface/ftdi/ti-icdi.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # This is an FTDI-based debugging solution as found on some TI boards,
 # e.g. CC3200 LaunchPad.
diff --git a/tcl/interface/ftdi/tumpa-lite.cfg b/tcl/interface/ftdi/tumpa-lite.cfg
index 625db16b1..e3f12e3b1 100644
--- a/tcl/interface/ftdi/tumpa-lite.cfg
+++ b/tcl/interface/ftdi/tumpa-lite.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # TIAO USB Multi-Protocol Adapter (TUMPA) Lite
 #
diff --git a/tcl/interface/ftdi/tumpa.cfg b/tcl/interface/ftdi/tumpa.cfg
index 4491c40b7..db4311bfe 100644
--- a/tcl/interface/ftdi/tumpa.cfg
+++ b/tcl/interface/ftdi/tumpa.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # TIAO USB Multi-Protocol Adapter (TUMPA)
 #
diff --git a/tcl/interface/ftdi/turtelizer2-revB.cfg b/tcl/interface/ftdi/turtelizer2-revB.cfg
index 593a545a8..f90fc58c1 100644
--- a/tcl/interface/ftdi/turtelizer2-revB.cfg
+++ b/tcl/interface/ftdi/turtelizer2-revB.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # egnite Turtelizer 2 rev B (with SRST only)
 #
diff --git a/tcl/interface/ftdi/turtelizer2-revC.cfg b/tcl/interface/ftdi/turtelizer2-revC.cfg
index 6e19259b9..94617a1dd 100644
--- a/tcl/interface/ftdi/turtelizer2-revC.cfg
+++ b/tcl/interface/ftdi/turtelizer2-revC.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # egnite Turtelizer 2 revC (with TRST and SRST)
 #
diff --git a/tcl/interface/ftdi/um232h.cfg b/tcl/interface/ftdi/um232h.cfg
index 10f267dd0..6be08b59c 100644
--- a/tcl/interface/ftdi/um232h.cfg
+++ b/tcl/interface/ftdi/um232h.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # FTDI UM232H as a JTAG interface
 #
diff --git a/tcl/interface/ftdi/vpaclink.cfg b/tcl/interface/ftdi/vpaclink.cfg
index 7e7f25702..ff508f2dc 100644
--- a/tcl/interface/ftdi/vpaclink.cfg
+++ b/tcl/interface/ftdi/vpaclink.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Voipac VPACLink
 #
diff --git a/tcl/interface/ftdi/xds100v2.cfg b/tcl/interface/ftdi/xds100v2.cfg
index bda87811b..373df4f49 100644
--- a/tcl/interface/ftdi/xds100v2.cfg
+++ b/tcl/interface/ftdi/xds100v2.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Texas Instruments XDS100v2
 #
diff --git a/tcl/interface/ftdi/xds100v3.cfg b/tcl/interface/ftdi/xds100v3.cfg
index 43a11bd35..dc722336f 100644
--- a/tcl/interface/ftdi/xds100v3.cfg
+++ b/tcl/interface/ftdi/xds100v3.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Texas Instruments XDS100 ver 3.0
 #
diff --git a/tcl/interface/imx-native.cfg b/tcl/interface/imx-native.cfg
index 9e1f38d03..01e42e34a 100644
--- a/tcl/interface/imx-native.cfg
+++ b/tcl/interface/imx-native.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Config for using NXP IMX CPU
 #
diff --git a/tcl/interface/jlink.cfg b/tcl/interface/jlink.cfg
index f9a18b05f..181c2cc93 100644
--- a/tcl/interface/jlink.cfg
+++ b/tcl/interface/jlink.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # SEGGER J-Link
 #
diff --git a/tcl/interface/jtag_vpi.cfg b/tcl/interface/jtag_vpi.cfg
index f2f90f745..e8164abeb 100644
--- a/tcl/interface/jtag_vpi.cfg
+++ b/tcl/interface/jtag_vpi.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 adapter driver jtag_vpi
 
 # Set the VPI JTAG server port
diff --git a/tcl/interface/kitprog.cfg b/tcl/interface/kitprog.cfg
index 933a05408..eb9ad9804 100644
--- a/tcl/interface/kitprog.cfg
+++ b/tcl/interface/kitprog.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Cypress Semiconductor KitProg
 #
diff --git a/tcl/interface/nds32-aice.cfg b/tcl/interface/nds32-aice.cfg
index fcc33ec28..1d9717c4c 100644
--- a/tcl/interface/nds32-aice.cfg
+++ b/tcl/interface/nds32-aice.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Andes AICE
 #
diff --git a/tcl/interface/nulink.cfg b/tcl/interface/nulink.cfg
index e49b36cda..2a4bc0b93 100644
--- a/tcl/interface/nulink.cfg
+++ b/tcl/interface/nulink.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Nuvoton Nu-Link in-circuit debugger/programmer
 #
diff --git a/tcl/interface/opendous.cfg b/tcl/interface/opendous.cfg
index 23fddc69c..9c5a804c8 100644
--- a/tcl/interface/opendous.cfg
+++ b/tcl/interface/opendous.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # opendous-jtag
 #
diff --git a/tcl/interface/openjtag.cfg b/tcl/interface/openjtag.cfg
index 8d015b704..1602352db 100644
--- a/tcl/interface/openjtag.cfg
+++ b/tcl/interface/openjtag.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # OpenJTAG
 #
diff --git a/tcl/interface/osbdm.cfg b/tcl/interface/osbdm.cfg
index 6e88c0736..e21848d89 100644
--- a/tcl/interface/osbdm.cfg
+++ b/tcl/interface/osbdm.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # P&E Micro OSBDM (aka OSJTAG) interface
 #
diff --git a/tcl/interface/parport.cfg b/tcl/interface/parport.cfg
index 05195f027..b9fceeb85 100644
--- a/tcl/interface/parport.cfg
+++ b/tcl/interface/parport.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Parallel port wiggler (many clones available) on port 0x378
 #
diff --git a/tcl/interface/parport_dlc5.cfg b/tcl/interface/parport_dlc5.cfg
index 19e21ffda..24acea7a9 100644
--- a/tcl/interface/parport_dlc5.cfg
+++ b/tcl/interface/parport_dlc5.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Xilinx Parallel Cable III 'DLC 5' (and various clones)
 #
diff --git a/tcl/interface/raspberrypi-native.cfg b/tcl/interface/raspberrypi-native.cfg
index 634b8c95a..6d5c3bfd4 100644
--- a/tcl/interface/raspberrypi-native.cfg
+++ b/tcl/interface/raspberrypi-native.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Config for using Raspberry Pi's expansion header
 #
diff --git a/tcl/interface/raspberrypi2-native.cfg b/tcl/interface/raspberrypi2-native.cfg
index 14c5771c4..547df0872 100644
--- a/tcl/interface/raspberrypi2-native.cfg
+++ b/tcl/interface/raspberrypi2-native.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Config for using Raspberry Pi's expansion header
 #
diff --git a/tcl/interface/rlink.cfg b/tcl/interface/rlink.cfg
index 29d3ce599..7671a3b0c 100644
--- a/tcl/interface/rlink.cfg
+++ b/tcl/interface/rlink.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Raisonance RLink
 #
diff --git a/tcl/interface/rshim.cfg b/tcl/interface/rshim.cfg
index accabf534..1d5da593e 100644
--- a/tcl/interface/rshim.cfg
+++ b/tcl/interface/rshim.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # BlueField SoC in-circuit debugger/programmer
 #
diff --git a/tcl/interface/stlink-dap.cfg b/tcl/interface/stlink-dap.cfg
index 5a7d2e9ae..5c24cbdab 100644
--- a/tcl/interface/stlink-dap.cfg
+++ b/tcl/interface/stlink-dap.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit
 # debugger/programmer
diff --git a/tcl/interface/stlink-v1.cfg b/tcl/interface/stlink-v1.cfg
index 000422725..96ed088d0 100644
--- a/tcl/interface/stlink-v1.cfg
+++ b/tcl/interface/stlink-v1.cfg
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 echo "WARNING: interface/stlink-v1.cfg is deprecated, please switch to interface/stlink.cfg"
 source [find interface/stlink.cfg]
diff --git a/tcl/interface/stlink-v2-1.cfg b/tcl/interface/stlink-v2-1.cfg
index 62f37dc33..d2baad47d 100644
--- a/tcl/interface/stlink-v2-1.cfg
+++ b/tcl/interface/stlink-v2-1.cfg
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 echo "WARNING: interface/stlink-v2-1.cfg is deprecated, please switch to interface/stlink.cfg"
 source [find interface/stlink.cfg]
diff --git a/tcl/interface/stlink-v2.cfg b/tcl/interface/stlink-v2.cfg
index 070e46958..400411e9c 100644
--- a/tcl/interface/stlink-v2.cfg
+++ b/tcl/interface/stlink-v2.cfg
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 echo "WARNING: interface/stlink-v2.cfg is deprecated, please switch to interface/stlink.cfg"
 source [find interface/stlink.cfg]
diff --git a/tcl/interface/stlink.cfg b/tcl/interface/stlink.cfg
index 8ac9b579f..e4906b74e 100644
--- a/tcl/interface/stlink.cfg
+++ b/tcl/interface/stlink.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit
 # debugger/programmer
diff --git a/tcl/interface/sysfsgpio-raspberrypi.cfg b/tcl/interface/sysfsgpio-raspberrypi.cfg
index 0030560ca..d2095a9fe 100644
--- a/tcl/interface/sysfsgpio-raspberrypi.cfg
+++ b/tcl/interface/sysfsgpio-raspberrypi.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Config for using RaspberryPi's expansion header
 #
diff --git a/tcl/interface/ti-icdi.cfg b/tcl/interface/ti-icdi.cfg
index 5cf6e37be..db4e1e0a0 100644
--- a/tcl/interface/ti-icdi.cfg
+++ b/tcl/interface/ti-icdi.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # TI Stellaris In-Circuit Debug Interface (ICDI) Board
 #
diff --git a/tcl/interface/ulink.cfg b/tcl/interface/ulink.cfg
index 164b990a1..89a02e95e 100644
--- a/tcl/interface/ulink.cfg
+++ b/tcl/interface/ulink.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Keil ULINK running OpenULINK firmware.
 #
diff --git a/tcl/interface/usb-jtag.cfg b/tcl/interface/usb-jtag.cfg
index bbfb076d1..039c748b3 100644
--- a/tcl/interface/usb-jtag.cfg
+++ b/tcl/interface/usb-jtag.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # ixo-usb-jtag - Emulation of a Altera Bus Blaster I on a Cypress FX2 IC.
 #
 # The ixo-usb-jtag firmware can be loaded onto a bunch of different hardware
diff --git a/tcl/interface/usbprog.cfg b/tcl/interface/usbprog.cfg
index f65c1d473..4f04b147e 100644
--- a/tcl/interface/usbprog.cfg
+++ b/tcl/interface/usbprog.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Embedded Projects USBprog
 #
diff --git a/tcl/interface/vsllink.cfg b/tcl/interface/vsllink.cfg
index d40dbb429..f780c896a 100644
--- a/tcl/interface/vsllink.cfg
+++ b/tcl/interface/vsllink.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Versaloon Link -- VSLLink
 #
diff --git a/tcl/interface/xds110.cfg b/tcl/interface/xds110.cfg
index 74122c3e6..aff0f38fc 100644
--- a/tcl/interface/xds110.cfg
+++ b/tcl/interface/xds110.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Texas Instruments XDS110
 #

-----------------------------------------------------------------------

Summary of changes:
 tcl/bitsbytes.tcl                            | 2 ++
 tcl/chip/atmel/at91/aic.tcl                  | 2 ++
 tcl/chip/atmel/at91/at91_pio.cfg             | 2 ++
 tcl/chip/atmel/at91/at91_pmc.cfg             | 2 ++
 tcl/chip/atmel/at91/at91_rstc.cfg            | 2 ++
 tcl/chip/atmel/at91/at91_wdt.cfg             | 2 ++
 tcl/chip/atmel/at91/at91sam7x128.tcl         | 2 ++
 tcl/chip/atmel/at91/at91sam7x256.tcl         | 2 ++
 tcl/chip/atmel/at91/at91sam9261.cfg          | 2 ++
 tcl/chip/atmel/at91/at91sam9261_matrix.cfg   | 1 +
 tcl/chip/atmel/at91/at91sam9263.cfg          | 2 ++
 tcl/chip/atmel/at91/at91sam9263_matrix.cfg   | 2 ++
 tcl/chip/atmel/at91/at91sam9_init.cfg        | 2 ++
 tcl/chip/atmel/at91/at91sam9_sdramc.cfg      | 1 +
 tcl/chip/atmel/at91/at91sam9_smc.cfg         | 2 ++
 tcl/chip/atmel/at91/hardware.cfg             | 2 ++
 tcl/chip/atmel/at91/pmc.tcl                  | 1 +
 tcl/chip/atmel/at91/rtt.tcl                  | 1 +
 tcl/chip/atmel/at91/sam9_smc.cfg             | 2 ++
 tcl/chip/atmel/at91/usarts.tcl               | 2 ++
 tcl/chip/st/spear/quirk_no_srst.tcl          | 2 ++
 tcl/chip/st/spear/spear3xx.tcl               | 2 ++
 tcl/chip/st/spear/spear3xx_ddr.tcl           | 2 ++
 tcl/chip/st/stm32/stm32.tcl                  | 2 ++
 tcl/chip/st/stm32/stm32_rcc.tcl              | 1 +
 tcl/chip/st/stm32/stm32_regs.tcl             | 2 ++
 tcl/chip/ti/lm3s/lm3s.tcl                    | 2 ++
 tcl/chip/ti/lm3s/lm3s_regs.tcl               | 2 ++
 tcl/cpld/altera-5m570z-cpld.cfg              | 2 ++
 tcl/cpld/altera-epm240.cfg                   | 2 ++
 tcl/cpld/jtagspi.cfg                         | 2 ++
 tcl/cpld/lattice-lc4032ze.cfg                | 2 ++
 tcl/cpld/xilinx-xc6s.cfg                     | 2 ++
 tcl/cpld/xilinx-xc7.cfg                      | 2 ++
 tcl/cpld/xilinx-xcf-p.cfg                    | 2 ++
 tcl/cpld/xilinx-xcf-s.cfg                    | 2 ++
 tcl/cpld/xilinx-xcr3256.cfg                  | 2 ++
 tcl/cpld/xilinx-xcu.cfg                      | 2 ++
 tcl/cpu/arm/arm7tdmi.tcl                     | 2 ++
 tcl/cpu/arm/arm920.tcl                       | 2 ++
 tcl/cpu/arm/arm946.tcl                       | 2 ++
 tcl/cpu/arm/arm966.tcl                       | 2 ++
 tcl/cpu/arm/cortex_m3.tcl                    | 2 ++
 tcl/fpga/altera-10m50.cfg                    | 2 ++
 tcl/fpga/altera-ep3c10.cfg                   | 2 ++
 tcl/fpga/xilinx-dna.cfg                      | 2 ++
 tcl/fpga/xilinx-xadc.cfg                     | 2 ++
 tcl/interface/altera-usb-blaster.cfg         | 2 ++
 tcl/interface/altera-usb-blaster2.cfg        | 2 ++
 tcl/interface/arm-jtag-ew.cfg                | 2 ++
 tcl/interface/at91rm9200.cfg                 | 2 ++
 tcl/interface/buspirate.cfg                  | 2 ++
 tcl/interface/calao-usb-a9260.cfg            | 2 ++
 tcl/interface/chameleon.cfg                  | 2 ++
 tcl/interface/cmsis-dap.cfg                  | 2 ++
 tcl/interface/dummy.cfg                      | 2 ++
 tcl/interface/estick.cfg                     | 2 ++
 tcl/interface/flashlink.cfg                  | 2 ++
 tcl/interface/ft232r.cfg                     | 2 ++
 tcl/interface/ftdi/100ask-openjtag.cfg       | 2 ++
 tcl/interface/ftdi/axm0432.cfg               | 2 ++
 tcl/interface/ftdi/c232hm.cfg                | 2 ++
 tcl/interface/ftdi/calao-usb-a9260-c01.cfg   | 2 ++
 tcl/interface/ftdi/calao-usb-a9260-c02.cfg   | 2 ++
 tcl/interface/ftdi/cortino.cfg               | 2 ++
 tcl/interface/ftdi/digilent-hs1.cfg          | 2 ++
 tcl/interface/ftdi/digilent-hs2.cfg          | 2 ++
 tcl/interface/ftdi/digilent_jtag_hs3.cfg     | 2 ++
 tcl/interface/ftdi/digilent_jtag_smt2.cfg    | 2 ++
 tcl/interface/ftdi/digilent_jtag_smt2_nc.cfg | 2 ++
 tcl/interface/ftdi/dlp-usb1232h.cfg          | 2 ++
 tcl/interface/ftdi/dp_busblaster.cfg         | 2 ++
 tcl/interface/ftdi/dp_busblaster_kt-link.cfg | 2 ++
 tcl/interface/ftdi/flossjtag-noeeprom.cfg    | 2 ++
 tcl/interface/ftdi/flossjtag.cfg             | 2 ++
 tcl/interface/ftdi/flyswatter.cfg           ...
 
[truncated message content]

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-745-g4157732bd

From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:54:05

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  4157732bd84c4e9e4b55357e1dc9a96078a35ee1 (commit)
       via  e6505b04892ccacf75603c3d173616f5d92809e7 (commit)
      from  2c5f263bcd61592b6575ed92672d14143bdb9aad (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 4157732bd84c4e9e4b55357e1dc9a96078a35ee1
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jun 12 23:48:05 2022 +0200

    tcl/board: add SPDX tag
    
    For historical reasons, no license information was added to the
    tcl files. This makes trivial adding the SPDX tag through script:
            fgrep -rL SPDX tcl/board | while read a;do \
            sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
            }' $a;done
    
    With no specific license information from the author, let's extend
    the OpenOCD project license GPL-2.0-or-later to the files.
    
    Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7028
    Tested-by: jenkins
    Reviewed-by: Tarek BOCHKATI <tar...@gm...>

diff --git a/tcl/board/8devices-lima.cfg b/tcl/board/8devices-lima.cfg
index 0d35cfbc1..a094caede 100644
--- a/tcl/board/8devices-lima.cfg
+++ b/tcl/board/8devices-lima.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Product page:
 # https://www.8devices.com/products/lima
 #
diff --git a/tcl/board/actux3.cfg b/tcl/board/actux3.cfg
index 0de4cb4ca..edb529c88 100644
--- a/tcl/board/actux3.cfg
+++ b/tcl/board/actux3.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # board config file for AcTux3/XBA IXP42x board
 # Date:   2010-12-16
 # Author: Michael Schwingen <mi...@sc...>
diff --git a/tcl/board/adapteva_parallella1.cfg b/tcl/board/adapteva_parallella1.cfg
index 83d1cd44b..d6336a8e2 100644
--- a/tcl/board/adapteva_parallella1.cfg
+++ b/tcl/board/adapteva_parallella1.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Adapteva Parallella-I board (via Porcupine-1 adapter board)
 #
diff --git a/tcl/board/adsp-sc584-ezbrd.cfg b/tcl/board/adsp-sc584-ezbrd.cfg
index 82df381f6..366a24a3f 100644
--- a/tcl/board/adsp-sc584-ezbrd.cfg
+++ b/tcl/board/adsp-sc584-ezbrd.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Analog Devices ADSP-SC584-EZBRD evaluation board
 #
diff --git a/tcl/board/alphascale_asm9260_ek.cfg b/tcl/board/alphascale_asm9260_ek.cfg
index 1c126827f..33a835411 100644
--- a/tcl/board/alphascale_asm9260_ek.cfg
+++ b/tcl/board/alphascale_asm9260_ek.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 source [find target/alphascale_asm9260t.cfg]
 
 reset_config trst_and_srst
diff --git a/tcl/board/altera_sockit.cfg b/tcl/board/altera_sockit.cfg
index 4d10aef7b..bbd87d646 100644
--- a/tcl/board/altera_sockit.cfg
+++ b/tcl/board/altera_sockit.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Cyclone V SocKit board
 # http://www.altera.com/b/arrow-sockit.html
diff --git a/tcl/board/am3517evm.cfg b/tcl/board/am3517evm.cfg
index 8d6eba160..0b19be68b 100644
--- a/tcl/board/am3517evm.cfg
+++ b/tcl/board/am3517evm.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # DANGER!!!! early work in progress for this PCB/target.
 #
 # The most basic operations work well enough that it is
diff --git a/tcl/board/arm_evaluator7t.cfg b/tcl/board/arm_evaluator7t.cfg
index ef4b7821f..0fb8778ce 100644
--- a/tcl/board/arm_evaluator7t.cfg
+++ b/tcl/board/arm_evaluator7t.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # This board is from ARM and has an samsung s3c45101x01 chip
 
 source [find target/samsung_s3c4510.cfg]
diff --git a/tcl/board/arm_musca_a.cfg b/tcl/board/arm_musca_a.cfg
index 25f8ce61a..b4880d100 100644
--- a/tcl/board/arm_musca_a.cfg
+++ b/tcl/board/arm_musca_a.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Configuration script for ARM Musca-A development board
 #
diff --git a/tcl/board/arty_s7.cfg b/tcl/board/arty_s7.cfg
index a5e26fc94..eaa15ab40 100644
--- a/tcl/board/arty_s7.cfg
+++ b/tcl/board/arty_s7.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Arty S7: Spartan7 25/50 FPGA Board for Makers and Hobbyists
 #
diff --git a/tcl/board/asus-rt-n16.cfg b/tcl/board/asus-rt-n16.cfg
index 78f111d38..a02bab853 100644
--- a/tcl/board/asus-rt-n16.cfg
+++ b/tcl/board/asus-rt-n16.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # http://wikidevi.com/wiki/ASUS_RT-N16
 #
diff --git a/tcl/board/asus-rt-n66u.cfg b/tcl/board/asus-rt-n66u.cfg
index 4b255cf94..dda0f33b7 100644
--- a/tcl/board/asus-rt-n66u.cfg
+++ b/tcl/board/asus-rt-n66u.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # http://wikidevi.com/wiki/Asus_RT-N66U
 #
diff --git a/tcl/board/at91cap7a-stk-sdram.cfg b/tcl/board/at91cap7a-stk-sdram.cfg
index 182a4067f..6da917ac7 100644
--- a/tcl/board/at91cap7a-stk-sdram.cfg
+++ b/tcl/board/at91cap7a-stk-sdram.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4394
 #
 # use combined on interfaces or targets that can't set TRST/SRST separately
diff --git a/tcl/board/at91eb40a.cfg b/tcl/board/at91eb40a.cfg
index d314e181d..60c6c6eac 100644
--- a/tcl/board/at91eb40a.cfg
+++ b/tcl/board/at91eb40a.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #Script for AT91EB40a
 
 # FIXME use some standard target config, maybe create one from this
diff --git a/tcl/board/at91rm9200-dk.cfg b/tcl/board/at91rm9200-dk.cfg
index b8ec00eab..3751103fc 100644
--- a/tcl/board/at91rm9200-dk.cfg
+++ b/tcl/board/at91rm9200-dk.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # This is for the "at91rm9200-DK" (not the EK) eval board.
 #
diff --git a/tcl/board/at91rm9200-ek.cfg b/tcl/board/at91rm9200-ek.cfg
index 958bc9d51..e38914e46 100644
--- a/tcl/board/at91rm9200-ek.cfg
+++ b/tcl/board/at91rm9200-ek.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Copyright 2010 Jean-Christophe PLAGNIOL-VILLARD <pla...@jc...>
 #
diff --git a/tcl/board/at91sam9261-ek.cfg b/tcl/board/at91sam9261-ek.cfg
index 1f3de48b8..c2d97b04e 100644
--- a/tcl/board/at91sam9261-ek.cfg
+++ b/tcl/board/at91sam9261-ek.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 ################################################################################
 # Atmel AT91SAM9261-EK eval board
 ################################################################################
diff --git a/tcl/board/at91sam9263-ek.cfg b/tcl/board/at91sam9263-ek.cfg
index ab04228ce..328a792a4 100644
--- a/tcl/board/at91sam9263-ek.cfg
+++ b/tcl/board/at91sam9263-ek.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 ################################################################################
 # Atmel AT91SAM9263-EK eval board
 ################################################################################
diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index 04d9a197c..a5831cd91 100644
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #################################################################################################
 #												#
 # Author: Gary Carlson (gca...@ca...)						#
diff --git a/tcl/board/atmel_at91sam7s-ek.cfg b/tcl/board/atmel_at91sam7s-ek.cfg
index 48edfc9a7..9cf85df23 100644
--- a/tcl/board/atmel_at91sam7s-ek.cfg
+++ b/tcl/board/atmel_at91sam7s-ek.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Atmel AT91SAM7S-EK
 # http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3784
 
diff --git a/tcl/board/atmel_at91sam9260-ek.cfg b/tcl/board/atmel_at91sam9260-ek.cfg
index a37f1f5d8..56fce3a71 100644
--- a/tcl/board/atmel_at91sam9260-ek.cfg
+++ b/tcl/board/atmel_at91sam9260-ek.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 ################################################################################
 # Atmel AT91SAM9260-EK eval board
 #
diff --git a/tcl/board/atmel_at91sam9rl-ek.cfg b/tcl/board/atmel_at91sam9rl-ek.cfg
index e18d1fdf3..cc3d9744e 100644
--- a/tcl/board/atmel_at91sam9rl-ek.cfg
+++ b/tcl/board/atmel_at91sam9rl-ek.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 ################################################################################
 #
 # Generated for Atmel AT91SAM9RL-EK evaluation board using Atmel SAM-ICE (J-Link) V6
diff --git a/tcl/board/atmel_sam3n_ek.cfg b/tcl/board/atmel_sam3n_ek.cfg
index e43008f10..af2fd952b 100644
--- a/tcl/board/atmel_sam3n_ek.cfg
+++ b/tcl/board/atmel_sam3n_ek.cfg
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
 
 #
 # Board configuration for Atmel's SAM3N-EK
diff --git a/tcl/board/atmel_sam3s_ek.cfg b/tcl/board/atmel_sam3s_ek.cfg
index 6e8ffe417..136e31d22 100644
--- a/tcl/board/atmel_sam3s_ek.cfg
+++ b/tcl/board/atmel_sam3s_ek.cfg
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 source [find target/at91sam3sXX.cfg]
diff --git a/tcl/board/atmel_sam3u_ek.cfg b/tcl/board/atmel_sam3u_ek.cfg
index 1584879bf..c308003a4 100644
--- a/tcl/board/atmel_sam3u_ek.cfg
+++ b/tcl/board/atmel_sam3u_ek.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 source [find target/at91sam3u4e.cfg]
 
 reset_config srst_only
diff --git a/tcl/board/atmel_sam3x_ek.cfg b/tcl/board/atmel_sam3x_ek.cfg
index bb8cd1713..c321cfbe2 100644
--- a/tcl/board/atmel_sam3x_ek.cfg
+++ b/tcl/board/atmel_sam3x_ek.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 source [find target/at91sam3ax_8x.cfg]
 
 reset_config srst_only
diff --git a/tcl/board/atmel_sam4e_ek.cfg b/tcl/board/atmel_sam4e_ek.cfg
index 75e67a94f..61191a925 100644
--- a/tcl/board/atmel_sam4e_ek.cfg
+++ b/tcl/board/atmel_sam4e_ek.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # This is an SAM4E-EK board with a single SAM4E16 chip.
 # http://www.atmel.com/tools/sam4e-ek.aspx
 
diff --git a/tcl/board/atmel_sam4l8_xplained_pro.cfg b/tcl/board/atmel_sam4l8_xplained_pro.cfg
index 80ccc9f19..d0c45163c 100644
--- a/tcl/board/atmel_sam4l8_xplained_pro.cfg
+++ b/tcl/board/atmel_sam4l8_xplained_pro.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Atmel SAM4L8 Xplained Pro evaluation kit.
 # http://www.atmel.com/tools/ATSAM4L8-XPRO.aspx
diff --git a/tcl/board/atmel_sam4s_ek.cfg b/tcl/board/atmel_sam4s_ek.cfg
index ca11e5487..7e4bb83a5 100644
--- a/tcl/board/atmel_sam4s_ek.cfg
+++ b/tcl/board/atmel_sam4s_ek.cfg
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 source [find target/at91sam4sXX.cfg]
diff --git a/tcl/board/atmel_sam4s_xplained_pro.cfg b/tcl/board/atmel_sam4s_xplained_pro.cfg
index d2acc487e..92191c7d1 100644
--- a/tcl/board/atmel_sam4s_xplained_pro.cfg
+++ b/tcl/board/atmel_sam4s_xplained_pro.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Atmel SAM4S Xplained Pro evaluation kit.
 # http://www.atmel.com/tools/ATSAM4S-XPRO.aspx
diff --git a/tcl/board/atmel_samc20_xplained_pro.cfg b/tcl/board/atmel_samc20_xplained_pro.cfg
index 1278eb7f1..3ac89a536 100644
--- a/tcl/board/atmel_samc20_xplained_pro.cfg
+++ b/tcl/board/atmel_samc20_xplained_pro.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Atmel SAMC20 Xplained Pro evaluation kit.
 #
diff --git a/tcl/board/atmel_samc21_xplained_pro.cfg b/tcl/board/atmel_samc21_xplained_pro.cfg
index ac269305c..5ad6ccfda 100644
--- a/tcl/board/atmel_samc21_xplained_pro.cfg
+++ b/tcl/board/atmel_samc21_xplained_pro.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Atmel SAMC21 Xplained Pro evaluation kit.
 # http://www.atmel.com/tools/ATSAMC21-XPRO.aspx
diff --git a/tcl/board/atmel_samd10_xplained_mini.cfg b/tcl/board/atmel_samd10_xplained_mini.cfg
index 64ae11ee9..f9f1d242e 100644
--- a/tcl/board/atmel_samd10_xplained_mini.cfg
+++ b/tcl/board/atmel_samd10_xplained_mini.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Atmel SAMD10 Xplained mini evaluation kit.
 # http://www.atmel.com/tools/atsamd10-xmini.aspx
diff --git a/tcl/board/atmel_samd11_xplained_pro.cfg b/tcl/board/atmel_samd11_xplained_pro.cfg
index 8ce9751b8..724c921b5 100644
--- a/tcl/board/atmel_samd11_xplained_pro.cfg
+++ b/tcl/board/atmel_samd11_xplained_pro.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Atmel SAMD11 Xplained Pro evaluation kit.
 #
diff --git a/tcl/board/atmel_samd20_xplained_pro.cfg b/tcl/board/atmel_samd20_xplained_pro.cfg
index 525aee069..1492958aa 100644
--- a/tcl/board/atmel_samd20_xplained_pro.cfg
+++ b/tcl/board/atmel_samd20_xplained_pro.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Atmel SAMD20 Xplained Pro evaluation kit.
 # http://www.atmel.com/tools/ATSAMD20-XPRO.aspx
diff --git a/tcl/board/atmel_samd21_xplained_pro.cfg b/tcl/board/atmel_samd21_xplained_pro.cfg
index 843b0ce21..f55b6b94d 100644
--- a/tcl/board/atmel_samd21_xplained_pro.cfg
+++ b/tcl/board/atmel_samd21_xplained_pro.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Atmel SAMD21 Xplained Pro evaluation kit.
 #
diff --git a/tcl/board/atmel_same70_xplained.cfg b/tcl/board/atmel_same70_xplained.cfg
index a22e801a2..f20e2a30f 100644
--- a/tcl/board/atmel_same70_xplained.cfg
+++ b/tcl/board/atmel_same70_xplained.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Atmel SAME70 Xplained evaluation kit.
 # http://www.atmel.com/tools/ATSAME70-XPLD.aspx
diff --git a/tcl/board/atmel_samg53_xplained_pro.cfg b/tcl/board/atmel_samg53_xplained_pro.cfg
index 06638cf56..060750c48 100644
--- a/tcl/board/atmel_samg53_xplained_pro.cfg
+++ b/tcl/board/atmel_samg53_xplained_pro.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Atmel SAMG53 Xplained Pro evaluation kit.
 # http://www.atmel.com/tools/ATSAMG53-XPRO.aspx
diff --git a/tcl/board/atmel_samg55_xplained_pro.cfg b/tcl/board/atmel_samg55_xplained_pro.cfg
index 3797bf8bc..147dc732b 100644
--- a/tcl/board/atmel_samg55_xplained_pro.cfg
+++ b/tcl/board/atmel_samg55_xplained_pro.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Atmel SAMG55 Xplained Pro evaluation kit.
 # http://www.atmel.com/tools/ATSAMG55-XPRO.aspx
diff --git a/tcl/board/atmel_saml21_xplained_pro.cfg b/tcl/board/atmel_saml21_xplained_pro.cfg
index 054bda4da..8e62eb295 100644
--- a/tcl/board/atmel_saml21_xplained_pro.cfg
+++ b/tcl/board/atmel_saml21_xplained_pro.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Atmel SAML21 Xplained Pro evaluation kit.
 #
diff --git a/tcl/board/atmel_samr21_xplained_pro.cfg b/tcl/board/atmel_samr21_xplained_pro.cfg
index 308e2bdb7..cd6d28ecd 100644
--- a/tcl/board/atmel_samr21_xplained_pro.cfg
+++ b/tcl/board/atmel_samr21_xplained_pro.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Atmel SAMR21 Xplained Pro evaluation kit.
 #
diff --git a/tcl/board/atmel_samv71_xplained_ultra.cfg b/tcl/board/atmel_samv71_xplained_ultra.cfg
index 4e0865d99..9368f610d 100644
--- a/tcl/board/atmel_samv71_xplained_ultra.cfg
+++ b/tcl/board/atmel_samv71_xplained_ultra.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Atmel SAMV71 Xplained Ultra evaluation kit.
 # http://www.atmel.com/tools/ATSAMV71-XULT.aspx
diff --git a/tcl/board/avnet_ultrazed-eg.cfg b/tcl/board/avnet_ultrazed-eg.cfg
index 3e4a11a3e..6701fd102 100644
--- a/tcl/board/avnet_ultrazed-eg.cfg
+++ b/tcl/board/avnet_ultrazed-eg.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # AVNET UltraZED EG StarterKit
 # ZynqMP UlraScale-EG plus IO Carrier with on-board digilent smt2
diff --git a/tcl/board/balloon3-cpu.cfg b/tcl/board/balloon3-cpu.cfg
index 468b867b2..3ee840bda 100644
--- a/tcl/board/balloon3-cpu.cfg
+++ b/tcl/board/balloon3-cpu.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Config for balloon3 board, cpu JTAG port. http://balloonboard.org/
 # The board has separate JTAG ports for cpu and CPLD/FPGA devices
 # Chaining is done on IO interfaces if desired.
diff --git a/tcl/board/bcm28155_ap.cfg b/tcl/board/bcm28155_ap.cfg
index 5d3d22a3e..99da948ff 100644
--- a/tcl/board/bcm28155_ap.cfg
+++ b/tcl/board/bcm28155_ap.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # BCM28155_AP
 
 adapter speed 20000
diff --git a/tcl/board/bluefield.cfg b/tcl/board/bluefield.cfg
index 3058d48ca..e96a74e0e 100644
--- a/tcl/board/bluefield.cfg
+++ b/tcl/board/bluefield.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Board configuration for BlueField SoC.
 #
diff --git a/tcl/board/bt-homehubv1.cfg b/tcl/board/bt-homehubv1.cfg
index c50c7d2b6..bbb6fa436 100644
--- a/tcl/board/bt-homehubv1.cfg
+++ b/tcl/board/bt-homehubv1.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # BT HomeHub v1
 #
diff --git a/tcl/board/colibri.cfg b/tcl/board/colibri.cfg
index 0f30afd09..b44985d9d 100644
--- a/tcl/board/colibri.cfg
+++ b/tcl/board/colibri.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Toradex Colibri PXA270
 source [find target/pxa270.cfg]
 reset_config trst_and_srst srst_push_pull
diff --git a/tcl/board/crossbow_tech_imote2.cfg b/tcl/board/crossbow_tech_imote2.cfg
index 277c353a1..07ce8c727 100644
--- a/tcl/board/crossbow_tech_imote2.cfg
+++ b/tcl/board/crossbow_tech_imote2.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Crossbow Technology iMote2
 
 set  CHIPNAME imote2
diff --git a/tcl/board/csb337.cfg b/tcl/board/csb337.cfg
index a9d013929..f75abbe0e 100644
--- a/tcl/board/csb337.cfg
+++ b/tcl/board/csb337.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Cogent CSB337
 #   http://cogcomp.com/csb_csb337.htm
 
diff --git a/tcl/board/csb732.cfg b/tcl/board/csb732.cfg
index 35e397ff2..6df17500c 100644
--- a/tcl/board/csb732.cfg
+++ b/tcl/board/csb732.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # The Cogent CSB732 board has a single i.MX35 chip
 source [find target/imx35.cfg]
 
diff --git a/tcl/board/da850evm.cfg b/tcl/board/da850evm.cfg
index fbec60921..12de3a7e3 100644
--- a/tcl/board/da850evm.cfg
+++ b/tcl/board/da850evm.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #DA850 EVM board
 # http://focus.ti.com/dsp/docs/thirdparty/catalog/devtoolsproductfolder.tsp?actionPerformed=productFolder&productId=5939
 # http://www.logicpd.com/products/development-kits/zoom-omap-l138-evm-development-kit
diff --git a/tcl/board/digi_connectcore_wi-9c.cfg b/tcl/board/digi_connectcore_wi-9c.cfg
index 43ad1c90e..0ff47428a 100644
--- a/tcl/board/digi_connectcore_wi-9c.cfg
+++ b/tcl/board/digi_connectcore_wi-9c.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 ######################################
 # Target: DIGI ConnectCore Wi-9C
 ######################################
diff --git a/tcl/board/digilent_analog_discovery.cfg b/tcl/board/digilent_analog_discovery.cfg
index 64cdacfa8..1bc239b63 100644
--- a/tcl/board/digilent_analog_discovery.cfg
+++ b/tcl/board/digilent_analog_discovery.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Digilent Analog Discovery
 #
diff --git a/tcl/board/digilent_atlys.cfg b/tcl/board/digilent_atlys.cfg
index 3eb6219fd..568253b98 100644
--- a/tcl/board/digilent_atlys.cfg
+++ b/tcl/board/digilent_atlys.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # http://digilentinc.com/atlys/
 #
 # The Digilent Atlys normally requires proprietary tools to program and will
diff --git a/tcl/board/digilent_zedboard.cfg b/tcl/board/digilent_zedboard.cfg
index 08d1a612f..010e8c6f3 100644
--- a/tcl/board/digilent_zedboard.cfg
+++ b/tcl/board/digilent_zedboard.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Digilent Zedboard Rev.C, Rev.D with Xilinx Zynq chip
 #
diff --git a/tcl/board/diolan_lpc4350-db1.cfg b/tcl/board/diolan_lpc4350-db1.cfg
index bd48d9ba0..c55621df0 100644
--- a/tcl/board/diolan_lpc4350-db1.cfg
+++ b/tcl/board/diolan_lpc4350-db1.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Diolan LPC-4350-DB1 development board
 #
diff --git a/tcl/board/diolan_lpc4357-db1.cfg b/tcl/board/diolan_lpc4357-db1.cfg
index d24cfd02c..155328ad5 100644
--- a/tcl/board/diolan_lpc4357-db1.cfg
+++ b/tcl/board/diolan_lpc4357-db1.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Diolan LPC-4357-DB1 development board
 #
diff --git a/tcl/board/dk-tm4c129.cfg b/tcl/board/dk-tm4c129.cfg
index 2c7de290d..27bd432ce 100644
--- a/tcl/board/dk-tm4c129.cfg
+++ b/tcl/board/dk-tm4c129.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 echo "WARNING: board/dk-tm4c129.cfg is deprecated, please switch to board/ti_dk-tm4c129.cfg"
 
 source [find board/ti_dk-tm4c129.cfg]
diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg
index bf5659ccc..0dbffa839 100644
--- a/tcl/board/dm355evm.cfg
+++ b/tcl/board/dm355evm.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # DM355 EVM board
 #   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
 #   http://c6000.spectrumdigital.com/evmdm355/
diff --git a/tcl/board/dm365evm.cfg b/tcl/board/dm365evm.cfg
index 8c7f8c0a6..15db24c20 100644
--- a/tcl/board/dm365evm.cfg
+++ b/tcl/board/dm365evm.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # DM365 EVM board -- Beta
 #   http://focus.ti.com/docs/toolsw/folders/print/tmdxevm365.html
 #   http://support.spectrumdigital.com/boards/evmdm365
diff --git a/tcl/board/dm6446evm.cfg b/tcl/board/dm6446evm.cfg
index 0d2f6a4d2..1236b8622 100644
--- a/tcl/board/dm6446evm.cfg
+++ b/tcl/board/dm6446evm.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # DM6446 EVM board
 #   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm6446.html
 #   http://c6000.spectrumdigital.com/davincievm/
diff --git a/tcl/board/dp_busblaster_v3.cfg b/tcl/board/dp_busblaster_v3.cfg
index b94b43a0b..55996176f 100644
--- a/tcl/board/dp_busblaster_v3.cfg
+++ b/tcl/board/dp_busblaster_v3.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Dangerous Prototypes - Bus Blaster
 #
diff --git a/tcl/board/dptechnics_dpt-board-v1.cfg b/tcl/board/dptechnics_dpt-board-v1.cfg
index 21470b02b..3ab2c684d 100644
--- a/tcl/board/dptechnics_dpt-board-v1.cfg
+++ b/tcl/board/dptechnics_dpt-board-v1.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Product page:
 # https://www.dptechnics.com/en/products/dpt-board-v1.html
 #
diff --git a/tcl/board/efikamx.cfg b/tcl/board/efikamx.cfg
index 007b312be..90835434a 100644
--- a/tcl/board/efikamx.cfg
+++ b/tcl/board/efikamx.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Genesi USA EfikaMX
 #  http://www.genesi-usa.com/products/efika
 
diff --git a/tcl/board/efm32.cfg b/tcl/board/efm32.cfg
index adbdda72e..0ffab04fd 100644
--- a/tcl/board/efm32.cfg
+++ b/tcl/board/efm32.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Configuration for EFM32 boards with on-board SEGGER J-Link
 #
 # Tested with Tiny, Giant and Zero Gecko Starter Kit.
diff --git a/tcl/board/eir.cfg b/tcl/board/eir.cfg
index 67758b81e..d6342499f 100644
--- a/tcl/board/eir.cfg
+++ b/tcl/board/eir.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Elector Internet Radio board
 # http://www.ethernut.de/en/hardware/eir/index.html
 
diff --git a/tcl/board/ek-lm3s1968.cfg b/tcl/board/ek-lm3s1968.cfg
index bbb04baa6..c794a17a0 100644
--- a/tcl/board/ek-lm3s1968.cfg
+++ b/tcl/board/ek-lm3s1968.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # TI/Luminary Stellaris LM3S1968 Evaluation Kits
 #
diff --git a/tcl/board/ek-lm3s3748.cfg b/tcl/board/ek-lm3s3748.cfg
index 36ecfcd32..705cb64ce 100644
--- a/tcl/board/ek-lm3s3748.cfg
+++ b/tcl/board/ek-lm3s3748.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # TI/Luminary Stellaris lm3s3748 Evaluation Kits
 #
diff --git a/tcl/board/ek-lm3s6965.cfg b/tcl/board/ek-lm3s6965.cfg
index c7696690d..ee4e15f8a 100644
--- a/tcl/board/ek-lm3s6965.cfg
+++ b/tcl/board/ek-lm3s6965.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # TI/Luminary Stellaris LM3S6965 Evaluation Kits
 #
diff --git a/tcl/board/ek-lm3s811-revb.cfg b/tcl/board/ek-lm3s811-revb.cfg
index 8729f1596..f968eece5 100644
--- a/tcl/board/ek-lm3s811-revb.cfg
+++ b/tcl/board/ek-lm3s811-revb.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # TI/Luminary Stellaris LM3S811 Evaluation Kits (rev B and earlier)
 #
diff --git a/tcl/board/ek-lm3s811.cfg b/tcl/board/ek-lm3s811.cfg
index d7fe243e6..0cf36c284 100644
--- a/tcl/board/ek-lm3s811.cfg
+++ b/tcl/board/ek-lm3s811.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # TI/Luminary Stellaris LM3S811 Evaluation Kits
 #
diff --git a/tcl/board/ek-lm3s8962.cfg b/tcl/board/ek-lm3s8962.cfg
index d02ce449a..71a1b1090 100644
--- a/tcl/board/ek-lm3s8962.cfg
+++ b/tcl/board/ek-lm3s8962.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # TI/Luminary Stellaris LM3S8962 Evaluation Kits
 #
diff --git a/tcl/board/ek-lm3s9b9x.cfg b/tcl/board/ek-lm3s9b9x.cfg
index 6dd7b31a8..289a2cc09 100644
--- a/tcl/board/ek-lm3s9b9x.cfg
+++ b/tcl/board/ek-lm3s9b9x.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # TI/Luminary Stellaris LM3S9B9x Evaluation Kits
 #
diff --git a/tcl/board/ek-lm3s9d92.cfg b/tcl/board/ek-lm3s9d92.cfg
index a0253d646..08bbbdb58 100644
--- a/tcl/board/ek-lm3s9d92.cfg
+++ b/tcl/board/ek-lm3s9d92.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # TI/Luminary Stellaris LM3S9D92 Evaluation Kits
 #
diff --git a/tcl/board/ek-lm4f120xl.cfg b/tcl/board/ek-lm4f120xl.cfg
index b2ebfa8cf..db8b2010b 100644
--- a/tcl/board/ek-lm4f120xl.cfg
+++ b/tcl/board/ek-lm4f120xl.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # TI Stellaris Launchpad ek-lm4f120xl Evaluation Kits
 #
diff --git a/tcl/board/ek-lm4f232.cfg b/tcl/board/ek-lm4f232.cfg
index 2e3fc7ca1..89b2c3ce8 100644
--- a/tcl/board/ek-lm4f232.cfg
+++ b/tcl/board/ek-lm4f232.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # TI Stellaris LM4F232 Evaluation Kits
 #
diff --git a/tcl/board/ek-tm4c123gxl.cfg b/tcl/board/ek-tm4c123gxl.cfg
index 3e497ba19..d569e58cd 100644
--- a/tcl/board/ek-tm4c123gxl.cfg
+++ b/tcl/board/ek-tm4c123gxl.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 echo "WARNING: board/ek-tm4c123gxl.cfg is deprecated, please switch to board/ti_ek-tm4c123gxl.cfg"
 
 source [find board/ti_ek-tm4c123gxl.cfg]
diff --git a/tcl/board/ek-tm4c1294xl.cfg b/tcl/board/ek-tm4c1294xl.cfg
index 676386680..5c1167451 100644
--- a/tcl/board/ek-tm4c1294xl.cfg
+++ b/tcl/board/ek-tm4c1294xl.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 echo "WARNING: board/ek-tm4c1294xl.cfg is deprecated, please switch to board/ti_ek-tm4c1294xl.cfg"
 
 source [find board/ti_ek-tm4c1294xl.cfg]
diff --git a/tcl/board/embedded-artists_lpc2478-32.cfg b/tcl/board/embedded-artists_lpc2478-32.cfg
index a73d83263..ef6106080 100644
--- a/tcl/board/embedded-artists_lpc2478-32.cfg
+++ b/tcl/board/embedded-artists_lpc2478-32.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Embedded Artists eval board for LPC2478
 # http://www.embeddedartists.com/
 
diff --git a/tcl/board/emcraft_imx8m-som-bsb.cfg b/tcl/board/emcraft_imx8m-som-bsb.cfg
index 248c0d400..7b9f7b1cc 100644
--- a/tcl/board/emcraft_imx8m-som-bsb.cfg
+++ b/tcl/board/emcraft_imx8m-som-bsb.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # configuration file for Emcraft IMX8M-SOM-BSB
 #
diff --git a/tcl/board/emcraft_twr-vf6-som-bsb.cfg b/tcl/board/emcraft_twr-vf6-som-bsb.cfg
index 3818b6793..57efa8f96 100644
--- a/tcl/board/emcraft_twr-vf6-som-bsb.cfg
+++ b/tcl/board/emcraft_twr-vf6-som-bsb.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # EmCraft Systems TWR-VF6-SOM-BSB
 #
diff --git a/tcl/board/emcraft_vf6-som.cfg b/tcl/board/emcraft_vf6-som.cfg
index 558651683..0a6f0f88d 100644
--- a/tcl/board/emcraft_vf6-som.cfg
+++ b/tcl/board/emcraft_vf6-som.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # EmCraft Systems Vybrid VF6 SOM
 #
diff --git a/tcl/board/ethernut3.cfg b/tcl/board/ethernut3.cfg
index 72fc5ade3..384db1d23 100644
--- a/tcl/board/ethernut3.cfg
+++ b/tcl/board/ethernut3.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Ethernut 3 board configuration file
 #
diff --git a/tcl/board/frdm-kl25z.cfg b/tcl/board/frdm-kl25z.cfg
index 89ee32dee..68dc48d49 100644
--- a/tcl/board/frdm-kl25z.cfg
+++ b/tcl/board/frdm-kl25z.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # This is an Freescale Freedom eval board with a single MKL25Z128VLK4 chip.
 # http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=FRDM-KL25Z
 #
diff --git a/tcl/board/frdm-kl46z.cfg b/tcl/board/frdm-kl46z.cfg
index eee4d8ead..3fb7205d7 100644
--- a/tcl/board/frdm-kl46z.cfg
+++ b/tcl/board/frdm-kl46z.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # This is an Freescale Freedom eval board with a single MKL46Z256VLL4 chip.
 # http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=FRDM-KL46Z
 #
diff --git a/tcl/board/fsl_imx6q_sabresd.cfg b/tcl/board/fsl_imx6q_sabresd.cfg
index cf34cd16d..faeeafb1f 100644
--- a/tcl/board/fsl_imx6q_sabresd.cfg
+++ b/tcl/board/fsl_imx6q_sabresd.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Board configuration file for the Freescale IMX6Q Sabre SD EVM
 #
diff --git a/tcl/board/glyn_tonga2.cfg b/tcl/board/glyn_tonga2.cfg
index f48702ca6..d847bec8a 100644
--- a/tcl/board/glyn_tonga2.cfg
+++ b/tcl/board/glyn_tonga2.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Glyn Tonga2 SO-DIMM CPU module (Toshiba TMPA900CMXBG, ARM9)
 #
diff --git a/tcl/board/gti/espressobin.cfg b/tcl/board/gti/espressobin.cfg
index 20d0452fd..d1492dfd8 100644
--- a/tcl/board/gti/espressobin.cfg
+++ b/tcl/board/gti/espressobin.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # config for ESPRESSObin from
 # Globalscale Technologies Inc.
 
diff --git a/tcl/board/gumstix-aerocore.cfg b/tcl/board/gumstix-aerocore.cfg
index 565df4cf8..ddadc88c0 100644
--- a/tcl/board/gumstix-aerocore.cfg
+++ b/tcl/board/gumstix-aerocore.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # JTAG for the STM32F4x chip used on the Gumstix AeroCore is available on
 # the first interface of a Quad FTDI chip.  nTRST is bit 4.
 adapter driver ftdi
diff --git a/tcl/board/hammer.cfg b/tcl/board/hammer.cfg
index ea3da8123..79d58ae19 100644
--- a/tcl/board/hammer.cfg
+++ b/tcl/board/hammer.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Target Configuration for the TinCanTools S3C2410 Based Hammer Module
 # http://www.tincantools.com
 
diff --git a/tcl/board/hilscher_nxdb500sys.cfg b/tcl/board/hilscher_nxdb500sys.cfg
index 20fa3ea03..68e1cdaf2 100644
--- a/tcl/board/hilscher_nxdb500sys.cfg
+++ b/tcl/board/hilscher_nxdb500sys.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 ################################################################################
 # Author: Michael Trensch (MTr...@go...)
 ################################################################################
diff --git a/tcl/board/hilscher_nxeb500hmi.cfg b/tcl/board/hilscher_nxeb500hmi.cfg
index a51fa03bc..a81436584 100644
--- a/tcl/board/hilscher_nxeb500hmi.cfg
+++ b/tcl/board/hilscher_nxeb500hmi.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 ################################################################################
 # Author: Michael Trensch (MTr...@go...)
 ################################################################################
diff --git a/tcl/board/hilscher_nxhx10.cfg b/tcl/board/hilscher_nxhx10.cfg
index 6e2eba79e..e116a6cc3 100644
--- a/tcl/board/hilscher_nxhx10.cfg
+++ b/tcl/board/hilscher_nxhx10.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 ################################################################################
 # Author: Michael Trensch (MTr...@go...)
 ################################################################################
diff --git a/tcl/board/hilscher_nxhx50.cfg b/tcl/board/hilscher_nxhx50.cfg
index 0867f2ed6..8aef6ca38 100644
--- a/tcl/board/hilscher_nxhx50.cfg
+++ b/tcl/board/hilscher_nxhx50.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 ################################################################################
 # Author: Michael Trensch (MTr...@go...)
 ################################################################################
diff --git a/tcl/board/hilscher_nxhx500.cfg b/tcl/board/hilscher_nxhx500.cfg
index 2ba030ec1..9ddf65790 100644
--- a/tcl/board/hilscher_nxhx500.cfg
+++ b/tcl/board/hilscher_nxhx500.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 ################################################################################
 # Author: Michael Trensch (MTr...@go...)
 ################################################################################
diff --git a/tcl/board/hilscher_nxsb100.cfg b/tcl/board/hilscher_nxsb100.cfg
index c332beec0..b59ea177a 100644
--- a/tcl/board/hilscher_nxsb100.cfg
+++ b/tcl/board/hilscher_nxsb100.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 ################################################################################
 # Author: Michael Trensch (MTr...@go...)
 ################################################################################
diff --git a/tcl/board/hitex_lpc1768stick.cfg b/tcl/board/hitex_lpc1768stick.cfg
index ac176cad7..52cf370c9 100644
--- a/tcl/board/hitex_lpc1768stick.cfg
+++ b/tcl/board/hitex_lpc1768stick.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Hitex LPC1768 Stick
 #
 # http://www.hitex.com/?id=1602
diff --git a/tcl/board/hitex_lpc2929.cfg b/tcl/board/hitex_lpc2929.cfg
index 826830669..35007c065 100644
--- a/tcl/board/hitex_lpc2929.cfg
+++ b/tcl/board/hitex_lpc2929.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Hitex eval board for LPC2929/LPC2939
 # http://www.hitex.com/
 
diff --git a/tcl/board/hitex_stm32-performancestick.cfg b/tcl/board/hitex_stm32-performancestick.cfg
index 74dc5839a..bab59648d 100644
--- a/tcl/board/hitex_stm32-performancestick.cfg
+++ b/tcl/board/hitex_stm32-performancestick.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Hitex stm32 performance stick
 
 reset_config trst_and_srst
diff --git a/tcl/board/hitex_str9-comstick.cfg b/tcl/board/hitex_str9-comstick.cfg
index 3b9225213..a50804690 100644
--- a/tcl/board/hitex_str9-comstick.cfg
+++ b/tcl/board/hitex_str9-comstick.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Hitex STR9-comStick
 # http://www.hitex.com/index.php?id=383
 # This works for the STR9-comStick revisions STR912CS-A1 and STR912CS-A2.
diff --git a/tcl/board/iar_lpc1768.cfg b/tcl/board/iar_lpc1768.cfg
index 38ffc3582..d8d669e98 100644
--- a/tcl/board/iar_lpc1768.cfg
+++ b/tcl/board/iar_lpc1768.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Board from IAR KickStart Kit for LPC1768
 # See www.iar.com and also
 # http://www.olimex.com/dev/lpc-1766stk.html
diff --git a/tcl/board/iar_str912_sk.cfg b/tcl/board/iar_str912_sk.cfg
index 54f517b73..d94c0ce5b 100644
--- a/tcl/board/iar_str912_sk.cfg
+++ b/tcl/board/iar_str912_sk.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # The IAR str912-sk evaluation kick start board has an str912
 
 source [find target/str912.cfg]
diff --git a/tcl/board/icnova_imx53_sodimm.cfg b/tcl/board/icnova_imx53_sodimm.cfg
index 363d7b4f3..c4e8bdec0 100644
--- a/tcl/board/icnova_imx53_sodimm.cfg
+++ b/tcl/board/icnova_imx53_sodimm.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #################################################################################################
 # Author: Benjamin Tietz <ben...@in...>                                        ;#
 # based on work from: Wjatscheslaw Stoljarski (Slawa) <wja...@ki...>   ;#
diff --git a/tcl/board/icnova_sam9g45_sodimm.cfg b/tcl/board/icnova_sam9g45_sodimm.cfg
index 91e0107c2..7efa8c2b5 100644
--- a/tcl/board/icnova_sam9g45_sodimm.cfg
+++ b/tcl/board/icnova_sam9g45_sodimm.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #################################################################################################
 #												                                                #
 # Author: Lars Poeschel (la...@wh...)												#
diff --git a/tcl/board/imx27ads.cfg b/tcl/board/imx27ads.cfg
index e705b1e16..79d3c5135 100644
--- a/tcl/board/imx27ads.cfg
+++ b/tcl/board/imx27ads.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # The IMX27 ADS eval board has a single IMX27 chip
 # Note: tested on IMX27ADS Board REV-2.6 and REV-2.8
 source [find target/imx27.cfg]
diff --git a/tcl/board/imx27lnst.cfg b/tcl/board/imx27lnst.cfg
index ac5a9f3e6..24f6ed8b2 100644
--- a/tcl/board/imx27lnst.cfg
+++ b/tcl/board/imx27lnst.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # The Linuxstamp-mx27 is board has a single IMX27 chip
 # For further info see http://opencircuits.com/Linuxstamp_mx27#OpenOCD
 source [find target/imx27.cfg]
diff --git a/tcl/board/imx28evk.cfg b/tcl/board/imx28evk.cfg
index a85c2ca67..cc13c5185 100644
--- a/tcl/board/imx28evk.cfg
+++ b/tcl/board/imx28evk.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # The IMX28EVK eval board has a IMX28 chip
 # Tested on SCH-26241 Rev D board with Olimex ARM-USB-OCD
 # Date:	201-02-01
diff --git a/tcl/board/imx31pdk.cfg b/tcl/board/imx31pdk.cfg
index 6c196543c..65fa520e4 100644
--- a/tcl/board/imx31pdk.cfg
+++ b/tcl/board/imx31pdk.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # The IMX31PDK eval board has a single IMX31 chip
 source [find target/imx31.cfg]
 source [find target/imx.cfg]
diff --git a/tcl/board/imx35pdk.cfg b/tcl/board/imx35pdk.cfg
index 2a7efaba7..41206c68b 100644
--- a/tcl/board/imx35pdk.cfg
+++ b/tcl/board/imx35pdk.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # The IMX35PDK eval board has a single IMX35 chip
 source [find target/imx35.cfg]
 source [find target/imx.cfg]
diff --git a/tcl/board/imx53-m53evk.cfg b/tcl/board/imx53-m53evk.cfg
index 04f0f9f15..6f9210a26 100644
--- a/tcl/board/imx53-m53evk.cfg
+++ b/tcl/board/imx53-m53evk.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #######################################
 # DENX M53EVK                         #
 # http://www.denx-cs.de/?q=M53EVK     #
diff --git a/tcl/board/imx53loco.cfg b/tcl/board/imx53loco.cfg
index c4d45f0e3..fcc2f4dda 100644
--- a/tcl/board/imx53loco.cfg
+++ b/tcl/board/imx53loco.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 ##################################################################################
 # Author: Wjatscheslaw Stoljarski (Slawa) <wja...@ki...> #
 # Kiwigrid GmbH                                                                  #
diff --git a/tcl/board/imx8mp-evk.cfg b/tcl/board/imx8mp-evk.cfg
index 97a303ac7..898f3b747 100644
--- a/tcl/board/imx8mp-evk.cfg
+++ b/tcl/board/imx8mp-evk.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # configuration file for NXP MC-IMX8MP-EVK
 #
diff --git a/tcl/board/insignal_arndale.cfg b/tcl/board/insignal_arndale.cfg
index 09a7223f0..c7c28b3dc 100644
--- a/tcl/board/insignal_arndale.cfg
+++ b/tcl/board/insignal_arndale.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # InSignal Arndale board
 #
diff --git a/tcl/board/kasli.cfg b/tcl/board/kasli.cfg
index 7cfdcf20e..d85e1ca15 100644
--- a/tcl/board/kasli.cfg
+++ b/tcl/board/kasli.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 adapter driver ftdi
 ftdi device_desc "Quad RS232-HS"
 ftdi vid_pid 0x0403 0x6011
diff --git a/tcl/board/kc100.cfg b/tcl/board/kc100.cfg
index 1d383bef5..2fd6965a5 100644
--- a/tcl/board/kc100.cfg
+++ b/tcl/board/kc100.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Knovative KC-100 cable modem
 
 # TNETC4401PYP, 208-QFP U3
diff --git a/tcl/board/kc705.cfg b/tcl/board/kc705.cfg
index 51ea14d46..fad9fff4d 100644
--- a/tcl/board/kc705.cfg
+++ b/tcl/board/kc705.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # http://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html
 
 source [find interface/ftdi/digilent-hs1.cfg]
diff --git a/tcl/board/kcu105.cfg b/tcl/board/kcu105.cfg
index e2b68ca75..1510a0616 100644
--- a/tcl/board/kcu105.cfg
+++ b/tcl/board/kcu105.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # xilinx ultrascale
 # http://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
 
diff --git a/tcl/board/keil_mcb1700.cfg b/tcl/board/keil_mcb1700.cfg
index 05f12dfba..6efbd6352 100644
--- a/tcl/board/keil_mcb1700.cfg
+++ b/tcl/board/keil_mcb1700.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Keil MCB1700 eval board
 #
diff --git a/tcl/board/keil_mcb2140.cfg b/tcl/board/keil_mcb2140.cfg
index bb41a2ab5..bb1d10bd0 100644
--- a/tcl/board/keil_mcb2140.cfg
+++ b/tcl/board/keil_mcb2140.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Keil MCB2140 eval board
 #
diff --git a/tcl/board/kindle2.cfg b/tcl/board/kindle2.cfg
index 71dca741c..8c032cb3a 100644
--- a/tcl/board/kindle2.cfg
+++ b/tcl/board/kindle2.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Board configuration file for Amazon Kindle Model No. D00701 and D00801
 # AKA Kindle 2nd generation and Kindle DX
 # using a Freescale MCIMX31LDVKN5D i.MX31 processor
diff --git a/tcl/board/kwikstik.cfg b/tcl/board/kwikstik.cfg
index f936d6e92..ade0c913b 100644
--- a/tcl/board/kwikstik.cfg
+++ b/tcl/board/kwikstik.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Freescale KwikStik development board
 #
diff --git a/tcl/board/la_fonera-fon2200.cfg b/tcl/board/la_fonera-fon2200.cfg
index f46b04200..b0b2966af 100644
--- a/tcl/board/la_fonera-fon2200.cfg
+++ b/tcl/board/la_fonera-fon2200.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 source [find target/atheros_ar2315.cfg]
 
 reset_config trst_and_srst
diff --git a/tcl/board/lemaker_hikey.cfg b/tcl/board/lemaker_hikey.cfg
index 325b6fdda..fc044359c 100644
--- a/tcl/board/lemaker_hikey.cfg
+++ b/tcl/board/lemaker_hikey.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # board configuration for LeMaker Hikey
 #
diff --git a/tcl/board/linksys-wag200g.cfg b/tcl/board/linksys-wag200g.cfg
index aa4887f94..26900a7d7 100644
--- a/tcl/board/linksys-wag200g.cfg
+++ b/tcl/board/linksys-wag200g.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Linksys WAG200G Router
 #
diff --git a/tcl/board/linksys-wrt54gl.cfg b/tcl/board/linksys-wrt54gl.cfg
index ffe53ffbb..58dfec398 100644
--- a/tcl/board/linksys-wrt54gl.cfg
+++ b/tcl/board/linksys-wrt54gl.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Linksys WRT54GL v1.1
 #
diff --git a/tcl/board/linksys_nslu2.cfg b/tcl/board/linksys_nslu2.cfg
index 0b0f58b84..536f97e23 100644
--- a/tcl/board/linksys_nslu2.cfg
+++ b/tcl/board/linksys_nslu2.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # This is for the LinkSys (CISCO) NSLU2 board
 # It is an Intel XSCALE IXP420 CPU.
 
diff --git a/tcl/board/lisa-l.cfg b/tcl/board/lisa-l.cfg
index 73f51a26d..1607fb862 100644
--- a/tcl/board/lisa-l.cfg
+++ b/tcl/board/lisa-l.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # the Lost Illusions Serendipitous Autopilot
 # http://paparazzi.enac.fr/wiki/Lisa
 
diff --git a/tcl/board/logicpd_imx27.cfg b/tcl/board/logicpd_imx27.cfg
index da0b46223..8365d4fdb 100644
--- a/tcl/board/logicpd_imx27.cfg
+++ b/tcl/board/logicpd_imx27.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # The LogicPD Eval IMX27 eval board has a single IMX27 chip
 source [find target/imx27.cfg]
 
diff --git a/tcl/board/lpc1850_spifi_generic.cfg b/tcl/board/lpc1850_spifi_generic.cfg
index bff4af605..167b624b5 100644
--- a/tcl/board/lpc1850_spifi_generic.cfg
+++ b/tcl/board/lpc1850_spifi_generic.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Generic LPC1850 board w/ SPIFI flash.
 # This config file is intended as an example of how to
diff --git a/tcl/board/lpc4350_spifi_generic.cfg b/tcl/board/lpc4350_spifi_generic.cfg
index b363f1eff..8a017ec7d 100644
--- a/tcl/board/lpc4350_spifi_generic.cfg
+++ b/tcl/board/lpc4350_spifi_generic.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Generic LPC4350 board w/ SPIFI flash.
 # This config file is intended as an example of how to
diff --git a/tcl/board/lubbock.cfg b/tcl/board/lubbock.cfg
index d803e6fb2..e4de385a4 100644
--- a/tcl/board/lubbock.cfg
+++ b/tcl/board/lubbock.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Intel "Lubbock" Development Board with PXA255 (dbpxa255)
 #  Obsolete; this was Intel's original PXA255 development system
 #  Board also had CPU cards for SA1100, PXA210, PXA250, and more.
diff --git a/tcl/board/marsohod.cfg b/tcl/board/marsohod.cfg
index b1393a914..2be8391af 100644
--- a/tcl/board/marsohod.cfg
+++ b/tcl/board/marsohod.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Marsohod CPLD Development and Education board
 #
diff --git a/tcl/board/marsohod2.cfg b/tcl/board/marsohod2.cfg
index 31819a2f9..957510054 100644
--- a/tcl/board/marsohod2.cfg
+++ b/tcl/board/marsohod2.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Marsohod2 FPGA Development and Education board
 #
diff --git a/tcl/board/marsohod3.cfg b/tcl/board/marsohod3.cfg
index fa00706d3..b4f2d3017 100644
--- a/tcl/board/marsohod3.cfg
+++ b/tcl/board/marsohod3.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Marsohod3 FPGA Development and Education board
 #
diff --git a/tcl/board/mbed-lpc11u24.cfg b/tcl/board/mbed-lpc11u24.cfg
index b1ec2a519..9f5be884c 100644
--- a/tcl/board/mbed-lpc11u24.cfg
+++ b/tcl/board/mbed-lpc11u24.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # This is an mbed eval board with a single NXP LPC11U24 chip.
 # http://mbed.org/handbook/mbed-NXP-LPC11U24
 #
diff --git a/tcl/board/mbed-lpc1768.cfg b/tcl/board/mbed-lpc1768.cfg
index 67f834011..62b0911b7 100644
--- a/tcl/board/mbed-lpc1768.cfg
+++ b/tcl/board/mbed-lpc1768.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # This is an mbed eval board with a single NXP LPC1768 chip.
 # http://mbed.org/handbook/mbed-NXP-LPC1768
 #
diff --git a/tcl/board/mcb1700.cfg b/tcl/board/mcb1700.cfg
index a5e19024a..8ab6e88c2 100644
--- a/tcl/board/mcb1700.cfg
+++ b/tcl/board/mcb1700.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Keil MCB1700 PCB with 1768
 #
 # Reset init script sets it to 100MHz
diff --git a/tcl/board/microchip_explorer16.cfg b/tcl/board/microchip_explorer16.cfg
index 7c036c665..6b528d62a 100644
--- a/tcl/board/microchip_explorer16.cfg
+++ b/tcl/board/microchip_explorer16.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Microchip Explorer 16 with PIC32MX360F512L PIM module.
 # http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en024858
 
diff --git a/tcl/board/microchip_same54_xplained_pro.cfg b/tcl/board/microchip_same54_xplained_pro.cfg
index 7482de47f..358816598 100644
--- a/tcl/board/microchip_same54_xplained_pro.cfg
+++ b/tcl/board/microchip_same54_xplained_pro.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Microchip (former Atmel) SAM E54 Xplained Pro evaluation kit.
 # http://www.microchip.com/developmenttools/productdetails.aspx?partno=atsame54-xpro
diff --git a/tcl/board/microchip_saml11_xplained_pro.cfg b/tcl/board/microchip_saml11_xplained_pro.cfg
index 2ab61118f..c2fcd65e0 100644
--- a/tcl/board/microchip_saml11_xplained_pro.cfg
+++ b/tcl/board/microchip_saml11_xplained_pro.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Microchip (formerly Atmel) SAM L11 Xplained Pro Evaluation Kit.
 # https://www.microchip.com/DevelopmentTools/ProductDetails/dm320205
diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg
index 3d01b38a2..790b4c7c8 100644
--- a/tcl/board/mini2440.cfg
+++ b/tcl/board/mini2440.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #-------------------------------------------------------------------------
 # Mini2440 Samsung s3c2440A Processor with 64MB DRAM, 64MB NAND, 2 MB N0R
 # NOTE: Configured for NAND boot (switch S2 in NANDBOOT)
diff --git a/tcl/board/mini6410.cfg b/tcl/board/mini6410.cfg
index 2cee93935..18f9e8d25 100644
--- a/tcl/board/mini6410.cfg
+++ b/tcl/board/mini6410.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Target configuration for the Samsung s3c6410 system on chip
 # Tested on a tiny6410
 # Processor       : ARM1176
diff --git a/tcl/board/minispartan6.cfg b/tcl/board/minispartan6.cfg
index 3de9e99d4..011cc542c 100644
--- a/tcl/board/minispartan6.cfg
+++ b/tcl/board/minispartan6.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # https://www.scarabhardware.com/minispartan6/
 
 source [find interface/ftdi/minispartan6.cfg]
diff --git a/tcl/board/nds32_xc5.cfg b/tcl/board/nds32_xc5.cfg
index 7d86996bd..82a117e71 100644
--- a/tcl/board/nds32_xc5.cfg
+++ b/tcl/board/nds32_xc5.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 set _CPUTAPID 0x1000063d
 set _CHIPNAME nds32
 source [find target/nds32v3.cfg]
diff --git a/tcl/board/netgear-dg834v3.cfg b/tcl/board/netgear-dg834v3.cfg
index 48d23daf9..a9938889c 100644
--- a/tcl/board/netgear-dg834v3.cfg
+++ b/tcl/board/netgear-dg834v3.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Netgear DG834v3 Router
 # Internal 4Kb RAM (@0x80000000)
diff --git a/tcl/board/netgear-wg102.cfg b/tcl/board/netgear-wg102.cfg
index 232d2e423..15f9c118a 100644
--- a/tcl/board/netgear-wg102.cfg
+++ b/tcl/board/netgear-wg102.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 source [find target/atheros_ar2313.cfg]
 
 reset_config trst_and_srst
diff --git a/tcl/board/nordic_nrf51822_mkit.cfg b/tcl/board/nordic_nrf51822_mkit.cfg
index aa6161f5d..266d71070 100644
--- a/tcl/board/nordic_nrf51822_mkit.cfg
+++ b/tcl/board/nordic_nrf51822_mkit.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Nordic Semiconductor PCA10024 board (aka nRF51822-mKIT)
 #
diff --git a/tcl/board/nordic_nrf51_dk.cfg b/tcl/board/nordic_nrf51_dk.cfg
index 96f5471a5..7ddae2d43 100644
--- a/tcl/board/nordic_nrf51_dk.cfg
+++ b/tcl/board/nordic_nrf51_dk.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Nordic Semiconductor NRF51 Development Kit (nRF6824)
 #
diff --git a/tcl/board/nordic_nrf52_dk.cfg b/tcl/board/nordic_nrf52_dk.cfg
index 9f528669c..7366bf94a 100644
--- a/tcl/board/nordic_nrf52_dk.cfg
+++ b/tcl/board/nordic_nrf52_dk.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Nordic Semiconductor NRF52 Development Kit (nRF52832)
 #
diff --git a/tcl/board/nordic_nrf52_ftx232.cfg b/tcl/board/nordic_nrf52_ftx232.cfg
index 938efedae..c3c69a89a 100644
--- a/tcl/board/nordic_nrf52_ftx232.cfg
+++ b/tcl/board/nordic_nrf52_ftx232.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # nordic module NRF52 (nRF52832/52840) attached to an adafruit ft232h module
 # or any FT232H/FT2232H/FT4232H based board/module
diff --git a/tcl/board/novena-internal-fpga.cfg b/tcl/board/novena-internal-fpga.cfg
index 780586223..c36938c35 100644
--- a/tcl/board/novena-internal-fpga.cfg
+++ b/tcl/board/novena-internal-fpga.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Novena open hardware and F/OSS-friendly computing platform
 #
diff --git a/tcl/board/numato_mimas_a7.cfg b/tcl/board/numato_mimas_a7.cfg
index 12df8913d..82d6a561b 100644
--- a/tcl/board/numato_mimas_a7.cfg
+++ b/tcl/board/numato_mimas_a7.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Numato Mimas A7 - Artix 7 FPGA Board
 #
diff --git a/tcl/board/numato_opsis.cfg b/tcl/board/numato_opsis.cfg
index e54a4eca8..ea07ff3e9 100644
--- a/tcl/board/numato_opsis.cfg
+++ b/tcl/board/numato_opsis.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # http://opsis.hdmi2usb.tv
 #
 # The Numato Opsis is an FPGA based, open video platform.
diff --git a/tcl/board/nxp_frdm-ls1012a.cfg b/tcl/board/nxp_frdm-ls1012a.cfg
index 3973b3cdf..17a50c9a6 100644
--- a/tcl/board/nxp_frdm-ls1012a.cfg
+++ b/tcl/board/nxp_frdm-ls1012a.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # NXP FRDM-LS1012A (Freedom)
 #
diff --git a/tcl/board/nxp_imx7sabre.cfg b/tcl/board/nxp_imx7sabre.cfg
index 789fc5b62..9b0c743af 100644
--- a/tcl/board/nxp_imx7sabre.cfg
+++ b/tcl/board/nxp_imx7sabre.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # NXP IMX7SABRE board
 # use on-board JTAG header
 transport select jtag
diff --git a/tcl/board/nxp_lpc-link2.cfg b/tcl/board/nxp_lpc-link2.cfg
index 593fa599a..52f13fa80 100644
--- a/tcl/board/nxp_lpc-link2.cfg
+++ b/tcl/board/nxp_lpc-link2.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # NXP LPC-Link2
 #
diff --git a/tcl/board/nxp_mcimx8m-evk.cfg b/tcl/board/nxp_mcimx8m-evk.cfg
index dd9bd53ac..bcd0f67c2 100644
--- a/tcl/board/nxp_mcimx8m-evk.cfg
+++ b/tcl/board/nxp_mcimx8m-evk.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # configuration file for NXP MC-IMX8M-EVK
 #
diff --git a/tcl/board/olimex_LPC2378STK.cfg b/tcl/board/olimex_LPC2378STK.cfg
index 7e9e58e70..23588aea8 100644
--- a/tcl/board/olimex_LPC2378STK.cfg
+++ b/tcl/board/olimex_LPC2378STK.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #####################################################
 # Olimex LPC2378STK eval board
 #
diff --git a/tcl/board/olimex_lpc_h2148.cfg b/tcl/board/olimex_lpc_h2148.cfg
index d8fb5bef9..96ae40516 100644
--- a/tcl/board/olimex_lpc_h2148.cfg
+++ b/tcl/board/olimex_lpc_h2148.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Olimex LPC-H2148 eval board
 #
diff --git a/tcl/board/olimex_sam7_ex256.cfg b/tcl/board/olimex_sam7_ex256.cfg
index 08ed4c17e..9924f2748 100644
--- a/tcl/board/olimex_sam7_ex256.cfg
+++ b/tcl/board/olimex_sam7_ex256.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Olimex SAM7-EX256 has a single Atmel at91sam7ex256 on it.
 
 source [find target/at91sam7x256.cfg]
diff --git a/tcl/board/olimex_sam7_la2.cfg b/tcl/board/olimex_sam7_la2.cfg
index 038fe67b6..d91432b1a 100644
--- a/tcl/board/olimex_sam7_la2.cfg
+++ b/tcl/board/olimex_sam7_la2.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 source [find target/at91sam7a2.cfg]
 
 # delays needed to get stable reads of cpu state
diff --git a/tcl/board/olimex_sam9_l9260.cfg b/tcl/board/olimex_sam9_l9260.cfg
index 72dce87b1..7491a0ed5 100644
--- a/tcl/board/olimex_sam9_l9260.cfg
+++ b/tcl/board/olimex_sam9_l9260.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 ################################################################################
 # Olimex SAM9-L9260 Development Board
 #
diff --git a/tcl/board/olimex_stm32_h103.cfg b/tcl/board/olimex_stm32_h103.cfg
index ec03034c1..92ca7ae58 100644
--- a/tcl/board/olimex_stm32_h103.cfg
+++ b/tcl/board/olimex_stm32_h103.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Olimex STM32-H103 eval board
 # http://olimex.com/dev/stm32-h103.html
 
diff --git a/tcl/board/olimex_stm32_h107.cfg b/tcl/board/olimex_stm32_h107.cfg
index e54fb4e70..c199cdcf4 100644
--- a/tcl/board/olimex_stm32_h107.cfg
+++ b/tcl/board/olimex_stm32_h107.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Olimex STM32-H107
 #
diff --git a/tcl/board/olimex_stm32_p107.cfg b/tcl/board/olimex_stm32_p107.cfg
index 98c72a6e7..9511030b7 100644
--- a/tcl/board/olimex_stm32_p107.cfg
+++ b/tcl/board/olimex_stm32_p107.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Olimex STM32-P107
 #
diff --git a/tcl/board/omap2420_h4.cfg b/tcl/board/omap2420_h4.cfg
index d789e2531..ec169654f 100644
--- a/tcl/board/omap2420_h4.cfg
+++ b/tcl/board/omap2420_h4.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # OMAP2420 SDP board ("H4")
 
 source [find target/omap2420.cfg]
diff --git a/tcl/board/openrd.cfg b/tcl/board/openrd.cfg
index fda01d129..f6c831770 100644
--- a/tcl/board/openrd.cfg
+++ b/tcl/board/openrd.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Marvell OpenRD
 
 source [find interface/ftdi/openrd.cfg]
diff --git a/tcl/board/or1k_generic.cfg b/tcl/board/or1k_generic.cfg
index 7c1956563..915a0de24 100644
--- a/tcl/board/or1k_generic.cfg
+++ b/tcl/board/or1k_generic.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # If you want to use the VJTAG TAP or the XILINX BSCAN,
 # you must set your FPGA TAP ID here
 
diff --git a/tcl/board/osk5912.cfg b/tcl/board/osk5912.cfg
index f4378f8cf..0759a27ac 100644
--- a/tcl/board/osk5912.cfg
+++ b/tcl/board/osk5912.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # http://omap.spectrumdigital.com/osk5912/
 
 source [find target/omap5912.cfg]
diff --git a/tcl/board/phone_se_j100i.cfg b/tcl/board/phone_se_j100i.cfg
index ec61425ac..70387ee15 100644
--- a/tcl/board/phone_se_j100i.cfg
+++ b/tcl/board/phone_se_j100i.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Sony Ericsson J100I Phone
 #
diff --git a/tcl/board/phytec_lpc3250.cfg b/tcl/board/phytec_lpc3250.cfg
index cee28cdd2..036b16f2b 100644
--- a/tcl/board/phytec_lpc3250.cfg
+++ b/tcl/board/phytec_lpc3250.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 source [find target/lpc3250.cfg]
 
 adapter srst delay 200
diff --git a/tcl/board/pic-p32mx.cfg b/tcl/board/pic-p32mx.cfg
index 661e3d63f..0703220ab 100644
--- a/tcl/board/pic-p32mx.cfg
+++ b/tcl/board/pic-p32mx.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # The Olimex PIC-P32MX has a PIC32MX
 
 set CPUTAPID 0x40916053
diff --git a/tcl/board/pipistrello.cfg b/tcl/board/pipistrello.cfg
index 87193b4a1..17584a0bd 100644
--- a/tcl/board/pipistrello.cfg
+++ b/tcl/board/pipistrello.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # http://pipistrello.saanlima.com/
 
 source [find interface/ftdi/pipistrello.cfg]
diff --git a/tcl/board/propox_mmnet1001.cfg b/tcl/board/propox_mmnet1001.cfg
index 39ae5cbc1..0e126044f 100644
--- a/tcl/board/propox_mmnet1001.cfg
+++ b/tcl/board/propox_mmnet1001.cfg
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
 
 ## Chip:
 set CHIPNAME at91sam9260
diff --git a/tcl/board/pxa255_sst.cfg b/tcl/board/pxa255_sst.cfg
index 2b44a0541..8d00dfe6a 100644
--- a/tcl/board/pxa255_sst.cfg
+++ b/tcl/board/pxa255_sst.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # A PXA255 test board with SST 39LF400A flash
 #
 # At reset the memory map is as follows. Note that
diff --git a/tcl/board/quark_d2000_refboard.cfg b/tcl/board/quark_d2000_refboard.cfg
index a89895d89..3af5735a8 100644
--- a/tcl/board/quark_d2000_refboard.cfg
+++ b/tcl/board/quark_d2000_refboard.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Intel Quark microcontroller D2000 Reference Board (web search for doc num 333...
 
[truncated message content]

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-743-g2c5f263bc

From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:52:44

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  2c5f263bcd61592b6575ed92672d14143bdb9aad (commit)
      from  69ea481e0b3607085cc05cbc5ca41740c9f938f6 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 2c5f263bcd61592b6575ed92672d14143bdb9aad
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jun 12 22:59:55 2022 +0200

    tcl: move SPDX tag as first line
    
    The SPDX tag is aimed at machine handling and it's thus expected
    to be placed in the first line.
    
    Change-Id: I3992856eeb28b333c38d010ef286e22471ede263
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7026
    Tested-by: jenkins

diff --git a/tcl/board/snps_em_sk.cfg b/tcl/board/snps_em_sk.cfg
index 3d9340735..56eed93df 100644
--- a/tcl/board/snps_em_sk.cfg
+++ b/tcl/board/snps_em_sk.cfg
@@ -1,8 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #  Copyright (C) 2014-2016,2020 Synopsys, Inc.
 #  Anton Kolesov <ant...@sy...>
 #  Didin Evgeniy <di...@sy...>
-#
-# SPDX-License-Identifier: GPL-2.0-or-later
 
 #
 # Synopsys DesignWare ARC EM Starter Kit v2.x
diff --git a/tcl/board/snps_em_sk_v1.cfg b/tcl/board/snps_em_sk_v1.cfg
index 0c1539ee5..94aab14ed 100644
--- a/tcl/board/snps_em_sk_v1.cfg
+++ b/tcl/board/snps_em_sk_v1.cfg
@@ -1,8 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #  Copyright (C) 2014-2016,2020 Synopsys, Inc.
 #  Anton Kolesov <ant...@sy...>
 #  Didin Evgeniy <di...@sy...>
-#
-# SPDX-License-Identifier: GPL-2.0-or-later
 
 #
 # Synopsys DesignWare ARC EM Starter Kit v1.0 and v1.1
diff --git a/tcl/board/snps_em_sk_v2.1.cfg b/tcl/board/snps_em_sk_v2.1.cfg
index c1fb232d5..96391df37 100644
--- a/tcl/board/snps_em_sk_v2.1.cfg
+++ b/tcl/board/snps_em_sk_v2.1.cfg
@@ -1,8 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #  Copyright (C) 2014-2016,2020 Synopsys, Inc.
 #  Anton Kolesov <ant...@sy...>
 #  Didin Evgeniy <di...@sy...>
-#
-# SPDX-License-Identifier: GPL-2.0-or-later
 
 #
 # Synopsys DesignWare ARC EM Starter Kit v2.1
diff --git a/tcl/board/snps_em_sk_v2.2.cfg b/tcl/board/snps_em_sk_v2.2.cfg
index 674d9f65c..c1f6a7223 100644
--- a/tcl/board/snps_em_sk_v2.2.cfg
+++ b/tcl/board/snps_em_sk_v2.2.cfg
@@ -1,8 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #  Copyright (C) 2016,2020 Synopsys, Inc.
 #  Anton Kolesov <ant...@sy...>
 #  Didin Evgeniy <di...@sy...>
-#
-# SPDX-License-Identifier: GPL-2.0-or-later
 
 #
 # Synopsys DesignWare ARC EM Starter Kit v2.2
diff --git a/tcl/board/snps_hsdk.cfg b/tcl/board/snps_hsdk.cfg
index a6228f4c1..24022e5a8 100644
--- a/tcl/board/snps_hsdk.cfg
+++ b/tcl/board/snps_hsdk.cfg
@@ -1,8 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #  Copyright (C) 2019, 2020 Synopsys, Inc.
 #  Anton Kolesov <ant...@sy...>
 #  Didin Evgeniy <di...@sy...>
-#
-# SPDX-License-Identifier: GPL-2.0-or-later
 
 #
 # Synopsys DesignWare ARC HSDK Software Development Platform (HS38 cores)
diff --git a/tcl/cpu/arc/common.tcl b/tcl/cpu/arc/common.tcl
index b31e31a34..e0de70bc0 100644
--- a/tcl/cpu/arc/common.tcl
+++ b/tcl/cpu/arc/common.tcl
@@ -1,8 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #  Copyright (C) 2015, 2020 Synopsys, Inc.
 #  Anton Kolesov <ant...@sy...>
 #  Didin Evgeniy <di...@sy...>
-#
-# SPDX-License-Identifier: GPL-2.0-or-later
 
 # Things common to all ARCs
 
diff --git a/tcl/cpu/arc/em.tcl b/tcl/cpu/arc/em.tcl
index 595a35130..13c5b437c 100644
--- a/tcl/cpu/arc/em.tcl
+++ b/tcl/cpu/arc/em.tcl
@@ -1,8 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #  Copyright (C) 2015, 2020 Synopsys, Inc.
 #  Anton Kolesov <ant...@sy...>
 #  Didin Evgeniy <di...@sy...>
-#
-# SPDX-License-Identifier: GPL-2.0-or-later
 
 source [find cpu/arc/v2.tcl]
 
diff --git a/tcl/cpu/arc/hs.tcl b/tcl/cpu/arc/hs.tcl
index 181f993bf..28e04f952 100644
--- a/tcl/cpu/arc/hs.tcl
+++ b/tcl/cpu/arc/hs.tcl
@@ -1,8 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #  Copyright (C) 2015, 2020 Synopsys, Inc.
 #  Anton Kolesov <ant...@sy...>
 #  Didin Evgeniy <di...@sy...>
-#
-# SPDX-License-Identifier: GPL-2.0-or-later
 
 source [find cpu/arc/v2.tcl]
 
diff --git a/tcl/cpu/arc/v2.tcl b/tcl/cpu/arc/v2.tcl
index 364e8af37..d28b9d974 100644
--- a/tcl/cpu/arc/v2.tcl
+++ b/tcl/cpu/arc/v2.tcl
@@ -1,8 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #  Copyright (C) 2015, 2020 Synopsys, Inc.
 #  Anton Kolesov <ant...@sy...>
 #  Didin Evgeniy <di...@sy...>
-#
-# SPDX-License-Identifier: GPL-2.0-or-later
 
 source [find cpu/arc/common.tcl]
 
diff --git a/tcl/interface/ftdi/snps_sdp.cfg b/tcl/interface/ftdi/snps_sdp.cfg
index 7bd8387b7..eb2aecc87 100644
--- a/tcl/interface/ftdi/snps_sdp.cfg
+++ b/tcl/interface/ftdi/snps_sdp.cfg
@@ -1,8 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #  Copyright (C) 2020 Synopsys, Inc.
 #  Anton Kolesov <ant...@sy...>
 #  Didin Evgeniy <di...@sy...>
-#
-#  SPDX-License-Identifier: GPL-2.0-or-later
 
 #
 # Synopsys SDP Mainboard has embdded FT2232 chip, which is similar to Digilent
diff --git a/tcl/target/snps_em_sk_fpga.cfg b/tcl/target/snps_em_sk_fpga.cfg
index d09561f38..62f4dec10 100644
--- a/tcl/target/snps_em_sk_fpga.cfg
+++ b/tcl/target/snps_em_sk_fpga.cfg
@@ -1,8 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #  Copyright (C) 2014-2015,2020 Synopsys, Inc.
 #  Anton Kolesov <ant...@sy...>
 #  Didin Evgeniy <di...@sy...>
-#
-#  SPDX-License-Identifier: GPL-2.0-or-later
 
 #
 # Xilinx Spartan-6 XC6SLX45  FPGA on EM Starter Kit v1.
diff --git a/tcl/target/snps_hsdk.cfg b/tcl/target/snps_hsdk.cfg
index 372b406f9..b4f368425 100644
--- a/tcl/target/snps_hsdk.cfg
+++ b/tcl/target/snps_hsdk.cfg
@@ -1,8 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #  Copyright (C) 2019,2020 Synopsys, Inc.
 #  Anton Kolesov <ant...@sy...>
 #  Didin Evgeniy <di...@sy...>
-#
-# SPDX-License-Identifier: GPL-2.0-or-later
 
 #
 # HS Development Kit SoC.

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/snps_em_sk.cfg        | 4 ++--
 tcl/board/snps_em_sk_v1.cfg     | 4 ++--
 tcl/board/snps_em_sk_v2.1.cfg   | 4 ++--
 tcl/board/snps_em_sk_v2.2.cfg   | 4 ++--
 tcl/board/snps_hsdk.cfg         | 4 ++--
 tcl/cpu/arc/common.tcl          | 4 ++--
 tcl/cpu/arc/em.tcl              | 4 ++--
 tcl/cpu/arc/hs.tcl              | 4 ++--
 tcl/cpu/arc/v2.tcl              | 4 ++--
 tcl/interface/ftdi/snps_sdp.cfg | 4 ++--
 tcl/target/snps_em_sk_fpga.cfg  | 4 ++--
 tcl/target/snps_hsdk.cfg        | 4 ++--
 12 files changed, 24 insertions(+), 24 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-742-g69ea481e0

From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:52:14

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  69ea481e0b3607085cc05cbc5ca41740c9f938f6 (commit)
       via  6306bdffc249809810a89e5b0ade1a998e62cf5d (commit)
      from  48727688f91713a5814f6a85883d1c3d7810103b (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 69ea481e0b3607085cc05cbc5ca41740c9f938f6
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jun 12 22:55:37 2022 +0200

    tcl: replace FSF boilerplate with SPDX tag
    
    OpenOCD project is switching to SPDX tags.
    Replace the few FSF boilerplate in tcl folder.
    
    Change-Id: I15b146eb77cc491ed7355178f684f3e76fc763b4
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7025
    Tested-by: jenkins
    Reviewed-by: Tarek BOCHKATI <tar...@gm...>

diff --git a/tcl/board/ampere_emag8180.cfg b/tcl/board/ampere_emag8180.cfg
index a122e0288..736be1225 100644
--- a/tcl/board/ampere_emag8180.cfg
+++ b/tcl/board/ampere_emag8180.cfg
@@ -1,22 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # OpenOCD Board Configuration for eMAG Development Platform
 #
 # Copyright (c) 2019-2021, Ampere Computing LLC
 #
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program;
-#
-#
 
 #
 # Configure JTAG speed
diff --git a/tcl/interface/jtag_dpi.cfg b/tcl/interface/jtag_dpi.cfg
index a92e131a9..225d4d545 100644
--- a/tcl/interface/jtag_dpi.cfg
+++ b/tcl/interface/jtag_dpi.cfg
@@ -1,22 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Provide support for the Cadence JTAG BFM
 #
 # Copyright (c) 2020, Ampere Computing LLC
 #
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program;
-#
-#
 
 adapter driver jtag_dpi
 
diff --git a/tcl/target/ampere_emag.cfg b/tcl/target/ampere_emag.cfg
index 2e828de86..0b0bd9e88 100644
--- a/tcl/target/ampere_emag.cfg
+++ b/tcl/target/ampere_emag.cfg
@@ -1,22 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # OpenOCD Target Configuration for eMAG ARMv8 Processor
 #
 # Copyright (c) 2019-2021, Ampere Computing LLC
 #
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program;
-#
-#
 
 #
 # Configure defaults for target

commit 6306bdffc249809810a89e5b0ade1a998e62cf5d
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Jun 13 00:08:15 2022 +0200

    tcl/board/steval-idb012v1: fix SPDX tag
    
    Remove trailing '.'
    While there, add newline to file's last line.
    
    Change-Id: I3a727e406b572d051b28e17688c24627e55520c4
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7024
    Tested-by: jenkins

diff --git a/tcl/board/steval-idb012v1.cfg b/tcl/board/steval-idb012v1.cfg
index 25efc581f..288cbb260 100644
--- a/tcl/board/steval-idb012v1.cfg
+++ b/tcl/board/steval-idb012v1.cfg
@@ -1,5 +1,6 @@
-# SPDX-License-Identifier: GPL-2.0-or-later.
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # This is an evaluation board with a single BlueNRG-LPS chip.
 set CHIPNAME bluenrg-lps
 source [find interface/cmsis-dap.cfg]
-source [find target/bluenrg-x.cfg]
\ No newline at end of file
+source [find target/bluenrg-x.cfg]

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/ampere_emag8180.cfg | 16 ++--------------
 tcl/board/steval-idb012v1.cfg |  5 +++--
 tcl/interface/jtag_dpi.cfg    | 16 ++--------------
 tcl/target/ampere_emag.cfg    | 16 ++--------------
 4 files changed, 9 insertions(+), 44 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-740-g48727688f

From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:51:40

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  48727688f91713a5814f6a85883d1c3d7810103b (commit)
      from  717b99164adc09c5a74bd25edeca87d66308e9dd (commit)

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- Log -----------------------------------------------------------------
commit 48727688f91713a5814f6a85883d1c3d7810103b
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Jun 13 00:09:41 2022 +0200

    tcl/interface/vdebug: add newline to file's last line
    
    Change-Id: I83d2477e8bc837aeac69bd5d08fdd923fd00a37c
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7023
    Tested-by: jenkins

diff --git a/tcl/interface/vdebug.cfg b/tcl/interface/vdebug.cfg
index 9cca6aaab..7350bb9a9 100644
--- a/tcl/interface/vdebug.cfg
+++ b/tcl/interface/vdebug.cfg
@@ -30,4 +30,4 @@ tcl_port disabled
 vdebug batching 1
 
 # Polling values
-vdebug polling 100 1000
\ No newline at end of file
+vdebug polling 100 1000

-----------------------------------------------------------------------

Summary of changes:
 tcl/interface/vdebug.cfg | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-739-g717b99164

From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:51:06

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- Log -----------------------------------------------------------------
commit 717b99164adc09c5a74bd25edeca87d66308e9dd
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Jun 13 15:41:22 2022 +0200

    semihosting: remove comparison with NULL
    
    Commit b9526f140127 ("semihosting: permit redirection of
    semihosting I/O to TCP") introduces a new comparison with NULL.
    
    Remove it.
    
    Change-Id: Ice4333c50d16f7592f0ff86b1640217fa42e34f6
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Fixes: b9526f140127 ("semihosting: permit redirection of semihosting I/O to TCP")
    Reviewed-on: https://review.openocd.org/c/openocd/+/7031
    Tested-by: jenkins

diff --git a/src/target/semihosting_common.c b/src/target/semihosting_common.c
index d54c341ac..2c7f4a118 100644
--- a/src/target/semihosting_common.c
+++ b/src/target/semihosting_common.c
@@ -1830,7 +1830,7 @@ COMMAND_HANDLER(handle_common_semihosting_redirect_command)
 {
 	struct target *target = get_current_target(CMD_CTX);
 
-	if (target == NULL) {
+	if (!target) {
 		LOG_ERROR("No target selected");
 		return ERROR_FAIL;
 	}

-----------------------------------------------------------------------

Summary of changes:
 src/target/semihosting_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:50:36

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       via  1a3573d73194a334d2737554538b51eff649e1a8 (commit)
      from  e4f5ce5d3e342826794739a273b1f72a48d63540 (commit)

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- Log -----------------------------------------------------------------
commit eab88eadd7b828f9c07007a8ac91988c37b5d036
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Jun 13 15:56:14 2022 +0200

    drivers/linuxgpiod: simplify gpio release
    
    We already have a helper to release the gpio.
    Extend it to also release its corresponding gpio chip.
    
    As side effect, remove comparison with NULL.
    
    Change-Id: I47cd446edfaead662d63c3330f25a791b747e882
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7033
    Tested-by: jenkins
    Reviewed-by: Steve Marple <ste...@go...>

diff --git a/src/jtag/drivers/linuxgpiod.c b/src/jtag/drivers/linuxgpiod.c
index 70fb55514..0e96d82e5 100644
--- a/src/jtag/drivers/linuxgpiod.c
+++ b/src/jtag/drivers/linuxgpiod.c
@@ -288,45 +288,26 @@ static bool linuxgpiod_swd_mode_possible(void)
 	return true;
 }
 
-static inline void helper_release(struct gpiod_line *line)
+static inline void helper_release(struct gpiod_line *line, struct gpiod_chip *chip)
 {
 	if (line)
 		gpiod_line_release(line);
+	if (chip)
+		gpiod_chip_close(chip);
 }
 
 static int linuxgpiod_quit(void)
 {
-	helper_release(gpiod_led);
-	helper_release(gpiod_srst);
-	helper_release(gpiod_swdio);
-	helper_release(gpiod_swdio_dir);
-	helper_release(gpiod_swclk);
-	helper_release(gpiod_trst);
-	helper_release(gpiod_tms);
-	helper_release(gpiod_tck);
-	helper_release(gpiod_tdi);
-	helper_release(gpiod_tdo);
-
-	if (gpiod_chip_led != NULL)
-		gpiod_chip_close(gpiod_chip_led);
-	if (gpiod_chip_srst != NULL)
-		gpiod_chip_close(gpiod_chip_srst);
-	if (gpiod_chip_swdio != NULL)
-		gpiod_chip_close(gpiod_chip_swdio);
-	if (gpiod_chip_swdio_dir != NULL)
-		gpiod_chip_close(gpiod_chip_swdio_dir);
-	if (gpiod_chip_swclk != NULL)
-		gpiod_chip_close(gpiod_chip_swclk);
-	if (gpiod_chip_trst != NULL)
-		gpiod_chip_close(gpiod_chip_trst);
-	if (gpiod_chip_tms != NULL)
-		gpiod_chip_close(gpiod_chip_tms);
-	if (gpiod_chip_tck != NULL)
-		gpiod_chip_close(gpiod_chip_tck);
-	if (gpiod_chip_tdi != NULL)
-		gpiod_chip_close(gpiod_chip_tdi);
-	if (gpiod_chip_tdo != NULL)
-		gpiod_chip_close(gpiod_chip_tdo);
+	helper_release(gpiod_led,       gpiod_chip_led);
+	helper_release(gpiod_srst,      gpiod_chip_srst);
+	helper_release(gpiod_swdio,     gpiod_chip_swdio);
+	helper_release(gpiod_swdio_dir, gpiod_chip_swdio_dir);
+	helper_release(gpiod_swclk,     gpiod_chip_swclk);
+	helper_release(gpiod_trst,      gpiod_chip_trst);
+	helper_release(gpiod_tms,       gpiod_chip_tms);
+	helper_release(gpiod_tck,       gpiod_chip_tck);
+	helper_release(gpiod_tdi,       gpiod_chip_tdi);
+	helper_release(gpiod_tdo,       gpiod_chip_tdo);
 
 	return ERROR_OK;
 }

commit 1a3573d73194a334d2737554538b51eff649e1a8
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Jun 13 22:59:42 2022 +0200

    drivers/linuxgpiod: release gpio at exit
    
    Commit 20adf85f3484 ("linuxgpiod: add SWDIO buffer") introduces an
    additional gpio for SWDIO direction, but does not release it at
    driver's exit.
    
    Release the gpio at exit.
    
    Change-Id: If7ea31f79ffed04af585864e49bcf1f35e118bdd
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7032
    Tested-by: jenkins
    Reviewed-by: Steve Marple <ste...@go...>

diff --git a/src/jtag/drivers/linuxgpiod.c b/src/jtag/drivers/linuxgpiod.c
index 288035f2e..70fb55514 100644
--- a/src/jtag/drivers/linuxgpiod.c
+++ b/src/jtag/drivers/linuxgpiod.c
@@ -299,6 +299,7 @@ static int linuxgpiod_quit(void)
 	helper_release(gpiod_led);
 	helper_release(gpiod_srst);
 	helper_release(gpiod_swdio);
+	helper_release(gpiod_swdio_dir);
 	helper_release(gpiod_swclk);
 	helper_release(gpiod_trst);
 	helper_release(gpiod_tms);

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/linuxgpiod.c | 44 +++++++++++++------------------------------
 1 file changed, 13 insertions(+), 31 deletions(-)


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From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:49:48

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      from  f23ac683430ffb08b511dd02afc93bc1f454a017 (commit)

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- Log -----------------------------------------------------------------
commit e4f5ce5d3e342826794739a273b1f72a48d63540
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Jun 13 16:41:11 2022 +0200

    aarch64: fix handling of 'reset halt'
    
    Commit 6c0151623cb0 ("aarch64: add support for "reset halt"")
    introduces the register setting to halt at reset vector, but:
    - does not consider the case 'srst_pulls_trst' that makes useless
      setting the registers as they will be erased by the pulled trst;
    - does not clean sticky errors in case of 'srst_gates_jtag'.
    
    Avoid any register initialization on 'srst_pulls_trst' and move
    the cleaning of sticky errors in the common block.
    
    Change-Id: I6f839f06f7b091e234ede31ec18096e51f017bcd
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Fixes: 6c0151623cb0 ("aarch64: add support for "reset halt"")
    Reviewed-on: https://review.openocd.org/c/openocd/+/7034
    Tested-by: jenkins
    Reviewed-by: Christian Hoff <chr...@ad...>

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 8a8f21d13..e4d420f07 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -1942,7 +1942,7 @@ static int aarch64_assert_reset(struct target *target)
 	else if (reset_config & RESET_HAS_SRST) {
 		bool srst_asserted = false;
 
-		if (target->reset_halt) {
+		if (target->reset_halt && !(reset_config & RESET_SRST_PULLS_TRST)) {
 			if (target_was_examined(target)) {
 
 				if (reset_config & RESET_SRST_NO_GATING) {
@@ -1952,12 +1952,12 @@ static int aarch64_assert_reset(struct target *target)
 					 */
 					adapter_assert_reset();
 					srst_asserted = true;
-
-					/* make sure to clear all sticky errors */
-					mem_ap_write_atomic_u32(armv8->debug_ap,
-							armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
 				}
 
+				/* make sure to clear all sticky errors */
+				mem_ap_write_atomic_u32(armv8->debug_ap,
+						armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
+
 				/* set up Reset Catch debug event to halt the CPU after reset */
 				retval = aarch64_enable_reset_catch(target, true);
 				if (retval != ERROR_OK)

-----------------------------------------------------------------------

Summary of changes:
 src/target/aarch64.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-735-gf23ac6834

From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:48:56

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
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      from  334a187e64121cb1f8bf6f07f5400e0e5ba8c0ff (commit)

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- Log -----------------------------------------------------------------
commit f23ac683430ffb08b511dd02afc93bc1f454a017
Author: Alvin Å ipraga <al...@ba...>
Date:   Sat Jun 11 00:01:01 2022 +0200

    tcl/target/imx8m: use hwthread rtos
    
    In order to facilitate debugging multiple cores, specify the coreid and
    the hwthread rtos in the imx8m target configuration.
    
    Change-Id: Ibd871517a160ceca15002fb10e27cb793f14d086
    Signed-off-by: Alvin Å ipraga <al...@ba...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7019
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/imx8m.cfg b/tcl/target/imx8m.cfg
index 9a8bfecb1..af424c1c3 100644
--- a/tcl/target/imx8m.cfg
+++ b/tcl/target/imx8m.cfg
@@ -38,13 +38,14 @@ for { set _core 0 } { $_core < $_cores } { incr _core } {
         -baseaddr [lindex $CTIBASE $_core]
 
     set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
-        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
+        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
 
     if { $_core != 0 } {
         # non-boot core examination may fail
         set _command "$_command -defer-examine"
         set _smp_command "$_smp_command $_TARGETNAME.$_core"
     } else {
+        set _command "$_command -rtos hwthread"
         set _smp_command "target smp $_TARGETNAME.$_core"
     }
 

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/imx8m.cfg | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)


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From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:48:06

This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
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      from  af9daf4433e006197942121a069a5e9d7ec28671 (commit)

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- Log -----------------------------------------------------------------
commit 334a187e64121cb1f8bf6f07f5400e0e5ba8c0ff
Author: Erhan Kurubas <erh...@es...>
Date:   Tue Apr 5 14:26:08 2022 +0300

    semihosting: add custom user command handler
    
    Custom user syscalls can be handled with target events in the TCL scripts.
    This patch gives another opportunity to handle custom syscalls in the c files.
    Besides that some utility functions are also exported for the custom handlers.
    
    Signed-off-by: Erhan Kurubas <erh...@es...>
    Change-Id: Ice13d527540a0de0b2a8abda912ae3dcff3834b7
    Reviewed-on: https://review.openocd.org/c/openocd/+/6889
    Tested-by: jenkins
    Reviewed-by: Ian Thompson <ia...@ca...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/semihosting_common.c b/src/target/semihosting_common.c
index 0a60eb121..d54c341ac 100644
--- a/src/target/semihosting_common.c
+++ b/src/target/semihosting_common.c
@@ -103,16 +103,6 @@ static int semihosting_common_fileio_info(struct target *target,
 static int semihosting_common_fileio_end(struct target *target, int result,
 	int fileio_errno, bool ctrl_c);
 
-static int semihosting_read_fields(struct target *target, size_t number,
-	uint8_t *fields);
-static int semihosting_write_fields(struct target *target, size_t number,
-	uint8_t *fields);
-static uint64_t semihosting_get_field(struct target *target, size_t index,
-	uint8_t *fields);
-static void semihosting_set_field(struct target *target, uint64_t value,
-	size_t index,
-	uint8_t *fields);
-
 /* Attempts to include gdb_server.h failed. */
 extern int gdb_actual_connections;
 
@@ -166,6 +156,7 @@ int semihosting_common_init(struct target *target, void *setup,
 
 	semihosting->setup = setup;
 	semihosting->post_result = post_result;
+	semihosting->user_command_extension = NULL;
 
 	target->semihosting = semihosting;
 
@@ -1467,9 +1458,14 @@ int semihosting_common(struct target *target)
 			 * Return
 			 * On exit, the RETURN REGISTER contains the return status.
 			 */
-		{
-			assert(!semihosting_user_op_params);
+			if (semihosting->user_command_extension) {
+				retval = semihosting->user_command_extension(target);
+				if (retval != ERROR_NOT_IMPLEMENTED)
+					break;
+				/* If custom user command not handled, we are looking for the TCL handler */
+			}
 
+			assert(!semihosting_user_op_params);
 			retval = semihosting_read_fields(target, 2, fields);
 			if (retval != ERROR_OK) {
 				LOG_ERROR("Failed to read fields for user defined command"
@@ -1507,11 +1503,8 @@ int semihosting_common(struct target *target)
 			target_handle_event(target, semihosting->op);
 			free(semihosting_user_op_params);
 			semihosting_user_op_params = NULL;
-
 			semihosting->result = 0;
 			break;
-		}
-
 
 		case SEMIHOSTING_SYS_ELAPSED:	/* 0x30 */
 		/*
@@ -1670,10 +1663,13 @@ static int semihosting_common_fileio_end(struct target *target, int result,
 	return semihosting->post_result(target);
 }
 
+/* -------------------------------------------------------------------------
+ * Utility functions. */
+
 /**
  * Read all fields of a command from target to buffer.
  */
-static int semihosting_read_fields(struct target *target, size_t number,
+int semihosting_read_fields(struct target *target, size_t number,
 	uint8_t *fields)
 {
 	struct semihosting *semihosting = target->semihosting;
@@ -1685,7 +1681,7 @@ static int semihosting_read_fields(struct target *target, size_t number,
 /**
  * Write all fields of a command from buffer to target.
  */
-static int semihosting_write_fields(struct target *target, size_t number,
+int semihosting_write_fields(struct target *target, size_t number,
 	uint8_t *fields)
 {
 	struct semihosting *semihosting = target->semihosting;
@@ -1697,7 +1693,7 @@ static int semihosting_write_fields(struct target *target, size_t number,
 /**
  * Extract a field from the buffer, considering register size and endianness.
  */
-static uint64_t semihosting_get_field(struct target *target, size_t index,
+uint64_t semihosting_get_field(struct target *target, size_t index,
 	uint8_t *fields)
 {
 	struct semihosting *semihosting = target->semihosting;
@@ -1710,7 +1706,7 @@ static uint64_t semihosting_get_field(struct target *target, size_t index,
 /**
  * Store a field in the buffer, considering register size and endianness.
  */
-static void semihosting_set_field(struct target *target, uint64_t value,
+void semihosting_set_field(struct target *target, uint64_t value,
 	size_t index,
 	uint8_t *fields)
 {
diff --git a/src/target/semihosting_common.h b/src/target/semihosting_common.h
index 404080f02..1b7169030 100644
--- a/src/target/semihosting_common.h
+++ b/src/target/semihosting_common.h
@@ -179,6 +179,13 @@ struct semihosting {
 	/** Base directory for semihosting I/O operations. */
 	char *basedir;
 
+	/**
+	 * Target's extension of semihosting user commands.
+	 * @returns ERROR_NOT_IMPLEMENTED when user command is not handled, otherwise
+	 * sets semihosting->result and semihosting->sys_errno and returns ERROR_OK.
+	 */
+	int (*user_command_extension)(struct target *target);
+
 	int (*setup)(struct target *target, int enable);
 	int (*post_result)(struct target *target);
 };
@@ -187,4 +194,15 @@ int semihosting_common_init(struct target *target, void *setup,
 	void *post_result);
 int semihosting_common(struct target *target);
 
+/* utility functions which may also be used by semihosting extensions (custom vendor-defined syscalls) */
+int semihosting_read_fields(struct target *target, size_t number,
+	uint8_t *fields);
+int semihosting_write_fields(struct target *target, size_t number,
+	uint8_t *fields);
+uint64_t semihosting_get_field(struct target *target, size_t index,
+	uint8_t *fields);
+void semihosting_set_field(struct target *target, uint64_t value,
+	size_t index,
+	uint8_t *fields);
+
 #endif	/* OPENOCD_TARGET_SEMIHOSTING_COMMON_H */

-----------------------------------------------------------------------

Summary of changes:
 src/target/semihosting_common.c | 34 +++++++++++++++-------------------
 src/target/semihosting_common.h | 18 ++++++++++++++++++
 2 files changed, 33 insertions(+), 19 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-733-gaf9daf443

From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:47:32

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- Log -----------------------------------------------------------------
commit af9daf4433e006197942121a069a5e9d7ec28671
Author: Erhan Kurubas <erh...@es...>
Date:   Sun Jun 12 01:04:08 2022 +0200

    esp32s2: convert counted timeout to timeval_ms
    
    Signed-off-by: Erhan Kurubas <erh...@es...>
    Change-Id: Id685408281478cec0e7e886dbedb3b8972c7b652
    Reviewed-on: https://review.openocd.org/c/openocd/+/7020
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Ian Thompson <ia...@ca...>

diff --git a/src/target/espressif/esp32s2.c b/src/target/espressif/esp32s2.c
index 36980325b..1bf56b9a7 100644
--- a/src/target/espressif/esp32s2.c
+++ b/src/target/espressif/esp32s2.c
@@ -21,6 +21,7 @@
 #include "config.h"
 #endif
 
+#include <helper/time_support.h>
 #include "assert.h"
 #include <target/target.h>
 #include <target/target_type.h>
@@ -482,15 +483,16 @@ static int esp32s2_soc_reset(struct target *target)
 	}
 	/* Wait for SoC to reset */
 	alive_sleep(100);
-	int timeout = 100;
-	while (target->state != TARGET_RESET && target->state != TARGET_RUNNING && --timeout > 0) {
+	int64_t timeout = timeval_ms() + 100;
+	while (target->state != TARGET_RESET && target->state != TARGET_RUNNING) {
 		alive_sleep(10);
 		xtensa_poll(target);
+		if (timeval_ms() >= timeout) {
+			LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d", target->state);
+			return ERROR_TARGET_TIMEOUT;
+		}
 	}
-	if (timeout == 0) {
-		LOG_ERROR("Timed out waiting for CPU to be reset, target->state=%d", target->state);
-		return ERROR_TARGET_TIMEOUT;
-	}
+
 	xtensa_halt(target);
 	res = target_wait_state(target, TARGET_HALTED, 1000);
 	if (res != ERROR_OK) {

-----------------------------------------------------------------------

Summary of changes:
 src/target/espressif/esp32s2.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)


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Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-732-g2053120ba

From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:47:08

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- Log -----------------------------------------------------------------
commit 2053120ba10d68339c61cd2b247bde01bda41ab7
Author: Erhan Kurubas <erh...@es...>
Date:   Sun May 22 23:17:48 2022 +0200

    target: add Espressif ESP32-S3 basic support
    
    ESP32-S3 is a dual core Xtensa SoC
    Not full featured yet. Some of the missing functionality:
    -Semihosting
    -Flash breakpoints
    -Flash loader
    -Apptrace
    -FreeRTOS
    
    Signed-off-by: Erhan Kurubas <erh...@es...>
    Change-Id: I44e17088030c96a9be9809f6579a4f16dbfc5794
    Reviewed-on: https://review.openocd.org/c/openocd/+/6990
    Tested-by: jenkins
    Reviewed-by: Ian Thompson <ia...@ca...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/contrib/loaders/reset/espressif/esp32s3/Makefile b/contrib/loaders/reset/espressif/esp32s3/Makefile
new file mode 100644
index 000000000..4dab161fd
--- /dev/null
+++ b/contrib/loaders/reset/espressif/esp32s3/Makefile
@@ -0,0 +1,31 @@
+# ESP32 Makefile to compile the SoC reset program
+# Copyright (C) 2022 Espressif Systems Ltd.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>
+
+# Prefix for ESP32 cross compilers (can include a directory path)
+CROSS ?= xtensa-esp32s3-elf-
+
+APP_ARCH := xtensa
+APP_CHIP := ESP32S3
+APP_CHIP_PATH := $(shell pwd)
+SRCS := $(APP_CHIP_PATH)/esp32s3_cpu_reset_handler.S
+
+CFLAGS :=
+LDFLAGS :=
+
+INCLUDES :=
+DEFINES :=
+
+include ../common.mk
diff --git a/contrib/loaders/reset/espressif/esp32s3/cpu_reset_handler_code.inc b/contrib/loaders/reset/espressif/esp32s3/cpu_reset_handler_code.inc
new file mode 100644
index 000000000..dc9702c62
--- /dev/null
+++ b/contrib/loaders/reset/espressif/esp32s3/cpu_reset_handler_code.inc
@@ -0,0 +1,17 @@
+/* Autogenerated with ../../../../../src/helper/bin2char.sh */
+0x06,0x23,0x00,0x00,0x06,0x18,0x00,0x00,0x38,0x80,0x00,0x60,0xc0,0x80,0x00,0x60,
+0xc4,0x80,0x00,0x60,0x90,0x80,0x00,0x60,0x74,0x80,0x00,0x60,0x18,0x32,0x58,0x01,
+0x00,0xa0,0x00,0x9c,0x00,0x80,0x00,0x60,0xa1,0x3a,0xd8,0x50,0xac,0x80,0x00,0x60,
+0x64,0xf0,0x01,0x60,0x64,0x00,0x02,0x60,0x94,0x80,0x00,0x60,0x48,0xf0,0x01,0x60,
+0x48,0x00,0x02,0x60,0xb4,0x80,0x00,0x60,0x2a,0x31,0x1d,0x8f,0xb0,0x80,0x00,0x60,
+0x00,0x00,0xb0,0x84,0x04,0x00,0x0c,0x60,0x00,0x00,0x0c,0x60,0x00,0x00,0x0c,0x60,
+0x38,0x80,0x00,0x60,0x00,0x30,0x00,0x00,0x50,0x55,0x30,0x41,0xe7,0xff,0x59,0x04,
+0x41,0xe7,0xff,0x59,0x04,0x41,0xe6,0xff,0x59,0x04,0x41,0xe6,0xff,0x59,0x04,0x41,
+0xe6,0xff,0x31,0xe6,0xff,0x39,0x04,0x31,0xe6,0xff,0x41,0xe6,0xff,0x39,0x04,0x00,
+0x60,0xeb,0x03,0x60,0x61,0x04,0x56,0x26,0x05,0x50,0x55,0x30,0x31,0xe3,0xff,0x41,
+0xe3,0xff,0x39,0x04,0x41,0xe3,0xff,0x39,0x04,0x41,0xe2,0xff,0x39,0x04,0x41,0xe2,
+0xff,0x59,0x04,0x41,0xe2,0xff,0x59,0x04,0x41,0xe2,0xff,0x59,0x04,0x41,0xe1,0xff,
+0x31,0xe2,0xff,0x39,0x04,0x41,0xe1,0xff,0x31,0xe2,0xff,0x39,0x04,0x41,0xe1,0xff,
+0x59,0x04,0x41,0xe1,0xff,0x0c,0x23,0x39,0x04,0x41,0xe0,0xff,0x0c,0x43,0x39,0x04,
+0x52,0x64,0x00,0x41,0xdf,0xff,0x31,0xdf,0xff,0x32,0x64,0x00,0x00,0x70,0x00,0x46,
+0xfe,0xff,
diff --git a/contrib/loaders/reset/espressif/esp32s3/esp32s3_cpu_reset_handler.S b/contrib/loaders/reset/espressif/esp32s3/esp32s3_cpu_reset_handler.S
new file mode 100644
index 000000000..e70ac9ca7
--- /dev/null
+++ b/contrib/loaders/reset/espressif/esp32s3/esp32s3_cpu_reset_handler.S
@@ -0,0 +1,152 @@
+/***************************************************************************
+ *   Reset stub used by esp32s3 target                                     *
+ *   Copyright (C) 2020 Espressif Systems (Shanghai) Co. Ltd.              *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#define RTC_CNTL_RESET_STATE_REG            0x60008038
+#define RTC_CNTL_RESET_STATE_DEF            0x3000
+#define RTC_CNTL_CLK_CONF_REG               0x60008074
+#define RTC_CNTL_CLK_CONF_DEF               0x1583218
+#define RTC_CNTL_STORE4_REG                 0x600080C0
+#define RTC_CNTL_STORE5_REG                 0x600080C4
+#define WDT_WKEY_VALUE                      0x50D83AA1
+#define TIMG0_WDTWPROTECT_REG               0x6001F064
+#define TIMG0_WDTCONFIG0_REG                0x6001F048
+#define TIMG1_WDTWPROTECT_REG               0x60020064
+#define TIMG1_WDTCONFIG0_REG                0x60020048
+#define RTC_CNTL_WDTCONFIG0_REG             0x60008094
+#define RTC_CNTL_WDTWPROTECT_REG            0x600080AC
+#define RTC_CNTL_OPTIONS0_REG               0x60008000
+#define RTC_CNTL_OPTIONS0_DEF               0x1C00A000
+#define RTC_CNTL_SW_SYS_RST                 0x80000000
+#define RTC_CNTL_DIG_PWC_REG                0x60008090
+#define RTC_CNTL_SWD_CONF_REG               0x600080B0
+#define RTC_CNTL_SWD_CONF_VAL               0x84B00000
+#define RTC_CNTL_SWD_WPROTECT_REG           0x600080B4
+#define RTC_CNTL_SWD_WKEY_VALUE             0x8F1D312A
+#define SYSTEM_CORE_1_CONTROL_0_REG         0x600C0000
+#define SYSTEM_CONTROL_CORE_1_RESETING      0x4
+#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN    0x2
+#define SYSTEM_CORE_1_CONTROL_1_REG         0x600C0004
+
+
+/* This stub is copied to RTC_SLOW_MEM by OpenOCD, and the CPU starts executing
+ * it instead of the ROM code (0x40000400). This stub disables watchdogs and
+ * goes into a loop.
+ * OpenOCD will then halt the target and perform CPU reset using OCD.
+ */
+
+
+/* Has to be at offset 0. This is the entry point of the CPU, once
+ * RTC_CNTL_PROCPU_STAT_VECTOR_SEL is cleared.
+ * CPU will come here after the system reset, triggered by RTC_CNTL_SW_SYS_RST.
+ */
+    .global     cpu_at_start_handler
+    .type       cpu_at_start_handler,@function
+    .align      4
+cpu_at_start_handler:
+    j start
+
+
+/* Has to be at offset 4. Once the stub code has been uploaded into RTC Slow
+ * memory, OpenOCD will set the PC to this address, and resume execution.
+ * The stub will then jump to 'reset' label and perform the reset.
+ */
+    .global     cpu_reset_handler
+    .type       cpu_reset_handler,@function
+    .align      4
+cpu_reset_handler:
+    j reset
+
+    .align 4
+    .literal_position
+
+    .align 4
+reset:
+    /* Use a5 as a zero register */
+    xor a5, a5, a5
+    /* Select static reset vector 0 (XCHAL_RESET_VECTOR0_VADDR, 0x50000000) */
+    movi a4, RTC_CNTL_RESET_STATE_REG
+    s32i a5, a4, 0
+    /* Set some clock-related RTC registers to the default values */
+    movi a4, RTC_CNTL_STORE4_REG
+    s32i a5, a4, 0
+    movi a4, RTC_CNTL_STORE5_REG
+    s32i a5, a4, 0
+    movi a4, RTC_CNTL_DIG_PWC_REG
+    s32i a5, a4, 0
+    movi a4, RTC_CNTL_CLK_CONF_REG
+    movi a3, RTC_CNTL_CLK_CONF_DEF
+    s32i a3, a4, 0
+    /* Reset the digital part of the chip (RTC controller doesn't get reset) */
+    movi a3, (RTC_CNTL_OPTIONS0_DEF | RTC_CNTL_SW_SYS_RST)
+    movi a4, RTC_CNTL_OPTIONS0_REG
+    s32i a3, a4, 0
+    /* Doesn't reach beyond this instruction */
+
+    .align 4
+start:
+    /* If running on the APP CPU, skip directly to the parking loop */
+    rsr.prid a6
+    extui a6, a6, 1, 1
+    bnez a6, parking_loop
+
+    /* Use a5 as a zero register */
+    xor a5, a5, a5
+    /* Disable the watchdogs */
+    movi a3, WDT_WKEY_VALUE
+    movi a4, RTC_CNTL_WDTWPROTECT_REG
+    s32i.n a3, a4, 0
+    movi a4, TIMG0_WDTWPROTECT_REG
+    s32i.n a3, a4, 0
+    movi a4, TIMG1_WDTWPROTECT_REG
+    s32i.n a3, a4, 0
+    movi a4, RTC_CNTL_WDTCONFIG0_REG
+    s32i.n a5, a4, 0
+    movi a4, TIMG0_WDTCONFIG0_REG
+    s32i.n a5, a4, 0
+    movi a4, TIMG1_WDTCONFIG0_REG
+    s32i.n a5, a4, 0
+    movi a4, RTC_CNTL_SWD_WPROTECT_REG
+    movi a3, RTC_CNTL_SWD_WKEY_VALUE
+    s32i.n a3, a4, 0
+    movi a4, RTC_CNTL_SWD_CONF_REG
+    movi a3, RTC_CNTL_SWD_CONF_VAL
+    s32i.n a3, a4, 0
+    /* Clear APP_CPU boot address */
+    movi a4, SYSTEM_CORE_1_CONTROL_1_REG
+    s32i.n a5, a4, 0
+    /* Clear APP_CPU clock gating */
+    movi a4, SYSTEM_CORE_1_CONTROL_0_REG
+    movi a3, SYSTEM_CONTROL_CORE_1_CLKGATE_EN
+    s32i.n a3, a4, 0
+    /* Set and clear APP_CPU reset */
+    movi a4, SYSTEM_CORE_1_CONTROL_0_REG
+    movi a3, SYSTEM_CONTROL_CORE_1_RESETING
+    s32i.n a3, a4, 0
+    s32i.n a5, a4, 0
+    /* Restore the reset vector to ROM */
+    movi a4, RTC_CNTL_RESET_STATE_REG
+    movi a3, RTC_CNTL_RESET_STATE_DEF
+    s32i.n a3, a4, 0
+
+
+parking_loop:
+    /* PRO and APP CPU will be in this loop, until OpenOCD
+     * finds the JTAG taps and puts the CPUs into debug mode.
+     */
+    waiti 0
+    j parking_loop
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 2661e46e7..f678621ee 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4915,6 +4915,7 @@ compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
 The current implementation supports eSi-32xx cores.
 @item @code{esp32} -- this is an Espressif SoC with dual Xtensa cores.
 @item @code{esp32s2} -- this is an Espressif SoC with single Xtensa core.
+@item @code{esp32s3} -- this is an Espressif SoC with dual Xtensa cores.
 @item @code{fa526} -- resembles arm920 (w/o Thumb).
 @item @code{feroceon} -- resembles arm926.
 @item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.
diff --git a/src/target/espressif/Makefile.am b/src/target/espressif/Makefile.am
index 2a9045b8a..2ea31d82c 100644
--- a/src/target/espressif/Makefile.am
+++ b/src/target/espressif/Makefile.am
@@ -4,7 +4,9 @@ noinst_LTLIBRARIES += %D%/libespressif.la
        %D%/esp_xtensa.h \
        %D%/esp_xtensa_smp.c \
        %D%/esp_xtensa_smp.h \
+       %D%/esp32.c \
+       %D%/esp32.h \
        %D%/esp32s2.c \
        %D%/esp32s2.h \
-       %D%/esp32.c \
-       %D%/esp32.h
+       %D%/esp32s3.c \
+       %D%/esp32s3.h
diff --git a/src/target/espressif/esp32s3.c b/src/target/espressif/esp32s3.c
new file mode 100644
index 000000000..98515834e
--- /dev/null
+++ b/src/target/espressif/esp32s3.c
@@ -0,0 +1,659 @@
+/***************************************************************************
+ *   ESP32-S3 target API for OpenOCD                                       *
+ *   Copyright (C) 2020 Espressif Systems Ltd.                             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <helper/time_support.h>
+#include <target/target.h>
+#include <target/target_type.h>
+#include <target/smp.h>
+#include "assert.h"
+#include "esp32s3.h"
+#include "esp_xtensa_smp.h"
+
+/*
+This is a JTAG driver for the ESP32_S3, the are two Tensilica cores inside
+the ESP32_S3 chip. For more information please have a look into ESP32_S3 target
+implementation.
+*/
+
+/* ESP32_S3 memory map */
+#define ESP32_S3_IRAM_LOW               0x40370000
+#define ESP32_S3_IRAM_HIGH              0x403E0000
+#define ESP32_S3_IROM_MASK_LOW          0x40000000
+#define ESP32_S3_IROM_MASK_HIGH         0x40060000
+#define ESP32_S3_DRAM_LOW               0x3FC88000
+#define ESP32_S3_DRAM_HIGH              0x3FD00000
+#define ESP32_S3_RTC_IRAM_LOW           0x600FE000
+#define ESP32_S3_RTC_IRAM_HIGH          0x60100000
+#define ESP32_S3_RTC_DRAM_LOW           0x600FE000
+#define ESP32_S3_RTC_DRAM_HIGH          0x60100000
+#define ESP32_S3_RTC_DATA_LOW           0x50000000
+#define ESP32_S3_RTC_DATA_HIGH          0x50002000
+#define ESP32_S3_EXTRAM_DATA_LOW        0x3D000000
+#define ESP32_S3_EXTRAM_DATA_HIGH       0x3E000000
+#define ESP32_S3_SYS_RAM_LOW            0x60000000UL
+#define ESP32_S3_SYS_RAM_HIGH           (ESP32_S3_SYS_RAM_LOW + 0x10000000UL)
+#define ESP32_S3_RTC_SLOW_MEM_BASE      ESP32_S3_RTC_DATA_LOW
+
+/* ESP32_S3 WDT */
+#define ESP32_S3_WDT_WKEY_VALUE       0x50D83AA1
+#define ESP32_S3_TIMG0_BASE           0x6001F000
+#define ESP32_S3_TIMG1_BASE           0x60020000
+#define ESP32_S3_TIMGWDT_CFG0_OFF     0x48
+#define ESP32_S3_TIMGWDT_PROTECT_OFF  0x64
+#define ESP32_S3_TIMG0WDT_CFG0        (ESP32_S3_TIMG0_BASE + ESP32_S3_TIMGWDT_CFG0_OFF)
+#define ESP32_S3_TIMG1WDT_CFG0        (ESP32_S3_TIMG1_BASE + ESP32_S3_TIMGWDT_CFG0_OFF)
+#define ESP32_S3_TIMG0WDT_PROTECT     (ESP32_S3_TIMG0_BASE + ESP32_S3_TIMGWDT_PROTECT_OFF)
+#define ESP32_S3_TIMG1WDT_PROTECT     (ESP32_S3_TIMG1_BASE + ESP32_S3_TIMGWDT_PROTECT_OFF)
+#define ESP32_S3_RTCCNTL_BASE         0x60008000
+#define ESP32_S3_RTCWDT_CFG_OFF       0x98
+#define ESP32_S3_RTCWDT_PROTECT_OFF   0xB0
+#define ESP32_S3_SWD_CONF_OFF         0xB0
+#define ESP32_S3_SWD_WPROTECT_OFF     0xB4
+#define ESP32_S3_RTCWDT_CFG           (ESP32_S3_RTCCNTL_BASE + ESP32_S3_RTCWDT_CFG_OFF)
+#define ESP32_S3_RTCWDT_PROTECT       (ESP32_S3_RTCCNTL_BASE + ESP32_S3_RTCWDT_PROTECT_OFF)
+#define ESP32_S3_SWD_CONF_REG         (ESP32_S3_RTCCNTL_BASE + ESP32_S3_SWD_CONF_OFF)
+#define ESP32_S3_SWD_WPROTECT_REG     (ESP32_S3_RTCCNTL_BASE + ESP32_S3_SWD_WPROTECT_OFF)
+#define ESP32_S3_SWD_AUTO_FEED_EN_M   BIT(31)
+#define ESP32_S3_SWD_WKEY_VALUE       0x8F1D312AU
+
+#define ESP32_S3_TRACEMEM_BLOCK_SZ    0x4000
+
+/* ESP32_S3 dport regs */
+#define ESP32_S3_DR_REG_SYSTEM_BASE                0x600c0000
+#define ESP32_S3_SYSTEM_CORE_1_CONTROL_0_REG       (ESP32_S3_DR_REG_SYSTEM_BASE + 0x014)
+#define ESP32_S3_SYSTEM_CONTROL_CORE_1_CLKGATE_EN  BIT(1)
+
+/* ESP32_S3 RTC regs */
+#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG (ESP32_S3_RTCCNTL_BASE + 0xBC)
+#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF 0x0
+
+/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
+ *xtensa-overlay */
+static const unsigned int esp32s3_gdb_regs_mapping[ESP32_S3_NUM_REGS] = {
+	XT_REG_IDX_PC,
+	XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
+	XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
+	XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
+	XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
+	XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
+	XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
+	XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
+	XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
+	XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
+	XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
+	XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
+	XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
+	XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
+	XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
+	XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
+	XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
+	XT_REG_IDX_LBEG, XT_REG_IDX_LEND, XT_REG_IDX_LCOUNT, XT_REG_IDX_SAR,
+	XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
+	XT_REG_IDX_PS, XT_REG_IDX_THREADPTR, XT_REG_IDX_BR, XT_REG_IDX_SCOMPARE1,
+	XT_REG_IDX_ACCLO, XT_REG_IDX_ACCHI,
+	XT_REG_IDX_M0, XT_REG_IDX_M1, XT_REG_IDX_M2, XT_REG_IDX_M3,
+	ESP32_S3_REG_IDX_GPIOOUT,
+	XT_REG_IDX_F0, XT_REG_IDX_F1, XT_REG_IDX_F2, XT_REG_IDX_F3,
+	XT_REG_IDX_F4, XT_REG_IDX_F5, XT_REG_IDX_F6, XT_REG_IDX_F7,
+	XT_REG_IDX_F8, XT_REG_IDX_F9, XT_REG_IDX_F10, XT_REG_IDX_F11,
+	XT_REG_IDX_F12, XT_REG_IDX_F13, XT_REG_IDX_F14, XT_REG_IDX_F15,
+	XT_REG_IDX_FCR, XT_REG_IDX_FSR,
+	ESP32_S3_REG_IDX_ACCX_0, ESP32_S3_REG_IDX_ACCX_1,
+	ESP32_S3_REG_IDX_QACC_H_0, ESP32_S3_REG_IDX_QACC_H_1, ESP32_S3_REG_IDX_QACC_H_2,
+	ESP32_S3_REG_IDX_QACC_H_3, ESP32_S3_REG_IDX_QACC_H_4,
+	ESP32_S3_REG_IDX_QACC_L_0, ESP32_S3_REG_IDX_QACC_L_1, ESP32_S3_REG_IDX_QACC_L_2,
+	ESP32_S3_REG_IDX_QACC_L_3, ESP32_S3_REG_IDX_QACC_L_4,
+	ESP32_S3_REG_IDX_SAR_BYTE, ESP32_S3_REG_IDX_FFT_BIT_WIDTH,
+	ESP32_S3_REG_IDX_UA_STATE_0, ESP32_S3_REG_IDX_UA_STATE_1, ESP32_S3_REG_IDX_UA_STATE_2,
+	ESP32_S3_REG_IDX_UA_STATE_3,
+	ESP32_S3_REG_IDX_Q0, ESP32_S3_REG_IDX_Q1, ESP32_S3_REG_IDX_Q2, ESP32_S3_REG_IDX_Q3,
+	ESP32_S3_REG_IDX_Q4, ESP32_S3_REG_IDX_Q5, ESP32_S3_REG_IDX_Q6, ESP32_S3_REG_IDX_Q7,
+
+	XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE,
+	XT_REG_IDX_MEMCTL, XT_REG_IDX_ATOMCTL, XT_REG_IDX_OCD_DDR,
+	XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
+	XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
+	XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
+	XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
+	XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
+	XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
+	XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
+	XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
+	XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
+	XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
+	XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
+	XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
+	XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
+
+	XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
+	XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
+	XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
+	XT_REG_IDX_FAULT_INFO,
+	XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
+	XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
+	XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
+	XT_REG_IDX_TRAX_MEMEND,
+	XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
+	XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
+	XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
+	XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
+	XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
+	XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
+	XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
+};
+
+/* actually this table contains user + TIE registers
+ * TODO: for TIE registers we need to specify custom access functions instead of `xtensa_user_reg_xxx_type`*/
+static const struct xtensa_user_reg_desc esp32s3_user_regs[ESP32_S3_NUM_REGS - XT_NUM_REGS] = {
+	{ "gpio_out", 0x00, 0, 32, &xtensa_user_reg_u32_type },
+	{ "accx_0", 0x01, 0, 32, &xtensa_user_reg_u32_type },
+	{ "accx_1", 0x02, 0, 32, &xtensa_user_reg_u32_type },
+	{ "qacc_h_0", 0x03, 0, 32, &xtensa_user_reg_u32_type },
+	{ "qacc_h_1", 0x04, 0, 32, &xtensa_user_reg_u32_type },
+	{ "qacc_h_2", 0x05, 0, 32, &xtensa_user_reg_u32_type },
+	{ "qacc_h_3", 0x06, 0, 32, &xtensa_user_reg_u32_type },
+	{ "qacc_h_4", 0x07, 0, 32, &xtensa_user_reg_u32_type },
+	{ "qacc_l_0", 0x08, 0, 32, &xtensa_user_reg_u32_type },
+	{ "qacc_l_1", 0x09, 0, 32, &xtensa_user_reg_u32_type },
+	{ "qacc_l_2", 0x0A, 0, 32, &xtensa_user_reg_u32_type },
+	{ "qacc_l_3", 0x0B, 0, 32, &xtensa_user_reg_u32_type },
+	{ "qacc_l_4", 0x0C, 0, 32, &xtensa_user_reg_u32_type },
+	{ "sar_byte", 0x0D, 0, 32, &xtensa_user_reg_u32_type },
+	{ "fft_bit_width", 0x0E, 0, 32, &xtensa_user_reg_u32_type },
+	{ "ua_state_0", 0x0F, 0, 32, &xtensa_user_reg_u32_type },
+	{ "ua_state_1", 0x10, 0, 32, &xtensa_user_reg_u32_type },
+	{ "ua_state_2", 0x11, 0, 32, &xtensa_user_reg_u32_type },
+	{ "ua_state_3", 0x12, 0, 32, &xtensa_user_reg_u32_type },
+	{ "q0", 0x13, 0, 128, &xtensa_user_reg_u128_type },
+	{ "q1", 0x14, 0, 128, &xtensa_user_reg_u128_type },
+	{ "q2", 0x15, 0, 128, &xtensa_user_reg_u128_type },
+	{ "q3", 0x16, 0, 128, &xtensa_user_reg_u128_type },
+	{ "q4", 0x17, 0, 128, &xtensa_user_reg_u128_type },
+	{ "q5", 0x18, 0, 128, &xtensa_user_reg_u128_type },
+	{ "q6", 0x19, 0, 128, &xtensa_user_reg_u128_type },
+	{ "q7", 0x20, 0, 128, &xtensa_user_reg_u128_type },
+};
+
+struct esp32s3_common {
+	struct esp_xtensa_smp_common esp_xtensa_smp;
+};
+
+static int esp32s3_fetch_user_regs(struct target *target);
+static int esp32s3_queue_write_dirty_user_regs(struct target *target);
+
+static const struct xtensa_config esp32s3_xtensa_cfg = {
+	.density = true,
+	.aregs_num = XT_AREGS_NUM_MAX,
+	.windowed = true,
+	.coproc = true,
+	.fp_coproc = true,
+	.loop = true,
+	.miscregs_num = 4,
+	.threadptr = true,
+	.boolean = true,
+	.reloc_vec = true,
+	.proc_id = true,
+	.cond_store = true,
+	.mac16 = true,
+	.user_regs_num = ARRAY_SIZE(esp32s3_user_regs),
+	.user_regs = esp32s3_user_regs,
+	.fetch_user_regs = esp32s3_fetch_user_regs,
+	.queue_write_dirty_user_regs = esp32s3_queue_write_dirty_user_regs,
+	.gdb_general_regs_num = ESP32_S3_NUM_REGS_G_COMMAND,
+	.gdb_regs_mapping = esp32s3_gdb_regs_mapping,
+	.irom = {
+		.count = 2,
+		.regions = {
+			{
+				.base = ESP32_S3_IROM_LOW,
+				.size = ESP32_S3_IROM_HIGH - ESP32_S3_IROM_LOW,
+				.access = XT_MEM_ACCESS_READ,
+			},
+			{
+				.base = ESP32_S3_IROM_MASK_LOW,
+				.size = ESP32_S3_IROM_MASK_HIGH - ESP32_S3_IROM_MASK_LOW,
+				.access = XT_MEM_ACCESS_READ,
+			}
+		}
+	},
+	.iram = {
+		.count = 2,
+		.regions = {
+			{
+				.base = ESP32_S3_IRAM_LOW,
+				.size = ESP32_S3_IRAM_HIGH - ESP32_S3_IRAM_LOW,
+				.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+			},
+			{
+				.base = ESP32_S3_RTC_IRAM_LOW,
+				.size = ESP32_S3_RTC_IRAM_HIGH - ESP32_S3_RTC_IRAM_LOW,
+				.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+			},
+		}
+	},
+	.drom = {
+		.count = 1,
+		.regions = {
+			{
+				.base = ESP32_S3_DROM_LOW,
+				.size = ESP32_S3_DROM_HIGH - ESP32_S3_DROM_LOW,
+				.access = XT_MEM_ACCESS_READ,
+			},
+		}
+	},
+	.dram = {
+		.count = 4,
+		.regions = {
+			{
+				.base = ESP32_S3_DRAM_LOW,
+				.size = ESP32_S3_DRAM_HIGH - ESP32_S3_DRAM_LOW,
+				.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+			},
+			{
+				.base = ESP32_S3_RTC_DRAM_LOW,
+				.size = ESP32_S3_RTC_DRAM_HIGH - ESP32_S3_RTC_DRAM_LOW,
+				.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+			},
+			{
+				.base = ESP32_S3_RTC_DATA_LOW,
+				.size = ESP32_S3_RTC_DATA_HIGH - ESP32_S3_RTC_DATA_LOW,
+				.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+			},
+			{
+				.base = ESP32_S3_SYS_RAM_LOW,
+				.size = ESP32_S3_SYS_RAM_HIGH - ESP32_S3_SYS_RAM_LOW,
+				.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+			},
+		}
+	},
+	.exc = {
+		.enabled = true,
+	},
+	.irq = {
+		.enabled = true,
+		.irq_num = 32,
+	},
+	.high_irq = {
+		.enabled = true,
+		.excm_level = 3,
+		.nmi_num = 1,
+	},
+	.tim_irq = {
+		.enabled = true,
+		.comp_num = 3,
+	},
+	.debug = {
+		.enabled = true,
+		.irq_level = 6,
+		.ibreaks_num = 2,
+		.dbreaks_num = 2,
+		.icount_sz = 32,
+	},
+	.trace = {
+		.enabled = true,
+		.mem_sz = ESP32_S3_TRACEMEM_BLOCK_SZ,
+	},
+};
+
+static int esp32s3_fetch_user_regs(struct target *target)
+{
+	LOG_DEBUG("%s: user regs fetching is not implemented!", target_name(target));
+	return ERROR_OK;
+}
+
+static int esp32s3_queue_write_dirty_user_regs(struct target *target)
+{
+	LOG_DEBUG("%s: user regs writing is not implemented!", target_name(target));
+	return ERROR_OK;
+}
+
+/* Reset ESP32-S3's peripherals.
+ * 1. OpenOCD makes sure the target is halted; if not, tries to halt it.
+ *    If that fails, tries to reset it (via OCD) and then halt.
+ * 2. OpenOCD loads the stub code into RTC_SLOW_MEM.
+ * 3. Executes the stub code from address 0x50000004.
+ * 4. The stub code changes the reset vector to 0x50000000, and triggers
+ *    a system reset using RTC_CNTL_SW_SYS_RST bit.
+ * 5. Once the PRO CPU is out of reset, it executes the stub code from address 0x50000000.
+ *    The stub code disables the watchdog, re-enables JTAG and the APP CPU,
+ *    restores the reset vector, and enters an infinite loop.
+ * 6. OpenOCD waits until it can talk to the OCD module again, then halts the target.
+ * 7. OpenOCD restores the contents of RTC_SLOW_MEM.
+ *
+ * End result: all the peripherals except RTC_CNTL are reset, CPU's PC is undefined,
+ * PRO CPU is halted, APP CPU is in reset.
+ */
+
+const uint8_t esp32s3_reset_stub_code[] = {
+#include "../../../contrib/loaders/reset/espressif/esp32s3/cpu_reset_handler_code.inc"
+};
+
+static int esp32s3_soc_reset(struct target *target)
+{
+	int res;
+	struct target_list *head;
+	struct xtensa *xtensa;
+
+	LOG_DEBUG("start");
+	/* In order to write to peripheral registers, target must be halted first */
+	if (target->state != TARGET_HALTED) {
+		LOG_DEBUG("Target not halted before SoC reset, trying to halt it first");
+		xtensa_halt(target);
+		res = target_wait_state(target, TARGET_HALTED, 1000);
+		if (res != ERROR_OK) {
+			LOG_DEBUG("Couldn't halt target before SoC reset, trying to do reset-halt");
+			res = xtensa_assert_reset(target);
+			if (res != ERROR_OK) {
+				LOG_ERROR(
+					"Couldn't halt target before SoC reset! (xtensa_assert_reset returned %d)",
+					res);
+				return res;
+			}
+			alive_sleep(10);
+			xtensa_poll(target);
+			bool reset_halt_save = target->reset_halt;
+			target->reset_halt = true;
+			res = xtensa_deassert_reset(target);
+			target->reset_halt = reset_halt_save;
+			if (res != ERROR_OK) {
+				LOG_ERROR(
+					"Couldn't halt target before SoC reset! (xtensa_deassert_reset returned %d)",
+					res);
+				return res;
+			}
+			alive_sleep(10);
+			xtensa_poll(target);
+			xtensa_halt(target);
+			res = target_wait_state(target, TARGET_HALTED, 1000);
+			if (res != ERROR_OK) {
+				LOG_ERROR("Couldn't halt target before SoC reset");
+				return res;
+			}
+		}
+	}
+
+	if (target->smp) {
+		foreach_smp_target(head, target->smp_targets) {
+			xtensa = target_to_xtensa(head->target);
+			/* if any of the cores is stalled unstall them */
+			if (xtensa_dm_core_is_stalled(&xtensa->dbg_mod)) {
+				LOG_TARGET_DEBUG(head->target, "Unstall CPUs before SW reset!");
+				res = target_write_u32(target,
+					ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG,
+					ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF);
+				if (res != ERROR_OK) {
+					LOG_TARGET_ERROR(head->target, "Failed to unstall CPUs before SW reset!");
+					return res;
+				}
+				break;	/* both cores are unstalled now, so exit the loop */
+			}
+		}
+	}
+
+	LOG_DEBUG("Loading stub code into RTC RAM");
+	uint8_t slow_mem_save[sizeof(esp32s3_reset_stub_code)];
+
+	/* Save contents of RTC_SLOW_MEM which we are about to overwrite */
+	res = target_read_buffer(target, ESP32_S3_RTC_SLOW_MEM_BASE, sizeof(slow_mem_save), slow_mem_save);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to save contents of RTC_SLOW_MEM (%d)!", res);
+		return res;
+	}
+
+	/* Write stub code into RTC_SLOW_MEM */
+	res = target_write_buffer(target,
+		ESP32_S3_RTC_SLOW_MEM_BASE,
+		sizeof(esp32s3_reset_stub_code),
+		esp32s3_reset_stub_code);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to write stub (%d)!", res);
+		return res;
+	}
+
+	LOG_DEBUG("Resuming the target");
+	xtensa = target_to_xtensa(target);
+	xtensa->suppress_dsr_errors = true;
+	res = xtensa_resume(target, 0, ESP32_S3_RTC_SLOW_MEM_BASE + 4, 0, 0);
+	xtensa->suppress_dsr_errors = false;
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to run stub (%d)!", res);
+		return res;
+	}
+	LOG_DEBUG("resume done, waiting for the target to come alive");
+
+	/* Wait for SoC to reset */
+	alive_sleep(100);
+	int64_t timeout = timeval_ms() + 100;
+	bool get_timeout = false;
+	while (target->state != TARGET_RESET && target->state != TARGET_RUNNING) {
+		alive_sleep(10);
+		xtensa_poll(target);
+		if (timeval_ms() >= timeout) {
+			LOG_TARGET_ERROR(target,
+				"Timed out waiting for CPU to be reset, target state=%d",
+				target->state);
+			get_timeout = true;
+			break;
+		}
+	}
+
+	/* Halt the CPU again */
+	LOG_DEBUG("halting the target");
+	xtensa_halt(target);
+	res = target_wait_state(target, TARGET_HALTED, 1000);
+	if (res == ERROR_OK) {
+		LOG_DEBUG("restoring RTC_SLOW_MEM");
+		res = target_write_buffer(target, ESP32_S3_RTC_SLOW_MEM_BASE, sizeof(slow_mem_save), slow_mem_save);
+		if (res != ERROR_OK)
+			LOG_TARGET_ERROR(target, "Failed to restore contents of RTC_SLOW_MEM (%d)!", res);
+	} else {
+		LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be halted after SoC reset");
+	}
+
+	return get_timeout ? ERROR_TARGET_TIMEOUT : res;
+}
+
+static int esp32s3_disable_wdts(struct target *target)
+{
+	/* TIMG1 WDT */
+	int res = target_write_u32(target, ESP32_S3_TIMG0WDT_PROTECT, ESP32_S3_WDT_WKEY_VALUE);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to write ESP32_S3_TIMG0WDT_PROTECT (%d)!", res);
+		return res;
+	}
+	res = target_write_u32(target, ESP32_S3_TIMG0WDT_CFG0, 0);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to write ESP32_S3_TIMG0WDT_CFG0 (%d)!", res);
+		return res;
+	}
+	/* TIMG2 WDT */
+	res = target_write_u32(target, ESP32_S3_TIMG1WDT_PROTECT, ESP32_S3_WDT_WKEY_VALUE);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to write ESP32_S3_TIMG1WDT_PROTECT (%d)!", res);
+		return res;
+	}
+	res = target_write_u32(target, ESP32_S3_TIMG1WDT_CFG0, 0);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to write ESP32_S3_TIMG1WDT_CFG0 (%d)!", res);
+		return res;
+	}
+	/* RTC WDT */
+	res = target_write_u32(target, ESP32_S3_RTCWDT_PROTECT, ESP32_S3_WDT_WKEY_VALUE);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to write ESP32_S3_RTCWDT_PROTECT (%d)!", res);
+		return res;
+	}
+	res = target_write_u32(target, ESP32_S3_RTCWDT_CFG, 0);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to write ESP32_S3_RTCWDT_CFG (%d)!", res);
+		return res;
+	}
+	/* Enable SWD auto-feed */
+	res = target_write_u32(target, ESP32_S3_SWD_WPROTECT_REG, ESP32_S3_SWD_WKEY_VALUE);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to write ESP32_S3_SWD_WPROTECT_REG (%d)!", res);
+		return res;
+	}
+	uint32_t swd_conf_reg = 0;
+	res = target_read_u32(target, ESP32_S3_SWD_CONF_REG, &swd_conf_reg);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to read ESP32_S3_SWD_CONF_REG (%d)!", res);
+		return res;
+	}
+	swd_conf_reg |= ESP32_S3_SWD_AUTO_FEED_EN_M;
+	res = target_write_u32(target, ESP32_S3_SWD_CONF_REG, swd_conf_reg);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to write ESP32_S3_SWD_CONF_REG (%d)!", res);
+		return res;
+	}
+	return ERROR_OK;
+}
+
+static int esp32s3_on_halt(struct target *target)
+{
+	return esp32s3_disable_wdts(target);
+}
+
+static int esp32s3_arch_state(struct target *target)
+{
+	return ERROR_OK;
+}
+
+static int esp32s3_virt2phys(struct target *target,
+	target_addr_t virtual, target_addr_t *physical)
+{
+	if (physical) {
+		*physical = virtual;
+		return ERROR_OK;
+	}
+	return ERROR_FAIL;
+}
+
+
+static int esp32s3_target_init(struct command_context *cmd_ctx, struct target *target)
+{
+	return esp_xtensa_target_init(cmd_ctx, target);
+}
+
+static const struct xtensa_debug_ops esp32s3_dbg_ops = {
+	.queue_enable = xtensa_dm_queue_enable,
+	.queue_reg_read = xtensa_dm_queue_reg_read,
+	.queue_reg_write = xtensa_dm_queue_reg_write
+};
+
+static const struct xtensa_power_ops esp32s3_pwr_ops = {
+	.queue_reg_read = xtensa_dm_queue_pwr_reg_read,
+	.queue_reg_write = xtensa_dm_queue_pwr_reg_write
+};
+
+static const struct esp_xtensa_smp_chip_ops esp32s3_chip_ops = {
+	.reset = esp32s3_soc_reset,
+	.on_halt = esp32s3_on_halt
+};
+
+static int esp32s3_target_create(struct target *target, Jim_Interp *interp)
+{
+	struct xtensa_debug_module_config esp32s3_dm_cfg = {
+		.dbg_ops = &esp32s3_dbg_ops,
+		.pwr_ops = &esp32s3_pwr_ops,
+		.tap = target->tap,
+		.queue_tdi_idle = NULL,
+		.queue_tdi_idle_arg = NULL
+	};
+
+	struct esp32s3_common *esp32s3 = calloc(1, sizeof(struct esp32s3_common));
+	if (!esp32s3) {
+		LOG_ERROR("Failed to alloc memory for arch info!");
+		return ERROR_FAIL;
+	}
+
+	int ret = esp_xtensa_smp_init_arch_info(target,
+		&esp32s3->esp_xtensa_smp,
+		&esp32s3_xtensa_cfg,
+		&esp32s3_dm_cfg,
+		&esp32s3_chip_ops);
+	if (ret != ERROR_OK) {
+		LOG_ERROR("Failed to init arch info!");
+		free(esp32s3);
+		return ret;
+	}
+
+	/* Assume running target. If different, the first poll will fix this. */
+	target->state = TARGET_RUNNING;
+	target->debug_reason = DBG_REASON_NOTHALTED;
+	return ERROR_OK;
+}
+
+static const struct command_registration esp32s3_command_handlers[] = {
+	{
+		.usage = "",
+		.chain = esp_xtensa_smp_command_handlers,
+	},
+	{
+		.name = "esp32",
+		.usage = "",
+		.chain = smp_command_handlers,
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
+/** Holds methods for Xtensa targets. */
+struct target_type esp32s3_target = {
+	.name = "esp32s3",
+
+	.poll = esp_xtensa_smp_poll,
+	.arch_state = esp32s3_arch_state,
+
+	.halt = xtensa_halt,
+	.resume = esp_xtensa_smp_resume,
+	.step = esp_xtensa_smp_step,
+
+	.assert_reset = esp_xtensa_smp_assert_reset,
+	.deassert_reset = esp_xtensa_smp_deassert_reset,
+	.soft_reset_halt = esp_xtensa_smp_soft_reset_halt,
+
+	.virt2phys = esp32s3_virt2phys,
+	.mmu = xtensa_mmu_is_enabled,
+	.read_memory = xtensa_read_memory,
+	.write_memory = xtensa_write_memory,
+
+	.read_buffer = xtensa_read_buffer,
+	.write_buffer = xtensa_write_buffer,
+
+	.checksum_memory = xtensa_checksum_memory,
+
+	.get_gdb_arch = xtensa_get_gdb_arch,
+	.get_gdb_reg_list = xtensa_get_gdb_reg_list,
+
+	.add_breakpoint = esp_xtensa_breakpoint_add,
+	.remove_breakpoint = esp_xtensa_breakpoint_remove,
+
+	.add_watchpoint = esp_xtensa_smp_watchpoint_add,
+	.remove_watchpoint = esp_xtensa_smp_watchpoint_remove,
+
+	.target_create = esp32s3_target_create,
+	.init_target = esp32s3_target_init,
+	.examine = xtensa_examine,
+	.deinit_target = esp_xtensa_target_deinit,
+
+	.commands = esp32s3_command_handlers,
+};
diff --git a/src/target/espressif/esp32s3.h b/src/target/espressif/esp32s3.h
new file mode 100644
index 000000000..0ba110115
--- /dev/null
+++ b/src/target/espressif/esp32s3.h
@@ -0,0 +1,65 @@
+/***************************************************************************
+ *   ESP32-S3 target for OpenOCD                                           *
+ *   Copyright (C) 2020 Espressif Systems Ltd.                             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifndef OPENOCD_TARGET_ESP32S3_H
+#define OPENOCD_TARGET_ESP32S3_H
+
+#include <target/xtensa/xtensa_regs.h>
+
+#define ESP32_S3_DROM_LOW             0x3C000000
+#define ESP32_S3_DROM_HIGH            0x3D000000
+#define ESP32_S3_IROM_LOW             0x42000000
+#define ESP32_S3_IROM_HIGH            0x44000000
+
+/*Number of registers returned directly by the G command
+ *Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
+#define ESP32_S3_NUM_REGS_G_COMMAND   128
+
+enum esp32s3_reg_id {
+	/* chip specific registers that extend ISA go after ISA-defined ones */
+	ESP32_S3_REG_IDX_GPIOOUT = XT_NUM_REGS,
+	ESP32_S3_REG_IDX_ACCX_0,
+	ESP32_S3_REG_IDX_ACCX_1,
+	ESP32_S3_REG_IDX_QACC_H_0,
+	ESP32_S3_REG_IDX_QACC_H_1,
+	ESP32_S3_REG_IDX_QACC_H_2,
+	ESP32_S3_REG_IDX_QACC_H_3,
+	ESP32_S3_REG_IDX_QACC_H_4,
+	ESP32_S3_REG_IDX_QACC_L_0,
+	ESP32_S3_REG_IDX_QACC_L_1,
+	ESP32_S3_REG_IDX_QACC_L_2,
+	ESP32_S3_REG_IDX_QACC_L_3,
+	ESP32_S3_REG_IDX_QACC_L_4,
+	ESP32_S3_REG_IDX_SAR_BYTE,
+	ESP32_S3_REG_IDX_FFT_BIT_WIDTH,
+	ESP32_S3_REG_IDX_UA_STATE_0,
+	ESP32_S3_REG_IDX_UA_STATE_1,
+	ESP32_S3_REG_IDX_UA_STATE_2,
+	ESP32_S3_REG_IDX_UA_STATE_3,
+	ESP32_S3_REG_IDX_Q0,
+	ESP32_S3_REG_IDX_Q1,
+	ESP32_S3_REG_IDX_Q2,
+	ESP32_S3_REG_IDX_Q3,
+	ESP32_S3_REG_IDX_Q4,
+	ESP32_S3_REG_IDX_Q5,
+	ESP32_S3_REG_IDX_Q6,
+	ESP32_S3_REG_IDX_Q7,
+	ESP32_S3_NUM_REGS,
+};
+
+#endif	/* OPENOCD_TARGET_ESP32S3_H */
diff --git a/src/target/target.c b/src/target/target.c
index ea49b7972..c9ad5fc65 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -107,6 +107,7 @@ extern struct target_type nds32_v3_target;
 extern struct target_type nds32_v3m_target;
 extern struct target_type esp32_target;
 extern struct target_type esp32s2_target;
+extern struct target_type esp32s3_target;
 extern struct target_type or1k_target;
 extern struct target_type quark_x10xx_target;
 extern struct target_type quark_d20xx_target;
@@ -145,6 +146,7 @@ static struct target_type *target_types[] = {
 	&nds32_v3m_target,
 	&esp32_target,
 	&esp32s2_target,
+	&esp32s3_target,
 	&or1k_target,
 	&quark_x10xx_target,
 	&quark_d20xx_target,
diff --git a/tcl/board/esp32s3-ftdi.cfg b/tcl/board/esp32s3-ftdi.cfg
new file mode 100644
index 000000000..60706646d
--- /dev/null
+++ b/tcl/board/esp32s3-ftdi.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-S3 connected via ESP-Prog.
+#
+# For example, OpenOCD can be started for ESP32-S3 debugging on
+#
+#   openocd -f board/esp32s3-ftdi.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+# Source the ESP32-S3 configuration file
+source [find target/esp32s3.cfg]
+
+# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+#
+# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter speed 20000
diff --git a/tcl/target/esp32s3.cfg b/tcl/target/esp32s3.cfg
new file mode 100644
index 000000000..0570501c7
--- /dev/null
+++ b/tcl/target/esp32s3.cfg
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# The ESP32-S3 only supports JTAG.
+transport select jtag
+
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+source [find bitsbytes.tcl]
+source [find memory.tcl]
+source [find mmr_helpers.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME esp32s3
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x120034e5
+}
+
+if { [info exists ESP32_S3_ONLYCPU] } {
+	set _ONLYCPU $ESP32_S3_ONLYCPU
+} else {
+	set _ONLYCPU 2
+}
+
+set _CPU0NAME cpu0
+set _CPU1NAME cpu1
+set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME
+set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME
+
+jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID
+if { $_ONLYCPU != 1 } {
+	jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID
+} else {
+	jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID
+}
+
+proc esp32s3_memprot_is_enabled { } {
+	# TODO: after https://review.openocd.org/c/openocd/+/7016 merged
+	return 0
+}
+
+# PRO-CPU
+target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0
+# APP-CPU
+if { $_ONLYCPU != 1 } {
+	target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1
+	target smp $_TARGETNAME_0 $_TARGETNAME_1
+}
+
+$_TARGETNAME_0 xtensa maskisr on
+$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
+
+$_TARGETNAME_0 configure -event gdb-attach {
+	$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
+	# necessary to auto-probe flash bank when GDB is connected
+	halt 1000
+	if { [esp32s3_memprot_is_enabled] } {
+		# 'reset halt' to disable memory protection and allow flasher to work correctly
+		echo "Memory protection is enabled. Reset target to disable it..."
+		reset halt
+    }
+}
+$_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt }
+
+if { $_ONLYCPU != 1 } {
+	$_TARGETNAME_1 configure -event gdb-attach {
+		$_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
+		# necessary to auto-probe flash bank when GDB is connected
+		halt 1000
+		if { [esp32s3_memprot_is_enabled] } {
+			# 'reset halt' to disable memory protection and allow flasher to work correctly
+			echo "Memory protection is enabled. Reset target to disable it..."
+			reset halt
+		}
+	}
+	$_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt }
+}
+
+gdb_breakpoint_override hard

-----------------------------------------------------------------------

Summary of changes:
 .../reset/espressif/{esp32 => esp32s3}/Makefile    |   6 +-
 .../espressif/esp32s3/cpu_reset_handler_code.inc   |  17 +
 .../esp32s3_cpu_reset_handler.S}                   |  73 +--
 doc/openocd.texi                                   |   1 +
 src/target/espressif/Makefile.am                   |   6 +-
 src/target/espressif/{esp32.c => esp32s3.c}        | 539 ++++++++++-----------
 src/target/espressif/esp32s3.h                     |  65 +++
 src/target/target.c                                |   2 +
 ...{esp32-wrover-kit-1.8v.cfg => esp32s3-ftdi.cfg} |  11 +-
 tcl/target/{esp32.cfg => esp32s3.cfg}              |  37 +-
 10 files changed, 409 insertions(+), 348 deletions(-)
 copy contrib/loaders/reset/espressif/{esp32 => esp32s3}/Makefile (89%)
 create mode 100644 contrib/loaders/reset/espressif/esp32s3/cpu_reset_handler_code.inc
 copy contrib/loaders/reset/espressif/{esp32/esp32_cpu_reset_handler.S => esp32s3/esp32s3_cpu_reset_handler.S} (67%)
 copy src/target/espressif/{esp32.c => esp32s3.c} (50%)
 create mode 100644 src/target/espressif/esp32s3.h
 copy tcl/board/{esp32-wrover-kit-1.8v.cfg => esp32s3-ftdi.cfg} (65%)
 copy tcl/target/{esp32.cfg => esp32s3.cfg} (66%)


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From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:46:44

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The branch, master has been updated
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      from  52fbb85d2e0911fa1500708a5841d3474c1c0289 (commit)

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- Log -----------------------------------------------------------------
commit 77287b8d47b4be8ee5612037fe1eba6f0e08147f
Author: Erhan Kurubas <erh...@es...>
Date:   Sat May 21 23:49:54 2022 +0200

    target: add Espressif ESP32 basic support
    
    ESP32 is a dual core Xtensa SoC
    Not full featured yet. Some of the missing functionality:
    -Semihosting
    -Flash breakpoints
    -Flash loader
    -Apptrace
    -FreeRTOS
    
    Signed-off-by: Erhan Kurubas <erh...@es...>
    Change-Id: I76fb184aa38ab9f4e30290c038b5ff8850060750
    Reviewed-on: https://review.openocd.org/c/openocd/+/6989
    Tested-by: jenkins
    Reviewed-by: Ian Thompson <ia...@ca...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/contrib/loaders/reset/espressif/common.mk b/contrib/loaders/reset/espressif/common.mk
new file mode 100644
index 000000000..4623583aa
--- /dev/null
+++ b/contrib/loaders/reset/espressif/common.mk
@@ -0,0 +1,51 @@
+# ESP32 Makefile to compile the SoC reset program
+# Copyright (C) 2022 Espressif Systems Ltd.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>
+
+# Pass V=1 to see the commands being executed by make
+ifneq ("$(V)","1")
+Q = @
+endif
+
+BIN2C = ../../../../../src/helper/bin2char.sh
+
+APP = cpu_reset_handler
+
+BUILD_DIR = build
+
+APP_OBJ = $(BUILD_DIR)/$(APP).o
+APP_BIN = $(BUILD_DIR)/$(APP)_code.bin
+APP_CODE = $(APP)_code.inc
+
+CFLAGS += -mtext-section-literals
+
+.PHONY: all cleanxten
+
+all: $(BUILD_DIR) $(APP_OBJ) $(APP_CODE)
+
+$(BUILD_DIR):
+	$(Q) mkdir $@
+
+$(APP_OBJ): $(SRCS)
+	@echo "  CC   $^ -> $@"
+	$(Q) $(CROSS)gcc -c $(CFLAGS)  -o $@ $^
+
+$(APP_CODE): $(APP_OBJ)
+	@echo "  CC   $^ -> $@"
+	$(Q) $(CROSS)objcopy -O binary -j.text $^ $(APP_BIN)
+	$(Q) $(BIN2C) < $(APP_BIN) > $@
+
+clean:
+	$(Q) rm -rf $(BUILD_DIR)
diff --git a/contrib/loaders/reset/espressif/esp32/Makefile b/contrib/loaders/reset/espressif/esp32/Makefile
new file mode 100644
index 000000000..3551b6a5e
--- /dev/null
+++ b/contrib/loaders/reset/espressif/esp32/Makefile
@@ -0,0 +1,31 @@
+# ESP32 Makefile to compile the SoC reset program
+# Copyright (C) 2022 Espressif Systems Ltd.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>
+
+# Prefix for ESP32 cross compilers (can include a directory path)
+CROSS ?= xtensa-esp32-elf-
+
+APP_ARCH := xtensa
+APP_CHIP := ESP32
+APP_CHIP_PATH := $(shell pwd)
+SRCS := $(APP_CHIP_PATH)/esp32_cpu_reset_handler.S
+
+CFLAGS :=
+LDFLAGS :=
+
+INCLUDES :=
+DEFINES :=
+
+include ../common.mk
diff --git a/contrib/loaders/reset/espressif/esp32/cpu_reset_handler_code.inc b/contrib/loaders/reset/espressif/esp32/cpu_reset_handler_code.inc
new file mode 100644
index 000000000..57ee12d19
--- /dev/null
+++ b/contrib/loaders/reset/espressif/esp32/cpu_reset_handler_code.inc
@@ -0,0 +1,15 @@
+/* Autogenerated with ../../../../../src/helper/bin2char.sh */
+0x06,0x1e,0x00,0x00,0x06,0x14,0x00,0x00,0x34,0x80,0xf4,0x3f,0xb0,0x80,0xf4,0x3f,
+0xb4,0x80,0xf4,0x3f,0x70,0x80,0xf4,0x3f,0x10,0x22,0x00,0x00,0x00,0x20,0x49,0x9c,
+0x00,0x80,0xf4,0x3f,0xa1,0x3a,0xd8,0x50,0xa4,0x80,0xf4,0x3f,0x64,0xf0,0xf5,0x3f,
+0x64,0x00,0xf6,0x3f,0x8c,0x80,0xf4,0x3f,0x48,0xf0,0xf5,0x3f,0x48,0x00,0xf6,0x3f,
+0xfc,0xa1,0xf5,0x3f,0x38,0x00,0xf0,0x3f,0x30,0x00,0xf0,0x3f,0x2c,0x00,0xf0,0x3f,
+0x34,0x80,0xf4,0x3f,0x00,0x30,0x00,0x00,0x50,0x55,0x30,0x41,0xeb,0xff,0x59,0x04,
+0x41,0xeb,0xff,0x59,0x04,0x41,0xea,0xff,0x59,0x04,0x41,0xea,0xff,0x31,0xea,0xff,
+0x39,0x04,0x31,0xea,0xff,0x41,0xea,0xff,0x39,0x04,0x00,0x00,0x60,0xeb,0x03,0x60,
+0x61,0x04,0x56,0x66,0x04,0x50,0x55,0x30,0x31,0xe7,0xff,0x41,0xe7,0xff,0x39,0x04,
+0x41,0xe7,0xff,0x39,0x04,0x41,0xe6,0xff,0x39,0x04,0x41,0xe6,0xff,0x59,0x04,0x41,
+0xe6,0xff,0x59,0x04,0x41,0xe6,0xff,0x59,0x04,0x41,0xe5,0xff,0x59,0x04,0x41,0xe5,
+0xff,0x59,0x04,0x41,0xe5,0xff,0x0c,0x13,0x39,0x04,0x41,0xe4,0xff,0x0c,0x13,0x39,
+0x04,0x59,0x04,0x41,0xe3,0xff,0x31,0xe3,0xff,0x32,0x64,0x00,0x00,0x70,0x00,0x46,
+0xfe,0xff,
diff --git a/contrib/loaders/reset/espressif/esp32/esp32_cpu_reset_handler.S b/contrib/loaders/reset/espressif/esp32/esp32_cpu_reset_handler.S
new file mode 100644
index 000000000..113254556
--- /dev/null
+++ b/contrib/loaders/reset/espressif/esp32/esp32_cpu_reset_handler.S
@@ -0,0 +1,145 @@
+/***************************************************************************
+ *   Reset stub used by esp32 target                                       *
+ *   Copyright (C) 2017 Espressif Systems Ltd.                             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#define RTC_CNTL_RESET_STATE_REG    0x3ff48034
+#define RTC_CNTL_RESET_STATE_DEF    0x3000
+#define RTC_CNTL_CLK_CONF_REG       0x3ff48070
+#define RTC_CNTL_CLK_CONF_DEF       0x2210
+#define RTC_CNTL_STORE4_REG         0x3ff480b0
+#define RTC_CNTL_STORE5_REG         0x3ff480b4
+#define WDT_WKEY_VALUE              0x50D83AA1
+#define TIMG0_WDTWPROTECT_REG       0x3ff5f064
+#define TIMG0_WDTCONFIG0_REG        0x3ff5f048
+#define TIMG1_WDTWPROTECT_REG       0x3FF60064
+#define TIMG1_WDTCONFIG0_REG        0x3ff60048
+#define RTC_CNTL_WDTCONFIG0_REG     0x3ff4808c
+#define RTC_CNTL_WDTWPROTECT_REG    0x3ff480a4
+#define JTAG_ENABLE_REG             0x3ff5a1fc
+#define RTC_CNTL_OPTIONS0_REG       0x3ff48000
+#define RTC_CNTL_OPTIONS0_DEF       0x1c492000
+#define RTC_CNTL_SW_SYS_RST         0x80000000
+#define DPORT_APPCPU_CTRL_A_REG     0x3ff0002c
+#define DPORT_APPCPU_RST_EN         0x1
+#define DPORT_APPCPU_CTRL_B_REG     0x3ff00030
+#define DPORT_APPCPU_CLKGATE_EN     0x1
+#define DPORT_APPCPU_CTRL_C_REG     0x3ff00034
+#define DPORT_APPCPU_CTRL_D_REG     0x3ff00038
+
+
+/* This stub is copied to RTC_SLOW_MEM by OpenOCD, and the CPU starts executing
+ * it instead of the ROM code (0x40000400). This stub disables watchdogs and
+ * goes into a loop.
+ * OpenOCD will then halt the target and perform CPU reset using OCD.
+ */
+
+
+/* Has to be at offset 0. This is the entry point of the CPU, once
+ * RTC_CNTL_PROCPU_STAT_VECTOR_SEL is cleared.
+ * CPU will come here after the system reset, triggered by RTC_CNTL_SW_SYS_RST.
+ */
+    .global     cpu_at_start_handler
+    .type       cpu_at_start_handler,@function
+    .align      4
+cpu_at_start_handler:
+    j start
+
+
+/* Has to be at offset 4. Once the stub code has been uploaded into RTC Slow
+ * memory, OpenOCD will set the PC to this address, and resume execution.
+ * The stub will then jump to 'reset' label and perform the reset.
+ */
+    .global     cpu_reset_handler
+    .type       cpu_reset_handler,@function
+    .align      4
+cpu_reset_handler:
+    j reset
+
+    .align 4
+    .literal_position
+
+    .align 4
+reset:
+    /* Use a5 as a zero register */
+    xor a5, a5, a5
+    /* Select static reset vector 0 (XCHAL_RESET_VECTOR0_VADDR, 0x50000000) */
+    movi a4, RTC_CNTL_RESET_STATE_REG
+    s32i a5, a4, 0
+    /* Set some clock-related RTC registers to the default values */
+    movi a4, RTC_CNTL_STORE4_REG
+    s32i a5, a4, 0
+    movi a4, RTC_CNTL_STORE5_REG
+    s32i a5, a4, 0
+    movi a4, RTC_CNTL_CLK_CONF_REG
+    movi a3, RTC_CNTL_CLK_CONF_DEF
+    s32i a3, a4, 0
+    /* Reset the digital part of the chip (RTC controller doesn't get reset) */
+    movi a3, (RTC_CNTL_OPTIONS0_DEF | RTC_CNTL_SW_SYS_RST)
+    movi a4, RTC_CNTL_OPTIONS0_REG
+    s32i a3, a4, 0
+    /* Doesn't reach beyond this instruction */
+
+    .align 4
+start:
+    /* If running on the APP CPU, skip directly to the parking loop */
+    rsr.prid a6
+    extui a6, a6, 1, 1
+    bnez a6, parking_loop
+
+    /* Use a5 as a zero register */
+    xor a5, a5, a5
+    /* Disable the watchdogs */
+    movi a3, WDT_WKEY_VALUE
+    movi a4, RTC_CNTL_WDTWPROTECT_REG
+    s32i.n a3, a4, 0
+    movi a4, TIMG0_WDTWPROTECT_REG
+    s32i.n a3, a4, 0
+    movi a4, TIMG1_WDTWPROTECT_REG
+    s32i.n a3, a4, 0
+    movi a4, RTC_CNTL_WDTCONFIG0_REG
+    s32i.n a5, a4, 0
+    movi a4, TIMG0_WDTCONFIG0_REG
+    s32i.n a5, a4, 0
+    movi a4, TIMG1_WDTCONFIG0_REG
+    s32i.n a5, a4, 0
+    /* Enable JTAG (needed since rev. 3) */
+    movi a4, JTAG_ENABLE_REG
+    s32i.n a5, a4, 0
+    /* Clear APP_CPU boot address */
+    movi a4, DPORT_APPCPU_CTRL_D_REG
+    s32i.n a5, a4, 0
+    /* Clear APP_CPU clock gating */
+    movi a4, DPORT_APPCPU_CTRL_B_REG
+    movi a3, DPORT_APPCPU_CLKGATE_EN
+    s32i.n a3, a4, 0
+    /* Set and clear APP_CPU reset */
+    movi a4, DPORT_APPCPU_CTRL_A_REG
+    movi a3, DPORT_APPCPU_RST_EN
+    s32i.n a3, a4, 0
+    s32i.n a5, a4, 0
+    /* Restore the reset vector to ROM */
+    movi a4, RTC_CNTL_RESET_STATE_REG
+    movi a3, RTC_CNTL_RESET_STATE_DEF
+    s32i.n a3, a4, 0
+
+
+parking_loop:
+    /* PRO and APP CPU will be in this loop, until OpenOCD
+     * finds the JTAG taps and puts the CPUs into debug mode.
+     */
+    waiti 0
+    j parking_loop
diff --git a/doc/openocd.texi b/doc/openocd.texi
index b328370e4..2661e46e7 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4913,6 +4913,7 @@ compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
 @item @code{dsp5680xx} -- implements Freescale's 5680x DSP.
 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
 The current implementation supports eSi-32xx cores.
+@item @code{esp32} -- this is an Espressif SoC with dual Xtensa cores.
 @item @code{esp32s2} -- this is an Espressif SoC with single Xtensa core.
 @item @code{fa526} -- resembles arm920 (w/o Thumb).
 @item @code{feroceon} -- resembles arm926.
diff --git a/src/target/espressif/Makefile.am b/src/target/espressif/Makefile.am
index c681e09aa..2a9045b8a 100644
--- a/src/target/espressif/Makefile.am
+++ b/src/target/espressif/Makefile.am
@@ -2,5 +2,9 @@ noinst_LTLIBRARIES += %D%/libespressif.la
 %C%_libespressif_la_SOURCES = \
        %D%/esp_xtensa.c \
        %D%/esp_xtensa.h \
+       %D%/esp_xtensa_smp.c \
+       %D%/esp_xtensa_smp.h \
        %D%/esp32s2.c \
-       %D%/esp32s2.h
+       %D%/esp32s2.h \
+       %D%/esp32.c \
+       %D%/esp32.h
diff --git a/src/target/espressif/esp32.c b/src/target/espressif/esp32.c
new file mode 100644
index 000000000..9d5099be0
--- /dev/null
+++ b/src/target/espressif/esp32.c
@@ -0,0 +1,704 @@
+/***************************************************************************
+ *   ESP32 target API for OpenOCD                                          *
+ *   Copyright (C) 2016-2019 Espressif Systems Ltd.                        *
+ *   Author: Dmitry Yakovlev <dm...@es...>                        *
+ *   Author: Alexey Gerenkov <al...@es...>                        *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <helper/time_support.h>
+#include <target/target.h>
+#include <target/target_type.h>
+#include <target/smp.h>
+#include "assert.h"
+#include "esp32.h"
+#include "esp_xtensa_smp.h"
+
+/*
+This is a JTAG driver for the ESP32, the are two Tensilica cores inside
+the ESP32 chip. For more information please have a look into ESP32 target
+implementation.
+*/
+
+/* ESP32 memory map */
+#define ESP32_DRAM_LOW            0x3ffae000
+#define ESP32_DRAM_HIGH           0x40000000
+#define ESP32_IROM_MASK_LOW       0x40000000
+#define ESP32_IROM_MASK_HIGH      0x40064f00
+#define ESP32_IRAM_LOW            0x40070000
+#define ESP32_IRAM_HIGH           0x400a0000
+#define ESP32_RTC_IRAM_LOW        0x400c0000
+#define ESP32_RTC_IRAM_HIGH       0x400c2000
+#define ESP32_RTC_DRAM_LOW        0x3ff80000
+#define ESP32_RTC_DRAM_HIGH       0x3ff82000
+#define ESP32_RTC_DATA_LOW        0x50000000
+#define ESP32_RTC_DATA_HIGH       0x50002000
+#define ESP32_EXTRAM_DATA_LOW     0x3f800000
+#define ESP32_EXTRAM_DATA_HIGH    0x3fc00000
+#define ESP32_DR_REG_LOW          0x3ff00000
+#define ESP32_DR_REG_HIGH         0x3ff71000
+#define ESP32_SYS_RAM_LOW         0x60000000UL
+#define ESP32_SYS_RAM_HIGH        (ESP32_SYS_RAM_LOW + 0x20000000UL)
+#define ESP32_RTC_SLOW_MEM_BASE   ESP32_RTC_DATA_LOW
+
+/* ESP32 WDT */
+#define ESP32_WDT_WKEY_VALUE       0x50d83aa1
+#define ESP32_TIMG0_BASE           0x3ff5f000
+#define ESP32_TIMG1_BASE           0x3ff60000
+#define ESP32_TIMGWDT_CFG0_OFF     0x48
+#define ESP32_TIMGWDT_PROTECT_OFF  0x64
+#define ESP32_TIMG0WDT_CFG0        (ESP32_TIMG0_BASE + ESP32_TIMGWDT_CFG0_OFF)
+#define ESP32_TIMG1WDT_CFG0        (ESP32_TIMG1_BASE + ESP32_TIMGWDT_CFG0_OFF)
+#define ESP32_TIMG0WDT_PROTECT     (ESP32_TIMG0_BASE + ESP32_TIMGWDT_PROTECT_OFF)
+#define ESP32_TIMG1WDT_PROTECT     (ESP32_TIMG1_BASE + ESP32_TIMGWDT_PROTECT_OFF)
+#define ESP32_RTCCNTL_BASE         0x3ff48000
+#define ESP32_RTCWDT_CFG_OFF       0x8C
+#define ESP32_RTCWDT_PROTECT_OFF   0xA4
+#define ESP32_RTCWDT_CFG           (ESP32_RTCCNTL_BASE + ESP32_RTCWDT_CFG_OFF)
+#define ESP32_RTCWDT_PROTECT       (ESP32_RTCCNTL_BASE + ESP32_RTCWDT_PROTECT_OFF)
+
+#define ESP32_TRACEMEM_BLOCK_SZ    0x4000
+
+/* ESP32 dport regs */
+#define ESP32_DR_REG_DPORT_BASE         ESP32_DR_REG_LOW
+#define ESP32_DPORT_APPCPU_CTRL_B_REG   (ESP32_DR_REG_DPORT_BASE + 0x030)
+#define ESP32_DPORT_APPCPU_CLKGATE_EN   BIT(0)
+/* ESP32 RTC regs */
+#define ESP32_RTC_CNTL_SW_CPU_STALL_REG (ESP32_RTCCNTL_BASE + 0xac)
+#define ESP32_RTC_CNTL_SW_CPU_STALL_DEF 0x0
+
+
+/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
+ *xtensa-overlay */
+static const unsigned int esp32_gdb_regs_mapping[ESP32_NUM_REGS] = {
+	XT_REG_IDX_PC,
+	XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
+	XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
+	XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
+	XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
+	XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
+	XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
+	XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
+	XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
+	XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
+	XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
+	XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
+	XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
+	XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
+	XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
+	XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
+	XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
+	XT_REG_IDX_LBEG, XT_REG_IDX_LEND, XT_REG_IDX_LCOUNT, XT_REG_IDX_SAR,
+	XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
+	XT_REG_IDX_PS, XT_REG_IDX_THREADPTR, XT_REG_IDX_BR, XT_REG_IDX_SCOMPARE1,
+	XT_REG_IDX_ACCLO, XT_REG_IDX_ACCHI,
+	XT_REG_IDX_M0, XT_REG_IDX_M1, XT_REG_IDX_M2, XT_REG_IDX_M3,
+	ESP32_REG_IDX_EXPSTATE,
+	ESP32_REG_IDX_F64R_LO,
+	ESP32_REG_IDX_F64R_HI,
+	ESP32_REG_IDX_F64S,
+	XT_REG_IDX_F0, XT_REG_IDX_F1, XT_REG_IDX_F2, XT_REG_IDX_F3,
+	XT_REG_IDX_F4, XT_REG_IDX_F5, XT_REG_IDX_F6, XT_REG_IDX_F7,
+	XT_REG_IDX_F8, XT_REG_IDX_F9, XT_REG_IDX_F10, XT_REG_IDX_F11,
+	XT_REG_IDX_F12, XT_REG_IDX_F13, XT_REG_IDX_F14, XT_REG_IDX_F15,
+	XT_REG_IDX_FCR, XT_REG_IDX_FSR, XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE,
+	XT_REG_IDX_MEMCTL, XT_REG_IDX_ATOMCTL, XT_REG_IDX_OCD_DDR,
+	XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
+	XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
+	XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
+	XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
+	XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
+	XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
+	XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
+	XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
+	XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
+	XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
+	XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
+	XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
+	XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
+	XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
+	XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
+	XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
+	XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
+	XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
+	XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
+	XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
+	XT_REG_IDX_FAULT_INFO,
+	XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
+	XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
+	XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
+	XT_REG_IDX_TRAX_MEMEND,
+	XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
+	XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
+	XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
+};
+
+static const struct xtensa_user_reg_desc esp32_user_regs[ESP32_NUM_REGS - XT_NUM_REGS] = {
+	{ "expstate", 0xE6, 0, 32, &xtensa_user_reg_u32_type },
+	{ "f64r_lo", 0xEA, 0, 32, &xtensa_user_reg_u32_type },
+	{ "f64r_hi", 0xEB, 0, 32, &xtensa_user_reg_u32_type },
+	{ "f64s", 0xEC, 0, 32, &xtensa_user_reg_u32_type },
+};
+
+static const struct xtensa_config esp32_xtensa_cfg = {
+	.density = true,
+	.aregs_num = XT_AREGS_NUM_MAX,
+	.windowed = true,
+	.coproc = true,
+	.fp_coproc = true,
+	.loop = true,
+	.miscregs_num = 4,
+	.threadptr = true,
+	.boolean = true,
+	.reloc_vec = true,
+	.proc_id = true,
+	.cond_store = true,
+	.mac16 = true,
+	.user_regs_num = ARRAY_SIZE(esp32_user_regs),
+	.user_regs = esp32_user_regs,
+	.fetch_user_regs = xtensa_fetch_user_regs_u32,
+	.queue_write_dirty_user_regs = xtensa_queue_write_dirty_user_regs_u32,
+	.gdb_general_regs_num = ESP32_NUM_REGS_G_COMMAND,
+	.gdb_regs_mapping = esp32_gdb_regs_mapping,
+	.irom = {
+		.count = 2,
+		.regions = {
+			{
+				.base = ESP32_IROM_LOW,
+				.size = ESP32_IROM_HIGH - ESP32_IROM_LOW,
+				.access = XT_MEM_ACCESS_READ,
+			},
+			{
+				.base = ESP32_IROM_MASK_LOW,
+				.size = ESP32_IROM_MASK_HIGH - ESP32_IROM_MASK_LOW,
+				.access = XT_MEM_ACCESS_READ,
+			},
+		}
+	},
+	.iram = {
+		.count = 2,
+		.regions = {
+			{
+				.base = ESP32_IRAM_LOW,
+				.size = ESP32_IRAM_HIGH - ESP32_IRAM_LOW,
+				.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+			},
+			{
+				.base = ESP32_RTC_IRAM_LOW,
+				.size = ESP32_RTC_IRAM_HIGH - ESP32_RTC_IRAM_LOW,
+				.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+			},
+		}
+	},
+	.drom = {
+		.count = 1,
+		.regions = {
+			{
+				.base = ESP32_DROM_LOW,
+				.size = ESP32_DROM_HIGH - ESP32_DROM_LOW,
+				.access = XT_MEM_ACCESS_READ,
+			},
+		}
+	},
+	.dram = {
+		.count = 6,
+		.regions = {
+			{
+				.base = ESP32_DRAM_LOW,
+				.size = ESP32_DRAM_HIGH - ESP32_DRAM_LOW,
+				.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+			},
+			{
+				.base = ESP32_RTC_DRAM_LOW,
+				.size = ESP32_RTC_DRAM_HIGH - ESP32_RTC_DRAM_LOW,
+				.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+			},
+			{
+				.base = ESP32_RTC_DATA_LOW,
+				.size = ESP32_RTC_DATA_HIGH - ESP32_RTC_DATA_LOW,
+				.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+			},
+			{
+				.base = ESP32_EXTRAM_DATA_LOW,
+				.size = ESP32_EXTRAM_DATA_HIGH - ESP32_EXTRAM_DATA_LOW,
+				.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+			},
+			{
+				.base = ESP32_DR_REG_LOW,
+				.size = ESP32_DR_REG_HIGH - ESP32_DR_REG_LOW,
+				.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+			},
+			{
+				.base = ESP32_SYS_RAM_LOW,
+				.size = ESP32_SYS_RAM_HIGH - ESP32_SYS_RAM_LOW,
+				.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+			},
+		}
+	},
+	.exc = {
+		.enabled = true,
+	},
+	.irq = {
+		.enabled = true,
+		.irq_num = 32,
+	},
+	.high_irq = {
+		.enabled = true,
+		.excm_level = 3,
+		.nmi_num = 1,
+	},
+	.tim_irq = {
+		.enabled = true,
+		.comp_num = 3,
+	},
+	.debug = {
+		.enabled = true,
+		.irq_level = 6,
+		.ibreaks_num = 2,
+		.dbreaks_num = 2,
+		.icount_sz = 32,
+	},
+	.trace = {
+		.enabled = true,
+		.mem_sz = ESP32_TRACEMEM_BLOCK_SZ,
+		.reversed_mem_access = true,
+	},
+};
+
+/* 0 - don't care, 1 - TMS low, 2 - TMS high */
+enum esp32_flash_bootstrap {
+	FBS_DONTCARE = 0,
+	FBS_TMSLOW,
+	FBS_TMSHIGH,
+};
+
+struct esp32_common {
+	struct esp_xtensa_smp_common esp_xtensa_smp;
+	enum esp32_flash_bootstrap flash_bootstrap;
+};
+
+static inline struct esp32_common *target_to_esp32(struct target *target)
+{
+	return container_of(target->arch_info, struct esp32_common, esp_xtensa_smp);
+}
+
+/* Reset ESP32 peripherals.
+ * Postconditions: all peripherals except RTC_CNTL are reset, CPU's PC is undefined, PRO CPU is halted,
+ * APP CPU is in reset
+ * How this works:
+ * 0. make sure target is halted; if not, try to halt it; if that fails, try to reset it (via OCD) and then halt
+ * 1. set CPU initial PC to 0x50000000 (ESP32_SMP_RTC_DATA_LOW) by clearing RTC_CNTL_{PRO,APP}CPU_STAT_VECTOR_SEL
+ * 2. load stub code into ESP32_SMP_RTC_DATA_LOW; once executed, stub code will disable watchdogs and
+ * make CPU spin in an idle loop.
+ * 3. trigger SoC reset using RTC_CNTL_SW_SYS_RST bit
+ * 4. wait for the OCD to be reset
+ * 5. halt the target and wait for it to be halted (at this point CPU is in the idle loop)
+ * 6. restore initial PC and the contents of ESP32_SMP_RTC_DATA_LOW
+ * TODO: some state of RTC_CNTL is not reset during SW_SYS_RST. Need to reset that manually. */
+
+const uint8_t esp32_reset_stub_code[] = {
+#include "../../../contrib/loaders/reset/espressif/esp32/cpu_reset_handler_code.inc"
+};
+
+static int esp32_soc_reset(struct target *target)
+{
+	int res;
+	struct target_list *head;
+	struct xtensa *xtensa;
+
+	LOG_DEBUG("start");
+	/* In order to write to peripheral registers, target must be halted first */
+	if (target->state != TARGET_HALTED) {
+		LOG_DEBUG("Target not halted before SoC reset, trying to halt it first");
+		xtensa_halt(target);
+		res = target_wait_state(target, TARGET_HALTED, 1000);
+		if (res != ERROR_OK) {
+			LOG_DEBUG("Couldn't halt target before SoC reset, trying to do reset-halt");
+			res = xtensa_assert_reset(target);
+			if (res != ERROR_OK) {
+				LOG_ERROR(
+					"Couldn't halt target before SoC reset! (xtensa_assert_reset returned %d)",
+					res);
+				return res;
+			}
+			alive_sleep(10);
+			xtensa_poll(target);
+			bool reset_halt_save = target->reset_halt;
+			target->reset_halt = true;
+			res = xtensa_deassert_reset(target);
+			target->reset_halt = reset_halt_save;
+			if (res != ERROR_OK) {
+				LOG_ERROR(
+					"Couldn't halt target before SoC reset! (xtensa_deassert_reset returned %d)",
+					res);
+				return res;
+			}
+			alive_sleep(10);
+			xtensa_poll(target);
+			xtensa_halt(target);
+			res = target_wait_state(target, TARGET_HALTED, 1000);
+			if (res != ERROR_OK) {
+				LOG_ERROR("Couldn't halt target before SoC reset");
+				return res;
+			}
+		}
+	}
+
+	if (target->smp) {
+		foreach_smp_target(head, target->smp_targets) {
+			xtensa = target_to_xtensa(head->target);
+			/* if any of the cores is stalled unstall them */
+			if (xtensa_dm_core_is_stalled(&xtensa->dbg_mod)) {
+				LOG_TARGET_DEBUG(head->target, "Unstall CPUs before SW reset!");
+				res = target_write_u32(target,
+					ESP32_RTC_CNTL_SW_CPU_STALL_REG,
+					ESP32_RTC_CNTL_SW_CPU_STALL_DEF);
+				if (res != ERROR_OK) {
+					LOG_TARGET_ERROR(head->target, "Failed to unstall CPUs before SW reset!");
+					return res;
+				}
+				break;	/* both cores are unstalled now, so exit the loop */
+			}
+		}
+	}
+
+	LOG_DEBUG("Loading stub code into RTC RAM");
+	uint8_t slow_mem_save[sizeof(esp32_reset_stub_code)];
+
+	/* Save contents of RTC_SLOW_MEM which we are about to overwrite */
+	res = target_read_buffer(target, ESP32_RTC_SLOW_MEM_BASE, sizeof(slow_mem_save), slow_mem_save);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to save contents of RTC_SLOW_MEM (%d)!", res);
+		return res;
+	}
+
+	/* Write stub code into RTC_SLOW_MEM */
+	res = target_write_buffer(target, ESP32_RTC_SLOW_MEM_BASE, sizeof(esp32_reset_stub_code), esp32_reset_stub_code);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to write stub (%d)!", res);
+		return res;
+	}
+
+	LOG_DEBUG("Resuming the target");
+	xtensa = target_to_xtensa(target);
+	xtensa->suppress_dsr_errors = true;
+	res = xtensa_resume(target, 0, ESP32_RTC_SLOW_MEM_BASE + 4, 0, 0);
+	xtensa->suppress_dsr_errors = false;
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to run stub (%d)!", res);
+		return res;
+	}
+	LOG_DEBUG("resume done, waiting for the target to come alive");
+
+	/* Wait for SoC to reset */
+	alive_sleep(100);
+	int64_t timeout = timeval_ms() + 100;
+	bool get_timeout = false;
+	while (target->state != TARGET_RESET && target->state != TARGET_RUNNING) {
+		alive_sleep(10);
+		xtensa_poll(target);
+		if (timeval_ms() >= timeout) {
+			LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d", target->state);
+			get_timeout = true;
+			break;
+		}
+	}
+
+	/* Halt the CPU again */
+	LOG_DEBUG("halting the target");
+	xtensa_halt(target);
+	res = target_wait_state(target, TARGET_HALTED, 1000);
+	if (res == ERROR_OK) {
+		LOG_DEBUG("restoring RTC_SLOW_MEM");
+		res = target_write_buffer(target, ESP32_RTC_SLOW_MEM_BASE, sizeof(slow_mem_save), slow_mem_save);
+		if (res != ERROR_OK)
+			LOG_TARGET_ERROR(target, "Failed to restore contents of RTC_SLOW_MEM (%d)!", res);
+	} else {
+		LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be halted after SoC reset");
+	}
+
+	return get_timeout ? ERROR_TARGET_TIMEOUT : res;
+}
+
+static int esp32_disable_wdts(struct target *target)
+{
+	/* TIMG1 WDT */
+	int res = target_write_u32(target, ESP32_TIMG0WDT_PROTECT, ESP32_WDT_WKEY_VALUE);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to write ESP32_TIMG0WDT_PROTECT (%d)!", res);
+		return res;
+	}
+	res = target_write_u32(target, ESP32_TIMG0WDT_CFG0, 0);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to write ESP32_TIMG0WDT_CFG0 (%d)!", res);
+		return res;
+	}
+	/* TIMG2 WDT */
+	res = target_write_u32(target, ESP32_TIMG1WDT_PROTECT, ESP32_WDT_WKEY_VALUE);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to write ESP32_TIMG1WDT_PROTECT (%d)!", res);
+		return res;
+	}
+	res = target_write_u32(target, ESP32_TIMG1WDT_CFG0, 0);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to write ESP32_TIMG1WDT_CFG0 (%d)!", res);
+		return res;
+	}
+	/* RTC WDT */
+	res = target_write_u32(target, ESP32_RTCWDT_PROTECT, ESP32_WDT_WKEY_VALUE);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to write ESP32_RTCWDT_PROTECT (%d)!", res);
+		return res;
+	}
+	res = target_write_u32(target, ESP32_RTCWDT_CFG, 0);
+	if (res != ERROR_OK) {
+		LOG_ERROR("Failed to write ESP32_RTCWDT_CFG (%d)!", res);
+		return res;
+	}
+	return ERROR_OK;
+}
+
+static int esp32_on_halt(struct target *target)
+{
+	return esp32_disable_wdts(target);
+}
+
+static int esp32_arch_state(struct target *target)
+{
+	return ERROR_OK;
+}
+
+static int esp32_virt2phys(struct target *target,
+	target_addr_t virtual, target_addr_t *physical)
+{
+	if (physical) {
+		*physical = virtual;
+		return ERROR_OK;
+	}
+	return ERROR_FAIL;
+}
+
+
+/* The TDI pin is also used as a flash Vcc bootstrap pin. If we reset the CPU externally, the last state of the TDI pin
+ * can allow the power to an 1.8V flash chip to be raised to 3.3V, or the other way around. Users can use the
+ * esp32 flashbootstrap command to set a level, and this routine will make sure the tdi line will return to
+ * that when the jtag port is idle. */
+
+static void esp32_queue_tdi_idle(struct target *target)
+{
+	struct esp32_common *esp32 = target_to_esp32(target);
+	static uint32_t value;
+	uint8_t t[4] = { 0, 0, 0, 0 };
+
+	if (esp32->flash_bootstrap == FBS_TMSLOW)
+		/* Make sure tdi is 0 at the exit of queue execution */
+		value = 0;
+	else if (esp32->flash_bootstrap == FBS_TMSHIGH)
+		/* Make sure tdi is 1 at the exit of queue execution */
+		value = 1;
+	else
+		return;
+
+	/* Scan out 1 bit, do not move from IRPAUSE after we're done. */
+	buf_set_u32(t, 0, 1, value);
+	jtag_add_plain_ir_scan(1, t, NULL, TAP_IRPAUSE);
+}
+
+static int esp32_target_init(struct command_context *cmd_ctx, struct target *target)
+{
+	return esp_xtensa_smp_target_init(cmd_ctx, target);
+}
+
+static const struct xtensa_debug_ops esp32_dbg_ops = {
+	.queue_enable = xtensa_dm_queue_enable,
+	.queue_reg_read = xtensa_dm_queue_reg_read,
+	.queue_reg_write = xtensa_dm_queue_reg_write
+};
+
+static const struct xtensa_power_ops esp32_pwr_ops = {
+	.queue_reg_read = xtensa_dm_queue_pwr_reg_read,
+	.queue_reg_write = xtensa_dm_queue_pwr_reg_write
+};
+
+static const struct esp_xtensa_smp_chip_ops esp32_chip_ops = {
+	.reset = esp32_soc_reset,
+	.on_halt = esp32_on_halt
+};
+
+static int esp32_target_create(struct target *target, Jim_Interp *interp)
+{
+	struct xtensa_debug_module_config esp32_dm_cfg = {
+		.dbg_ops = &esp32_dbg_ops,
+		.pwr_ops = &esp32_pwr_ops,
+		.tap = target->tap,
+		.queue_tdi_idle = esp32_queue_tdi_idle,
+		.queue_tdi_idle_arg = target
+	};
+
+	struct esp32_common *esp32 = calloc(1, sizeof(struct esp32_common));
+	if (!esp32) {
+		LOG_ERROR("Failed to alloc memory for arch info!");
+		return ERROR_FAIL;
+	}
+
+	int ret = esp_xtensa_smp_init_arch_info(target, &esp32->esp_xtensa_smp, &esp32_xtensa_cfg,
+		&esp32_dm_cfg, &esp32_chip_ops);
+	if (ret != ERROR_OK) {
+		LOG_ERROR("Failed to init arch info!");
+		free(esp32);
+		return ret;
+	}
+	esp32->flash_bootstrap = FBS_DONTCARE;
+
+	/* Assume running target. If different, the first poll will fix this. */
+	target->state = TARGET_RUNNING;
+	target->debug_reason = DBG_REASON_NOTHALTED;
+	return ERROR_OK;
+}
+
+COMMAND_HELPER(esp32_cmd_flashbootstrap_do, struct esp32_common *esp32)
+{
+	int state = -1;
+
+	if (CMD_ARGC < 1) {
+		const char *st;
+		state = esp32->flash_bootstrap;
+		if (state == FBS_DONTCARE)
+			st = "Don't care";
+		else if (state == FBS_TMSLOW)
+			st = "Low (3.3V)";
+		else if (state == FBS_TMSHIGH)
+			st = "High (1.8V)";
+		else
+			st = "None";
+		command_print(CMD, "Current idle tms state: %s", st);
+		return ERROR_OK;
+	}
+
+	if (!strcasecmp(CMD_ARGV[0], "none"))
+		state = FBS_DONTCARE;
+	else if (!strcasecmp(CMD_ARGV[0], "1.8"))
+		state = FBS_TMSHIGH;
+	else if (!strcasecmp(CMD_ARGV[0], "3.3"))
+		state = FBS_TMSLOW;
+	else if (!strcasecmp(CMD_ARGV[0], "high"))
+		state = FBS_TMSHIGH;
+	else if (!strcasecmp(CMD_ARGV[0], "low"))
+		state = FBS_TMSLOW;
+
+	if (state == -1) {
+		command_print(CMD,
+			"Argument unknown. Please pick one of none, high, low, 1.8 or 3.3");
+		return ERROR_FAIL;
+	}
+	esp32->flash_bootstrap = state;
+	return ERROR_OK;
+}
+
+COMMAND_HANDLER(esp32_cmd_flashbootstrap)
+{
+	struct target *target = get_current_target(CMD_CTX);
+
+	if (target->smp) {
+		struct target_list *head;
+		struct target *curr;
+		foreach_smp_target(head, target->smp_targets) {
+			curr = head->target;
+			int ret = CALL_COMMAND_HANDLER(esp32_cmd_flashbootstrap_do,
+				target_to_esp32(curr));
+			if (ret != ERROR_OK)
+				return ret;
+		}
+		return ERROR_OK;
+	}
+	return CALL_COMMAND_HANDLER(esp32_cmd_flashbootstrap_do,
+		target_to_esp32(target));
+}
+
+static const struct command_registration esp32_any_command_handlers[] = {
+	{
+		.name = "flashbootstrap",
+		.handler = esp32_cmd_flashbootstrap,
+		.mode = COMMAND_ANY,
+		.help =
+			"Set the idle state of the TMS pin, which at reset also is the voltage selector for the flash chip.",
+		.usage = "none|1.8|3.3|high|low",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
+extern const struct command_registration semihosting_common_handlers[];
+static const struct command_registration esp32_command_handlers[] = {
+	{
+		.chain = esp_xtensa_smp_command_handlers,
+	},
+	{
+		.name = "esp32",
+		.usage = "",
+		.chain = smp_command_handlers,
+	},
+	{
+		.name = "esp32",
+		.usage = "",
+		.chain = esp32_any_command_handlers,
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
+/** Holds methods for Xtensa targets. */
+struct target_type esp32_target = {
+	.name = "esp32",
+
+	.poll = esp_xtensa_smp_poll,
+	.arch_state = esp32_arch_state,
+
+	.halt = xtensa_halt,
+	.resume = esp_xtensa_smp_resume,
+	.step = esp_xtensa_smp_step,
+
+	.assert_reset = esp_xtensa_smp_assert_reset,
+	.deassert_reset = esp_xtensa_smp_deassert_reset,
+	.soft_reset_halt = esp_xtensa_smp_soft_reset_halt,
+
+	.virt2phys = esp32_virt2phys,
+	.mmu = xtensa_mmu_is_enabled,
+	.read_memory = xtensa_read_memory,
+	.write_memory = xtensa_write_memory,
+
+	.read_buffer = xtensa_read_buffer,
+	.write_buffer = xtensa_write_buffer,
+
+	.checksum_memory = xtensa_checksum_memory,
+
+	.get_gdb_arch = xtensa_get_gdb_arch,
+	.get_gdb_reg_list = xtensa_get_gdb_reg_list,
+
+	.add_breakpoint = esp_xtensa_breakpoint_add,
+	.remove_breakpoint = esp_xtensa_breakpoint_remove,
+
+	.add_watchpoint = esp_xtensa_smp_watchpoint_add,
+	.remove_watchpoint = esp_xtensa_smp_watchpoint_remove,
+
+	.target_create = esp32_target_create,
+	.init_target = esp32_target_init,
+	.examine = xtensa_examine,
+	.deinit_target = esp_xtensa_target_deinit,
+
+	.commands = esp32_command_handlers,
+};
diff --git a/src/target/espressif/esp32.h b/src/target/espressif/esp32.h
new file mode 100644
index 000000000..bb812d0a2
--- /dev/null
+++ b/src/target/espressif/esp32.h
@@ -0,0 +1,42 @@
+/***************************************************************************
+ *   ESP32 target for OpenOCD                                              *
+ *   Copyright (C) 2017 Espressif Systems Ltd.                             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifndef OPENOCD_TARGET_ESP32_H
+#define OPENOCD_TARGET_ESP32_H
+
+#include <target/xtensa/xtensa_regs.h>
+
+#define ESP32_DROM_LOW             0x3F400000
+#define ESP32_DROM_HIGH            0x3F800000
+#define ESP32_IROM_LOW             0x400D0000
+#define ESP32_IROM_HIGH            0x40400000
+
+/* Number of registers returned directly by the G command
+ * Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
+#define ESP32_NUM_REGS_G_COMMAND   105
+
+enum esp32_reg_id {
+	/* chip specific registers that extend ISA go after ISA-defined ones */
+	ESP32_REG_IDX_EXPSTATE = XT_USR_REG_START,
+	ESP32_REG_IDX_F64R_LO,
+	ESP32_REG_IDX_F64R_HI,
+	ESP32_REG_IDX_F64S,
+	ESP32_NUM_REGS,
+};
+
+#endif	/* OPENOCD_TARGET_ESP32_H */
diff --git a/src/target/espressif/esp32s2.c b/src/target/espressif/esp32s2.c
index 212533ff8..36980325b 100644
--- a/src/target/espressif/esp32s2.c
+++ b/src/target/espressif/esp32s2.c
@@ -474,7 +474,7 @@ static int esp32s2_soc_reset(struct target *target)
 	res = esp32s2_set_peri_reg_mask(target,
 		ESP32_S2_OPTIONS0,
 		ESP32_S2_SW_SYS_RST_M,
-		1U << ESP32_S2_SW_SYS_RST_S);
+		BIT(ESP32_S2_SW_SYS_RST_S));
 	xtensa->suppress_dsr_errors = false;
 	if (res != ERROR_OK) {
 		LOG_ERROR("Failed to write ESP32_S2_OPTIONS0 (%d)!", res);
diff --git a/src/target/espressif/esp_xtensa_smp.c b/src/target/espressif/esp_xtensa_smp.c
new file mode 100644
index 000000000..1c36a295a
--- /dev/null
+++ b/src/target/espressif/esp_xtensa_smp.c
@@ -0,0 +1,716 @@
+/***************************************************************************
+ *   ESP Xtensa SMP target API for OpenOCD                                 *
+ *   Copyright (C) 2020 Espressif Systems Ltd. Co                          *
+ *   Author: Alexey Gerenkov <al...@es...>                        *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "assert.h"
+#include <target/target.h>
+#include <target/target_type.h>
+#include <target/smp.h>
+#include "esp_xtensa_smp.h"
+
+/*
+Multiprocessor stuff common:
+
+The ESP Xtensa chip can have several cores in it, which can run in SMP-mode if an
+SMP-capable OS is running. The hardware has a few features which makes
+SMP debugging much easier.
+
+First of all, there's something called a 'break network', consisting of a
+BreakIn input  and a BreakOut output on each CPU. The idea is that as soon
+as a CPU goes into debug mode for whatever reason, it'll signal that using
+its DebugOut pin. This signal is connected to the other CPU's DebugIn
+input, causing this CPU also to go into debugging mode. To resume execution
+when using only this break network, we will need to manually resume both
+CPUs.
+
+An alternative to this is the XOCDMode output and the RunStall (or DebugStall)
+input. When these are cross-connected, a CPU that goes into debug mode will
+halt execution entirely on the other CPU. Execution on the other CPU can be
+resumed by either the first CPU going out of debug mode, or the second CPU
+going into debug mode: the stall is temporarily lifted as long as the stalled
+CPU is in debug mode.
+
+A third, separate, signal is CrossTrigger. This is connected in the same way
+as the breakIn/breakOut network, but is for the TRAX (trace memory) feature;
+it does not affect OCD in any way.
+*/
+
+/*
+Multiprocessor stuff:
+
+The ESP Xtensa chip has several Xtensa cores inside, but represent themself to the OCD
+as one chip that works in multithreading mode under FreeRTOS OS.
+The core that initiate the stop condition will be defined as an active cpu.
+When one core stops, then other core will be stopped automatically by smpbreak.
+The core that initiates stop condition will be defined as an active core, and
+registers of this core will be transferred.
+*/
+
+#define ESP_XTENSA_SMP_EXAMINE_OTHER_CORES      5
+
+static int esp_xtensa_smp_update_halt_gdb(struct target *target, bool *need_resume);
+
+static inline struct esp_xtensa_smp_common *target_to_esp_xtensa_smp(struct target *target)
+{
+	return container_of(target->arch_info, struct esp_xtensa_smp_common, esp_xtensa);
+}
+
+int esp_xtensa_smp_assert_reset(struct target *target)
+{
+	return ERROR_OK;
+}
+
+int esp_xtensa_smp_deassert_reset(struct target *target)
+{
+	LOG_TARGET_DEBUG(target, "begin");
+
+	int ret = xtensa_deassert_reset(target);
+	if (ret != ERROR_OK)
+		return ret;
+	/* in SMP mode when chip was running single-core app the other core can be left un-examined,
+	   because examination is done before SOC reset. But after SOC reset it is functional and should be handled.
+	   So try to examine un-examined core just after SOC reset */
+	if (target->smp && !target_was_examined(target))
+		ret = xtensa_examine(target);
+	return ret;
+}
+
+int esp_xtensa_smp_soft_reset_halt(struct target *target)
+{
+	int res;
+	struct target_list *head;
+	struct esp_xtensa_smp_common *esp_xtensa_smp = target_to_esp_xtensa_smp(target);
+
+	LOG_TARGET_DEBUG(target, "begin");
+	/* in SMP mode we need to ensure that at first we reset SOC on PRO-CPU
+	   and then call xtensa_assert_reset() for all cores */
+	if (target->smp && target->coreid != 0)
+		return ERROR_OK;
+	/* Reset the SoC first */
+	if (esp_xtensa_smp->chip_ops->reset) {
+		res = esp_xtensa_smp->chip_ops->reset(target);
+		if (res != ERROR_OK)
+			return res;
+	}
+	if (!target->smp)
+		return xtensa_assert_reset(target);
+
+	foreach_smp_target(head, target->smp_targets) {
+		res = xtensa_assert_reset(head->target);
+		if (res != ERROR_OK)
+			return res;
+	}
+	return ERROR_OK;
+}
+
+static struct target *get_halted_esp_xtensa_smp(struct target *target, int32_t coreid)
+{
+	struct target_list *head;
+	struct target *curr;
+
+	foreach_smp_target(head, target->smp_targets) {
+		curr = head->target;
+		if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
+			return curr;
+	}
+
+	return target;
+}
+
+int esp_xtensa_smp_poll(struct target *target)
+{
+	enum target_state old_state = target->state;
+	struct esp_xtensa_smp_common *esp_xtensa_smp = target_to_esp_xtensa_smp(target);
+	struct target_list *head;
+	struct target *curr;
+	bool other_core_resume_req = false;
+
+	if (target->state == TARGET_HALTED && target->smp && target->gdb_service && !target->gdb_service->target) {
+		target->gdb_service->target = get_halted_esp_xtensa_smp(target, target->gdb_service->core[1]);
+		LOG_INFO("Switch GDB target to '%s'", target_name(target->gdb_service->target));
+		if (esp_xtensa_smp->chip_ops->on_halt)
+			esp_xtensa_smp->chip_ops->on_halt(target);
+		target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+		return ERROR_OK;
+	}
+
+	int ret = esp_xtensa_poll(target);
+	if (ret != ERROR_OK)
+		return ret;
+
+	if (target->smp) {
+		if (target->state == TARGET_RESET) {
+			esp_xtensa_smp->examine_other_cores = ESP_XTENSA_SMP_EXAMINE_OTHER_CORES;
+		} else if (esp_xtensa_smp->examine_other_cores > 0 &&
+			(target->state == TARGET_RUNNING || target->state == TARGET_HALTED)) {
+			LOG_TARGET_DEBUG(target, "Check for unexamined cores after reset");
+			bool all_examined = true;
+			foreach_smp_target(head, target->smp_targets) {
+				curr = head->target;
+				if (curr == target)
+					continue;
+				if (!target_was_examined(curr)) {
+					if (target_examine_one(curr) != ERROR_OK) {
+						LOG_DEBUG("Failed to examine!");
+						all_examined = false;
+					}
+				}
+			}
+			if (all_examined)
+				esp_xtensa_smp->examine_other_cores = 0;
+			else
+				esp_xtensa_smp->examine_other_cores--;
+		}
+	}
+
+	if (old_state != TARGET_HALTED && target->state == TARGET_HALTED) {
+		if (target->smp) {
+			ret = esp_xtensa_smp_update_halt_gdb(target, &other_core_resume_req);
+			if (ret != ERROR_OK)
+				return ret;
+		}
+		/* Call any event callbacks that are applicable */
+		if (old_state == TARGET_DEBUG_RUNNING) {
+			target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
+		} else {
+			/* check whether any core polled by esp_xtensa_smp_update_halt_gdb() requested resume */
+			if (target->smp && other_core_resume_req) {
+				/* Resume xtensa_resume will handle BREAK instruction. */
+				ret = target_resume(target, 1, 0, 1, 0);
+				if (ret != ERROR_OK) {
+					LOG_ERROR("Failed to resume target");
+					return ret;
+				}
+				return ERROR_OK;
+			}
+			if (esp_xtensa_smp->chip_ops->on_halt)
+				esp_xtensa_smp->chip_ops->on_halt(target);
+			target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+		}
+	}
+
+	return ERROR_OK;
+}
+
+static int esp_xtensa_smp_update_halt_gdb(struct target *target, bool *need_resume)
+{
+	struct esp_xtensa_smp_common *esp_xtensa_smp;
+	struct target *gdb_target = NULL;
+	struct target_list *head;
+	struct target *curr;
+	int ret = ERROR_OK;
+
+	*need_resume = false;
+
+	if (target->gdb_service && target->gdb_service->target)
+		LOG_DEBUG("GDB target '%s'", target_name(target->gdb_service->target));
+
+	if (target->gdb_service && target->gdb_service->core[0] == -1) {
+		target->gdb_service->target = target;
+		target->gdb_service->core[0] = target->coreid;
+		LOG_INFO("Set GDB target to '%s'", target_name(target));
+	}
+
+	if (target->gdb_service)
+		gdb_target = target->gdb_service->target;
+
+	/* due to smpbreak config other cores can also go to HALTED state */
+	foreach_smp_target(head, target->smp_targets) {
+		curr = head->target;
+		LOG_DEBUG("Check target '%s'", target_name(curr));
+		/* skip calling context */
+		if (curr == target)
+			continue;
+		if (!target_was_examined(curr)) {
+			curr->state = TARGET_HALTED;
+			continue;
+		}
+		/* skip targets that were already halted */
+		if (curr->state == TARGET_HALTED)
+			continue;
+		/* Skip gdb_target; it alerts GDB so has to be polled as last one */
+		if (curr == gdb_target)
+			continue;
+		LOG_DEBUG("Poll target '%s'", target_name(curr));
+
+		esp_xtensa_smp = target_to_esp_xtensa_smp(curr);
+		/* avoid auto-resume after syscall, it will be done later */
+		esp_xtensa_smp->other_core_does_resume = true;
+		/* avoid recursion in esp_xtensa_smp_poll() */
+		curr->smp = 0;
+		if (esp_xtensa_smp->chip_ops->poll)
+			ret = esp_xtensa_smp->chip_ops->poll(curr);
+		else
+			ret = esp_xtensa_smp_poll(curr);
+		curr->smp = 1;
+		if (ret != ERROR_OK)
+			return ret;
+		esp_xtensa_smp->other_core_does_resume = false;
+	}
+
+	/* after all targets were updated, poll the gdb serving target */
+	if (gdb_target && gdb_target != target) {
+		esp_xtensa_smp = target_to_esp_xtensa_smp(gdb_target);
+		if (esp_xtensa_smp->chip_ops->poll)
+			ret = esp_xtensa_smp->chip_ops->poll(gdb_target);
+		else
+			ret = esp_xtensa_smp_poll(gdb_target);
+	}
+
+	LOG_DEBUG("exit");
+
+	return ret;
+}
+
+static inline int esp_xtensa_smp_smpbreak_disable(struct target *target, uint32_t *smp_break)
+{
+	int res = xtensa_smpbreak_get(target, smp_break);
+	if (res != ERROR_OK)
+		return res;
+	return xtensa_smpbreak_set(target, 0);
+}
+
+static inline int esp_xtensa_smp_smpbreak_restore(struct target *target, uint32_t smp_break)
+{
+	return xtensa_smpbreak_set(target, smp_break);
+}
+
+static int esp_xtensa_smp_resume_cores(struct target *target,
+	int handle_breakpoints,
+	int debug_execution)
+{
+	struct target_list *head;
+	struct target *curr;
+
+	LOG_TARGET_DEBUG(target, "begin");
+
+	foreach_smp_target(head, target->smp_targets) {
+		curr = head->target;
+		/* in single-core mode disabled core cannot be examined, but need to be resumed too*/
+		if ((curr != target) && (curr->state != TARGET_RUNNING) && target_was_examined(curr)) {
+			/*  resume current address, not in SMP mode */
+			curr->smp = 0;
+			int res = esp_xtensa_smp_resume(curr, 1, 0, handle_breakpoints, debug_execution);
+			curr->smp = 1;
+			if (res != ERROR_OK)
+				return res;
+		}
+	}
+	return ERROR_OK;
+}
+
+int esp_xtensa_smp_resume(struct target *target,
+	int current,
+	target_addr_t address,
+	int handle_breakpoints,
+	int debug_execution)
+{
+	int res;
+	uint32_t smp_break;
+
+	xtensa_smpbreak_get(target, &smp_break);
+	LOG_TARGET_DEBUG(target, "smp_break=0x%" PRIx32, smp_break);
+
+	/* dummy resume for smp toggle in order to reduce gdb impact  */
+	if ((target->smp) && (target->gdb_service) && (target->gdb_service->core[1] != -1)) {
+		/* simulate a start and halt of target */
+		target->gdb_service->target = NULL;
+		target->gdb_service->core[0] = target->gdb_service->core[1];
+		/* fake resume at next poll we play the  target core[1], see poll*/
+		LOG_TARGET_DEBUG(target, "Fake resume");
+		target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+		return ERROR_OK;
+	}
+
+	/* xtensa_prepare_resume() can step over breakpoint/watchpoint and generate signals on BreakInOut circuit for
+	 * other cores. So disconnect this core from BreakInOut circuit and do xtensa_prepare_resume(). */
+	res = esp_xtensa_smp_smpbreak_disable(target, &smp_break);
+	if (res != ERROR_OK)
+		return res;
+	res = xtensa_prepare_resume(target, current, address, handle_breakpoints, debug_execution);
+	/* restore configured BreakInOut signals config */
+	int ret = esp_xtensa_smp_smpbreak_restore(target, smp_break);
+	if (ret != ERROR_OK)
+		return ret;
+	if (res != ERROR_OK) {
+		LOG_TARGET_ERROR(target, "Failed to prepare for resume!");
+		return res;
+	}
+
+	if (target->smp) {
+		if (target->gdb_service)
+			target->gdb_service->core[0] = -1;
+		res = esp_xtensa_smp_resume_cores(target, handle_breakpoints, debug_execution);
+		if (res != ERROR_OK)
+			return res;
+	}
+
+	res = xtensa_do_resume(target);
+	if (res != ERROR_OK) {
+		LOG_TARGET_ERROR(target, "Failed to resume!");
+		return res;
+	}
+
+	target->debug_reason = DBG_REASON_NOTHALTED;
+	if (!debug_execution)
+		target->state = TARGET_RUNNING;
+	else
+		target->state = TARGET_DEBUG_RUNNING;
+
+	target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+	return ERROR_OK;
+}
+
+int esp_xtensa_smp_step(struct target *target,
+	int current,
+	target_addr_t address,
+	int handle_breakpoints)
+{
+	int res;
+	uint32_t smp_break;
+	struct esp_xtensa_smp_common *esp_xtensa_smp = target_to_esp_xtensa_smp(target);
+
+	if (target->smp) {
+		res = esp_xtensa_smp_smpbreak_disable(target, &smp_break);
+		if (res != ERROR_OK)
+			return res;
+	}
+	res = xtensa_step(target, current, address, handle_breakpoints);
+
+	if (res == ERROR_OK) {
+		if (esp_xtensa_smp->chip_ops->on_halt)
+			esp_xtensa_smp->chip_ops->on_halt(target);
+		target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+	}
+
+	if (target->smp) {
+		int ret = esp_xtensa_smp_smpbreak_restore(target, smp_break);
+		if (ret != ERROR_OK)
+			return ret;
+	}
+
+	return res;
+}
+
+int esp_xtensa_smp_watchpoint_add(struct target *target, struct watchpoint *watchpoint)
+{
+	int res = xtensa_watchpoint_add(target, watchpoint);
+	if (res != ERROR_OK)
+		return res;
+
+	if (!target->smp)
+		return ERROR_OK;
+
+	struct target_list *head;
+	foreach_smp_target(head, target->smp_targets) {
+		struct target *curr = head->target;
+		if (curr == target || !target_was_examined(curr))
+			continue;
+		/* Need to use high level API here because every target for core contains list of watchpoints.
+		 * GDB works with active core only, so we need to duplicate every watchpoint on other cores,
+		 * otherwise watchpoint_free() on active core can fail if WP has been initially added on another core. */
+		curr->smp = 0;
+		res = watchpoint_add(curr, watchpoint->address, watchpoint->length,
+			watchpoint->rw, watchpoint->value, watchpoint->mask);
+		curr->smp = 1;
+		if (res != ERROR_OK)
+			return res;
+	}
+	return ERROR_OK;
+}
+
+int esp_xtensa_smp_watchpoint_remove(struct target *target, struct watchpoint *watchpoint)
+{
+	int res = xtensa_watchpoint_remove(target, watchpoint);
+	if (res != ERROR_OK)
+		return res;
+
+	if (!target->smp)
+		return ERROR_OK;
+
+	struct target_list *head;
+	foreach_smp_target(head, target->smp_targets) {
+		struct target *curr = head->target;
+		if (curr == target)
+			continue;
+		/* see big comment in esp_xtensa_smp_watchpoint_add() */
+		curr->smp = 0;
+		watchpoint_remove(curr, watchpoint->address);
+		curr->smp = 1;
+	}
+	return ERROR_OK;
+}
+
+int esp_xtensa_smp_init_arch_info(struct target *target,
+	struct esp_xtensa_smp_common *esp_xtensa_smp,
+	const struct xtensa_config *xtensa_cfg,
+	struct xtensa_debug_module_config *dm_cfg,
+	const struct esp_xtensa_smp_chip_ops *chip_ops)
+{
+	int ret = esp_xtensa_init_arch_info(target, &esp_xtensa_smp->esp_xtensa, xtensa_cfg, dm_cfg);
+	if (ret != ERROR_OK)
+		return ret;
+	esp_xtensa_smp->chip_ops = chip_ops;
+	esp_xtensa_smp->examine_other_cores = ESP_XTENSA_SMP_EXAMINE_OTHER_CORES;
+	return ERROR_OK;
+}
+
+int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *target)
+{
+	return esp_xtensa_target_init(cmd_ctx, target);
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_permissive_mode)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	if (target->smp && CMD_ARGC > 0) {
+		struct target_list *head;
+		struct target *curr;
+		foreach_smp_target(head, target->smp_targets) {
+			curr = head->target;
+			int ret = CALL_COMMAND_HANDLER(xtensa_cmd_permissive_mode_do,
+				target_to_xtensa(curr));
+			if (ret != ERROR_OK)
+				return ret;
+		}
+		return ERROR_OK;
+	}
+	return CALL_COMMAND_HANDLER(xtensa_cmd_permissive_mode_do,
+		target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_smpbreak)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	if (target->smp && CMD_ARGC > 0) {
+		struct target_list *head;
+		struct target *curr;
+		foreach_smp_target(head, target->smp_targets) {
+			curr = head->target;
+			int ret = CALL_COMMAND_HANDLER(xtensa_cmd_smpbreak_do, curr);
+			if (ret != ERROR_OK)
+				return ret;
+		}
+		return ERROR_OK;
+	}
+	return CALL_COMMAND_HANDLER(xtensa_cmd_smpbreak_do, target);
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_mask_interrupts)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	if (target->smp && CMD_ARGC > 0) {
+		struct target_list *head;
+		struct target *curr;
+		foreach_smp_target(head, target->smp_targets) {
+			curr = head->target;
+			int ret = CALL_COMMAND_HANDLER(xtensa_cmd_mask_interrupts_do,
+				target_to_xtensa(curr));
+			if (ret != ERROR_OK)
+				return ret;
+		}
+		return ERROR_OK;
+	}
+	return CALL_COMMAND_HANDLER(xtensa_cmd_mask_interrupts_do,
+		target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_perfmon_enable)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	if (target->smp && CMD_ARGC > 0) {
+		struct target_list *head;
+		struct target *curr;
+		foreach_smp_target(head, target->smp_targets) {
+			curr = head->target;
+			int ret = CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_enable_do,
+				target_to_xtensa(curr));
+			if (ret != ERROR_OK)
+				return ret;
+		}
+		return ERROR_OK;
+	}
+	return CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_enable_do,
+		target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_perfmon_dump)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	if (target->smp) {
+		struct target_list *head;
+		struct target *curr;
+		foreach_smp_target(head, target->smp_targets) {
+			curr = head->target;
+			LOG_INFO("CPU%d:", curr->coreid);
+			int ret = CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_dump_do,
+				target_to_xtensa(curr));
+			if (ret != ERROR_OK)
+				return ret;
+		}
+		return ERROR_OK;
+	}
+	return CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_dump_do,
+		target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_tracestart)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	if (target->smp) {
+		struct target_list *head;
+		struct target *curr;
+		foreach_smp_target(head, target->smp_targets) {
+			curr = head->target;
+			int ret = CALL_COMMAND_HANDLER(xtensa_cmd_tracestart_do,
+				target_to_xtensa(curr));
+			if (ret != ERROR_OK)
+				return ret;
+		}
+		return ERROR_OK;
+	}
+	return CALL_COMMAND_HANDLER(xtensa_cmd_tracestart_do,
+		target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_tracestop)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	if (target->smp) {
+		struct target_list *head;
+		struct target *curr;
+		foreach_smp_target(head, target->smp_targets) {
+			curr = head->target;
+			int ret = CALL_COMMAND_HANDLER(xtensa_cmd_tracestop_do,
+				target_to_xtensa(curr));
+			if (ret != ERROR_OK)
+				return ret;
+		}
+		return ERROR_OK;
+	}
+	return CALL_COMMAND_HANDLER(xtensa_cmd_tracestop_do,
+		target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_tracedump)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	if (target->smp) {
+		struct target_list *head;
+		struct target *curr;
+		int32_t cores_max_id = 0;
+		/* assume that core IDs are assigned to SMP targets sequentially: 0,1,2... */
+		foreach_smp_target(head, target->smp_targets) {
+			curr = head->target;
+			if (cores_max_id < curr->coreid)
+				cores_max_id = curr->coreid;
+		}
+		if (CMD_ARGC < ((uint32_t)cores_max_id + 1)) {
+...
 
[truncated message content]

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-730-g52fbb85d2

From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:40:25

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- Log -----------------------------------------------------------------
commit 52fbb85d2e0911fa1500708a5841d3474c1c0289
Author: Daniel Goehring <dgo...@os...>
Date:   Fri Apr 3 19:28:03 2020 -0400

    target/board: Add Ampere QS|MQ config files
    
    Add Ampere Altra ("Quicksilver") and Ampere Altra Max ("Mystique")
    target/board configuration files.
    
    The target configuration file supports silicon and emulation.
    The board configuration files support 1 and 2 socket platforms.
    
    Tested on Ampere emulation and silicon
    
    Change-Id: I036c798a50624e30ab51ccd2895b6f60c40be096
    Signed-off-by: Daniel Goehring <dgo...@os...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/5591
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/board/ampere_qs_mq_1s.cfg b/tcl/board/ampere_qs_mq_1s.cfg
new file mode 100644
index 000000000..bc649edb8
--- /dev/null
+++ b/tcl/board/ampere_qs_mq_1s.cfg
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and
+# Ampere Altra Max ("Mystique") processors
+#
+# Copyright (c) 2019-2021, Ampere Computing LLC
+
+# Argument Description
+#
+# JTAGFREQ
+# Set the JTAG clock frequency
+# Syntax: -c "set JTAGFREQ {freq_in_khz}"
+#
+# SYSNAME
+# Set the system name
+# If not specified, defaults to "qs"
+# Syntax: -c "set SYSNAME {qs}"
+#
+# Life-Cycle State (LCS)
+# If not specified, defaults to "Secure LCS"
+# LCS=0, "Secure LCS"
+# LCS=1, "Chip Manufacturing LCS"
+# Syntax: -c "set LCS {0}"
+# Syntax: -c "set LCS {1}"
+#
+# CORELIST_S0
+# Specify available physical cores by number
+# Example syntax to connect to physical cores 16 and 17 for S0
+# Syntax: -c "set CORELIST_S0 {16 17}"
+#
+# COREMASK_S0_LO
+# Specify available physical cores 0-63 by mask
+# Example syntax to connect to physical cores 16 and 17 for S0
+# Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}"
+#
+# COREMASK_S0_HI
+# Specify available physical cores 64 and above by mask
+# Example syntax to connect to physical cores 94 and 95 for S0
+# Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}"
+#
+# PHYS_IDX
+# Enable OpenOCD ARMv8 core target physical indexing
+# If not specified, defaults to OpenOCD ARMv8 core target logical indexing
+# Syntax: -c "set PHYS_IDX {}"
+
+#
+# Configure JTAG speed
+#
+
+if { [info exists JTAGFREQ] } {
+	adapter speed $JTAGFREQ
+} else {
+	adapter speed 100
+}
+
+#
+# Set the system name
+#
+
+if { [info exists SYSNAME] } {
+	set _SYSNAME $SYSNAME
+} else {
+	set _SYSNAME qs
+}
+
+#
+# Configure Resets
+#
+
+jtag_ntrst_delay 100
+reset_config trst_only
+
+#
+# Configure Targets
+#
+
+if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] } {
+	set CHIPNAME ${_SYSNAME}0
+	if { [info exists CORELIST_S0] } {
+		set CORELIST $CORELIST_S0
+	} else {
+		if { [info exists COREMASK_S0_LO] } {
+			set COREMASK_LO $COREMASK_S0_LO
+		} else {
+			set COREMASK_LO 0x0
+		}
+
+		if { [info exists COREMASK_S0_HI] } {
+			set COREMASK_HI $COREMASK_S0_HI
+		} else {
+			set COREMASK_HI 0x0
+		}
+	}
+} else {
+	set CHIPNAME ${_SYSNAME}0
+	set COREMASK_LO 0x1
+	set COREMASK_HI 0x0
+}
+
+source [find target/ampere_qs_mq.cfg]
diff --git a/tcl/board/ampere_qs_mq_2s.cfg b/tcl/board/ampere_qs_mq_2s.cfg
new file mode 100644
index 000000000..76d82d214
--- /dev/null
+++ b/tcl/board/ampere_qs_mq_2s.cfg
@@ -0,0 +1,164 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and
+# Ampere Altra Max ("Mystique") processors
+#
+# Copyright (c) 2019-2021, Ampere Computing LLC
+
+# Argument Description
+#
+# JTAGFREQ
+# Set the JTAG clock frequency
+# Syntax: -c "set JTAGFREQ {freq_in_khz}"
+#
+# SYSNAME
+# Set the system name
+# If not specified, defaults to "qs"
+# Syntax: -c "set SYSNAME {qs}"
+#
+# Life-Cycle State (LCS)
+# If not specified, defaults to "Secure LCS"
+# LCS=0, "Secure LCS"
+# LCS=1, "Chip Manufacturing LCS"
+# Syntax: -c "set LCS {0}"
+# Syntax: -c "set LCS {1}"
+#
+# CORELIST_S0, CORELIST_S1
+# Specify available physical cores by number
+# Example syntax to connect to physical cores 16 and 17 for S0 and S1
+# Syntax: -c "set CORELIST_S0 {16 17}"
+# Syntax: -c "set CORELIST_S1 {16 17}"
+#
+# COREMASK_S0_LO, COREMASK_S1_LO
+# Specify available physical cores 0-63 by mask
+# Example syntax to connect to physical cores 16 and 17 for S0 and S1
+# Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}"
+# Syntax: -c "set COREMASK_S1_LO {0x0000000000030000}"
+#
+# COREMASK_S0_HI, COREMASK_S1_HI
+# Specify available physical cores 64 and above by mask
+# Example syntax to connect to physical cores 94 and 95 for S0 and S1
+# Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}"
+# Syntax: -c "set COREMASK_S1_HI {0x00000000C0000000}"
+#
+# SPLITSMP
+# Group all ARMv8 cores per socket into individual SMP sessions
+# If not specified, group ARMv8 cores from both sockets into one SMP session
+# Syntax: -c "set SPLITSMP {}"
+#
+# PHYS_IDX
+# Enable OpenOCD ARMv8 core target physical indexing
+# If not specified, defaults to OpenOCD ARMv8 core target logical indexing
+# Syntax: -c "set PHYS_IDX {}"
+
+#
+# Configure JTAG speed
+#
+
+if { [info exists JTAGFREQ] } {
+	adapter speed $JTAGFREQ
+} else {
+	adapter speed 100
+}
+
+#
+# Set the system name
+#
+
+if { [info exists SYSNAME] } {
+	set _SYSNAME $SYSNAME
+} else {
+	set _SYSNAME qs
+}
+
+#
+# Configure Board level SMP configuration if necessary
+#
+
+if { ![info exists SPLITSMP] } {
+	# Group dual chip into a single SMP configuration
+	set SMP_STR "target smp"
+	set CORE_INDEX_OFFSET 0
+	set DUAL_SOCKET_SMP_ENABLED ""
+}
+
+#
+# Configure Resets
+#
+
+jtag_ntrst_delay 100
+reset_config trst_only
+
+#
+# Configure Targets
+#
+
+if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] || \
+     [info exists CORELIST_S1] || [info exists COREMASK_S1_LO] || [info exists COREMASK_S1_HI] } {
+	set CHIPNAME ${_SYSNAME}1
+	if { [info exists CORELIST_S1] } {
+		set CORELIST $CORELIST_S1
+	} else {
+		if { [info exists COREMASK_S1_LO] } {
+			set COREMASK_LO $COREMASK_S1_LO
+		} else {
+			set COREMASK_LO 0x0
+		}
+
+		if { [info exists COREMASK_S1_HI] } {
+			set COREMASK_HI $COREMASK_S1_HI
+		} else {
+			set COREMASK_HI 0x0
+		}
+	}
+	source [find target/ampere_qs_mq.cfg]
+
+	if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {
+		if { [info exists MQ_ENABLE] } {
+			set CORE_INDEX_OFFSET 128
+		} else {
+			set CORE_INDEX_OFFSET 80
+		}
+	}
+
+	set CHIPNAME ${_SYSNAME}0
+	if { [info exists CORELIST_S0] } {
+		set CORELIST $CORELIST_S0
+	} else {
+		if { [info exists COREMASK_S0_LO] } {
+			set COREMASK_LO $COREMASK_S0_LO
+		} else {
+			set COREMASK_LO 0x0
+		}
+
+		if { [info exists COREMASK_S0_HI] } {
+			set COREMASK_HI $COREMASK_S0_HI
+		} else {
+			set COREMASK_HI 0x0
+		}
+	}
+	source [find target/ampere_qs_mq.cfg]
+} else {
+	set CHIPNAME ${_SYSNAME}1
+	set COREMASK_LO 0x0
+	set COREMASK_HI 0x0
+	source [find target/ampere_qs_mq.cfg]
+
+	if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {
+		if { [info exists MQ_ENABLE] } {
+			set CORE_INDEX_OFFSET 128
+		} else {
+			set CORE_INDEX_OFFSET 80
+		}
+	}
+
+	set CHIPNAME ${_SYSNAME}0
+	set COREMASK_LO 0x1
+	set COREMASK_HI 0x0
+	source [find target/ampere_qs_mq.cfg]
+}
+
+if { [info exists DUAL_SOCKET_SMP_ENABLED] } {
+	# For dual socket SMP configuration, evaluate the string
+	eval $SMP_STR
+}
diff --git a/tcl/target/ampere_qs_mq.cfg b/tcl/target/ampere_qs_mq.cfg
new file mode 100644
index 000000000..0e83766bb
--- /dev/null
+++ b/tcl/target/ampere_qs_mq.cfg
@@ -0,0 +1,333 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# OpenOCD Target Configuration for Ampere Altra ("Quicksilver") and
+# Ampere Altra Max ("Mystique") processors
+#
+# Copyright (c) 2019-2022, Ampere Computing LLC
+
+# Command Line Argument Description
+#
+# SPLITSMP
+# Only used for dual socket systems. Do not use for a single socket setup.
+# Option pertains to the ARMv8 target core naming in a dual socket setup.
+# If specified, name all ARMv8 cores per socket as individual SMP sessions.
+# If not specified, name ARMv8 cores from both sockets as one SMP session.
+# This option is used in conjunction with the SMP_STR board file option.
+# Syntax: -c "set SPLITSMP {}"
+#
+# PHYS_IDX
+# Enable OpenOCD ARMv8 core target physical indexing.
+# If not specified, defaults to OpenOCD ARMv8 core target logical indexing.
+# Syntax: -c "set PHYS_IDX {}"
+#
+# CHIPNAME
+# Specifies the name of the chip.
+# Will typically be either qs, qs0, qs1, mq, mq0 or mq1.
+# If not specified, defaults to qs.
+# Syntax: -c "set CHIPNAME {qs}"
+#
+# SYSNAME
+# Specifies the name of the system.
+# Will typically be either qs or mq.
+# If not specified, defaults to qs.
+# Syntax: -c "set SYSNAME {qs}"
+#
+# Life-Cycle State (LCS)
+# If not specified, defaults to "Secure LCS".
+# LCS=0, "Secure LCS"
+# LCS=1, "Chip Manufacturing LCS"
+# Syntax: -c "set LCS {0}"
+# Syntax: -c "set LCS {1}"
+#
+# CORELIST
+# Specify available physical cores by number.
+# Example syntax to connect to physical cores 16 and 17.
+# Syntax: -c "set CORELIST {16 17}"
+#
+# COREMASK_LO
+# Specify available physical cores 0-63 by mask.
+# Example syntax to connect to physical cores 16 and 17.
+# Syntax: -c "set COREMASK_LO {0x0000000000030000}"
+#
+# COREMASK_HI
+# Specify available physical cores 64 and above by mask.
+# Example syntax to connect to physical cores 94 and 95.
+# Syntax: -c "set COREMASK_HI {0x00000000C0000000}"
+#
+# ARMV8_TAPID
+# Can override the ARMV8 TAPID default value if necessary.
+# Experimental Use. Most users will not use this option.
+# Syntax: -c "set ARMV8_TAPID {0x3BA06477}"
+#
+# SMPMPRO_TAPID
+# Can override the SMPMPRO TAPID default value if necessary.
+# Experimental Use. Most users will not use this option.
+# Syntax: -c "set SMPMPRO_TAPID {0x4BA00477}"
+#
+#
+# Board File Argument Description
+# These optional arguments are defined in the board file and
+# referenced by the target file. See the corresponding board
+# files for examples of their use.
+#
+# SMP_STR
+# This option is used primarily for a dual socket system and it is not
+# recommended for a single socket setup. This option configures whether
+# the SMP ARMv8 core grouping is maintained at the board or target cfg level.
+# Specify the option if the SMP core grouping is defined at the board level.
+# Do not specify if the SMP core grouping is defined at the chip level.
+# If not specified, defaults to SMP core grouping defined per socket.
+# If specified, "SMP_STR=target smp", the SMP core grouping is maintained
+# at the board cfg level.
+# Used in conjunction with the SPLITSMP option to group two chips into
+# a single SMP configuration or maintain as two separate SMP sessions.
+#
+# CORE_INDEX_OFFSET
+# Specifies the starting logical core index value.
+# Used for dual-socket systems.
+# For socket #0, set to 0.
+# For socket #1, set the starting logical core based from
+# the last logical core on socket #0.
+# If not specified, defaults to 0.
+#
+
+#
+# Configure defaults for target.
+# Can be overridden in board configuration file.
+#
+
+if { [info exists SMP_STR] } {
+	# SMP configured at the dual socket board level
+	set _SMP_STR $SMP_STR
+} else {
+	# SMP configured at the single socket target level
+	set _SMP_STR "target smp"
+}
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME qs
+}
+
+if { [info exists SYSNAME] } {
+	set _SYSNAME $SYSNAME
+} else {
+	set _SYSNAME qs
+}
+
+if { [info exists CORE_INDEX_OFFSET] } {
+	set _CORE_INDEX_OFFSET $CORE_INDEX_OFFSET
+} else {
+	set _CORE_INDEX_OFFSET 0
+}
+
+if { [info exists ENDIAN] } {
+	set _ENDIAN $ENDIAN
+} else {
+	set _ENDIAN little
+}
+
+if { [info exists ARMV8_TAPID] } {
+	set _ARMV8_TAPID $ARMV8_TAPID
+} else {
+	if { [info exists MQ_ENABLE] } {
+		# Configure for Mystique
+		set _ARMV8_TAPID 0x3BA06477
+		set _MAX_CORE 128
+	} else {
+		# Configure for Quicksilver
+		set _ARMV8_TAPID 0x2BA06477
+		set _MAX_CORE 80
+	}
+}
+
+if { [info exists SMPMPRO_TAPID] } {
+	set _SMPMPRO_TAPID $SMPMPRO_TAPID
+} else {
+	set _SMPMPRO_TAPID 0x4BA00477
+}
+
+if { [info exists CORELIST] } {
+	set _CORELIST $CORELIST
+} else {
+	if { [info exists COREMASK_LO] } {
+		set _COREMASK_LO $COREMASK_LO
+	} else {
+		set _COREMASK_LO 0x0
+	}
+
+	if { [info exists COREMASK_HI] } {
+		set _COREMASK_HI $COREMASK_HI
+	} else {
+		set _COREMASK_HI 0x0
+	}
+
+	set _CORELIST {}
+
+	set _MASK 0x1
+	for {set i 0} {$i < 64} {incr i} {
+		if { [expr {$_COREMASK_LO & $_MASK}] != 0x0 } {
+			set _CORELIST "$_CORELIST $i"
+		}
+		set _MASK [expr {$_MASK << 0x1}]
+	}
+
+	set _MASK 0x1
+	for {} {$i < $_MAX_CORE} {incr i} {
+		if { [expr {$_COREMASK_HI & $_MASK}] != 0x0 } {
+			set _CORELIST "$_CORELIST $i"
+		}
+		set _MASK [expr {$_MASK << 0x1}]
+	}
+}
+
+#
+# Definition of target names
+#
+set _TARGETNAME_PMPRO pmpro
+set _TARGETNAME_SMPRO smpro
+set _TARGETNAME_ARMV8 armv8
+
+#
+# Configure JTAG TAPs - TAP chain declaration order is important
+#
+
+jtag newtap $_CHIPNAME pmpro.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_SMPMPRO_TAPID
+set _TAPNAME_PMPRO $_CHIPNAME.$_TARGETNAME_PMPRO.tap
+
+jtag newtap $_CHIPNAME smpro.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_SMPMPRO_TAPID
+set _TAPNAME_SMPRO $_CHIPNAME.$_TARGETNAME_SMPRO.tap
+
+jtag newtap $_CHIPNAME armv8.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_ARMV8_TAPID
+set _TAPNAME_ARMV8 $_CHIPNAME.$_TARGETNAME_ARMV8.tap
+
+set _DAPNAME_PMPRO $_CHIPNAME.$_TARGETNAME_PMPRO.dap
+set _DAPNAME_SMPRO $_CHIPNAME.$_TARGETNAME_SMPRO.dap
+set _DAPNAME_ARMV8 $_CHIPNAME.$_TARGETNAME_ARMV8.dap
+
+set _AP_PMPRO_AHB 0
+set _AP_SMPRO_AHB 0
+set _AP_ARMV8_APB 0x00010000
+set _AP_ARMV8_AXI 0x00020000
+
+#
+# Configure JTAG DAPs
+#
+
+dap create $_DAPNAME_PMPRO -chain-position $_TAPNAME_PMPRO -adiv5
+dap create $_DAPNAME_SMPRO -chain-position $_TAPNAME_SMPRO -adiv5
+dap create $_DAPNAME_ARMV8 -chain-position $_TAPNAME_ARMV8 -adiv6
+
+if { [info exists LCS] && [expr {"$LCS"!="0"}] } {
+	#
+	# Create the DAP AHB-AP MEM-AP target for the PMPRO CPU
+	#
+
+	target create $_CHIPNAME.$_TARGETNAME_PMPRO.ahb mem_ap -endian $_ENDIAN -dap $_DAPNAME_PMPRO -ap-num $_AP_PMPRO_AHB
+
+	#
+	# Configure target PMPRO CPU
+	#
+
+	target create $_CHIPNAME.$_TARGETNAME_PMPRO cortex_m -endian $_ENDIAN -dap $_DAPNAME_PMPRO -ap-num $_AP_PMPRO_AHB
+
+	#
+	# Create the DAP AHB-AP MEM-AP target for the SMPRO CPU
+	#
+
+	target create $_CHIPNAME.$_TARGETNAME_SMPRO.ahb mem_ap -endian $_ENDIAN -dap $_DAPNAME_SMPRO -ap-num $_AP_SMPRO_AHB
+
+	#
+	# Configure target SMPRO CPU
+	#
+
+	target create $_CHIPNAME.$_TARGETNAME_SMPRO cortex_m -endian $_ENDIAN -dap $_DAPNAME_SMPRO -ap-num $_AP_SMPRO_AHB
+}
+
+# Create the DAP APB-AP MEM-AP target for the ARMV8 cores
+target create $_CHIPNAME.$_TARGETNAME_ARMV8.apb mem_ap -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB
+
+# Create the DAP AXI-AP MEM-AP target for the ARMV8 cores
+target create $_CHIPNAME.$_TARGETNAME_ARMV8.axi mem_ap -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_AXI
+
+# Set CSW register value default correctly for AXI accessible device memory:
+# Select the correct Access Port Number
+$_DAPNAME_ARMV8 apsel $_AP_ARMV8_AXI
+# First set the CSW to OpenOCD's internal default
+$_DAPNAME_ARMV8 apcsw default
+# Set Domain[1:0]=b'11  (CSW[14:13]=b'11)
+# Set Cache[3:0]=b'0000 (CSW[27:24]=b'0000)
+# Porter Cfg registers require secure access, AxPROT[1] (CSW[29]) must be b'0'.
+# Set AxPROT[2:0]=b'000 (CSW[30:28]=b'000) for an Unpriveleged, Secure, Data access.
+$_DAPNAME_ARMV8 apcsw 0x00006000 0x7F006000
+
+#
+# Configure target CPUs
+#
+
+set logical_index $_CORE_INDEX_OFFSET
+
+foreach physical_index $_CORELIST {
+	if { [info exists PHYS_IDX] } {
+		set logical_index [expr {$physical_index + $_CORE_INDEX_OFFSET}]
+	}
+
+	# Format a string to reference which CPU target to use
+	if { [info exists SPLITSMP] } {
+		eval "set _TARGETNAME $_CHIPNAME.${_TARGETNAME_ARMV8}_$logical_index"
+	} else {
+		eval "set _TARGETNAME $_SYSNAME.${_TARGETNAME_ARMV8}_$logical_index"
+	}
+
+	# Create and configure Cross Trigger Interface (CTI) - required for halt and resume
+	set _CTINAME $_TARGETNAME.cti
+	set _offset [expr {(0x00100000 * $physical_index) + (0x00200000 * ($physical_index>>1))}]
+	cti create $_CTINAME -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -baseaddr [expr {0xA0220000 + $_offset}]
+
+	# Create the target
+	target create $_TARGETNAME aarch64 -endian $_ENDIAN \
+		-dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -dbgbase [expr {0xA0210000 + $_offset}] \
+		-rtos hwthread -cti $_CTINAME -coreid $logical_index
+
+	# Build string used to enable SMP mode for the ARMv8 CPU cores
+	set _SMP_STR "$_SMP_STR $_TARGETNAME"
+
+	# Clear CTI output/input enables that are not configured by OpenOCD for aarch64
+	$_TARGETNAME configure -event reset-init [subst {
+		$_CTINAME write INEN0 0x00000000
+		$_CTINAME write INEN1 0x00000000
+		$_CTINAME write INEN2 0x00000000
+		$_CTINAME write INEN3 0x00000000
+		$_CTINAME write INEN4 0x00000000
+		$_CTINAME write INEN5 0x00000000
+		$_CTINAME write INEN6 0x00000000
+		$_CTINAME write INEN7 0x00000000
+		$_CTINAME write INEN8 0x00000000
+
+		$_CTINAME write OUTEN0 0x00000000
+		$_CTINAME write OUTEN1 0x00000000
+		$_CTINAME write OUTEN2 0x00000000
+		$_CTINAME write OUTEN3 0x00000000
+		$_CTINAME write OUTEN4 0x00000000
+		$_CTINAME write OUTEN5 0x00000000
+		$_CTINAME write OUTEN6 0x00000000
+		$_CTINAME write OUTEN7 0x00000000
+		$_CTINAME write OUTEN8 0x00000000
+	}]
+
+	incr logical_index
+}
+
+if { [info exists SMP_STR] } {
+	# Return updated SMP configuration string back to board level
+	set SMP_STR $_SMP_STR
+} else {
+	# For single socket per SMP configuration, evaluate the string
+	eval $_SMP_STR
+}
+
+if { [info exists CORE_INDEX_OFFSET] } {
+	# For multi-socket, return total number of cores back to board level
+	set CORE_INDEX_OFFSET $logical_index
+}

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/ampere_qs_mq_1s.cfg | 100 +++++++++++++
 tcl/board/ampere_qs_mq_2s.cfg | 164 +++++++++++++++++++++
 tcl/target/ampere_qs_mq.cfg   | 333 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 597 insertions(+)
 create mode 100644 tcl/board/ampere_qs_mq_1s.cfg
 create mode 100644 tcl/board/ampere_qs_mq_2s.cfg
 create mode 100644 tcl/target/ampere_qs_mq.cfg


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-729-gc28ae626a

From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:40:08

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
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      from  1842cf69a92d07866ebefee3bc7090a58782b059 (commit)

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- Log -----------------------------------------------------------------
commit c28ae626a24e77963127017cb6b1bfb59ff541e4
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Jan 3 10:08:35 2022 +0100

    arm_adi_v5: parse ROM tables behind SoC-600 APv1 adapter
    
    Arm "CoreSight System-on-Chip SoC-600" specification describes a
    bridge "Access Port v1 adapter" aimed to "connect a legacy Access
    Port (AP) ... into an CoreSight Architecture v3 system".
    
    A ROM table can be located in the "legacy" part of the system,
    on the legacy AP behind the APv1 adapter.
    
    For the purpose of scanning the ROM tables, consider an ADIv6
    SoC-600 APv1 adapter as an ADIv5 AP.
    
    Change-Id: I97d42fb77013c1251fb68d0caa4274086bf38a70
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/6827
    Tested-by: jenkins

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 01adbeff7..3ec98afcd 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -930,6 +930,7 @@ static const struct {
 #define DEVARCH_ID_MASK         (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)
 #define DEVARCH_MEM_AP          ARCH_ID(ARM_ID, 0x0A17)
 #define DEVARCH_ROM_C_0X9       ARCH_ID(ARM_ID, 0x0AF7)
+#define DEVARCH_UNKNOWN_V2      ARCH_ID(ARM_ID, 0x0A47)
 
 static const char *class0x9_devarch_description(uint32_t devarch)
 {
@@ -1844,8 +1845,16 @@ static int rtp_cs_component(enum coresight_access_mode mode, const struct rtp_op
 		if ((v.devarch & ARM_CS_C9_DEVARCH_PRESENT) == 0)
 			return ERROR_OK;
 
-		if (is_mem_ap && (v.devarch & DEVARCH_ID_MASK) == DEVARCH_MEM_AP)
-			*is_mem_ap = true;
+		if (is_mem_ap) {
+			if ((v.devarch & DEVARCH_ID_MASK) == DEVARCH_MEM_AP)
+				*is_mem_ap = true;
+
+			/* SoC-600 APv1 Adapter */
+			if ((v.devarch & DEVARCH_ID_MASK) == DEVARCH_UNKNOWN_V2 &&
+					ARM_CS_PIDR_DESIGNER(v.pid) == ARM_ID &&
+					ARM_CS_PIDR_PART(v.pid) == 0x9e5)
+				*is_mem_ap = true;
+		}
 
 		/* quit if not ROM table */
 		if ((v.devarch & DEVARCH_ID_MASK) != DEVARCH_ROM_C_0X9)
@@ -1880,7 +1889,7 @@ static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap, int depth)
 
 		if (!is_mem_ap)
 			return ERROR_OK;
-		/* Continue for an ADIv6 MEM-AP */
+		/* Continue for an ADIv6 MEM-AP or SoC-600 APv1 Adapter */
 	}
 
 	/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_adi_v5.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-728-g1842cf69a

From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:39:46

This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
       via  1842cf69a92d07866ebefee3bc7090a58782b059 (commit)
      from  9f0ac0e6bba85ca8afc99b77ce4ec2df96dba2bb (commit)

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- Log -----------------------------------------------------------------
commit 1842cf69a92d07866ebefee3bc7090a58782b059
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jan 23 01:25:45 2022 +0100

    adiv6: stay in same AP during dap_lookup_cs_component()
    
    Configuration file can specify, as target's debug AP, an AP that
    contains a ROM table that points, in turn, to other APs.
    Current code in cortex_a and aarch64 is not able to handle a
    return from dap_lookup_cs_component() that points to another AP.
    
    While it could be interesting to specify 'root' as target's debug
    AP, drop any found value if it's not in the starting AP.
    
    Change-Id: Id206e4fa7a29e9402c8e2393026817b410bbb8bd
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/6826
    Tested-by: jenkins

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 84518b0a1..01adbeff7 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -2124,6 +2124,7 @@ struct dap_lookup_data {
 	unsigned int type;
 	/* output */
 	uint64_t component_base;
+	uint64_t ap_num;
 };
 
 static int dap_lookup_cs_component_cs_component(int retval,
@@ -2152,6 +2153,7 @@ static int dap_lookup_cs_component_cs_component(int retval,
 
 	/* Found! */
 	lookup->component_base = v->component_base;
+	lookup->ap_num = v->ap->ap_num;
 	return CORESIGHT_COMPONENT_FOUND;
 }
 
@@ -2172,6 +2174,11 @@ int dap_lookup_cs_component(struct adiv5_ap *ap, uint8_t type,
 
 	int retval = rtp_ap(&dap_lookup_cs_component_ops, ap, 0);
 	if (retval == CORESIGHT_COMPONENT_FOUND) {
+		if (lookup.ap_num != ap->ap_num) {
+			/* TODO: handle search from root ROM table */
+			LOG_DEBUG("CS lookup ended in AP # 0x%" PRIx64 ". Ignore it", lookup.ap_num);
+			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+		}
 		LOG_DEBUG("CS lookup found at 0x%" PRIx64, lookup.component_base);
 		*addr = lookup.component_base;
 		return ERROR_OK;

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_adi_v5.c | 7 +++++++
 1 file changed, 7 insertions(+)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-727-g9f0ac0e6b

From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:39:22

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- Log -----------------------------------------------------------------
commit 9f0ac0e6bba85ca8afc99b77ce4ec2df96dba2bb
Author: Antonio Borneo <bor...@gm...>
Date:   Wed Aug 11 15:29:45 2021 +0200

    adiv6: add support for ROM tables in AP
    
    ADIv6 adds AP that only contain a ROM table in the AP itself, that
    can point to other AP containing either another AP level ROM table
    or a MEM-AP to be parsed as usual.
    
    Add support for parsing AP level ROM tables.
    
    Change-Id: Ic25863b16463b8a6adc3b15e26db7fdca858d6df
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/6467
    Tested-by: jenkins

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index ad4d7a725..84518b0a1 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -928,6 +928,7 @@ static const struct {
 };
 
 #define DEVARCH_ID_MASK         (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)
+#define DEVARCH_MEM_AP          ARCH_ID(ARM_ID, 0x0A17)
 #define DEVARCH_ROM_C_0X9       ARCH_ID(ARM_ID, 0x0AF7)
 
 static const char *class0x9_devarch_description(uint32_t devarch)
@@ -1180,6 +1181,17 @@ int adiv6_dap_read_baseptr(struct command_invocation *cmd, struct adiv5_dap *dap
 	return ERROR_OK;
 }
 
+/**
+ * Method to access the CoreSight component.
+ * On ADIv5, CoreSight components are on the bus behind a MEM-AP.
+ * On ADIv6, CoreSight components can either be on the bus behind a MEM-AP
+ * or directly in the AP.
+ */
+enum coresight_access_mode {
+	CS_ACCESS_AP,
+	CS_ACCESS_MEM_AP,
+};
+
 /** Holds registers and coordinates of a CoreSight component */
 struct cs_component_vals {
 	struct adiv5_ap *ap;
@@ -1189,19 +1201,43 @@ struct cs_component_vals {
 	uint32_t devarch;
 	uint32_t devid;
 	uint32_t devtype_memtype;
+	enum coresight_access_mode mode;
 };
 
+/**
+ * Helper to read CoreSight component's registers, either on the bus
+ * behind a MEM-AP or directly in the AP.
+ *
+ * @param mode           Method to access the component (AP or MEM-AP).
+ * @param ap             Pointer to AP containing the component.
+ * @param component_base On MEM-AP access method, base address of the component.
+ * @param reg            Offset of the component's register to read.
+ * @param value          Pointer to the store the read value.
+ *
+ * @return ERROR_OK on success, else a fault code.
+ */
+static int dap_queue_read_reg(enum coresight_access_mode mode, struct adiv5_ap *ap,
+		uint64_t component_base, unsigned int reg, uint32_t *value)
+{
+	if (mode == CS_ACCESS_AP)
+		return dap_queue_ap_read(ap, reg, value);
+
+	/* mode == CS_ACCESS_MEM_AP */
+	return mem_ap_read_u32(ap, component_base + reg, value);
+}
+
 /**
  * Read the CoreSight registers needed during ROM Table Parsing (RTP).
  *
+ * @param mode           Method to access the component (AP or MEM-AP).
  * @param ap             Pointer to AP containing the component.
  * @param component_base On MEM-AP access method, base address of the component.
  * @param v              Pointer to the struct holding the value of registers.
  *
  * @return ERROR_OK on success, else a fault code.
  */
-static int rtp_read_cs_regs(struct adiv5_ap *ap, target_addr_t component_base,
-		struct cs_component_vals *v)
+static int rtp_read_cs_regs(enum coresight_access_mode mode, struct adiv5_ap *ap,
+		target_addr_t component_base, struct cs_component_vals *v)
 {
 	assert(IS_ALIGNED(component_base, ARM_CS_ALIGN));
 	assert(ap && v);
@@ -1212,6 +1248,7 @@ static int rtp_read_cs_regs(struct adiv5_ap *ap, target_addr_t component_base,
 
 	v->ap = ap;
 	v->component_base = component_base;
+	v->mode = mode;
 
 	/* sort by offset to gain speed */
 
@@ -1221,35 +1258,35 @@ static int rtp_read_cs_regs(struct adiv5_ap *ap, target_addr_t component_base,
 	 * without triggering error. Read them for eventual use on Class 0x9.
 	 */
 	if (retval == ERROR_OK)
-		retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVARCH, &v->devarch);
+		retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_C9_DEVARCH, &v->devarch);
 
 	if (retval == ERROR_OK)
-		retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVID, &v->devid);
+		retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_C9_DEVID, &v->devid);
 
 	/* Same address as ARM_CS_C1_MEMTYPE */
 	if (retval == ERROR_OK)
-		retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVTYPE, &v->devtype_memtype);
+		retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_C9_DEVTYPE, &v->devtype_memtype);
 
 	if (retval == ERROR_OK)
-		retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR4, &pid4);
+		retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR4, &pid4);
 
 	if (retval == ERROR_OK)
-		retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR0, &pid0);
+		retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR0, &pid0);
 	if (retval == ERROR_OK)
-		retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR1, &pid1);
+		retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR1, &pid1);
 	if (retval == ERROR_OK)
-		retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR2, &pid2);
+		retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR2, &pid2);
 	if (retval == ERROR_OK)
-		retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR3, &pid3);
+		retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR3, &pid3);
 
 	if (retval == ERROR_OK)
-		retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR0, &cid0);
+		retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_CIDR0, &cid0);
 	if (retval == ERROR_OK)
-		retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR1, &cid1);
+		retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_CIDR1, &cid1);
 	if (retval == ERROR_OK)
-		retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR2, &cid2);
+		retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_CIDR2, &cid2);
 	if (retval == ERROR_OK)
-		retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR3, &cid3);
+		retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_CIDR3, &cid3);
 
 	if (retval == ERROR_OK)
 		retval = dap_run(ap->dap);
@@ -1572,6 +1609,14 @@ static int dap_devtype_display(struct command_invocation *cmd, uint32_t devtype)
  * Actions/operations to be executed while parsing ROM tables.
  */
 struct rtp_ops {
+	/**
+	 * Executed at the start of a new AP, typically to print the AP header.
+	 * @param ap        Pointer to AP.
+	 * @param depth     The current depth level of ROM table.
+	 * @param priv      Pointer to private data.
+	 * @return          ERROR_OK on success, else a fault code.
+	 */
+	int (*ap_header)(struct adiv5_ap *ap, int depth, void *priv);
 	/**
 	 * Executed at the start of a new MEM-AP, typically to print the MEM-AP header.
 	 * @param retval    Error encountered while reading AP.
@@ -1612,6 +1657,18 @@ struct rtp_ops {
 	void *priv;
 };
 
+/**
+ * Wrapper around struct rtp_ops::ap_header.
+ */
+static int rtp_ops_ap_header(const struct rtp_ops *ops,
+		struct adiv5_ap *ap, int depth)
+{
+	if (ops->ap_header)
+		return ops->ap_header(ap, depth, ops->priv);
+
+	return ERROR_OK;
+}
+
 /**
  * Wrapper around struct rtp_ops::mem_ap_header.
  * Input parameter @a retval is propagated.
@@ -1671,13 +1728,18 @@ static int rtp_ops_rom_table_entry(const struct rtp_ops *ops,
  */
 #define CORESIGHT_COMPONENT_FOUND (1)
 
-static int rtp_cs_component(const struct rtp_ops *ops,
-		struct adiv5_ap *ap, target_addr_t dbgbase, int depth);
+static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap, int depth);
+static int rtp_cs_component(enum coresight_access_mode mode, const struct rtp_ops *ops,
+		struct adiv5_ap *ap, target_addr_t dbgbase, bool *is_mem_ap, int depth);
 
-static int rtp_rom_loop(const struct rtp_ops *ops,
+static int rtp_rom_loop(enum coresight_access_mode mode, const struct rtp_ops *ops,
 		struct adiv5_ap *ap, target_addr_t base_address, int depth,
 		unsigned int width, unsigned int max_entries)
 {
+	/* ADIv6 AP ROM table provide offset from current AP */
+	if (mode == CS_ACCESS_AP)
+		base_address = ap->ap_num;
+
 	assert(IS_ALIGNED(base_address, ARM_CS_ALIGN));
 
 	unsigned int offset = 0;
@@ -1687,10 +1749,10 @@ static int rtp_rom_loop(const struct rtp_ops *ops,
 		target_addr_t component_base;
 		unsigned int saved_offset = offset;
 
-		int retval = mem_ap_read_u32(ap, base_address + offset, &romentry_low);
+		int retval = dap_queue_read_reg(mode, ap, base_address, offset, &romentry_low);
 		offset += 4;
 		if (retval == ERROR_OK && width == 64) {
-			retval = mem_ap_read_u32(ap, base_address + offset, &romentry_high);
+			retval = dap_queue_read_reg(mode, ap, base_address, offset, &romentry_high);
 			offset += 4;
 		}
 		if (retval == ERROR_OK)
@@ -1724,7 +1786,18 @@ static int rtp_rom_loop(const struct rtp_ops *ops,
 			continue;
 
 		/* Recurse */
-		retval = rtp_cs_component(ops, ap, component_base, depth + 1);
+		if (mode == CS_ACCESS_AP) {
+			struct adiv5_ap *next_ap = dap_get_ap(ap->dap, component_base);
+			if (!next_ap) {
+				LOG_DEBUG("Wrong AP # 0x%" PRIx64, component_base);
+				continue;
+			}
+			retval = rtp_ap(ops, next_ap, depth + 1);
+			dap_put_ap(next_ap);
+		} else {
+			/* mode == CS_ACCESS_MEM_AP */
+			retval = rtp_cs_component(mode, ops, ap, component_base, NULL, depth + 1);
+		}
 		if (retval == CORESIGHT_COMPONENT_FOUND)
 			return CORESIGHT_COMPONENT_FOUND;
 		if (retval != ERROR_OK) {
@@ -1737,18 +1810,21 @@ static int rtp_rom_loop(const struct rtp_ops *ops,
 	return ERROR_OK;
 }
 
-static int rtp_cs_component(const struct rtp_ops *ops,
-		struct adiv5_ap *ap, target_addr_t base_address, int depth)
+static int rtp_cs_component(enum coresight_access_mode mode, const struct rtp_ops *ops,
+		struct adiv5_ap *ap, target_addr_t base_address, bool *is_mem_ap, int depth)
 {
 	struct cs_component_vals v;
 	int retval;
 
 	assert(IS_ALIGNED(base_address, ARM_CS_ALIGN));
 
+	if (is_mem_ap)
+		*is_mem_ap = false;
+
 	if (depth > ROM_TABLE_MAX_DEPTH)
 		retval = ERROR_FAIL;
 	else
-		retval = rtp_read_cs_regs(ap, base_address, &v);
+		retval = rtp_read_cs_regs(mode, ap, base_address, &v);
 
 	retval = rtp_ops_cs_component(ops, retval, &v, depth);
 	if (retval == CORESIGHT_COMPONENT_FOUND)
@@ -1762,20 +1838,23 @@ static int rtp_cs_component(const struct rtp_ops *ops,
 	const unsigned int class = ARM_CS_CIDR_CLASS(v.cid);
 
 	if (class == ARM_CS_CLASS_0X1_ROM_TABLE)
-		return rtp_rom_loop(ops, ap, base_address, depth, 32, 960);
+		return rtp_rom_loop(mode, ops, ap, base_address, depth, 32, 960);
 
 	if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
 		if ((v.devarch & ARM_CS_C9_DEVARCH_PRESENT) == 0)
 			return ERROR_OK;
 
+		if (is_mem_ap && (v.devarch & DEVARCH_ID_MASK) == DEVARCH_MEM_AP)
+			*is_mem_ap = true;
+
 		/* quit if not ROM table */
 		if ((v.devarch & DEVARCH_ID_MASK) != DEVARCH_ROM_C_0X9)
 			return ERROR_OK;
 
 		if ((v.devid & ARM_CS_C9_DEVID_FORMAT_MASK) == ARM_CS_C9_DEVID_FORMAT_64BIT)
-			return rtp_rom_loop(ops, ap, base_address, depth, 64, 256);
+			return rtp_rom_loop(mode, ops, ap, base_address, depth, 64, 256);
 		else
-			return rtp_rom_loop(ops, ap, base_address, depth, 32, 512);
+			return rtp_rom_loop(mode, ops, ap, base_address, depth, 32, 512);
 	}
 
 	/* Class other than 0x1 and 0x9 */
@@ -1784,10 +1863,26 @@ static int rtp_cs_component(const struct rtp_ops *ops,
 
 static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap, int depth)
 {
-	int retval;
 	uint32_t apid;
 	target_addr_t dbgbase, invalid_entry;
 
+	int retval = rtp_ops_ap_header(ops, ap, depth);
+	if (retval != ERROR_OK || depth > ROM_TABLE_MAX_DEPTH)
+		return ERROR_OK; /* Don't abort recursion */
+
+	if (is_adiv6(ap->dap)) {
+		bool is_mem_ap;
+		retval = rtp_cs_component(CS_ACCESS_AP, ops, ap, 0, &is_mem_ap, depth);
+		if (retval == CORESIGHT_COMPONENT_FOUND)
+			return CORESIGHT_COMPONENT_FOUND;
+		if (retval != ERROR_OK)
+			return ERROR_OK; /* Don't abort recursion */
+
+		if (!is_mem_ap)
+			return ERROR_OK;
+		/* Continue for an ADIv6 MEM-AP */
+	}
+
 	/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
 	retval = dap_get_debugbase(ap, &dbgbase, &apid);
 	if (retval != ERROR_OK)
@@ -1811,7 +1906,8 @@ static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap, int depth)
 			invalid_entry = 0xFFFFFFFFul;
 
 		if (dbgbase != invalid_entry && (dbgbase & 0x3) != 0x2) {
-			retval = rtp_cs_component(ops, ap, dbgbase & 0xFFFFFFFFFFFFF000ull, depth);
+			retval = rtp_cs_component(CS_ACCESS_MEM_AP, ops, ap,
+					dbgbase & 0xFFFFFFFFFFFFF000ull, NULL, depth);
 			if (retval == CORESIGHT_COMPONENT_FOUND)
 				return CORESIGHT_COMPONENT_FOUND;
 		}
@@ -1822,6 +1918,19 @@ static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap, int depth)
 
 /* Actions for command "dap info" */
 
+static int dap_info_ap_header(struct adiv5_ap *ap, int depth, void *priv)
+{
+	struct command_invocation *cmd = priv;
+
+	if (depth > ROM_TABLE_MAX_DEPTH) {
+		command_print(cmd, "\tTables too deep");
+		return ERROR_FAIL;
+	}
+
+	command_print(cmd, "%sAP # 0x%" PRIx64, (depth) ? "\t\t" : "", ap->ap_num);
+	return ERROR_OK;
+}
+
 static int dap_info_mem_ap_header(int retval, struct adiv5_ap *ap,
 		target_addr_t dbgbase, uint32_t apid, int depth, void *priv)
 {
@@ -1842,8 +1951,6 @@ static int dap_info_mem_ap_header(int retval, struct adiv5_ap *ap,
 	if (depth)
 		snprintf(tabs, sizeof(tabs), "\t[L%02d] ", depth);
 
-	command_print(cmd, "%sAP # 0x%" PRIx64, tabs, ap->ap_num);
-
 	command_print(cmd, "\t\tAP ID register 0x%8.8" PRIx32, apid);
 	if (apid == 0) {
 		command_print(cmd, "\t\tNo AP found at this AP#0x%" PRIx64, ap->ap_num);
@@ -1887,7 +1994,8 @@ static int dap_info_cs_component(int retval, struct cs_component_vals *v, int de
 		return ERROR_FAIL;
 	}
 
-	command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, v->component_base);
+	if (v->mode == CS_ACCESS_MEM_AP)
+		command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, v->component_base);
 
 	if (retval != ERROR_OK) {
 		command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off");
@@ -1998,6 +2106,7 @@ static int dap_info_rom_table_entry(int retval, int depth,
 int dap_info_command(struct command_invocation *cmd, struct adiv5_ap *ap)
 {
 	struct rtp_ops dap_info_ops = {
+		.ap_header       = dap_info_ap_header,
 		.mem_ap_header   = dap_info_mem_ap_header,
 		.cs_component    = dap_info_cs_component,
 		.rom_table_entry = dap_info_rom_table_entry,
@@ -2054,6 +2163,7 @@ int dap_lookup_cs_component(struct adiv5_ap *ap, uint8_t type,
 		.idx  = core_id,
 	};
 	struct rtp_ops dap_lookup_cs_component_ops = {
+		.ap_header       = NULL,
 		.mem_ap_header   = NULL,
 		.cs_component    = dap_lookup_cs_component_cs_component,
 		.rom_table_entry = NULL,

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_adi_v5.c | 172 +++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 141 insertions(+), 31 deletions(-)


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- Log -----------------------------------------------------------------
commit b987a419b41f9f2c6e0aaf0ca2ff4b6c347ae7d8
Author: Antonio Borneo <bor...@gm...>
Date:   Wed Aug 11 11:03:49 2021 +0200

    adiv6: prepare for AP level ROM tables
    
    ADIv6 adds AP that only contain a ROM table in the AP itself, that
    can point to other AP containing either another AP level ROM table
    or a MEM-AP to be parsed as usual.
    
    To handle recursive AP access, reorganize the code to:
    - pass the depth==0 from the command 'dap info';
    - print the AP number as first line, adding proper indentation on
      depth>0;
    - align the following print with proper indentation.
    
    Change-Id: I5b811810c807fc51b307bd60f67817d9de2aa095
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/6466
    Tested-by: jenkins

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index d33dcf853..ad4d7a725 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1578,11 +1578,12 @@ struct rtp_ops {
 	 * @param ap        Pointer to AP.
 	 * @param dbgbase   Value of MEM-AP Debug Base Address register.
 	 * @param apid      Value of MEM-AP IDR Identification Register.
+	 * @param depth     The current depth level of ROM table.
 	 * @param priv      Pointer to private data.
 	 * @return          ERROR_OK on success, else a fault code.
 	 */
 	int (*mem_ap_header)(int retval, struct adiv5_ap *ap, uint64_t dbgbase,
-			uint32_t apid, void *priv);
+			uint32_t apid, int depth, void *priv);
 	/**
 	 * Executed when a CoreSight component is parsed, typically to print
 	 * information on the component.
@@ -1616,12 +1617,12 @@ struct rtp_ops {
  * Input parameter @a retval is propagated.
  */
 static int rtp_ops_mem_ap_header(const struct rtp_ops *ops,
-		int retval, struct adiv5_ap *ap, uint64_t dbgbase, uint32_t apid)
+		int retval, struct adiv5_ap *ap, uint64_t dbgbase, uint32_t apid, int depth)
 {
 	if (!ops->mem_ap_header)
 		return retval;
 
-	int retval1 = ops->mem_ap_header(retval, ap, dbgbase, apid, ops->priv);
+	int retval1 = ops->mem_ap_header(retval, ap, dbgbase, apid, depth, ops->priv);
 	if (retval != ERROR_OK)
 		return retval;
 	return retval1;
@@ -1781,7 +1782,7 @@ static int rtp_cs_component(const struct rtp_ops *ops,
 	return ERROR_OK;
 }
 
-static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap)
+static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap, int depth)
 {
 	int retval;
 	uint32_t apid;
@@ -1791,7 +1792,7 @@ static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap)
 	retval = dap_get_debugbase(ap, &dbgbase, &apid);
 	if (retval != ERROR_OK)
 		return retval;
-	retval = rtp_ops_mem_ap_header(ops, retval, ap, dbgbase, apid);
+	retval = rtp_ops_mem_ap_header(ops, retval, ap, dbgbase, apid, depth);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -1810,7 +1811,7 @@ static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap)
 			invalid_entry = 0xFFFFFFFFul;
 
 		if (dbgbase != invalid_entry && (dbgbase & 0x3) != 0x2) {
-			retval = rtp_cs_component(ops, ap, dbgbase & 0xFFFFFFFFFFFFF000ull, 0);
+			retval = rtp_cs_component(ops, ap, dbgbase & 0xFFFFFFFFFFFFF000ull, depth);
 			if (retval == CORESIGHT_COMPONENT_FOUND)
 				return CORESIGHT_COMPONENT_FOUND;
 		}
@@ -1822,23 +1823,34 @@ static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap)
 /* Actions for command "dap info" */
 
 static int dap_info_mem_ap_header(int retval, struct adiv5_ap *ap,
-		target_addr_t dbgbase, uint32_t apid, void *priv)
+		target_addr_t dbgbase, uint32_t apid, int depth, void *priv)
 {
 	struct command_invocation *cmd = priv;
 	target_addr_t invalid_entry;
+	char tabs[17] = "";
 
 	if (retval != ERROR_OK) {
 		command_print(cmd, "\t\tCan't read MEM-AP, the corresponding core might be turned off");
 		return retval;
 	}
 
-	command_print(cmd, "AP ID register 0x%8.8" PRIx32, apid);
+	if (depth > ROM_TABLE_MAX_DEPTH) {
+		command_print(cmd, "\tTables too deep");
+		return ERROR_FAIL;
+	}
+
+	if (depth)
+		snprintf(tabs, sizeof(tabs), "\t[L%02d] ", depth);
+
+	command_print(cmd, "%sAP # 0x%" PRIx64, tabs, ap->ap_num);
+
+	command_print(cmd, "\t\tAP ID register 0x%8.8" PRIx32, apid);
 	if (apid == 0) {
-		command_print(cmd, "No AP found at this AP#0x%" PRIx64, ap->ap_num);
+		command_print(cmd, "\t\tNo AP found at this AP#0x%" PRIx64, ap->ap_num);
 		return ERROR_FAIL;
 	}
 
-	command_print(cmd, "\tType is %s", ap_type_to_description(apid & AP_TYPE_MASK));
+	command_print(cmd, "\t\tType is %s", ap_type_to_description(apid & AP_TYPE_MASK));
 
 	/* NOTE: a MEM-AP may have a single CoreSight component that's
 	 * not a ROM table ... or have no such components at all.
@@ -1851,15 +1863,15 @@ static int dap_info_mem_ap_header(int retval, struct adiv5_ap *ap,
 		else
 			invalid_entry = 0xFFFFFFFFul;
 
-		command_print(cmd, "MEM-AP BASE " TARGET_ADDR_FMT, dbgbase);
+		command_print(cmd, "%sMEM-AP BASE " TARGET_ADDR_FMT, tabs, dbgbase);
 
 		if (dbgbase == invalid_entry || (dbgbase & 0x3) == 0x2) {
-			command_print(cmd, "\tNo ROM table present");
+			command_print(cmd, "\t\tNo ROM table present");
 		} else {
 			if (dbgbase & 0x01)
-				command_print(cmd, "\tValid ROM table present");
+				command_print(cmd, "\t\tValid ROM table present");
 			else
-				command_print(cmd, "\tROM table in legacy format");
+				command_print(cmd, "\t\tROM table in legacy format");
 		}
 	}
 
@@ -1992,7 +2004,7 @@ int dap_info_command(struct command_invocation *cmd, struct adiv5_ap *ap)
 		.priv            = cmd,
 	};
 
-	return rtp_ap(&dap_info_ops, ap);
+	return rtp_ap(&dap_info_ops, ap, 0);
 }
 
 /* Actions for dap_lookup_cs_component() */
@@ -2048,7 +2060,7 @@ int dap_lookup_cs_component(struct adiv5_ap *ap, uint8_t type,
 		.priv            = &lookup,
 	};
 
-	int retval = rtp_ap(&dap_lookup_cs_component_ops, ap);
+	int retval = rtp_ap(&dap_lookup_cs_component_ops, ap, 0);
 	if (retval == CORESIGHT_COMPONENT_FOUND) {
 		LOG_DEBUG("CS lookup found at 0x%" PRIx64, lookup.component_base);
 		*addr = lookup.component_base;

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_adi_v5.c | 44 ++++++++++++++++++++++++++++----------------
 1 file changed, 28 insertions(+), 16 deletions(-)


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From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:38:32

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- Log -----------------------------------------------------------------
commit 8c1d518232c3105e5599099f41038212250f3798
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Aug 9 15:31:10 2021 +0200

    arm_adi_v5: add option 'root' to 'dap info' command
    
    On ADIv6 the system root ROM table is found by reading the DAP DP
    registers BASEPTR0 and BASEPTR1.
    
    Add option 'root' to the commands 'dap info' to let it retrieve
    the system root ROM table's AP from DAP DP, then use such AP for
    following dump.
    
    Change-Id: I1789457a005faa3870c5d14f763378d2f6a5f095
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/6462
    Tested-by: jenkins

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 0398e2fb4..b328370e4 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4677,11 +4677,12 @@ This command returns a list of all registered DAP objects. It it useful mainly
 for TCL scripting.
 @end deffn
 
-@deffn {Command} {dap info} [num]
+@deffn {Command} {dap info} [@var{num}|@option{root}]
 Displays the ROM table for MEM-AP @var{num},
 defaulting to the currently selected AP of the currently selected target.
 On ADIv5 DAP @var{num} is the numeric index of the AP.
 On ADIv6 DAP @var{num} is the base address of the AP.
+With ADIv6 only, @option{root} specifies the root ROM table.
 @end deffn
 
 @deffn {Command} {dap init}
@@ -4692,11 +4693,12 @@ initialization, too.
 
 The following commands exist as subcommands of DAP instances:
 
-@deffn {Command} {$dap_name info} [num]
+@deffn {Command} {$dap_name info} [@var{num}|@option{root}]
 Displays the ROM table for MEM-AP @var{num},
 defaulting to the currently selected AP.
 On ADIv5 DAP @var{num} is the numeric index of the AP.
 On ADIv6 DAP @var{num} is the base address of the AP.
+With ADIv6 only, @option{root} specifies the root ROM table.
 @end deffn
 
 @deffn {Command} {$dap_name apid} [num]
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 79f9b8d2b..d33dcf853 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1154,6 +1154,32 @@ static int dap_get_debugbase(struct adiv5_ap *ap,
 	return ERROR_OK;
 }
 
+int adiv6_dap_read_baseptr(struct command_invocation *cmd, struct adiv5_dap *dap, uint64_t *baseptr)
+{
+	uint32_t baseptr_lower, baseptr_upper = 0;
+	int retval;
+
+	if (dap->asize > 32) {
+		retval = dap_queue_dp_read(dap, DP_BASEPTR1, &baseptr_upper);
+		if (retval != ERROR_OK)
+			return retval;
+	}
+
+	retval = dap_dp_read_atomic(dap, DP_BASEPTR0, &baseptr_lower);
+	if (retval != ERROR_OK)
+		return retval;
+
+	if ((baseptr_lower & DP_BASEPTR0_VALID) != DP_BASEPTR0_VALID) {
+		command_print(cmd, "System root table not present");
+		return ERROR_FAIL;
+	}
+
+	baseptr_lower &= ~0x0fff;
+	*baseptr = (((uint64_t)baseptr_upper) << 32) | baseptr_lower;
+
+	return ERROR_OK;
+}
+
 /** Holds registers and coordinates of a CoreSight component */
 struct cs_component_vals {
 	struct adiv5_ap *ap;
@@ -2225,6 +2251,18 @@ COMMAND_HANDLER(handle_dap_info_command)
 		apsel = dap->apsel;
 		break;
 	case 1:
+		if (!strcmp(CMD_ARGV[0], "root")) {
+			if (!is_adiv6(dap)) {
+				command_print(CMD, "Option \"root\" not allowed with ADIv5 DAP");
+				return ERROR_COMMAND_ARGUMENT_INVALID;
+			}
+			int retval = adiv6_dap_read_baseptr(CMD, dap, &apsel);
+			if (retval != ERROR_OK) {
+				command_print(CMD, "Failed reading DAP baseptr");
+				return retval;
+			}
+			break;
+		}
 		COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
 		if (!is_ap_num_valid(dap, apsel)) {
 			command_print(CMD, "Invalid AP number");
@@ -2595,9 +2633,9 @@ const struct command_registration dap_instance_commands[] = {
 		.name = "info",
 		.handler = handle_dap_info_command,
 		.mode = COMMAND_EXEC,
-		.help = "display ROM table for MEM-AP "
-			"(default currently selected AP)",
-		.usage = "[ap_num]",
+		.help = "display ROM table for specified MEM-AP (default currently selected AP) "
+			"or the ADIv6 root ROM table",
+		.usage = "[ap_num | 'root']",
 	},
 	{
 		.name = "apsel",
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 534dd3b73..8fb57470b 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -86,6 +86,9 @@
 #define DP_DPIDR1_ASIZE_MASK    (0x7F)
 #define DP_DPIDR1_ERRMODE       BIT(7)
 
+/* Fields of register DP_BASEPTR0 */
+#define DP_BASEPTR0_VALID       BIT(0)
+
 /* Fields of the DP's CTRL/STAT register */
 #define CORUNDETECT     (1UL << 0)
 #define SSTICKYORUN     (1UL << 1)
@@ -692,6 +695,9 @@ int mem_ap_init(struct adiv5_ap *ap);
 /* Invalidate cached DP select and cached TAR and CSW of all APs */
 void dap_invalidate_cache(struct adiv5_dap *dap);
 
+/* read ADIv6 baseptr register */
+int adiv6_dap_read_baseptr(struct command_invocation *cmd, struct adiv5_dap *dap, target_addr_t *baseptr);
+
 /* test if ap_num is valid, based on current knowledge of dap */
 bool is_ap_num_valid(struct adiv5_dap *dap, uint64_t ap_num);
 
diff --git a/src/target/arm_dap.c b/src/target/arm_dap.c
index cfd14de93..05fd6806a 100644
--- a/src/target/arm_dap.c
+++ b/src/target/arm_dap.c
@@ -471,6 +471,18 @@ COMMAND_HANDLER(handle_dap_info_command)
 			apsel = dap->apsel;
 			break;
 		case 1:
+			if (!strcmp(CMD_ARGV[0], "root")) {
+				if (!is_adiv6(dap)) {
+					command_print(CMD, "Option \"root\" not allowed with ADIv5 DAP");
+					return ERROR_COMMAND_ARGUMENT_INVALID;
+				}
+				int retval = adiv6_dap_read_baseptr(CMD, dap, &apsel);
+				if (retval != ERROR_OK) {
+					command_print(CMD, "Failed reading DAP baseptr");
+					return retval;
+				}
+				break;
+			}
 			COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
 			if (!is_ap_num_valid(dap, apsel))
 				return ERROR_COMMAND_SYNTAX_ERROR;
@@ -515,9 +527,9 @@ static const struct command_registration dap_subcommand_handlers[] = {
 		.name = "info",
 		.handler = handle_dap_info_command,
 		.mode = COMMAND_EXEC,
-		.help = "display ROM table for MEM-AP of current target "
-		"(default currently selected AP)",
-		.usage = "[ap_num]",
+		.help = "display ROM table for specified MEM-AP (default MEM-AP of current target) "
+			"or the ADIv6 root ROM table of current target's DAP",
+		.usage = "[ap_num | 'root']",
 	},
 	COMMAND_REGISTRATION_DONE
 };

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi        |  6 ++++--
 src/target/arm_adi_v5.c | 44 +++++++++++++++++++++++++++++++++++++++++---
 src/target/arm_adi_v5.h |  6 ++++++
 src/target/arm_dap.c    | 18 +++++++++++++++---
 4 files changed, 66 insertions(+), 8 deletions(-)


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- Log -----------------------------------------------------------------
commit 3f4bc6ce7f5c5a619590c3cc05a74d6bff6a124f
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Aug 14 23:56:12 2021 +0200

    adiv6: use struct adiv5_ap->ap_num to contain the AP base address
    
    ADIv5 DAP can only have 256 AP, while ADIv6 can provide till
    2**40 (1,099,511,627,776) AP per DAP.
    
    Reuse the field ap_num in struct adiv5_ap, currently used on ADIv5
    to hold the ADIv5 AP number (apsel), to contain the ADIv6 AP base
    address.
    
    Convert struct adiv5_ap->ap_num to 64 bit and initialize it to
    DP_APSEL_INVALID for unused AP.
    Restrict dap_find_get_ap() to ADIv5 only. To be enhanced.
    On ADIv6, let dap_get_ap() return an already allocated AP, or
    allocate and return an unused AP.
    Add function is_ap_num_valid() and use it.
    
    Change-Id: Ib2fe8c7ec0d08393cd91c29fdac5d632dfc1e438
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/6461
    Reviewed-by: Daniel Goehring <dgo...@os...>
    Tested-by: jenkins

diff --git a/doc/openocd.texi b/doc/openocd.texi
index e8535b7a1..0398e2fb4 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4680,6 +4680,8 @@ for TCL scripting.
 @deffn {Command} {dap info} [num]
 Displays the ROM table for MEM-AP @var{num},
 defaulting to the currently selected AP of the currently selected target.
+On ADIv5 DAP @var{num} is the numeric index of the AP.
+On ADIv6 DAP @var{num} is the base address of the AP.
 @end deffn
 
 @deffn {Command} {dap init}
@@ -4693,21 +4695,29 @@ The following commands exist as subcommands of DAP instances:
 @deffn {Command} {$dap_name info} [num]
 Displays the ROM table for MEM-AP @var{num},
 defaulting to the currently selected AP.
+On ADIv5 DAP @var{num} is the numeric index of the AP.
+On ADIv6 DAP @var{num} is the base address of the AP.
 @end deffn
 
 @deffn {Command} {$dap_name apid} [num]
 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
+On ADIv5 DAP @var{num} is the numeric index of the AP.
+On ADIv6 DAP @var{num} is the base address of the AP.
 @end deffn
 
 @anchor{DAP subcommand apreg}
 @deffn {Command} {$dap_name apreg} ap_num reg [value]
 Displays content of a register @var{reg} from AP @var{ap_num}
 or set a new value @var{value}.
+On ADIv5 DAP @var{ap_num} is the numeric index of the AP.
+On ADIv6 DAP @var{ap_num} is the base address of the AP.
 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
 @end deffn
 
 @deffn {Command} {$dap_name apsel} [num]
 Select AP @var{num}, defaulting to 0.
+On ADIv5 DAP @var{num} is the numeric index of the AP.
+On ADIv6 DAP @var{num} is the base address of the AP.
 @end deffn
 
 @deffn {Command} {$dap_name dpreg} reg [value]
@@ -4725,6 +4735,8 @@ background activity by OpenOCD while you are operating at such low-level.
 @deffn {Command} {$dap_name baseaddr} [num]
 Displays debug base address from MEM-AP @var{num},
 defaulting to the currently selected AP.
+On ADIv5 DAP @var{num} is the numeric index of the AP.
+On ADIv6 DAP @var{num} is the base address of the AP.
 @end deffn
 
 @deffn {Command} {$dap_name memaccess} [value]
@@ -5098,8 +5110,9 @@ The value should normally correspond to a static mapping for the
 scan and after a reset. A manual call to arp_examine is required to
 access the target for debugging.
 
-@item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
-@var{ap_number} is the numeric index of the DAP AP the target is connected to.
+@item @code{-ap-num} @var{ap_number} -- set DAP access port for target.
+On ADIv5 DAP @var{ap_number} is the numeric index of the DAP AP the target is connected to.
+On ADIv6 DAP @var{ap_number} is the base address of the DAP AP the target is connected to.
 Use this option with systems where multiple, independent cores are connected
 to separate access ports of the same DAP.
 
@@ -9449,7 +9462,10 @@ the @emph{cti} group of commands.
 
 @deffn {Command} {cti create} cti_name @option{-dap} dap_name @option{-ap-num} apn @option{-baseaddr} base_address
 Creates a CTI instance @var{cti_name} on the DAP instance @var{dap_name} on MEM-AP
-@var{apn}. The @var{base_address} must match the base address of the CTI
+@var{apn}.
+On ADIv5 DAP @var{apn} is the numeric index of the DAP AP the CTI is connected to.
+On ADIv6 DAP @var{apn} is the base address of the DAP AP the CTI is connected to.
+The @var{base_address} must match the base address of the CTI
 on the respective MEM-AP. All arguments are mandatory. This creates a
 new command @command{$cti_name} which is used for various purposes
 including additional configuration.
@@ -10114,8 +10130,9 @@ using the @command{$tpiu_name cget} command.
 @item @code{-dap} @var{dap_name} -- names the DAP used to access this
 TPIU. @xref{dapdeclaration,,DAP declaration}, on how to create and manage DAP instances.
 
-@item @code{-ap-num} @var{ap_number} -- sets DAP access port for TPIU,
-@var{ap_number} is the numeric index of the DAP AP the TPIU is connected to.
+@item @code{-ap-num} @var{ap_number} -- sets DAP access port for TPIU.
+On ADIv5 DAP @var{ap_number} is the numeric index of the DAP AP the TPIU is connected to.
+On ADIv6 DAP @var{ap_number} is the base address of the DAP AP the TPIU is connected to.
 
 @item @code{-baseaddr} @var{base_address} -- sets the TPIU @var{base_address} where
 to access the TPIU in the DAP AP memory space.
diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c
index 8a9028bd1..046d29776 100644
--- a/src/jtag/drivers/stlink_usb.c
+++ b/src/jtag/drivers/stlink_usb.c
@@ -4152,7 +4152,7 @@ static int stlink_dap_reinit_interface(void)
 	stlink_dap_handle->reconnect_pending = false;
 	/* on new FW, calling mode-leave closes all the opened AP; reopen them! */
 	if (stlink_dap_handle->version.flags & STLINK_F_HAS_AP_INIT)
-		for (int apsel = 0; apsel <= DP_APSEL_MAX; apsel++)
+		for (unsigned int apsel = 0; apsel <= DP_APSEL_MAX; apsel++)
 			if (test_bit(apsel, opened_ap)) {
 				clear_bit(apsel, opened_ap);
 				stlink_dap_open_ap(apsel);
@@ -4348,7 +4348,7 @@ static int stlink_usb_misc_rw_segment(void *handle, const struct dap_queue *q, u
 
 	LOG_DEBUG("Queue: %u commands in %u items", len, items);
 
-	int ap_num = DP_APSEL_INVALID;
+	uint32_t ap_num = DP_APSEL_INVALID;
 	unsigned int cmd_index = 0;
 	unsigned int val_index = ALIGN_UP(items, 4);
 	for (unsigned int i = 0; i < len; i++) {
@@ -4497,7 +4497,7 @@ static int stlink_usb_count_misc_rw_queue(void *handle, const struct dap_queue *
 {
 	struct stlink_usb_handle_s *h = handle;
 	unsigned int i, items = 0;
-	int ap_num = DP_APSEL_INVALID;
+	uint32_t ap_num = DP_APSEL_INVALID;
 	unsigned int misc_max_items = (h->version.stlink == 2) ? STLINK_V2_RW_MISC_SIZE : STLINK_V3_RW_MISC_SIZE;
 
 	if (!(h->version.flags & STLINK_F_HAS_RW_MISC))
@@ -4864,9 +4864,10 @@ static int stlink_dap_op_queue_ap_write(struct adiv5_ap *ap, unsigned int reg,
 		q->ap_w.reg = reg;
 		q->ap_w.ap = ap;
 		q->ap_w.data = data;
-		if (reg == ADIV5_MEM_AP_REG_CSW && ap->csw_default != last_csw_default[ap->ap_num]) {
+		uint8_t ap_num = ap->ap_num;
+		if (reg == ADIV5_MEM_AP_REG_CSW && ap->csw_default != last_csw_default[ap_num]) {
 			q->ap_w.changes_csw_default = true;
-			last_csw_default[ap->ap_num] = ap->csw_default;
+			last_csw_default[ap_num] = ap->csw_default;
 		} else {
 			q->ap_w.changes_csw_default = false;
 		}
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index a74e47f79..79f9b8d2b 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -966,16 +966,45 @@ static const char *ap_type_to_description(enum ap_type type)
 	return "Unknown";
 }
 
+bool is_ap_num_valid(struct adiv5_dap *dap, uint64_t ap_num)
+{
+	if (!dap)
+		return false;
+
+	/* no autodetection, by now, so uninitialized is equivalent to ADIv5 for
+	 * backward compatibility */
+	if (!is_adiv6(dap)) {
+		if (ap_num > DP_APSEL_MAX)
+			return false;
+		return true;
+	}
+
+	if (is_adiv6(dap)) {
+		if (ap_num & 0x0fffULL)
+			return false;
+		if (dap->asize != 0)
+			if (ap_num & ((~0ULL) << dap->asize))
+				return false;
+		return true;
+	}
+
+	return false;
+}
+
 /*
  * This function checks the ID for each access port to find the requested Access Port type
  * It also calls dap_get_ap() to increment the AP refcount
  */
 int dap_find_get_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
 {
-	int ap_num;
+	if (is_adiv6(dap)) {
+		/* TODO: scan the ROM table and detect the AP available */
+		LOG_DEBUG("On ADIv6 we cannot scan all the possible AP");
+		return ERROR_FAIL;
+	}
 
 	/* Maximum AP number is 255 since the SELECT register is 8 bits */
-	for (ap_num = 0; ap_num <= DP_APSEL_MAX; ap_num++) {
+	for (unsigned int ap_num = 0; ap_num <= DP_APSEL_MAX; ap_num++) {
 		struct adiv5_ap *ap = dap_get_ap(dap, ap_num);
 		if (!ap)
 			continue;
@@ -1014,33 +1043,55 @@ static inline bool is_ap_in_use(struct adiv5_ap *ap)
 	return ap->refcount > 0 || ap->config_ap_never_release;
 }
 
-static struct adiv5_ap *_dap_get_ap(struct adiv5_dap *dap, unsigned int ap_num)
+static struct adiv5_ap *_dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
 {
-	if (ap_num > DP_APSEL_MAX) {
-		LOG_ERROR("Invalid AP#%u", ap_num);
+	if (!is_ap_num_valid(dap, ap_num)) {
+		LOG_ERROR("Invalid AP#0x%" PRIx64, ap_num);
 		return NULL;
 	}
+	if (is_adiv6(dap)) {
+		for (unsigned int i = 0; i <= DP_APSEL_MAX; i++) {
+			struct adiv5_ap *ap = &dap->ap[i];
+			if (is_ap_in_use(ap) && ap->ap_num == ap_num) {
+				++ap->refcount;
+				return ap;
+			}
+		}
+		for (unsigned int i = 0; i <= DP_APSEL_MAX; i++) {
+			struct adiv5_ap *ap = &dap->ap[i];
+			if (!is_ap_in_use(ap)) {
+				ap->ap_num = ap_num;
+				++ap->refcount;
+				return ap;
+			}
+		}
+		LOG_ERROR("No more AP available!");
+		return NULL;
+	}
+
+	/* ADIv5 */
 	struct adiv5_ap *ap = &dap->ap[ap_num];
+	ap->ap_num = ap_num;
 	++ap->refcount;
 	return ap;
 }
 
 /* Return AP with specified ap_num. Increment AP refcount */
-struct adiv5_ap *dap_get_ap(struct adiv5_dap *dap, unsigned int ap_num)
+struct adiv5_ap *dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
 {
 	struct adiv5_ap *ap = _dap_get_ap(dap, ap_num);
 	if (ap)
-		LOG_DEBUG("refcount AP#%u get %u", ap_num, ap->refcount);
+		LOG_DEBUG("refcount AP#0x%" PRIx64 " get %u", ap_num, ap->refcount);
 	return ap;
 }
 
 /* Return AP with specified ap_num. Increment AP refcount and keep it non-zero */
-struct adiv5_ap *dap_get_config_ap(struct adiv5_dap *dap, unsigned int ap_num)
+struct adiv5_ap *dap_get_config_ap(struct adiv5_dap *dap, uint64_t ap_num)
 {
 	struct adiv5_ap *ap = _dap_get_ap(dap, ap_num);
 	if (ap) {
 		ap->config_ap_never_release = true;
-		LOG_DEBUG("refcount AP#%u get_config %u", ap_num, ap->refcount);
+		LOG_DEBUG("refcount AP#0x%" PRIx64 " get_config %u", ap_num, ap->refcount);
 	}
 	return ap;
 }
@@ -1049,15 +1100,16 @@ struct adiv5_ap *dap_get_config_ap(struct adiv5_dap *dap, unsigned int ap_num)
 int dap_put_ap(struct adiv5_ap *ap)
 {
 	if (ap->refcount == 0) {
-		LOG_ERROR("BUG: refcount AP#%" PRIu8 " put underflow", ap->ap_num);
+		LOG_ERROR("BUG: refcount AP#0x%" PRIx64 " put underflow", ap->ap_num);
 		return ERROR_FAIL;
 	}
 
 	--ap->refcount;
 
-	LOG_DEBUG("refcount AP#%" PRIu8 " put %u", ap->ap_num, ap->refcount);
+	LOG_DEBUG("refcount AP#0x%" PRIx64 " put %u", ap->ap_num, ap->refcount);
 	if (!is_ap_in_use(ap)) {
 		/* defaults from dap_instance_init() */
+		ap->ap_num = DP_APSEL_INVALID;
 		ap->memaccess_tck = 255;
 		ap->tar_autoincr_block = (1 << 10);
 		ap->csw_default = CSW_AHB_DEFAULT;
@@ -1756,7 +1808,7 @@ static int dap_info_mem_ap_header(int retval, struct adiv5_ap *ap,
 
 	command_print(cmd, "AP ID register 0x%8.8" PRIx32, apid);
 	if (apid == 0) {
-		command_print(cmd, "No AP found at this ap 0x%x", ap->ap_num);
+		command_print(cmd, "No AP found at this AP#0x%" PRIx64, ap->ap_num);
 		return ERROR_FAIL;
 	}
 
@@ -2000,7 +2052,7 @@ static const struct jim_nvp nvp_config_opts[] = {
 };
 
 static int adiv5_jim_spot_configure(struct jim_getopt_info *goi,
-		struct adiv5_dap **dap_p, int *ap_num_p, uint32_t *base_p)
+		struct adiv5_dap **dap_p, uint64_t *ap_num_p, uint32_t *base_p)
 {
 	assert(dap_p && ap_num_p);
 
@@ -2055,11 +2107,13 @@ static int adiv5_jim_spot_configure(struct jim_getopt_info *goi,
 
 	case CFG_AP_NUM:
 		if (goi->isconfigure) {
+			/* jim_wide is a signed 64 bits int, ap_num is unsigned with max 52 bits */
 			jim_wide ap_num;
 			e = jim_getopt_wide(goi, &ap_num);
 			if (e != JIM_OK)
 				return e;
-			if (ap_num < 0 || ap_num > DP_APSEL_MAX) {
+			/* we still don't know dap->adi_version */
+			if (ap_num < 0 || (ap_num > DP_APSEL_MAX && (ap_num & 0xfff))) {
 				Jim_SetResultString(goi->interp, "Invalid AP number!", -1);
 				return JIM_ERR;
 			}
@@ -2164,15 +2218,15 @@ int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot *p)
 COMMAND_HANDLER(handle_dap_info_command)
 {
 	struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
-	uint32_t apsel;
+	uint64_t apsel;
 
 	switch (CMD_ARGC) {
 	case 0:
 		apsel = dap->apsel;
 		break;
 	case 1:
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
-		if (apsel > DP_APSEL_MAX) {
+		COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
+		if (!is_ap_num_valid(dap, apsel)) {
 			command_print(CMD, "Invalid AP number");
 			return ERROR_COMMAND_ARGUMENT_INVALID;
 		}
@@ -2195,7 +2249,8 @@ COMMAND_HANDLER(handle_dap_info_command)
 COMMAND_HANDLER(dap_baseaddr_command)
 {
 	struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
-	uint32_t apsel, baseaddr_lower, baseaddr_upper;
+	uint64_t apsel;
+	uint32_t baseaddr_lower, baseaddr_upper;
 	struct adiv5_ap *ap;
 	target_addr_t baseaddr;
 	int retval;
@@ -2207,9 +2262,8 @@ COMMAND_HANDLER(dap_baseaddr_command)
 		apsel = dap->apsel;
 		break;
 	case 1:
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
-		/* AP address is in bits 31:24 of DP_SELECT */
-		if (apsel > DP_APSEL_MAX) {
+		COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
+		if (!is_ap_num_valid(dap, apsel)) {
 			command_print(CMD, "Invalid AP number");
 			return ERROR_COMMAND_ARGUMENT_INVALID;
 		}
@@ -2294,16 +2348,15 @@ COMMAND_HANDLER(dap_memaccess_command)
 COMMAND_HANDLER(dap_apsel_command)
 {
 	struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
-	uint32_t apsel;
+	uint64_t apsel;
 
 	switch (CMD_ARGC) {
 	case 0:
-		command_print(CMD, "%" PRIu32, dap->apsel);
+		command_print(CMD, "0x%" PRIx64, dap->apsel);
 		return ERROR_OK;
 	case 1:
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
-		/* AP address is in bits 31:24 of DP_SELECT */
-		if (apsel > DP_APSEL_MAX) {
+		COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
+		if (!is_ap_num_valid(dap, apsel)) {
 			command_print(CMD, "Invalid AP number");
 			return ERROR_COMMAND_ARGUMENT_INVALID;
 		}
@@ -2329,7 +2382,7 @@ COMMAND_HANDLER(dap_apcsw_command)
 			command_print(CMD, "Cannot get AP");
 			return ERROR_FAIL;
 		}
-		command_print(CMD, "ap %" PRIu32 " selected, csw 0x%8.8" PRIx32,
+		command_print(CMD, "AP#0x%" PRIx64 " selected, csw 0x%8.8" PRIx32,
 			dap->apsel, ap->csw_default);
 		break;
 	case 1:
@@ -2376,7 +2429,8 @@ COMMAND_HANDLER(dap_apcsw_command)
 COMMAND_HANDLER(dap_apid_command)
 {
 	struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
-	uint32_t apsel, apid;
+	uint64_t apsel;
+	uint32_t apid;
 	int retval;
 
 	switch (CMD_ARGC) {
@@ -2384,9 +2438,8 @@ COMMAND_HANDLER(dap_apid_command)
 		apsel = dap->apsel;
 		break;
 	case 1:
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
-		/* AP address is in bits 31:24 of DP_SELECT */
-		if (apsel > DP_APSEL_MAX) {
+		COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
+		if (!is_ap_num_valid(dap, apsel)) {
 			command_print(CMD, "Invalid AP number");
 			return ERROR_COMMAND_ARGUMENT_INVALID;
 		}
@@ -2418,23 +2471,30 @@ COMMAND_HANDLER(dap_apid_command)
 COMMAND_HANDLER(dap_apreg_command)
 {
 	struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
-	uint32_t apsel, reg, value;
+	uint64_t apsel;
+	uint32_t reg, value;
 	int retval;
 
 	if (CMD_ARGC < 2 || CMD_ARGC > 3)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
-	/* AP address is in bits 31:24 of DP_SELECT */
-	if (apsel > DP_APSEL_MAX) {
+	COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
+	if (!is_ap_num_valid(dap, apsel)) {
 		command_print(CMD, "Invalid AP number");
 		return ERROR_COMMAND_ARGUMENT_INVALID;
 	}
 
 	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
-	if (reg >= 256 || (reg & 3)) {
-		command_print(CMD, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
-		return ERROR_COMMAND_ARGUMENT_INVALID;
+	if (is_adiv6(dap)) {
+		if (reg >= 4096 || (reg & 3)) {
+			command_print(CMD, "Invalid reg value (should be less than 4096 and 4 bytes aligned)");
+			return ERROR_COMMAND_ARGUMENT_INVALID;
+		}
+	} else {	/* ADI version 5 */
+		if (reg >= 256 || (reg & 3)) {
+			command_print(CMD, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
+			return ERROR_COMMAND_ARGUMENT_INVALID;
+		}
 	}
 
 	struct adiv5_ap *ap = dap_get_ap(dap, apsel);
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 4eab35d6e..534dd3b73 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -110,8 +110,8 @@
 #define DP_SELECT_DPBANK 0x0000000F
 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
 
-#define DP_APSEL_MAX        (255)
-#define DP_APSEL_INVALID    (-1)
+#define DP_APSEL_MAX        (255) /* for ADIv5 only */
+#define DP_APSEL_INVALID    0xF00 /* more than DP_APSEL_MAX and not ADIv6 aligned 4k */
 
 #define DP_TARGETSEL_INVALID 0xFFFFFFFFU
 #define DP_TARGETSEL_DPID_MASK 0x0FFFFFFFU
@@ -255,9 +255,11 @@ struct adiv5_ap {
 	struct adiv5_dap *dap;
 
 	/**
-	 * Number of this AP.
+	 * ADIv5: Number of this AP (0~255)
+	 * ADIv6: Base address of this AP (4k aligned)
+	 * TODO: to be more coherent, it should be renamed apsel
 	 */
-	uint8_t ap_num;
+	uint64_t ap_num;
 
 	/**
 	 * Default value for (MEM-AP) AP_REG_CSW register.
@@ -342,7 +344,7 @@ struct adiv5_dap {
 	struct adiv5_ap ap[DP_APSEL_MAX + 1];
 
 	/* The current manually selected AP by the "dap apsel" command */
-	uint32_t apsel;
+	uint64_t apsel;
 
 	/**
 	 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
@@ -551,7 +553,7 @@ static inline int dap_queue_ap_read(struct adiv5_ap *ap,
 	assert(ap->dap->ops);
 	if (ap->refcount == 0) {
 		ap->refcount = 1;
-		LOG_ERROR("BUG: refcount AP#%" PRIu8 " used without get", ap->ap_num);
+		LOG_ERROR("BUG: refcount AP#0x%" PRIx64 " used without get", ap->ap_num);
 	}
 	return ap->dap->ops->queue_ap_read(ap, reg, data);
 }
@@ -571,7 +573,7 @@ static inline int dap_queue_ap_write(struct adiv5_ap *ap,
 	assert(ap->dap->ops);
 	if (ap->refcount == 0) {
 		ap->refcount = 1;
-		LOG_ERROR("BUG: refcount AP#%" PRIu8 " used without get", ap->ap_num);
+		LOG_ERROR("BUG: refcount AP#0x%" PRIx64 " used without get", ap->ap_num);
 	}
 	return ap->dap->ops->queue_ap_write(ap, reg, data);
 }
@@ -690,16 +692,19 @@ int mem_ap_init(struct adiv5_ap *ap);
 /* Invalidate cached DP select and cached TAR and CSW of all APs */
 void dap_invalidate_cache(struct adiv5_dap *dap);
 
+/* test if ap_num is valid, based on current knowledge of dap */
+bool is_ap_num_valid(struct adiv5_dap *dap, uint64_t ap_num);
+
 /* Probe Access Ports to find a particular type. Increment AP refcount */
 int dap_find_get_ap(struct adiv5_dap *dap,
 			enum ap_type type_to_find,
 			struct adiv5_ap **ap_out);
 
 /* Return AP with specified ap_num. Increment AP refcount */
-struct adiv5_ap *dap_get_ap(struct adiv5_dap *dap, unsigned int ap_num);
+struct adiv5_ap *dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num);
 
 /* Return AP with specified ap_num. Increment AP refcount and keep it non-zero */
-struct adiv5_ap *dap_get_config_ap(struct adiv5_dap *dap, unsigned int ap_num);
+struct adiv5_ap *dap_get_config_ap(struct adiv5_dap *dap, uint64_t ap_num);
 
 /* Decrement AP refcount and release the AP when refcount reaches zero */
 int dap_put_ap(struct adiv5_ap *ap);
@@ -735,7 +740,7 @@ extern const struct swd_driver *adiv5_dap_swd_driver(struct adiv5_dap *self);
 extern int dap_cleanup_all(void);
 
 struct adiv5_private_config {
-	int ap_num;
+	uint64_t ap_num;
 	struct adiv5_dap *dap;
 };
 
@@ -744,7 +749,7 @@ extern int adiv5_jim_configure(struct target *target, struct jim_getopt_info *go
 
 struct adiv5_mem_ap_spot {
 	struct adiv5_dap *dap;
-	int ap_num;
+	uint64_t ap_num;
 	uint32_t base;
 };
 
diff --git a/src/target/arm_dap.c b/src/target/arm_dap.c
index d2e3f9997..cfd14de93 100644
--- a/src/target/arm_dap.c
+++ b/src/target/arm_dap.c
@@ -50,7 +50,7 @@ static void dap_instance_init(struct adiv5_dap *dap)
 	/* Set up with safe defaults */
 	for (i = 0; i <= DP_APSEL_MAX; i++) {
 		dap->ap[i].dap = dap;
-		dap->ap[i].ap_num = i;
+		dap->ap[i].ap_num = DP_APSEL_INVALID;
 		/* memaccess_tck max is 255 */
 		dap->ap[i].memaccess_tck = 255;
 		/* Number of bits for tar autoincrement, impl. dep. at least 10 */
@@ -459,7 +459,7 @@ COMMAND_HANDLER(handle_dap_info_command)
 	struct target *target = get_current_target(CMD_CTX);
 	struct arm *arm = target_to_arm(target);
 	struct adiv5_dap *dap = arm->dap;
-	uint32_t apsel;
+	uint64_t apsel;
 
 	if (!dap) {
 		LOG_ERROR("DAP instance not available. Probably a HLA target...");
@@ -471,8 +471,8 @@ COMMAND_HANDLER(handle_dap_info_command)
 			apsel = dap->apsel;
 			break;
 		case 1:
-			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
-			if (apsel > DP_APSEL_MAX)
+			COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
+			if (!is_ap_num_valid(dap, apsel))
 				return ERROR_COMMAND_SYNTAX_ERROR;
 			break;
 		default:
diff --git a/src/target/arm_tpiu_swo.c b/src/target/arm_tpiu_swo.c
index 5cbd89b86..a9f558e12 100644
--- a/src/target/arm_tpiu_swo.c
+++ b/src/target/arm_tpiu_swo.c
@@ -617,8 +617,8 @@ static int jim_arm_tpiu_swo_enable(Jim_Interp *interp, int argc, Jim_Obj *const
 	if (obj->enabled)
 		return JIM_OK;
 
-	if (transport_is_hla() && obj->spot.ap_num > 0) {
-		LOG_ERROR("Invalid access port %d. Only AP#0 allowed with hla transport", obj->spot.ap_num);
+	if (transport_is_hla() && obj->spot.ap_num != 0) {
+		LOG_ERROR("Invalid access port 0x%" PRIx64 ". Only AP#0 allowed with hla transport", obj->spot.ap_num);
 		return JIM_ERR;
 	}
 
@@ -650,8 +650,8 @@ static int jim_arm_tpiu_swo_enable(Jim_Interp *interp, int argc, Jim_Obj *const
 		if (obj->spot.ap_num == 0)
 			LOG_INFO(MSG "Confirmed TPIU %s is on AP 0", obj->name);
 		else
-			LOG_INFO(MSG "Target %s is on AP %d. Revised command is "
-				"\'tpiu create %s -dap %s -ap-num %d\'",
+			LOG_INFO(MSG "Target %s is on AP#0x%" PRIx64 ". Revised command is "
+				"\'tpiu create %s -dap %s -ap-num 0x%" PRIx64 "\'",
 				target_name(target), obj->spot.ap_num,
 				obj->name, adiv5_dap_name(obj->spot.dap), obj->spot.ap_num);
 	}
@@ -1047,7 +1047,7 @@ COMMAND_HANDLER(handle_tpiu_deprecated_config_command)
 		struct cortex_m_common *cm = target_to_cm(target);
 		struct adiv5_private_config *pc = target->private_config;
 		struct adiv5_dap *dap = pc->dap;
-		int ap_num = pc->ap_num;
+		uint64_t ap_num = pc->ap_num;
 		bool set_recheck_ap_cur_target = false;
 
 		LOG_INFO(MSG "Adding a TPIU \'%s.tpiu\' in the configuration", target_name(target));
@@ -1065,10 +1065,10 @@ COMMAND_HANDLER(handle_tpiu_deprecated_config_command)
 			set_recheck_ap_cur_target = true;
 		}
 
-		LOG_INFO(MSG "Running: \'tpiu create %s.tpiu -dap %s -ap-num %d\'",
+		LOG_INFO(MSG "Running: \'tpiu create %s.tpiu -dap %s -ap-num 0x%" PRIx64 "\'",
 			target_name(target), adiv5_dap_name(dap), ap_num);
 
-		retval = command_run_linef(CMD_CTX, "tpiu create %s.tpiu -dap %s -ap-num %d",
+		retval = command_run_linef(CMD_CTX, "tpiu create %s.tpiu -dap %s -ap-num 0x%" PRIx64,
 			target_name(target), adiv5_dap_name(dap), ap_num);
 		if (retval != ERROR_OK)
 			return retval;
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 555401416..1fab871e1 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -241,7 +241,7 @@ struct cortex_m_common {
 
 	bool slow_register_read;	/* A register has not been ready, poll S_REGRDY */
 
-	int apsel;
+	uint64_t apsel;
 
 	/* Whether this target has the erratum that makes C_MASKINTS not apply to
 	 * already pending interrupts */
diff --git a/src/target/hla_target.c b/src/target/hla_target.c
index 3e359b950..487ffe7c9 100644
--- a/src/target/hla_target.c
+++ b/src/target/hla_target.c
@@ -203,7 +203,7 @@ static int adapter_target_create(struct target *target,
 {
 	LOG_DEBUG("%s", __func__);
 	struct adiv5_private_config *pc = target->private_config;
-	if (pc && pc->ap_num > 0) {
+	if (pc && pc->ap_num != DP_APSEL_INVALID && pc->ap_num != 0) {
 		LOG_ERROR("hla_target: invalid parameter -ap-num (> 0)");
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
diff --git a/src/target/mem_ap.c b/src/target/mem_ap.c
index 86bb29f21..cf5aa5449 100644
--- a/src/target/mem_ap.c
+++ b/src/target/mem_ap.c
@@ -29,7 +29,7 @@ struct mem_ap {
 	int common_magic;
 	struct adiv5_dap *dap;
 	struct adiv5_ap *ap;
-	int ap_num;
+	uint64_t ap_num;
 };
 
 static int mem_ap_target_create(struct target *target, Jim_Interp *interp)

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi              |  27 +++++++--
 src/jtag/drivers/stlink_usb.c |  11 ++--
 src/target/arm_adi_v5.c       | 136 ++++++++++++++++++++++++++++++------------
 src/target/arm_adi_v5.h       |  27 +++++----
 src/target/arm_dap.c          |   8 +--
 src/target/arm_tpiu_swo.c     |  14 ++---
 src/target/cortex_m.h         |   2 +-
 src/target/hla_target.c       |   2 +-
 src/target/mem_ap.c           |   2 +-
 9 files changed, 156 insertions(+), 73 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-723-g72fb88613

From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:37:47

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- Log -----------------------------------------------------------------
commit 72fb88613f02f2c9336426f78312ec2b1ad6ba3f
Author: Antonio Borneo <bor...@gm...>
Date:   Thu Nov 11 23:49:23 2021 +0100

    adiv6: add low level swd transport
    
    During enter in SWD read DP_DPIDR without selecting the register
    bank through DP_SELECT_DPBANK.
    Handle the different format of DP_SELECT register.
    
    Change-Id: Iea1b8eb6ec94177e16a430d5885595a38e833eeb
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/6697
    Tested-by: jenkins

diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c
index 6ef138aa7..d10667a33 100644
--- a/src/target/adi_v5_swd.c
+++ b/src/target/adi_v5_swd.c
@@ -29,6 +29,7 @@
  * for details, see "ARM IHI 0031A"
  * ARM Debug Interface v5 Architecture Specification
  * especially section 5.3 for SWD protocol
+ * and "ARM IHI 0074C" ARM Debug Interface Architecture Specification ADIv6.0
  *
  * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
  * to JTAG.  Boards may support one or both.  There are also SWD-only chips,
@@ -112,20 +113,20 @@ static inline int check_sync(struct adiv5_dap *dap)
 /** Select the DP register bank matching bits 7:4 of reg. */
 static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned int reg)
 {
-	/* Only register address 4 is banked. */
-	if ((reg & 0xf) != 4)
+	/* Only register address 0 and 4 are banked. */
+	if ((reg & 0xf) > 4)
 		return ERROR_OK;
 
-	uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
-	uint32_t sel = select_dp_bank
-			| (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
+	uint64_t sel = (reg & 0x000000F0) >> 4;
+	if (dap->select != DP_SELECT_INVALID)
+		sel |= dap->select & ~0xfULL;
 
 	if (sel == dap->select)
 		return ERROR_OK;
 
 	dap->select = sel;
 
-	int retval = swd_queue_dp_write_inner(dap, DP_SELECT, sel);
+	int retval = swd_queue_dp_write_inner(dap, DP_SELECT, (uint32_t)sel);
 	if (retval != ERROR_OK)
 		dap->select = DP_SELECT_INVALID;
 
@@ -326,6 +327,21 @@ static int swd_connect_single(struct adiv5_dap *dap)
 		dap->do_reconnect = false;
 		dap_invalidate_cache(dap);
 
+		/* The sequences to enter in SWD (JTAG_TO_SWD and DORMANT_TO_SWD) end
+		 * with a SWD line reset sequence (50 clk with SWDIO high).
+		 * From ARM IHI 0074C ADIv6.0, chapter B4.3.3 "Connection and line reset
+		 * sequence":
+		 * - line reset sets DP_SELECT_DPBANK to zero;
+		 * - read of DP_DPIDR takes the connection out of reset;
+		 * - write of DP_TARGETSEL keeps the connection in reset;
+		 * - other accesses return protocol error (SWDIO not driven by target).
+		 *
+		 * Read DP_DPIDR to get out of reset. Initialize dap->select to zero to
+		 * skip the write to DP_SELECT, avoiding the protocol error. Set again
+		 * dap->select to DP_SELECT_INVALID because the rest of the register is
+		 * unknown after line reset.
+		 */
+		dap->select = 0;
 		retval = swd_queue_dp_read_inner(dap, DP_DPIDR, &dpidr);
 		if (retval == ERROR_OK) {
 			retval = swd_run_inner(dap);
@@ -337,6 +353,7 @@ static int swd_connect_single(struct adiv5_dap *dap)
 
 		dap->switch_through_dormant = !dap->switch_through_dormant;
 	} while (timeval_ms() < timeout);
+	dap->select = DP_SELECT_INVALID;
 
 	if (retval != ERROR_OK) {
 		LOG_ERROR("Error connecting DP: cannot read IDR");
@@ -473,17 +490,42 @@ static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
 /** Select the AP register bank matching bits 7:4 of reg. */
 static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
 {
+	int retval;
 	struct adiv5_dap *dap = ap->dap;
-	uint32_t sel = ((uint32_t)ap->ap_num << 24)
-			| (reg & 0x000000F0)
-			| (dap->select & DP_SELECT_DPBANK);
+	uint64_t sel;
+
+	if (is_adiv6(dap)) {
+		sel = ap->ap_num | (reg & 0x00000FF0);
+		if (sel == (dap->select & ~0xfULL))
+			return ERROR_OK;
+
+		if (dap->select != DP_SELECT_INVALID)
+			sel |= dap->select & 0xf;
+		dap->select = sel;
+		LOG_DEBUG("AP BANKSEL: %" PRIx64, sel);
+
+		retval = swd_queue_dp_write(dap, DP_SELECT, (uint32_t)sel);
+
+		if (retval == ERROR_OK && dap->asize > 32)
+			retval = swd_queue_dp_write(dap, DP_SELECT1, (uint32_t)(sel >> 32));
+
+		if (retval != ERROR_OK)
+			dap->select = DP_SELECT_INVALID;
+
+		return retval;
+	}
+
+	/* ADIv5 */
+	sel = (ap->ap_num << 24) | (reg & 0x000000F0);
+	if (dap->select != DP_SELECT_INVALID)
+		sel |= dap->select & DP_SELECT_DPBANK;
 
 	if (sel == dap->select)
 		return ERROR_OK;
 
 	dap->select = sel;
 
-	int retval = swd_queue_dp_write_inner(dap, DP_SELECT, sel);
+	retval = swd_queue_dp_write_inner(dap, DP_SELECT, sel);
 	if (retval != ERROR_OK)
 		dap->select = DP_SELECT_INVALID;
 
@@ -497,14 +539,6 @@ static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
 	const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 	assert(swd);
 
-	if (is_adiv6(dap)) {
-		static bool error_flagged;
-		if (!error_flagged)
-			LOG_ERROR("ADIv6 dap not supported in SWD mode");
-		error_flagged = true;
-		return ERROR_FAIL;
-	}
-
 	int retval = swd_check_reconnect(dap);
 	if (retval != ERROR_OK)
 		return retval;
@@ -530,14 +564,6 @@ static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
 	const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 	assert(swd);
 
-	if (is_adiv6(dap)) {
-		static bool error_flagged;
-		if (!error_flagged)
-			LOG_ERROR("ADIv6 dap not supported in SWD mode");
-		error_flagged = true;
-		return ERROR_FAIL;
-	}
-
 	int retval = swd_check_reconnect(dap);
 	if (retval != ERROR_OK)
 		return retval;

-----------------------------------------------------------------------

Summary of changes:
 src/target/adi_v5_swd.c | 78 ++++++++++++++++++++++++++++++++-----------------
 1 file changed, 52 insertions(+), 26 deletions(-)


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From: OpenOCD-Gerrit <ope...@us...> - 2022-06-24 21:37:25

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  62058c0a32e0e98db39087f8c1e29085e611f2b8 (commit)
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- Log -----------------------------------------------------------------
commit 62058c0a32e0e98db39087f8c1e29085e611f2b8
Author: Kevin Burke <ke...@os...>
Date:   Sat Aug 14 18:55:28 2021 +0200

    adi_v5_jtag: extend memaccess_tck to every AP access
    
    ADIv5 reports:
            Accessing AP registers or debug resources in connected
            device through an AP can be subjected to other variable
            response delays in the system. A debugger that can adapt
            to these delays and avoid wasting WAIT scans operates more
            efficiently and provides higher maximum data throughput.
    
    The existing code in OpenOCD uses extra tck only for accessing
    resources through an AP.
    
    Extend the use of extra tck also for accessing an AP register.
    
    Split from change https://review.openocd.org/6077/
    
    Change-Id: I2082362e098d09f4ba0668e01f5196afc965c8f3
    Signed-off-by: Kevin Burke <ke...@os...>
    Signed-off-by: Daniel Goehring <dgo...@os...>
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/6460
    Tested-by: jenkins

diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index 810a5ab76..67ad0b1e9 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -284,17 +284,14 @@ static int adi_jtag_dp_scan_cmd(struct adiv5_dap *dap, struct dap_cmd *cmd, uint
 
 	jtag_add_dr_scan(tap, 2, cmd->fields, TAP_IDLE);
 
-	/* Add specified number of tck clocks after starting memory bus
-	 * access, giving the hardware time to complete the access.
+	/* Add specified number of tck clocks after starting AP register
+	 * access or memory bus access, giving the hardware time to complete
+	 * the access.
 	 * They provide more time for the (MEM) AP to complete the read ...
 	 * See "Minimum Response Time" for JTAG-DP, in the ADIv5/ADIv6 spec.
 	 */
-	if (cmd->instr == JTAG_DP_APACC) {
-		if ((cmd->reg_addr == MEM_AP_REG_DRW(dap) ||
-			 (cmd->reg_addr & 0xFF0) == MEM_AP_REG_BD0(dap)) &&
-			cmd->memaccess_tck != 0)
-			jtag_add_runtest(cmd->memaccess_tck, TAP_IDLE);
-	}
+	if (cmd->instr == JTAG_DP_APACC && cmd->memaccess_tck != 0)
+		jtag_add_runtest(cmd->memaccess_tck, TAP_IDLE);
 
 	return ERROR_OK;
 }

-----------------------------------------------------------------------

Summary of changes:
 src/target/adi_v5_jtag.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)


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