openocd-commit — OpenOCD commit maling list - read only

[Openocd-svn] r1958 - trunk/src/target

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-31 08:00:28 +0200 (Sun, 31 May 2009)
New Revision: 1958

Modified:
   trunk/src/target/target.c
Log:
Simplify the handle_md_command routine in target.c:
 - fix buffer overrun in mdw; final '\0' would overflow the output buffer.
 - return ERROR_COMMAND_SYNTAX_ERROR instead of ERROR_OK if:
   - less than one argument is provided
   - the command is called with a name other than mdb, mdh, or mdw.
 - factor all command output into new handle_md_output function


Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c	2009-05-31 04:58:51 UTC (rev 1957)
+++ trunk/src/target/target.c	2009-05-31 06:00:28 UTC (rev 1958)
@@ -1844,77 +1844,80 @@
 	return ERROR_OK;
 }
 
-static int handle_md_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static void handle_md_output(struct command_context_s *cmd_ctx,
+		struct target_s *target, u32 address, unsigned size,
+		unsigned count, const u8 *buffer)
 {
-	const int line_bytecnt = 32;
-	int count = 1;
-	int size = 4;
-	u32 address = 0;
-	int line_modulo;
-	int i;
+	const unsigned line_bytecnt = 32;
+	unsigned line_modulo = line_bytecnt / size;
 
-	char output[128];
-	int output_len;
+	char output[line_bytecnt * 4 + 1];
+	unsigned output_len = 0;
 
-	int retval;
+	const char *value_fmt;
+	switch (size) {
+	case 4: value_fmt = "%8.8x"; break;
+	case 2: value_fmt = "%4.2x"; break;
+	case 1: value_fmt = "%2.2x"; break;
+	default:
+		LOG_ERROR("invalid memory read size: %u", size);
+		exit(-1);
+	}
 
-	u8 *buffer;
-	target_t *target = get_current_target(cmd_ctx);
+	for (unsigned i = 0; i < count; i++)
+	{
+		if (i % line_modulo == 0)
+		{
+			output_len += snprintf(output + output_len,
+					sizeof(output) - output_len,
+					"0x%8.8x: ", address + (i*size));
+		}
 
-	if (argc < 1)
-		return ERROR_OK;
+		u32 value;
+		const u8 *value_ptr = buffer + i * size;
+		switch (size) {
+		case 4: value = target_buffer_get_u32(target, value_ptr); break;
+		case 2: value = target_buffer_get_u16(target, value_ptr); break;
+		case 1: value = *value_ptr;
+		}
+		output_len += snprintf(output + output_len,
+				sizeof(output) - output_len,
+				value_fmt, value);
 
-	if (argc == 2)
-		count = strtoul(args[1], NULL, 0);
+		if ((i % line_modulo == line_modulo - 1) || (i == count - 1))
+		{
+			command_print(cmd_ctx, "%s", output);
+			output_len = 0;
+		}
+	}
+}
 
-	address = strtoul(args[0], NULL, 0);
+static int handle_md_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+	if (argc < 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	switch (cmd[2])
-	{
-		case 'w':
-			size = 4; line_modulo = line_bytecnt / 4;
-			break;
-		case 'h':
-			size = 2; line_modulo = line_bytecnt / 2;
-			break;
-		case 'b':
-			size = 1; line_modulo = line_bytecnt / 1;
-			break;
-		default:
-			return ERROR_OK;
+	unsigned size = 0;
+	switch (cmd[2]) {
+	case 'w': size = 4; break;
+	case 'h': size = 2; break;
+	case 'b': size = 1; break;
+	default: return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	buffer = calloc(count, size);
-	retval  = target->type->read_memory(target, address, size, count, buffer);
-	if (retval == ERROR_OK)
-	{
-		output_len = 0;
+	u32 address = strtoul(args[0], NULL, 0);
 
-		for (i = 0; i < count; i++)
-		{
-			if (i%line_modulo == 0)
-				output_len += snprintf(output + output_len, 128 - output_len, "0x%8.8x: ", address + (i*size));
+	unsigned count = 1;
+	if (argc == 2)
+		count = strtoul(args[1], NULL, 0);
 
-			switch (size)
-			{
-				case 4:
-					output_len += snprintf(output + output_len, 128 - output_len, "%8.8x ", target_buffer_get_u32(target, &buffer[i*4]));
-					break;
-				case 2:
-					output_len += snprintf(output + output_len, 128 - output_len, "%4.4x ", target_buffer_get_u16(target, &buffer[i*2]));
-					break;
-				case 1:
-					output_len += snprintf(output + output_len, 128 - output_len, "%2.2x ", buffer[i*1]);
-					break;
-			}
+	u8 *buffer = calloc(count, size);
 
-			if ((i%line_modulo == line_modulo-1) || (i == count - 1))
-			{
-				command_print(cmd_ctx, "%s", output);
-				output_len = 0;
-			}
-		}
-	}
+	target_t *target = get_current_target(cmd_ctx);
+	int retval = target->type->read_memory(target,
+				address, size, count, buffer);
+	if (ERROR_OK == retval)
+		handle_md_output(cmd_ctx, target, address, size, count, buffer);
 
 	free(buffer);
 

[Openocd-svn] r1957 - trunk/src/target

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-31 06:58:51 +0200 (Sun, 31 May 2009)
New Revision: 1957

Modified:
   trunk/src/target/target.c
   trunk/src/target/target.h
Log:
Make nvp_target_event static; remove its external declaration.

Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c	2009-05-31 02:18:26 UTC (rev 1956)
+++ trunk/src/target/target.c	2009-05-31 04:58:51 UTC (rev 1957)
@@ -150,7 +150,7 @@
 	}
 }
 
-const Jim_Nvp nvp_target_event[] = {
+static const Jim_Nvp nvp_target_event[] = {
 	{ .value = TARGET_EVENT_OLD_gdb_program_config , .name = "old-gdb_program_config" },
 	{ .value = TARGET_EVENT_OLD_pre_resume         , .name = "old-pre_resume" },
 

Modified: trunk/src/target/target.h
===================================================================
--- trunk/src/target/target.h	2009-05-31 02:18:26 UTC (rev 1956)
+++ trunk/src/target/target.h	2009-05-31 04:58:51 UTC (rev 1957)
@@ -318,8 +318,6 @@
 	TARGET_EVENT_GDB_FLASH_WRITE_END,
 };
 
-extern const Jim_Nvp nvp_target_event[];
-
 struct target_event_action_s {
 	enum target_event event;
 	Jim_Obj *body;

[Openocd-svn] r1956 - trunk/src/target

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-31 04:18:26 +0200 (Sun, 31 May 2009)
New Revision: 1956

Modified:
   trunk/src/target/target.c
   trunk/src/target/target.h
Log:
Make target_buffer_get_uXX interfaces work with constant buffers.

Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c	2009-05-31 01:07:43 UTC (rev 1955)
+++ trunk/src/target/target.c	2009-05-31 02:18:26 UTC (rev 1956)
@@ -273,7 +273,7 @@
 static int target_continous_poll = 1;
 
 /* read a u32 from a buffer in target memory endianness */
-u32 target_buffer_get_u32(target_t *target, u8 *buffer)
+u32 target_buffer_get_u32(target_t *target, const u8 *buffer)
 {
 	if (target->endianness == TARGET_LITTLE_ENDIAN)
 		return le_to_h_u32(buffer);
@@ -282,7 +282,7 @@
 }
 
 /* read a u16 from a buffer in target memory endianness */
-u16 target_buffer_get_u16(target_t *target, u8 *buffer)
+u16 target_buffer_get_u16(target_t *target, const u8 *buffer)
 {
 	if (target->endianness == TARGET_LITTLE_ENDIAN)
 		return le_to_h_u16(buffer);
@@ -291,7 +291,7 @@
 }
 
 /* read a u8 from a buffer in target memory endianness */
-u8 target_buffer_get_u8(target_t *target, u8 *buffer)
+u8 target_buffer_get_u8(target_t *target, const u8 *buffer)
 {
 	return *buffer & 0x0ff;
 }

Modified: trunk/src/target/target.h
===================================================================
--- trunk/src/target/target.h	2009-05-31 01:07:43 UTC (rev 1955)
+++ trunk/src/target/target.h	2009-05-31 02:18:26 UTC (rev 1956)
@@ -401,9 +401,9 @@
 extern target_event_callback_t *target_event_callbacks;
 extern target_timer_callback_t *target_timer_callbacks;
 
-extern u32 target_buffer_get_u32(target_t *target, u8 *buffer);
-extern u16 target_buffer_get_u16(target_t *target, u8 *buffer);
-extern u8  target_buffer_get_u8 (target_t *target, u8 *buffer);
+extern u32 target_buffer_get_u32(target_t *target, const u8 *buffer);
+extern u16 target_buffer_get_u16(target_t *target, const u8 *buffer);
+extern u8  target_buffer_get_u8 (target_t *target, const u8 *buffer);
 extern void target_buffer_set_u32(target_t *target, u8 *buffer, u32 value);
 extern void target_buffer_set_u16(target_t *target, u8 *buffer, u16 value);
 extern void target_buffer_set_u8 (target_t *target, u8 *buffer, u8  value);

[Openocd-svn] r1955 - trunk/src/jtag

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-31 03:07:43 +0200 (Sun, 31 May 2009)
New Revision: 1955

Modified:
   trunk/src/jtag/jlink.c
Log:
Peter Denison <op...@ma...>:

The debugging code in jlink_tap_execute() called when _DEBUG_USB_COMMS_ is 
defined was using the entire cached scan length to print the results 
buffers, and not the correct length of each individual buffer.


Modified: trunk/src/jtag/jlink.c
===================================================================
--- trunk/src/jtag/jlink.c	2009-05-31 00:49:03 UTC (rev 1954)
+++ trunk/src/jtag/jlink.c	2009-05-31 01:07:43 UTC (rev 1955)
@@ -809,7 +809,7 @@
 		DEBUG_JTAG_IO("pending scan result, length = %d", length);
 
 #ifdef _DEBUG_USB_COMMS_
-		jlink_debug_buffer(buffer, byte_length);
+		jlink_debug_buffer(buffer, TAP_SCAN_BYTES(length));
 #endif
 
 		if (jtag_read_buffer(buffer, command) != ERROR_OK)

[Openocd-svn] r1954 - trunk/doc/manual/primer

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-31 02:49:03 +0200 (Sun, 31 May 2009)
New Revision: 1954

Modified:
   trunk/doc/manual/primer/jtag.txt
Log:
Add new JTAG boundary scan primer, with links to BSDL information.

Modified: trunk/doc/manual/primer/jtag.txt
===================================================================
--- trunk/doc/manual/primer/jtag.txt	2009-05-30 23:57:30 UTC (rev 1953)
+++ trunk/doc/manual/primer/jtag.txt	2009-05-31 00:49:03 UTC (rev 1954)
@@ -11,12 +11,10 @@
 Think of JTAG as I2C for testing.  It doesn't define what it can do, 
 just a logical interface that allows a uniform channel for communication.
 
-See:
-
+See @par
 	http://en.wikipedia.org/wiki/Joint_Test_Action_Group
 
-and
-
+and @par
 	http://www.inaccessnetworks.com/projects/ianjtag/jtag-intro/jtag-state-machine-large.png
 
 The first page (among other things) shows a logical representation 
@@ -107,4 +105,64 @@
 registers do, so you can actually do something useful.  That's where it
 gets interesting.  But in and of itself, JTAG is actually very simple.
 
+A separate primer contains information about @subpage primerjtagbs for
+developers that want to extend OpenOCD for such purposes.
+
  */
+/** @page primerjtagbs JTAG Boundary Scan Primer
+
+The following page provides an introduction on JTAG that focuses on its
+boundary scan capabilities: @par
+http://www.engr.udayton.edu/faculty/jloomis/ece446/notes/jtag/jtag1.html
+
+OpenOCD does not presently have clear means of using JTAG for boundary
+scan testing purposes; however, some developers have explored the
+possibilities.  The page contains information that may be useful to
+those wishing to implement boundary scan capabilities in OpenOCD.
+
+@section primerbsdl The BSDL Language
+
+For more information on the Boundary Scan Description Language (BSDL),
+the following page provides a good introduction: @par
+http://www.radio-electronics.com/info/t_and_m/boundaryscan/bsdl.php
+
+@section primerbsdlvendors Vendor BSDL Files
+
+NXP LPC: @par
+http://www.standardics.nxp.com/support/models/lpc2000/
+
+Freescale PowerPC: @par
+http://www.freescale.com/webapp/sps/site/overview.jsp?code=DRPPCBSDLFLS
+
+Freescale i.MX1 (too old): @par
+http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX1&nodeId=0162468rH311432973ZrDR&fpsp=1&tab=Design_Tools_Tab
+
+Renesas R32C/117: @par
+http://sg.renesas.com/fmwk.jsp?cnt=r32c116_7_8_root.jsp&fp=/products/mpumcu/m16c_family/r32c100_series/r32c116_7_8_group/
+- The device page does not come with BSDL file; you have to register to
+  download them. @par
+  http://www.corelis.com/support/BSDL.htm
+
+TI links theirs right off the generic page for each chip;
+this may be the case for other vendors as well.  For example:
+
+- DaVinci DM355 -- http://www.ti.com/litv/zip/sprm262b
+- DaVinci DM6446
+  - 2.1 silicon -- http://www.ti.com/litv/zip/sprm325a
+  - older silicon -- http://www.ti.com/litv/zip/sprm203
+- OMAP 3530
+  - CBB package -- http://www.ti.com/litv/zip/sprm315b
+    - 515 ball s-PGBA, POP, 0.4mm pitch
+  - CUS package -- http://www.ti.com/litv/zip/sprm314a
+    - 515 ball s-PGBA, POP, 0.5mm pitch
+  - CBC package -- http://www.ti.com/litv/zip/sprm346
+    - 423 ball s-PGBA, 0.65mm pitch
+
+Many other files are available in the "Semiconductor Manufacturer's BSDL
+files" section of the following site: @par
+http://www.freelabs.com/~whitis/electronics/jtag/
+
+ */
+/** @file
+This file contains the @ref primerjtag and @ref bsdl page.
+ */

[Openocd-svn] r1953 - trunk/src/target

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-31 01:57:30 +0200 (Sun, 31 May 2009)
New Revision: 1953

Modified:
   trunk/src/target/target.c
Log:
Eliminate duplicated code in the handle_mw_command memory write loop.
- wordsize will always be 1, 2, or 4 due to preceeding switch statement.
- move call to keep_alive after successful writes, not upon failures


Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c	2009-05-30 22:23:12 UTC (rev 1952)
+++ trunk/src/target/target.c	2009-05-30 23:57:30 UTC (rev 1953)
@@ -1958,27 +1958,11 @@
 	}
 	for (i=0; i<count; i++)
 	{
-		int retval;
-		switch (wordsize)
-		{
-			case 4:
-				retval = target->type->write_memory(target, address + i*wordsize, 4, 1, value_buf);
-				break;
-			case 2:
-				retval = target->type->write_memory(target, address + i*wordsize, 2, 1, value_buf);
-				break;
-			case 1:
-				retval = target->type->write_memory(target, address + i*wordsize, 1, 1, value_buf);
-			break;
-			default:
-			return ERROR_OK;
-		}
-		keep_alive();
-
-		if (retval!=ERROR_OK)
-		{
+		int retval = target->type->write_memory(target,
+				address + i * wordsize, wordsize, 1, value_buf);
+		if (ERROR_OK != retval)
 			return retval;
-		}
+		keep_alive();
 	}
 
 	return ERROR_OK;

[Openocd-svn] r1952 - in trunk/src: . jtag

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-31 00:23:12 +0200 (Sun, 31 May 2009)
New Revision: 1952

Modified:
   trunk/src/jtag/jtag.c
   trunk/src/jtag/jtag.h
   trunk/src/openocd.c
Log:
Encapsulate the global "jtag" jtag_interface pointer:
- Add jtag_interface_quit, factored from exit_handler() in openocd.c.
- Remove its extern declaration.
- Add static keyword to its definition.


Modified: trunk/src/jtag/jtag.c
===================================================================
--- trunk/src/jtag/jtag.c	2009-05-30 21:53:10 UTC (rev 1951)
+++ trunk/src/jtag/jtag.c	2009-05-30 22:23:12 UTC (rev 1952)
@@ -227,7 +227,7 @@
 	NULL,
 };
 
-jtag_interface_t *jtag = NULL;
+static jtag_interface_t *jtag = NULL;
 
 /* configuration */
 static jtag_interface_t *jtag_interface = NULL;
@@ -2407,6 +2407,20 @@
 	return ERROR_OK;
 }
 
+int jtag_interface_quit(void)
+{
+	if (!jtag || !jtag->quit)
+		return ERROR_OK;
+
+	// close the JTAG interface
+	int result = jtag->quit();
+	if (ERROR_OK != result)
+		LOG_ERROR("failed: %d", result);
+
+	return ERROR_OK;
+}
+
+
 int jtag_init_reset(struct command_context_s *cmd_ctx)
 {
 	int retval;

Modified: trunk/src/jtag/jtag.h
===================================================================
--- trunk/src/jtag/jtag.h	2009-05-30 21:53:10 UTC (rev 1951)
+++ trunk/src/jtag/jtag.h	2009-05-30 22:23:12 UTC (rev 1952)
@@ -512,8 +512,6 @@
 
 extern jtag_event_callback_t* jtag_event_callbacks;
 
-extern jtag_interface_t*      jtag; /* global pointer to configured JTAG interface */
-
 extern int jtag_speed;
 extern int jtag_speed_post_reset;
 
@@ -535,6 +533,9 @@
  */
 extern int  jtag_interface_init(struct command_context_s* cmd_ctx);
 
+/// Shutdown the JTAG interface upon program exit.
+extern int  jtag_interface_quit(void);
+
 /* initialize JTAG chain using only a RESET reset. If init fails,
  * try reset + init.
  */

Modified: trunk/src/openocd.c
===================================================================
--- trunk/src/openocd.c	2009-05-30 21:53:10 UTC (rev 1951)
+++ trunk/src/openocd.c	2009-05-30 22:23:12 UTC (rev 1952)
@@ -79,9 +79,7 @@
 
 static void exit_handler(void)
 {
-	/* close JTAG interface */
-	if (jtag && jtag->quit)
-		jtag->quit();
+	jtag_interface_quit();
 }
 
 static int log_target_callback_event_handler(struct target_s *target, enum target_event event, void *priv)

[Openocd-svn] r1951 - trunk/src/jtag

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-30 23:53:10 +0200 (Sat, 30 May 2009)
New Revision: 1951

Modified:
   trunk/src/jtag/jlink.c
Log:
Remove unused jlink_execute_end_state (unreferenced after r1949).

Modified: trunk/src/jtag/jlink.c
===================================================================
--- trunk/src/jtag/jlink.c	2009-05-30 11:55:14 UTC (rev 1950)
+++ trunk/src/jtag/jlink.c	2009-05-30 21:53:10 UTC (rev 1951)
@@ -150,14 +150,6 @@
 	.quit = jlink_quit
 };
 
-static void jlink_execute_end_state(jtag_command_t *cmd)
-{
-	DEBUG_JTAG_IO("end_state: %i", cmd->cmd.end_state->end_state);
-
-	if (cmd->cmd.end_state->end_state != TAP_INVALID)
-		jlink_end_state(cmd->cmd.end_state->end_state);
-}
-
 static void jlink_execute_runtest(jtag_command_t *cmd)
 {
 	DEBUG_JTAG_IO("runtest %i cycles, end in %i",

[Openocd-svn] r1950 - trunk/src/jtag

[<oh...@ma...>]

Author: oharboe
Date: 2009-05-30 13:55:14 +0200 (Sat, 30 May 2009)
New Revision: 1950

Modified:
   trunk/src/jtag/ft2232.c
   trunk/src/jtag/jtag.h
Log:
remove unused JTAG_END_STATE part 2

Modified: trunk/src/jtag/ft2232.c
===================================================================
--- trunk/src/jtag/ft2232.c	2009-05-30 11:37:21 UTC (rev 1949)
+++ trunk/src/jtag/ft2232.c	2009-05-30 11:55:14 UTC (rev 1950)
@@ -512,7 +512,6 @@
 	}
 }
 
-
 static void ft2232_read_scan(enum scan_type type, u8* buffer, int scan_size)
 {
 	int num_bytes = (scan_size + 7) / 8;
@@ -1412,20 +1411,6 @@
 	LOG_DEBUG("trst: %i, srst: %i, high_output: 0x%2.2x, high_direction: 0x%2.2x", trst, srst, high_output, high_direction);
 }
 
-static int ft2232_execute_end_state(jtag_command_t *cmd)
-{
-	int  retval;
-	retval = ERROR_OK;
-
-	DEBUG_JTAG_IO("execute_end_state: %s", tap_state_name(cmd->cmd.end_state->end_state) );
-
-	if (cmd->cmd.end_state->end_state != TAP_INVALID)
-		ft2232_end_state(cmd->cmd.end_state->end_state);
-
-	return retval;
-}
-
-
 static int ft2232_execute_runtest(jtag_command_t *cmd)
 {
 	int  retval;
@@ -1682,7 +1667,6 @@
 
 	switch (cmd->type)
 	{
-	case JTAG_END_STATE: 	retval = ft2232_execute_end_state(cmd); break;
 	case JTAG_RESET:	 		retval = ft2232_execute_reset(cmd); break;
 	case JTAG_RUNTEST:   	retval = ft2232_execute_runtest(cmd); break;
 	case JTAG_STATEMOVE: 	retval = ft2232_execute_statemove(cmd); break;

Modified: trunk/src/jtag/jtag.h
===================================================================
--- trunk/src/jtag/jtag.h	2009-05-30 11:37:21 UTC (rev 1949)
+++ trunk/src/jtag/jtag.h	2009-05-30 11:55:14 UTC (rev 1950)
@@ -348,7 +348,6 @@
 	JTAG_STATEMOVE    = 2,
 	JTAG_RUNTEST      = 3,
 	JTAG_RESET        = 4,
-	JTAG_END_STATE    = 5,
 	JTAG_PATHMOVE     = 6,
 	JTAG_SLEEP        = 7,
 	JTAG_STABLECLOCKS = 8

[Openocd-svn] r1949 - in trunk/src/jtag: . rlink

[<oh...@ma...>]

Author: oharboe
Date: 2009-05-30 13:37:21 +0200 (Sat, 30 May 2009)
New Revision: 1949

Modified:
   trunk/src/jtag/amt_jtagaccel.c
   trunk/src/jtag/arm-jtag-ew.c
   trunk/src/jtag/bitbang.c
   trunk/src/jtag/bitq.c
   trunk/src/jtag/gw16012.c
   trunk/src/jtag/jlink.c
   trunk/src/jtag/rlink/rlink.c
   trunk/src/jtag/usbprog.c
   trunk/src/jtag/vsllink.c
Log:
remove unused JTAG_END_STATE

Modified: trunk/src/jtag/amt_jtagaccel.c
===================================================================
--- trunk/src/jtag/amt_jtagaccel.c	2009-05-30 07:56:14 UTC (rev 1948)
+++ trunk/src/jtag/amt_jtagaccel.c	2009-05-30 11:37:21 UTC (rev 1949)
@@ -332,13 +332,6 @@
 	{
 		switch (cmd->type)
 		{
-			case JTAG_END_STATE:
-#ifdef _DEBUG_JTAG_IO_
-				LOG_DEBUG("end_state: %i", cmd->cmd.end_state->end_state);
-#endif
-				if (cmd->cmd.end_state->end_state != TAP_INVALID)
-					amt_jtagaccel_end_state(cmd->cmd.end_state->end_state);
-				break;
 			case JTAG_RESET:
 #ifdef _DEBUG_JTAG_IO_
 				LOG_DEBUG("reset trst: %i srst %i", cmd->cmd.reset->trst, cmd->cmd.reset->srst);

Modified: trunk/src/jtag/arm-jtag-ew.c
===================================================================
--- trunk/src/jtag/arm-jtag-ew.c	2009-05-30 07:56:14 UTC (rev 1948)
+++ trunk/src/jtag/arm-jtag-ew.c	2009-05-30 11:37:21 UTC (rev 1949)
@@ -133,15 +133,6 @@
 	{
 		switch (cmd->type)
 		{
-			case JTAG_END_STATE:
-				DEBUG_JTAG_IO("end_state: %i", cmd->cmd.end_state->end_state);
-
-				if (cmd->cmd.end_state->end_state != TAP_INVALID)
-				{
-					armjtagew_end_state(cmd->cmd.end_state->end_state);
-				}
-				break;
-
 			case JTAG_RUNTEST:
 				DEBUG_JTAG_IO( "runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, \
 					cmd->cmd.runtest->end_state);

Modified: trunk/src/jtag/bitbang.c
===================================================================
--- trunk/src/jtag/bitbang.c	2009-05-30 07:56:14 UTC (rev 1948)
+++ trunk/src/jtag/bitbang.c	2009-05-30 11:37:21 UTC (rev 1949)
@@ -253,13 +253,6 @@
 	{
 		switch (cmd->type)
 		{
-			case JTAG_END_STATE:
-#ifdef _DEBUG_JTAG_IO_
-				LOG_DEBUG("end_state: %s", tap_state_name(cmd->cmd.end_state->end_state) );
-#endif
-				if (cmd->cmd.end_state->end_state != TAP_INVALID)
-					bitbang_end_state(cmd->cmd.end_state->end_state);
-				break;
 			case JTAG_RESET:
 #ifdef _DEBUG_JTAG_IO_
 				LOG_DEBUG("reset trst: %i srst %i", cmd->cmd.reset->trst, cmd->cmd.reset->srst);

Modified: trunk/src/jtag/bitq.c
===================================================================
--- trunk/src/jtag/bitq.c	2009-05-30 07:56:14 UTC (rev 1948)
+++ trunk/src/jtag/bitq.c	2009-05-30 11:37:21 UTC (rev 1949)
@@ -296,13 +296,6 @@
 	{
 		switch (cmd->type)
 		{
-		case JTAG_END_STATE:
-#ifdef _DEBUG_JTAG_IO_
-			LOG_DEBUG("end_state: %i", cmd->cmd.end_state->end_state);
-#endif
-			bitq_end_state(cmd->cmd.end_state->end_state);
-			break;
-
 		case JTAG_RESET:
 #ifdef _DEBUG_JTAG_IO_
 			LOG_DEBUG("reset trst: %i srst %i", cmd->cmd.reset->trst, cmd->cmd.reset->srst);

Modified: trunk/src/jtag/gw16012.c
===================================================================
--- trunk/src/jtag/gw16012.c	2009-05-30 07:56:14 UTC (rev 1948)
+++ trunk/src/jtag/gw16012.c	2009-05-30 11:37:21 UTC (rev 1949)
@@ -354,13 +354,6 @@
 	{
 		switch (cmd->type)
 		{
-			case JTAG_END_STATE:
-#ifdef _DEBUG_JTAG_IO_
-				LOG_DEBUG("end_state: %i", cmd->cmd.end_state->end_state);
-#endif
-				if (cmd->cmd.end_state->end_state != TAP_INVALID)
-					gw16012_end_state(cmd->cmd.end_state->end_state);
-				break;
 			case JTAG_RESET:
 #ifdef _DEBUG_JTAG_IO_
 				LOG_DEBUG("reset trst: %i srst %i", cmd->cmd.reset->trst, cmd->cmd.reset->srst);

Modified: trunk/src/jtag/jlink.c
===================================================================
--- trunk/src/jtag/jlink.c	2009-05-30 07:56:14 UTC (rev 1948)
+++ trunk/src/jtag/jlink.c	2009-05-30 11:37:21 UTC (rev 1949)
@@ -234,7 +234,6 @@
 {
 	switch (cmd->type)
 	{
-	case JTAG_END_STATE: jlink_execute_end_state(cmd); break;
 	case JTAG_RUNTEST:   jlink_execute_runtest(cmd); break;
 	case JTAG_STATEMOVE: jlink_execute_statemove(cmd); break;
 	case JTAG_PATHMOVE:  jlink_execute_pathmove(cmd); break;

Modified: trunk/src/jtag/rlink/rlink.c
===================================================================
--- trunk/src/jtag/rlink/rlink.c	2009-05-30 07:56:14 UTC (rev 1948)
+++ trunk/src/jtag/rlink/rlink.c	2009-05-30 11:37:21 UTC (rev 1949)
@@ -1399,7 +1399,6 @@
 	{
 		switch (cmd->type)
 		{
-			case JTAG_END_STATE:
 			case JTAG_RUNTEST:
 			case JTAG_STATEMOVE:
 			case JTAG_PATHMOVE:
@@ -1415,13 +1414,6 @@
 
 		switch (cmd->type)
 		{
-			case JTAG_END_STATE:
-#ifdef _DEBUG_JTAG_IO_
-				LOG_DEBUG("end_state: %i", cmd->cmd.end_state->end_state);
-#endif
-				if (cmd->cmd.end_state->end_state != -1)
-					rlink_end_state(cmd->cmd.end_state->end_state);
-				break;
 			case JTAG_RESET:
 #ifdef _DEBUG_JTAG_IO_
 				LOG_DEBUG("reset trst: %i srst %i", cmd->cmd.reset->trst, cmd->cmd.reset->srst);

Modified: trunk/src/jtag/usbprog.c
===================================================================
--- trunk/src/jtag/usbprog.c	2009-05-30 07:56:14 UTC (rev 1948)
+++ trunk/src/jtag/usbprog.c	2009-05-30 11:37:21 UTC (rev 1949)
@@ -135,13 +135,6 @@
 	{
 		switch (cmd->type)
 		{
-			case JTAG_END_STATE:
-#ifdef _DEBUG_JTAG_IO_
-				LOG_DEBUG("end_state: %i", cmd->cmd.end_state->end_state);
-#endif
-				if (cmd->cmd.end_state->end_state != TAP_INVALID)
-					usbprog_end_state(cmd->cmd.end_state->end_state);
-				break;
 			case JTAG_RESET:
 #ifdef _DEBUG_JTAG_IO_
 				LOG_DEBUG("reset trst: %i srst %i", cmd->cmd.reset->trst, cmd->cmd.reset->srst);

Modified: trunk/src/jtag/vsllink.c
===================================================================
--- trunk/src/jtag/vsllink.c	2009-05-30 07:56:14 UTC (rev 1948)
+++ trunk/src/jtag/vsllink.c	2009-05-30 11:37:21 UTC (rev 1949)
@@ -296,15 +296,6 @@
 	{
 		switch (cmd->type)
 		{
-			case JTAG_END_STATE:
-				DEBUG_JTAG_IO("end_state: %s", tap_state_name(cmd->cmd.end_state->end_state));
-			
-				if (cmd->cmd.end_state->end_state != TAP_INVALID)
-				{
-					vsllink_end_state(cmd->cmd.end_state->end_state);
-				}
-				break;
-				
 			case JTAG_RUNTEST:
 				DEBUG_JTAG_IO( "runtest %i cycles, end in %s", cmd->cmd.runtest->num_cycles, \
 					tap_state_name(cmd->cmd.runtest->end_state));

[Openocd-svn] r1948 - trunk/doc

[<oh...@ma...>]

Author: oharboe
Date: 2009-05-30 09:56:14 +0200 (Sat, 30 May 2009)
New Revision: 1948

Modified:
   trunk/doc/openocd.texi
Log:
added some comments on meminfo command

Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-05-30 07:53:40 UTC (rev 1947)
+++ trunk/doc/openocd.texi	2009-05-30 07:56:14 UTC (rev 1948)
@@ -3488,7 +3488,9 @@
 @section Memory access commands
 @anchor{Memory access}
 @subsection meminfo
-display available RAM memory.
+display available RAM memory on OpenOCD host. Used in OpenOCD regression testing scripts. Mainly
+useful on embedded targets, PC type hosts have complimentary tools like Valgrind to address
+resource tracking problems.
 @subsection Memory peek/poke type commands
 These commands allow accesses of a specific size to the memory
 system. Often these are used to configure the current target in some

[Openocd-svn] r1947 - trunk/doc

[<oh...@ma...>]

Author: oharboe
Date: 2009-05-30 09:53:40 +0200 (Sat, 30 May 2009)
New Revision: 1947

Modified:
   trunk/doc/openocd.texi
Log:
more reset_config texts

Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-05-30 01:44:22 UTC (rev 1946)
+++ trunk/doc/openocd.texi	2009-05-30 07:53:40 UTC (rev 1947)
@@ -1699,8 +1699,21 @@
 
 @deffn {Command} reset_config mode_flag ...
 This command tells OpenOCD the reset configuration
-of your combination of JTAG interface, board, and target.
+of your combination of JTAG board and target in target
+configuration scripts.
 
+If you have an interface that does not support SRST and
+TRST(unlikely), then you may be able to work around that
+problem by using a reset_config command to override any
+settings in the target configuration script.
+
+SRST and TRST has a fairly well understood definition and
+behaviour in the JTAG specification, but vendors take
+liberties to achieve various more or less clearly understood
+goals. Sometimes documentation is available, other times it
+is not. OpenOCD has the reset_config command to allow OpenOCD
+to deal with the various common cases.
+
 The @var{mode_flag} options can be specified in any order, but only one
 of each type -- @var{signals}, @var{combination}, @var{trst_type},
 and @var{srst_type} -- may be specified at a time.

[Openocd-svn] r1946 - trunk/src/target

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-30 03:44:22 +0200 (Sat, 30 May 2009)
New Revision: 1946

Modified:
   trunk/src/target/oocd_trace.c
Log:
Remove trailing whitespace from oocd_trace source file.

Modified: trunk/src/target/oocd_trace.c
===================================================================
--- trunk/src/target/oocd_trace.c	2009-05-30 01:43:21 UTC (rev 1945)
+++ trunk/src/target/oocd_trace.c	2009-05-30 01:44:22 UTC (rev 1946)
@@ -48,7 +48,7 @@
 	}
 
 	LOG_DEBUG("reg #%i: 0x%8.8x\n", reg, *value);
-	
+
 	return ERROR_OK;
 }
 
@@ -92,7 +92,7 @@
 		else
 			bytes_to_read -= bytes_read;
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -101,7 +101,7 @@
 	u8 trash[256];
 	oocd_trace_t *oocd_trace = etm_ctx->capture_driver_priv;
 	size_t bytes_read;
-	
+
 	oocd_trace->tty_fd = open(oocd_trace->tty, O_RDWR | O_NOCTTY | O_NONBLOCK);
 
 	if(oocd_trace->tty_fd < 0)
@@ -114,32 +114,32 @@
 	tcflush(oocd_trace->tty_fd, TCOFLUSH);
 	tcflush(oocd_trace->tty_fd, TCIFLUSH);
 	fcntl(oocd_trace->tty_fd, F_SETFL, fcntl(oocd_trace->tty_fd, F_GETFL) & ~O_NONBLOCK);
-	
+
 	tcgetattr(oocd_trace->tty_fd, &oocd_trace->oldtio); /* save current port settings */
-	
+
 	bzero(&oocd_trace->newtio, sizeof(oocd_trace->newtio));
 	oocd_trace->newtio.c_cflag = CS8 | CLOCAL | CREAD | B2500000;
-	
+
 	oocd_trace->newtio.c_iflag = IGNPAR | IGNBRK | IXON | IXOFF;
 	oocd_trace->newtio.c_oflag = 0;
-	
+
 	/* set input mode (non-canonical, no echo,...) */
 	oocd_trace->newtio.c_lflag = 0;
-	
+
 	cfmakeraw(&oocd_trace->newtio);
 	oocd_trace->newtio.c_cc[VTIME] = 1;   /* inter-character timer used */
 	oocd_trace->newtio.c_cc[VMIN] = 0;   /* blocking read until 0 chars received */
-	
+
 	tcflush(oocd_trace->tty_fd, TCIFLUSH);
 	tcsetattr(oocd_trace->tty_fd, TCSANOW, &oocd_trace->newtio);
-	
+
 	/* occasionally one bogus character is left in the input buffer
 	 * read up any leftover characters to ensure communication is in sync */
 	while ((bytes_read = read(oocd_trace->tty_fd, trash, sizeof(trash))) > 0)
 	{
 		LOG_DEBUG("%zi bytes read\n", bytes_read);
 	};
-	
+
 	return ERROR_OK;
 }
 
@@ -147,9 +147,9 @@
 {
 	oocd_trace_t *oocd_trace = etm_ctx->capture_driver_priv;
 	u32 status;
-	
+
 	oocd_trace_read_reg(oocd_trace, OOCD_TRACE_STATUS, &status);
-	
+
 	/* if tracing is currently idle, return this information */
 	if (etm_ctx->capture_status == TRACE_IDLE)
 	{
@@ -160,18 +160,18 @@
 		/* check Full bit to identify an overflow */
 		if (status & 0x4)
 			etm_ctx->capture_status |= TRACE_OVERFLOWED;
-		
+
 		/* check Triggered bit to identify trigger condition */
 		if (status & 0x2)
 			etm_ctx->capture_status |= TRACE_TRIGGERED;
-		
+
 		if (status & 0x1)
 		{
 			etm_ctx->capture_status &= ~TRACE_RUNNING;
 			etm_ctx->capture_status |= TRACE_COMPLETED;
 		}
 	}
-	
+
 	return etm_ctx->capture_status;
 }
 
@@ -196,7 +196,7 @@
 	else
 		num_frames = address;
 
-	/* read data into temporary array for unpacking 
+	/* read data into temporary array for unpacking
 	 * one frame from OpenOCD+trace corresponds to 16 trace cycles
 	 */
 	trace_data = malloc(sizeof(u8) * num_frames * 16);
@@ -209,13 +209,13 @@
 
 	etm_ctx->trace_depth = num_frames * 16;
 	etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
-	
+
 	for (i = 0; i < num_frames * 16; i++)
 	{
 		etm_ctx->trace_data[i].pipestat = (trace_data[i] & 0x7);
 		etm_ctx->trace_data[i].packet = (trace_data[i] & 0x78) >> 3;
 		etm_ctx->trace_data[i].flags = 0;
-		
+
 		if ((trace_data[i] & 0x80) >> 7)
 		{
 			etm_ctx->trace_data[i].flags |= ETMV1_TRACESYNC_CYCLE;
@@ -227,7 +227,7 @@
 			etm_ctx->trace_data[i].flags |= ETMV1_TRIGGER_CYCLE;
 		}
 	}
-	
+
 	free(trace_data);
 
 	return ERROR_OK;
@@ -238,19 +238,19 @@
 	oocd_trace_t *oocd_trace = etm_ctx->capture_driver_priv;
 	u32 control = 0x1;	/* 0x1: enabled */
 	u32 trigger_count;
-	
+
 	if (((etm_ctx->portmode & ETM_PORT_MODE_MASK) != ETM_PORT_NORMAL)
 		|| ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_4BIT))
 	{
 		LOG_DEBUG("OpenOCD+trace only supports normal 4-bit ETM mode");
 		return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
 	}
-	
+
 	if ((etm_ctx->portmode & ETM_PORT_CLOCK_MASK) == ETM_PORT_HALF_CLOCK)
 	{
 		control |= 0x2;	/* half rate clock, capture at twice the clock rate */
 	}
-	
+
 	/* OpenOCD+trace holds up to 16 million samples,
 	 * but trigger counts is set in multiples of 16 */
 	trigger_count = (1048576 * etm_ctx->trigger_percent) / 100;
@@ -259,22 +259,22 @@
 	oocd_trace_write_reg(oocd_trace, OOCD_TRACE_ADDRESS, 0x0);
 	oocd_trace_write_reg(oocd_trace, OOCD_TRACE_TRIGGER_COUNTER, trigger_count);
 	oocd_trace_write_reg(oocd_trace, OOCD_TRACE_CONTROL, control);
-	
+
 	/* we're starting a new trace, initialize capture status */
 	etm_ctx->capture_status = TRACE_RUNNING;
-	
-	return ERROR_OK; 
+
+	return ERROR_OK;
 }
 
 static int oocd_trace_stop_capture(etm_context_t *etm_ctx)
 {
 	oocd_trace_t *oocd_trace = etm_ctx->capture_driver_priv;
 
-	/* trace stopped, just clear running flag, but preserve others */ 
+	/* trace stopped, just clear running flag, but preserve others */
 	etm_ctx->capture_status &= ~TRACE_RUNNING;
-	
+
 	oocd_trace_write_reg(oocd_trace, OOCD_TRACE_CONTROL, 0x0);
-	
+
 	return ERROR_OK;
 }
 
@@ -294,28 +294,28 @@
 	target_t *target;
 	armv4_5_common_t *armv4_5;
 	arm7_9_common_t *arm7_9;
-	
+
 	if (argc != 2)
 	{
 		LOG_ERROR("incomplete 'oocd_trace config <target> <tty>' command");
 		exit(-1);
 	}
-	
+
 	target = get_current_target(cmd_ctx);
-	
+
 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
 	{
 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
 		return ERROR_OK;
 	}
-	
+
 	if (arm7_9->etm_ctx)
 	{
 		oocd_trace_t *oocd_trace = malloc(sizeof(oocd_trace_t));
-		
+
 		arm7_9->etm_ctx->capture_driver_priv = oocd_trace;
 		oocd_trace->etm_ctx = arm7_9->etm_ctx;
-		
+
 		/* copy name of TTY device used to communicate with OpenOCD+trace */
 		oocd_trace->tty = strndup(args[1], 256);
 	}
@@ -334,36 +334,36 @@
 	arm7_9_common_t *arm7_9;
 	oocd_trace_t *oocd_trace;
 	u32 status;
-	
+
 	target = get_current_target(cmd_ctx);
-	
+
 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
 	{
 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
 		return ERROR_OK;
 	}
-	
+
 	if (!arm7_9->etm_ctx)
 	{
 		command_print(cmd_ctx, "current target doesn't have an ETM configured");
 		return ERROR_OK;
 	}
-	
+
 	if (strcmp(arm7_9->etm_ctx->capture_driver->name, "oocd_trace") != 0)
 	{
 		command_print(cmd_ctx, "current target's ETM capture driver isn't 'oocd_trace'");
 		return ERROR_OK;
 	}
-	
+
 	oocd_trace = (oocd_trace_t*)arm7_9->etm_ctx->capture_driver_priv;
-	
+
 	oocd_trace_read_reg(oocd_trace, OOCD_TRACE_STATUS, &status);
-	
+
 	if (status & 0x8)
 		command_print(cmd_ctx, "trace clock locked");
 	else
 		command_print(cmd_ctx, "no trace clock");
-		
+
 	return ERROR_OK;
 }
 
@@ -375,33 +375,33 @@
 	oocd_trace_t *oocd_trace;
 	size_t bytes_written;
 	u8 cmd_array[1];
-	
+
 	target = get_current_target(cmd_ctx);
-	
+
 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
 	{
 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
 		return ERROR_OK;
 	}
-	
+
 	if (!arm7_9->etm_ctx)
 	{
 		command_print(cmd_ctx, "current target doesn't have an ETM configured");
 		return ERROR_OK;
 	}
-	
+
 	if (strcmp(arm7_9->etm_ctx->capture_driver->name, "oocd_trace") != 0)
 	{
 		command_print(cmd_ctx, "current target's ETM capture driver isn't 'oocd_trace'");
 		return ERROR_OK;
 	}
-	
+
 	oocd_trace = (oocd_trace_t*)arm7_9->etm_ctx->capture_driver_priv;
-	
+
 	cmd_array[0] = 0xf0;
 
 	bytes_written = write(oocd_trace->tty_fd, cmd_array, 1);
-	
+
 	command_print(cmd_ctx, "requesting traceclock resync");
 	LOG_DEBUG("resyncing traceclk pll");
 
@@ -411,9 +411,9 @@
 int oocd_trace_register_commands(struct command_context_s *cmd_ctx)
 {
 	command_t *oocd_trace_cmd;
-	
+
 	oocd_trace_cmd = register_command(cmd_ctx, NULL, "oocd_trace", NULL, COMMAND_ANY, "OpenOCD+trace");
-	
+
 	register_command(cmd_ctx, oocd_trace_cmd, "config", handle_oocd_trace_config_command, COMMAND_CONFIG, NULL);
 
 	register_command(cmd_ctx, oocd_trace_cmd, "status", handle_oocd_trace_status_command, COMMAND_EXEC, "display OpenOCD+trace status");

[Openocd-svn] r1945 - in trunk: doc src/target

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-30 03:43:21 +0200 (Sat, 30 May 2009)
New Revision: 1945

Modified:
   trunk/doc/openocd.texi
   trunk/src/target/etm.c
   trunk/src/target/oocd_trace.c
Log:
David Brownell <da...@pa...>:

Provide basic documentation on the ARM ETM and ETB trace commands.

Fix minor goofs in registration of the ETM commands; and whitespace
issues in the proof-of-concept oocd_trace code.  (Plus include a
ref to Dominic's email saying that it's just proof-of-concept code.)

Note that I'm still not sure whether the ETM support works.  But
documenting how it's expected to work should help sort out which
behaviors are bugs, which will help get bugs patched.

ZW: whitespace changes were split out of this patch but will follow.


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-05-30 01:32:19 UTC (rev 1944)
+++ trunk/doc/openocd.texi	2009-05-30 01:43:21 UTC (rev 1945)
@@ -1094,17 +1094,11 @@
 examination of the instruction and data bus activity.  Trace
 activity is controlled through an ``Embedded Trace Module'' (ETM)
 on one of the core's scan chains.  The ETM emits voluminous data
-through a ``trace port''.  The trace port is accessed in one
-of two ways.  When its signals are pinned out from the chip,
-boards may provide a special high speed debugging connector;
-software support for this is not configured by default, use
-the ``--enable-oocd_trace'' option.  Alternatively, trace data
-may be stored an on-chip SRAM which is packaged as an ``Embedded
-Trace Buffer'' (ETB).  An ETB has its own TAP, usually right after
-its associated ARM core.  OpenOCD supports the ETM, and your
-target configuration should set it up with the relevant trace
-port:  ``etb'' for chips which use that, else the board-specific
-option will be either ``oocd_trace'' or ``dummy''.
+through a ``trace port''.  (@xref{ARM Tracing}.)
+If you are using an external trace port,
+configure it in your board config file.
+If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
+configure it in your target config file.
 
 @example
 etm config $_TARGETNAME 16 normal full etb
@@ -3586,6 +3580,181 @@
 Some of those operations don't fit well in that framework, so they are
 exposed here using architecture or implementation specific commands.
 
+@anchor{ARM Tracing}
+@subsection ARM Tracing
+@cindex ETM
+@cindex ETB
+
+CPUs based on ARM cores may include standard tracing interfaces,
+based on an ``Embedded Trace Module'' (ETM) which sends voluminous
+address and data bus trace records to a ``Trace Port''.
+
+@itemize
+@item
+Development-oriented boards will sometimes provide a high speed
+trace connector for collecting that data, when the particular CPU
+supports such an interface.
+(The standard connector is a 38-pin Mictor, with both JTAG
+and trace port support.)
+Those trace connectors are supported by higher end JTAG adapters
+and some logic analyzer modules; frequently those modules can
+buffer several megabytes of trace data.
+Configuring an ETM coupled to such an external trace port belongs
+in the board-specific configuration file.
+@item
+If the CPU doesn't provide an external interface, it probably
+has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
+dedicated SRAM.  4KBytes is one common ETB size.
+Configuring an ETM coupled only to an ETB belongs in the CPU-specific
+(target) configuration file, since it works the same on all boards.
+@end itemize
+
+ETM support in OpenOCD doesn't seem to be widely used yet.
+
+@quotation Issues
+ETM support may be buggy, and at least some @command{etm config}
+parameters should be detected by asking the ETM for them.
+It seems like a GDB hookup should be possible,
+as well as triggering trace on specific events
+(perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
+There should be GUI tools to manipulate saved trace data and help
+analyse it in conjunction with the source code.
+It's unclear how much of a common interface is shared
+with the current XScale trace support, or should be
+shared with eventual Nexus-style trace module support.
+@end quotation
+
+@subsubsection ETM Configuration
+ETM setup is coupled with the trace port driver configuration.
+
+@deffn {Config Command} {etm config} target width mode clocking driver
+Declares the ETM associated with @var{target}, and associates it
+with a given trace port @var{driver}.  @xref{Trace Port Drivers}.
+
+Several of the parameters must reflect the trace port configuration.
+The @var{width} must be either 4, 8, or 16.
+The @var{mode} must be @option{normal}, @option{multiplexted},
+or @option{demultiplexted}.
+The @var{clocking} must be @option{half} or @option{full}.
+
+@quotation Note
+You can see the ETM registers using the @command{reg} command, although
+not all of those possible registers are present in every ETM.
+@end quotation
+@end deffn
+
+@deffn Command {etm info}
+Displays information about the current target's ETM.
+@end deffn
+
+@deffn Command {etm status}
+Displays status of the current target's ETM:
+is the ETM idle, or is it collecting data?
+Did trace data overflow?
+Was it triggered?
+@end deffn
+
+@deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
+Displays what data that ETM will collect.
+If arguments are provided, first configures that data.
+When the configuration changes, tracing is stopped
+and any buffered trace data is invalidated.
+
+@itemize
+@item @var{type} ... one of
+@option{none} (save nothing),
+@option{data} (save data),
+@option{address} (save addresses),
+@option{all} (save data and addresses)
+@item @var{context_id_bits} ... 0, 8, 16, or 32
+@item @var{cycle_accurate} ...  @option{enable} or @option{disable}
+@item @var{branch_output} ...  @option{enable} or @option{disable}
+@end itemize
+@end deffn
+
+@deffn Command {etm trigger_percent} percent
+@emph{Buggy and effectively a NOP ... @var{percent} from 2..100}
+@end deffn
+
+@subsubsection ETM Trace Operation
+
+After setting up the ETM, you can use it to collect data.
+That data can be exported to files for later analysis.
+It can also be parsed with OpenOCD, for basic sanity checking.
+
+@deffn Command {etm analyze}
+Reads trace data into memory, if it wasn't already present.
+Decodes and prints the data that was collected.
+@end deffn
+
+@deffn Command {etm dump} filename
+Stores the captured trace data in @file{filename}.
+@end deffn
+
+@deffn Command {etm image} filename [base_address] [type]
+Opens an image file.
+@end deffn
+
+@deffn Command {etm load} filename
+Loads captured trace data from @file{filename}.
+@end deffn
+
+@deffn Command {etm start}
+Starts trace data collection.
+@end deffn
+
+@deffn Command {etm stop}
+Stops trace data collection.
+@end deffn
+
+@anchor{Trace Port Drivers}
+@subsubsection Trace Port Drivers
+
+To use an ETM trace port it must be associated with a driver.
+
+@deffn {Trace Port Driver} etb
+Use the @option{etb} driver if you are configuring an ETM
+to use on-chip ETB memory.
+@deffn {Config Command} {etb config} target etb_tap
+Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
+You can see the ETB registers using the @command{reg} command.
+@end deffn
+@end deffn
+
+@deffn {Trace Port Driver} etm_dummy
+Use the @option{etm_dummy} driver if you are configuring an ETM that's
+not connected to anything (on-chip ETB or off-chip trace connector).
+@emph{This driver lets OpenOCD talk to the ETM, but it does not expose
+any trace data collection.}
+@deffn {Config Command} {etm_dummy config} target
+Associates the ETM for @var{target} with a dummy driver.
+@end deffn
+@end deffn
+
+@deffn {Trace Port Driver} oocd_trace
+This driver isn't available unless OpenOCD was explicitly configured
+with the @option{--enable-oocd_trace} option.  You probably don't want
+to configure it unless you've built the appropriate prototype hardware;
+it's @emph{proof-of-concept} software.
+
+Use the @option{oocd_trace} driver if you are configuring an ETM that's
+connected to an off-chip trace connector.
+
+@deffn {Config Command} {oocd_trace config} target tty
+Associates the ETM for @var{target} with a trace driver which
+collects data through the serial port @var{tty}.
+@end deffn
+
+@deffn Command {oocd_trace resync}
+Re-synchronizes with the capture clock.
+@end deffn
+
+@deffn Command {oocd_trace status}
+Reports whether the capture clock is locked or not.
+@end deffn
+@end deffn
+
+
 @subsection ARMv4 and ARMv5 Architecture
 @cindex ARMv4 specific commands
 @cindex ARMv5 specific commands

Modified: trunk/src/target/etm.c
===================================================================
--- trunk/src/target/etm.c	2009-05-30 01:32:19 UTC (rev 1944)
+++ trunk/src/target/etm.c	2009-05-30 01:43:21 UTC (rev 1945)
@@ -1815,7 +1815,8 @@
 {
 	etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
 
-	register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command, COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
+	register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
+		COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
 
 	return ERROR_OK;
 }
@@ -1823,12 +1824,13 @@
 int etm_register_user_commands(struct command_context_s *cmd_ctx)
 {
 	register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
-		COMMAND_EXEC, "configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output");
+		COMMAND_EXEC, "configure trace mode <none|data|address|all> "
+			"<context_id_bits> <cycle_accurate> <branch_output>");
 
 	register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
 		COMMAND_EXEC, "display info about the current target's ETM");
 
-	register_command(cmd_ctx, etm_cmd, "trigger_percent <percent>", handle_etm_trigger_percent_command,
+	register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
 		COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
 	register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
 		COMMAND_EXEC, "display current target's ETM status");

Modified: trunk/src/target/oocd_trace.c
===================================================================
--- trunk/src/target/oocd_trace.c	2009-05-30 01:32:19 UTC (rev 1944)
+++ trunk/src/target/oocd_trace.c	2009-05-30 01:43:21 UTC (rev 1945)
@@ -24,7 +24,12 @@
 #include "oocd_trace.h"
 #include "arm7_9_common.h"
 
+/*
+ * This is "proof of concept" code, for prototype hardware:
+ * https://lists.berlios.de/pipermail/openocd-development/2007-September/000336.html
+ */
 
+
 static int oocd_trace_register_commands(struct command_context_s *cmd_ctx);
 
 static int oocd_trace_read_reg(oocd_trace_t *oocd_trace, int reg, u32 *value)

[Openocd-svn] r1944 - in trunk: doc src/jtag

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-30 03:32:19 +0200 (Sat, 30 May 2009)
New Revision: 1944

Modified:
   trunk/doc/openocd.texi
   trunk/src/jtag/jtag.c
Log:
David Brownell <da...@pa...>:

Make it so the magic "reset_config" keywords can be provided in any
order.  This eliminates needless error paths, and makes it easier
to define things at the right level (adapter, board, target).
It also includes two other behavioral changes:

  (1)	When "handle_reset_config" sees a parameter error, it
  	exits without changing anything.   This is best viewed
	as a bugfix.  (Old behavior:  restore defaults, even if
	they weren't previously active.)

  (2)	Only the behaviors that were explicitly specified get
  	changed.  (Old behavior:  everything else gets reset to
	the "default".)  So for example you can now specify SRST
	drive requirements without saying anything about the
	three unrelated topics you previously had to specify.

That second one might cause confusion for any configs that end
up calling "reset_config" twice, so it will deserve to be called
out in the release notes.  (There were no such configurations in
the current OpenOCD source tree.)

Update docs accordingly.  Note that at least some versions of
the texi-to-html tools can't handle "@xref{with spaces}", but
those work properly in PDF and in the info files.


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-05-29 05:50:01 UTC (rev 1943)
+++ trunk/doc/openocd.texi	2009-05-30 01:32:19 UTC (rev 1944)
@@ -1574,9 +1574,13 @@
 
 Every system configuration may require a different reset
 configuration. This can also be quite confusing.
+Resets also interact with @var{reset-init} event handlers,
+which do things like setting up clocks and DRAM, and
+JTAG clock rates.  (@xref{JTAG Speed}.)
 Please see the various board files for examples.
 
-@b{Note} to maintainers and integrators:
+@quotation Note
+To maintainers and integrators:
 Reset configuration touches several things at once.
 Normally the board configuration file
 should define it and assume that the JTAG adapter supports
@@ -1587,6 +1591,7 @@
 And when the JTAG adapter doesn't support everything, the
 system configuration file will need to override parts of
 the reset configuration provided by other files.
+@end quotation
 
 @section Types of Reset
 
@@ -1671,12 +1676,19 @@
 
 There can also be other issues.
 Some devices don't fully conform to the JTAG specifications.
-Others have chip-specific extensions like extra steps needed
-during TAP reset, or a requirement to use the normally-optional TRST
-signal.
 Trivial system-specific differences are common, such as
 SRST and TRST using slightly different names.
+There are also vendors who distribute key JTAG documentation for
+their chips only to developers who have signed a Non-Disclosure
+Agreement (NDA).
 
+Sometimes there are chip-specific extensions like a requirement to use
+the normally-optional TRST signal (precluding use of JTAG adapters which
+don't pass TRST through), or needing extra steps to complete a TAP reset.
+
+In short, SRST and especially TRST handling may be very finicky,
+needing to cope with both architecture and board specific constraints.
+
 @section Commands for Handling Resets
 
 @deffn {Command} jtag_nsrst_delay milliseconds
@@ -1691,31 +1703,58 @@
 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
 @end deffn
 
-@deffn {Command} reset_config signals [combination [trst_type [srst_type]]]
+@deffn {Command} reset_config mode_flag ...
 This command tells OpenOCD the reset configuration
 of your combination of JTAG interface, board, and target.
-If the JTAG interface provides SRST, but the board doesn't connect
-that signal properly, then OpenOCD can't use it. @var{signals} can
-be @option{none}, @option{trst_only}, @option{srst_only} or
-@option{trst_and_srst}.
 
+The @var{mode_flag} options can be specified in any order, but only one
+of each type -- @var{signals}, @var{combination}, @var{trst_type},
+and @var{srst_type} -- may be specified at a time.
+If you don't provide a new value for a given type, its previous
+value (perhaps the default) is unchanged.
+For example, this means that you don't need to say anything at all about
+TRST just to declare that if the JTAG adapter should want to drive SRST,
+it must explicitly be driven high (@option{srst_push_pull}).
+
+@var{signals} can specify which of the reset signals are connected.
+For example, If the JTAG interface provides SRST, but the board doesn't
+connect that signal properly, then OpenOCD can't use it.
+Possible values are @option{none} (the default), @option{trst_only},
+@option{srst_only} and @option{trst_and_srst}.
+
+@quotation Tip
+If your board provides SRST or TRST through the JTAG connector,
+you must declare that or else those signals will not be used.
+@end quotation
+
 The @var{combination} is an optional value specifying broken reset
-signal implementations.  @option{srst_pulls_trst} states that the
+signal implementations.
+The default behaviour if no option given is @option{separate},
+indicating everything behaves normally.
+@option{srst_pulls_trst} states that the
 test logic is reset together with the reset of the system (e.g. Philips
 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
 the system is reset together with the test logic (only hypothetical, I
 haven't seen hardware with such a bug, and can be worked around).
 @option{combined} implies both @option{srst_pulls_trst} and
-@option{trst_pulls_srst}.  The default behaviour if no option given is
-@option{separate}.
+@option{trst_pulls_srst}.
 
 The optional @var{trst_type} and @var{srst_type} parameters allow the
-driver type of the reset lines to be specified. Possible values are
-@option{trst_push_pull} (default) and @option{trst_open_drain} for the
-test reset signal, and @option{srst_open_drain} (default) and
-@option{srst_push_pull} for the system reset. These values only affect
-JTAG interfaces with support for different drivers, like the Amontec
-JTAGkey and JTAGAccelerator.
+driver mode of each reset line to be specified.  These values only affect
+JTAG interfaces with support for different driver modes, like the Amontec
+JTAGkey and JTAGAccelerator.  Also, they are necessarily ignored if the
+relevant signal (TRST or SRST) is not connected.
+
+Possible @var{trst_type} driver modes for the test reset signal (TRST)
+are @option{trst_push_pull} (default) and @option{trst_open_drain}.
+Most boards connect this signal to a pulldown, so the JTAG TAPs
+never leave reset unless they are hooked up to a JTAG adapter.
+
+Possible @var{srst_type} driver modes for the system reset signal (SRST)
+are the default @option{srst_open_drain}, and @option{srst_push_pull}.
+Most boards connect this signal to a pullup, and allow the
+signal to be pulled low by various events including system
+powerup and pressing a reset button.
 @end deffn
 
 

Modified: trunk/src/jtag/jtag.c
===================================================================
--- trunk/src/jtag/jtag.c	2009-05-29 05:50:01 UTC (rev 1943)
+++ trunk/src/jtag/jtag.c	2009-05-30 01:32:19 UTC (rev 1944)
@@ -2651,77 +2651,111 @@
 
 static int handle_reset_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
+	int new_cfg = 0;
+	int mask = 0;
+
 	if (argc < 1)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	if (argc >= 1)
-	{
-		if (strcmp(args[0], "none") == 0)
-			jtag_reset_config = RESET_NONE;
-		else if (strcmp(args[0], "trst_only") == 0)
-			jtag_reset_config = RESET_HAS_TRST;
-		else if (strcmp(args[0], "srst_only") == 0)
-			jtag_reset_config = RESET_HAS_SRST;
-		else if (strcmp(args[0], "trst_and_srst") == 0)
-			jtag_reset_config = RESET_TRST_AND_SRST;
+	/* Original versions cared about the order of these tokens:
+	 *   reset_config signals [combination [trst_type [srst_type]]]
+	 * They also clobbered the previous configuration even on error.
+	 *
+	 * Here we don't care about the order, and only change values
+	 * which have been explicitly specified.
+	 */
+	for (; argc; argc--, args++) {
+		int tmp = 0;
+		int m;
+
+		/* signals */
+		m = RESET_HAS_TRST | RESET_HAS_SRST;
+		if (strcmp(*args, "none") == 0)
+			tmp = RESET_NONE;
+		else if (strcmp(*args, "trst_only") == 0)
+			tmp = RESET_HAS_TRST;
+		else if (strcmp(*args, "srst_only") == 0)
+			tmp = RESET_HAS_SRST;
+		else if (strcmp(*args, "trst_and_srst") == 0)
+			tmp = RESET_HAS_TRST | RESET_HAS_SRST;
 		else
-		{
-			LOG_ERROR("(1) invalid reset_config argument (%s), defaulting to none", args[0]);
-			jtag_reset_config = RESET_NONE;
+			m = 0;
+		if (mask & m) {
+			LOG_ERROR("extra reset_config %s spec (%s)",
+					"signal", *args);
 			return ERROR_INVALID_ARGUMENTS;
 		}
-	}
+		if (m)
+			goto next;
 
-	if (argc >= 2)
-	{
-		if (strcmp(args[1], "separate") == 0)
-		{
-			/* seperate reset lines - default */
-		} else
-		{
-			if (strcmp(args[1], "srst_pulls_trst") == 0)
-				jtag_reset_config |= RESET_SRST_PULLS_TRST;
-			else if (strcmp(args[1], "trst_pulls_srst") == 0)
-				jtag_reset_config |= RESET_TRST_PULLS_SRST;
-			else if (strcmp(args[1], "combined") == 0)
-				jtag_reset_config |= RESET_SRST_PULLS_TRST | RESET_TRST_PULLS_SRST;
-			else
-			{
-				LOG_ERROR("(2) invalid reset_config argument (%s), defaulting to none", args[1]);
-				jtag_reset_config = RESET_NONE;
-				return ERROR_INVALID_ARGUMENTS;
-			}
+		/* combination (options for broken wiring) */
+		m = RESET_SRST_PULLS_TRST | RESET_TRST_PULLS_SRST;
+		if (strcmp(*args, "separate") == 0)
+			/* separate reset lines - default */;
+		else if (strcmp(*args, "srst_pulls_trst") == 0)
+			tmp |= RESET_SRST_PULLS_TRST;
+		else if (strcmp(*args, "trst_pulls_srst") == 0)
+			tmp |= RESET_TRST_PULLS_SRST;
+		else if (strcmp(*args, "combined") == 0)
+			tmp |= RESET_SRST_PULLS_TRST | RESET_TRST_PULLS_SRST;
+		else
+			m = 0;
+		if (mask & m) {
+			LOG_ERROR("extra reset_config %s spec (%s)",
+					"combination", *args);
+			return ERROR_INVALID_ARGUMENTS;
 		}
-	}
+		if (m)
+			goto next;
 
-	if (argc >= 3)
-	{
-		if (strcmp(args[2], "trst_open_drain") == 0)
-			jtag_reset_config |= RESET_TRST_OPEN_DRAIN;
-		else if (strcmp(args[2], "trst_push_pull") == 0)
-			jtag_reset_config &= ~RESET_TRST_OPEN_DRAIN;
+		/* trst_type (NOP without HAS_TRST) */
+		m = RESET_TRST_OPEN_DRAIN;
+		if (strcmp(*args, "trst_open_drain") == 0)
+			tmp |= RESET_TRST_OPEN_DRAIN;
+		else if (strcmp(*args, "trst_push_pull") == 0)
+			/* push/pull from adapter - default */;
 		else
-		{
-			LOG_ERROR("(3) invalid reset_config argument (%s) defaulting to none", args[2] );
-			jtag_reset_config = RESET_NONE;
+			m = 0;
+		if (mask & m) {
+			LOG_ERROR("extra reset_config %s spec (%s)",
+					"trst_type", *args);
 			return ERROR_INVALID_ARGUMENTS;
 		}
-	}
+		if (m)
+			goto next;
 
-	if (argc >= 4)
-	{
-		if (strcmp(args[3], "srst_push_pull") == 0)
-			jtag_reset_config |= RESET_SRST_PUSH_PULL;
-		else if (strcmp(args[3], "srst_open_drain") == 0)
-			jtag_reset_config &= ~RESET_SRST_PUSH_PULL;
+		/* srst_type (NOP without HAS_SRST) */
+		m |= RESET_SRST_PUSH_PULL;
+		if (strcmp(*args, "srst_push_pull") == 0)
+			tmp |= RESET_SRST_PUSH_PULL;
+		else if (strcmp(*args, "srst_open_drain") == 0)
+			/* open drain from adapter - default */;
 		else
-		{
-			LOG_ERROR("(4) invalid reset_config argument (%s), defaulting to none", args[3]);
-			jtag_reset_config = RESET_NONE;
+			m = 0;
+		if (mask & m) {
+			LOG_ERROR("extra reset_config %s spec (%s)",
+					"srst_type", *args);
 			return ERROR_INVALID_ARGUMENTS;
 		}
+		if (m)
+			goto next;
+
+		/* caller provided nonsense; fail */
+		LOG_ERROR("unknown reset_config flag (%s)", *args);
+		return ERROR_INVALID_ARGUMENTS;
+
+next:
+		/* Remember the bits which were specified (mask)
+		 * and their new values (new_cfg).
+		 */
+		mask |= m;
+		new_cfg |= tmp;
 	}
 
+	/* clear previous values of those bits, save new values */
+	jtag_reset_config &= ~mask;
+	jtag_reset_config |= new_cfg;
+
 	return ERROR_OK;
 }
 

[Openocd-svn] r1943 - trunk/src/jtag

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-29 07:50:01 +0200 (Fri, 29 May 2009)
New Revision: 1943

Modified:
   trunk/src/jtag/jtag.h
Log:
Remove error_handler_t type definition; it was unused in the tree.

Modified: trunk/src/jtag/jtag.h
===================================================================
--- trunk/src/jtag/jtag.h	2009-05-29 04:00:51 UTC (rev 1942)
+++ trunk/src/jtag/jtag.h	2009-05-29 05:50:01 UTC (rev 1943)
@@ -258,8 +258,6 @@
 extern tap_state_t cmd_queue_end_state;         /* finish DR scans in dr_end_state */
 extern tap_state_t cmd_queue_cur_state;         /* current TAP state */
 
-typedef void* error_handler_t;  /* Later on we can delete error_handler_t, but keep it for now to make patches more readable */
-
 struct scan_field_s;
 typedef int (*in_handler_t)(u8* in_value, void* priv, struct scan_field_s* field);
 

[Openocd-svn] r1942 - trunk/src/flash

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-29 06:00:51 +0200 (Fri, 29 May 2009)
New Revision: 1942

Modified:
   trunk/src/flash/flash.h
Log:
Add documentation to flash.h:
- provides low-level information about each flash API interface,
- gives driver authors some documentation about the driver interface,
- updated extensively from the original patch provided by Duane Ellis.


Modified: trunk/src/flash/flash.h
===================================================================
--- trunk/src/flash/flash.h	2009-05-29 01:33:04 UTC (rev 1941)
+++ trunk/src/flash/flash.h	2009-05-29 04:00:51 UTC (rev 1942)
@@ -33,65 +33,298 @@
 
 #define FLASH_MAX_ERROR_STR	(128)
 
+/**
+ * Describes the geometry and status of a single flash sector
+ * within a flash bank.  A single bank typically consists of multiple
+ * sectors, each of which can be erased and protected independently.
+ */
 typedef struct flash_sector_s
 {
+	/// Bus offset from start of the flash chip (in bytes).
 	u32 offset;
+	/// Number of bytes in this flash sector.
 	u32 size;
+	/**
+	 * Indication of erasure status: 0=not erased, 1=erased,
+	 * other=unknown.  Set by @c flash_driver_s::erase_check.
+	 */
 	int is_erased;
+	/**
+	 * Indication of protection status: 0=unprotected/unlocked,
+	 * 1=protected/locked, other=unknown.  Set by
+	 * @c flash_driver_s::protect_check.
+	 */
 	int is_protected;
 } flash_sector_t;
 
 struct flash_bank_s;
 
+/**
+ * @brief Provides the implementation-independent structure that defines
+ * all of the callbacks required by OpenOCD flash drivers.
+ *
+ * Driver authors must implement the routines defined here, providing an
+ * instance with the fields filled out.  After that, the instance must
+ * be registered in flash.c, so it can be used by the driver lookup system.
+ *
+ * Specifically, the user can issue the command: @par
+ * @code
+ * flash bank DRIVERNAME ...parameters...
+ * @endcode
+ *
+ * OpenOCD will search for the driver with a @c flash_driver_s::name
+ * that matches @c DRIVERNAME.
+ *
+ * The flash subsystem calls some of the other drivers routines a using
+ * corresponding static <code>flash_driver_<i>callback</i>()</code>
+ * routine in flash.c.
+ */
 typedef struct flash_driver_s
 {
+	/** 
+	 * Gives a human-readable name of this flash driver,
+	 * This field is used to select and initialize the driver.
+	 */
 	char *name;
+
+	/** 
+	 * Registers driver-specific commands.  When called (during the
+	 * "flash bank" command), the driver may register addition
+	 * commands to support new flash chip functions.
+	 *
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
 	int (*register_commands)(struct command_context_s *cmd_ctx);
+
+	/** 
+	 * Finish the "flash bank" command for @a bank.  The
+	 * @a bank parameter will have been filled in by the core flash
+	 * layer when this routine is called, and the driver can store
+	 * additional information in its flash_bank_t::driver_priv field.
+	 * 
+	 * @param cmd_ctx - the command context
+	 * @param cmd     - the command, in this case 'flash'
+	 * @param args    - parameters, see below
+	 * @param argc    - number of parameters on command line
+	 * @param bank    - new filled in flash bank.
+	 *
+	 * The args are: @par
+	 * @code
+	 * args[0] = bank
+	 * args[1] = drivername {name above}
+	 * args[2] = baseaddress 
+	 * args[3] = lengthbytes
+	 * args[4] = chip_width_in bytes
+	 * args[5] = bus_width_bytes
+	 * args[6] = driver-specific parameters
+	 * @endcode
+	 *
+	 * For example, args[4] = 16 bit flash, args[5] = 32bit bus.
+	 *
+	 * If extra arguments are provided (@a argc > 6), they will
+	 * start in @a args[6].  These can be used to implement
+	 * driver-specific extensions.
+	 *
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
 	int (*flash_bank_command)(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
 
-	/* use flash_driver_erase() wrapper to invoke */
+	/** 
+	 * Bank/sector erase routine (target-specific).  When
+	 * called, the flash driver should erase the specified sectors
+	 * using whatever means are at its disposal.
+	 *
+	 * @param bank The bank of flash to be erased.
+	 * @param first The number of the first sector to erase, typically 0.
+	 * @param last The number of the last sector to erase, typically N-1.
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
 	int (*erase)(struct flash_bank_s *bank, int first, int last);
 
-	/* use flash_driver_protect() wrapper to invoke */
+	/** 
+	 * Bank/sector protection routine (target-specific).
+	 * When called, the driver should disable 'flash write' bits (or
+	 * enable 'erase protection' bits) for the given @a bank and @a
+	 * sectors.
+	 *
+	 * @param bank The bank to protect or unprotect.
+	 * @param set If non-zero, enable protection; if 0, disable it.
+	 * @param first The first sector to (un)protect, typicaly 0.
+	 * @param last The last sector to (un)project, typically N-1.
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
 	int (*protect)(struct flash_bank_s *bank, int set, int first, int last);
 
-	/* use the flash_driver_write() wrapper to invoke. */
+	/** 
+	 * Program data into the flash.  Note CPU address will be
+	 * "bank->base + offset", while the physical address is
+	 * dependent upon current target MMU mappings.
+	 *
+	 * @param bank The bank to program
+	 * @param buffer The data bytes to write.
+	 * @param offset The offset into the chip to program.
+	 * @param count The number of bytes to write.
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
 	int (*write)(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
 
+	/** 
+	 * Probe to determine what kind of flash is present.
+	 * This is invoked by the "probe" script command.
+	 *
+	 * @param bank The bank to probe
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
 	int (*probe)(struct flash_bank_s *bank);
+	
+	/** 
+	 * Check the erasure status of a flash bank.
+	 * When called, the driver routine must perform the required
+	 * checks and then set the @c flash_sector_s::is_erased field
+	 * for each of the flash banks's sectors.
+	 *
+	 * @param bank The bank to check
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
 	int (*erase_check)(struct flash_bank_s *bank);
+
+	/**
+	 * Determine if the specific bank is "protected" or not.
+	 * When called, the driver routine must must perform the
+	 * required protection check(s) and then set the @c
+	 * flash_sector_s::is_protected field for each of the flash
+	 * bank's sectors.
+	 *
+	 * @param bank - the bank to check
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
 	int (*protect_check)(struct flash_bank_s *bank);
+
+	/**
+	 * Display human-readable information about the flash
+	 * bank into the given buffer.  Drivers must be careful to avoid
+	 * overflowing the buffer.
+	 *
+	 * @param bank - the bank to get info about
+	 * @param char - where to put the text for the human to read
+	 * @param buf_size - the size of the human buffer.
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */ 
 	int (*info)(struct flash_bank_s *bank, char *buf, int buf_size);
+
+	/**
+	 * A more gentle flavor of filash_driver_s::probe, performing
+	 * setup with less noise.  Generally, driver routines should test
+	 * to seee if the bank has already been probed; if it has, the
+	 * driver probably should not perform its probe a second time.
+	 *
+	 * This callback is often called from the inside of other
+	 * routines (e.g. GDB flash downloads) to autoprobe the flash as
+	 * it is programing the flash.
+	 *
+	 * @param bank - the bank to probe
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
 	int (*auto_probe)(struct flash_bank_s *bank);
 } flash_driver_t;
 
+/** 
+ * Provides details of a flash bank, available either on-chip or through
+ * a major interface.
+ *
+ * This structure will be passed as a parameter to the callbacks in the
+ * flash_driver_s structure, some of which may modify the contents of
+ * this structure of the area of flash that it defines.  Driver writers
+ * may use the @c driver_priv member to store additional data on a
+ * per-bank basis, if required.
+ */
 typedef struct flash_bank_s
 {
-	struct target_s *target;
-	flash_driver_t *driver;
-	void *driver_priv;
-	int bank_number;
-	u32 base;
-	u32 size;
-	int chip_width;
-	int bus_width;
+	struct target_s *target; /**< Target to which this bank belongs. */
+
+	flash_driver_t *driver; /**< Driver for this bank. */
+	void *driver_priv; /**< Private driver storage pointer */
+
+	int bank_number; /**< The 'bank' (or chip number) of this instance. */
+	u32 base; /**< The base address of this bank */
+	u32 size; /**< The size of this chip bank, in bytes */
+
+	int chip_width; /**< Width of the chip in bytes (1,2,4 bytes) */
+	int bus_width; /**< Maximum bus width, in bytes (1,2,4 bytes) */
+
+	/**
+	 * The number of sectors on this chip.  This value will
+	 * be set intially to 0, and the flash driver must set this to
+	 * some non-zero value during "probe()" or "auto_probe()".
+	 */
 	int num_sectors;
+	/// Array of sectors, allocated and initilized by the flash driver
 	flash_sector_t *sectors;
-	struct flash_bank_s *next;
+
+	struct flash_bank_s *next; /**< The next flash bank on this chip */
 } flash_bank_t;
 
+/// Registers the 'flash' subsystem commands
 extern int flash_register_commands(struct command_context_s *cmd_ctx);
+/// Initializes the 'flash' subsystem drivers
 extern int flash_init_drivers(struct command_context_s *cmd_ctx);
 
+/**
+ * Erases @a length bytes in the @a target flash, starting at @a addr.
+ * @returns ERROR_OK if successful; otherwise, an error code.
+ */
 extern int flash_erase_address_range(struct target_s *target, u32 addr, u32 length);
+/**
+ * Writes @a image into the @a target flash.  The @a written parameter
+ * will contain the 
+ * @param target The target with the flash to be programmed.
+ * @param image The image that will be programmed to flash.
+ * @param written On return, contains the number of bytes written.
+ * @param erase If non-zero, indicates the flash driver should first
+ * erase the corresponding banks or sectors before programming.
+ * @returns ERROR_OK if successful; otherwise, an error code.
+ */
 extern int flash_write(struct target_s *target, struct image_s *image, u32 *written, int erase);
+/**
+ * Forces targets to re-examine their erase/protection state.
+ * This routine must be called when the system may modify the status.
+ */
 extern void flash_set_dirty(void);
+/// @returns The number of flash banks currently defined.
 extern int flash_get_bank_count(void);
+/**
+ * Provides default erased-bank check handling. Checks to see if
+ * the flash driver knows they are erased; if things look uncertain,
+ * this routine will call default_flash_mem_blank_check() to confirm.
+ * @returns ERROR_OK if successful; otherwise, an error code.
+ */
 extern int default_flash_blank_check(struct flash_bank_s *bank);
+/**
+ * Provides a default blank flash memory check.  Ensures the contents
+ * of the given bank have truly been erased.
+ * @param bank The flash bank.
+ * @returns ERROR_OK if successful; otherwise, an error code.
+ */
 extern int default_flash_mem_blank_check(struct flash_bank_s *bank);
 
+/**
+ * Returns a flash bank by the specified flash_bank_s bank_number, @a num.
+ * @param num The flash bank number.
+ * @returns A flash_bank_t for flash bank @a num, or NULL
+ */
 extern flash_bank_t *get_flash_bank_by_num(int num);
+/**
+ * Returns the flash bank like get_flash_bank_by_num(), without probing.
+ * @param num The flash bank number.
+ * @returns A flash_bank_t for flash bank @a num, or NULL.
+ */
 extern flash_bank_t *get_flash_bank_by_num_noprobe(int num);
+/**
+ * Returns the flash bank located at a specified address.
+ * @param target The target, presumed to contain one or more banks.
+ * @param addr An address that is within the range of the bank.
+ * @returns The flash_bank_t located at @a addr, or NULL.
+ */
 extern flash_bank_t *get_flash_bank_by_addr(struct target_s *target, u32 addr);
 
 #define ERROR_FLASH_BANK_INVALID			(-900)

[Openocd-svn] r1941 - trunk/doc

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-29 03:33:04 +0200 (Fri, 29 May 2009)
New Revision: 1941

Modified:
   trunk/doc/openocd.texi
Log:
David Brownell <da...@pa...>:

Provide basic documentation for some of the other flash drivers.

 avr ... looks incomplete, may work with one AVR8 microcontroller
 ecosflash ... can't find docs
 lpc288x ... an NXP part, driver seems lpc2888-specific
 ocl ... some arm7/arm9 thing, can't find docs
 pic32mx ... looks incomplete, for PIC32MX (MIPS 4K) devices
 tms470 ... for TI TMS470 parts

Still seems to be mostly arm7tdmi... several of these have no
users in the current tree.


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-05-28 23:47:37 UTC (rev 1940)
+++ trunk/doc/openocd.texi	2009-05-29 01:33:04 UTC (rev 1941)
@@ -2625,6 +2625,19 @@
 @end deffn
 @end deffn
 
+@deffn {Flash Driver} avr
+The AVR 8-bit microcontrollers from Atmel integrate flash memory.
+@emph{The current implementation is incomplete.}
+@comment - defines mass_erase ... pointless given flash_erase_address
+@end deffn
+
+@deffn {Flash Driver} ecosflash
+@emph{No idea what this is...}
+The @var{ecosflash} driver defines one mandatory parameter,
+the name of a modules of target code which is downloaded
+and executed.
+@end deffn
+
 @deffn {Flash Driver} lpc2000
 Most members of the LPC2000 microcontroller family from NXP
 include internal flash and use ARM7TDMI cores.
@@ -2649,6 +2662,46 @@
 @end example
 @end deffn
 
+@deffn {Flash Driver} lpc288x
+The LPC2888 microcontroller from NXP needs slightly different flash
+support from its lpc2000 siblings.
+The @var{lpc288x} driver defines one mandatory parameter,
+the programming clock rate in Hz.
+LPC flashes don't require the chip and bus width to be specified.
+
+@example
+flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
+@end example
+@end deffn
+
+@deffn {Flash Driver} ocl
+@emph{No idea what this is, other than using some arm7/arm9 core.}
+
+@example
+flash bank ocl 0 0 0 0 $_TARGETNAME
+@end example
+@end deffn
+
+@deffn {Flash Driver} pic32mx
+The PIC32MX microcontrollers are based on the MIPS 4K cores,
+and integrate flash memory.
+@emph{The current implementation is incomplete.}
+
+@example
+flash bank pix32mx 0 0 0 0 $_TARGETNAME
+@end example
+
+@comment numerous *disabled* commands are defined:
+@comment - chip_erase ... pointless given flash_erase_address
+@comment - lock, unlock ... pointless given protect on/off (yes?)
+@comment - pgm_word ... shouldn't bank be deduced from address??
+Some pic32mx-specific commands are defined:
+@deffn Command {pic32mx pgm_word} address value bank
+Programs the specified 32-bit @var{value} at the given @var{address}
+in the specified chip @var{bank}.
+@end deffn
+@end deffn
+
 @deffn {Flash Driver} stellaris
 All members of the Stellaris LM3Sxxx microcontroller family from
 Texas Instruments
@@ -2738,6 +2791,27 @@
 
 @end deffn
 
+@deffn {Flash Driver} tms470
+Most members of the TMS470 microcontroller family from Texas Instruments
+include internal flash and use ARM7TDMI cores.
+This driver doesn't require the chip and bus width to be specified.
+
+Some tms470-specific commands are defined:
+
+@deffn Command {tms470 flash_keyset} key0 key1 key2 key3
+Saves programming keys in a register, to enable flash erase and write commands.
+@end deffn
+
+@deffn Command {tms470 osc_mhz} clock_mhz
+Reports the clock speed, which is used to calculate timings.
+@end deffn
+
+@deffn Command {tms470 plldis} (0|1)
+Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
+the flash clock.
+@end deffn
+@end deffn
+
 @subsection str9xpec driver
 @cindex str9xpec
 

[Openocd-svn] r1940 - trunk

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-29 01:47:37 +0200 (Fri, 29 May 2009)
New Revision: 1940

Modified:
   trunk/bootstrap
Log:
Remove redundant call to autoheader in bootstrap script.

Modified: trunk/bootstrap
===================================================================
--- trunk/bootstrap	2009-05-28 23:13:32 UTC (rev 1939)
+++ trunk/bootstrap	2009-05-28 23:47:37 UTC (rev 1940)
@@ -1,4 +1,5 @@
 #!/bin/sh -e
+# Run the autotools bootstrap sequence to create the configure script
 
 if libtoolize --version >/dev/null 2>&1; then
 	libtoolize="libtoolize"
@@ -13,7 +14,6 @@
 (
 set -x
 aclocal
-autoheader
 ${libtoolize} --automake --copy
 autoconf
 autoheader

[Openocd-svn] r1939 - trunk/doc

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-29 01:13:32 +0200 (Fri, 29 May 2009)
New Revision: 1939

Modified:
   trunk/doc/openocd.texi
Log:
David Brownell <da...@pa...>:

Start converting the architecture-specific commands to @deffn format,
reviewing against the code.

  * armv4_5 disassemble ... now documented; although Jazelle code
    is not handled

  * It's "armv4_5 core_state" not "core_mode"; although Jazelle state
    is not handled

  * arm7/9 "debug" commands ... now with other arm7_9 commands, no
    longer in a separate section

  * arm926ejs cp15 ... previous description was broken, it matched
    the code for arm920t instead

  * Have separate subsections for ARMv4/ARMv5, ARMv6, and ARMv7; the
    latter are new
    
  * Move core-specific descriptions into sub-subsections under those
    architectures; XScale and ARM11 descriptions are new

The new XScale and ARM11 command descriptions surely need elaboration
and review.  ARM CP15 operation descriptions in general seem to be
confused and incomplete.


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-05-28 01:18:47 UTC (rev 1938)
+++ trunk/doc/openocd.texi	2009-05-28 23:13:32 UTC (rev 1939)
@@ -2482,8 +2482,9 @@
 A relocation @var{offset} may be specified, in which case it is added
 to the base address for each section in the image.
 The file [@var{type}] can be specified
-explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
-(ELF file) or @option{s19} (Motorola s19).
+explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
+@option{elf} (ELF file), @option{s19} (Motorola s19).
+@option{mem}, or @option{builder}.
 The relevant flash sectors will be erased prior to programming
 if the @option{erase} parameter is given.
 The flash bank to use is inferred from the @var{address} of
@@ -3463,189 +3464,404 @@
 
 @end itemize
 
-@section Target Specific Commands
-@cindex Target Specific Commands
+@section Architecture and Core Specific Commands
+@cindex Architecture Specific Commands
+@cindex Core Specific Commands
 
+Most CPUs have specialized JTAG operations to support debugging.
+OpenOCD packages most such operations in its standard command framework.
+Some of those operations don't fit well in that framework, so they are
+exposed here using architecture or implementation specific commands.
 
-@section Architecture Specific Commands
-@cindex Architecture Specific Commands
+@subsection ARMv4 and ARMv5 Architecture
+@cindex ARMv4 specific commands
+@cindex ARMv5 specific commands
 
-@subsection ARMV4/5 specific commands
-@cindex ARMV4/5 specific commands
+These commands are specific to ARM architecture v4 and v5,
+including all ARM7 or ARM9 systems and Intel XScale.
+They are available in addition to other core-specific
+commands that may be available.
 
-These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
-or Intel XScale (XScale isn't supported yet).
-@itemize @bullet
-@item @b{armv4_5 reg}
-@cindex armv4_5 reg
-@*Display a list of all banked core registers, fetching the current value from every
+@deffn Command {armv4_5 core_state} [arm|thumb]
+Displays the core_state, optionally changing it to process
+either @option{arm} or @option{thumb} instructions.
+The target may later be resumed in the currently set core_state.
+(Processors may also support the Jazelle state, but
+that is not currently supported in OpenOCD.)
+@end deffn
+
+@deffn Command {armv4_5 disassemble} address count [thumb]
+@cindex disassemble
+Disassembles @var{count} instructions starting at @var{address}.
+If @option{thumb} is specified, Thumb (16-bit) instructions are used;
+else ARM (32-bit) instructions are used.
+(Processors may also support the Jazelle state, but
+those instructions are not currently understood by OpenOCD.)
+@end deffn
+
+@deffn Command {armv4_5 reg}
+Display a list of all banked core registers, fetching the current value from every
 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
 register value. 
-@item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
-@cindex armv4_5 core_mode
-@*Displays the core_mode, optionally changing it to either ARM or Thumb mode.
-The target is resumed in the currently set @option{core_mode}. 
-@end itemize
+@end deffn
 
-@subsection ARM7/9 specific commands
-@cindex ARM7/9 specific commands
+@subsubsection ARM7 and ARM9 specific commands
+@cindex ARM7 specific commands
+@cindex ARM9 specific commands
 
-These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
-ARM920T or ARM926EJ-S.
-@itemize @bullet
-@item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
-@cindex arm7_9 dbgrq
-@*Enable use of the DBGRQ bit to force entry into debug mode. This should be
+These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
+ARM9TDMI, ARM920T or ARM926EJ-S.
+They are available in addition to the ARMv4/5 commands,
+and any other core-specific commands that may be available.
+
+@deffn Command {arm7_9 dbgrq} (enable|disable)
+Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
+instead of breakpoints.  This should be
 safe for all but ARM7TDMI--S cores (like Philips LPC). 
-@item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
-@cindex arm7_9 fast_memory_access
+@end deffn
+
+@deffn Command {arm7_9 dcc_downloads} (enable|disable)
+@cindex DCC
+Control the use of the debug communications channel (DCC) to write larger (>128 byte)
+amounts of memory. DCC downloads offer a huge speed increase, but might be
+unsafe, especially with targets running at very low speeds. This command was introduced
+with OpenOCD rev. 60, and requires a few bytes of working area.
+@end deffn
+
 @anchor{arm7_9 fast_memory_access}
-@*Allow OpenOCD to read and write memory without checking completion of
+@deffn Command {arm7_9 fast_memory_access} (enable|disable)
+Enable or disable memory writes and reads that don't check completion of
 the operation. This provides a huge speed increase, especially with USB JTAG
 cables (FT2232), but might be unsafe if used with targets running at very low
 speeds, like the 32kHz startup clock of an AT91RM9200. 
-@item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
-@cindex arm7_9 dcc_downloads
-@*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
-amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
-unsafe, especially with targets running at very low speeds. This command was introduced
-with OpenOCD rev. 60, and requires a few bytes of working area.
-@end itemize
+@end deffn
 
-@subsection ARM720T specific commands
+@deffn {Debug Command} {arm7_9 write_core_reg} num mode word
+@emph{This is intended for use while debugging OpenOCD; you probably
+shouldn't use it.}
+
+Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
+as used in the specified @var{mode}
+(where e.g. mode 16 is "user" and mode 19 is "supervisor";
+the M4..M0 bits of the PSR).
+Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
+Register 16 is the mode-specific SPSR,
+unless the specified mode is 0xffffffff (32-bit all-ones)
+in which case register 16 is the CPSR.
+The write goes directly to the CPU, bypassing the register cache.
+@end deffn
+
+@deffn {Debug Command} {arm7_9 write_xpsr} word (0|1)
+@emph{This is intended for use while debugging OpenOCD; you probably
+shouldn't use it.}
+
+If the second parameter is zero, writes @var{word} to the
+Current Program Status register (CPSR).
+Else writes @var{word} to the current mode's Saved PSR (SPSR).
+In both cases, this bypasses the register cache.
+@end deffn
+
+@deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (0|1)
+@emph{This is intended for use while debugging OpenOCD; you probably
+shouldn't use it.}
+
+Writes eight bits to the CPSR or SPSR,
+first rotating them by @math{2*rotate} bits,
+and bypassing the register cache.
+This has lower JTAG overhead than writing the entire CPSR or SPSR
+with @command{arm7_9 write_xpsr}.
+@end deffn
+
+@subsubsection ARM720T specific commands
 @cindex ARM720T specific commands
 
-@itemize @bullet
-@item @b{arm720t cp15} <@var{num}> [@var{value}]
-@cindex arm720t cp15
-@*display/modify cp15 register <@option{num}> [@option{value}].
-@item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
-@cindex arm720t md<bhw>_phys
-@*Display memory at physical address addr. 
-@item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
-@cindex arm720t mw<bhw>_phys
-@*Write memory at physical address addr.
-@item @b{arm720t virt2phys} <@var{va}>
-@cindex arm720t virt2phys
-@*Translate a virtual address to a physical address. 
-@end itemize
+These commands are available to ARM720T based CPUs,
+which are implementations of the ARMv4T architecture
+based on the ARM7TDMI-S integer core.
+They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
 
-@subsection ARM9TDMI specific commands
+@deffn Command {arm720t cp15} regnum [value]
+Display cp15 register @var{regnum};
+else if a @var{value} is provided, that value is written to that register.
+@end deffn
+
+@deffn Command {arm720t mdw_phys} addr [count]
+@deffnx Command {arm720t mdh_phys} addr [count]
+@deffnx Command {arm720t mdb_phys} addr [count]
+Display contents of physical address @var{addr}, as
+32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
+or 8-bit bytes (@command{mdb_phys}).
+If @var{count} is specified, displays that many units.
+@end deffn
+
+@deffn Command {arm720t mww_phys} addr word
+@deffnx Command {arm720t mwh_phys} addr halfword
+@deffnx Command {arm720t mwb_phys} addr byte
+Writes the specified @var{word} (32 bits),
+@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
+at the specified physical address @var{addr}.
+@end deffn
+
+@deffn Command {arm720t virt2phys} va
+Translate a virtual address @var{va} to a physical address
+and display the result.
+@end deffn
+
+@subsubsection ARM9TDMI specific commands
 @cindex ARM9TDMI specific commands
 
-@itemize @bullet
-@item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
-@cindex arm9tdmi vector_catch
-@*Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
+Many ARM9-family CPUs are built around ARM9TDMI integer cores,
+or processors resembling ARM9TDMI, and can use these commands.
+Such cores include the ARM920T, ARM926EJ-S, and ARM966.
+
+@deffn Command {arm9tdmi vector_catch} (all|none|list)
+Catch arm9 interrupt vectors, can be @option{all}, @option{none},
+or a list with one or more of the following:
 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
 @option{irq} @option{fiq}.
+@end deffn
 
-Can also be used on other ARM9 based cores such as ARM966, ARM920T and ARM926EJ-S.
-@end itemize
+@subsubsection ARM920T specific commands
+@cindex ARM920T specific commands
 
-@subsection ARM966E specific commands
-@cindex ARM966E specific commands
+These commands are available to ARM920T based CPUs,
+which are implementations of the ARMv4T architecture
+built using the ARM9TDMI integer core.
+They are available in addition to the ARMv4/5, ARM7/ARM9,
+and ARM9TDMI commands.
 
-@itemize @bullet
-@item @b{arm966e cp15} <@var{num}> [@var{value}]
-@cindex arm966e cp15
-@*display/modify cp15 register <@option{num}> [@option{value}].
-@end itemize
+@deffn Command {arm920t cache_info}
+Print information about the caches found. This allows to see whether your target
+is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
+@end deffn
 
-@subsection ARM920T specific commands
-@cindex ARM920T specific commands
+@deffn Command {arm920t cp15} regnum [value]
+Display cp15 register @var{regnum};
+else if a @var{value} is provided, that value is written to that register.
+@end deffn
 
-@itemize @bullet
-@item @b{arm920t cp15} <@var{num}> [@var{value}]
-@cindex arm920t cp15
-@*display/modify cp15 register <@option{num}> [@option{value}].
-@item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
-@cindex arm920t cp15i
-@*display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
-@item @b{arm920t cache_info}
-@cindex arm920t cache_info
-@*Print information about the caches found. This allows to see whether your target
-is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache). 
-@item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
-@cindex arm920t md<bhw>_phys
-@*Display memory at physical address addr. 
-@item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
-@cindex arm920t mw<bhw>_phys
-@*Write memory at physical address addr. 
-@item @b{arm920t read_cache} <@var{filename}>
-@cindex arm920t read_cache
-@*Dump the content of ICache and DCache to a file. 
-@item @b{arm920t read_mmu} <@var{filename}>
-@cindex arm920t read_mmu
-@*Dump the content of the ITLB and DTLB to a file. 
-@item @b{arm920t virt2phys} <@var{va}>
-@cindex arm920t virt2phys
-@*Translate a virtual address to a physical address. 
-@end itemize
+@deffn Command {arm920t cp15i} opcode [value [address]]
+Interpreted access using cp15 @var{opcode}.
+If no @var{value} is provided, the result is displayed.
+Else if that value is written using the specified @var{address},
+or using zero if no other address is not provided.
+@end deffn
 
-@subsection ARM926EJ-S specific commands
+@deffn Command {arm920t mdw_phys} addr [count]
+@deffnx Command {arm920t mdh_phys} addr [count]
+@deffnx Command {arm920t mdb_phys} addr [count]
+Display contents of physical address @var{addr}, as
+32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
+or 8-bit bytes (@command{mdb_phys}).
+If @var{count} is specified, displays that many units.
+@end deffn
+
+@deffn Command {arm920t mww_phys} addr word
+@deffnx Command {arm920t mwh_phys} addr halfword
+@deffnx Command {arm920t mwb_phys} addr byte
+Writes the specified @var{word} (32 bits),
+@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
+at the specified physical address @var{addr}.
+@end deffn
+
+@deffn Command {arm920t read_cache} filename
+Dump the content of ICache and DCache to a file named @file{filename}.
+@end deffn
+
+@deffn Command {arm920t read_mmu} filename
+Dump the content of the ITLB and DTLB to a file named @file{filename}.
+@end deffn
+
+@deffn Command {arm920t virt2phys} @var{va}
+Translate a virtual address @var{va} to a physical address
+and display the result.
+@end deffn
+
+@subsubsection ARM926EJ-S specific commands
 @cindex ARM926EJ-S specific commands
 
-@itemize @bullet
-@item @b{arm926ejs cp15} <@var{num}> [@var{value}]
-@cindex arm926ejs cp15
-@*display/modify cp15 register <@option{num}> [@option{value}].
-@item @b{arm926ejs cache_info}
-@cindex arm926ejs cache_info
-@*Print information about the caches found.
-@item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
-@cindex arm926ejs md<bhw>_phys
-@*Display memory at physical address addr. 
-@item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
-@cindex arm926ejs mw<bhw>_phys
-@*Write memory at physical address addr. 
-@item @b{arm926ejs virt2phys} <@var{va}>
-@cindex arm926ejs virt2phys
-@*Translate a virtual address to a physical address. 
-@end itemize
+These commands are available to ARM926EJ-S based CPUs,
+which are implementations of the ARMv5TEJ architecture
+based on the ARM9EJ-S integer core.
+They are available in addition to the ARMv4/5, ARM7/ARM9,
+and ARM9TDMI commands.
 
-@subsection CORTEX_M3 specific commands
-@cindex CORTEX_M3 specific commands
+@deffn Command {arm926ejs cache_info}
+Print information about the caches found.
+@end deffn
 
-@itemize @bullet
-@item @b{cortex_m3 maskisr} <@var{on}|@var{off}>
-@cindex cortex_m3 maskisr
-@*Enable masking (disabling) interrupts during target step/resume.
-@end itemize
+@deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
+Accesses cp15 register @var{regnum} using
+@var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
+If a @var{value} is provided, that value is written to that register.
+Else that register is read and displayed.
+@end deffn
 
-@page
-@section Debug commands
-@cindex Debug commands
-The following commands give direct access to the core, and are most likely
-only useful while debugging OpenOCD.
-@itemize @bullet
-@item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
-@cindex arm7_9 write_xpsr
-@*Immediately write either the current program status register (CPSR) or the saved
-program status register (SPSR), without changing the register cache (as displayed
-by the @option{reg} and @option{armv4_5 reg} commands). 
-@item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
-<@var{0=cpsr},@var{1=spsr}>
-@cindex arm7_9 write_xpsr_im8
-@*Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
-operation (similar to @option{write_xpsr}). 
-@item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
-@cindex arm7_9 write_core_reg
-@*Write a core register, without changing the register cache (as displayed by the
-@option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
-encoding of the [M4:M0] bits of the PSR. 
-@end itemize
+@deffn Command {arm926ejs mdw_phys} addr [count]
+@deffnx Command {arm926ejs mdh_phys} addr [count]
+@deffnx Command {arm926ejs mdb_phys} addr [count]
+Display contents of physical address @var{addr}, as
+32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
+or 8-bit bytes (@command{mdb_phys}).
+If @var{count} is specified, displays that many units.
+@end deffn
 
-@section Target Requests
-@cindex Target Requests
-OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
+@deffn Command {arm926ejs mww_phys} addr word
+@deffnx Command {arm926ejs mwh_phys} addr halfword
+@deffnx Command {arm926ejs mwb_phys} addr byte
+Writes the specified @var{word} (32 bits),
+@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
+at the specified physical address @var{addr}.
+@end deffn
+
+@deffn Command {arm926ejs virt2phys} @var{va}
+Translate a virtual address @var{va} to a physical address
+and display the result.
+@end deffn
+
+@subsubsection ARM966E specific commands
+@cindex ARM966E specific commands
+
+These commands are available to ARM966 based CPUs,
+which are implementations of the ARMv5TE architecture.
+They are available in addition to the ARMv4/5, ARM7/ARM9,
+and ARM9TDMI commands.
+
+@deffn Command {arm966e cp15} regnum [value]
+Display cp15 register @var{regnum};
+else if a @var{value} is provided, that value is written to that register.
+@end deffn
+
+@subsubsection XScale specific commands
+@cindex XScale specific commands
+
+These commands are available to XScale based CPUs,
+which are implementations of the ARMv5TE architecture.
+
+@deffn Command {xscale analyze_trace}
+Displays the contents of the trace buffer.
+@end deffn
+
+@deffn Command {xscale cache_clean_address} address
+Changes the address used when cleaning the data cache.
+@end deffn
+
+@deffn Command {xscale cache_info}
+Displays information about the CPU caches.
+@end deffn
+
+@deffn Command {xscale cp15} regnum [value]
+Display cp15 register @var{regnum};
+else if a @var{value} is provided, that value is written to that register.
+@end deffn
+
+@deffn Command {xscale debug_handler} target address
+Changes the address used for the specified target's debug handler.
+@end deffn
+
+@deffn Command {xscale dcache} (enable|disable)
+Enables or disable the CPU's data cache.
+@end deffn
+
+@deffn Command {xscale dump_trace} filename
+Dumps the raw contents of the trace buffer to @file{filename}.
+@end deffn
+
+@deffn Command {xscale icache} (enable|disable)
+Enables or disable the CPU's instruction cache.
+@end deffn
+
+@deffn Command {xscale mmu} (enable|disable)
+Enables or disable the CPU's memory management unit.
+@end deffn
+
+@deffn Command {xscale trace_buffer} (enable|disable) [fill [n] | wrap]
+Enables or disables the trace buffer,
+and controls how it is emptied.
+@end deffn
+
+@deffn Command {xscale trace_image} filename [offset [type]]
+Opens a trace image from @file{filename}, optionally rebasing
+its segment addresses by @var{offset}.
+The image @var{type} may be one of
+@option{bin} (binary), @option{ihex} (Intel hex),
+@option{elf} (ELF file), @option{s19} (Motorola s19),
+@option{mem}, or @option{builder}.
+@end deffn
+
+@deffn Command {xscale vector_catch} mask
+Provide a bitmask showing the vectors to catch.
+@end deffn
+
+@subsection ARMv6 Architecture
+
+@subsubsection ARM11 specific commands
+@cindex ARM11 specific commands
+
+@deffn Command {arm11 mcr} p1 p2 p3 p4 p5
+Read coprocessor register
+@end deffn
+
+@deffn Command {arm11 memwrite burst} [value]
+Displays the value of the memwrite burst-enable flag,
+which is enabled by default.
+If @var{value} is defined, first assigns that.
+@end deffn
+
+@deffn Command {arm11 memwrite error_fatal} [value]
+Displays the value of the memwrite error_fatal flag,
+which is enabled by default.
+If @var{value} is defined, first assigns that.
+@end deffn
+
+@deffn Command {arm11 mrc} p1 p2 p3 p4 p5 value
+Write coprocessor register
+@end deffn
+
+@deffn Command {arm11 no_increment}  [value]
+Displays the value of the flag controlling whether
+some read or write operations increment the pointer
+(the default behavior) or not (acting like a FIFO).
+If @var{value} is defined, first assigns that.
+@end deffn
+
+@deffn Command {arm11 step_irq_enable}  [value]
+Displays the value of the flag controlling whether
+IRQs are enabled during single stepping;
+they is disabled by default.
+If @var{value} is defined, first assigns that.
+@end deffn
+
+@subsection ARMv7 Architecture
+
+@subsubsection Cortex-M3 specific commands
+@cindex Cortex-M3 specific commands
+
+@deffn Command {cortex_m3 maskisr} (on|off)
+Control masking (disabling) interrupts during target step/resume.
+@end deffn
+
+@section Target DCC Requests
+@cindex Linux-ARM DCC support
+@cindex libdcc
+@cindex DCC
+OpenOCD can handle certain target requests; currently debugmsgs
+@command{target_request debugmsgs}
+are only supported for arm7_9 and cortex_m3.
+
 See libdcc in the contrib dir for more details.
-@itemize @bullet
-@item @b{target_request debugmsgs} <@var{enable}|@var{disable}|@var{charmsg}>
-@cindex target_request debugmsgs
-@*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running. @var{charmsg} receives messages if Linux kernel ``Kernel low-level debugging via EmbeddedICE DCC channel'' option is enabled.
-@end itemize
+Linux-ARM kernels have a ``Kernel low-level debugging
+via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
+depends on CONFIG_DEBUG_LL) which uses this mechanism to
+deliver messages before a serial console can be activated.
 
+@deffn Command {target_request debugmsgs} [enable|disable|charmsg]
+Displays current handling of target DCC message requests.
+These messages may be sent to the debugger while the target is running.
+The optional @option{enable} and @option{charmsg} parameters are
+equivalent; both enable the messages, @option{disable} disables them.
+@end deffn
+
 @node JTAG Commands
 @chapter JTAG Commands
 @cindex JTAG Commands

[Openocd-svn] r1938 - trunk/doc

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-28 03:18:47 +0200 (Thu, 28 May 2009)
New Revision: 1938

Modified:
   trunk/doc/openocd.texi
Log:
David Brownell <da...@pa...>:

Continue updating the NOR flash coverage to use @deffn syntax, so the
commands have more consistent presentation and formatting.  This
reorganizes information and updates its presentation, except where
the information didn't really match the code.

This patch updates the main commands, and finishes making the section
structure parallel the NAND presentation.  Of note:

 - The "flash fill[whb] addr value length" commands are now documented.

 - The "flash bank" command is now presented much earlier

 - Explicit mention is made that NOR flash should be read using just
   standard memory access commands, like "mdw" and "dump_image".



Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-05-28 01:11:10 UTC (rev 1937)
+++ trunk/doc/openocd.texi	2009-05-28 01:18:47 UTC (rev 1938)
@@ -64,7 +64,7 @@
 * Reset Configuration::              Reset Configuration
 * Tap Creation::                     Tap Creation
 * Target Configuration::             Target Configuration
-* Flash Configuration::              Flash Configuration
+* Flash Commands::                   Flash Commands
 * NAND Flash Commands::              NAND Flash Commands
 * General Commands::                 General Commands
 * JTAG Commands::                    JTAG Commands
@@ -2305,9 +2305,8 @@
 @end example
 @* The target# is a the 0 based target numerical index.
 
-@node Flash Configuration
-@chapter Flash programming
-@cindex Flash Configuration
+@node Flash Commands
+@chapter Flash Commands
 
 OpenOCD has different commands for NOR and NAND flash;
 the ``flash'' command works with NOR flash, while
@@ -2319,95 +2318,36 @@
 However, the documentation also uses ``flash'' as a generic term;
 for example, ``Put flash configuration in board-specific files''.
 
-@b{Note:} As of 28/nov/2008 OpenOCD does not know how to program a SPI
+@quotation Note
+As of 28-nov-2008 OpenOCD does not know how to program a SPI
 flash that a micro may boot from. Perhaps you, the reader, would like to
 contribute support for this.
+@end quotation
 
 Flash Steps:
 @enumerate
-@item Configure via the command @b{flash bank} 
-@* Normally this is done in a configuration file.
-@item Operate on the flash via @b{flash SOMECOMMAND}
+@item Configure via the command @command{flash bank}
+@* Do this in a board-specific configuration file,
+passing parameters as needed by the driver.
+@item Operate on the flash via @command{flash subcommand}
 @* Often commands to manipulate the flash are typed by a human, or run
-via a script in some automated way. For example: To program the boot
-flash on your board.
+via a script in some automated way.  Common tasks include writing a
+boot loader, operating system, or other data.
 @item GDB Flashing
 @* Flashing via GDB requires the flash be configured via ``flash
 bank'', and the GDB flash features be enabled.
 @xref{GDB Configuration}.
 @end enumerate
 
-@section Flash commands
-@cindex Flash commands
-@subsection flash banks
-@b{flash banks}
-@cindex flash banks
-@*List configured flash banks 
-@*@b{NOTE:} the singular form: 'flash bank' is used to configure the flash banks.
-@subsection flash info
-@b{flash info} <@var{num}>
-@cindex flash info
-@*Print info about flash bank <@option{num}> 
-@subsection flash probe
-@b{flash probe} <@var{num}>
-@cindex flash probe
-@*Identify the flash, or validate the parameters of the configured flash. Operation
-depends on the flash type. 
-@subsection flash erase_check
-@b{flash erase_check} <@var{num}>
-@cindex flash erase_check
-@*Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
-updates the erase state information displayed by @option{flash info}. That means you have
-to issue an @option{erase_check} command after erasing or programming the device to get
-updated information. 
-@subsection flash protect_check
-@b{flash protect_check} <@var{num}>
-@cindex flash protect_check
-@*Check protection state of sectors in flash bank <num>. 
-@option{flash erase_sector} using the same syntax. 
-@subsection flash erase_sector
-@b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
-@cindex flash erase_sector
-@anchor{flash erase_sector}
-@*Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
-<@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
-require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
-the CFI driver).
-@subsection flash erase_address
-@b{flash erase_address} <@var{address}> <@var{length}>
-@cindex flash erase_address
-@*Erase sectors starting at <@var{address}> for <@var{length}> bytes
-@subsection flash write_bank
-@b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
-@cindex flash write_bank
-@anchor{flash write_bank}
-@*Write the binary <@var{file}> to flash bank <@var{num}>, starting at
-<@option{offset}> bytes from the beginning of the bank.
-@subsection flash write_image
-@b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
-@cindex flash write_image
-@anchor{flash write_image}
-@*Write the image <@var{file}> to the current target's flash bank(s). A relocation
-[@var{offset}] can be specified and the file [@var{type}] can be specified
-explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
-(ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
-if the @option{erase} parameter is given.
-@subsection flash protect
-@b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
-@cindex flash protect
-@*Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
-<@var{last}> of @option{flash bank} <@var{num}>.
+Many CPUs have the ablity to ``boot'' from the first flash bank.
+This means that misprograming that bank can ``brick'' a system,
+so that it can't boot.
+JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
+board by (re)installing working boot firmware.
 
-@section flash bank command
-The @command{flash bank} command is used to configure one or more flash
-chips (or @emph{banks} in OpenOCD terms).
-Most CPUs have the ablity to ``boot'' from the first flash bank.
+@section Flash Configuration Commands
+@cindex flash configuration
 
-@quotation Note
-This command is not available after OpenOCD initialization has completed.
-Use it in board specific configuration files, not interactively.
-@end quotation
-
 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
 Configures a flash bank which provides persistent storage
 for addresses from @math{base} to @math{base + size - 1}.
@@ -2435,8 +2375,154 @@
 additional parameters.  See the driver-specific documentation
 for more information.
 @end itemize
+@quotation Note
+This command is not available after OpenOCD initialization has completed.
+Use it in board specific configuration files, not interactively.
+@end quotation
 @end deffn
 
+@comment the REAL name for this command is "ocd_flash_banks"
+@comment less confusing would be:  "flash list" (like "nand list")
+@deffn Command {flash banks}
+Prints a one-line summary of each device declared
+using @command{flash bank}, numbered from zero.
+Note that this is the @emph{plural} form;
+the @emph{singular} form is a very different command.
+@end deffn
+
+@deffn Command {flash probe} num
+Identify the flash, or validate the parameters of the configured flash. Operation
+depends on the flash type.
+The @var{num} parameter is a value shown by @command{flash banks}.
+Most flash commands will implicitly @emph{autoprobe} the bank;
+flash drivers can distinguish between probing and autoprobing,
+but most don't bother.
+@end deffn
+
+@section Erasing, Reading, Writing to Flash
+@cindex flash erasing
+@cindex flash reading
+@cindex flash writing
+@cindex flash programming
+
+One feature distinguishing NOR flash from NAND or serial flash technologies
+is that for read access, it acts exactly like any other addressible memory.
+This means you can use normal memory read commands like @command{mdw} or
+@command{dump_image} with it, with no special @command{flash} subcommands.
+@xref{Memory access}.
+@xref{Image access}.
+
+Write access works differently.  Flash memory normally needs to be erased
+before it's written.  Erasing a sector turns all of its bits to ones, and
+writing can turn ones into zeroes.  This is why there are special commands
+for interactive erasing and writing, and why GDB needs to know which parts
+of the address space hold NOR flash memory.
+
+@quotation Note
+Most of these erase and write commands leverage the fact that NOR flash
+chips consume target address space.  They implicitly refer to the current
+JTAG target, and map from an address in that target's address space
+back to a flash bank.
+@comment In May 2009, those mappings may fail if any bank associated
+@comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
+A few commands use abstract addressing based on bank and sector numbers,
+and don't depend on searching the current target and its address space.
+Avoid confusing the two command models.
+@end quotation
+
+Some flash chips implement software protection against accidental writes,
+since such buggy writes could in some cases ``brick'' a system.
+For such systems, erasing and writing may require sector protection to be
+disabled first.
+Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
+and AT91SAM7 on-chip flash.
+@xref{flash protect}.
+
+@anchor{flash erase_sector}
+@deffn Command {flash erase_sector} num first last
+Erase sectors in bank @var{num}, starting at sector @var{first} up to and including
+@var{last}. Sector numbering starts at 0.
+The @var{num} parameter is a value shown by @command{flash banks}.
+@end deffn
+
+@deffn Command {flash erase_address} address length
+Erase sectors starting at @var{address} for @var{length} bytes.
+The flash bank to use is inferred from the @var{address}, and
+the specified length must stay within that bank.
+As a special case, when @var{length} is zero and @var{address} is
+the start of the bank, the whole flash is erased.
+@end deffn
+
+@deffn Command {flash fillw} address word length
+@deffnx Command {flash fillh} address halfword length
+@deffnx Command {flash fillb} address byte length
+Fills flash memory with the specified @var{word} (32 bits),
+@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
+starting at @var{address} and continuing
+for @var{length} units (word/halfword/byte).
+No erasure is done before writing; when needed, that must be done
+before issuing this command.
+Writes are done in blocks of up to 1024 bytes, and each write is
+verified by reading back the data and comparing it to what was written.
+The flash bank to use is inferred from the @var{address} of
+each block, and the specified length must stay within that bank.
+@end deffn
+@comment no current checks for errors if fill blocks touch multiple banks!
+
+@anchor{flash write_bank}
+@deffn Command {flash write_bank} num filename offset
+Write the binary @file{filename} to flash bank @var{num},
+starting at @var{offset} bytes from the beginning of the bank.
+The @var{num} parameter is a value shown by @command{flash banks}.
+@end deffn
+
+@anchor{flash write_image}
+@deffn Command {flash write_image} [erase] filename [offset] [type]
+Write the image @file{filename} to the current target's flash bank(s).
+A relocation @var{offset} may be specified, in which case it is added
+to the base address for each section in the image.
+The file [@var{type}] can be specified
+explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
+(ELF file) or @option{s19} (Motorola s19).
+The relevant flash sectors will be erased prior to programming
+if the @option{erase} parameter is given.
+The flash bank to use is inferred from the @var{address} of
+each image segment.
+@end deffn
+
+@section Other Flash commands
+@cindex flash protection
+
+@deffn Command {flash erase_check} num
+Check erase state of sectors in flash bank @var{num},
+and display that status.
+The @var{num} parameter is a value shown by @command{flash banks}.
+This is the only operation that
+updates the erase state information displayed by @option{flash info}. That means you have
+to issue an @command{flash erase_check} command after erasing or programming the device
+to get updated information.
+(Code execution may have invalidated any state records kept by OpenOCD.)
+@end deffn
+
+@deffn Command {flash info} num
+Print info about flash bank @var{num}
+The @var{num} parameter is a value shown by @command{flash banks}.
+The information includes per-sector protect status.
+@end deffn
+
+@anchor{flash protect}
+@deffn Command {flash protect} num first last (on|off)
+Enable (@var{on}) or disable (@var{off}) protection of flash sectors
+@var{first} to @var{last} of flash bank @var{num}.
+The @var{num} parameter is a value shown by @command{flash banks}.
+@end deffn
+
+@deffn Command {flash protect_check} num
+Check protection state of sectors in flash bank @var{num}.
+The @var{num} parameter is a value shown by @command{flash banks}.
+@comment @option{flash erase_sector} using the same syntax.
+@end deffn
+
 @section Flash Drivers, Options, and Commands
 @anchor{Flash Driver List}
 As noted above, the @command{flash bank} command requires a driver name,
@@ -3279,6 +3365,7 @@
 
 
 @section Memory access commands
+@anchor{Memory access}
 @subsection meminfo
 display available RAM memory.
 @subsection Memory peek/poke type commands
@@ -3314,6 +3401,7 @@
 @end itemize
 
 @section Image loading commands
+@anchor{Image access}
 @subsection load_image
 @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
 @cindex load_image

[Openocd-svn] r1937 - trunk/doc

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-28 03:11:10 +0200 (Thu, 28 May 2009)
New Revision: 1937

Modified:
   trunk/doc/openocd.texi
Log:
David Brownell <da...@pa...>:

Start updating the NOR flash coverage to use @deffn syntax, so the
commands have more consistent presentation and formatting.  This
reorganizes information and updates its presentation, except where
the information didn't really match the code.

This patch updates most of the driver specific support, creating one
new (and alphabetized!) section just for driver-specific data, where
previously that data was split over up to three sections.  Of note:

 - The at91sam7 docs were a bit out of date with respect to the code.

 - The "str9xpec" stuff still deserves some work.  For now, it sits
   in its own subsection; pretty messy.

 - Likewise the "mflash" stuff.  That's a parallel infrastructure,
   and is now in a section of its own.

 - The "mass_erase" commands for the Cortex M3 chips got turned into
   footnotes.  IMO, they should vanish sometime; they're superfluous.

 - There are still a bunch of undocumented NOR drivers.  Examples:
   avr(8), tms470, pic32mx, more.

Plus there are a handful of minor tweaks to the NAND docs (to help make
the NOR and NAND presentations be parallel); the "Command Index" has
been renamed as the "Command and Driver Index"; reference TI instead
of Luminary Micro in several places.


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-05-28 00:47:30 UTC (rev 1936)
+++ trunk/doc/openocd.texi	2009-05-28 01:11:10 UTC (rev 1937)
@@ -82,7 +82,7 @@
 @comment Occurs when creating ``--html --no-split'' output
 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
 * OpenOCD Concept Index::            Concept Index
-* OpenOCD Command Index::            Command Index
+* Command and Driver Index::         Command and Driver Index
 @end menu
 
 @node About
@@ -110,7 +110,7 @@
 
 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
-Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be
+Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
 debugged via the GDB protocol.
 
 @b{Flash Programing:} Flash writing is supported for external CFI
@@ -497,7 +497,7 @@
 @item @b{signalyzer}
 @* See: @url{http://www.signalyzer.com}
 @item @b{evb_lm3s811}
-@* See: @url{http://www.luminarymicro.com} - The Luminary Micro Stellaris LM3S811 eval board has an FTD2232C chip built in.
+@* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
 @item @b{olimex-jtag}
 @* See: @url{http://www.olimex.com}
 @item @b{flyswatter}
@@ -2398,204 +2398,265 @@
 @*Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
 <@var{last}> of @option{flash bank} <@var{num}>.
 
-@subsection mFlash commands
-@cindex mFlash commands
+@section flash bank command
+The @command{flash bank} command is used to configure one or more flash
+chips (or @emph{banks} in OpenOCD terms).
+Most CPUs have the ablity to ``boot'' from the first flash bank.
+
+@quotation Note
+This command is not available after OpenOCD initialization has completed.
+Use it in board specific configuration files, not interactively.
+@end quotation
+
+@deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
+Configures a flash bank which provides persistent storage
+for addresses from @math{base} to @math{base + size - 1}.
+These banks will often be visible to GDB through the target's memory map.
+In some cases, configuring a flash bank will activate extra commands;
+see the driver-specific documentation.
+
 @itemize @bullet
-@item @b{mflash probe} 
-@cindex mflash probe
-@*Probe mflash.
-@item @b{mflash write} <@var{num}> <@var{file}> <@var{offset}>
-@cindex mflash write
-@*Write the binary <@var{file}> to mflash bank <@var{num}>, starting at
-<@var{offset}> bytes from the beginning of the bank.
-@item @b{mflash dump} <@var{num}> <@var{file}> <@var{offset}> <@var{size}>
-@cindex mflash dump
-@*Dump <size> bytes, starting at <@var{offset}> bytes from the beginning of the <@var{num}> bank 
-to a <@var{file}>.
-@item @b{mflash config pll} <@var{frequency}>
-@cindex mflash config pll
-@*Configure mflash pll. <@var{frequency}> is input frequency of mflash. The order is Hz.
-Issuing this command will erase mflash's whole internal nand and write new pll. 
-After this command, mflash needs power-on-reset for normal operation.
-If pll was newly configured, storage and boot(optional) info also need to be update.
-@item @b{mflash config boot}
-@cindex mflash config boot
-@*Configure bootable option. If bootable option is set, mflash offer the first 8 sectors
-(4kB) for boot.
-@item @b{mflash config storage}
-@cindex mflash config storage
-@*Configure storage information. For the normal storage operation, this information must be
-written. 
+@item @var{driver} ... identifies the controller driver
+associated with the flash bank being declared.
+This is usually @code{cfi} for external flash, or else
+the name of a microcontroller with embedded flash memory.
+@xref{Flash Driver List}.
+@item @var{base} ... Base address of the flash chip.
+@item @var{size} ... Size of the chip, in bytes.
+For some drivers, this value is detected from the hardware.
+@item @var{chip_width} ... Width of the flash chip, in bytes;
+ignored for most microcontroller drivers.
+@item @var{bus_width} ... Width of the data bus used to access the
+chip, in bytes; ignored for most microcontroller drivers.
+@item @var{target} ... Names the target used to issue
+commands to the flash controller.
+@comment Actually, it's currently a controller-specific parameter...
+@item @var{driver_options} ... drivers may support, or require,
+additional parameters.  See the driver-specific documentation
+for more information.
 @end itemize
+@end deffn
 
-@section flash bank command
-The @b{flash bank} command is used to configure one or more flash chips (or banks in OpenOCD terms)
+@section Flash Drivers, Options, and Commands
+@anchor{Flash Driver List}
+As noted above, the @command{flash bank} command requires a driver name,
+and allows driver-specific options and behaviors.
+Some drivers also activate driver-specific commands.
 
-@example
-@b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
-<@var{bus_width}> <@var{target}> [@var{driver_options ...}]
-@end example
-@cindex flash bank
-@*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
-and <@var{bus_width}> bytes using the selected flash <driver>.
+@subsection External Flash
 
-@subsection External Flash - cfi options
-@cindex cfi options
-CFI flashes are external flash chips - often they are connected to a
-specific chip select on the CPU. By default, at hard reset, most
-CPUs have the ablity to ``boot'' from some flash chip - typically
-attached to the CPU's CS0 pin.
-
-For other chip selects: OpenOCD does not know how to configure, or
-access a specific chip select. Instead you, the human, might need to 
-configure additional chip selects via other commands (like: mww) , or
+@deffn {Flash Driver} cfi
+@cindex Common Flash Interface
+@cindex CFI
+The ``Common Flash Interface'' (CFI) is the main standard for
+external NOR flash chips, each of which connects to a
+specific external chip select on the CPU.
+Frequently the first such chip is used to boot the system.
+Your board's @code{reset-init} handler might need to
+configure additional chip selects using other commands (like: @command{mww} to
+configure a bus and its timings) , or
 perhaps configure a GPIO pin that controls the ``write protect'' pin
 on the flash chip.
+The CFI driver can use a target-specific working area to significantly
+speed up operation.
 
-@b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
-<@var{target}> [@var{jedec_probe}|@var{x16_as_x8}]
-@*CFI flashes require the name or number of the target they're connected to
-as an additional
-argument. The CFI driver makes use of a working area (specified for the target)
-to significantly speed up operation. 
+The CFI driver can accept the following optional parameters, in any order:
 
-@var{chip_width} and @var{bus_width} are specified in bytes.
+@itemize
+@item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
+like AM29LV010 and similar types.
+@item @var{x16_as_x8} ...
+@end itemize
 
-The @var{jedec_probe} option is used to detect certain non-CFI flash ROMs, like AM29LV010 and similar types.
+To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
+wide on a sixteen bit bus:
 
-@var{x16_as_x8} ???
+@example
+flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
+flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
+@end example
+@end deffn
 
 @subsection Internal Flash (Microcontrollers)
-@subsubsection lpc2000 options
-@cindex lpc2000 options
 
-@b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
-<@var{clock}> [@var{calc_checksum}]
-@*LPC flashes don't require the chip and bus width to be specified. Additional
-parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
-or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx),
-the name or number of the target this flash belongs to (first is 0),
-the frequency at which the core
-is currently running (in kHz - must be an integral number), and the optional keyword
-@var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
-vector table. 
+@deffn {Flash Driver} aduc702x
+The ADUC702x analog microcontrollers from ST Micro
+include internal flash and use ARM7TDMI cores.
+The aduc702x flash driver works with models ADUC7019 through ADUC7028.
+The setup command only requires the @var{target} argument
+since all devices in this family have the same memory layout.
 
+@example
+flash bank aduc702x 0 0 0 0 $_TARGETNAME
+@end example
+@end deffn
 
-@subsubsection at91sam7 options
-@cindex at91sam7 options
+@deffn {Flash Driver} at91sam7
+All members of the AT91SAM7 microcontroller family from Atmel
+include internal flash and use ARM7TDMI cores.
+The driver automatically recognizes a number of these chips using
+the chip identification register, and autoconfigures itself.
 
-@b{flash bank at91sam7} 0 0 0 0 <@var{target}>
-@*AT91SAM7 flashes only require the @var{target}, all other values are looked up after
-reading the chip-id and type. 
+@example
+flash bank at91sam7 0 0 0 0 $_TARGETNAME
+@end example
 
-@subsubsection str7 options
-@cindex str7 options
+For chips which are not recognized by the controller driver, you must
+provide additional parameters in the following order:
 
-@b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
-@*variant can be either STR71x, STR73x or STR75x. 
+@itemize
+@item @var{chip_model} ... label used with @command{flash info}
+@item @var{banks}
+@item @var{sectors_per_bank}
+@item @var{pages_per_sector}
+@item @var{pages_size}
+@item @var{num_nvm_bits}
+@item @var{freq_khz} ... required if an external clock is provided,
+optional (but recommended) when the oscillator frequency is known
+@end itemize
 
-@subsubsection str9 options
-@cindex str9 options
+It is recommended that you provide zeroes for all of those values
+except the clock frequency, so that everything except that frequency
+will be autoconfigured.
+Knowing the frequency helps ensure correct timings for flash access.
 
-@b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target}>
-@*The str9 needs the flash controller to be configured prior to Flash programming, e.g.
+The flash controller handles erases automatically on a page (128/256 byte)
+basis, so explicit erase commands are not necessary for flash programming.
+However, there is an ``EraseAll`` command that can erase an entire flash
+plane (of up to 256KB), and it will be used automatically when you issue
+@command{flash erase_sector} or @command{flash erase_address} commands.
+
+@deffn Command {at91sam7 gpnvm} bitnum (set|clear)
+Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
+bit for the processor.   Each processor has a number of such bits,
+used for controlling features such as brownout detection (so they
+are not truly general purpose).
+@quotation Note
+This assumes that the first flash bank (number 0) is associated with
+the appropriate at91sam7 target.
+@end quotation
+@end deffn
+@end deffn
+
+@deffn {Flash Driver} lpc2000
+Most members of the LPC2000 microcontroller family from NXP
+include internal flash and use ARM7TDMI cores.
+The @var{lpc2000} driver defines two mandatory and one optional parameters,
+which must appear in the following order:
+
+@itemize
+@item @var{variant} ... required, may be
+@var{lpc2000_v1} (older LPC21xx and LPC22xx)
+or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
+@item @var{clock_kHz} ... the frequency, in kiloHertz,
+at which the core is running
+@item @var{calc_checksum} ... optional (but you probably want to provide this!),
+telling the driver to calculate a valid checksum for the exception vector table.
+@end itemize
+
+LPC flashes don't require the chip and bus width to be specified.
+
 @example
-str9x flash_config 0 4 2 0 0x80000
+flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
+      lpc2000_v2 14765 calc_checksum
 @end example
-This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively. 
+@end deffn
 
-@subsubsection str9 options (str9xpec driver)
+@deffn {Flash Driver} stellaris
+All members of the Stellaris LM3Sxxx microcontroller family from
+Texas Instruments
+include internal flash and use ARM Cortex M3 cores.
+The driver automatically recognizes a number of these chips using
+the chip identification register, and autoconfigures itself.
+@footnote{Currently there is a @command{stellaris mass_erase} command.
+That seems pointless since the same effect can be had using the
+standard @command{flash erase_address} command.}
 
-@b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target}>
-@*Before using the flash commands the turbo mode must be enabled using str9xpec
-@option{enable_turbo} <@var{num>.}
+@example
+flash bank stellaris 0 0 0 0 $_TARGETNAME
+@end example
+@end deffn
 
-Only use this driver for locking/unlocking the device or configuring the option bytes.
-Use the standard str9 driver for programming. @xref{STR9 specific commands}.
+@deffn {Flash Driver} stm32x
+All members of the STM32 microcontroller family from ST Microelectronics
+include internal flash and use ARM Cortex M3 cores.
+The driver automatically recognizes a number of these chips using
+the chip identification register, and autoconfigures itself.
 
-@subsubsection Stellaris (LM3Sxxx) options
-@cindex Stellaris (LM3Sxxx) options
+@example
+flash bank stm32x 0 0 0 0 $_TARGETNAME
+@end example
 
-@b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target}>
-@*Stellaris flash plugin only require the @var{target}.
+Some stm32x-specific commands
+@footnote{Currently there is a @command{stm32x mass_erase} command.
+That seems pointless since the same effect can be had using the
+standard @command{flash erase_address} command.}
+are defined:
 
-@subsubsection stm32x options
-@cindex stm32x options
+@deffn Command {stm32x lock} num
+Locks the entire stm32 device.
+The @var{num} parameter is a value shown by @command{flash banks}.
+@end deffn
 
-@b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target}>
-@*stm32x flash plugin only require the @var{target}.
+@deffn Command {stm32x unlock} num
+Unlocks the entire stm32 device.
+The @var{num} parameter is a value shown by @command{flash banks}.
+@end deffn
 
-@subsubsection aduc702x options
-@cindex aduc702x options
+@deffn Command {stm32x options_read} num
+Read and display the stm32 option bytes written by
+the @command{stm32x options_write} command.
+The @var{num} parameter is a value shown by @command{flash banks}.
+@end deffn
 
-@b{flash bank aduc702x} 0 0 0 0 <@var{target}>
-@*The aduc702x flash plugin works with Analog Devices model numbers ADUC7019 through ADUC7028.  The setup command only requires the @var{target} argument (all devices in this family have the same memory layout).
+@deffn Command {stm32x options_write} num (SWWDG|HWWDG) (RSTSTNDBY|NORSTSTNDBY) (RSTSTOP|NORSTSTOP)
+Writes the stm32 option byte with the specified values.
+The @var{num} parameter is a value shown by @command{flash banks}.
+@end deffn
+@end deffn
 
-@subsection mFlash Configuration
-@cindex mFlash Configuration
-@b{mflash bank} <@var{soc}> <@var{base}> <@var{RST pin}> <@var{target}>
-@cindex mflash bank
-@*Configures a mflash for <@var{soc}> host bank at
-<@var{base}>. Pin number format is dependent on host GPIO calling convention.
-Currently, mflash bank support s3c2440 and pxa270.
+@deffn {Flash Driver} str7x
+All members of the STR7 microcontroller family from ST Microelectronics
+include internal flash and use ARM7TDMI cores.
+The @var{str7x} driver defines one mandatory parameter, @var{variant},
+which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
 
-(ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1.
 @example
-mflash bank s3c2440 0x10000000 1b 0
+flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
 @end example
-(ex. of pxa270) mflash <@var{RST pin}> is GPIO 43.
+@end deffn
+
+@deffn {Flash Driver} str9x
+Most members of the STR9 microcontroller family from ST Microelectronics
+include internal flash and use ARM966E cores.
+The str9 needs the flash controller to be configured using
+the @command{str9x flash_config} command prior to Flash programming.
+
 @example
-mflash bank pxa270 0x08000000 43 0  
+flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
+str9x flash_config 0 4 2 0 0x80000
 @end example
 
-@section Microcontroller specific Flash Commands
+@deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
+Configures the str9 flash controller.
+The @var{num} parameter is a value shown by @command{flash banks}.
 
-@subsection AT91SAM7 specific commands
-@cindex AT91SAM7 specific commands
-The flash configuration is deduced from the chip identification register. The flash
-controller handles erases automatically on a page (128/265 byte) basis, so erase is
-not necessary for flash programming. AT91SAM7 processors with less than 512K flash
-only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
-that can be erased separatly. Only an EraseAll command is supported by the controller
-for each flash plane and this is called with
 @itemize @bullet
-@item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
-@*bulk erase flash planes first_plane to last_plane. 
-@item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
-@cindex at91sam7 gpnvm
-@*set or clear a gpnvm bit for the processor 
+@item @var{bbsr} - Boot Bank Size register
+@item @var{nbbsr} - Non Boot Bank Size register
+@item @var{bbadr} - Boot Bank Start Address register
+@item @var{nbbadr} - Boot Bank Start Address register
 @end itemize
+@end deffn
 
-@subsection STR9 specific commands
-@cindex STR9 specific commands
-@anchor{STR9 specific commands}
-These are flash specific commands when using the str9xpec driver.
-@itemize @bullet
-@item @b{str9xpec enable_turbo} <@var{num}>
-@cindex str9xpec enable_turbo
-@*enable turbo mode, will simply remove the str9 from the chain and talk
-directly to the embedded flash controller. 
-@item @b{str9xpec disable_turbo} <@var{num}>
-@cindex str9xpec disable_turbo
-@*restore the str9 into JTAG chain. 
-@item @b{str9xpec lock} <@var{num}>
-@cindex str9xpec lock
-@*lock str9 device. The str9 will only respond to an unlock command that will
-erase the device. 
-@item @b{str9xpec unlock} <@var{num}>
-@cindex str9xpec unlock
-@*unlock str9 device. 
-@item @b{str9xpec options_read} <@var{num}>
-@cindex str9xpec options_read
-@*read str9 option bytes. 
-@item @b{str9xpec options_write} <@var{num}>
-@cindex str9xpec options_write
-@*write str9 option bytes. 
-@end itemize
+@end deffn
 
-Note: Before using the str9xpec driver here is some background info to help
-you better understand how the drivers works. OpenOCD has two flash drivers for
-the str9.
+@subsection str9xpec driver
+@cindex str9xpec
+
+Here is some background info to help
+you better understand how this driver works. OpenOCD has two flash drivers for
+the str9:
 @enumerate
 @item
 Standard driver @option{str9x} programmed via the str9 core. Normally used for
@@ -2630,25 +2691,45 @@
 has been locked. Halting the core is not required for the @option{str9xpec} driver
 as mentioned above, just issue the commands above manually or from a telnet prompt.
 
-@subsection STR9 configuration
-@cindex STR9 configuration
+@subsubsection str9xpec driver options
+
+@b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target}>
+@*Before using the flash commands the turbo mode must be enabled using str9xpec
+@option{enable_turbo} <@var{num>.}
+
+Only use this driver for locking/unlocking the device or configuring the option bytes.
+Use the standard str9 driver for programming.
+
+@subsubsection str9xpec specific commands
+@cindex str9xpec specific commands
+These are flash specific commands when using the str9xpec driver.
+
 @itemize @bullet
-@item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
-<@var{BBADR}> <@var{NBBADR}>
-@cindex str9x flash_config
-@*Configure str9 flash controller.
-@example
-e.g. str9x flash_config 0 4 2 0 0x80000
-This will setup
-BBSR - Boot Bank Size register
-NBBSR - Non Boot Bank Size register
-BBADR - Boot Bank Start Address register
-NBBADR - Boot Bank Start Address register
-@end example
+@item @b{str9xpec enable_turbo} <@var{num}>
+@cindex str9xpec enable_turbo
+@*enable turbo mode, will simply remove the str9 from the chain and talk
+directly to the embedded flash controller.
+@item @b{str9xpec disable_turbo} <@var{num}>
+@cindex str9xpec disable_turbo
+@*restore the str9 into JTAG chain.
+@item @b{str9xpec lock} <@var{num}>
+@cindex str9xpec lock
+@*lock str9 device. The str9 will only respond to an unlock command that will
+erase the device.
+@item @b{str9xpec unlock} <@var{num}>
+@cindex str9xpec unlock
+@*unlock str9 device.
+@item @b{str9xpec options_read} <@var{num}>
+@cindex str9xpec options_read
+@*read str9 option bytes.
+@item @b{str9xpec options_write} <@var{num}>
+@cindex str9xpec options_write
+@*write str9 option bytes.
 @end itemize
 
-@subsection STR9 option byte configuration
+@subsubsection STR9 option byte configuration
 @cindex STR9 option byte configuration
+
 @itemize @bullet
 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
 @cindex str9xpec options_cmap
@@ -2664,37 +2745,57 @@
 @*configure str9 lvd reset warning source. 
 @end itemize
 
-@subsection STM32x specific commands
-@cindex STM32x specific commands
- 
-These are flash specific commands when using the stm32x driver.
-@itemize @bullet
-@item @b{stm32x lock} <@var{num}>
-@cindex stm32x lock
-@*lock stm32 device. 
-@item @b{stm32x unlock} <@var{num}>
-@cindex stm32x unlock
-@*unlock stm32 device. 
-@item @b{stm32x options_read} <@var{num}>
-@cindex stm32x options_read
-@*read stm32 option bytes. 
-@item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
-<@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
-@cindex stm32x options_write
-@*write stm32 option bytes. 
-@item @b{stm32x mass_erase} <@var{num}>
-@cindex stm32x mass_erase
-@*mass erase flash memory. 
-@end itemize
+@section mFlash
 
-@subsection Stellaris specific commands
-@cindex Stellaris specific commands
- 
-These are flash specific commands when using the Stellaris driver.
+@subsection mFlash Configuration
+@cindex mFlash Configuration
+@b{mflash bank} <@var{soc}> <@var{base}> <@var{RST pin}> <@var{target}>
+@cindex mflash bank
+@*Configures a mflash for <@var{soc}> host bank at
+<@var{base}>. Pin number format is dependent on host GPIO calling convention.
+Currently, mflash bank support s3c2440 and pxa270.
+
+(ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1.
+
+@example
+mflash bank s3c2440 0x10000000 1b 0
+@end example
+
+(ex. of pxa270) mflash <@var{RST pin}> is GPIO 43.
+
+@example
+mflash bank pxa270 0x08000000 43 0
+@end example
+
+@subsection mFlash commands
+@cindex mFlash commands
+
 @itemize @bullet
-@item @b{stellaris mass_erase} <@var{num}>
-@cindex stellaris mass_erase
-@*mass erase flash memory. 
+@item @b{mflash probe}
+@cindex mflash probe
+@*Probe mflash.
+@item @b{mflash write} <@var{num}> <@var{file}> <@var{offset}>
+@cindex mflash write
+@*Write the binary <@var{file}> to mflash bank <@var{num}>, starting at
+<@var{offset}> bytes from the beginning of the bank.
+@item @b{mflash dump} <@var{num}> <@var{file}> <@var{offset}> <@var{size}>
+@cindex mflash dump
+@*Dump <size> bytes, starting at <@var{offset}> bytes from the beginning of the <@var{num}> bank
+to a <@var{file}>.
+@item @b{mflash config pll} <@var{frequency}>
+@cindex mflash config pll
+@*Configure mflash pll. <@var{frequency}> is input frequency of mflash. The order is Hz.
+Issuing this command will erase mflash's whole internal nand and write new pll.
+After this command, mflash needs power-on-reset for normal operation.
+If pll was newly configured, storage and boot(optional) info also need to be update.
+@item @b{mflash config boot}
+@cindex mflash config boot
+@*Configure bootable option. If bootable option is set, mflash offer the first 8 sectors
+(4kB) for boot.
+@item @b{mflash config storage}
+@cindex mflash config storage
+@*Configure storage information. For the normal storage operation, this information must be
+written.
 @end itemize
 
 @node NAND Flash Commands
@@ -2782,7 +2883,7 @@
 configuration files, not interactively.
 
 @itemize @bullet
-@item @var{controller} ... identifies a the controller driver
+@item @var{controller} ... identifies the controller driver
 associated with the NAND device being declared.
 @xref{NAND Driver List}.
 @item @var{target} ... names the target used when issuing
@@ -2849,6 +2950,7 @@
 
 @deffn Command {nand erase} num offset length
 @cindex NAND erasing
+@cindex NAND programming
 Erases blocks on the specified NAND device, starting at the
 specified @var{offset} and continuing for @var{length} bytes.
 Both of those values must be exact multiples of the device's
@@ -2864,6 +2966,7 @@
 
 @deffn Command {nand write} num filename offset [option...]
 @cindex NAND writing
+@cindex NAND programming
 Writes binary data from the file into the specified NAND device,
 starting at the specified offset.  Those pages should already
 have been erased; you can't change zero bits to one bits.
@@ -2963,7 +3066,7 @@
 with the wrong ECC data can cause them to be marked as bad.
 @end deffn
 
-@section NAND Drivers; Driver-specific Options and Commands
+@section NAND Drivers, Options, and Commands
 @anchor{NAND Driver List}
 As noted above, the @command{nand device} command allows
 driver-specific options and behaviors.
@@ -2989,7 +3092,7 @@
 @deffn {NAND Driver} lpc3180
 These controllers require an extra @command{nand device}
 parameter:  the clock rate used by the controller.
-@deffn Command {nand lpc3180 select} num [mlc|slc]
+@deffn Command {lpc3180 select} num [mlc|slc]
 Configures use of the MLC or SLC controller mode.
 MLC implies use of hardware ECC.
 The @var{num} parameter is the value shown by @command{nand list}.
@@ -3014,7 +3117,10 @@
 change any behavior.
 @end deffn
 
-@deffn {NAND Driver} {s3c2410, s3c2412, s3c2440, s3c2443}
+@deffn {NAND Driver} s3c2410
+@deffnx {NAND Driver} s3c2412
+@deffnx {NAND Driver} s3c2440
+@deffnx {NAND Driver} s3c2443
 These S3C24xx family controllers don't have any special
 @command{nand device} options, and don't define any
 specialized commands.
@@ -3273,7 +3379,6 @@
 @cindex Target Specific Commands
 
 
-@page
 @section Architecture Specific Commands
 @cindex Architecture Specific Commands
 
@@ -4503,8 +4608,8 @@
 
 @printindex cp
 
-@node OpenOCD Command Index
-@unnumbered OpenOCD Command Index
+@node Command and Driver Index
+@unnumbered Command and Driver Index
 @printindex fn
 
 @bye

[Openocd-svn] r1936 - trunk/doc

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-28 02:47:30 +0200 (Thu, 28 May 2009)
New Revision: 1936

Modified:
   trunk/doc/openocd.texi
Log:
David Brownell <da...@pa...>:

Fix a bunch of PDF generation bugs in the texi:

 * The "overfull" warnings are basically complaints about lines
   that are too long, so they ran off the right margin of the
   PDF documentation and turn into a "black blot".

 * The "underfull" warnings are basically complaints about lines
   that look ugly when they get filled, because the tokens are
   so long that the line-break algorithm can't do anything good.

In a few cases the simplest fix seemed to be to use more appropriate
texi commands.

In other cases the fix was a content bugfix:  "ocd_" not "openocd_";
and many of those "target variants" actually aren't recognized.


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-05-27 23:54:16 UTC (rev 1935)
+++ trunk/doc/openocd.texi	2009-05-28 00:47:30 UTC (rev 1936)
@@ -261,7 +261,7 @@
 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
-homepage (@uref{http://www.amontec.com}), as the JTAGkey uses a non-standard VID/PID. 
+homepage (@uref{http://www.amontec.com}). The JTAGkey uses a non-standard VID/PID.
 @end itemize
 
 libftdi is supported under Windows. Do not use versions earlier than 0.14.
@@ -320,9 +320,11 @@
 @item
 @option{--enable-ft2232_libftdi} - An open source (free) alternative to FTDICHIP.COM ftd2xx solution (Linux, MacOS, Cygwin).
 @item
-@option{--with-ftd2xx-win32-zipdir=PATH} - If using FTDICHIP.COM ft2232c, point at the directory where the Win32 FTDICHIP.COM 'CDM' driver zip file was unpacked.
+@option{--with-ftd2xx-win32-zipdir=PATH} - If using FTDICHIP.COM ft2232c driver,
+give the directory where the Win32 FTDICHIP.COM 'CDM' driver zip file was unpacked.
 @item
-@option{--with-ftd2xx-linux-tardir=PATH} - Linux only. Equivalent of @option{--with-ftd2xx-win32-zipdir}, where you unpacked the TAR.GZ file.
+@option{--with-ftd2xx-linux-tardir=PATH} - If using FTDICHIP.COM ft2232c driver
+on Linux, give the directory where the Linux driver's TAR.GZ file was unpacked.
 @item
 @option{--with-ftd2xx-lib=shared|static} - Linux only. Default: static. Specifies how the FTDICHIP.COM libftd2xx driver should be linked. Note: 'static' only works in conjunction with @option{--with-ftd2xx-linux-tardir}. The 'shared' value is supported (12/26/2008), however you must manually install the required header files and shared libraries in an appropriate place. This uses ``libusb'' internally.
 @item
@@ -369,43 +371,54 @@
 
 Below is an example build process:
 
-1) Check out the latest version of ``openocd'' from SVN.
+@enumerate
+@item Check out the latest version of ``openocd'' from SVN.
 
-2) Download & unpack either the Windows or Linux FTD2xx drivers
-    (@uref{http://www.ftdichip.com/Drivers/D2XX.htm}).
+@item If you are using the FTDICHIP.COM driver, download
+and unpack the Windows or Linux FTD2xx drivers
+(@uref{http://www.ftdichip.com/Drivers/D2XX.htm}).
+If you are using the libftdi driver, install that package
+(e.g. @command{apt-get install libftdi} on systems with APT).
 
 @example
-   /home/duane/ftd2xx.win32    => the Cygwin/Win32 ZIP file contents.
-   /home/duane/libftd2xx0.4.16 => the Linux TAR.GZ file contents.
+/home/duane/ftd2xx.win32    => the Cygwin/Win32 ZIP file contents
+/home/duane/libftd2xx0.4.16 => the Linux TAR.GZ file contents
 @end example
 
-3) Configure with these options:
+@item Configure with options resembling the following.
 
+@enumerate a
+@item Cygwin FTDICHIP solution:
 @example
-Cygwin FTDICHIP solution:
-   ./configure --prefix=/home/duane/mytools \
-               --enable-ft2232_ftd2xx \
-               --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
+./configure --prefix=/home/duane/mytools \
+        --enable-ft2232_ftd2xx \
+        --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
+@end example
 
-Linux FTDICHIP solution:
-   ./configure --prefix=/home/duane/mytools \
-               --enable-ft2232_ftd2xx \
-               --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
+@item Linux FTDICHIP solution:
+@example
+./configure --prefix=/home/duane/mytools \
+        --enable-ft2232_ftd2xx \
+        --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
+@end example
 
-Cygwin/Linux LIBFTDI solution:
-    Assumes: 
-    1a) For Windows: The Windows port of LIBUSB is in place.
-    1b) For Linux: libusb has been built/installed and is in place.
+@item Cygwin/Linux LIBFTDI solution ... assuming that
+@itemize
+@item For Windows -- that the Windows port of LIBUSB is in place.
+@item For Linux -- that libusb has been built/installed and is in place.
+@item That libftdi has been built and installed (relies on libusb).
+@end itemize
 
-    2) And libftdi has been built and installed
-    Note: libftdi - relies upon libusb.
+Then configure the libftdi solution like this:
 
-    ./configure --prefix=/home/duane/mytools \
-                --enable-ft2232_libftdi
-       
+@example
+./configure --prefix=/home/duane/mytools \
+        --enable-ft2232_libftdi
 @end example
+@end enumerate
 
-4) Then just type ``make'', and perhaps ``make install''.
+@item Then just type ``make'', and perhaps ``make install''.
+@end enumerate
 
 
 @section Miscellaneous Configure Options
@@ -467,10 +480,11 @@
 
 There are many USB JTAG dongles on the market, many of them are based
 on a chip from ``Future Technology Devices International'' (FTDI)
-known as the FTDI FT2232.
+known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
+See: @url{http://www.ftdichip.com} for more information.
+In summer 2009, USB high speed (480 Mbps) versions of these FTDI
+chips are starting to become available in JTAG adapters.
 
-See: @url{http://www.ftdichip.com} or @url{http://www.ftdichip.com/Products/FT2232H.htm}
-
 As of 28/Nov/2008, the following are supported:
 
 @itemize @bullet
@@ -489,7 +503,9 @@
 @item @b{flyswatter}
 @* See: @url{http://www.tincantools.com}
 @item @b{turtelizer2}
-@* See: @url{http://www.ethernut.de}, or @url{http://www.ethernut.de/en/hardware/turtelizer/index.html}
+@* See:
+@uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
+@url{http://www.ethernut.de}
 @item @b{comstick}
 @* Link: @url{http://www.hitex.com/index.php?id=383}
 @item @b{stm32stick}
@@ -563,7 +579,8 @@
 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
 
 @item @b{Wiggler2}
-@* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
+@*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
+Improved parallel-port wiggler-style JTAG adapter}
 
 @item @b{Wiggler_ntrst_inverted}
 @* Yet another variation - See the source code, src/jtag/parport.c
@@ -581,12 +598,13 @@
 @* Unknown.
 
 @item @b{Lattice}
-@* ispDownload from Lattice Semiconductor @url{http://www.latticesemi.com/lit/docs/devtools/dlcable.pdf}
+@* ispDownload from Lattice Semiconductor
+@url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
 
 @item @b{flashlink}
-@* From ST Microsystems, link:
-@url{http://www.st.com/stonline/products/literature/um/7889.pdf}
-Title: FlashLINK JTAG programing cable for PSD and uPSD
+@* From ST Microsystems;
+@uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
+FlashLINK JTAG programing cable for PSD and uPSD}
 
 @end itemize
 
@@ -717,7 +735,7 @@
 OpenOCD will read each filename in sequence, for example:
 
 @example
-        openocd -f file1.cfg -f file2.cfg -f file2.cfg
+openocd -f file1.cfg -f file2.cfg -f file2.cfg
 @end example
 
 You can also intermix various commands with the ``-c'' command line
@@ -806,11 +824,6 @@
 today, that said, perhaps some interfaces have only been used by the
 sole developer who created it.
 
-@b{FIXME/NOTE:} We need to add support for a variable like Tcl variable
-tcl_platform(platform), it should be called jim_platform (because it
-is jim, not real tcl) and it should contain 1 of 3 words: ``linux'',
-``cygwin'' or ``mingw''
-
 Interface files should be found in @t{$(INSTALLDIR)/lib/openocd/interface}
 
 @section Board Config Files
@@ -881,8 +894,10 @@
 problems in OpenOCD configurations.
 
 @example
-Info:   JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
-Error:  ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
+Info:   JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
+                (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
+Error:  ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678,
+                Got: 0x3f0f0f0f
 Error:  ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
 Error:  ERROR:      got: mfg: 0x787, part: 0xf0f0, ver: 0x3
 @end example
@@ -989,7 +1004,8 @@
 @example
 # for an ARM7TDMI.
 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
+        -expected-id $_CPUTAPID
 @end example
 
 @b{COMPLEX example:}
@@ -1007,14 +1023,16 @@
 @} else @{
    set _FLASHTAPID 0x25966041
 @}
-jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 \
+        -expected-id $_FLASHTAPID
 
 if @{ [info exists CPUTAPID ] @} @{
    set _CPUTAPID $CPUTAPID
 @} else @{
    set _CPUTAPID 0x25966041
 @}
-jtag newtap $_CHIPNAME cpu   -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe \
+        -expected-id $_CPUTAPID
 
 
 if @{ [info exists BSTAPID ] @} @{
@@ -1022,7 +1040,8 @@
 @} else @{
    set _BSTAPID 0x1457f041
 @}
-jtag newtap $_CHIPNAME bs    -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 \
+        -expected-id $_BSTAPID
 
 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
 @end example
@@ -1145,7 +1164,6 @@
 @* See: @xref{Tcl Crash Course}.
 @end itemize
 
-
 @node Daemon Configuration
 @chapter Daemon Configuration
 @cindex initialization
@@ -2087,7 +2105,10 @@
        reset halt
    @}
    mychip.cpu configure -event gdb-attach my_attach_proc 
-   mychip.cpu configure -event gdb-attach @{ puts "Reset..." ; reset halt @}
+   mychip.cpu configure -event gdb-attach @{
+	   puts "Reset..."
+	   reset halt
+   @}
 @end example
 
 @section Current Events
@@ -2256,27 +2277,16 @@
 
 @section Target Variants
 @itemize @bullet
-@item @b{arm7tdmi}
-@* Unknown (please write me)
-@item @b{arm720t}
-@* Unknown (please write me) (similar to arm7tdmi)
-@item @b{arm9tdmi}
-@* Variants: @option{arm920t}, @option{arm922t} and @option{arm940t}
-This enables the hardware single-stepping support found on these
-cores.
-@item @b{arm920t}
-@* None.
-@item @b{arm966e}
-@* None (this is also used as the ARM946)
 @item @b{cortex_m3}
-@* use variant <@var{-variant lm3s}> when debugging Luminary lm3s targets. This will cause
-OpenOCD to use a software reset rather than asserting SRST to avoid a issue with clearing
-the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
+@* Use variant @option{lm3s} when debugging older Stellaris LM3S targets.
+This will cause OpenOCD to use a software reset rather than asserting
+SRST, to avoid a issue with clearing the debug registers.
+This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
 be detected and the normal reset behaviour used.
 @item @b{xscale}
-@* Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},@option{pxa250}, @option{pxa255}, @option{pxa26x}.
-@item @b{arm11}
-@* Supported variants are @option{arm1136}, @option{arm1156}, @option{arm1176}
+@*Supported variants are
+@option{ixp42x}, @option{ixp45x}, @option{ixp46x},
+@option{pxa250}, @option{pxa255}, @option{pxa26x}.
 @item @b{mips_m4k}
 @* Use variant @option{ejtag_srst} when debugging targets that do not
 provide a functional SRST line on the EJTAG connector.  This causes
@@ -3536,8 +3546,13 @@
 
 The way this works on the ZY1000 is to prefix a filename by
 "/tftp/ip/" and append the TFTP path on the TFTP
-server (tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf" will
-load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
+server (tftpd). For example,
+
+@example
+load_image /tftp/10.0.0.96/c:\temp\abc.elf
+@end example
+
+will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
 if the file was hosted on the embedded host.
 
 In order to achieve decent performance, you must choose a TFTP server
@@ -3567,7 +3582,8 @@
 To start OpenOCD with a target script for the AT91R40008 CPU and reset
 the CPU upon startup of the OpenOCD daemon.
 @example
-openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset 
+openocd -f interface/parport.cfg -f target/at91r40008.cfg \
+        -c "init" -c "reset"
 @end example
 
 
@@ -3585,7 +3601,8 @@
 errors, which has since been fixed: look up 1836 in
 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
 
-@*OpenOCD can communicate with GDB in two ways:
+OpenOCD can communicate with GDB in two ways:
+
 @enumerate
 @item
 A socket (TCP/IP) connection is typically started as follows:
@@ -3603,7 +3620,7 @@
 session.
 @end enumerate
 
-@*To see a list of available OpenOCD commands type @option{monitor help} on the
+To list the available OpenOCD commands type @command{monitor help} on the
 GDB command line.
 
 OpenOCD supports the gdb @option{qSupported} packet, this enables information
@@ -3707,8 +3724,9 @@
 
 By low-level, the intent is a human would not directly use these commands.
 
-Low-level commands are (should be) prefixed with "openocd_", e.g. openocd_flash_banks
-is the low level API upon which "flash banks" is implemented.
+Low-level commands are (should be) prefixed with "ocd_", e.g.
+@command{ocd_flash_banks}
+is the low level API upon which @command{flash banks} is implemented.
 
 @itemize @bullet
 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
@@ -3745,6 +3763,13 @@
 
 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
 
+@quotation Note
+We should add support for a variable like Tcl variable
+@code{tcl_platform(platform)}, it should be called
+@code{jim_platform} (because it
+is jim, not real tcl).
+@end quotation
+
 @node Upgrading
 @chapter Deprecated/Removed Commands
 @cindex Deprecated/Removed Commands
@@ -3753,7 +3778,8 @@
 @itemize @bullet
 @item @b{arm7_9 fast_writes}
 @cindex arm7_9 fast_writes
-@*use @option{arm7_9 fast_memory_access} command with same args. @xref{arm7_9 fast_memory_access}.
+@*Use @command{arm7_9 fast_memory_access} instead.
+@xref{arm7_9 fast_memory_access}.
 @item @b{arm7_9 force_hw_bkpts}
 @cindex arm7_9 force_hw_bkpts
 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
@@ -4451,7 +4477,8 @@
 is set to 10kHz for reset and 8MHz for post reset.
 
 @example
-openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
+openocd -f interface/parport.cfg -f target/str710.cfg \
+        -c "init" -c "reset"
 @end example
 
 To list the target scripts available:

[Openocd-svn] r1935 - trunk/src/flash

[<zw...@ma...>]

Author: zwelch
Date: 2009-05-28 01:54:16 +0200 (Thu, 28 May 2009)
New Revision: 1935

Modified:
   trunk/src/flash/mflash.c
Log:
Fix potentialyl unaligned memory accesses in mflash driver.

Modified: trunk/src/flash/mflash.c
===================================================================
--- trunk/src/flash/mflash.c	2009-05-27 21:03:51 UTC (rev 1934)
+++ trunk/src/flash/mflash.c	2009-05-27 23:54:16 UTC (rev 1935)
@@ -1126,8 +1126,9 @@
 	u8 buff[512];
 
 	memset(buff, 0xff, 512);
-	*((u32 *)&buff[0]) = pll->lock_cyc;	/* PLL Lock cycle */
-	*((u16 *)&buff[4]) = pll->feedback_div;	/* PLL Feedback 9bit Divider */
+	/* PLL Lock cycle and Feedback 9bit Divider */
+	memcpy(buff, &pll->lock_cyc, sizeof(u32));
+	memcpy(buff + 4, &pll->feedback_div, sizeof(u16));
 	buff[6] = pll->input_div;		/* PLL Input 5bit Divider */
 	buff[7] = pll->output_div;		/* PLL Output Divider */
 

[Openocd-svn] r1934 - trunk/src/target

[kc8apf at B. <kc...@ma...>]

Author: kc8apf
Date: 2009-05-27 23:03:51 +0200 (Wed, 27 May 2009)
New Revision: 1934

Modified:
   trunk/src/target/embeddedice.c
Log:
Author: Nicolas Pitre <ni...@ca...>
	- cut out the "unknown EmbeddedICE version" message with Feroceon


Modified: trunk/src/target/embeddedice.c
===================================================================
--- trunk/src/target/embeddedice.c	2009-05-27 20:30:17 UTC (rev 1933)
+++ trunk/src/target/embeddedice.c	2009-05-27 21:03:51 UTC (rev 1934)
@@ -179,6 +179,13 @@
 			arm7_9->has_monitor_mode = 1;
 			break;
 		default:
+			/*
+			 * The Feroceon implementation has the version number
+			 * in some unusual bits.  Let feroceon.c validate it
+			 * and do the appropriate setup itself.
+			 */
+			if (strcmp(target->type->name, "feroceon") == 0)
+				break;
 			LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 	}